diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.qpf b/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.qpf new file mode 100644 index 00000000..6d91ff79 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "ComputerSpace" diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.qsf b/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.qsf new file mode 100644 index 00000000..00455d64 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.qsf @@ -0,0 +1,171 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 17:39:19 November 07, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ComputerSpace_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/v74161_16bit.vhd +set_global_assignment -name VHDL_FILE rtl/v74161.vhd +set_global_assignment -name VHDL_FILE rtl/sync_star_board.vhd +set_global_assignment -name VHDL_FILE rtl/sound.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/scan_counter.vhd +set_global_assignment -name QIP_FILE rtl/saucer_shooting.qip +set_global_assignment -name VHDL_FILE rtl/saucer_diode_image.vhd +set_global_assignment -name QIP_FILE rtl/rocket_thrust.qip +set_global_assignment -name QIP_FILE rtl/rocket_shooting.qip +set_global_assignment -name QIP_FILE rtl/rocket_rotate.qip +set_global_assignment -name VHDL_FILE rtl/rocket_diode_images.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VHDL_FILE rtl/motion_board.vhd +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VHDL_FILE rtl/memory_board.vhd +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name QIP_FILE rtl/explosion.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/CSpace.sv +set_global_assignment -name VHDL_FILE rtl/computer_space_top.vhd +set_global_assignment -name VHDL_FILE rtl/computer_space_logic.vhd +set_global_assignment -name VHDL_FILE rtl/clocks.vhd +set_global_assignment -name QIP_FILE rtl/bakam.qip +set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY CSpace +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------- +# start ENTITY(CSpace) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(CSpace) +# ------------------ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.srf b/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/ComputerSpace.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/README.txt b/Arcade/Custom Hardware/ComputerSpace_MiST/README.txt new file mode 100644 index 00000000..1980e38f --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Computer Space - World first commercial arcade! +-- Port to MiST by Gehstock +-- 07 November 2017 +-- +--------------------------------------------------------------------------------- +-- +-- Computer Space by Mattias G (2015) +-- +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- F1 : Start +-- SPACE : Thrust +-- RIGHT/LEFT : Turn +-- CTRL : Fire +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/Release/ComputerSpace.rbf b/Arcade/Custom Hardware/ComputerSpace_MiST/Release/ComputerSpace.rbf new file mode 100644 index 00000000..0b8ef50c Binary files /dev/null and b/Arcade/Custom Hardware/ComputerSpace_MiST/Release/ComputerSpace.rbf differ diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/clean.bat b/Arcade/Custom Hardware/ComputerSpace_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/CSpace.sv b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/CSpace.sv new file mode 100644 index 00000000..31ec630f --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/CSpace.sv @@ -0,0 +1,154 @@ +module CSpace +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "C. Space;;", + "T2,START;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_5m; +wire clk_50m; +wire vclk; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(reset), + .c0(clk_5m), + .c1(clk_50m), + .locked(pll_locked) +); + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [15:0] audio; +wire video, blank; +wire reset = buttons[1] | status[0] | status[6]; +wire hsync,vsync; +assign LED = 1; + + +wire [3:0] G = blank ? 4'b0 : {4{video}}; +wire [3:0] R = blank ? 4'b0 : {4{video}}; +wire [3:0] B = blank ? 4'b0 : {4{video}}; + +video_mixer #(.LINE_LENGTH(350), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_50m), + .ce_pix(clk_5m), + .ce_pix_actual(clk_5m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(R), + .G(G), + .B(B), + .HSync(hsync), + .VSync(vsync), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(1) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_50m ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +computer_space_top computerspace +( + .reset(reset), + .clock_50(clk_50m), + .game_clk(clk_5m), + .signal_ccw(kbjoy[6] | joystick_0[1] | joystick_1[1]),//left + .signal_cw(kbjoy[7] | joystick_0[0] | joystick_1[0]),//right + .signal_thrust(kbjoy[4] | joystick_0[3] | joystick_1[3]),//thrust + .signal_fire(kbjoy[0] | joystick_0[4] | joystick_1[4]),//fire + .signal_start(kbjoy[3] | kbjoy[1] | kbjoy[1] | status[2]),//start + .hsync(hsync), + .vsync(vsync), + .blank(blank), + .video(video), + .wav_out(audio) +); + + +sigma_delta_dac dacr( + .CLK(clk_50m), + .RESET(reset), + .DACin(audio), + .DACout(AUDIO_R) + ); + +sigma_delta_dac dacl( + .CLK(clk_50m), + .RESET(reset), + .DACin(audio), + .DACout(AUDIO_L) + ); + +keyboard keyboard( + .clk(clk_50m), + .reset(reset), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/bakam.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/bakam.qip new file mode 100644 index 00000000..a47cb9aa --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/bakam.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "bakam.vhd"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/bakam.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/bakam.vhd new file mode 100644 index 00000000..e5574cb0 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/bakam.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: bakam.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY bakam IS + PORT + ( + address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END bakam; + + +ARCHITECTURE SYN OF bakam IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "bakamb_8_11.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 16384, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + widthad_a => 14, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "bakamb_8_11.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "bakamb_8_11.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 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+:13362000FFFEFEFDFDFCFCFCFCFCFCFCFCFDFDFEFEFEFFCF +:00000001FF diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/build_id.tcl b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/build_id.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/build_id.v new file mode 100644 index 00000000..2e0b64db --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "055618" diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/clocks.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/clocks.vhd new file mode 100644 index 00000000..3d3faba8 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/clocks.vhd @@ -0,0 +1,196 @@ +----------------------------------------------------------------------------- +-- CLOCKS -- +-- For use with Computer Space FPGA emulator. -- +-- Generates the clocks required to run the CS game, -- +-- to emulate analogue timers and pulse trains, -- +-- and to run implementation specifics such as: -- +-- sigma-delta audio and interlaced composite video. -- +-- -- +-- In the real game; capacitors, NOT gates and schmitt trigger ICs -- +-- create timers and "pulse trains" that are used for: -- +-- thrust impact(acceleration/deceleration), engine flame motion, -- +-- rotation speed, duration of explosion, rotation speed during explosion, -- +-- duration of missiles, and seconds counters for game time. -- +-- -- +-- The FPGA emulation "replaces" the analogue parts with digital -- +-- clocks and counters. -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +USE ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; + +--80--------------------------------------------------------------------------| + +entity clocks is + port( + clock_50 : in std_logic; + + thrust_and_rotate_clk : out std_logic:='0'; + + explosion_clk, explosion_rotate_clk : out std_logic; + + timer_base_clk : out std_logic; + rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : out integer; + + seconds_clk : out std_logic + ); + +end clocks; + +architecture clocks_architecture + of clocks is + +-- signals to generate clock +-- that controls: +-- rocket flame motion freq, +-- acceleration/deceleration and +-- rocket rotation speed +signal thrust_and_rotate_clk_count : integer:=0; +signal thrust_and_rotate_clk_buffer : std_logic:='0'; + +-- signals for explosion +-- circuitry logic +signal explosion_clk_count : integer:=0; +signal explosion_clk_buffer : std_logic:='0'; + +-- signals to generate clock used for +-- rotating the rocket rapdily +-- during explosion +signal explosion_rotate_clk_count : integer:=0; +signal explosion_rotate_clk_buffer : std_logic:='0'; + +-- signals used for generating +-- seconds clock (game time) +signal seconds_clk_count : integer :=0; +signal seconds_clk_buffer : std_logic:='0'; + +-----------------------------------------------------------------------------// +begin + +----------------------------------------------------------------------------- +-- creating clock for thrust, rocket engine flame and rotation -- +-- (based on the 50MHz clock ) -- +-- count of 2777778 @ 50 MhZ=> 18 Hz -- +-- measured to 18.2 Hz at real Memory Board -- +----------------------------------------------------------------------------- +process (clock_50) +begin +if clock_50'event and clock_50='1' then + if thrust_and_rotate_clk_count = 2777778 then + thrust_and_rotate_clk_count <= 0; + thrust_and_rotate_clk_buffer <= not (thrust_and_rotate_clk_buffer); + else + thrust_and_rotate_clk_count <= thrust_and_rotate_clk_count+1; + end if; +end if; +end process; + +-- buffer required +thrust_and_rotate_clk <= thrust_and_rotate_clk_buffer; + +----------------------------------------------------------------------------- +-- creating clock for explosion circuitry; -- +-- (based on the 50MHz clock ) -- +-- use count of 4166667 @ 50 MhZ => 6 Hz -- +-- measured to 6.13 - 6.19 Hz at real Sync Star Board -- +----------------------------------------------------------------------------- +process (clock_50) +begin +if clock_50'event and clock_50='1' then + if explosion_clk_count = 4166667 then + explosion_clk_count <= 0; + explosion_clk_buffer <= not (explosion_clk_buffer); + else + explosion_clk_count <= explosion_clk_count+1; + end if; +end if; +end process; + +-- buffer required +explosion_clk <= explosion_clk_buffer; + +----------------------------------------------------------------------------- +-- creating clock to rotate the ship at explosion; -- +-- (based on the 50MHz clock) -- +-- 147 @ 50 Mhz gives the fundamental explosion clock: 340KHz -- +-- as measured on real Memory Board -- +----------------------------------------------------------------------------- +process (clock_50) +begin +if clock_50'event and clock_50='1' then + if explosion_rotate_clk_count = 147 then + explosion_rotate_clk_count <= 0; + explosion_rotate_clk_buffer <= not (explosion_rotate_clk_buffer); + else + explosion_rotate_clk_count <= explosion_rotate_clk_count+1; + end if; +end if; +end process; + +-- buffer required +explosion_rotate_clk <= explosion_rotate_clk_buffer; + +----------------------------------------------------------------------------- +-- creating clock second pulses from the 50 Mhz clock -- +-- 25.000.000 gives second long clock pulse with 50MHz clock => 1Hz -- +----------------------------------------------------------------------------- +process (clock_50) +begin +if clock_50'event and clock_50='1' then + if seconds_clk_count = 25000000 then + seconds_clk_count <= 0; + seconds_clk_buffer <= not (seconds_clk_buffer); + else + seconds_clk_count <= seconds_clk_count+1; + end if; +end if; +end process; + +-- buffer required +seconds_clk <= seconds_clk_buffer; + +----------------------------------------------------------------------------- +-- Creating clock and timer duration used by Motion Board: -- +-- > rocket missile life time -- +-- > saucer missile life time and duration between missile launches -- +-- > signal delay emulation -- +-- Replaces the disrete/analogue timer solutions on the board -- +-- Values set to closely match values measured on real CS boards -- +----------------------------------------------------------------------------- +timer_base_clk <= clock_50; + +rocket_missile_life_time_duration <= 115000000; -- 2,3s +-- calculate rocket_missile_life_time_duration as: +-- rocket_missile_life_time_duration / timer_base_clk = 2,3s +-- reaching a life time of 2.3 seconds +-- as measured on real CS board set + +saucer_missile_life_time_duration <= 115000000; -- 2,3 s +-- calculate saucer_missile_life_time_duration as: +-- saucer_missile_life_time_duration / timer_base_clk = 2.3s +-- reaching a life time of 2.3 seconds +-- as measured on real CS board set + +saucer_missile_hold_duration <= 10000000; -- 0.2s +-- calculate saucer_missile_hold_duration as: +-- saucer_missile_hold_duration / timer_base_clk = 0,2s +-- reaching a hold time of 0.2 seconds +-- as measured on real CS board set + +signal_delay_duration <= 150000; -- 0,003s (should actually be only 3us) +-- calculate signal_delay_duration as: +-- signal_delay_duration / timer_base_clk = 0,003s +-- reaching a signal delay time of 0.003 seconds +-- measured to 3us on real CS board set + +end clocks_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/computer_space_logic.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/computer_space_logic.vhd new file mode 100644 index 00000000..ef4ccfec --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/computer_space_logic.vhd @@ -0,0 +1,349 @@ +----------------------------------------------------------------------------- +-- COMPUTER SPACE LOGIC -- +-- Implementation of Computer Space FPGA emulator. -- +-- Module that embodies the three CS boards -- +-- and manages the interfaces between those boards -- +-- as well as the interface with the implementation specifics and key -- +-- clocks/timers -- +-- -- +-- This entity is implementation agnostic -- +-- -- +-- Naming convention: -- +-- Sync Star Board inputs/outputs are labelled SB_, where is -- +-- according to original schematics input/output labels. -- +-- Motion Board inputs/outputs are labelled MB_, where is -- +-- according to original schematics input/output labels. -- +-- Memory Board inputs/outputs are labelled MemBrd_, where is -- +-- according to original schematics input/output labels. -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; + +--80--------------------------------------------------------------------------| + +entity computer_space_logic is + port + ( + reset, + + -- clocks and timers + game_clk, super_clk, explosion_clk, + seconds_clk, timer_base_clk : in std_logic; + + rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : in integer; + + -- for use with memory board + thrust_and_rotate_clk, + explosion_rotate_clk : in std_logic; + + -- control panel signals incl coin + signal_start, signal_coin, + signal_thrust, signal_fire, + signal_cw, signal_ccw : in std_logic; + + -- composite video + -- signals; to send via gpio + -- to TV (via resistor circuitry) + composite_video_signal : out std_logic; + blank : out std_logic; + + hsync : out std_logic; + vsync : out std_logic; + + -- signals for sound + audio_gate : out std_logic; + sound_switch : out std_logic_vector (7 downto 0) + := "00000000" + ); + +end computer_space_logic; + +architecture +computer_space_logic_architecture +of computer_space_logic is + +component sync_star_board + port ( + reset, + game_clk : in std_logic; + super_clk, + explosion_clk, seconds_clk : in std_logic; + + SB_3, SB_4, SB_6, SB_7, + SB_C, SB_E, SB_N : in std_logic; + + SB_2, SB_5, SB_H, SB_K, + SB_L, SB_M, SB_Y : out std_logic; + + hsync : out std_logic; + vsync : out std_logic; + composite_video_signal : out std_logic; + blank : out std_logic + ); +end component; + +component motion_board + port ( + super_clk, timer_base_clk : in std_logic; + rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : in integer; + + MB_3, MB_4, MB_16, MB_17, + MB_18, MB_19, MB_20, + MB_C, MB_D, MB_H, MB_J, + MB_T, MB_U, MB_V, MB_Y : in std_logic; + + MB_5, MB_6, MB_8, MB_9, + MB_10, MB_11, MB_12, + MB_13, MB_14, MB_15,MB_21, + MB_B, MB_E, MB_F, + MB_K, MB_L, MB_N, MB_M, + MB_P, MB_R, MB_W, + MB_2_rocket, MB_2_saucer : out std_logic + ); +end component; + +component memory_board + port ( + super_clk, thrust_and_rotate_clk, + explosion_rotate_clk : in std_logic := '1'; + + MemBrd_2, MemBrd_3, MemBrd_4, + MemBrd_5, MemBrd_6, MemBrd_7, + MemBrd_8, MemBrd_9, MemBrd_10, + MemBrd_11, MemBrd_A, MemBrd_B, + MemBrd_C, MemBrd_D, MemBrd_E, + MemBrd_F, MemBrd_H, MemBrd_J, + MemBrd_K, MemBrd_M, MemBrd_N, + MemBrd_R, MemBrd_S : in std_logic; + + MemBrd_12, MemBrd_13, MemBrd_14, + MemBrd_15, MemBrd_16, MemBrd_17, + MemBrd_K1, MemBrd_K2, MemBrd_P, + MemBrd_T, MemBrd_U, MemBrd_V, + MemBrd_W, MemBrd_X, MemBrd_Y : out std_logic + ); +end component; + +-- signals for interfacing +-- with sync star board +signal SB_3, SB_4, SB_6, + SB_C, SB_E, SB_N : std_logic; +signal SB_2, SB_5, SB_7, + SB_H, SB_K, SB_L, SB_M, SB_Y : std_logic; + +-- signals for interfacing with +-- memory board +signal MemBrd_A, MemBrd_B, MemBrd_C, + MemBrd_D, MemBrd_2, MemBrd_3, + MemBrd_4, MemBrd_5,MemBrd_E, + MemBrd_F, MemBrd_J, MemBrd_H, + MemBrd_6, MemBrd_7, MemBrd_8, + MemBrd_9 : std_logic; +signal MemBrd_13, MemBrd_14, MemBrd_15, + MemBrd_16 : std_logic; +signal MemBrd_W, MemBrd_V, MemBrd_X, + MemBrd_Y, MemBrd_S : std_logic; +signal MemBrd_17, MemBrd_T, MemBrd_U, + MemBrd_12, MemBrd_11 : std_logic; +signal MemBrd_10, MemBrd_22, MemBrd_R, + MemBrd_K, MemBrd_P, MemBrd_M, + MemBrd_N : std_logic; +signal MemBrd_K1, MemBrd_K2 : std_logic := '0'; + +-- signals for interfacing +-- with motion board +signal MB_V, MB_U, MB_T, MB_4, MB_D, + MB_3, MB_H, MB_J, MB_B, MB_C : std_logic; +signal MB_19, MB_18, MB_16, MB_17, MB_20 : std_logic; + +signal MB_E, MB_5, MB_F, MB_6, MB_L, + MB_9, MB_K, MB_8, MB_21, MB_M, + MB_11, MB_N, MB_12, MB_14, MB_R, + MB_13, MB_15, MB_P, MB_W, MB_10, + MB_Y : std_logic; +signal MB_2_rocket, MB_2_saucer : std_logic; + +-----------------------------------------------------------------------------// +begin + +----------------------------------------------------------------------------- +-- SYNC STAR BOARD -- +----------------------------------------------------------------------------- +Sync_Star_Brd : sync_star_board +port map (reset, game_clk, super_clk, explosion_clk, seconds_clk, +SB_3, SB_4, SB_6, SB_7, SB_C, SB_E, SB_N, +SB_2, SB_5, SB_H, SB_K, SB_L, SB_M, SB_Y, hsync, vsync, +composite_video_signal, blank); + +----------------------------------------------------------------------------- +-- MOTION BOARD -- +----------------------------------------------------------------------------- +Motion_Brd: motion_board +port map (super_clk, timer_base_clk, rocket_missile_life_time_duration, +saucer_missile_life_time_duration, saucer_missile_hold_duration, +signal_delay_duration, MB_3, MB_4, MB_16, MB_17, MB_18, MB_19, MB_20, MB_C, +MB_D, MB_H, MB_J, MB_T, MB_U, MB_V, MB_Y, MB_5, MB_6, MB_8, MB_9, MB_10, +MB_11, MB_12, MB_13, MB_14, MB_15,MB_21, MB_B, MB_E, MB_F, MB_K, MB_L, MB_N, +MB_M, MB_P, MB_R, MB_W, MB_2_rocket, MB_2_saucer); + +----------------------------------------------------------------------------- +-- MEMORY BOARD -- +----------------------------------------------------------------------------- +Memory_Brd: memory_board +port map(super_clk, thrust_and_rotate_clk, explosion_rotate_clk, MemBrd_2, +MemBrd_3, MemBrd_4, MemBrd_5, MemBrd_6, MemBrd_7, MemBrd_8, MemBrd_9, +MemBrd_10, MemBrd_11, MemBrd_A, MemBrd_B, MemBrd_C, MemBrd_D, MemBrd_E, +MemBrd_F, MemBrd_H, MemBrd_J, MemBrd_K, MemBrd_M, MemBrd_N, MemBrd_R, +MemBrd_S, MemBrd_12, MemBrd_13, MemBrd_14, MemBrd_15, MemBrd_16, MemBrd_17, +MemBrd_K1, MemBrd_K2, MemBrd_P, MemBrd_T, MemBrd_U, MemBrd_V, MemBrd_W, +MemBrd_X, MemBrd_Y); + +----------------------------------------------------------------------------- +-- COMPUTER SPACE BOARD INTRA CONNECTION MAPPING -- +-- from Motion Board to Memory Board -- +----------------------------------------------------------------------------- +MemBrd_A <= MB_8; -- SAUCER VERTICAL BIT 3 +MemBrd_2 <= MB_K; -- SAUCER VERTICAL BIT 2 +MemBrd_E <= MB_9; -- SAUCER VERTICAL BIT 1 +MemBrd_6 <= MB_L; -- SAUCER VERTICAL BIT 0 + +MemBrd_B <= MB_6; -- SAUCER HORIZONTAL BIT 3 +MemBrd_3 <= MB_F; -- SAUCER HORIZONTAL BIT 2 +MemBrd_F <= MB_5; -- SAUCER HORIZONTAL BIT 1 +MemBrd_7 <= MB_E; -- SAUCER HORIZONTAL BIT 0 + +MemBrd_C <= MB_12; -- ROCKET HORIZONTAL BIT 3 +MemBrd_4 <= MB_N; -- ROCKET HORIZONTAL BIT 2 +MemBrd_H <= MB_11; -- ROCKET HORIZONTAL BIT 1 +MemBrd_8 <= MB_M; -- ROCKET HORIZONTAL BIT 0 + +MemBrd_D <= MB_15; -- ROCKET VERTICAL BIT 3 +MemBrd_5 <= MB_13; -- ROCKET VERTICAL BIT 2 +MemBrd_J <= MB_R; -- ROCKET VERTICAL BIT 1 +MemBrd_9 <= MB_14; -- ROCKET VERTICAL BIT 0 + + +MemBrd_11 <= MB_B; -- 30Hz pulse train + +----------------------------------------------------------------------------- +-- COMPUTER SPACE BOARD INTRA CONNECTION MAPPING -- +-- from Memory Board to Motion Board -- +----------------------------------------------------------------------------- +MB_V <= MemBrd_X; -- rocket vertical velocity level bit 2 +MB_U <= MemBrd_V; -- rocket vertical velocity level bit 1 +MB_T <= MemBrd_W; -- rocket vertical velocity level bit 0 + +MB_4 <= MemBrd_15; -- rocket horizontal velocity level bit 2 +MB_D <= MemBrd_13; -- rocket horizontal velocity level bit 1 +MB_3 <= MemBrd_14; -- rocket horizontal velocity level bit 0 + +MB_H <= MemBrd_Y; -- rocket vertical velocity: + -- rocket going up or down + -- 0 up / 1 down + +MB_J <= MemBrd_16; -- rocket horizontal velocity: + -- rocket going right or left + -- 0 - left / 1 - right + +MB_19 <= MemBrd_T; -- rocket missile + -- vertical (up / down) speed + -- constant 1 - no speed + -- constant 0 - "60Hz" speed (60 pixels / second) + -- pulse 0/1 at 30 Hz rate + -- gives "30 Hz" speed (30 pixels / second) + +MB_18 <= MemBrd_12; -- rocket missile + -- vertical direction + -- 0 - up, 1 - down + +MB_17 <= MemBrd_U; -- rocket missile + -- horizontal (right/left) speed + -- constant 1 - no speed + -- constant 0 - "60Hz" speed + -- pulse 0/1 at 30 Hz rate + -- gives "30 Hz" speed + +MB_16 <= MemBrd_17; -- rocket missile + -- horizontal direction + -- 1- right, 0 - left + +----------------------------------------------------------------------------- +-- COMPUTER SPACE BOARD INTRA CONNECTION MAPPING -- +-- from Motion Board to Sync Star Board -- +----------------------------------------------------------------------------- +SB_3 <= MB_21; -- saucer enable +SB_E <= MB_W; -- rocket enable +SB_4 <= MB_10; -- saucer missile video +SB_6 <= MB_P; -- rocket missile video from motionboard to syncboard + -- (game on and collision/explosion) + +----------------------------------------------------------------------------- +-- COMPUTER SPACE BOARD INTRA CONNECTION MAPPING -- +-- from Sync Star Board to Memory Board -- +----------------------------------------------------------------------------- +MemBrd_K <= SB_2; -- saucer out / saucer enable + -- after collision/explosion logic has been applied + +MemBrd_10 <= SB_5; -- rocket_enable + -- after game on and collision/explosion + -- logic has been applied + +MemBrd_22 <= SB_L; -- explosion audio trigger + -- (in real impl connected to audio unit + -- on Memory Board) + +MemBrd_R <= SB_M; -- spin + +----------------------------------------------------------------------------- +-- COMPUTER SPACE BOARD INTRA CONNECTION MAPPING -- +-- from Memory Board to Sync Star Board -- +----------------------------------------------------------------------------- +SB_N <= MemBrd_P; -- video out (rocket and saucer) + +----------------------------------------------------------------------------- +-- COMPUTER SPACE BOARD INTRA CONNECTION MAPPING -- +-- from Sync Star Board to Motion Board -- +----------------------------------------------------------------------------- +MB_C <= SB_H; -- count enable +MB_20 <= SB_Y; -- clock inverse + +----------------------------------------------------------------------------- +-- CONNECTING TO BUTTONS -- +----------------------------------------------------------------------------- +SB_C <= signal_coin; +SB_7 <= signal_start; +MemBrd_S <= signal_thrust; +MB_Y <= signal_fire; +MemBrd_M <= signal_cw; +MemBrd_N <= signal_ccw; + +----------------------------------------------------------------------------- +-- CONNECTING TO AUDIO -- +-- -- +-- connecting to sound module, specific to the fpga board implementation -- +----------------------------------------------------------------------------- +audio_gate <= not SB_K; -- if high, then audio is active (game is on) + -- if low then audio is inactive (game is not on) + +sound_switch (1) <= MemBrd_K1; -- rocket rotation +sound_switch (2) <= MemBrd_K2; -- rocket thrust +sound_switch (3) <= MB_2_rocket; -- rocket missile shooting +sound_switch (4) <= MemBrd_22; -- explosion +sound_switch (5) <= MB_2_saucer; -- saucer missile shooting +sound_switch (6) <= '0'; + +end computer_space_logic_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/computer_space_top.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/computer_space_top.vhd new file mode 100644 index 00000000..a7bc383e --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/computer_space_top.vhd @@ -0,0 +1,199 @@ +----------------------------------------------------------------------------- +-- COMPUTER SPACE TOP LEVEL - embedded audio memory version -- +-- Implementation of Computer Space FPGA emulator. -- +-- -- +-- Developed primarily to understand the inner workings of -- +-- the Computer Space game logic. -- +-- -- +-- The emulator can also serve the purpose of game -- +-- preservation as the schematics have been copied "wire by wire" -- +-- and "component by component"/"gate by gate" and hence represents -- +-- a very close realization of the original, except for sound -- +-- generation which in this solution is based on audio samples. -- +-- -- +-- Some errors in the original schematics have been -- +-- discovered during the transfer of schematics into vhdl. They are -- +-- accounted for and corrected in the vhdl code. -- +-- -- +-- The Computer Space Logic part replicates the three Computer Space -- +-- Boards and represents the complete game. It is implementation agnostic, -- +-- but requires the ability to support global clock signals, -- +-- input signals from control panel buttons and -- +-- coin mechanism, output signal to trigger audio and output signal for -- +-- composite ntsc video and audio. -- +-- -- +-- -- +-- Credit goes to: -- +-- * Overall fpga development community; there is a lot of stuff -- +-- readily available as inspiration and working code - in -- +-- particular regarding the implementation specifics -- +-- * Mike Salay (KLOV: road.runner) - who has provided a large number -- +-- of measurement points from real Computer Space boards to determine-- +-- timer values, resolve logic behind the distribution of stars on -- +-- screen and verify the original video sync logic. -- +-- * Computerspacefan.com - who has provided sound samples and -- +-- original schematics -- +-- * Chris (http://www.pyroelectro.com/) whose code for interlaced -- +-- ntsc signalling I have kindly used as a basis for creating an -- +-- interlaced ntsc video signal version -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; + +--80---------------------------------------------------------------------------| + +entity computer_space_top is + port + ( + reset : in std_logic; + clock_50 : in std_logic; + game_clk : in std_logic; + + signal_ccw : in std_logic; + signal_cw : in std_logic; + signal_thrust : in std_logic; + signal_fire : in std_logic; + signal_start : in std_logic; + + hsync : out std_logic; + vsync : out std_logic; + blank : out std_logic; + video : out std_logic; + + wav_out : out signed (15 downto 0) + ); +end computer_space_top; + +architecture computer_space_architecture + of computer_space_top is + +component clocks is + port ( + clock_50 : in std_logic; + thrust_and_rotate_clk : out std_logic:='0'; + explosion_clk : out std_logic; + explosion_rotate_clk : out std_logic; + seconds_clk : out std_logic; + timer_base_clk : out std_logic; + rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : out integer + ); +end component clocks; + +component computer_space_logic is + port ( + reset, + game_clk, super_clk, explosion_clk, + seconds_clk : in std_logic; + timer_base_clk : in std_logic; + rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : in integer; + thrust_and_rotate_clk, + explosion_rotate_clk : in std_logic; + signal_start, signal_coin, + signal_thrust, signal_fire, + signal_cw, signal_ccw : in std_logic; + composite_video_signal : out std_logic; + blank : out std_logic; + hsync : out std_logic; + vsync : out std_logic; + audio_gate : out std_logic; + sound_switch : out std_logic_vector (7 downto 0) + ); +end component computer_space_logic; + +component sound is + port ( + clock_50, audio_gate : in std_logic; + sound_switch : in std_logic_vector (7 downto 0); + sigma_delta_wav : out signed (15 downto 0) + ); +end component sound; + +-- signals for thrust +-- so that a continuous button push +-- create continuous thrust and/or +-- rotation +signal thrust_and_rotate_clk : std_logic:='0'; + +-- signals for explosion circuitry +-- logic +signal explosion_clk : std_logic; + +-- clock to rotate the rocket +-- rapdily at explosion +signal explosion_rotate_clk : std_logic; + +--signals for clock counting seconds +signal seconds_clk : std_logic; + +-- timer components for Motion Board +signal timer_base_clk : std_logic; +signal rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : integer; + +-- signals for composite +-- video + + +-- signals to fetch and activate sound +-- from audio memory +signal sound_switch : std_logic_vector (7 downto 0) + := "00000000" ; +-- not using bit 0, only bit 1 to 5 +-- 1 = rocket rotate +-- 2 = rocket thrust, +-- 3 = rocket missile +-- 4 = rocket explosion, +-- 5 = saucer missile shooting + +signal audio_gate : std_logic; + + + +------------------------------------------------------------------------// +begin + +-------------------------------------------------------------------------- +-- GENERATE CLOCKS -- +-------------------------------------------------------------------------- +generate_clock : CLOCKS +port map +(clock_50, thrust_and_rotate_clk,explosion_clk, explosion_rotate_clk, +seconds_clk, timer_base_clk, +rocket_missile_life_time_duration, saucer_missile_life_time_duration, +saucer_missile_hold_duration, signal_delay_duration); + +-------------------------------------------------------------------------- +-- CORE COMPUTER SPACE LOGIC -- +-------------------------------------------------------------------------- +computer_space : COMPUTER_SPACE_LOGIC +port map +(reset, game_clk, clock_50, explosion_clk, seconds_clk, timer_base_clk, +rocket_missile_life_time_duration, saucer_missile_life_time_duration, +saucer_missile_hold_duration, signal_delay_duration, +thrust_and_rotate_clk, explosion_rotate_clk, +signal_start, signal_start, signal_thrust, signal_fire, +signal_cw,signal_ccw, video, blank, +hsync, vsync, +audio_gate, sound_switch +); + +audio_playback : sound + port map (clock_50, audio_gate, sound_switch, wav_out); + +end computer_space_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion.qip new file mode 100644 index 00000000..f10ca668 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "explosion.vhd"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion.vhd new file mode 100644 index 00000000..759a2a44 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: explosion.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY explosion IS + PORT + ( + address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END explosion; + + +ARCHITECTURE SYN OF explosion IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "explosion_8_11.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 16384, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + widthad_a => 14, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "explosion_8_11.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "explosion_8_11.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL explosion.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL explosion.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL explosion.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL explosion.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL explosion_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion_8_11.hex b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion_8_11.hex new file mode 100644 index 00000000..0057a0a1 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/explosion_8_11.hex @@ -0,0 +1,276 @@ +:200000000305040705030404020302FF01F6E8EBEEF1FE040607080C0E1315152022190F36 +:200020000702FDFDF8F1EAE0E1E6E5E8EAE9EDF0F3F9FAFBFF01040808090A0A0B0C0C0C85 +:200040000C0D0F0E0C0B0909090604010000FEFCFAFAFAF9F4EDE8F3FAEDF0F6EEF70303D8 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Hardware/ComputerSpace_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..3e406318 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bxx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/keyboard.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/memory_board.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/memory_board.vhd new file mode 100644 index 00000000..fc10e204 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/memory_board.vhd @@ -0,0 +1,1839 @@ +----------------------------------------------------------------------------- +-- MEMORY BOARD LOGIC -- +-- For use with Computer Space FPGA emulator. -- +-- Implementation of Computer Space's Memory Board -- +-- "wire by wire" and "component by component"/"gate by gate" -- +-- according to original schematics. -- +-- With exceptions regarding: -- +-- > analogue based timers (impl as counters) -- +-- > all flip flops / ICs using asynch clock inputs are replaced with -- +-- flip flops driven by a high freq clock and logic to -- +-- identify edge changes on the logical clock input -- +-- > the "diode matrix" is implemented as a vector rather than a diode -- +-- equivalent; but the resulting functionality becomes the same -- +-- > sound pulse trains used by the analogue sound unit are replaced by -- +-- on/off flags to trigger sound sample playback -- +-- -- +-- This entity is implementation agnostic -- +-- -- +-- There are plenty of comments throughout the code to make it easier to -- +-- understand the logic, but due to the sheer number of comments there -- +-- may exist occasional mishaps. -- +-- -- +-- Please take a moment to marvel at the logic behind rotating the four -- +-- core rocket images into 32 different positions. Very clever, keeping in -- +-- mind this was done back in 1971 (without RAM, ROM and CPU) -- +-- and that this was the first commercial video arcade game ever. -- +-- Pretty cool and ambitious graphics stuff to go for as a first, -- +-- compared to the simplicity of the subsequent Pong graphics. -- +-- Even in "modern" day it is not all together easy to figure out how to -- +-- create 32 rotational position images based on four (16x16 pixel) base -- +-- images. Hats off! -- +-- -- +-- Naming convention: -- +-- Signals are labelled after the component that generates the signal; -- +-- more specifically the component's schematics label and the specific -- +-- output. For instance: NOR gate F6 and its output pin 10 generate a -- +-- signal which will be labelled f6_10. -- +-- Occasionally signals are labelled after a component input - this is -- +-- most common for components where the input is exposed -- +-- to "component-internal processing" beyond simple gate functionality, -- +-- such as bistable latches, counters, flip-flops and multiplexers. -- +-- Memory Board inputs/outputs are labelled MemBrd_, where is -- +-- according to original schematics input/output labels. -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; + +--80--------------------------------------------------------------------------| + +entity memory_board is + port( + super_clk, -- Clock to emulate + -- asynch flip flop logic + + thrust_and_rotate_clk, + explosion_rotate_clk : in std_logic := '1'; + + MemBrd_2, -- saucer 16x8 image's + -- vertical position bit 1 + MemBrd_3, -- saucer 16x8 image's + -- horizontal position bit 1 + MemBrd_4, -- rocket 16x16 image's + -- horizontal position bit 1 + MemBrd_5, -- rocket 16x16 image's + -- vertical position bit 1 + MemBrd_6, -- saucer 16x8 image's + -- vertical position bit 3 + MemBrd_7, -- saucer 16x8 image's + -- horizontal position bit 3 + MemBrd_8, -- rocket 16x16 image's + -- vertical position bit 3 + MemBrd_9, -- rocket 16x16 image's + -- horizontal position bit 3 + + MemBrd_10, -- Rocket Enable + -- the tv beam is in position + -- to display rocket + -- on screen and the + -- rocket image can actually be + -- displayed (for instance + -- rocket should not be visible + -- on screen directly after + -- being hit by saucer missile, + -- having collided with saucer + -- or game is not playing) + + MemBrd_11, -- 30Hz pulse train + -- to give rocket missile + -- vertical and/or + -- horizontal "speed" with + -- which it can move in + -- "angels" other than + -- up/down, righ/left and + -- 45/135/225/315 degrees + -- Resulting angels are: + -- 22,5/67,5/112.5/157,5/ + -- 212.5/257.5/302.5/342.5 + -- degrees + + MemBrd_A, -- saucer 16x8 image's + -- vertical position bit 0 + MemBrd_B, -- saucer 16x8 image's + -- horizontal position bit 0 + MemBrd_C, -- rocket 16x16 image's + -- vertical position bit 0 + MemBrd_D, -- rocket 16x16 image's + -- horizontal position bit 0 + MemBrd_E, -- saucer 16x8 image's + -- vertical position bit 2 + MemBrd_F, -- saucer 16x8 image's + -- horizontal position bit 2 + MemBrd_H, -- rocket 16x16 image's + -- vertical position bit 2 + MemBrd_J, -- rocket 16x16 image's + -- horizontal position bit 2 + + MemBrd_K, -- Saucer Enable + -- the tv beam is in position + -- to display one of the + -- saucers on screen + -- and the saucer + -- image will actually be + -- displayed (for instance a + -- saucer should not be visible + -- on screen directly after + -- being hit by rocket missile, + -- or having collided + -- with rocket) + + MemBrd_M, -- signal to rotate + -- rocket clock wise (cw) + + MemBrd_N, -- signal to rotate + -- rocket counter + -- clock wise (ccw) + + MemBrd_R, -- signal to spin rocket + -- clock wise during + -- explosion + + MemBrd_S -- Thrust button pressed + : in std_logic; + + MemBrd_12, -- rocket pointing upwards + -- or downwards + -- 0 - up / 1 - down + + MemBrd_13, -- rocket horizontal + -- velocity level bit 1 + MemBrd_14, -- rocket horizontal + -- velocity level bit 0 + MemBrd_15, -- rocket horizontal + -- velocity level bit 2 + MemBrd_16, -- rocket horizontal + -- velocity: rocket going + -- right or left + -- 0 - left / 1 - right + + MemBrd_17, -- rocket pointing towards + -- right or left + -- 0 - left / 1 - right + + MemBrd_K1, -- signal for rocket rotation + -- audio + + MemBrd_K2, -- signal for rocket thrust + -- audio + + MemBrd_P, -- video out (rocket and + -- saucer) + + MemBrd_T, -- Rocket Missile + -- Up/Down Enable + -- 0 - up/down allowed + -- 1 - up/down not allowed + -- Is either constantly + -- 1 or 0 or + -- switches between 1 and 0 + -- with a 30 Hz frequency + -- to allow for rocket + -- missile direction of: + -- 67,5/112.5/257.5/302.5 + -- degrees + MemBrd_U, -- Rocket Missile + -- Right/Left Enable + -- 0 - right/left allowed + -- 1 - right/left not allowed + -- Is either constantly + -- 1 or 0 or + -- switches between 1 and 0 + -- with a 30 Hz frequency + -- to allow for rocket + -- missile direction of + -- 22,5/157,5/212.5/342.5 + -- degrees + MemBrd_V, -- rocket vertical + -- velocity level bit 1 + MemBrd_W, -- rocket vertical + -- velocity level bit 0 + MemBrd_X, -- rocket vertical + -- velocity level bit 2 + MemBrd_Y -- rocket vertical velocity: + -- rocket going up or down + -- 0 up / 1 down + : out std_logic + ); + +end memory_board; + +architecture memory_board_architecture + of memory_board is + +component rocket_diode_images is +port( + image_select : in integer range 0 to 3; + rocket_hor, rocket_ver : in integer range 0 to 15; + diode_left_column, diode_right_column : in std_logic; + out_image_bit : out std_logic + ); +end component; + +component saucer_diode_image is +port( + saucer_enable : in std_logic; + saucer_ver : in integer range 0 to 7; + saucer_hor : in integer range 0 to 15; + saucer_diode_rotating_light : in std_logic; + out_saucer_image_bit : out std_logic + ); +end component; + +-- statemachine type for 74193 +-- with carry and borrow +TYPE STATE_TYPE IS +(UNSIGNED_UP_DOWN, READY_FOR_CARRY, +READY_FOR_BORROW, CARRY, BORROW); + +-- A5 pins, 7486 +signal a5_8,a5_11,a5_3,a5_6 : std_logic; + +-- B5 pins, 7486 +signal b5_8, b5_11, b5_3, b5_6 : std_logic; + +-- A6 pins, 74153 +signal a6_10, a6_11, a6_12, a6_13, a6_6, + a6_4, a6_3, a6_14,a6_2, a6_7, a6_9, + a6_5 : std_logic; + +-- B6 pins, 74153 +signal b6_10, b6_11, b6_12, b6_13, b6_6, + b6_4,b6_3, b6_14,b6_2, b6_7, b6_9, + b6_5 : std_logic; + +-- C6 pins, 74153 +signal c6_10, c6_11, c6_12, c6_13, c6_6, + c6_4, c6_3, c6_14,c6_2,c6_7, c6_9, + c6_5 : std_logic; + +-- D6 pins, 74153 +signal d6_10, d6_11,d6_12, d6_13, d6_6, + d6_4, d6_3, d6_14, d6_2, d6_7, + d6_9, d6_5 : std_logic; + +signal f4_4,f4_8,c5_8, c5_11, c5_3 : std_logic :='0'; +signal e1_10, e2_9, e2_7, e1_13, h2_8, + e5_3, c5_6 : std_logic:='0'; +signal diode_image0_bit, diode_image1_bit, + diode_image2_bit, diode_image3_bit : std_logic :='0'; + +signal rocket_hor, rocket_ver : integer range 0 to 15; +signal saucer_ver : integer range 0 to 7; +signal saucer_hor : integer range 0 to 15; +signal saucer_image_bit : std_logic :='0'; + +signal RVER, RHOR : std_logic_vector (3 downto 0); +signal SVER : std_logic_vector (2 downto 0); +signal count : integer range 0 to 15 := 0; +signal counter_clock : std_logic; +signal count_r : unsigned (3 downto 0) := "0000"; +signal e4_count : unsigned (3 downto 0) := "0000"; + +signal e4_12 ,e4_13 : std_logic :='1'; +-- set to initial '1' to avoid ship from +-- flipping from initial position + +signal h2_10, e4_4, e4_5, e4_2, e4_3, + e4_6, e4_7, e4_11 : std_logic; +signal e2_7x, e2_9x : std_logic; +signal e3_1 : std_logic; + +signal e2_10, e2_11, e2_2, e2_14, e2_15, + e2_1,e2_3, e2_4 , e2_5, e2_12, e2_6, + e2_13 : std_logic; + +signal f6_8, e5_6, d5_3, e6_10 : std_logic; +signal f4_10, e5_11, d5_11, d5_8, e5_8 : std_logic; +signal d5_6, e4_11_process : std_logic; +signal e3_15 : std_logic := '0'; +signal e3_14 : std_logic := '1'; + +-- thrust circuitry and velocity signals +signal f2_12,f2_10, f3_3, h2_6, f3_6 : std_logic; +signal j4_2, j4_3,j4_4, j4_5, j4_6, j4_7 : std_logic; +signal j5_6, j5_11, j5_3 : std_logic; +signal j6_6, inv_4, j6_8, j3_8, j3_6, + j2_10, j2_13 : std_logic; +signal h4_2, h4_3, h4_4, h4_5, h4_6, h4_7 : std_logic; +signal h5_6, h5_11, h5_3, h6_6, h2_2, + h6_8, h3_6, h3_8, h2_12 : std_logic; +signal f5_10, f5_13, h5_8, j5_8, + f4_6, f6_6, f4_2, f4_12, f5_4, f5_1 : std_logic; + +signal thrust : std_logic; +signal j4_count, h4_count : unsigned (3 downto 0) := "0000"; +signal j4_clock, h4_clock : std_logic; + +signal explode_rotate_clock_wise, + combined_clk : std_logic; + +-- rocket engine flame +signal diode_row_1, diode_row_3, f2_6, + f2_8, e1_1, e1_4, f3_8, f3_11, + diode_left_column, + diode_right_column : std_logic; + +-- saucer rotating light +signal saucer_diode_rotating_light : std_logic; + +-- signals to manage asynchronous +-- clock design embedded in +-- synchronous clk solutions +signal e4_4_old, e4_5_old, e3_1_old : std_logic; +signal j4_4_old, j4_5_old, h4_4_old, + h4_5_old : std_logic; + +-- signals for audio +signal e6_4, e6_1 : std_logic; + +-- signals for 74193 circuit statemachine +signal state : STATE_TYPE := UNSIGNED_UP_DOWN; + +----------------------------------------------------------------------------// +begin + +----------------------------------------------------------------------------- +-- GENERAL INFORMATION -- +-- The rocket has four base images from which in total 32 different images -- +-- are created to represent the rocket’s rotational positions. The 32 -- +-- images are created through the following 3 key-mechanisms: -- +-- 1) Vary which base image to read from; Choose between one of the -- +-- four images -- +-- 2) Vary image read direction: Reading the base image either "top to -- +-- bottom" or "bottom to top" and from "right to left" or "left to -- +-- right" -- +-- 3) Vary image x-y axis: Reading the base image’s horizontal -- +-- slices (rows) as horizontal slices (rows) onto screen or -- +-- reading the vertical slices (columns) as horizontal slices (rows) -- +-- onto screen -- +-- -- +-- The Memory Board contains logic that can determine which base image to -- +-- select, which image read direction to apply and which image axis setup -- +-- to use depending on the rocket’s rotational position. -- +-- -- +-- ALL ROCKET ORIENTATIONS AND THEIR CORRESPONDING IMAGE LOGIC: -- +-- Deg - approx degree that the rocket is pointing in -- +-- R/L - indicate if rocket is pointing to the right or to the left -- +-- Pos - the corresponding "position value" for a specific degree -- +-- (R/L-flag and Pos together corresponds to any of the unique 32 rocket -- +-- orientations / degrees) -- +-- Image - the diode matrix image (0-3) to use -- +-- Image Read Direction - How the diode matrix image is being read along -- +-- its two "axis" -- +-- X-Y axis setup - (Horizontal-2-Horizontal): The image's horizontal -- +-- slices will be fed to -- +-- the screen as horizontal -- +-- slices acc to Image Read -- +-- Direction -- +-- (Vertical-2-Horizontal) : The image's vertical -- +-- slices will be fed to -- +-- the screen as horizontal -- +-- slices acc to Image Read -- +-- Direction -- +-- -- +-- Deg R/L Pos Image Image Read Direction X-Y Axis Setup -- +-- === === === ===== ====================== ======================= -- +-- ~3 R 0 0 Top2Bottom Left2Right Horizontal-2-Horizontal -- +-- ~16 R 1 1 Top2Bottom Left2Right Horizontal-2-Horizontal -- +-- ~32 R 2 2 Top2Bottom Left2Right Horizontal-2-Horizontal -- +-- ~43 R 3 3 Top2Bottom Left2Right Horizontal-2-Horizontal -- +-- -- +-- ~47 R 4 3 Bottom2Top Right2Left Vertical-2-Horizontal -- +-- ~61 R 5 2 Bottom2Top Right2Left Vertical-2-Horizontal -- +-- ~74 R 6 1 Bottom2Top Right2Left Vertical-2-Horizontal -- +-- ~87 R 7 0 Bottom2Top Right2Left Vertical-2-Horizontal -- +-- -- +-- ~93 R 8 0 Bottom2Top Left2Right Vertical-2-Horizontal -- +-- ~105 R 9 1 Bottom2Top Left2Right Vertical-2-Horizontal -- +-- ~121 R 10 2 Bottom2Top Left2Right Vertical-2-Horizontal -- +-- ~134 R 11 3 Bottom2Top Left2Right Vertical-2-Horizontal -- +-- -- +-- ~137 R 12 3 Bottom2Top Left2Right Horizontal-2-Horizontal -- +-- ~151 R 13 2 Bottom2Top Left2Right Horizontal-2-Horizontal -- +-- ~163 R 14 1 Bottom2Top Left2Right Horizontal-2-Horizontal -- +-- ~175 R 15 0 Bottom2Top Left2Right Horizontal-2-Horizontal -- +-- -- +-- ~183 L 0 0 Bottom2Top Right2Left Horizontal-2-Horizontal -- +-- ~197 L 1 1 Bottom2Top Right2Left Horizontal-2-Horizontal -- +-- ~209 L 2 2 Bottom2Top Right2Left Horizontal-2-Horizontal -- +-- ~223 L 3 3 Bottom2Top Right2Left Horizontal-2-Horizontal -- +-- -- +-- ~229 L 4 3 Top2Bottom Left2Right Vertical-2-Horizontal -- +-- ~240 L 5 2 Top2Bottom Left2Right Vertical-2-Horizontal -- +-- ~253 L 6 1 Top2Bottom Left2Right Vertical-2-Horizontal -- +-- ~267 L 7 0 Top2Bottom Left2Right Vertical-2-Horizontal -- +-- -- +-- ~274 L 8 0 Top2Bottom Right2Left Vertical-2-Horizontal -- +-- ~287 L 9 1 Top2Bottom Right2Left Vertical-2-Horizontal -- +-- ~300 L 10 2 Top2Bottom Right2Left Vertical-2-Horizontal -- +-- ~312 L 11 3 Top2Bottom Right2Left Vertical-2-Horizontal -- +-- -- +-- ~319 L 12 3 Top2Bottom Right2Left Horizontal-2-Horizontal -- +-- ~331 L 13 2 Top2Bottom Right2Left Horizontal-2-Horizontal -- +-- ~343 L 14 1 Top2Bottom Right2Left Horizontal-2-Horizontal -- +-- ~356 L 15 0 Top2Bottom Right2Left Horizontal-2-Horizontal -- +----------------------------------------------------------------------------- + +----------------------------------------------------------------------------- +-- Saucer Video Enable -- +-- Inverting the Saucer Enable signal for downstream logic -- +-- where it is applicable to have the inverse as "active" -- +----------------------------------------------------------------------------- +f4_8 <= not MemBrd_K; -- f4_8 is (inverse) active + -- when saucer video should be + -- displayed + +----------------------------------------------------------------------------- +-- IMAGE READ: Select horizontal diode matrix slice -- +-- 7486 xor -- +-- diode matrix "horizontal slice" (row) selector -- +-- Input to 74154 for both saucer, rocket, regarding which -- +-- horizontal slice to read image pixel data from -- +-- 4-bit binary number that can address 16 slices (0-15) -- +----------------------------------------------------------------------------- +a5_8 <= a6_9 xor f4_4; -- D ; horizontal slice number bit 3 +a5_11 <= b6_9 xor f4_4; -- C ; horizontal slice number bit 2 +a5_3 <= c6_9 xor f4_4; -- B ; horizontal slice number bit 1 +a5_6 <= d6_9 xor f4_4; -- A ; horizontal slice number bit 0 + +----------------------------------------------------------------------------- +-- IMAGE READ: Select vertical diode matrix slice -- +-- 7486 xor -- +-- diode matrix "vertical slice" (colum) selector -- +-- -- +-- Input to 74151 for saucer, and 74150:s for rocket, regarding which -- +-- vertical slice to read image pixel data from -- +-- 4-bit binary number that can address 16 slices (0-15) -- +-- 74151 is only using three bits (0-2); and can consequently address 8 -- +-- slices -- +-- 74151: Only 5 inputs are connected to diode matrix slices -- +-- 74150:s Only 12 inputs are connected to diode matrix slices -- +-- The other inputs that are not connected to any slice will only give -- +-- "black" pixels when addressed -- +----------------------------------------------------------------------------- +b5_8 <= a6_7 xor c5_11; -- D ; vertical slice number bit 3 +b5_11 <= b6_7 xor c5_11; -- C ; vertical slice number bit 2 +b5_3 <= c6_7 xor c5_11; -- B ; vertical slice number bit 1 +b5_6 <= d6_7 xor c5_11; -- A ; vertical slice number bit 0 + +----------------------------------------------------------------------------- +-- IMAGE READ: Select saucer vertical diode matrix slice -- +-- 74151 8-Line To 1-Line Data Selector / Multiplexer -- +-- DECODE VERTICAL DIODE IMAGE LINES -- +-- SVER(0) is pin 11 A -- +-- SVER(1) is pin 10 B -- +-- SVER(2) is pin 9 C -- +----------------------------------------------------------------------------- +SVER(0) <= b5_6; -- 74151 pin11 A +SVER(1) <= b5_3; -- 74151 pin10 B +SVER(2) <= b5_11; -- 74151 pin9 C + +-- DECODE +saucer_ver <= + 0 when SVER ="000" else + 1 when SVER ="001" else + 2 when SVER ="010" else + 3 when SVER ="011" else + 4 when SVER ="100" else + 5 when SVER ="101" else + 6 when SVER ="110" else + 7 ; + +----------------------------------------------------------------------------- +-- IMAGE READ: Select saucer horizontal diode matrix slice -- +-- SAUCER 74153 4-Line To 16-Line Decoders/Demultiplexers -- +-- DECODE HORIZONTAL DIODE IMAGE LINES -- +----------------------------------------------------------------------------- +saucer_hor <= rocket_hor; -- horizontal decoding the same as for rocket; + -- use the same 74154 to "activate" a + -- horizontal slice of diodes + +----------------------------------------------------------------------------- +-- IMAGE READ: SAUCER DIODE MATRIX & 74151: -- +-- emulates the diode matrix and the part of 74151 that reads the matrix -- +-- value -- +-- corresponds to activating a specific horizontal slice -- +-- and reading resulting "value" for a specific vertical slice -- +----------------------------------------------------------------------------- +saucer_image: saucer_diode_image +port map (MemBrd_K, saucer_ver, saucer_hor, + saucer_diode_rotating_light, saucer_image_bit); + + +----------------------------------------------------------------------------- +-- IMAGE READ: SAUCER VIDEO ENABLE -- +-- Letting saucer image pass through to screen output -- +-- This "filter" prevents the saucer image from being written -- +-- repeatedly when it shouldnt -- +----------------------------------------------------------------------------- +c5_6 <= saucer_image_bit nand f4_8; -- f4_8 is only active when + -- saucer should be displayed + +----------------------------------------------------------------------------- +-- IMAGE READ: Select rocket horizontal diode matrix slice -- +-- DECODE HORIZONTAL DIODE IMAGE LINES -- +-- 74154 connection -- +-- RHOR(0) is pin 23 A -- +-- RHOR(1) is pin 22 B -- +-- RHOR(2) is pin 21 C -- +-- RHOR(3) is pin 20 D -- +----------------------------------------------------------------------------- +RHOR(0) <= a5_6; -- 74154 pin23 A +RHOR(1) <= a5_3; -- 74154 pin22 B +RHOR(2) <= a5_11; -- 74154 pin21 C +RHOR(3) <= a5_8; -- 74154 pin20 D + +-- DECODE +rocket_hor <= + 0 when RHOR ="0000" else + 1 when RHOR ="0001" else + 2 when RHOR ="0010" else + 3 when RHOR ="0011" else + 4 when RHOR ="0100" else + 5 when RHOR ="0101" else + 6 when RHOR ="0110" else + 7 when RHOR ="0111" else + 8 when RHOR ="1000" else + 9 when RHOR ="1001" else + 10 when RHOR ="1010" else + 11 when RHOR ="1011" else + 12 when RHOR ="1100" else + 13 when RHOR ="1101" else + 14 when RHOR ="1110" else + 15; + +----------------------------------------------------------------------------- +-- IMAGE READ: Select rocket vertical diode matrix slice -- +-- 74150's - all four -- +-- DECODE VERTICAL DIODE IMAGE LINES -- +-- RVER(0) is pin 15 A -- +-- RVER(1) is pin 14 B -- +-- RVER(2) is pin 13 C -- +-- RVER(3) is pin 11 D -- +----------------------------------------------------------------------------- +RVER(0) <= b5_6; -- 74150 pin15 A +RVER(1) <= b5_3; -- 74150 pin14 B +RVER(2) <= b5_11; -- 74150 pin13 C +RVER(3) <= b5_8; -- 74150 pin11 D + +-- DECODE +rocket_ver <= + 0 when RVER ="0000" else + 1 when RVER ="0001" else + 2 when RVER ="0010" else + 3 when RVER ="0011" else + 4 when RVER ="0100" else + 5 when RVER ="0101" else + 6 when RVER ="0110" else + 7 when RVER ="0111" else + 8 when RVER ="1000" else + 9 when RVER ="1001" else + 10 when RVER ="1010" else + 11 when RVER ="1011" else + 12 when RVER ="1100" else + 13 when RVER ="1101" else + 14 when RVER ="1110" else + 15; + +----------------------------------------------------------------------------- +-- IMAGE READ: ROCKET DIODE MATRIX & 74150: Rocket Image 0 - 3 -- +-- emulates the diode matrix and the part of 74150 that reads the matrix -- +-- value -- +-- corresponds to activating a specific horizontal slice -- +-- and reading resulting "value" for a specific vertical slice -- +----------------------------------------------------------------------------- +rocket_image_0: rocket_diode_images +port map (0, rocket_hor,rocket_ver, + diode_left_column, diode_right_column, diode_image0_bit); + +rocket_image_1: rocket_diode_images +port map (1, rocket_hor,rocket_ver, + diode_left_column, diode_right_column, diode_image1_bit); + +rocket_image_2: rocket_diode_images +port map (2, rocket_hor, rocket_ver, + diode_left_column, diode_right_column, diode_image2_bit); + +rocket_image_3: rocket_diode_images +port map (3, rocket_hor, rocket_ver, + diode_left_column, diode_right_column, diode_image3_bit); + + +----------------------------------------------------------------------------- +-- IMAGE READ: Rocket Engine "Flame" Logic -- +----------------------------------------------------------------------------- +diode_row_1 <= '0' when rocket_hor = 0 else '1'; + +diode_row_3 <= '0' when rocket_hor = 2 else '1'; + +e1_1 <= f2_6 nor diode_row_1; +e1_4 <= f2_8 nor diode_row_3; + +f3_8 <= e1_1 nand MemBrd_S; +f3_11 <= e1_4 nand MemBrd_S; + +diode_left_column <= not f3_8; -- send info to diode image component + -- (in real circuit expecting active low, + -- in this realization - active high) + + +diode_right_column <= not f3_11; -- send info to diode image component + -- (in real circuit expecting active + -- low, in this realization - active high) + + +----------------------------------------------------------------------------- +-- THRUST CIRCUITRY: Create thrust pulse train -- +----------------------------------------------------------------------------- +f2_6 <= thrust_and_rotate_clk; -- emulating the clk that is generated + -- by the digital and discrete/analogues + +f2_8 <= not thrust_and_rotate_clk; -- emulating the clk that is generated + -- by the digital and discrete/analogues + +----------------------------------------------------------------------------- +-- IMAGE READ: Saucer "Rotating Lights" Logic -- +-- using a signal to create a pulse train to drive rotating light -- +-- frequency -- +-- the pulse train is derived from reading a bit of the rocket's -- +-- horizontal scan counter -- +----------------------------------------------------------------------------- +saucer_diode_rotating_light <= not MemBrd_H; + +----------------------------------------------------------------------------- +-- IMAGE READ: X-Y AXIS IMAGE READ CONTROL - bit 3 processing -- +-- A6, 74153 -- +-- 4-line to 1-line data selector/multiplexor -- +-- (a,b) select c0 to c3 -- +-- (0,0):c0=>y, (0,1):c1=>y, (1,0):c2=>y, (1,1):c3=>y -- +-- -- +-- Rocket & Saucer hor & vert bit 3 processing -- +-- -- +-- OVERALL: A6, B6, C6, D6 Logic -- +-- Forwards which horizontal and vertical position to read from the saucer -- +-- and rocket's images - ie which pixel from the 16x8 or 16x16 image -- +-- grid to output to screen - and whether to read the rocket's image’s -- +-- horizontal slices as horizontal slices onto the screen or reading the -- +-- vertical slices as horizontal slices onto screen. -- +-- The saucer is always default to reading the vertical slices as -- +-- horizontal slices onto screen. -- +-- -- +-- The positions are given as 4-bit values (0000 - 1111; 16 positions) -- +-- and each chip (A6, B6, C6, D6) manages one of the bits each; for both -- +-- the vertical and the horizontal position for the saucer and the rocket. -- +-- A6 - bit 3, B6 - bit 2, C6 - bit 1, D6 - bit 0, -- +-- -- +-- The output can only be either rocket or saucer positions, so a set -- +-- of selectors choose between saucer and rocket and also determine -- +-- whether to read the rocket's image’s horizontal slices as horizontal -- +-- slices onto the screen or reading the vertical slices as horizontal -- +-- slices onto screen. -- +-- The saucer is always default to reading he vertical slices as -- +-- horizontal slices onto screen. -- +-- -- +-- The input is fed by rocket's motion counter's horizontal and vertical -- +-- lower bits (0-3 for horizontal / x-axis and 8-11 for vertical / y-axis) -- +-- and likewise from the saucer's motion counter -- +-- These feeds are constantly active and contribute to overall image pixel -- +-- read, but at a further stage, in the Memory Board, image video is only -- +-- "allowed" when the rocket's 16x16 image position or one of the -- +-- saucers's two 16x8 images positions matches the TV beams current -- +-- position as it sweeps across the TV screen. This is done via -- +-- Rocket Enable and Saucer Enable flags. Otherwise images would be -- +-- repeated across the screen for every 16 pixels and 16 lines (8 lines -- +-- for saucer) -- +-- -- +-- The selector input combination a and b determines which input to pass -- +-- through to rest of the graphics circuitry. -- +-- The way a and b are fed by upstream logic and how the data inputs -- +-- are "reverse connected" gives the following effect: -- +-- b - determines whether saucer or rocket should be fed to screen -- +-- a - determines whether the rocket's horizontal image slices should -- +-- be displayed on the x axis or y axis on the screen and consequently -- +-- whether the rocket's vertical image slices should be displayed on the -- +-- y or x axis. This is the basis for one subsset of the 32 potential -- +-- rocket images. -- +-- Selector a does not vary for saucer image as it is pre-set by -- +-- up stream logic whenever selector b is set to display saucer (c5_3) -- +----------------------------------------------------------------------------- +a6_10 <= MemBrd_C; -- data input 2C0 rocket horizontal bit 3 +a6_11 <= MemBrd_D; -- data input 2C1 rocket vertical bit 3 +a6_12 <= MemBrd_A; -- data input 2C2 saucer vertical bit 3 +a6_13 <= MemBrd_B; -- data input 2C3 saucer horizontal bit 3 + +a6_6 <= a6_11; -- data input 1C0 rocket vertical bit 3 +a6_5 <= a6_10; -- data input 1C1 rocket horizontal bit 3 +a6_4 <= a6_13; -- data input 1C2 saucer horizontal bit 3 +a6_3 <= a6_12; -- data input 1C3 saucer vertical bit 3 + +a6_14 <= c5_3; -- A select INPUT depending on rotation +a6_2 <= f4_8; -- B select INPUT depends on saucer enable + +a6_7 <= -- output y1 + a6_6 when (a6_14='0' and a6_2='0') else + a6_5 when (a6_14='1' and a6_2='0') else + a6_4 when (a6_14='0' and a6_2='1') else + a6_3; + +a6_9 <= -- output y2 + a6_10 when (a6_14='0' and a6_2='0') else + a6_11 when (a6_14='1' and a6_2='0') else + a6_12 when (a6_14='0' and a6_2='1') else + a6_13; + +----------------------------------------------------------------------------- +-- IMAGE READ: X-Y AXIS IMAGE READ CONTROL - bit 2 processing -- +-- B6, 74153 -- +-- 4-line to 1-line data selector/multiplexor -- +-- (a,b) select c0 to c3 -- +-- (0,0):c0=>y, (0,1):c1=>y, (1,0):c2=>y, (1,1):c3=>y -- +-- -- +-- For overall logic refer to A6 -- +----------------------------------------------------------------------------- +b6_10 <= MemBrd_4; -- data input 2C0 rocket horizontal bit 2 +b6_11 <= MemBrd_5; -- data input 2C1 rocket vertical bit 2 +b6_12 <= MemBrd_2; -- data input 2C2 saucer vertical bit 2 +b6_13 <= MemBrd_3; -- data input 2C3 saucer horizontal bit 2 + +b6_6 <= b6_11 ; -- data input 1C0 rocket vertical bit 2 +b6_5 <= b6_10; -- data input 1C1 rocket horizontal bit 2 +b6_4 <= b6_13; -- data input 1C2 saucer horizontal bit 2 +b6_3 <= b6_12; -- data input 1C3 saucer vertical bit 2 + +b6_14 <= c5_3; -- A select INPUT +b6_2 <= f4_8; -- B select INPUT depends on saucer enable + +b6_7 <= -- output y1 + b6_6 when (b6_14='0' and b6_2='0') else + b6_5 when (b6_14='1' and b6_2='0') else + b6_4 when (b6_14='0' and b6_2='1') else + b6_3; + +b6_9 <= -- output y2 + b6_10 when (b6_14='0' and b6_2='0') else + b6_11 when (b6_14='1' and b6_2='0') else + b6_12 when (b6_14='0' and b6_2='1') else + b6_13; + +----------------------------------------------------------------------------- +-- IMAGE READ: X-Y AXIS IMAGE READ CONTROL - bit 1 processing -- +-- C6, 74153 -- +-- 4-line to 1-line data selector/multiplexor -- +-- (a,b) select c0 to c3 -- +-- (0,0):c0=>y, (0,1):c1=>y, (1,0):c2=>y, (1,1):c3=>y -- +-- -- +-- For overall logic refer to A6 -- +----------------------------------------------------------------------------- +c6_10 <= MemBrd_H; -- data input 2C0 rocket horizontal bit 1 +c6_11 <= MemBrd_J; -- data input 2C1 rocket vertical bit 1 +c6_12 <= MemBrd_E; -- data input 2C2 saucer vertical bit 1 +c6_13 <= MemBrd_F; -- data input 2C3 saucer horizontal bit 1 + +c6_6 <= c6_11 ; -- data input 1C0 rocket vertical bit 1 +c6_5 <= c6_10; -- data input 1C1 rocket horizontal bit 1 +c6_4 <= c6_13; -- data input 1C2 saucer horizontal bit 1 +c6_3 <= c6_12; -- data input 1C3 saucer vertical bit 1 + +c6_14 <= c5_3; -- A select INPUT +c6_2 <= f4_8; -- B select INPUT depends on saucer enable + +c6_7 <= -- output y1 + c6_6 when (c6_14='0' and c6_2='0') else + c6_5 when (c6_14='1' and c6_2='0') else + c6_4 when (c6_14='0' and c6_2='1') else + c6_3; + +c6_9 <= -- output y2 + c6_10 when (c6_14='0' and c6_2='0') else + c6_11 when (c6_14='1' and c6_2='0') else + c6_12 when (c6_14='0' and c6_2='1') else + c6_13; + +----------------------------------------------------------------------------- +-- IMAGE READ: X-Y AXIS IMAGE READ CONTROL - bit 0 processing -- +-- D6, 74153 -- +-- 4-line to 1-line data selector/multiplexor -- +-- (a,b) select c0 to c3 -- +-- (0,0):c0=>y, (0,1):c1=>y, (1,0):c2=>y, (1,1):c3=>y -- +-- -- +-- For overall logic refer to A6 -- +----------------------------------------------------------------------------- +d6_10 <= MemBrd_8; -- data input 2C0 rocket horizontal bit 0 +d6_11 <= MemBrd_9; -- data input 2C1 rocket vertical bit 0 +d6_12 <= MemBrd_6; -- data input 2C2 saucer vertical bit 0 +d6_13 <= MemBrd_7; -- data input 2C3 saucer horizontal bit 0 + +d6_6 <= d6_11 ; -- data input 1C0 rocket vertical bit 0 +d6_5 <= d6_10; -- data input 1C1 rocket horizontal bit 0 +d6_4 <= d6_13; -- data input 1C2 saucer horizontal bit 0 +d6_3 <= d6_12; -- data input 1C3 saucer vertical bit 0 + +d6_14 <= c5_3; -- A select INPUT +d6_2 <= f4_8; -- B select INPUT depends on saucer enable + +d6_7 <= -- output y1 + d6_6 when (d6_14='0' and d6_2='0') else + d6_5 when (d6_14='1' and d6_2='0') else + d6_4 when (d6_14='0' and d6_2='1') else + d6_3; + +d6_9 <= -- output y2 + d6_10 when (d6_14='0' and d6_2='0') else + d6_11 when (d6_14='1' and d6_2='0') else + d6_12 when (d6_14='0' and d6_2='1') else + d6_13; + +----------------------------------------------------------------------------- +-- IMAGE READ LOGIC: ROCKET IMAGE SELECTOR -- +-- E2, 74153 -- +-- 4-line to 1-line data selector/multiplexor -- +-- with strobe logic, to select output pin 9 and/or pin 7 -- +-- -- +-- Logic to determine which rocket diode image to use (to send to screen). -- +-- In the design the "image read direction" and "axis setup" operate -- +-- on all four images simultaneously - and the final stage is to select -- +-- which image to use (rather than selecting image first, and then apply -- +-- direction and axis logic). -- +-- Please refer to comment section "GENERAL INFORMATION" above regarding -- +-- how rocket orientation position drives selection of base image. -- +-- -- +-- Current image bit from all four rocket diode images are sent -- +-- simultaneously to the multiplexor -- +-- a and b selectors (e2_14 and e2_1) determine which image to output -- +-- The selectors are fed by bit 0 and bit 1 (00, 01, 10, 11) from the -- +-- image counter (E4, 74193). -- +-- Strobe g1 and g2 (e2_15 and e2_2) are used to select whether images -- +-- are output straight (00=image 0, 01=image 1, 10=image 2, 11=image 3) or -- +-- "reversed" (00=image 3, 01=image 2, 10=image 1, 11=image 0). -- +-- The strobes are fed by bit 3 from the image counter (E4, 74193) -- +-- as straight and as inverse (which keep images output mutually switched -- +-- on/off). -- +-- As the image bits are mirrored/reversed on one of the data inputs -- +-- and straight on the other data inputs, selecting one or the other -- +-- input to have active output achives the effect of "reversing" image. -- +-- -- +-- output from E4 74193 to control image selection -- +-- QD QC QB QA Image to output -- +-- e4_7 e4_6 e4_2 e4_3 (e9_9 and e_7) -- +-- X 0 0 0 0 -- +-- X 0 0 1 1 -- +-- X 0 1 0 2 -- +-- X 0 1 1 3 -- +-- X 1 0 0 3 -- +-- X 1 0 1 2 -- +-- X 1 1 0 1 -- +-- X 1 1 1 0 -- +----------------------------------------------------------------------------- +e2_10 <= diode_image3_bit; -- image input in normal order 0->3 +e2_11 <= diode_image2_bit; -- image input in normal order 0->3 +e2_12 <= diode_image1_bit; -- image input in normal order 0->3 +e2_13 <= diode_image0_bit; -- image input in normal order 0->3 + +e2_3 <= e2_10; -- image input in "reverse" order 3->0 +e2_4 <= e2_11; -- image input in "reverse" order 3->0 +e2_5 <= e2_12; -- image input in "reverse" order 3->0 +e2_6 <= e2_13; -- image input in "reverse" order 3->0 + +e2_14 <= e4_3; -- a select +e2_2 <= e4_2; -- b select + -- controlling which image to output + +e2_1 <= e4_6; -- logic for choosing either normal image read +h2_10 <= not e4_6; -- or +e2_15 <= h2_10; -- reversed image read + + +e2_7x <= -- output y1; normal image read/output + e2_6 when (e2_14='0' and e2_2='0') else + e2_5 when (e2_14='1' and e2_2='0') else + e2_4 when (e2_14='0' and e2_2='1') else + e2_3; + +e2_7 <= e2_7x and (not e2_1); -- strobe from pin 1, active low + +e2_9x <= -- output y2; "reversed" image read/output + e2_10 when (e2_14='0' and e2_2='0') else + e2_11 when (e2_14='1' and e2_2='0') else + e2_12 when (e2_14='0' and e2_2='1') else + e2_13; + +e2_9 <= e2_9x and (not e2_15); -- strobe from pin 15, active low + +----------------------------------------------------------------------------- +-- Video Out Logic -- +----------------------------------------------------------------------------- +e1_10 <= e2_9 nor e2_7; -- merging normal image read and reversed + -- image read + -- as they are mutually on/off + -- the images can never be in conflict + +e1_13 <= MemBrd_10 nor e1_10; -- only displaying rocket if it is enabled + -- MemBrd_10 is "rocket enable", which + -- is active low when the TV beam is + -- passing by any of the pixel's screen + -- positions in the rocket's 16x16 image grid + -- and rocket is allowed to be displayed (not + -- directly after collision/explosion or + -- game is not playing) + +h2_8 <= not e1_13; -- inverting to get signal chain correct + +e5_3 <= h2_8 nand c5_6; -- merging with saucer image output + +MemBrd_P <= e5_3; -- Resulting video out, saucer or rocket + -- pixel level + +----------------------------------------------------------------------------- +-- Rotation Circuitry: Rotation input logic -- +-- Rotation input logic - incl sending rotation signal to sound unit -- +----------------------------------------------------------------------------- +-- 7450 : rotate_clock_wise +f6_8 <= not ((explosion_rotate_clk and MemBrd_R) or + (thrust_and_rotate_clk and MemBrd_M)); + +-- 7400 : rotate_counter_clock_wise +e5_6 <= thrust_and_rotate_clk nand MemBrd_N; + +-- 7402 +e6_4 <= not (MemBrd_N nor MemBrd_M); + +-- simplified output to audio, do not need other freq input +-- as the audio is generated from audio samples +-- in this case K1 only triggers a sample. +-- otherwise include logic as per schematics to +-- get sound frequency input via e6_13. +e6_1 <= e6_4; +MemBrd_K1 <= e6_1; + +----------------------------------------------------------------------------- +-- Rocket orientation register: Keep & update rocket orientation -- +-- E4, 74193 -- +-- synchronous 4-bit up/down counter (dual clock with clear) -- +-- binary counter -- +-- Implemented as a state machine to makes things easy to get carry -- +-- and borrow behaving properly on clock edges -- +-- -- +-- OVERALL: -- +-- The rocket can be in any of 32 positions. The current rocket position -- +-- is stored as two parameters; one flag (right / left) and a position -- +-- number (0 to 15). -- +-- -- +-- This counter holds the position number 0-15, and can move in one step -- +-- increments (up/down) between the numbers -- +-- -- +-- When the counter reaches 15 and is increased by 1, the right/left flag -- +-- changes direction from right to left (or left to right) and the counter -- +-- is reset to 0. Similar logic follows when the counter reaches 0 and -- +-- is decreaed by 1; direction change + reset to 15. -- +-- -- +-- Counter value: 0000 -> 1111 (0-15) -- +-- Represents which position the rocket is in for either 0-180 degrees -- +-- or 180-360 degrees. -- +-- The carry/borrow bits that are set as the counter moves between -- +-- 0000 and 1111 are used to set a flag (flip-flop) that indicates -- +-- whether the rocket is in sector 0-180 degrees or 180-360 degrees -- +-- -- +-- Counter specifics: -- +-- clear not used -- +-- loadn not used -- +-- Data inputs not used -- +-- +1 occurs on count up rising edge, and count_down is high -- +-- carry goes from high to low when falling edge of count_up -- +-- -1 occurs on count down rising edge, and count_up is high -- +-- borrow occurs on (goes low) on count down falling edge -- +----------------------------------------------------------------------------- +e4_4 <= e5_6; -- down clk needs to be active low +e4_5 <= f6_8; -- up clk needs to be active low + +process (super_clk) +begin +if rising_edge (super_clk) then + e4_4_old <= e4_4; + e4_5_old <= e4_5; + + case state is + when UNSIGNED_UP_DOWN => + e4_12 <= '1'; + e4_13 <= '1'; + if (e4_5_old = '0') and (e4_5 = '1') then + -- PRIO for UP clock rising edge of count up clock => need to + -- increment counter + if e4_count = 14 then + state <= READY_FOR_CARRY; + e4_count <= "1111"; + else + state <= UNSIGNED_UP_DOWN; + e4_count <= e4_count + 1; + end if; + elsif (e4_4_old = '0') and (e4_4 = '1') then + -- rising edge of count down clock => need to decrease counter + if e4_count = 1 then + state <= READY_FOR_BORROW; + e4_count <= "0000"; + else + state <= UNSIGNED_UP_DOWN; + e4_count <= e4_count - 1; + end if; + end if; + + when READY_FOR_CARRY => -- e4_count is "1111" + e4_12 <= '1'; + e4_13 <= '1'; + if (e4_5_old = '1') and (e4_5 = '0') then + -- PRIO for UP clock falling edge of count up clock => need to set + -- carry flag + e4_12 <= '0'; -- setting carry flag + state <= CARRY; + elsif (e4_4_old = '0') and (e4_4 = '1') then + -- rising edge of count down clock => need to decrease counter + e4_count <= e4_count - 1; + state <= UNSIGNED_UP_DOWN; + end if; + + when READY_FOR_BORROW => -- e4_count is "0000" + e4_12 <= '1'; + e4_13 <= '1'; + if (e4_5_old = '0') and (e4_5 = '1') then + -- PRIO for UP clock; rising edge of count UP clock => need to + -- increase counter + e4_count <= e4_count + 1; + state <= UNSIGNED_UP_DOWN; + elsif (e4_4_old = '1') and (e4_4 = '0') then + -- falling edge of count down clock => need to set borrow flag + e4_13 <= '0'; -- setting borrow flag + state <= BORROW; + + end if; + + when CARRY => + e4_12 <= '0'; + e4_13 <= '1'; + if (e4_5_old = '0') and (e4_5 = '1') then + -- rising edge of count up clock => need to clear carry flag and + -- increment + e4_12 <= '1'; -- clear carry flag + e4_count <= "0000"; + state <= READY_FOR_BORROW; + end if; + + when BORROW => + e4_12 <= '1'; + e4_13 <= '0'; + if (e4_4_old = '0') and (e4_4 = '1') then + -- rising edge of count down clock => need to clear borrow flag and + -- decrease + e4_13 <= '1'; -- clear carry flag + e4_count <= "1111"; + state <= READY_FOR_CARRY; + end if; + + when others => + e4_12 <= '1'; + e4_13 <= '1'; + state <= UNSIGNED_UP_DOWN; + e4_count <= "0000"; + + end case; +end if; +end process; + +e4_2 <= e4_count(1); -- Qb +e4_3 <= e4_count(0); -- Qa +e4_6 <= e4_count(2); -- Qc +e4_7 <= e4_count(3); -- Qd + +----------------------------------------------------------------------------- +-- Rocket orientation register: Indicate move fr. right to left or reverse -- +-- Bridge from up/down counter to flip flop -- +-- Signals when to move between 0<-<180 and 180<-<360 degree sectors -- +-- which is equivalent to whether rocket is pointing to the right or to -- +-- the left. -- +----------------------------------------------------------------------------- +e5_8 <= e4_13 nand e4_12; -- merges carry and borrow to signal + -- the rocket has moved between 0<-<180 and + -- 180<-<360 degree sectors + -- (changing left-to-right or right-to-left) + +----------------------------------------------------------------------------- +-- Rocket orientation register: Set right-left flag -- +-- E3 7476 -- +-- Flip flop that acts as a flag to indicate whether the rocket is -- +-- pointing to the right (0<-<180 degrees)or -- +-- to the left (180<-<360 degrees) -- +-- -- +-- e3_14: -- +-- 0 - rocket pointing to the left -- +-- 1 - rocket pointing to the right -- +-- -- +-- e3_15: -- +-- 0 - rocket pointing to the right -- +-- 1 - rocket pointing to the left -- +----------------------------------------------------------------------------- +e3_1 <= e5_8; + +process (super_clk) +begin +if rising_edge (super_clk) then + e3_1_old <= e3_1; + if (e3_1_old = '1') and (e3_1 = '0') then + -- falling edge, j and k permanent high => toggle + e3_15 <= not e3_15; + e3_14 <= not e3_14; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- IMAGE READ LOGIC: Determine Image Read Direction -- +-- Logic to determine when to read the diode images "left to right" and -- +-- when to read the diode images "right to left". -- +-- Please refer to comment section "GENERAL INFORMATION" above regarding -- +-- how rocket orientation position drives image read direction. -- +-- -- +-- c5_11: -- +-- '0' read image "left to right" -- +-- '1' reads "right to left" (inverting read line input) -- +----------------------------------------------------------------------------- +f4_10 <= not e4_7; +e5_11 <= f4_10 nand e4_6; -- For rocket: + -- determines whether + -- the rocket is in range: + -- 45< - <90 degrees or + -- 225< - <270 degrees + -- to give it value '0' + -- all other angels are giving value '1' + +d5_11 <= e5_11 xor e3_15; -- For rocket: + -- all angels in range <0 - <180 degrees + -- maintains it read direction value + -- otherwise the value is inversed. + -- this results in angels 45< - <90 degrees, + -- 180< - <225 degrees, 270< - <360 degrees + -- are being read "right to left" + +c5_11 <= d5_11 nand MemBrd_K; -- if saucer is being drawn + -- (saucer video enabled: MemBrd_K) then + -- default read direction required by + -- saucer image (right to left) is set + -- otherwise d5_11 signal is inversed + +----------------------------------------------------------------------------- +-- IMAGE READ LOGIC: Determine Image Activation Direction -- +-- Logic to determine when to activate the diode images top-to-botton and -- +-- when to activate images bottom-to-top. -- +-- Please refer to comment section "GENERAL INFORMATION" above regarding -- +-- how rocket orientation position drives activation direction -- +-- -- +-- c5_8: -- +-- '1' activates image "top to bottom" via 74154 -- +-- '0' activates "bottom to top" via 74154 by inverting activation line -- +-- input. -- +----------------------------------------------------------------------------- +e6_10 <= e4_7 nor e4_6; -- For rocket: + -- verify if image no is 0-3 (out of 0-15); + -- which could be either first four images + -- in 0< - <45 degrees + -- or first four images 180< - <225 degrees + +d5_8 <= e3_15 xor e6_10; -- For rocket: + -- excludes 180< - < 225 degrees + -- and adds 225< - <360 degrees + -- this is done via e3_15 + -- e3_15 = '1' means images are in range: + -- 180< - <360 degrees. + -- Result is that rocket pointing: + -- 0< - <45 degrees or 225< - <360 degrees + -- is read Top to Bottom. + -- Otherwise Bottom to Top. + +c5_8 <= MemBrd_K nand d5_8; -- if saucer is being drawn then default + -- activation direction required by saucer + -- image (bottom up) + -- otherwise signal is just inversed + +f4_4 <= not c5_8; -- re-inverses signal + -- to fit follow-on logic + +----------------------------------------------------------------------------- +-- IMAGE READ LOGIC: Determine Activation and Read Axis -- +-- Logic to determine whether the horizontal diode image slices are read -- +-- as horizontal slices onto screen OR the vertical diode image slices -- +-- are read as horizontal image slices onto screen -- +-- Please refer to comment section "GENERAL INFORMATION" above regarding -- +-- how rocket orientation position drives axis setup -- +-- -- +-- c5_3: -- +-- '0': Reading the diode image’s horizontal slices (rows) as horizontal -- +-- slices (rows) onto screen -- +-- '1' Reading the diode image’s vertical slices (columns) as -- +--- horizontal slices (rows) onto screen -- +----------------------------------------------------------------------------- +d5_3 <= e4_6 xor e4_7; -- For rocket: + -- whenever image no is between 4 - 11 + -- meaning 45< - <135 degree or + -- 225< - <315 degrees + -- d5_3 is set to use the horizontal part of + -- the diode matrix as the "on screen" + -- horizontal part OR the vertical part + -- of the diode matrix as the "on screen" + -- horizontal part + -- '0' activates diode matrix row by row and + -- and for each row read pixel by pixel => + -- horizontal images slices are read onto + -- screen as horizontal slices + -- '1' activates diode matrix row and reads + -- pixel in current column, and move through + -- all rows in this manner until all pixels + -- for a column is read, then repeat this + -- process column by column => vertical image + -- slices are read onto screen as horizontal + -- slices + +c5_3 <= MemBrd_K nand d5_3; -- if saucer is being drawn then default to + -- activation/read axis required by saucer + -- image:read vertical diode part as + -- horizontal + -- - which is easy to realize just by looking + -- at the 90 degree tilted saucer diode + -- image on the schematics + -- Otherwise signal is just inversed for rocket + -- to comply with down stream logic needs. + +----------------------------------------------------------------------------- +-- Rocket North/South/West/East Indicator: D5_6 -- +-- Determine whether the rocket is oriented (pointing) very close to -- +-- 0 degrees, 90 degrees, 180 degrees, or 270 degrees -- +-- within two positions on each side of each main direction -- +-- using bit 1 and bit 2 of the image position counter -- +----------------------------------------------------------------------------- +d5_6 <= e4_2 xor e4_6; -- 0: very close to 0, 90, 180 or 270 degrees + -- 1: not very close to 0, 90, 180 or 270 degrees + +----------------------------------------------------------------------------- +-- THRUST CIRCUITRY: Create thrust pulse train -- +-- when thrust button is pressed, create a pulse train that controls -- +-- how fast the rocket's engine flame pulsates, and how fast the rocket's -- +-- velocity level change (gives the feeling of acceleration/deceleration) -- +----------------------------------------------------------------------------- +f3_6 <= not (MemBrd_S and thrust_and_rotate_clk) ; + +----------------------------------------------------------------------------- +-- THRUST CIRCUITRY: audio -- +-- signal to create thrust sound when thrust button is pressed -- +-- not a true implementation of the original schematics -- +-- as this implementation relies on sampled audio and only needs "button -- +-- press" signal (and no audio frequency) -- +----------------------------------------------------------------------------- +membrd_K2 <= MemBrd_S; -- thrust audio + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Keep and Update Velocity Level -- +-- 74193 -- +-- Aynchronous 4-bit up/down counter (dual clock with clear) -- +-- Binary counter -- +-- Counter to hold the current velocity level value, and to increase or -- +-- decrease the value when told to do so -- +-- j4_3 (bit0), j4_2 (bit 1), j4_6 (bit 2) represent the 3 bit -- +-- velocity level -- +-- j4_7 (bit 3=) represents direction left or right -- +-- 0 - left / 1 - right -- +-- -- +-- Counting up - decreases rightbound/increases leftbound velocity -- +-- Counting down - increases rightbound/decreases leftbound velocity -- +-- When velocity is (0)000 and counting down, the counter flips to (1)111 -- +-- velocity levels gets "reversed/flipped" for rightbound velocity -- +-- j4_7 = 0 (left); 000 means no velocity and 111 means max velocity -- +-- j4_7 = 1 (right); 111 means no velocity and 000 means max velocity -- +-- -- +-- Please note that left/right values are inversed as they reach the -- +-- Motion Board's Rocket Motion unit (0 = right, 1 = left) to fit the -- +-- Motion Logic -- +----------------------------------------------------------------------------- +j4_4 <= j3_6; -- count down (decrease) +j4_5 <= j3_8; -- count up (increase) + +process (super_clk) +begin +if rising_edge (super_clk) then + j4_4_old <= j4_4; + j4_5_old <= j4_5; + if (j4_4_old = '0') and (j4_4 = '1') and (j4_5 = '1') then + j4_count <= j4_count-1; + elsif (j4_5_old = '0') and (j4_5 = '1') and (j4_4 = '1') then + j4_count <= j4_count+1; + end if; +end if; +end process; + +j4_2 <= j4_count(1); -- Qb +j4_3 <= j4_count(0); -- Qa +j4_6 <= j4_count(2); -- Qc +j4_7 <= j4_count(3); -- Qd + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Velocity Level "Harmonization" -- +-- -- +-- j4_3 (bit0), j4_2 (bit 1), j4_6 (bit 2) represent the 3 bit -- +-- velocity level -- +-- j4_7 represents direction left or right, and due to the use of counter -- +-- the velocity levels gets "reversed/flipped" for rightbound velocity -- +-- j4_7 = 0 (left); 000 means no velocity and 111 means max velocity -- +-- j4_7 = 1 (right); 111 means no velocity and 000 means max velocity -- +-- -- +-- By applying XOR logic with the direction signal j4_7, the velocity -- +-- level is "harmonized" so that direction does not matter -- +-- and 000 means no velocity and 111 means max velocity -- +----------------------------------------------------------------------------- +j5_6 <= j4_3 xor j4_7; +j5_11 <= j4_2 xor j4_7; +j5_3 <= j4_6 xor j4_7; + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Output Velocity Level and Direction -- +-- 000 represents zero motion and 111 is maximum velocity -- +-- -- +-- Please note that left/right values are inversed as they reach the -- +-- Motion Board's Rocket Motion unit (0 = right, 1 = left) to fit the -- +-- Motion Logic -- +----------------------------------------------------------------------------- +MemBrd_14 <= j5_6; -- velocity bit 0 +MemBrd_13 <= j5_11; -- velocity bit 1 +MemBrd_15 <= j5_3; -- velocity bit 3 +MemBrd_16 <= j4_7; -- (0)Left /(1)Right + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Max Rightbound Velocity Level Flag -- +-- Logic to flag when max velocity level has been reached -- +-- Flag is used to stop velocity counter from being further decreased -- +-- (for rightbound velocity; decrease counter increases velocity) -- +----------------------------------------------------------------------------- +j6_6 <= not ( j5_6 and j5_11 and j5_3 and j4_7); -- when velocity level is + -- 111 and direction is + -- to the right, + -- then flag is set + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Max Leftbound Velocity Level Flag -- +-- Logic to flag when max velocity level has been reached -- +-- Flag is used to stop velocity counter from being further increased -- +----------------------------------------------------------------------------- +inv_4 <= not j4_7; -- no markings on + -- schematics, call it + -- inv_4 + +j6_8 <= not ( j5_6 and j5_11 and j5_3 and inv_4); -- when velocity level is + -- 111 and direction is + -- to the left, + -- then flag is set + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Incr Leftb Velocity/Decr. Rightb velocity -- +-- Sends signal to decrease rightbound velocity until rocket has no right -- +-- bound motion and increase leftbound velocity until max velocity has -- +-- been reached. -- +-- Decreasing velocity in one direction can only be achieved by applying -- +-- thrust in opposite direction. -- +-- Thrust only has impact if the rocket is pointing to the left -- +-- (180-360 deg.) but is not pointing very close to north/south. -- +-- Logically j3_8 sends signal to velocity counter to increase the counter -- +-- value. -- +----------------------------------------------------------------------------- +j3_8 <= not ( j6_8 and e3_15 and j2_10); -- j6_8: flag that indicates + -- whether max velocity has been + -- reached or not. If max velocity + -- then it prevents further + -- increase + -- e3_15: right/left flag + -- active and allowing for + -- increse in velocity only + -- when set to "left" (1) + -- j2_10: pulse that gives the + -- pace with which the velocity + -- can change (acceleration/ + -- deceleration) - pulsating + -- when thrust button is pressed + -- and rocket is not pointing + -- very close to north/south + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Incr Rightb Velocity/Decr. Leftb velocity -- +-- Sends signal to decrease Leftbound velocity until rocket has no left -- +-- bound motion and increase Rightbound velocity until max velocity has -- +-- been reached. -- +-- Decreasing velocity in one direction can only be achieved by applying -- +-- thrust in opposite direction. -- +-- Thrust only has impact if the rocket is pointing to the right -- +-- (0-180 deg.) but not pointing very close to north/south -- +-- -- +-- Logically j3_6 sends signal to velocity counter to decrease the -- +-- counter value -- +----------------------------------------------------------------------------- +j3_6 <= not (j6_6 and j2_10 and e3_14); -- j6_6: flag that indicates + -- whether max velocity has been + -- reached or not. If max velocity + -- then it prevents further + -- counter decrease + -- e3_14: right/left flag + -- active and allowing for + -- increse in velocity only + -- when set to "right"(1) + -- j2_10: pulse that gives the + -- pace with which the velocity + -- can change (acceleration/ + -- deceleration) - pulsating + -- when thrust button is pressed + -- and rocket is not pointing + -- very close to north/south + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Horizontal Thrust Pulse -- +-- Pulse that gives the pace with which the velocity can change -- +-- (acceleration/ deceleration). -- +-- only pulses as long as rocket is not pointing very close to either -- +-- north or south -- +-- f5_13 NOR f3_6 -- +-- 00:1 -- +-- 01:0 -- +-- 10:0 -- +-- 11:0 -- +-- when f5_13=1 then the rocket is pointing very close to either north -- +-- or south, the rocket is not seen as being able to create any -- +-- horizontal thrust, and consequently no pulse is allowed -- +-- when f5_13=0 then thrust pulse is allowed -- +-- The resulting thrust pulse is inverted, but it does not matter -- +-- f3_6 is a continuous pulse train - when the thrust button is pressed -- +----------------------------------------------------------------------------- +j2_10 <= f5_13 nor f3_6; + +----------------------------------------------------------------------------- +-- Horizontal Rocket Velocity: Near North/South Direction F5_13 -- +-- Determines when the rocket is pointing very close to north/south or -- +-- not. -- +-- "Very close" is within 2 positions from north/south -- +-- Is used to determine whether thrust should have impact on horizontal -- +-- velocity or not -- +-- "Input": -- +-- d5_3 flag is active when rocket is pointing in either: -- +-- 45-135 degrees or 225 - 315 degrees -- +-- d5_6 flag is "active low" whenever the rocket is pointing very close to -- +-- either side of: north, south, east or west -- +-- "Output": -- +-- Combining these flags with NOR gives: -- +-- 1: when rocket is pointing very close to north or south -- +-- 0: when rocket is pointing in any direction except -- +-- for very close to north or south (then thrust is allowed to impact -- +-- horizontal velocity) -- +----------------------------------------------------------------------------- +f5_13 <= d5_6 nor d5_3; + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Keep and Update Velocity Level -- +-- 74193 -- +-- Aynchronous 4-bit up/down counter (dual clock with clear) -- +-- Binary counter -- +-- Counter to hold the current velocity level value, and to increase or -- +-- decrease the value when told to do so -- +-- h4_3 (bit0), h4_2 (bit 1), h4_6 (bit 2) represent the 3 bit -- +-- velocity level -- +-- h4_7 (bit 3=) represents direction up or down -- +-- 0 - up / 1 - down -- +-- -- +-- Counting up - decreases downward/increases upward velocity -- +-- Counting down - increases downward/decreases upward velocity -- +-- When velocity is (0)000 and counting down, the counter flips to (1)111 -- +-- velocity levels gets "reversed/flipped" for downward velocity -- +-- h4_7 = 0 (up); 000 means no velocity and 111 means max velocity -- +-- h4_7 = 1 (down); 111 means no velocity and 000 means max velocity -- +-- -- +-- Please note that up/down values are inversed as they reach the Motion -- +-- Board's Rocket Motion unit (0 = down, 1 = up) to fit the Motion Logic -- +----------------------------------------------------------------------------- +h4_4 <= h3_6; -- count down (decrease) +h4_5 <= h3_8; -- count up (increase) + +process (super_clk) +begin +if rising_edge (super_clk) then + h4_4_old <= h4_4; + h4_5_old <= h4_5; + if (h4_4_old = '0') and (h4_4 = '1') and (h4_5 = '1') then + h4_count <= h4_count-1; + elsif (h4_5_old = '0') and (h4_5 = '1') and (h4_4 = '1') then + h4_count <= h4_count+1; + end if; +end if; +end process; + +h4_2 <= h4_count(1); -- Qb +h4_3 <= h4_count(0); -- Qa +h4_6 <= h4_count(2); -- Qc +h4_7 <= h4_count(3); -- Qd + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Near East/West Direction F5_10 -- +-- Determines when the rocket is pointing very close to east/west or not. -- +-- "Very close" is within 2 positions from east/west -- +-- Is used to determine whether thrust should have impact on vertical -- +-- velocity or not -- +-- "Input": -- +-- f4_12 flag is active when rocket is pointing in either: -- +-- 315< - <45 degrees or 135< - <225 degrees -- +-- d5_6 flag is "active low" whenever the rocket is pointing very close to -- +-- either side of: north, south, east or west -- +-- "Output": -- +-- Combining these flags with NOR gives: -- +-- 1: when rocket is pointing very close to east or west -- +-- 0: when rocket is pointing in any direction except -- +-- for very close to east or west (then thrust is allowed to impact -- +-- vertical velocity) -- +----------------------------------------------------------------------------- +f5_10 <= d5_6 nor f4_12; + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Vertical Thrust Pulse -- +-- Pulse that gives the pace with which the velocity can change -- +-- (acceleration/ deceleration). -- +-- only pulses as long as rocket is not pointing very close to either -- +-- east or west -- +-- f5_10 NOR f3_6 -- +-- 0 0 => 1 -- +-- 0 1 => 0 -- +-- 1 0 => 0 -- +-- 1 1 => 0 -- +-- when f5_10=1 then the rocket is pointing very close to either east -- +-- or west and the rocket is not seen as being able to create any -- +-- vertical thrust, and consequently no pulse is allowed -- +-- when f5_10=0 then thrust pulse is allowed -- +-- The resulting thrust pusle is inverted, but it does not matter -- +-- f3_6 is a continuous pulse train - when the thrust button is pressed -- +----------------------------------------------------------------------------- +j2_13 <= f3_6 nor f5_10; + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Velocity Level "Harmonization" -- +-- -- +-- h4_3 (bit0), h4_2 (bit 1), h4_6 (bit 2) represent the 3 bit -- +-- velocity level -- +-- h4_7 represents direction up or down, and due to the use of counter -- +-- the velocity levels gets "reversed/flipped" for downward velocity -- +-- h4_7 = 0 (up); 000 means no velocity and 111 means max velocity -- +-- h4_7 = 1 (down); 111 means no velocity and 000 means max velocity -- +-- -- +-- By applying XOR logic with the direction signal h4_7, the velocity -- +-- level is "harmonized" so that direction does not matter -- +-- and 000 means no velocity and 111 means max velocity -- +----------------------------------------------------------------------------- +h5_6 <= h4_3 xor h4_7; +h5_11 <= h4_2 xor h4_7; +h5_3 <= h4_6 xor h4_7; + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Output Velocity Level and Direction -- +-- 000 represents zero motion and 111 is maximum velocity -- +-- -- +-- Please note that up/down values are inversed as they reach the Motion -- +-- Board's Rocket Motion unit (0 = down, 1 = up) to fit the Motion Logic -- +----------------------------------------------------------------------------- +MemBrd_W <= h5_6; -- velocity bit 0 +MemBrd_V <= h5_11; -- velocity bit 1 +MemBrd_X <= h5_3; -- velocity bit 3 +MemBrd_Y <= h4_7; -- Up(0) / Down(1) + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Max Downward Velocity Level Flag -- +-- Logic to flag when max velocity level has been reached -- +-- Flag is used to stop velocity counter from being further decreased -- +-- (for downward velocity: counter decrease => increases velocity) -- +----------------------------------------------------------------------------- +h6_6 <= not ( h5_6 and h5_11 and h5_3 and h4_7); -- when velocity level is + -- 111 and direction is + -- downwards, + -- then flag is set + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Max Upward Velocity Level Flag -- +-- Logic to flag when max velocity level has been reached -- +-- Flag is used to stop velocity counter from being further increased -- +----------------------------------------------------------------------------- +h2_2 <= not h4_7; +h6_8 <= not ( h5_6 and h5_11 and h5_3 and h2_2); -- when velocity level is + -- 111 and direction is + -- upwards, + -- then flag is set + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Incr Downw. Velocity / Decr. Upward velocity -- +-- Sends signal to decrease upward velocity until rocket has no upward -- +-- motion and increase downward velocity until max velocity has been -- +-- reached. -- +-- Decreasing velocity in one direction can only be achieved by applying -- +-- thrust in opposite direction. -- +-- Thrust only has impact if the rocket is pointing downwards (90-270 deg) -- +-- but is not pointing very close to east/west. -- +-- Logically h3_6 send signal to velocity counter to decrease the counter -- +-- value -- +----------------------------------------------------------------------------- +h3_6 <= not (h6_6 and j2_13 and j5_8); -- h6_6: flag that indicates + -- whether max velocity has been + -- reached or not. If max velocity + -- then it prevents further + -- velocity increase + -- j5_8: up/down flag + -- active and allowing for + -- increse in velocity only + -- when set to "down" (1) + -- j2_13: pulse that gives the + -- pace with which the velocity + -- can change (acceleration/ + -- deceleration) - pulsating + -- when thrust button is pressed + -- and rocket is not pointing + -- very close to east or west + +----------------------------------------------------------------------------- +-- Vertical Rocket Velocity: Incr Upward Velocity / Decr. Downw. Velocity -- +-- Sends signal to decrease downward velocity until rocket has no down -- +-- ward motion and increase upward velocity until max velocity has been -- +-- reached. -- +-- Decreasing velocity in one direction can only be achieved by applying -- +-- thrust in opposite direction. -- +-- Thrust only has impact if the rocket is pointing downwards (270-90 deg) -- +-- but is not pointing very close to east/west. -- +-- Logically h3_8 sends signal to velocity counter to increase the counter -- +-- value -- +----------------------------------------------------------------------------- +h2_12 <= not j5_8; -- j5_8: flag that indicates + -- whether rocket is pointing + -- upwards or downwards + -- 0 - up, 1 - down + -- h2_12 is inversing to fit + -- follow on logic requirement + -- that UP is active high (1) + +h3_8 <= not (h6_8 and h2_12 and j2_13); -- h6_8: flag that indicates + -- whether max velocity has been + -- reached or not. If max velocity + -- then it prevents further + -- velocity increase + -- h2_12: up/down flag + -- active and allowing for + -- increse in velocity only + -- when set to "up" (1) + -- j2_13: pulse that gives the + -- pace with which the velocity + -- can change (acceleration/ + -- deceleration) - pulsating + -- when thrust button is pressed + -- and rocket is not pointing + -- very close to east or west + +----------------------------------------------------------------------------- +-- ROCKET MISSILE DIRECTION LOGIC: Determine rocket missile direction -- +-- up / down AND left / right -- +-- used for rocket missile launch angle and manouvering post launch -- +----------------------------------------------------------------------------- +MemBrd_12 <= j5_8; -- Missile Up or Down + -- 0 = Up / 1 = Down + +MemBrd_17 <= e3_14; -- Missile Right or Left (0-180dg vs 180-360 dg) + -- e3_14 is the inverse of e3_15 + -- 0 = Left / 1 = Right + +----------------------------------------------------------------------------- +-- ROCKET MISSILE DIRECTION LOGIC: Rocket missile direction -- +-- Determines which direction the rocket missile should move in. The -- +-- direction is dependent on the direction in which the rocket is -- +-- pointing. In summary: -- +-- 1) Straight up/down or right/left missile motion when the rocket is -- +-- pointing very close to north/south or west/east. At speed of one pixel -- +-- per every 1/60 second -- +-- 2) â€45 degree†(or equivalent 135 / 215 / 305) motion when the rocket -- +-- is pointing close to 45 degree (or equivalent). At speed of one pixel -- +-- per every 1/60 second -- +-- 3) 22,5/157,5/212.5/342.5 degree motion when rocket is close to those -- +-- angels. At one pixel per every 1/60 second in vertical direction -- +-- and one pixel per every 1/30 second in horizontal direction -- +-- 4) 67,5/112.5/257.5/302.5 degree motion when rocket is close to those -- +-- angels. At one pixel per every 1/30 second in vertical direction and -- +-- one pixel per every 1/60 second in horizontal direction -- +-- -- +-- The rocket missile direction is changing as the rocket orientation -- +-- is changing - allowing for rocket missile manouverability -- +-- -- +-- One input lacks marking on the one player schematics, -- +-- but looking at the 2-player schematics concludes this is tapping from -- +-- motionboard B (MB_B) (ref MemBrd_11) -- +-- MB_B is a pulse train which goes high/low with half the screen refresh -- +-- freq: 30 Hz -- +----------------------------------------------------------------------------- +f4_12 <= not d5_3; -- active low whenever rocket is + -- pointing: + -- 45< - <135 degrees or + -- 225< - <315 degrees + +-- h5_8 <= e4_2 nand e4_3; -- original schematics; wrong label + -- on gate; should be xor, not nand +h5_8 <= e4_2 xor e4_3; -- revised logic + -- indicates (low) when the rocket + -- is oriented, within one position, + -- to either side of the + -- 0/45/90/135/180/225/270/325 + -- degree-lines + -- otherwise high + +f4_6 <= not h5_8; -- indicates (high) when the rocket + -- is oriented, within one position, + -- to either side of the + -- 0/45/90/135/180/225/270/325 + -- degree-lines + -- otherwise low + +f6_6 <= not((h5_8 and MemBrd_11) -- pulses between two logical output + or (d5_6 and f4_6)); -- constructs at a rate of 30Hz + -- 1: indicate (high) when rocket is + -- oriented within one position to + -- either side of north, south, east + -- or west + -- otherwise low + -- 2: indicate (low) when rocket is + -- within one position to either side + -- of 45/135/225/325 degree lines + -- otherwise high + +f4_2 <= not f6_6; -- pulses between two logical output + -- constructs at a rate of 30Hz + -- 1: indicate (low) when rocket is + -- oriented within one position to + -- either side of north, south, east + -- or west + -- otherwise high + -- 2: indicate (high) when rocket is + -- within one position to either side + -- of 45/135/225/325 degree lines + -- otherwise low + +f5_4 <= f4_2 nor f4_12; -- Rocket is pointing: + -- 1) within one position + -- to either side of + -- east or west + -- => 1 + -- 2) ~61 - ~74 / ~105 - ~121 / + -- ~240 - ~253 / ~287 - ~300 + -- degrees + -- => switches between 1 and 0 + -- with a 30 Hz frequency + -- 3) ~300 < - < ~61 degrees or + -- ~121 < - < ~240 degrees + -- => 0 + +f5_1 <= f4_2 nor d5_3; -- Rocket is pointing: + -- 1) within one position + -- to either side of + -- north or south + -- => 1 + -- 2) ~16 - ~32 / ~151 - ~163 / + -- ~197 - ~209 / ~331 - ~343 + -- degrees + -- => switches between 1 and 0 + -- with a 30 Hz frequency + -- 3) ~32 < - < ~151 degrees or + -- ~209 < - < ~331 degrees + -- => 0 + +MemBrd_T <= f5_4; -- Rocket Missile Up/Down Enable + -- 0 - up/down allowed + -- 1 - up/down not allowed + -- Is either constantly + -- 1 or 0 or + -- switches between 1 and 0 + -- with a 30 Hz frequency + -- to allow for rocket + -- missile direction of: + -- 67,5/112.5/257.5/302.5 + -- degrees + +MemBrd_U <= f5_1; -- Rocket Missile Right/Left Enable + -- 0 - right/left allowed + -- 1 - right/left not allowed + -- Is either constantly + -- 1 or 0 or + -- switches between 1 and 0 + -- with a 30 Hz frequency + -- to allow for rocket + -- missile direction of + -- 22,5/157,5/212.5/342.5 + -- degrees + +----------------------------------------------------------------------------- +-- Determine rocket's main orientation -- +-- up / down and left / right -- +-- used for rocket's vertical/horizontal velocity acc/dec. -- +-- and for rocket missile launch angle and manouvering post launch -- +----------------------------------------------------------------------------- +j5_8 <= e3_15 xor e4_7; -- e3_15 signals whether 0-180 degrees or + -- 180-360 degrees (right or left pointing) + -- e4_7 signals whether 90-180 / 270-360 degrees + -- or 0-90 / 180-270 degrees + -- XOR gives UP when e3_15(0-180 degrees) meet + -- e4_7(0-90 degres) + -- or e3_15(180-360 degrees) meet e4_7(270-350dg) + -- otherwise DOWN + +end memory_board_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/mist_io.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/motion_board.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/motion_board.vhd new file mode 100644 index 00000000..617c37d2 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/motion_board.vhd @@ -0,0 +1,1476 @@ +----------------------------------------------------------------------------- +-- MOTION BOARD LOGIC -- +-- For use with Computer Space FPGA emulator. -- +-- Implementation of Computer Space's Motion Board -- +-- "wire by wire" and "component by component"/"gate by gate" based on -- +-- original schematics. -- +-- With exceptions regarding: -- +-- > analogue based timers (impl as counters) -- +-- > all flip flops / ICs using asynch clock inputs are replaced with -- +-- flip flops driven by a high freq clock and logic to -- +-- identify "logical clock edge" changes -- +-- > sound pulse trains used by the analogue sound unit are replaced by -- +-- on/off flags to trigger sound sample playback -- +-- -- +-- There are plenty of comments throughout the code to make it easier to -- +-- understand the logic, but due to the sheer number of comments there -- +-- may exist occasional mishaps. -- +-- -- +-- This entity is implementation agnostic -- +-- -- +-- Naming convention: -- +-- Signals are labelled after the component that generates the signal; -- +-- more specifically the component's schematics label and the specific -- +-- output. For instance: NOR gate F6 and its output pin 10 generate a -- +-- signal which will be labelled f6_10. -- +-- Occasionally signals are labelled after a component input - this is -- +-- most common for components where the input is exposed -- +-- to "component-internal processing" beyond simple gate functionality, -- +-- such as bistable latches, counters, flip-flops and multiplexers. -- +-- Motion Board inputs/outputs are labelled MB_, where is -- +-- according to original schematics input/output labels. -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library work; + +--80--------------------------------------------------------------------------| + +entity motion_board is + port ( + super_clk, -- Clock to emulate + -- asynch flip flop logic + + timer_base_clk : in std_logic; + rocket_missile_life_time_duration, + saucer_missile_life_time_duration, + saucer_missile_hold_duration, + signal_delay_duration : in integer; + + MB_3, -- rocket horizontal velocity: + -- speed bit 0 + MB_4, -- rocket horizontal velocity: + -- speed bit 2 + + MB_16, -- rocket missile + -- horizontal direction + -- 1- right, 0 - left + MB_17, -- rocket missile + -- horizontal (right/left) + -- speed + -- constant 1 - no speed + -- constant 0 - "60Hz" speed + -- pulse 0/1 at 30 Hz rate + -- gives "30 Hz" speed + + MB_18, -- rocket missile + -- vertical direction + -- 0 - up, 1 - down + MB_19, -- rocket missile + -- vertical (up / down) + -- speed + -- constant 1 - no speed + -- constant 0 - "60Hz" speed + -- (60 pixels / second) + -- pulse 0/1 at 30 Hz rate + -- gives "30 Hz" speed + -- (30 pixels / second) + + MB_20, -- game clock + MB_C, -- count enable + + MB_D, -- rocket horizontal velocity: + -- speed bit 1 + + MB_H, -- rocket up or down + -- 0 - up / 1 - down + MB_J, -- rocket right or left + -- 0 - left / 1- right + + MB_T, -- rocket vertical velocity: + -- speed bit 0 + MB_U, -- rocket vertical velocity: + -- speed bit 1 + MB_V, -- rocket vertical velocity: + -- speed bit 2 + + MB_Y -- rocket missile fire; + -- active when fire button + -- has been pressed + : in std_logic; + + MB_5, -- saucer 16x8 image's + -- horizontal position bit 2 + MB_6, -- saucer 16x8 image's + -- horizontal position bit 0 + MB_8, -- saucer 16x8 image's + -- vertical position bit 0 + MB_9, -- saucer 16x8 image's + -- vertical position bit 2 + + MB_10, -- saucer missile video + -- signals that the TV beam + -- is "sweeping" by the current + -- pixel position of an active + -- saucer missile + + MB_11, -- rocket 16x16 image's + -- horizontal position bit 2 + MB_12, -- rocket 16x16 image's + -- horizontal position bit 0 + MB_13, -- rocket 16x16 image's + -- vertical position bit 1 + MB_14, -- rocket 16x16 image's + -- vertical position bit 3 + MB_15, -- rocket 16x16 image's + -- vertical position bit 0 + + MB_21, -- Saucer Enable + -- signals that the TV beam + -- is "sweeping" by the current + -- position of one of the + -- two 16 x 8 + -- saucer image grids + -- The exact image pixel that + -- the TV beam is sweeping by + -- is provided by + -- horizontal pos bit 0-3: + -- MB_6, MB_F, MB_5, MB_E + -- vertical pos bit 0-3: + -- MB_8, MB_K, MB_9, MB_L + -- The information is used + -- by the Memory Board + -- to feed the correct + -- image pixel for further + -- video signal processing + -- at the sync star board + + MB_B, -- 30Hz frequency pulse train + -- used by Memory Board to create + -- Rocket missile motion + + MB_E, -- saucer 16x8 image's + -- horizontal position bit 3 + MB_F, -- saucer 16x8 image's + -- horizontal position bit 1 + MB_K, -- saucer 16x8 image's + -- vertical position bit 1 + MB_L, -- saucer 16x8 image's + -- vertical position bit 3 + + MB_N, -- rocket 16x16 image's + -- horizontal position bit 1 + MB_M, -- rocket 16x16 image's + -- horizontal position bit 3 + + MB_P, -- Rocket Missile Video + -- signals that the TV beam + -- is "sweeping" by the current + -- pixel position of an active + -- rocket missile + + MB_R, -- rocket 16x16 image's + -- vertical position bit 2 + + MB_W, -- Rocket Enable + -- signals that the TV beam + -- is "sweeping" by the current + -- position of the 16 x 16 + -- rocket image grid + -- The exact image pixel that + -- the TV beam is sweeping by + -- is provided by + -- horizontal pos bit 0-3: + -- MB_12, MB_N, MB_11, MB_M, + -- vertical pos bit 0-3: + -- MB_15, MB_13, MB_R, MB_14 + -- The information is used + -- by the Memory Board + -- to feed the correct + -- image pixel for further + -- video signal processing + -- at the sync star board + + MB_2_rocket, -- rocket missile + -- sound trigger + MB_2_saucer -- saucer missile + -- sound trigger + : out std_logic + ); +end motion_board; + +architecture motion_board_architecture + of motion_board is + +signal clk : std_logic ; +signal e5_15, missile_timer : std_logic := '0'; +signal f4_8 : std_logic := '1'; +signal d6_1, f6_10, f6_13,f6_4, + e6_6 : std_logic := '1'; + +signal a_rocket_q : unsigned (15 downto 0) + := "0000000000000000"; + +-- signals for horizontal and vertical +-- velocity for the rocket +signal f5_8, f3_10, f3_13, f2_8, + b1_10, e1_6, e1_8, f4_12, + f4_6, a6_12, a5_8 : std_logic; + +signal c1_1, c1_6, d1_1, d1_6 : std_logic; +signal d1_11, c1_15, d1_15, c1_11 : std_logic := '0'; +signal c1_10 : std_logic := '1'; + +signal b4_3, b4_4, d4_3, d4_4 : std_logic ; +signal d5_3, d5_4, b5_4, b5_3 : std_logic ; +signal e4_11, e4_12, e4_13, c4_11, + c4_12, c4_13 : std_logic ; + +signal e4_14, c4_14, d4_11, b4_11 : std_logic ; + +signal missile_life_time_counter : integer := 0; + +--- saucer signals +signal d3_4, d3_3, b3_4, b3_3, e3_11, + e3_13, e3_14, b3_14, a6_10, + a3_8, f3_1, f3_4, g1_8, g1_6, + f1_2, f1_3, e3_12, e3_15 : std_logic; + +signal f1_13, f1_7, f1_6, f1_15_0, + f1_16_0, f1_9_0, f1_10_0, + f1_10, f1_15, f1_16, f1_9 : std_logic; + +signal c3_11, c3_12, c3_13, c3_14, d3_11 : std_logic; +signal c6_1, f6_1 : std_logic; + +signal saucer_q : std_logic_vector (15 downto 0) + := "0000000000000000"; + +-- to simulate pulse to change direction +-- of saucer and to launch saucer +-- missile at the same time +signal clk_count : integer := 0; + +-- saucer missile signals +signal a4_1, a4_2, a4_4, a4_5, a4_13, + a4_12, a4_10, a4_9 : std_logic; +signal a4_3, a4_6, a4_11, a4_8 : std_logic; +signal a2_2, a2_3, a2_5, a2_6, a2_1, a2_4 : std_logic; +signal a1_2, a1_3, a1_6, a1_7, a1_13 : std_logic; +signal a1_15_0, a1_16_0, a1_9_0, a1_10_0 : std_logic; +signal a1_15, a1_16, a1_10, a1_9 : std_logic; +signal b1_1, b6_2, b1_13, g1_3 : std_logic; +signal f4_2 : std_logic := '1'; + +signal e2_15 : std_logic := '0'; +signal d2_4, d2_3, b2_4, b2_3, b1_4 : std_logic; +signal launch_missile : std_logic := '1'; +signal b6_6 : std_logic; +signal b6_5 : std_logic; +signal b6_5_old : std_logic := '0'; +signal delay_count : integer := 0; + +-- signals to manage asynchronous +-- clock design embedded in +-- synchronous clk solutions +signal c1_1_old, c1_6_old, + f1_13_old, a1_13_old : std_logic; + +signal d1_1_old, d1_6_old : std_logic; + +component v74161_16bit + port( + clk : in std_logic; + clrn : in std_logic; + ldn : in std_logic; + enp : in std_logic; + ent : in std_logic; + D : in unsigned (15 downto 0); + Q : out unsigned (15 downto 0); + rco : out std_logic + ); +end component; + +-----------------------------------------------------------------------------// +begin + +----------------------------------------------------------------------------- +-- clk is the game_clk -- +-- replaces a6_8, a6_6, a6_4, a6_2 -- +----------------------------------------------------------------------------- +clk <= not MB_20; + +----------------------------------------------------------------------------- +-- ROCKET MISSILE MOTION: Keep and change position -- +-- 74161 counters: B5, C5, D5, E5 -- +-- -- +-- GENERAL: -- +-- The game screen is defined by the game as a grid of 255 lines -- +-- where each line is divided into 256 pixels, except for one line -- +-- which only has 255 pixels. The reason for the 255 pixels -- +-- has to do with the approach to create object motion - described below -- +-- -- +-- Consequently a full screen consists of: -- +-- 255 pixels at one line + 256 pixels/line x 254 lines = 65.279 pixels -- +-- -- +-- Missiles are 1x1 pixel objects, each saucer is a 16x8 pixel object and -- +-- the rocket is a 16x16 pixel object. -- +-- -- +-- In modern day programming, the object's pixels would be mapped in a -- +-- 256x256 memory buffer, with pointers to each object's position. -- +-- Movement would be simply to change the object's x,y coordinates and -- +-- re-draw the objects in their new position. The TV picture would be -- +-- generated by reading from the memory buffer. -- +-- -- +-- In the world of Computer Space, without RAM, ROM and CPU, a non-buffer -- +-- approach is applied to object "screen draw" and motion. In essence the -- +-- object's pixels are processed and sent to the video signal in sync -- +-- with the TV beam as the beam moves across the screen - without any -- +-- memory buffer. The trick is to use a "relative counter" approach -- +-- where each object keeps track of its own "relative screen position". -- +-- Computer Space uses a 16-bit counter solution (implemented as 4 x 4-bit -- +-- counters) to count all 65.279 pixels. -- +-- -- +-- Full 16 bit counter: (2 raised to the power of 16) -1 = 65.535 -- +-- from 0 - 65.535 = 65.536 positions -- +-- 65.536 pixels max - 1 pixel less on first line - 256 pixels -- +-- for one line less (only 255 lines) = 65.279 -- +-- => starting on 257 (256 +1) and counting 65.278 times to cover -- +-- 65.279 position will have the counter reach its max value 65.535 -- +-- before resetting to zero. -- +-- -- +-- For instance: -- +-- 1) when a 1x1 missile pixel has been drawn, its -- +-- 16 bit counter (4 x 4-bit counters) is reset to 257 -- +-- = (msb:0000 0001 0000 0001 lsb - E5 D5 C5 B5) and its carry flag -- +-- (RCO) is reset to 0. -- +-- 2) For each pixel that the TV beam passes by, the missile position -- +-- counter is increaed by 1 in full sync with the TV beam. -- +-- The RCO-value (=0) is continuously fed to the video signal, which -- +-- equals the color black. -- +-- 3) When the counter reaches 65.535 (1111 1111 1111 1111) and sets -- +-- carry flag (RCO) to '1', the TV beam has travelled across all -- +-- 65.279 pixels (65.535-257+1) and arrived at the missile pixel's -- +-- original position. The RCO flag '1' is fed to the video signal at -- +-- which point the pixel is drawn again (to keep it visible on the -- +-- screen). The value '1' equals the color white -- +-- 4) The counter is reset to 257 again (and RCO is reset), and the -- +-- process starts all over, resulting in a motionless pixel drawn -- +-- onto screen. The exact position of the pixel depends on the TV -- +-- beam's position in relation to when the counter reaches 65.535 -- +-- -- +-- For clarity: the TV beam does not have any pixels to relate to, it is -- +-- a continuous "analogue" sweeping motion across the screen. Instead, -- +-- each "pixel" is a duration of time that translates into a specific -- +-- distance that the TV beam covers as it moves horizontally across the -- +-- screen - line by line. -- +-- -- +-- Horizontal movement: -- +-- Moving the missile pixel horizontally is now a very simple operation. -- +-- By resetting the counter to 256 instead of 257 the counter will have -- +-- to count one extra time (65.280 instead of 65.279) before it reaches -- +-- 65.535 and hence the pixel will move to the right of its previous -- +-- position. -- +-- bit 15.................0 -- +-- 257: 0000 0001 0000 0001 (bit0=1, bit1=0): no movement -- +-- 256: 0000 0001 0000 0000 (bit0=0, bit1=0): movement to the right -- +-- -- +-- Similarly, if the counter is reset to 258, the counter reaches -- +-- 65.535 one pixel ahead of its previous position; a move to the left. -- +-- bit 15.................0 -- +-- 257: 0000 0001 0000 0001 (bit0=1, bit1=0): no movement -- +-- 258: 0000 0001 0000 0010 (bit0=0, bit1=1): movement to the left -- +-- -- +-- Vertical Movement: -- +-- Reset to 1 and the counter have to count a full line (256 pixels) -- +-- extra before it reaches 65.535 - which creates a downward motion -- +-- bit 15.......8.........0 -- +-- 257: 0000 0001 0000 0001 (bit8=1, bit9=0): no movement -- +-- 1: 0000 0000 0000 0001 (bit8=0, bit9=0): movement down -- +-- -- +-- Reset to 513 - and the counter reaches 65.535 one line (256 pixels) -- +-- ahead of its previous position - upward motion. -- +-- bit 15.......8.........0 -- +-- 257: 0000 0001 0000 0001 (bit8=1, bit9=0): no movement -- +-- 513: 0000 0010 0000 0001 (bit8=0, bit9=1): movement up -- +-- -- +-- Resulting motion control signals: -- +-- bit 0: Horizontal movement (0) or not (1) -- +-- bit 1: Move Right (0) or Left (1) -- +-- bit 8: Vertical movement (0) or not (1) -- +-- bit 9: Move Down (0) or Up (1) -- +-- -- +-- Maximum speed: -- +-- The pixel can only move at a maximum pace of 60 pixels/second as the -- +-- TV beam sweeps across the screen 60 times/second (60Hz) for NTSC -- +-- standard. Slower speed can be achieved by moving the object only -- +-- every second screen refresh or less, and let it stand still in between -- +-- -- +-- Counters viewed as horizontal and vertical counters: -- +-- The counters can also be viewed as horizontal (x) and vertical (y) -- +-- D5, E5 - represent the current line (vertical) -- +-- B5, C5 - represent the pixel on that line (horizontal position) -- +-- This view may be a more attractive way of thinking about the relative -- +-- screen position, but keeping in mind that origo of the x,y coordinate -- +-- system for an object is to the left of the object's bottom right corner -- +-- and the first "line" is only 255 pixels. -- +-- -- +-- IMPLEMENTATION: -- +-- The counter represents the relative screen position as a 16-bit binary -- +-- number (with 4 x 4-bit counters) -- +-- -- +-- bits 0 and 1 are for controlling horizontal movement: -- +-- 0: (bit0=0, bit1=0) => right movement one pixel per 1/60s -- +-- 1: (bit0=1, bit1=0) => no horizontal movement -- +-- 2: (bit0=0, bit1=1) => left movement one pixel per 1/60s -- +-- -- +-- bits 8 and 9 are for controlling vertical movement: -- +-- 0 : (bit8=0, bit9=0) => downward movement one pixel per 1/60s -- +-- 256: (bit8=1, bit9=0) => no vertical movement -- +-- 512: (bit8=0, bit9=1) => upward movement one pixel per 1/60s -- +-- -- +-- in VHDL implemented as a 16 bit counter instead of 4 x 4-bit counters -- +----------------------------------------------------------------------------- +missile_motion: v74161_16bit + port map( + clk => clk, + clrn => e6_6, + ldn => f4_8, + enp => '1', + ent => MB_C, + D(15) => '0', + D(14) => '0', + D(13) => '0', + D(12) => '0', + D(11) => '0', + D(10) => '0', + D(9) => d5_4, -- Down (0) or Up (1) + D(8) => d5_3, -- Vertical movement (0) or not (1) + D(7) => '0', + D(6) => '0', + D(5) => '0', + D(4) => '0', + D(3) => '0', + D(2) => '0', + D(1) => b5_4, -- Right (0) or Left (1) + D(0) => b5_3, -- Horizontal movement (0) or not (1) + rco => e5_15 + ); + +d5_3 <= MB_19; -- MB_19 sets the vertical speed + -- constant 1 - no speed + -- constant 0 - speed of 60 pixels/second + -- pulse 0/1 @ 30 Hz rate - speed of 30 pixels/s + -- (a full screen is 255 pixels vertically) + +d5_4 <= f6_13; -- f6_13 sets the vertical direction + -- 0 - down, 1 - up + +b5_4 <= f6_10; -- f6_10 sets the horizontal direction + -- 0 - right, 1 - left + +b5_3 <= MB_17; -- MB_17 sets the horizontal speed + -- constant 1 - no speed + -- constant 0 - speed of 60 pixels/second + -- pulse 0/1 @ 30 Hz rate - speed of 30 pixels/s + -- (a screen is 256 pixels horizontally) + +f4_8 <= not (e5_15); -- trigger load of new start value once + -- counter has reached 65.535 (RCO is high) + +----------------------------------------------------------------------------- +-- Rocket missile video -- +----------------------------------------------------------------------------- +MB_P <= e5_15; -- rocket missile video (=RCO) + +----------------------------------------------------------------------------- +-- ROCKET MISSILE MOTION: VERTICAL SPEED AND DIRECTION LOGIC -- +-- -- +-- f6_13 sets the vertical direction: 0 - down, 1 - up -- +-- its the inverse of MB_18 (which comes from Memory Board) -- +-- Its fed to the missile motion counter, but will only result in vertical -- +-- motion if MB_19 is set to 0 for a specific screen draw -- +----------------------------------------------------------------------------- +f6_13 <= MB_19 nor MB_18; -- MB_19 sets the vertical speed + -- constant 1 - no speed + -- constant 0 - speed of 60 pixels/second + -- pulse 0/1 @ 30 Hz rate - speed of 30 pixels/s + -- (a full screen i 255 pixels vertically) + -- MB_18 sets the vertical direction + -- 0 - up, 1 - down + +----------------------------------------------------------------------------- +-- ROCKET MISSILE MOTION: HORIZONTAL SPEED AND DIRECTION LOGIC -- +-- -- +-- f6_10 sets the horizontal direction: 0 - right, 1 - left -- +-- its the inverse of MB_16 (which comes from Memory Board) in order to -- +-- fit the missile motion counter logic -- +-- Its fed to the missile motion counter, but will only result in -- +-- horizontal motion if MB_17 is set to 0 for a specific screen draw -- +----------------------------------------------------------------------------- +f6_10 <= MB_17 nor MB_16; -- MB_17 sets the horizontal speed + -- constant 1 - no speed + -- constant 0 - speed of 60 pixels/second + -- pulse 0/1 @ 30 Hz rate - speed of 30 pixels/s + -- (a full screen i 256 pixels horizontally) + -- MB_16 sets the horizontal direction + -- 0 - left, 1 - right + +----------------------------------------------------------------------------- +-- ROCKET MISSILE LIFE CYCLE: Timer functionality -- +-- D6, 74121 -- +-- when rocket missile fire button is pressed, the timer starts -- +-- counting the lifetime for the missile, a few seconds. -- +-- Time is dependent on "timer_base_clk" frequency and -- +-- "missile_life_time_counter". Both set in implementation specific code -- +-- MB_2_rocket is used instead of MB_2 and g1_11 - for the rocket missile -- +-- audio. -- +----------------------------------------------------------------------------- +process (timer_base_clk, MB_Y, missile_timer, missile_life_time_counter, rocket_missile_life_time_duration) +begin +if (MB_Y = '1' and missile_timer = '0') then + d6_1 <= '0'; + missile_timer <= '1'; + MB_2_rocket <= '1'; -- rocket missile sound sample trigger on +elsif (rising_edge(timer_base_clk) and missile_timer = '1') then + missile_life_time_counter <= missile_life_time_counter + 1; +elsif (rising_edge(timer_base_clk) and + missile_life_time_counter > rocket_missile_life_time_duration) then + missile_life_time_counter <= 0; + missile_timer <= '0'; + d6_1 <= '1'; + MB_2_rocket <= '0'; -- rocket missile sound sample trigger off +end if; +end process; + +----------------------------------------------------------------------------- +-- ROCKET MISSILE LIFE CYCLE: ROCKET MISSILE LAUNCH & VIDEO ENABLE -- +-- If rocket missile is active then the rocket missile may be displayed -- +-- (final display enable logic is done at Sync Star Board) -- +-- When the missile launches it originates from "the heart" of the -- +-- rocket. -- +-- -- +-- f6_4 is dividing the rocket's 16x16 image grid into four quadrants; -- +-- each an 8x8 pixel image grid. The upper left quadrant's pixels are -- +-- given a value of 1 and the other quadrants' pixels are given a value -- +-- of 0. -- +-- This follows from applying NOR on the MSBs of the rocket's motion -- +-- counters lower nibble for horizontal and vertical counting. -- +-- -- +-- horizontal d4_14 vertical c4_14 => f6_4 (NOR) -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 0000000000000000 1111111100000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- 0000000011111111 1111111111111111 0000000000000000 -- +-- -- +-- The rocket's 16x16 image is always appearing on the last 16 lines and -- +-- last 16 pixels of those lines. -- +-- -- +-- 1) If the missile is not active (d6_1 = 1) then e6_6 will go low -- +-- when the TV beam reaches any pixel in the upper left quadrant, -- +-- and consequently the missile motion counter will be reset. -- +-- 2) When the TV beam moves from the bottom right pixel (the "last" -- +-- pixel) of the 8x8 upper left pixel quadrant into the next quadrant -- +-- then e6_6 moves from low to high and the missile motion counter -- +-- starts counting. -- +-- 3) The above process is repeated for every screen drawn (60 times /s); -- +-- - which means the missile motion counter is always counting and -- +-- ready to go. -- +-- 4) If the missile has become active(missile launch) or is active then -- +-- there will be no clear signal when the TV beam moves into the upper -- +-- left 8x8 pixel quadrant and consequently the missile pixel will -- +-- be displayed as missile motion counter reaches 65.535. -- +-- 5) If it is a missile launch then the pixel will appear one line -- +-- below the rocket's center, immediately to the right of the 8x8 -- +-- upper left quadrant; which is almost in the center/heart of the -- +-- rocket. -- +----------------------------------------------------------------------------- +a6_12 <= not a5_8; -- signals when TV beam is + -- passing by the + -- current position of the + -- rocket's 16x16 image grid + +f6_4 <= d4_11 nor b4_11; -- signals that the TV beam + -- is passing by the upper + -- left 8x8 pixel quadrant + -- of any 16x16 image + -- grid (could be the rocket's) + -- at "16 pixels intervals" and + -- at "16 lines intervals" + +e6_6 <= not (d6_1 and a6_12 and f6_4); -- Missile Active Flag + -- d6_1 signals that the + -- missile is active + -- The combination of a6_12 and + -- f6_4 signals when the TV + -- beam passes by the upper left + -- 8x8 pixel quadrant of the + -- rocket's 16x16 image grid. + -- The resulting signal feeds + -- the Rocket Missile Motion + -- Counter's clrn + -- If the missile is not active + -- when the TV beam moves into + -- the 8x8 pixel quadrant, then + -- the counter will be cleared + -- - and when the TV beam moves + -- from the bottom right pixel + -- (the "last" pixel) of the 8x8 + -- upper left pixel quadrant + -- into the next quadrant then + -- the resulting signal moves + -- from "clear" to "not clear" + -- and starts counting. + -- If the missile has been set + -- to active or is active then + -- there will be no clear signal + -- when the TV beam moves into + -- the upper left 8x8 pixel + -- quadrant and consequently the + -- missile pixel will be + -- displayed as the motion + -- counter reaches 65.535. + -- If it is the launch then the + -- pixel will appear one line + -- below and one pixel to the + -- right of the rocket center + +----------------------------------------------------------------------------- +-- ROCKET MOTION: Keep and change position -- +-- 74161 counters: B4, C4, D4, E4 -- +-- -- +-- Motion principles: -- +-- For basic motion principles, please see explanation above for -- +-- ROCKET MISSILE MOTION. -- +-- Whereas the 1x1 missile pixel is using RCO to feed the video signal -- +-- the rocket needs to feed 16x16 pixels, which requires additional logic. -- +-- The rocket object is placed in the last 16 pixel of the last 16 lines -- +-- that the rocket motion counter (B4,C4,D4,E4) is counting. The very last -- +-- pixel (the bottom right pixel of the 16x16 image grid) is displayed -- +-- at the count of 65.535. -- +-- In this context, it can be useful to view the counter as one -- +-- horizontal counter and one vertical counter. -- +-- -- +-- V: H: 240..............255 -- +-- 239 ..................... -- +-- 240 .....xxxxxxxxxxxxxxxx (240,240)->(255,240) or 61.680->61.695 -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- . .....xxxxxxxxxxxxxxxx . -- +-- 255 .....xxxxxxxxxxxxxxxO (240,255)->(255,255) or 65.520->65.535 -- +-- -- +-- A very simple logic (a5_8) determines when the last 16 pixels for the -- +-- last 16 lines are being counted by the rocket motion counter - by -- +-- simply looking at the MSB nibble -- +-- MSB nibble: 1111 xxxx = 240 - 255 for horizontal -- +-- MSB nibble: 1111 xxxx = 240 - 255 for vertical -- +-- -- +-- If the counter is being reset in the same way as explained for the -- +-- ROCKET MISSILE MOTION to achieve horizontal and/or vertical movement -- +-- then this will consequently imapct all the 16x16 bits, as their -- +-- relative positions are all, naturally, "hanging together". -- +-- -- +-- IMPLEMENTATION: -- +-- The counter represents the relative screen position as a 16-bit binary -- +-- number (with 4 x 4-bit counters) -- +-- -- +-- bits 0 and 1 are for controlling horizontal movement: -- +-- 0: (bit0=0, bit1=0) => right movement one pixel per 1/60s -- +-- 1: (bit0=1, bit1=0) => no horizontal movement -- +-- 2: (bit0=0, bit1=1) => left movement one pixel per 1/60s -- +-- -- +-- Horizontal speed is achieved by changing the frequency -- +-- with which the rocket is set to move horizontally. For instance -- +-- letting the rocket pause every 1/30s and move every 1/30s -- +-- gives the impression of moving one pixel per 1/30s -- +-- -- +-- bits 8 and 9 are for controlling vertical movement: -- +-- 0 : (bit8=0, bit9=0) => downward movement one pixel per 1/60s -- +-- 256: (bit8=1, bit9=0) => no vertical movement -- +-- 512: (bit8=0, bit9=1) => upward movement one pixel per 1/60s -- +-- -- +-- Vertical speed is achieved by changing the frequency -- +-- with which the rocket is set to move vertically. For instance -- +-- letting the rocket pause every 1/30s and move every 1/30s -- +-- gives the impression of moving one pixel per 1/30s -- +-- -- +-- in VHDL implemented as a 16 bit counter instead of 4 x 4-bit counters -- +----------------------------------------------------------------------------- +process (clk) +begin +if rising_edge(clk) then + if MB_C='1' then + if a_rocket_q < 65534 then + a_rocket_q <= a_rocket_q + 1; + elsif a_rocket_q < 65535 then + a_rocket_q <= a_rocket_q + 1; + else + a_rocket_q (0) <= b4_3; -- Horizontal movement (0) or not (1) + a_rocket_q (1) <= b4_4; -- Right (0) or Left (1) + a_rocket_q (2) <= '0'; + a_rocket_q (3) <= '0'; + a_rocket_q (4) <= '0'; + a_rocket_q (5) <= '0'; + a_rocket_q (6) <= '0'; + a_rocket_q (7) <= '0'; + a_rocket_q (8) <= d4_3; -- Vertical movement (0) or not (1) + a_rocket_q (9) <= d4_4; -- Down (0) or Up (1) + a_rocket_q (10) <= '0'; + a_rocket_q (11) <= '0'; + a_rocket_q (12) <= '0'; + a_rocket_q (13) <= '0'; + a_rocket_q (14) <= '0'; + a_rocket_q (15) <= '0'; + end if; + end if; +end if; +end process; + +d4_4 <= f3_10; -- Down (0) or Up (1) + +d4_3 <= f5_8; -- Vertical movement (0) or not (1) + -- constant 1 gives no movemenet + -- pulsing between 0 and 1 at specific + -- frequency intervals + -- gives a range of screen speeds + +b4_4 <= f3_13; -- Right (0) or Left (1) + +b4_3 <= f2_8; -- Horizontal movement (0) or not (1) + -- constant 1 gives no movemenet + -- pulsing between 0 and 1 at specific + -- frequency intervals + -- gives a range of screen speeds + + +d4_11 <= a_rocket_q(11); + +e4_11 <= a_rocket_q(15); +e4_12 <= a_rocket_q(14); +e4_13 <= a_rocket_q(13); +e4_14 <= a_rocket_q(12); +c4_11 <= a_rocket_q(7); +c4_12 <= a_rocket_q(6); +c4_13 <= a_rocket_q(5); +c4_14 <= a_rocket_q(4); + +b4_11 <= a_rocket_q(3); + +-- creating motion board connectors from chip B4 and D4 +MB_M <= a_rocket_q(0); +MB_11 <= a_rocket_q(1); +MB_N <= a_rocket_q(2); +MB_12 <= a_rocket_q(3); + +MB_14 <= a_rocket_q(8); +MB_R <= a_rocket_q(9); +MB_13 <= a_rocket_q(10); +MB_15 <= a_rocket_q(11); + +----------------------------------------------------------------------------- +-- ROCKET MOTION: creating rocket enable signal (active low) -- +-- when the TV beam is passing by the position of the -- +-- rocket's 16 x 16 image grid -- +----------------------------------------------------------------------------- +MB_W <= a5_8; -- Rocket Enable + +a5_8 <= not (c4_11 and c4_12 and c4_13 and c4_14 + and e4_11 and e4_12 and e4_13 and e4_14); + +----------------------------------------------------------------------------- +-- ROCKET MOTION: Vertical direction and velocity -- +-- f3_10 sets the vertical direction: 0 - down, 1 - up -- +-- its the inverse of MB_H (which comes from Memory Board) in order to -- +-- fit the rocket motion counter logic -- +-- Its fed to the rocket motion counter, but will only result in -- +-- vertical motion when f5_8 is set to 0 for a specific screen draw -- +----------------------------------------------------------------------------- +f3_10 <= MB_H nor f5_8; -- MB_H sets the vertical direction + -- 0 - up, 1 - down + -- f5_8 sets the vertical speed + -- pulses 0/1:s at discrete frequencies which + -- will make the rocket move a pixel at specific + -- intervals and create a range of rocket speeds + -- 1 - no speed + -- 0 - one pixel movement per new screen draw + +----------------------------------------------------------------------------- +-- ROCKET MOTION: Horizontal direction and velocity -- +-- f6_13 sets the horizontal direction: 0 - right, 1 - left -- +-- its the inverse of MB_J (which comes from Memory Board) in order to -- +-- fit the rocket motion counter logic -- +-- Its fed to the rocket motion counter, but will only result in -- +-- horizontal motion when f2_8 is set to 0 for a specific screen draw -- +----------------------------------------------------------------------------- +f3_13 <= MB_J nor f2_8; -- MB_J sets the horizontal direction + -- 0 - left, 1 - right + -- f2_8 sets the horizontal speed + -- pulses 0/1:s at discrete frequencies which + -- will make the rocket move a pixel at specific + -- intervals and create a range of rocket speeds + -- 1 - no speed + -- 0 - one pixel movement per new screen draw + +----------------------------------------------------------------------------- +-- ROCKET VELOCITY: Vertical screen velocity pulse train -- +-- Mixing the rocket's current vertical velocity level (0-7) with base -- +-- frequencies to create a range of discrete frequencies that will -- +-- increase with velocity level. -- +-- Higher frequency results in rocket moving more frequent and -- +-- consequently achieving a higher vertical speed on screen. -- +----------------------------------------------------------------------------- +f5_8 <= not ((MB_V and b1_10) or (MB_U and f4_6) or (MB_T and f4_12)); + +----------------------------------------------------------------------------- +-- ROCKET VELOCITY: Horizontal screen velocity pulse train -- +-- Mixing the rocket's current horizontal velocity level (0-7) with base -- +-- frequencies to create a range of discrete frequencies that will -- +-- increase with velocity level. -- +-- Higher frequency results in rocket moving more frequent and -- +-- consequently achieving a higher horizontal speed on screen. -- +----------------------------------------------------------------------------- +f2_8 <= not ((MB_4 and b1_10) or (MB_D and f4_6) or (MB_3 and f4_12)); + +----------------------------------------------------------------------------- +-- ROCKET VELOCITY: Frequency mixing -- +-- create frequencies used as a basis to create a range of discrete rocket -- +-- velocities -- +-- b1_10: 15 Hz frequency pulse train with positive pulse lasting 1/30 s -- +-- f4_6 : 7,5 Hz fequency pulse train with positive pulse lasting 1/30 s -- +-- f4_12: 3.25 Hz fequency pulse train with positive pulse lasting 1/30 s -- +----------------------------------------------------------------------------- +b1_10 <= c1_15 nor c1_10; + +e1_6 <= not (c1_15 and c1_10 and d1_6 and d1_6); -- 7420 (nand) + -- wrong gate + -- marking (7402 nor) + -- on original + -- schematics + +f4_6 <= not e1_6; + +e1_8 <= not (c1_10 and d1_15 and c1_15 and d1_11); -- 7420 (nand) + -- wrong gate + -- marking (7402 nor) + -- on original + -- schematics + +f4_12 <= not e1_8; + +----------------------------------------------------------------------------- +-- ROCKET VELOCITY: FREQUENCY DIVIDER LOGIC -- +-- Flip-Flops C1 & D1 -- +-- Frequency division as a base to create a range of discrete rocket -- +-- velocities -- +-- c1_15: 30 Hz pulse train -- +-- c1_10: 15 Hz pulse train -- +-- d1_15: 7.5 Hz pulse train -- +-- di_11: 3.25 Hz pulse train -- +-- MB_B : 30 Hz pulse train used by Memory Board to create rocket missile -- +-- speed -- +----------------------------------------------------------------------------- +c1_1 <= e3_11; + +process (super_clk) +begin +if rising_edge (super_clk) then + c1_1_old <= c1_1; + if (c1_1_old = '1') and (c1_1 = '0') then + c1_15 <= not c1_15; + end if; +end if; +end process; + +MB_B <= c1_15; + +c1_6 <= c1_15; + +process (super_clk) +begin +if rising_edge (super_clk) then + c1_6_old <= c1_6; + if (c1_6_old = '1') and (c1_6 = '0') then + c1_11 <= not c1_11; + c1_10 <= not c1_10; + end if; +end if; +end process; + +d1_1 <= c1_11; + +process (super_clk) +begin +if rising_edge (super_clk) then + d1_1_old <= d1_1; + if (d1_1_old = '1') and (d1_1 = '0') then + d1_15 <= not d1_15; + end if; +end if; +end process; + +d1_6 <= d1_15; + +process (super_clk) +begin +if rising_edge (super_clk) then + d1_6_old <= d1_6; + if (d1_6_old = '1') and (d1_6 = '0') then + d1_11 <= not d1_11 ; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- SAUCER MOTION: Keep and change position -- +-- 74161 counters: B3, C3, D3, E3 -- +-- -- +-- Motion principles: -- +-- For basic motion principles, please see explanation above for -- +-- ROCKET MOTION. -- +-- -- +-- bits 0 and 1 are for controlling horizontal movement: -- +-- (bit0=0, bit1=1) => no horizontal movement -- +-- (bit0=1, bit1=1) => right movement one pixel per 1/60s -- +-- (bit0=1, bit1=0) => left movement one pixel per 1/60s -- +-- -- +-- The de facto horizontal speed is achieved by moving the saucer every -- +-- 1/30s. This is achived by pulsing the movement signal on/off every -- +-- second screen draw (=>30Hz) -- +-- -- +-- bits 8 and 9 are for controlling vertical movement: -- +-- (bit8=0, bit9=1) => no vertical movement -- +-- (bit8=1, bit9=1) => downward movement one pixel per 1/60s -- +-- (bit8=1, bit9=0) => upward movement one pixel per 1/60s -- +-- -- +-- The de facto vertical speed is achieved by moving the saucer every -- +-- 1/30s. This is achived by pulsing the movement signal on/off every -- +-- second screen draw (=>30Hz) -- +-- -- +-- Implemented as a 16 bit counter instead of 4 x 4 bit counters -- +----------------------------------------------------------------------------- +process (clk) +begin +if rising_edge(clk) then + if MB_C='1' then + if saucer_q < 65534 then + saucer_q <= saucer_q + 1; + e3_15 <= '0'; + elsif saucer_q < 65535 then + saucer_q <= saucer_q + 1; + e3_15 <= '1'; + else + e3_15 <= '0'; + saucer_q (0) <= b3_3; -- Horizontal movement (0) or not (1) + saucer_q (1) <= b3_4; -- Right (0) or Left (1) + saucer_q (2) <= '0'; + saucer_q (3) <= '0'; + saucer_q (4) <= '0'; + saucer_q (5) <= '0'; + saucer_q (6) <= '0'; + saucer_q (7) <= '0'; + saucer_q (8) <= d3_3; -- Vertical movement (0) or not (1) + saucer_q (9) <= d3_4; -- Down (0) or Up (1) + saucer_q (10) <= '0'; + saucer_q (11) <= '0'; + saucer_q (12) <= '0'; + saucer_q (13) <= '0'; + saucer_q (14) <= '0'; + saucer_q (15) <= '0'; + end if; + end if; +end if; +end process; + +d3_4 <= f3_1; -- Down (0) or Up (1) + +d3_3 <= g1_8; -- Vertical movement (0) or not (1) + -- constant 1 gives no movemenet + -- pulsing between 0 and 1 at 30Hz + -- gives a 30 pixels/s screen speed + +b3_4 <= f3_4; -- Right (0) or Left (1) + +b3_3 <= g1_6; -- Horizontal movement (0) or not (1) + -- constant 1 gives no movemenet + -- pulsing between 0 and 1 at 30Hz + -- gives a 30 pixels/s screen speed + +-- creating motion board connectors from chip B4 and D4 +MB_E <= saucer_q(0); +MB_5 <= saucer_q(1); +MB_F <= saucer_q(2); +MB_6 <= saucer_q(3); + +MB_L <= saucer_q(8); +MB_9 <= saucer_q(9); +MB_K <= saucer_q(10); +MB_8 <= saucer_q(11); + + +b3_14 <= saucer_q(0); +c3_11 <= saucer_q(7); +c3_12 <= saucer_q(6); +c3_13 <= saucer_q(5); +c3_14 <= saucer_q(4); + +d3_11 <= saucer_q(11); + +e3_11 <= saucer_q(15); +e3_12 <= saucer_q(14); +e3_13 <= saucer_q(13); +e3_14 <= saucer_q(12); + +----------------------------------------------------------------------------- +-- SAUCER MOTION: creating saucer enable signal (active low) -- +-- when the TV beam is passing by the position of either one of the -- +-- saucer's 16 x 8 image grids -- +----------------------------------------------------------------------------- +MB_21 <= not a3_8; --saucer_enable + + a3_8 <= not (c3_11 and c3_12 and c3_13 and c3_14 + and e3_12 and e3_13 and e3_14 and d3_11); + +----------------------------------------------------------------------------- +-- SAUCER MOTION: saucer vertical direction and speed -- +-- f3_1 sets the vertical direction: 0 - down, 1 - up -- +-- its the inverse of f1_9 in order to fit the saucer motion counter -- +-- logic -- +-- Its fed to the saucer motion counter, but will only result in -- +-- vertical motion when g1_8 is set to 0 for a specific screen draw -- +----------------------------------------------------------------------------- +f3_1 <= f1_9 nor g1_8; -- f1_9 sets the vertical direction + -- 0 - up, 1 - down + -- g1_8 sets the vertical speed + -- it is either constant 1 - no speed or + -- pulses 0/1:s at 30Hz frequency which + -- will make the saucer move 30 pixels/s + -- 0 - one pixel movement per new screen draw + +----------------------------------------------------------------------------- +-- SAUCER MOTION: saucer horizontal direction and speed -- +-- f3_4 sets the horizontal direction: 0 - right, 1 - left -- +-- its the inverse of f1_15 in order to fit the saucer motion counter -- +-- logic -- +-- Its fed to the saucer motion counter, but will only result in -- +-- horizontal motion when g1_6 is set to 0 for a specific screen draw -- +----------------------------------------------------------------------------- +f3_4 <= f1_15 nor g1_6; -- f1_15 sets the horizontal direction + -- 0 - left, 1 - right + -- g1_6 sets the horizontal speed + -- it is either constant 1 - no speed or + -- pulses 0/1:s at 30Hz frequency which + -- will make the saucer move 30 pixels/s + -- 0 - one pixel movement per new screen draw + +----------------------------------------------------------------------------- +-- SAUCER VELOCITY: Saucer vertical speed -- +-- "Filters" the frequency that is the basis for saucer speed -- +----------------------------------------------------------------------------- +g1_8 <= f1_10 nand c1_15; -- f1_10 is a flag that signals whether + -- the saucer should have vertical speed or not + -- c1_15 is a 30Hz frequency that is passed + -- through to g1_8 when f1_10 = 1 + +----------------------------------------------------------------------------- +-- SAUCER VELOCITY: Saucer horizontal speed -- +-- "Filters" the frequency that is the basis for saucer speed -- +----------------------------------------------------------------------------- +g1_6 <= f1_16 nand c1_15; -- f1_16 is a flag that signals whether + -- the saucer should have vertical speed or not + -- c1_15 is a 30Hz frequency that is passed + -- through to g1_6 when f1_16 = 1 + +----------------------------------------------------------------------------- +-- SAUCER DIRECTION SELECTION: Load and lock new or same direction -- +-- F1 7475 -- +-- 4-bit bistable latch -- +-- emulated as a clocked version -- +-- determines the next saucer direction -- +----------------------------------------------------------------------------- +f1_2 <= e3_11; -- 60 Hz frequency in sync with + -- final saucer pixel being drawn to screen + +f1_3 <= b3_14; +f1_13 <= f6_1; +f1_7 <= e3_12; +f1_6 <= e3_13; + +process (clk) +begin +if rising_edge (clk) then + f1_13_old <= f1_13; + if (f1_13_old = '0') and (f1_13 = '1') then + f1_15 <= f1_3; -- vertical velocity or not + f1_16 <= f1_2; -- horizontal velocity or not + f1_9 <= f1_7; -- vertical direction up/down + f1_10 <= f1_6; -- horizontal direction left/right + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- SAUCER MISSILE LIFECYCLE AND DIRECTION CHANGE TIMER -- +-- C6 74121 - Schmitt Astabile Multivibrator -- +-- Drive change of c6_1 as an emulation of b6_8/10/12 + 250uF and the -- +-- 74121 set-up -- +----------------------------------------------------------------------------- +process (timer_base_clk) +begin +if rising_edge (timer_base_clk) then + if c6_1 = '0' then + if clk_count < saucer_missile_life_time_duration then + clk_count <= clk_count+1; + else + clk_count <= 0; -- reset clock_count to start a new pulse wave + c6_1 <= '1'; + end if; + elsif c6_1 = '1' then + if clk_count < saucer_missile_hold_duration then + clk_count <= clk_count+1; + else + clk_count <= 0; -- reset clock_count to start a new pulse wave + c6_1 <= '0'; + end if; + end if; +end if; +end process; + +-- special case; assign input of b6_6 the input value (operand then applies +-- with delay on b6_6 below) +b6_5 <= c6_1; + +----------------------------------------------------------------------------- +-- SAUCER DIRECTION SELECTION: Create direction change pulse -- +-- Drive change of b6_6 as an emulation of delay caused by b6 and .2F Cap -- +-- Create the pulse that will load the saucer's new (or the same) -- +-- direction -- +-- The pulse is somewhat delayed in relation to the launch of the saucer -- +-- missile, creating the effect that the saucer will first launch its -- +-- missile and thereafter change (or maintain) direction -- +----------------------------------------------------------------------------- +process (timer_base_clk) +begin +if rising_edge (timer_base_clk) then + b6_5_old <= b6_5; + if b6_5_old = '0' and b6_5 = '1' then + -- if rising edge , initiate a delay before output changes + delay_count <= 0; + elsif b6_5_old = '0' and b6_5 = '1' then + -- if falling edge , initiate a delay before output changes + delay_count <= 0; + else + if delay_count < signal_delay_duration then + delay_count <= delay_count +1; + else + delay_count <= 0; + b6_6 <= not b6_5; + -- change output after signal delay; this causes a signal spike + end if; + end if; +end if; +end process; + +f6_1 <= c6_1 nor b6_6; + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: Rocket's position relative current TV beam pos -- +-- A4, 7486 -- +-- quadruple 2-input xor gates -- +-- Identify how the current TV beam position relates to the rocket's -- +-- vertical and horizontal position. -- +-- -- +-- The complete missile AI logic will determine whether the rocket is to -- +-- the left or to the right of (or on level with) the saucer and whether -- +-- it is below or above (or on plane with) the saucer. This will control -- +-- the saucer missile's launch direction. -- +-- If the rocket and the saucer are very close to each other -- +-- then the saucer missile will not get any movement and instead become -- +-- a "mine" (a missile that appears like a motionless star that exists -- +-- for a while and then disappears) -- +----------------------------------------------------------------------------- +a4_1 <= e4_11; +a4_2 <= e4_12; +a4_4 <= e4_12; +a4_5 <= e4_13; +a4_13 <= c4_11; +a4_12 <= c4_12; +a4_10 <= c4_12; +a4_9 <= c4_13; + +a4_3 <= a4_1 xor a4_2; -- current TV beam position + -- above or below the rocket's 16x16 image + -- position within 65 - 255 pixels (=1) + -- or within 64 pixels (=0) + +a4_6 <= a4_4 xor a4_5; -- current TV beam position + -- above or below the rocket's 16x16 image + -- position within 33 - 191 pixels (=1) + -- or within 32 pixels (=0) + +a4_11 <= a4_13 xor a4_12; -- current TV beam position + -- to the left or to the right of + -- the rocket's 16x16 image position + -- within 65 - 255 pixels (=1) + -- or within 64 pixels (=0) + +a4_8 <= a4_10 xor a4_9; -- current TV beam position + -- to the left or to the right of + -- the rocket's 16x16 image position + -- within 33 - 191 pixels (=1) + -- or within 32 pixels (=0) + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: Current TV beam pos very close to rocket? -- +-- A2, 7402 -- +-- quadruple 2-input nor gates -- +-- if the current TV beam position is very close to the rocket vertically -- +-- and/or horizontally; sets a flag. Used by downstream logic to prevent -- +-- saucer missile motion vertically and/or horizontally. -- +-- -- +-- The complete missile AI logic will determine whether the rocket is to -- +-- the left or to the right of (or on level with) the saucer and whether -- +-- it is below or above (or on plane with) the saucer. This will control -- +-- the saucer missile's launch direction. -- +-- If the rocket and the saucer are very close to each other -- +-- then the saucer missile will not get any movement and instead become -- +-- a "mine" (a missile that appears like a motionless star that exists -- +-- for a while and then disappears) -- +----------------------------------------------------------------------------- +a2_2 <= a4_3; +a2_3 <= a4_6; +a2_5 <= a4_11; +a2_6 <= a4_8; + +a2_1 <= a2_2 nor a2_3; -- current TV beam position + -- above or below the rocket's 16x16 image + -- position within 32 pixels (=1) + +a2_4 <= a2_5 nor a2_6; -- current TV beam position + -- to the left or to the right of + -- the rocket's 16x16 image position + -- within 32 pixels (=1) + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: Launch missile! -- +-- when the saucer missile timer is reset and starts counting (c6_1) and -- +-- the missile carrying saucer's last pixel has just been drawn to screen -- +-- (e3_15) then this creats a short combined pulse (g1_3) that will be -- +-- used to: -- +-- 1) lock the current saucer missile direction input value (A1) -- +-- 2) load those values into the saucer missile motion logic and -- +-- allow the saucer missile to launch -- +----------------------------------------------------------------------------- +g1_3 <= c6_1 nand e3_15; +b6_2 <= not g1_3; + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: Load saucer missile direction input values -- +-- input to A1, 7475 -- +-- The inputs, their values and their donwstream impact: -- +-- c4_14: -- +-- 0=rocket is closer to the left of current TV beam position -- +-- => right bound missile motion -- +-- 1=rocket is closer to the right of current TV beam position -- +-- => leftbound missile motion -- +-- -- +-- e4_14: -- +-- 0=rocket is closer above current TV beam position -- +-- => upward missile motion -- +-- 1=rocket is closer below current TV beam position -- +-- => downward missile motion -- +-- -- +-- c4_14 and e4_14 are the msb for horizontal and vertical rocket count -- +-- which in one view point counts how far "away" from the rocket the TV -- +-- beam is -- +-- -- +-- a2_4 -- +-- 1= current TV beam position to the left or to the right of -- +-- the rocket's 16x16 image position within 32 pixels -- +-- and should prevent horizontal saucer missile motion -- +-- 0= not within 32 pixels -- +-- -- +-- a2_1 -- +-- 1= current TV beam position below or above -- +-- the rocket's 16x16 image position within 32 pixels -- +-- and should prevent vertical saucer missile motion -- +-- 0= not within 32 pixels -- +----------------------------------------------------------------------------- +a1_2 <= a2_4; -- 1d (data input) + +a1_3 <= c4_11; -- 2d (data input) + +a1_6 <= a2_1; -- 3d (data input) + +a1_7 <= e4_11; -- 4d (data input) + +a1_13 <= b6_2; -- 1c, 2c (enable) + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: Lock saucer missile direction input values -- +-- A1, 7475 -- +-- 4-bit bistable latch -- +-- when enable is high, output q will follow input data d -- +-- when enable goes low; data input at time of transition to low -- +-- will be retained at output q -- +-- -- +-- When missile is about to launch it is synchronized with current TV -- +-- beam position, and consequently its relative position to the rocket. -- +----------------------------------------------------------------------------- +process (clk) +begin +if rising_edge (clk) then + a1_13_old <= a1_13; + if (a1_13_old = '1') and (a1_13 = '0') then + a1_15 <= a1_3; + a1_16 <= a1_2; + a1_9 <= a1_7; + a1_10 <= a1_6; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: horizontal movement feed -- +-- -- +-- a1_15 (=c4_14): -- +-- 0=rocket is closer to the left of current TV beam position -- +-- => right bound missile motion -- +-- 1=rocket is closer to the right of current TV beam position -- +-- => leftbound missile motion -- +-- -- +-- a1_16 (=a2_4) -- +-- 1= current TV beam position to the left or to the right of -- +-- the rocket's 16x16 image position within 32 pixels -- +-- and should prevent horizontal saucer missile motion -- +-- 0= not within 32 pixels -- +----------------------------------------------------------------------------- +b1_1 <= a1_15 nor a1_16; -- right or left motion + +----------------------------------------------------------------------------- +-- SAUCER MISSILE AI LOGIC: vertical movement feed -- +-- -- +-- a1_9 (=e4_14): -- +-- 0=rocket is closer above current TV beam position -- +-- => upward missile motion -- +-- 1=rocket is closer below current TV beam position -- +-- => downward missile motion -- +-- -- +-- a1_10 (=a2_1) -- +-- 1= current TV beam position below or above -- +-- the rocket's 16x16 image position within 32 pixels -- +-- and should prevent vertical suacer missile motion -- +-- 0= not within 32 pixels -- +----------------------------------------------------------------------------- +b1_13 <= a1_10 nor a1_9; -- up or down motion + +----------------------------------------------------------------------------- +-- SAUCER MISSILE MOTION: Keep and change position -- +-- 74161 counters: B2, C2, D2, E2 -- +-- -- +-- Motion principles: -- +-- For basic motion principles, please see explanation above for -- +-- ROCKET MISSILE MOTION. -- +-- -- +-- bits 0 and 1 are for controlling horizontal movement: -- +-- (bit0=0, bit1=1) => no horizontal movement -- +-- (bit0=1, bit1=1) => right movement one pixel per 1/60s -- +-- (bit0=1, bit1=0) => left movement one pixel per 1/60s -- +-- -- +-- bits 8 and 9 are for controlling vertical movement: -- +-- (bit8=0, bit9=1) => no vertical movement -- +-- (bit8=1, bit9=1) => downward movement one pixel per 1/60s -- +-- (bit8=1, bit9=0) => upward movement one pixel per 1/60s -- +-- -- +-- implemented as a 16 bit counter instead of 4 x 4-bit counters -- +----------------------------------------------------------------------------- +saucer_missile: v74161_16bit + port map( + clk => clk, + clrn => g1_3, + ldn => f4_2, + enp => '1', + ent => MB_C, + D(15) => '0', + D(14) => '0', + D(13) => '0', + D(12) => '0', + D(11) => '0', + D(10) => '0', + D(9) => d2_4, -- Down (0) or Up (1) + D(8) => d2_3, -- Vertical movement (0) or not (1) + D(7) => '0', + D(6) => '0', + D(5) => '0', + D(4) => '0', + D(3) => '0', + D(2) => '0', + D(1) => b2_4, -- Right (0) or Left (1) + D(0) => b2_3, -- Horizontal movement (0) or not (1) + rco => e2_15 + ); + +b2_4 <= b1_1; -- Right (0) or Left (1) + +b2_3 <= a1_16; -- Horizontal movement (0) or not (1) + -- either constant 1 - no movement; or + -- constant 0 - "60Hz" horizontal speed + -- (60 pixels / second) + +d2_3 <= a1_10; -- Vertical movement (0) or not (1) + -- either constant 1 - no movement; or + -- constant 0 - "60Hz" vertical speed + -- (60 pixels / second) + +d2_4 <= b1_13; -- Down (0) or Up (1) + + +f4_2 <= not (e2_15); -- RCO enables the load of value for next cycle + +----------------------------------------------------------------------------- +-- Saucer missile video -- +----------------------------------------------------------------------------- +MB_10 <= e2_15; -- RCO + +----------------------------------------------------------------------------- +-- Saucer missile audio -- +----------------------------------------------------------------------------- +--b1_4 <= d2_13 nor c6_1; -- original schematics (correct) + -- but can not use freq from d2_13 as the + -- audio is generated from a sample +b1_4 <= not c6_1; -- instead, to trigger sample + +MB_2_saucer <= b1_4; -- saucer missile sound sample trigger + -- instead of MB_2 + + +end motion_board_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/osd.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/pll.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/pll.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/pll.v new file mode 100644 index 00000000..3d37470a --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/pll.v @@ -0,0 +1,376 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + c2, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 5, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 27, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 50, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 27, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 20, + altpll_component.clk2_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "20.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "50" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "20" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "5.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "20.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_diode_images.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_diode_images.vhd new file mode 100644 index 00000000..b4704c06 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_diode_images.vhd @@ -0,0 +1,182 @@ +----------------------------------------------------------------------------- +-- ROCKET DIODE IMAGES LOGIC -- +-- For use with Computer Space FPGA emulator. -- +-- emulates the rocket diode matrix function -- +-- on Computer Space's Motion Board -- +-- -- +-- This entity is implementation agnostic -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; + +--80--------------------------------------------------------------------------| + +entity rocket_diode_images is + port ( + image_select : in integer range 0 to 3; + -- select rocket image + -- 0-3 + + rocket_hor, rocket_ver : in integer range 0 to 15; + -- address the + -- horizontal and + -- vertical slices of + -- the rocket diode + -- matrix images + + diode_left_column, + diode_right_column : in std_logic; + -- indicate + -- whether right column or + -- left column should show + -- rocket engine flames + + out_image_bit : out std_logic + ); + +end rocket_diode_images; + +architecture rocket_diode_images_architecture + of rocket_diode_images is + +-- ROCKET IMAGES +type image_line_16_bit is array (0 to 15) + of std_logic; +type image_line_8_bit is array (0 to 7) + of std_logic; + +type rocket_image is array(0 to 15) of + image_line_16_bit; + +-- defining signal to load +-- images from the arrays +signal image_line : image_line_16_bit; +signal I_rocket_hor, I_rocket_ver : integer range 0 to 15; +signal rocket_engine_flame : std_logic; + +-- rocket image no 0 +signal rocket_image_0 : rocket_image := ( +("0000000000000000"), +("0000000000010000"), +("0001000000000000"), +("0000000001000000"), +("0000010000000100"), +("0100000000000000"), +("0000000000000000"), +("0000000000010000"), +("0000100000000000"), +("0000000000010000"), +("0000100000000000"), +("0000000000010000"), +("0000010000000000"), +("0000000000100000"), +("0000001000000000"), +("0000000010000000") +); + +-- rocket image no 1 +signal rocket_image_1 : rocket_image := ( +("0000000000100000"), +("0000000000000000"), +("0000000000000100"), +("0010000010000000"), +("0000010000000000"), +("0000000000000000"), +("0100000000010000"), +("0000000000000000"), +("0000100000001000"), +("0000000000000000"), +("0000100000001000"), +("0000000000000000"), +("0000010000000000"), +("0000000000010000"), +("0000000100000000"), +("0000000000100000") +); + +-- rocket image no 2 +signal rocket_image_2 : rocket_image := ( +("0000000010000000"), +("0000000000000000"), +("0000000000010000"), +("0000000100000000"), +("0100000000000000"), +("0000100000100000"), +("0000000000000000"), +("0100100000010000"), +("0000000000000000"), +("0000000000001000"), +("0000010000000000"), +("0000000000000000"), +("0000000100001000"), +("0000000000000000"), +("0000000001010000"), +("0000000000000000") +); + +-- rocket image no 3 +signal rocket_image_3 : rocket_image := ( +("0000000100000000"), +("0000000000100000"), +("0000000000000000"), +("0000001000000000"), +("0000000000000000"), +("1000000000100000"), +("0001000000010000"), +("0000000000000000"), +("0000000000001000"), +("0100000000000000"), +("0000010000000000"), +("0000001000000100"), +("0000000010000000"), +("0000000000101000"), +("0000000000000000"), +("0000000000000000") +); + +----------------------------------------------------------------------------// + +begin + +I_rocket_hor <= rocket_hor; +I_rocket_ver <= rocket_ver; + +image_line <= -- DECODE + rocket_image_0 (I_rocket_hor) when image_select = 0 else + rocket_image_1 (I_rocket_hor) when image_select = 1 else + rocket_image_2 (I_rocket_hor) when image_select = 2 else + rocket_image_3 (I_rocket_hor); + +rocket_engine_flame <= +-- please note that the flame diodes are connected to other parts of the +-- 74150 than what they appear looking at the diode matrix on the +-- Computer Space schematics. +-- Also note that pin 8 is equal to "I_rocket_ver = 0" + + (diode_left_column or diode_right_column) when (image_select = 0 and + I_rocket_ver = 7) else + + diode_left_column when (image_select = 1 and I_rocket_ver = 5) else + + diode_right_column when (image_select = 1 and I_rocket_ver = 6) else + + diode_left_column when (image_select = 2 and I_rocket_ver = 3) else + + diode_right_column when (image_select = 2 and I_rocket_ver = 4) else + + diode_left_column when (image_select = 3 and I_rocket_ver = 1) else + + diode_right_column when (image_select = 3 and I_rocket_ver = 3) else + + '0'; + +out_image_bit <= image_line (I_rocket_ver) or rocket_engine_flame; + +end rocket_diode_images_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_rotate.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_rotate.qip new file mode 100644 index 00000000..320dc837 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_rotate.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rocket_rotate.vhd"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_rotate.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_rotate.vhd new file mode 100644 index 00000000..15c06db2 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_rotate.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: rocket_rotate.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY rocket_rotate IS + PORT + ( + address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END rocket_rotate; + + +ARCHITECTURE SYN OF rocket_rotate IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "rotate_8_11.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2048, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + widthad_a => 11, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "rotate_8_11.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "rotate_8_11.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_rotate.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_rotate.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_rotate.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_rotate.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_rotate_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting.qip new file mode 100644 index 00000000..27a0f2c5 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rocket_shooting.vhd"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting.vhd new file mode 100644 index 00000000..8db6b9da --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: rocket_shooting.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY rocket_shooting IS + PORT + ( + address : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END rocket_shooting; + + +ARCHITECTURE SYN OF rocket_shooting IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "rocket_shooting_8_11.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 8192, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + widthad_a => 13, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "rocket_shooting_8_11.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "rocket_shooting_8_11.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_shooting.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_shooting.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_shooting.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_shooting.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rocket_shooting_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting_8_11.hex b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting_8_11.hex new file mode 100644 index 00000000..c0fa8d01 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_shooting_8_11.hex @@ -0,0 +1,629 @@ +:2000000002FEFBFFF8F7FDF9FD01FF0403FD0201FB0202FF0606060A030206FFFE03FE02D8 +:2000200006020504FD00FFF7FDFDF90200FD02FDFBFFF8F8FEFAFD03000405FE0203FC01E0 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+:204E4000FDFDFDF7FBFAF6FBFCF7FBFAF6FBF9F9FFFCFE05000004FEFF02FF02040206079E +:094E60000505040204010103022E +:00000001FF diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_thrust.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_thrust.qip new file mode 100644 index 00000000..745c795e --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_thrust.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rocket_thrust.vhd"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_thrust.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_thrust.vhd new file mode 100644 index 00000000..ee166fd8 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/rocket_thrust.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: rocket_thrust.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY rocket_thrust IS + PORT + ( + address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END rocket_thrust; + + +ARCHITECTURE SYN OF rocket_thrust IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "thrust_8_11.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 4096, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + widthad_a => 12, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "thrust_8_11.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "thrust_8_11.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +-- Retrieval info: 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+----------------------------------------------------------------------------- +-- SAUCER DIODE IMAGE -- +-- For use with Computer Space FPGA emulator -- +-- emulates saucer diode matrix on -- +-- Computer Space's Motion Board -- +-- -- +-- This entity is implementation agnostic -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; + +--80--------------------------------------------------------------------------| + +entity saucer_diode_image is + port( + saucer_enable : in std_logic; + + -- address the vertical slices + -- of the saucer diode matrix image + saucer_ver : in integer range 0 to 7; + + -- address the horizontal slices + -- of the saucer diode matrix image + saucer_hor : in integer range 0 to 15; + + saucer_diode_rotating_light : in std_logic; + out_saucer_image_bit : out std_logic + ); +end saucer_diode_image; + +architecture saucer_diode_image_architecture + of saucer_diode_image is + +type image_line_8_bit is array (0 to 7) + of std_logic; + +type saucer_image is array(0 to 15) + of image_line_8_bit; + +-- defining signal to load images +-- from the arrays +signal image_line : image_line_8_bit; +signal I_saucer_hor : integer range 0 to 15; +signal I_saucer_ver : integer range 0 to 7; +signal saucer_rotating_light_bit : std_logic; + +-- Saucer image +signal saucer_image_1 : saucer_image := ( +("00001000"), +("00000000"), +("01000010"), +("00000000"), +("00000000"), +("01000010"), +("10000001"), +("00000000"), +("00000000"), +("10000001"), +("01000010"), +("00000000"), +("00000000"), +("01000010"), +("00000000"), +("00001000") +); + +---------------------------------------------------------------------------// + +begin + +I_saucer_hor <= saucer_hor; -- 0 - 15 slices +I_saucer_ver <= saucer_ver; -- 0 - 7 pixels per slice + +image_line <= saucer_image_1 (I_saucer_hor); + +-- add saucer rotating light when column 4 is read +saucer_rotating_light_bit <= + saucer_diode_rotating_light when I_saucer_ver = 4 else + '0'; + +out_saucer_image_bit <= + (image_line (I_saucer_ver) or + saucer_rotating_light_bit) when saucer_enable = '0' else + '0'; + --- impacted by saucer enable on strobe input + +end saucer_diode_image_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting.qip b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting.qip new file mode 100644 index 00000000..b212d849 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "saucer_shooting.vhd"] diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting.vhd new file mode 100644 index 00000000..70b76f21 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: saucer_shooting.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY saucer_shooting IS + PORT + ( + address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END saucer_shooting; + + +ARCHITECTURE SYN OF saucer_shooting IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "saucer_shooting_8_11.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 4096, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + widthad_a => 12, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "saucer_shooting_8_11.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "saucer_shooting_8_11.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL saucer_shooting.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL saucer_shooting.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL saucer_shooting.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL saucer_shooting.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL saucer_shooting_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting_8_11.hex b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting_8_11.hex new file mode 100644 index 00000000..0a48af01 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/saucer_shooting_8_11.hex @@ -0,0 +1,209 @@ +:2000000001010100000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF00FFFF00FF0001FF000100ED +:2000200001010001010001010002010002000001FFFF01FFFF01FE0001FE0000FE0000FEBD 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00000000..e187403d --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/scan_counter.vhd @@ -0,0 +1,286 @@ +----------------------------------------------------------------------------- +-- ORIGINAL SCAN COUNTERS, SYNC, BLANK, ENABLE, STARS -- +-- For use with Computer Space FPGA emulator. -- +-- Implemented as part of the Sync Star Board. -- +-- Emulates the original timing (sort of progressive NTSC) for: -- +-- > scan counter logic (horizontal and vertical scan counters) -- +-- > count enable/blanking -- +-- > sync out logic -- +-- > star generation circuit -- +-- -- +-- This entity is implementation agnostic -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library work; + +--80---------------------------------------------------------------------------| + +entity scan_counter is + port( + game_clk : in std_logic; + hsync : out std_logic; + vsync : out std_logic; + star_video_out, + count_enable : out std_logic:= '0'; + blank : out std_logic:= '1'; + b2_12 : out std_logic; + vertical, horizontal : out std_logic_vector (7 downto 0) + ); +end scan_counter; + +architecture scan_counter_architecture of + scan_counter is + +-- 8 bit counter used for star generation +component v74161 is +port ( CLK, CLRN, LDN, ENP, ENT : in std_logic; + D : in unsigned (7 downto 0); + Q : out unsigned (7 downto 0); + RCO : out std_logic ); +end component; + +-- statemachine +type STATE_TYPE is (sLINE, sSYNC_BLANK); + +signal state : STATE_TYPE := sSYNC_BLANK; + +-- signals for +-- video signalling +signal hcount : integer :=130; +signal vcount : integer :=1; +signal blank_buffer : std_logic ; + +signal hor_scan_q : std_logic_vector (7 downto 0) + := "10000010"; +signal ver_scan_q : std_logic_vector (7 downto 0) + := "00000001"; + +signal hblank, vblank : std_logic; + +-- signals for star generation logic +signal b5_10, b1_6, b1_5, b1_4 : std_logic; +signal b1_3, b1_2, b1_1,b1_9, b2_8 : std_logic; + +signal a1_7, a1_6, a1_4, a1_3, a1_2 : std_logic; +signal a1_1, a1_9, b1_10, a1_15 : std_logic; + +signal SB_16 : std_logic; +signal b2_6 : std_logic; + +-- initial value for count enable +-- flip-flop +signal c4_14 : std_logic :='1'; + +-- iniital value for rco +signal e1_15_old : std_logic :='0'; +signal e1_15 : std_logic :='0'; + +-- scan counter signals +signal d1_e1_9, c1_f1_9, c1_f1_2 : std_logic; +signal e1_6, d1_4, d1_3 : std_logic; + +signal f1_15 : std_logic := '0'; +signal b2_4 : std_logic; +signal h1_11 : std_logic; +signal d1_13, d1_12 : std_logic; +signal c1_11, c1_12, c1_14, + f1_12, f1_13 : std_logic; + +signal star_enable : std_logic; + +----------------------------------------------------------------------------// +begin + +b2_12 <= game_clk; +b5_10 <= not game_clk; + +----------------------------------------------------------------------------- +-- GENERATE SYNC SIGNAL AND SCAN COUNTER VALUES -- +-- -- +-- replaces/emulates scan counter logic, count enable/blanking: -- +-- 74161s; D1, E1, C1, F1 -- +-- 7476 C4 (pin 1,2,3,4, 14, 15,1 6) -- +-- 7404 B2 (pin 3,4 and pin 5,6) -- +-- 7400 H1 (pin 11,12,13) -- +-- -- +-- replaces/emulates sync out logic: -- +-- 7420 J2 (j2_12) -- +-- 7486 J1 (j1_3) -- +-- 7420 F2 (f2_8) -- +-- 7486 J1 (j1_11) -- +----------------------------------------------------------------------------- +-- 5,842 mhz version + +----------------------------------------------------------------------------- +-- SCAN COUNTER -- +----------------------------------------------------------------------------- +process (game_clk) +begin +if rising_edge (game_clk) then + + case state is + + when sSYNC_BLANK => + + star_enable <= '0'; + + if hcount < 255 then + hcount <= hcount + 1; + hor_scan_q <= hor_scan_q + 1; + if hcount = 159 then hsync <= '1'; end if; + if hcount = 191 then hsync <= '0'; end if; + else + hcount <= 0; + hor_scan_q <= "00000000"; + c4_14 <= '1'; -- CE + star_enable <= '1'; + state <= sLINE; + hblank <= '0'; + end if; + + when sLINE => + + if hcount < 255 then -- visible line + hcount <= hcount + 1; + hor_scan_q <= hor_scan_q + 1; + + else -- last pixel on visible line + hcount <= 130; -- load value for blank&sync + hor_scan_q <= "10000010"; + c4_14 <= '0'; -- BLANK (not CE) + state <= sSYNC_BLANK; + + hblank <= '1'; + if vcount = 239 then vblank <= '1'; end if; + + if vcount < 254 then -- Increase vertical count + vcount <= vcount + 1; + ver_scan_q <= ver_scan_q +1; + + elsif vcount = 254 then + vcount <= vcount + 1; + ver_scan_q <= ver_scan_q +1; + f1_15 <= '1'; + + else + vcount <= 1; + vblank <= '0'; + ver_scan_q <= "00000001"; + f1_15 <= '0'; + star_enable <= '0'; + + end if; + end if; + + end case; +end if; +end process; + +d1_13 <= hor_scan_q(1); +d1_12 <= hor_scan_q(2); + +c1_14 <= ver_scan_q(0); +c1_12 <= ver_scan_q(2); +c1_11 <= ver_scan_q(3); + +f1_13 <= ver_scan_q(5); +f1_12 <= ver_scan_q(6); + +----------------------------------------------------------------------------- +-- Clear signal to star generator -- +----------------------------------------------------------------------------- +b2_6 <= not f1_15; + +----------------------------------------------------------------------------- +-- CREATING THE SYNC SIGNAL -- +----------------------------------------------------------------------------- +vsync <= vblank; + +----------------------------------------------------------------------------- +-- COUNT ENABLE & BLANK -- +----------------------------------------------------------------------------- +count_enable <= c4_14; +blank <= hblank or vblank; + +----------------------------------------------------------------------------- +-- SCAN COUNTER VALUES -- +----------------------------------------------------------------------------- +horizontal <= hor_scan_q; +vertical <= ver_scan_q; + +----------------------------------------------------------------------------- +-- GENERATE STAR VIDEO -- +-- Signetics 74161: B1 & A1 -- +-- using one 8-bit counter instead of two 4-bit counters -- +-- -- +-- Instead of using c4_14 to drive the ENT (b1_10) a separate enable -- +-- signal (star_enable) is used in order to overcome a "deviation" in the -- +-- Signetics 74161 chip, that Computer Space uses, from the "standard" -- +-- 74161 implementations. -- +-- The Signetics 74161 allows one counter increment when ENT is low, -- +-- in the case ENT goes low when the clock is also low. -- +-- "Standard" 74161 (eg TI and others) prohibits increments all the time -- +-- when ENT is low. -- +-- The star layout on screen is a result of this deviation in Signetics -- +-- implementation of the 74161 counter. A deviation that took a very long -- +-- time to uncover. It was not until measurement data from a real -- +-- Computer Space Board was compared with standard 74161 chip behaviour -- +-- that this piece of the puzzle was solved. -- +-- -- +-- The implementation uses standard 74161 logic and a work-around with a -- +-- delayed ENT signal (star_enable) -- +----------------------------------------------------------------------------- +star_counter: v74161 +port map( + clk => b5_10, + clrn => b1_1, + ldn => b1_9, + enp => '1', + ent => b1_10, + D(7) => a1_6, + D(6) => '0', + D(5) => a1_4, + D(4) => a1_3, + D(3) => b1_6, + D(2) => b1_5, + D(1) => b1_4, + D(0) => b1_3, + rco => a1_15 + ); + +b1_6 <= d1_13; -- equals to d1_13; +b1_5 <= c1_12; +b1_4 <= c1_11; +b1_3 <= c1_14; + +b1_1 <= b2_6; -- rco for msb +b1_9 <= b2_8; + +b1_10 <= star_enable; -- using an additional flag + -- called star_enable + -- (should be c4_14) + -- to cater for the fact that + -- the CS Signetics 74161 has + -- an odd implementation of + -- the standard 74161 + -- related to how ENT impact + -- increment when ENT is set + -- to low when clock is low + +a1_6 <= d1_12; +a1_4 <= f1_13; +a1_3 <= f1_12; + +b2_8 <= not a1_15; + +star_video_out <= a1_15; + +end scan_counter_architecture; diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/scandoubler.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sigma_delta_dac.v b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sigma_delta_dac.v new file mode 100644 index 00000000..ddc79f1f --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=15) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= 1; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= ~SigmaLatch[MSBI+2]; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sound.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sound.vhd new file mode 100644 index 00000000..017ad0d9 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sound.vhd @@ -0,0 +1,377 @@ +----------------------------------------------------------------------------- +-- SOUND LOGIC -- +-- For use with Computer Space FPGA emulator -- +-- Sound stored in DE0 nano embedded fpga memory as "ROM IP Component" -- +-- The sounds are: 8 bit @ 11kHz -- +-- -- +-- sounds are: -- +-- > rocket rotate -- +-- > rocket thrust -- +-- > rocket missile shooting -- +-- > explosion -- +-- > saucer missile shooting -- +-- > background ambience sound -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use IEEE.std_logic_signed.all; +use IEEE.std_logic_unsigned.all; +library work; + +--80---------------------------------------------------------------------------| + +entity sound is + port ( + clock_50, audio_gate : in std_logic; + + sound_switch : in std_logic_vector (7 downto 0); + -- sound_switch(1): rocket rotate + -- sound_switch(2): rocket thrust + -- sound_switch(3): rocket missile + -- sound_switch(4): explosion + -- sound_switch(5): saucer missile + -- sound_switch(7): background ambience + + -- 16 bit wav to be used as input + -- to sigma delta audio dac logic. + -- just a normal raw wav file without + -- the wav header + sigma_delta_wav : out signed (15 downto 0) + ); + +end sound; + + +architecture sound_architecture + of sound is + +component rocket_rotate is + port ( + address : in STD_LOGIC_VECTOR (10 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + +component rocket_thrust is + port ( + address : in STD_LOGIC_VECTOR (11 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + +component rocket_shooting is + port ( + address : in STD_LOGIC_VECTOR (12 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + +component explosion is + port ( + address : in STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + +component saucer_shooting is + port ( + address : in STD_LOGIC_VECTOR (11 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + +component bakam is + port ( + address : in STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + + +type state_type is (FREQ_COUNT, READ_BYTE, MERGE_SOUNDS); + +signal state : state_type := FREQ_COUNT; + +-- memory clock +signal fm_clock : std_logic; + +signal reset : std_logic := '1'; + +signal sample_rate_count : integer := 1; + +-- memory low and high bytes +signal fm_data_low_1, fm_data_low_2 : signed (7 DOWNTO 0); +signal fm_data_low_3, fm_data_low_4 : signed (7 DOWNTO 0); +signal fm_data_low_5, fm_data_low_7 : signed (7 DOWNTO 0); + +-- current sound memory +-- addresses for each sound 1-7 +signal sound_adr_1 : STD_LOGIC_VECTOR (10 DOWNTO 0); +signal sound_adr_1_num : natural range 0 to 1042303; +-- for comparisons + +signal sound_adr_2 : STD_LOGIC_VECTOR (11 DOWNTO 0); +signal sound_adr_2_num : natural range 0 to 1042303; +-- for comparisons + +signal sound_adr_3 : STD_LOGIC_VECTOR (12 DOWNTO 0); +signal sound_adr_3_num : natural range 0 to 1042303; +-- for comparisons + +signal sound_adr_4 : STD_LOGIC_VECTOR (13 DOWNTO 0); +signal sound_adr_4_num : natural range 0 to 1042303; +-- for comparisons + +signal sound_adr_5 : STD_LOGIC_VECTOR (11 DOWNTO 0); +signal sound_adr_5_num : natural range 0 to 1042303; +-- for comparisons + +signal sound_adr_7 : STD_LOGIC_VECTOR (13 DOWNTO 0); +signal sound_adr_7_num : natural range 0 to 1042303; +-- for comparisons + +-- hard coded sound memory +-- address intervals for each +-- sound 1-7 + +signal sound_adr_4_state : std_logic := '0'; + -- initial state + +-- not using bit 0, +-- only bit 1 to 5 + +signal sound_prev : std_logic_vector (6 downto 0) + :="0000000" ; + +--signals for audio codec +signal fm_data_16_bit : signed (8 DOWNTO 0) + :="000000000"; + +signal rocket_rotate_rom_read : STD_LOGIC_VECTOR (7 DOWNTO 0) ; +signal rocket_thrust_rom_read : STD_LOGIC_VECTOR (7 DOWNTO 0) ; +signal rocket_shooting_rom_read : STD_LOGIC_VECTOR (7 DOWNTO 0) ; +signal background_ambience_rom_read : STD_LOGIC_VECTOR (7 DOWNTO 0) ; +signal explosion_rom_read : STD_LOGIC_VECTOR (7 DOWNTO 0) ; +signal saucer_shooting_rom_read : STD_LOGIC_VECTOR (7 DOWNTO 0) ; + + +------------------------------------------------------------------------------- +begin + +----------------------------------------------------------------------------- +-- rocket rotate sound ROM -- +----------------------------------------------------------------------------- +rocket_rotate_sound : component rocket_rotate + port map ( + address => sound_adr_1, + clock => clock_50, + q => rocket_rotate_rom_read + ); + +rocket_thrust_sound : component rocket_thrust + port map ( + address => sound_adr_2, + clock => clock_50, + q => rocket_thrust_rom_read + ); + + +rocket_shooting_sound : component rocket_shooting + port map ( + address => sound_adr_3, + clock => clock_50, + q => rocket_shooting_rom_read + ); + +explosion_sound : component explosion + port map ( + address => sound_adr_4, + clock => clock_50, + q => explosion_rom_read + ); + +saucer_shooting_sound : component saucer_shooting + port map ( + address => sound_adr_5, + clock => clock_50, + q => saucer_shooting_rom_read + ); + + +background_ambience : component bakam + port map ( + address => sound_adr_7, + clock => clock_50, + q => background_ambience_rom_read + ); + +----------------------------------------------------------------------------- +-- Sound sample retrieval -- +-- sound by sound, sample by sample -- +-- 11 kHz -- +-- 8 bit -- +----------------------------------------------------------------------------- +process (clock_50) +begin + if rising_edge (clock_50)then + if audio_gate = '1' then + + sound_prev(4) <= sound_switch(4); + + case state is + + when FREQ_COUNT => + sample_rate_count <= sample_rate_count +1; + if sample_rate_count > 4535 then -- 12kHz + state <= READ_BYTE; + sample_rate_count <= 1; + else + state <= FREQ_COUNT; + end if; + + if sound_prev(4) = '0' and sound_switch(4) = '1' then + -- explosion single shot verification, '0' means ready for + -- single shot + sound_adr_4_state <= '1'; -- '1' means single shot ongoing + sound_adr_4 <= (others => '0'); -- set to start of sound + sound_adr_4_num <= 0; -- set to start of sound + end if; + + when READ_BYTE => -- read byte + + -- 1 = rocket rotate + if sound_switch(1) = '1' then + fm_data_low_1 <= signed (rocket_rotate_rom_read); + else + fm_data_low_1 <= "00000000"; -- set to '0' if sound is not on + end if; + + -- 2 = rocket thrust + if sound_switch(2) = '1' then + fm_data_low_2 <= signed (rocket_thrust_rom_read); + -- read sample if sound is active + else + fm_data_low_2 <= "00000000"; -- set to '0' if sound is not on + end if; + + -- 3 = rocket shooting + if sound_switch(3) = '1' then + fm_data_low_3 <= signed (rocket_shooting_rom_read); + -- read sample if sound is active + else + fm_data_low_3 <= "00000000"; -- set to '0' if sound is not on + end if; + + -- 4 = rocket & saucer explosion + if sound_adr_4_state = '1' then -- single shot ongoing + fm_data_low_4 <= signed (explosion_rom_read); + -- read sample if sound is active + else + fm_data_low_4 <= "00000000"; -- set to '0' if sound is not on + end if; + + -- 5 = saucer shooting + if sound_switch(5) = '1' then + fm_data_low_5 <= signed (saucer_shooting_rom_read); + -- read sample if sound is active + else + fm_data_low_5 <= "00000000"; -- set to '0' if sound is not on + end if; + + -- 7 = background ambience + fm_data_low_7 <= signed (background_ambience_rom_read); + + -- increase adress pointers + -- 1 = rocket rotate : loop + if sound_adr_1_num < 4529 then + sound_adr_1 <= sound_adr_1 + 1; + sound_adr_1_num <= sound_adr_1_num + 1; + else + sound_adr_1 <= (others => '0'); + sound_adr_1_num <= 0; + end if; + + -- 2 = rocket thrust : loop + if sound_adr_2_num < 5067 then + sound_adr_2 <= sound_adr_2 + 1; + sound_adr_2_num <= sound_adr_2_num + 1; + else + sound_adr_2 <= (others => '0'); + sound_adr_2_num <= 0; + end if; + + -- 3 = rocket shooting : loop + if sound_adr_3_num < 20072 then + sound_adr_3 <= sound_adr_3 + 1; + sound_adr_3_num <= sound_adr_3_num + 1; + else + sound_adr_3 <= (others => '0'); + sound_adr_3_num <= 0; + end if; + + + -- 4 = rocket & saucer explosion/single shot + -- no loop + if sound_adr_4_num < 8781 then + sound_adr_4 <= sound_adr_4 + 1; + sound_adr_4_num <= sound_adr_4_num + 1; + else + sound_adr_4_state <= '0'; -- single shot ongoing <= '1'; + -- single shot is complete + sound_adr_4 <= (others => '0'); + sound_adr_4_num <= 0; + end if; + + -- 5 = saucer shooting : loop + if sound_adr_5_num < 6636 then + sound_adr_5 <= sound_adr_5 + 1; + sound_adr_5_num <= sound_adr_5_num + 1; + else + sound_adr_5 <= (others => '0'); + sound_adr_5_num <= 0; + end if; + + -- 7 = background ambience : loop + if sound_adr_7_num < 13874 then + sound_adr_7 <= sound_adr_7 + 1; + sound_adr_7_num <= sound_adr_7_num + 1; + else + sound_adr_7 <= (others => '0'); + sound_adr_7_num <= 0; + end if; + + state <= MERGE_SOUNDS; + + when MERGE_SOUNDS => -- read byte + -- transfer read data and fix endian (from little endian to big endian) + + sigma_delta_wav <=(fm_data_low_1(7) & fm_data_low_1(7) & fm_data_low_1 & "000000") + + (fm_data_low_2(7) & fm_data_low_2(7) & fm_data_low_2 & "000000") + + (fm_data_low_3(7) & fm_data_low_3(7) & fm_data_low_3 & "000000") + + (fm_data_low_4(7) & fm_data_low_4(7) & fm_data_low_4 & "000000") + + (fm_data_low_5(7) & fm_data_low_5(7) & fm_data_low_5(7) & fm_data_low_5 & "00000") + + (fm_data_low_7(7) & fm_data_low_7(7) & fm_data_low_7 & "000000"); + + state <= FREQ_COUNT; + + when others => + state <= FREQ_COUNT; + + end case; + end if; + end if; +end process; + +end sound_architecture; diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sync_star_board.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sync_star_board.vhd new file mode 100644 index 00000000..55bec5d0 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/sync_star_board.vhd @@ -0,0 +1,1368 @@ +----------------------------------------------------------------------------- +-- SYNC STAR BOARD -- +-- For use with Computer Space FPGA emulator -- +-- Implementation of Computer Space's Sync Star Board -- +-- "wire by wire" and "component by component"/"gate by gate" based on -- +-- original schematics. -- +-- With exceptions regarding: -- +-- > start/stop & replay logic (impl as state machine instead) -- +-- > analogue/discrete based timers (impl as counters) -- +-- > scan counter, sync and star generation logic -- +-- - implemented in separate entity to provide interlaced ntsc -- +-- video and overcome Signetics 74161 deviation that impacts -- +-- star generation -- +-- > all flip flops which use asynch clock inputs are replaced with -- +-- flip flops driven by high freq clock and logic to identify -- +-- edge changes on the logical clock input -- +-- -- +-- There are plenty of comments throughout the code to make it easier to -- +-- understand the logic, but due to the sheer number of comments there -- +-- may exist occasional mishaps. -- +-- -- +-- This entity is implementation agnostic. -- +-- -- +-- Naming convention: -- +-- Signals are labelled after the component that generates the signal; -- +-- more specifically the component's schematics label and the specific -- +-- output. For instance: NOR gate F6 and its output pin 10 generate a -- +-- signal which will be labelled f6_10. -- +-- Occasionally signals are labelled after a component input - this is -- +-- most common for components where the input is exposed -- +-- to "component-internal processing" beyond simple gate functionality, -- +-- such as bistable latches, counters, flip-flops and multiplexers. -- +-- Sync Star Board inputs/outputs are labelled SB_, where is -- +-- according to original schematics input/output labels. -- +-- -- +-- v1.0 -- +-- by Mattias G, 2015 -- +-- Enjoy! -- +----------------------------------------------------------------------------- + + +library ieee; +USE ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +library work; + +--80--------------------------------------------------------------------------| + + +entity sync_star_board is + port ( + reset, + game_clk -- Fundamental game + -- clock for the whole game's + -- logical timing + -- Only used when + -- video_signal_type is + -- set to '1' (ie emulating + -- original video signalling) + : in std_logic; + super_clk, -- Clock to emulate + -- asynch flip flop logic + + explosion_clk, + seconds_clk : in std_logic; + + SB_3, -- Saucer Enable + -- signals that the TV beam + -- is "sweeping" by the current + -- position of one of the + -- two 16 x 8 pixel + -- saucer image grids + SB_4, -- Saucer Missile + -- signals that the TV beam + -- is "sweeping" by the current + -- pixel position of an active + -- saucer missile + SB_6, -- Rocket Missile + -- signals that the TV beam + -- is "sweeping" by the current + -- pixel position of an active + -- rocket missile + SB_7, -- "start button pressed" signal + SB_C, -- "coin inserted" signal + SB_E, -- Rocket Enable + -- signals that the TV beam + -- is "sweeping" by the current + -- position of the 16 x 16 pixel + -- rocket image grid + SB_N -- rocket & saucer video mix signal + : in std_logic; + + SB_2, -- Saucer Video Enable + -- active when saucer + -- can be drawn onto screen (ie its not + -- in the "pause" state after a + -- hit or collision) + SB_5, -- Rocket Video Enable + -- active when rocket + -- can be drawn onto screen (ie its not + -- in the "pause" state after an + -- explosion or collision, and its + -- ongoing game play) + SB_H, -- Count Enable + -- active during the + -- visible part of the screen to signal + -- that objects can be moved and drawn + -- onto screen + SB_K, -- audio gate; active when game is on + -- to open up for audio + SB_L, -- signal to trigger explosion + -- audio sample + SB_M, -- spin; signal to spin rocket + -- after being hit by saucer missile, + -- active when spinning + SB_Y -- inverse clock out + : out std_logic; + + -- signals for + -- composite video / instead of SB_20 + hsync : out std_logic; + vsync : out std_logic; + composite_video_signal : out std_logic; + blank : out std_logic + ); + +end sync_star_board; + +architecture sync_star_board_architecture of + sync_star_board is + +component scan_counter is + port ( + game_clk : in std_logic; + hsync : out std_logic; + vsync : out std_logic; + star_video_out : out std_logic; + count_enable : out std_logic; + blank : out std_logic; + b2_12 : out std_logic; + vertical, horizontal : out std_logic_vector (7 downto 0) + ); +end component; + +-- statemachine for coin detection, +-- start game and indicate "game on" +type STATE_TYPE is +(IDLE, COIN_INSERTED, GAME_ON); + +signal count_enable, a1_15, c4_14 : std_logic; + +-- signals for score & time display logic +signal j4_8, j2_8, h3_8, h3_6, j3_8, + j3_6, j3_12, h3_12 : std_logic; +signal g3_9, g3_10, g3_11, g3_12, + g3_13, g3_14, g3_15 : std_logic; +signal e5_2 : std_logic; + +signal g3_out : std_logic_vector (6 downto 0); +signal g3_in : std_logic_vector (3 downto 0); + +signal g1_8, d2_13, d2_10, c2_6 : std_logic; +signal d1_11, d1_12, d1_13, c1_11, + c1_12, c1_13 : std_logic; +signal c2_3 : std_logic; +signal g3_7, g3_1, g3_2, g3_6 : std_logic; +signal f1_11, f1_12, f1_13, f1_14, + e1_11, e1_12, e1_13, e1_14 : std_logic; +signal j2_6, h1_8, g1_6, f2_6, g2_8, + g2_6, e2_6, e2_8, b2_2, d2_4, + d2_1 : std_logic; +signal h2_13, h2_4, h2_10, g1_12, h1_3 : std_logic; + +signal horizontal_position : std_logic_vector (7 downto 0) + := "00000000"; +signal vertical_position : std_logic_vector (7 downto 0) + := "00000000"; + +-- signals for score and time keeping +signal f3_3, f3_4, f3_5, f3_6, + f3_10, f3_11, f3_12, f3_13, + f3_14, f3_2, f3_7, f3_9 : std_logic; +signal a3_3, a3_4, a3_5, + a3_6, a3_10, a3_11, a3_12, + a3_13, a3_14, a3_2, a3_7, a3_9 : std_logic; + + +signal d3_14, d3_2 : std_logic; +signal e3_14, e3_2 : std_logic; +signal h1_6, c5_6, e5_8 : std_logic; +signal e3_12, e3_11, e3_9, e3_8 : std_logic; +signal d3_12, d3_11, d3_9, d3_8 : std_logic; +signal c3_14, c3_2, c3_12, c3_11, + c3_9, c3_8 : std_logic; +signal b3_14, b3_2, b3_12, + b3_11, b3_9, b3_8 : std_logic; + +signal b3_count : std_logic_vector (3 downto 0); +signal c3_count : std_logic_vector (3 downto 0); +signal d3_count : std_logic_vector (3 downto 0); +signal e3_count : std_logic_vector (3 downto 0); +signal a2_A, a2_B : std_logic_vector (3 downto 0); + +-- signals for replay +signal a2_3, a2_4, a2_5, a2_6, + a2_10, a2_11, a2_12, + a2_13, a2_15 : std_logic; +signal c2_11 : std_logic; + +signal SB_F : std_logic; + +-- signals for explosion circuitry logic +signal a6_8, h2_1, a6_3, a6_11, + a6_6, e2_13, e2_4, + e2_10, j5_3, c5_8, c5_11 : std_logic; +signal b6_1 : std_logic :='1'; +signal b5_11, b5_13, b5_12 : std_logic; +signal b5_3, b5_1, b5_2 : std_logic; +signal a5_3, a5_1, a5_2 : std_logic; +signal a4_12, d4_6 : std_logic; +signal b4_1, b4_3, b4_4, b4_16 : std_logic; +signal b4_6, b4_9, b4_12, b4_8 : std_logic; +signal c4_6, c4_9, c4_12, c4_8 : std_logic; + +-- q output from flip flops that +-- need initial value +signal a5_5, b5_5, b5_9, + b4_15, b4_11, c4_11 : std_logic :='0'; + +-- qn output from flip flops that +-- need initial value +signal a5_6, b5_6, b5_8, b4_10, c4_10 : std_logic :='1'; + +signal a4_8, a4_6, d4_8, j1_6 : std_logic; +signal a5_3_1, b5_3_1, b5_11_13, + c4_6_8, b4_6_8, b4_1_3 : std_logic; + +-- signals for start/end game +-- circuitry logic +signal SB_D, SB_B : std_logic; +--signal SB_7_old : std_logic :='1'; +signal SB_C_old : std_logic :='1'; + +-- game clock +signal b2_12 : std_logic; + +signal e3_10, c5_3 : std_logic; +signal e5_12 : std_logic :='1'; +signal d6_6 : std_logic :='0'; +signal d6_8 : std_logic :='1'; +signal a5_11, a5_12, a5_10 : std_logic; +signal a5_9 : std_logic :='0'; +signal a5_8 : std_logic :='1'; +signal c2_8 : std_logic; +signal d5_1, d5_3, d5_2 : std_logic; +signal e5_10 : std_logic := '0'; +signal d5_6 : std_logic :='1'; +signal d5_13, d5_11, d5_12, d5_10 : std_logic; +signal d5_9 : std_logic := '0'; +signal d5_8 : std_logic := '1'; +signal c6_5, c6_6, c6_1 : std_logic; + +signal state : STATE_TYPE := IDLE; + +-- signals to manage asynchronous +-- clock design embedded in +-- synchronous clk solutions +signal b5_3_old, a5_3_old : std_logic; +signal c4_6_old, b4_6_old, + b4_1_old, b5_11_old : std_logic; +signal d5_11_old, d5_3_old : std_logic := '1'; +-- set to initial '1' as the initial +-- signal is also '1', +-- to avoid trigger of game +-- start directly + +signal e3_14_old, d3_14_old, + c3_14_old, b3_14_old : std_logic := '0'; + +-- signal for composite +-- star video generation +signal star_video : std_logic; + +-- signals for external buttons +-- and coin mechanism +signal signal_ccw, signal_cw, + signal_thrust, signal_fire, + signal_start, signal_coin : std_logic; + +-----------------------------------------------------------------------------// +begin + +----------------------------------------------------------------------------- +-- Game Clock Mapping -- +----------------------------------------------------------------------------- +SB_Y <= not b2_12; -- new + +----------------------------------------------------------------------------- +-- Composite video sync, scan counter, star generation, game clock -- +-- Corresponds to: -- +-- Sync Counter: D1, E1, C4 (pin 1-4 / 14-16), C1, F1 -- +-- b2_6, b2_4, h1_11 -- +-- Sync Generator: j2_12, j1_3, f2_8, j1_11 -- +-- Star Generator: B1, A1, b2_8 -- +-- Game Clock: b2_12 -- +-- -- +-- Logic that provides either original video signalling or interlaced -- +-- ntsc video signal. As it is not according to original schematics it is -- +-- placed in a separate entity to isolate from rest of original -- +-- schematics. Functionally it will provide "black box" output -- +-- identical to Computer Space game logic behaviour. -- +-- -- +-- Star generation also resides in the same entity to emulate a -- +-- "deviation" in the Signetics 74161 chip, that Computer Space uses, -- +-- versus the "standard" 74161 implementations. -- +-- The Signetics 74161 allows one counter increment when ENT is low, -- +-- in the case ENT goes low when the clock is also low. -- +-- "Standard" 74161 (eg TI and others) prohibits increments all the time -- +-- when ENT is low. -- +-- The star layout on screen is a result of this deviation in Signetics -- +-- implementation of the 74161 counter. A deviation that took a very long -- +-- time to uncover. It was not until measurement data from a real -- +-- Computer Space Board was compared with standard 74161 chip behaviour -- +-- that this piece of the puzzle was solved. -- +----------------------------------------------------------------------------- +sync_and_stars: component scan_counter + port map(game_clk, hsync, vsync, star_video, + count_enable, blank, b2_12, vertical_position, + horizontal_position); + +a1_15 <= star_video; +SB_H <= count_enable; +c4_14 <= count_enable; + +----------------------------------------------------------------------------- +-- Assign counter value from scan counters -- +----------------------------------------------------------------------------- +d1_11 <= horizontal_position (3); +d1_12 <= horizontal_position (2); +d1_13 <= horizontal_position (1); + +e1_11 <= horizontal_position (7); +e1_12 <= horizontal_position (6); +e1_13 <= horizontal_position (5); +e1_14 <= horizontal_position (4); + +c1_11 <= vertical_position (3); +c1_12 <= vertical_position (2); +c1_13 <= vertical_position (1); + +f1_11 <= vertical_position (7); +f1_12 <= vertical_position (6); +f1_13 <= vertical_position (5); +f1_14 <= vertical_position (4); + +----------------------------------------------------------------------------- +-- COMPOSITE VIDEO OUT -- +-- Replaces the entire discrete electronics video part in the schematics -- +-- including SB_20 - except for sync signal (which is a separate signal) -- +-- note j1_6 is steering inverse or not -- +-- a1_15 is star video NORMAL -- +-- e5_2 is score & time dislay video signal NORMAL -- +-- c4_14 is count enable -- +-- SB_N is rocket/saucer video signal -- +----------------------------------------------------------------------------- +composite_video_signal <= c4_14 and -- count enable + (j1_6 xor (SB_N or e5_2 or a1_15 or j5_3)); + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Seven Segment Display Video -- +-- Outputs the right seven-segment "pixels" depending on where the -- +-- TV beam is currently positioned -- +-- Essentially it decodes the horizontal and vertical position bits (0-3) -- +-- to map segment by segment -- +----------------------------------------------------------------------------- +j2_8 <= not (g3_9 and c1_11 and d2_13); -- segment e + +h3_8 <= not (g3_10 and c1_11 and c2_6); -- segment d + +h3_6 <= not (g3_11 and c1_11 and c2_3); -- segment c + +j3_8 <= not (g3_12 and g1_8 and c2_3); -- segment b + +j3_6 <= not (g3_13 and g1_8 and d2_10); -- segment a + +j3_12 <= not (g3_14 and g1_8 and c2_6); -- segment f + +h3_12 <= not (g3_15 and g1_8 and d2_13); -- segment g + +j4_8 <= not (j2_8 and h3_8 and h3_6 and -- segment video mix signal + j3_8 and j3_6 and j3_12 and + h3_12); + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: BCD-TO-SEVEN-SEGMENT DECODER -- +-- G3 7448 -- +-- BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS -- +-- 448 pin 1=b, pin 2=c, pin 6=d, pin 7=a -- +-- -- +-- Decode 4 bit binary into a set of active segments that represent -- +-- decimal characters (0-9), six strange symbols and one complete blank. -- +-- There are seven segments; a - g represented by 7 outputs (abcdefg). -- +-- All segments active = 11111111 (abcdefg) -- +-- no segment active = 0000000 (abcdefg) -- +-- -- +-- ---------------- EXAMPLES --------------- -- +-- -- +-- 8 = 1000 0 = 0000 2 = 0010 -- +-- a => 1111111 => 1111110 => 1101101 -- +-- ----- ----- ----- ----- -- +-- I I I I I I I -- +-- f I I b I I I I I -- +-- --g-- ----- ----- -- +-- I I I I I I I -- +-- e I I c I I I I I -- +-- ----- ----- ----- ----- -- +-- d -- +-- -- +----------------------------------------------------------------------------- +--g3_7 <= a3_7; -- flawed original schematics + -- connects the wrong bits from the time&score + -- keeping part +g3_7 <= a3_9; -- revised connection logic for bit 0 + +--g3_1 <= a3_9; -- flawed original schematics + -- connects the wrong bits from the time&score + -- keeping part +g3_1 <= a3_7; -- revised connection logic for bit 1 + +g3_2 <= f3_9; -- bit 3 +g3_6 <= f3_7; -- bit 4 + +g3_in (0) <= g3_7; -- input a +g3_in (1) <= g3_1; -- input b +g3_in (2) <= g3_2; -- input c +g3_in (3) <= g3_6; -- input d + +g3_out <= + "1111110" when g3_in = "0000" else + "0110000" when g3_in = "0001" else + "1101101" when g3_in = "0010" else + "1111001" when g3_in = "0011" else + "0110011" when g3_in = "0100" else + "1011011" when g3_in = "0101" else + "0011111" when g3_in = "0110" else + "1110000" when g3_in = "0111" else + "1111111" when g3_in = "1000" else + "1110011" when g3_in = "1001" else + "0001101" when g3_in = "1010" else + "0011001" when g3_in = "1011" else + "0100011" when g3_in = "1100" else + "1001011" when g3_in = "1101" else + "0001111" when g3_in = "1110" else + "0000000" ; + +-- segment output +g3_13 <= g3_out (6); --output segment a +g3_12 <= g3_out (5); --output segment b +g3_11 <= g3_out (4); --output segment c +g3_10 <= g3_out (3); --output segment d +g3_9 <= g3_out (2); --output segment e +g3_15 <= g3_out (1); --output segment f +g3_14 <= g3_out (0); --output segment g + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Segment display position input -- +-- Logic to determine when the TV beam's current position matches the -- +-- position required for individual segments and their "pixels" -- +-- Essentially it decodes the horizontal and vertical position bits (0-3) -- +----------------------------------------------------------------------------- +c2_6 <= c1_12 and c1_13; +d2_10 <= c1_12 nor c1_13; +d2_13 <= d1_13 nor d1_12; +c2_3 <= d1_13 and d1_12; + +g1_8 <= not c1_11; + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Rocket/Saucer Score and Time Video Enable -- +-- logic to determine when the TV beam is currently at the vertical -- +-- and horizontal position interval of the screen where either rocket -- +-- score, saucer score or time (tens & unit) shall be be displayed -- +----------------------------------------------------------------------------- +j2_6 <= not ( g2_6 and g2_8 and f2_6); -- flag that signals that + -- either rocket score, saucer + -- score or time (tens&unit) can + -- be displayed + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Score & Time Video Out -- +----------------------------------------------------------------------------- +h1_3 <= j4_8 nand j2_6; -- j4_8 is the "seven segment" video signal + -- containing the current pixel (black or white) + -- to display, given the TV beam's current + -- position, to "draw" score/time characters on + -- screen + -- j2_6 is a flag that indicates whether + -- either rocket score, saucer score or time + -- (tens & unit) should be displayed or not + -- (to avoid characters being repeated across + -- the screen) +e5_2 <= not h1_3; -- Score & Time video out signal (inversed to + -- comply with downstream logic's active level) + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: UNIT Display Enable -- +-- logic to determine when the TV beam is currently at the horizontal -- +-- position interval of the screen where UNITS shall be displayed -- +----------------------------------------------------------------------------- +b2_2 <= not e1_14; + +d2_4 <= d1_11 nor b2_2; + +e2_8 <= not (e1_11 and e1_12 and e1_13 and d2_4); -- flag signals UNIT + -- can be displayed + +g1_6 <= not e2_8; -- flag signals UNIT + -- can be displayed + -- (set to inverse + -- to fit downstream + -- active level logic) + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: TENS Display Enable -- +-- logic to determine when the TV beam is currently at the horizontal -- +-- position interval of the screen where TENS shall be displayed -- +----------------------------------------------------------------------------- +d2_1 <= e1_14 nor d1_11; + +e2_6 <= not (e1_11 and e1_12 and e1_13 and d2_1); -- Flag signals TENS + -- can be displayed + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: TENS and UNIT Display Enable -- +-- logic to determine when the TV beam is currently at the horizontal -- +-- position interval of the screen where TENS or UNIT shall be displayed -- +----------------------------------------------------------------------------- +h1_8 <= e2_6 nand e2_8; -- flag that signals that the TV beam's current + -- horizontal position is either passing + -- by the TENS position or UNIT position + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Rocket Score Display Enable -- +-- logic to determine when the TV beam is currently at the vertical -- +-- and horizontal position interval of the screen where rocket score shall -- +-- be displayed -- +----------------------------------------------------------------------------- +g1_12 <= not f1_12; + +h2_10 <= f1_11 nor g1_12; + +g2_8 <= not (g1_6 and f1_14 and f1_13 and h2_10); -- g1_6 indicates + -- proper horizontal + -- position interval + -- (for UNIT) + -- f1_11, f1_12, h2_10 + -- indicate proper + -- vertical position + -- interval + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Saucer Score Display Enable -- +-- logic to determine when the TV beam is currently at the vertical and -- +-- horizontal position interval of the screen where saucer score shall -- +-- be displayed -- +----------------------------------------------------------------------------- +h2_13 <= f1_13 nor f1_11; + +g2_6 <= not (g1_6 and f1_14 and f1_12 and h2_13); -- g1_6 indicates + -- proper horizontal + -- position interval + -- (for UNIT) + -- f1_11, f1_13, h2_13 + -- indicate proper + -- vertical position + -- interval + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Time Display Enable -- +-- logic to determine when the TV beam is currently at the vertical and -- +-- horizontal position interval of the screen where TIME shall be -- +-- displayed (both TENS and UNIT) -- +----------------------------------------------------------------------------- +h2_4 <= f1_13 nor f1_12; + +f2_6 <= not (h1_8 and h2_4 and f1_11 and f1_14); -- h1_8 indicates + -- proper horizontal + -- position interval + -- (for UNIT & TENS) + -- h2_4, f1_11, f1_14 + -- indicate proper + -- vertical position + -- interval + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Saucer Display Enable Logic -- +-- verify that saucer can actually be displayed -- +----------------------------------------------------------------------------- +a6_8 <= SB_3 nand b6_1; -- SB_3 is saucer_enable from Motion Board + -- that signals that the TV beam's position is + -- passing by any of the two saucer's 16x8 image + -- grid pixels' positions + -- b6_1 is flagging whether the saucer should + -- be visible or not (delay after collision + -- or hit) + +SB_2 <= a6_8; -- Saucer Enable to Memory Board + -- it is ok to display + -- saucer video image + -- (not to be confused with Saucer Enable + -- from Motion Board) + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket Display Enable Logic -- +-- verify that the rocket can actually be displayed -- +----------------------------------------------------------------------------- +h2_1 <= SB_E nor c5_8; -- SB_E is Rocket Enable from Motion Board + -- that signals that the TV beam's position is + -- passing by any of the rocket's 16x16 image + -- grid pixels' positions + -- c5_8 is flagging whether the rocket should + -- be visible or not (delay after collision + -- or hit) + +a6_11 <= h2_1 nand d5_9; -- Verifies that a game is playing (d5_9) + -- otherwise the rocket will not be + -- displayed + +SB_5 <= a6_11; -- Rocket Enable to Memory Board + -- it is ok to display + -- rocket video image + -- (not to be confused with Rocket Enable + -- from Motion Board) + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Saucer Missile Video Enable Logic -- +-- verify whether saucer missile can be displayed or not -- +-- if a game is on then missile will be displayed, otherwise not -- +----------------------------------------------------------------------------- +a6_3 <= SB_4 nand d5_9; -- SB_4 is saucer_missile video out + -- which is active when the TV beam's position + -- is passing by the missile pixel position + -- d5_9 is flagging whether a game is on or not + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket Missile Video Enable Logic -- +-- verify whether rocket missile can be displayed or not -- +-- if a game is on then missile will be displayed, otherwise not -- +----------------------------------------------------------------------------- +a6_6 <= SB_6 nand d5_9; -- SB_6 is rocket_missile video out + -- which is active when the TV beam's position + -- is passing by the missile pixel position + -- d5_9 is flagging whether a game is or or not + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket and Saucer Missile Video Out -- +----------------------------------------------------------------------------- +j5_3 <= a6_3 nand a6_6; -- saucer and rocket missile video out + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Detect collision and missile hit -- +----------------------------------------------------------------------------- +e2_13 <= a6_3 nor a6_11; -- detects rocket hit by saucer missile +e2_4 <= a6_8 nor a6_6; -- detects saucer hit by rocket missile +e2_10 <= a6_11 nor a6_8; -- detects rocket colliding with saucer + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Saucer Visible or Not? -- +----------------------------------------------------------------------------- +b6_1 <= b5_9 nor b5_5; -- flags whether saucer should be visible or not + -- It is not visible for a period of time + -- after it has collided with the rocket or + -- it has been hit by a rocket missile + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket Visible or Not? -- +----------------------------------------------------------------------------- +c5_11 <= a5_5 nand c4_11; -- signals that saucer should not be visible for + -- a period of time after rocket has been spinning + -- (following being hit by saucer missile) + +c5_8 <= b5_8 nand c5_11; -- signals that saucer should not be visible + -- for a period of time + -- after it has collided with a saucer (b5_8) + -- or it has been hit by a saucer missile (c5_11) + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket & Saucer Collision Flag -- +-- 7474, B5, pin 8-13 -- +-- dual d-type pos edge triggered flipflop w preset & clear -- +-- pin 13 2clrn -- +-- pin 12 2d -- +-- pin 11 2clk -- +-- pin 10 2pren -- +-- pin 9 2q -- +-- pin 8 2qn -- +-- -- +-- Flag is set when rocket and saucer collide, and reset back to normal -- +-- after a while by a timer signal (a4_8) -- +----------------------------------------------------------------------------- +b5_11 <= e2_10; -- instant collision detection feeds clk +b5_13 <= a4_8; -- timer signal a4_8 feeds clrn + +-- Check if Rocket has collided with Saucer +process (super_clk, b5_13) +begin +if b5_13 = '0' then -- clrn + b5_9 <= '0'; + -- q is cleared when clrn is active low, + -- as pren is permanently high + + b5_8 <= '1'; + -- qn is cleared when clrn is active low, + -- as pren is permanently high +elsif rising_edge (super_clk) then + b5_11_old <= b5_11; + if (b5_11_old = '0') and (b5_11 = '1') then + b5_9 <= '1'; + b5_8 <= '0'; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Saucer Hit By Rocket Missile Flag -- +-- 7474, B5, pin 1-6 -- +-- dual d-type pos edge triggered flipflop w preset & clear -- +-- pin 1 1clrn -- +-- pin 2 1d -- +-- pin 3 1clk -- +-- pin 4 1pren -- +-- pin 5 1q -- +-- pin 6 1qn -- +-- -- +-- Flag is set when saucer is hit by rocket missile and reset back to -- +-- normal after a while by a timer signal (a4_8) -- +----------------------------------------------------------------------------- +b5_3 <= e2_4; -- instant missile hit detection feeds clk +b5_1 <= a4_8; -- timer signal a4_8 feeds clrn + +-- check if Saucer is hit by Rocket missile +process (super_clk, b5_1) +begin +if b5_1 = '0' then -- clrn + b5_5 <= '0'; + -- q is cleared when clrn is active low, as pren is permanently high + + b5_6 <= '1'; + -- qn is cleared when clrn is active low, as pren is permanently high + +elsif rising_edge (super_clk) then + b5_3_old <= b5_3; + if (b5_3_old = '0') and (b5_3 = '1') then + b5_5 <= '1'; + b5_6 <= '0'; -- signal to increase score for rocket player + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket hit by Saucer Missile Flag -- +-- 7474, A5, pin 1-6 -- +-- dual d-type pos edge triggered flipflop w preset & clear -- +-- pin 1 1clrn -- +-- pin 2 1d -- +-- pin 3 1clk -- +-- pin 4 1pren -- +-- pin 5 1q -- +-- pin 6 1qn -- +-- -- +-- Flag is set when rocket is hit by saucer missile and reset back to -- +-- normal after a while by a timer signal (a4_8) -- +----------------------------------------------------------------------------- +a5_3 <= e2_13; -- instant missile hit detection feeds clk +a5_1 <= a4_8; -- timer signal a4_8 feeds clrn + +-- Check if Rocket has been hit by Saucer missile +process (super_clk, a5_1) +begin +if a5_1 = '0' then -- clrn + a5_5 <= '0'; + -- q is cleared when clrn is active low, + -- as pren is permanently high + + a5_6 <= '1'; + -- qn is cleared when clrn is active low, + -- as pren is permanently high + +elsif rising_edge (super_clk) then + a5_3_old <= a5_3; + if (a5_3_old = '0') and (a5_3 = '1')then + a5_5 <= '1'; + a5_6 <= '0'; -- signal to increase score for saucer + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Rocket spin signal -- +----------------------------------------------------------------------------- +SB_M <= a5_5; -- spin + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Collision & Explosion Timer Signal -- +-- Signals when the rocket or saucer has been hit by a missile or rocket -- +-- and saucer have collided -- +-- The signal triggers downstream collision timer to start counting the -- +-- time for collision/explosion "events" -- +----------------------------------------------------------------------------- +a4_12 <= not (a5_6 and b5_6 and b5_8); + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Fundamental clock -- +-- Creates the fundamental pulse train for timing collision and -- +-- explosion events -- +----------------------------------------------------------------------------- +d4_6 <= explosion_clk; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Frequency divider logic flipflop 1 -- +-- 7476, B4, flip flop 1 -- +-- dual master slave jk flip flop with clear -- +-- pin 1 clk 1 -- +-- pin 3 clr 1 -- +-- pin 14 qn -- +-- pin 15 q -- +-- -- +-- Overall B4 and C4(pin 6-12) -- +-- Creates the frequency pulse trains that are the basis for the timing -- +-- of explosion and collision events (such as rocket spinning, screen -- +-- inversing/"flashing", explosion sound and removing saucer/rocket from -- +-- the screen for a while after being hit ) -- +----------------------------------------------------------------------------- +b4_1 <= d4_6; -- explosion clock +b4_3 <= a4_12; -- clrn + +process (super_clk, b4_3) +begin +if b4_3 = '0' then -- clr active low + b4_15 <= '0'; + b4_1_old <= '0'; +elsif rising_edge (super_clk) then + b4_1_old <= b4_1; + if (b4_1_old = '1') and (b4_1 = '0') then + -- data out on falling edge; j,k can be viewed as permanent high => toggle + b4_15 <= not b4_15; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Frequency divider logic flipflop 2 -- +-- 7476, B4, flip flop 2 -- +-- dual master slave jk flip flop with clear -- +-- pin 6 clk 1 -- +-- pin 8 clr 1 -- +-- pin 10 qn -- +-- pin 11 q -- +-- -- +-- Overall B4 and C4(pin 6-12) -- +-- Creates the frequency pulse trains that are the basis for the timing -- +-- of explosion and collision events (such as rocket spinning, screen -- +-- inversing/"flashing", explosion sound and removing saucer/rocket from -- +-- the screen for a while after being hit ) -- +----------------------------------------------------------------------------- +b4_6 <= b4_15; -- clk +b4_8 <= a4_12; --clrn + +process (super_clk, b4_8) +begin +if b4_8 = '0' then + b4_11 <= '0'; + b4_10 <= '1'; + b4_6_old <= '0'; +elsif rising_edge (super_clk) then + b4_6_old <= b4_6; + if (b4_6_old = '1') and (b4_6 = '0') then + -- data out on falling edge, j,k are permanent high => toggle + b4_11 <= not b4_11; + b4_10 <= not b4_10; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Frequency divider logic flipflop 3 -- +-- 7476, B4, flip flop 3 -- +-- dual master slave jk flip flop with clear -- +-- pin 6 clk 1 -- +-- pin 8 clr 1 -- +-- pin 10 qn -- +-- pin 11 q -- +-- -- +-- Overall B4 and C4(pin 6-12) -- +-- Creates the frequency pulse trains that are the basis for the timing -- +-- of explosion and collision events (such as rocket spinning, screen -- +-- inversing/"flashing", explosion sound and removing saucer/rocket from -- +-- the screen for a while after being hit ) -- +----------------------------------------------------------------------------- +c4_6 <= b4_11; -- clk +c4_8 <= a4_12; -- clrn + +process (super_clk, c4_8) +begin +if c4_8 ='0' then + c4_11 <= '0'; + c4_10 <= '1'; + c4_6_old <= '0'; +elsif rising_edge (super_clk) then + c4_6_old <= c4_6; + if (c4_6_old = '1') and (c4_6 = '0') then + -- data out on falling edge; j,k are permanent high => toggle + c4_11 <= not c4_11; + c4_10 <= not c4_10; + end if; +end if; +end process; + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Collision and Explosion Timer -- +-- is active for the duration of the rocket spin, the time the rocket -- +-- and/or saucer is not visible on the screen following collision or hit -- +----------------------------------------------------------------------------- +a4_8 <= not (b4_15 and b4_11 and c4_11); + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: screen flash & sound timer -- +-- is active for the duration of screen flash (inverse the screen color) -- +----------------------------------------------------------------------------- +a4_6 <= not (b4_15 and b4_10 and c4_10); + +----------------------------------------------------------------------------- +-- COLLISION DETECTION & EXPLOSION: Trigger explosion sound -- +----------------------------------------------------------------------------- +d4_8 <= not a4_6; -- inversing signal to fit sound unit's active level +SB_L <= d4_8; + +----------------------------------------------------------------------------- +-- Hyperspace Screen Management -- +-- Signals to video out unit to use inverse video signals (white becomes -- +-- black and black becomes white) -- +-- Inversing happens either when game is in hyperspace mode (replay) or -- +-- when a collision or missile hit has occurred -- +----------------------------------------------------------------------------- +j1_6 <= d5_6 xor a4_6; -- normal/hyperspace (nor/hyp) + +----------------------------------------------------------------------------- +-- GAME TIME CLOCK -- +-- provide clk input to the time keeping circuit -- +----------------------------------------------------------------------------- +c5_6 <= seconds_clk nand d5_9; -- seconds_clk is called "Game Speed + -- Adjust" in the original schematics + -- essentially the speed with which each + -- time unit progresses + -- d5_9 is active high when a game is "on" + -- and lets c5_6 pass through clock pulses + +----------------------------------------------------------------------------- +-- SCORE & TIME KEEPING CIRCUITRY: Keep and update time unit -- +-- E3, 7490 -- +-- decade counter TIME UNIT -- +----------------------------------------------------------------------------- +e3_14 <= c5_6; -- clk a +e3_2 <= e5_8; -- reseet when high + +process (super_clk, e3_2) +begin +if e3_2 = '1' then --- reset + e3_count <= "0000"; +elsif rising_edge (super_clk) then + e3_14_old <= e3_14; + if (e3_14_old = '1') and (e3_14 = '0') then -- falling edge + if e3_count = "1001" then -- decade counter, reset after reaching 9 + e3_count <= "0000"; + else + e3_count <= e3_count+1; + end if; + end if; +end if; +end process; + +e3_12 <= e3_count (0); -- qa +e3_11 <= e3_count (3); -- qd +e3_9 <= e3_count (1); -- qb +e3_8 <= e3_count (2); -- qc + +----------------------------------------------------------------------------- +-- SCORE & TIME KEEPING CIRCUITRY: Keep and update time tens -- +-- D3, 7490 -- +-- decade counter TIME TENS -- +----------------------------------------------------------------------------- +d3_14 <= e3_11; -- clk a +d3_2 <= e5_8; -- reseet when high + +process (super_clk, d3_2) +begin +if d3_2 = '1' then --- reset + d3_count <= "0000"; +elsif rising_edge (super_clk) then + d3_14_old <= d3_14; + if (d3_14_old = '1') and (d3_14 = '0') then -- falling edge + if d3_count = "1001" then -- decade counter, reset after reaching 9 + d3_count <= "0000"; + else + d3_count <= d3_count+1; + end if; + end if; +end if; +end process; + +d3_12 <= d3_count (0); -- qa +d3_11 <= d3_count (3); -- qd +d3_9 <= d3_count (1); -- qb +d3_8 <= d3_count (2); -- qc + +----------------------------------------------------------------------------- +-- SCORE & TIME KEEPING CIRCUITRY: keep and update rocket score -- +-- C3, 7493 -- +-- BINARY COUNTER -- +-- interestingly they use a binary counter instead of decade -- +-- which results in "strange" symbols when rocket score goes beyond 9 -- +----------------------------------------------------------------------------- +c3_14 <= b5_6; -- clk a, when rocket missile hits saucer +c3_2 <= e5_8; -- reset when high + +process (super_clk, c3_2) +begin +if c3_2 = '1' then --- reset + c3_count <= "0000"; +elsif rising_edge (super_clk) then + c3_14_old <= c3_14; + if (c3_14_old = '1') and (c3_14 = '0') then -- falling edge + if c3_count = "1111" then -- binary counter, reset after reaching 15 + c3_count <= "0000"; + else + c3_count <= c3_count+1; + end if; + end if; +end if; +end process; + +c3_12 <= c3_count (0); -- qa +c3_11 <= c3_count (3); -- qd +c3_9 <= c3_count (1); -- qb +c3_8 <= C3_count (2); -- qc + +----------------------------------------------------------------------------- +-- SCORE & TIME KEEPING CIRCUITRY: Keep and update saucer score -- +-- B3, 7490 -- +-- decade counter -- +----------------------------------------------------------------------------- +b3_14 <= a5_6; -- clk a, when saucer missile hits rocket +b3_2 <= e5_8; -- reseet when high + +process (super_clk, b3_2) +begin +if b3_2 = '1' then --- reset + b3_count <= "0000"; +elsif rising_edge (super_clk) then + b3_14_old <= b3_14; + if (b3_14_old = '1') and (b3_14 = '0') then -- falling edge + if b3_count = "1001" then -- decade counter, reset after reaching 9 + b3_count <= "0000"; + else + b3_count <= b3_count+1; + end if; + end if; +end if; +end process; + +b3_12 <= b3_count (0); -- qa +b3_11 <= b3_count (3); -- qd +b3_9 <= b3_count (1); -- qb +b3_8 <= b3_count (2); -- qc + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: TENS and Rocket Flag -- +-- This flag is a bit clever as it embeds the input from two unrelated -- +-- "items": -- +-- 1) TENS - signal whether the TV beam is within the TENS horizontal -- +-- position -- +-- 2) Rocket - signal whether the TV beam is within the rocket score's -- +-- horizontal and vertical position -- +-- -- +-- The "dual-info" flag is decomposed in downstream logic to determine -- +-- whether to forward TIME TENS or UNITS value to the segment decoder -- +-- if TIME is to be displayed OR whether to forward the rocket's or the -- +-- saucer's score value to the segment decoder if TIME is not to be -- +-- displayed -- +----------------------------------------------------------------------------- +h1_6 <= e2_6 nand g2_8; + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Select score and time(tens/unit) to display -- +-- A3, 74153 -- +-- DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXOR -- +-- (a,b) => output (y1 and y2) -- +-- (0,0) => c0 -- +-- (0,1) => c1 -- +-- (1,0) => c2 -- +-- (1,1) => c3 -- +-- Depending on the current screen position, the two Selectors A3 and F3 -- +-- forwards the corresponding value from either rocket score, -- +-- saucer score, time tens or time unit to the binary-segment decoder. -- +-- A3 and F3 manages four bits in total, two bits each, from the score and -- +-- time tens/units - as each value has four bits. -- +-- -- +-- A3 forwards bit 0 and bit 1 from rocket/saucer/time unit/time tens -- +-- F3 fowards bit 2 and bit 3 from rocket/saucer/time unit/time tens -- +-- -- +-- When Time Display is enabled (f2_6: active low) then the data -- +-- selector forwards c1 or c2 (tens or units). If TENS flag is set (e2_6 -- +-- cleverly embedded in h1_6) then c1(tens) is selected, otherwise unit. -- +-- -- +-- When Time Display is not enabled -- +-- either c2 or c3 (rocket score or saucer score) are in scope; which one -- +-- depends on whether Rocket Score Display is enabled (g2_8 cleverly -- +-- embedded in h1_6) or not. -- +----------------------------------------------------------------------------- +a3_3 <= b3_9; -- 1c3: saucer score bit qb +a3_4 <= c3_9; -- 1c2: rocket score bit qb +a3_5 <= d3_9; -- 1c1: time tens bit qb +a3_6 <= e3_9; -- 1c0: time units bit qb + +a3_10 <= e3_12; -- 2c0: time units bit qa +a3_11 <= d3_12; -- 2c1: time tens bit qa +a3_12 <= c3_12; -- 2c2: rocket score bit qa +a3_13 <= b3_12; -- 2c3: saucer score bit qa + +a3_14 <= h1_6; -- a select +a3_2 <= f2_6; -- b select + +a3_7 <= -- y1 + a3_6 when (a3_14 = '0' and a3_2 = '0') else + a3_5 when (a3_14 = '1' and a3_2 = '0') else + a3_4 when (a3_14 = '0' and a3_2 = '1') else + a3_3; + + +a3_9 <= -- y2 + a3_10 when (a3_14 = '0' and a3_2 = '0') else + a3_11 when (a3_14 = '1' and a3_2 = '0') else + a3_12 when (a3_14 = '0' and a3_2 = '1') else + a3_13; + +----------------------------------------------------------------------------- +-- DISPLAY SCORE & TIME: Select score and time (tens/unit) to display -- +-- F3, 74153 -- +-- DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXOR -- +-- (a,b) => output (y1 and y2) -- +-- (0,0) => c0 -- +-- (0,1) => c1 -- +-- (1,0) => c2 -- +-- (1,1) => c3 -- +-- Depending on the current screen position, the two Selectors A3 and F3 -- +-- forwards the corresponding value from either rocket score, -- +-- saucer score, time tens or time unit to the binary-segment decoder. -- +-- A3 and F3 manages four bits in total, two bits each, from the score and -- +-- time tens/units - as each value has four bits. -- +-- -- +-- A3 forwards bit 0 and bit 1 from rocket/saucer/time unit/time tens -- +-- F3 fowards bit 2 and bit 3 from rocket/saucer/time unit/time tens -- +-- -- +-- When Time Display is enabled (f2_6: active low) then the data -- +-- selector forwards c1 or c2 (tens or units). If TENS flag is set (e2_6 -- +-- cleverly embedded in h1_6) then c1(tens) is selected, otherwise unit. -- +-- -- +-- When Time Display is not enabled -- +-- either c2 or c3 (rocket score or saucer score) are in scope; which one -- +-- depends on whether Rocket Score Display is enabled (g2_8 cleverly -- +-- embedded in h1_6) or not. -- +----------------------------------------------------------------------------- +f3_3 <= b3_11; -- 1c3: saucer score bit qd +f3_4 <= c3_11; -- 1c2: rocket score bit qd +f3_5 <= d3_11; -- 1c1: time tens bit qd +f3_6 <= e3_11; -- 1c0: time units bit qd + +f3_10 <= e3_8; -- 2c0: time units bit qc +f3_11 <= d3_8; -- 2c1: time tens bit qc +f3_12 <= c3_8; -- 2c2: rocket score bit qc +f3_13 <= b3_8; -- 2c3: saucer score bit qc + +f3_14 <= h1_6; -- a select +f3_2 <= f2_6; -- b select + +f3_7 <= -- y1 + f3_6 when (f3_14 = '0' and f3_2 = '0') else + f3_5 when (f3_14 = '1' and f3_2 = '0') else + f3_4 when (f3_14 = '0' and f3_2 = '1') else + f3_3; + +f3_9 <= -- y2 + f3_10 when (f3_14 = '0' and f3_2 = '0') else + f3_11 when (f3_14 = '1' and f3_2 = '0') else + f3_12 when (f3_14 = '0' and f3_2 = '1') else + f3_13; + +----------------------------------------------------------------------------- +-- REPLAY CIRCUITRY: Compare Player/Rocket score with Saucer score -- +-- A2, 9324 -- +-- 5-Bit comparator -- +-- comparing score between rocket and saucer -- +-- if player/rocket score is higher than saucer score then set a2_15 flag -- +----------------------------------------------------------------------------- +a2_3 <= b3_12; +a2_4 <= b3_9; +a2_5 <= b3_8; +a2_6 <= b3_11; + +a2_10 <= c3_11; +a2_11 <= c3_8; +a2_12 <= c3_9; +a2_13 <= c3_12; + +a2_A (0) <= a2_13; +a2_A (1) <= a2_12; +a2_A (2) <= a2_11; +a2_A (3) <= a2_10; + +a2_B (0) <= a2_3; +a2_B (1) <= a2_4; +a2_B (2) <= a2_5; +a2_B (3) <= a2_6; + +-- checks if rocket score is higher than saucer score +a2_15 <= '1' when a2_A > a2_B else '0'; + +----------------------------------------------------------------------------- +-- REPLAY CIRCUITRY: Set Replay or not -- +-- -- +-- SB_F = '1'; flag allows for replay -- +----------------------------------------------------------------------------- +SB_F <= '1'; +c2_11 <= SB_F and a2_15; -- determine replay or not, depending on score + +----------------------------------------------------------------------------- +-- START/END GAME: Start Game Process -- +-- -- +-- start game circuitry is not fully reproduced -- +-- a "state machine" represents the logic -- +-- -- +-- SB_7 connected to Start button on player control panel. -- +-- -- +-- SB_C connected to coin microswitch -- +----------------------------------------------------------------------------- +process (super_clk, reset) +begin +if reset = '1' then + state <= IDLE; + e5_12 <= '0'; + d6_8 <= '0'; +elsif rising_edge (super_clk) then + --SB_7_old <= SB_7; + SB_C_old <= SB_C; + + case state is + when IDLE => + e5_12 <= '0'; + d6_8 <= '1'; + if SB_C_old = '0' and SB_C = '1' then + e5_12 <= '1'; + state <= COIN_INSERTED; + end if; + + when COIN_INSERTED => + d6_8 <= '1'; + e5_12 <= '1'; + --if SB_7_old = '0' and SB_7 = '1' then + d6_8 <= '0'; + state <= GAME_ON; + --end if; + + when GAME_ON => + d6_8 <= '1'; + e5_12 <= '1'; + if d5_9 = '0' then + state <= IDLE; + e5_12 <= '0'; + end if; + + when others => + state <= IDLE; + e5_12 <= '0'; + d6_8 <= '1'; + + end case; +end if; +end process; + +----------------------------------------------------------------------------- +-- START/END GAME: Replay or not -- +-- will signal for replay if player score is greater than saucer score -- +-- (c2_11) and if player is not already in replay mode (d5_6) -- +----------------------------------------------------------------------------- +c2_8 <= c2_11 and d5_6; + +----------------------------------------------------------------------------- +-- START/END GAME: Signal that Time = 99 -- +-- signals that game time has reached 99 -- +-- downstream logic will determine whether to stop the game or go for -- +-- replay -- +----------------------------------------------------------------------------- +e5_10 <= not d3_11; + +----------------------------------------------------------------------------- +-- START/END GAME: Replay Flag -- +-- D5, 7474, pin 1-6 -- +-- d5_6 signals whether game is in replay mode or not -- +----------------------------------------------------------------------------- +d5_1 <= e5_12; -- clrn +d5_3 <= e5_10; -- clk +d5_2 <= c2_8; -- d : replay or not + +process(super_clk, d5_1) +begin + if d5_1 = '0' then + d5_6 <= '1'; -- qn is cleared when clrn is active low + elsif rising_edge (super_clk) then + d5_3_old <= d5_3; + if (d5_3_old = '0') and (d5_3 = '1') then + d5_6 <= not d5_2; + end if; + end if; +end process; + +----------------------------------------------------------------------------- +-- START/END GAME: Game On/Off Flag -- +-- D5, 7474, pin 8-13 -- +-- d5_9 signals whether game is on or off, 1-on, 0-off -- +-- d5_8 is the inverse of d5_9 -- +----------------------------------------------------------------------------- +d5_13 <= e5_12; -- clrn +d5_11 <= e5_10; -- clk +d5_12 <= c2_8; -- d +d5_10 <= d6_8; -- pren + +process(super_clk, d5_13, d5_10) +begin + if d5_13 = '0' then + d5_9 <= '0'; -- q is cleared when clrn is active low + d5_8 <= '1'; -- qn is cleared when clrn is active low + elsif d5_10 = '0' then + d5_9 <= '1'; -- q is set to high when pren is active low + d5_8 <= '0'; -- qn is set to low when pren is active low + elsif rising_edge (super_clk) then + d5_11_old <= d5_11; + if (d5_11_old = '0') and (d5_11 = '1') then + d5_9 <= d5_12; + d5_8 <= not d5_12; + end if; + end if; +end process; + +----------------------------------------------------------------------------- +-- START/END GAME: Reset Score and Time (Unit and Tens) -- +-- signals to score and time keeping units to reset score and time -- +----------------------------------------------------------------------------- +e5_8 <= not d6_8; + +----------------------------------------------------------------------------- +-- START/END GAME: Audio On/Off -- +-- signals to audio unit to switch on the sound, incl backgrund noise, -- +-- when a game is playing, otherwise switch off -- +----------------------------------------------------------------------------- +SB_K <= d5_8; -- audio gate signal + +end sync_star_board_architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/thrust_8_11.hex b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/thrust_8_11.hex new file mode 100644 index 00000000..0e03fcb2 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/thrust_8_11.hex @@ -0,0 +1,160 @@ +:20000000FFFE00FEFD02030000FFFF0403030804FAF8FBFD0003FEF7FAFAFBFDFCFCFF0208 +:200020000002070601020705010408040306030201FEFBF8F7FA0608FCF9FC0004FEF8FBAC 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+:0C13C00002020101FF000405010003030C +:00000001FF diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/v74161.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/v74161.vhd new file mode 100644 index 00000000..6a03d402 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/v74161.vhd @@ -0,0 +1,43 @@ +-- 74161 counter - extended to 8 bits +-- code found on the internet +-- adjustments made for 8 bit counter structure + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +entity v74161 is +port ( CLK, CLRN, LDN, ENP, ENT: in STD_LOGIC :='0'; +D: in UNSIGNED (7 downto 0) := "00000000"; +Q: out UNSIGNED (7 downto 0):= "00000000"; +RCO: out STD_LOGIC :='0'); +end v74161; + +architecture V74x161_arch of v74161 is + signal IQ: UNSIGNED (7 downto 0) := "00000000"; + signal IRCO: STD_LOGIC := '0'; + begin + +process (CLK, CLRN, IQ, ENT) +begin + +if CLRN='0' then IQ <= "00000000"; +elsif rising_edge(CLK) then +if LDN='0' then IQ <= D; +elsif (ENT and ENP)='1' then IQ <= IQ + 1; +end if; +end if; + +--if (IQ=15) and (ENT='1') then IRCO <= '1'; +if (IQ=255) and (ENT='1') then IRCO <= '1'; +else IRCO <= '0'; +end if; + +end process; + + + +Q <= IQ; +RCO <= IRCO; + +end V74x161_arch; diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/v74161_16bit.vhd b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/v74161_16bit.vhd new file mode 100644 index 00000000..efd71187 --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/v74161_16bit.vhd @@ -0,0 +1,44 @@ +-- 74161 counter: 16 bit extended version +-- code found on the internet +-- adjusted to fit 16 bit counter structure + +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +entity v74161_16bit is +port ( CLK, CLRN, LDN, ENP, ENT: in STD_LOGIC :='0'; +D: in UNSIGNED (15 downto 0) := "0000000000000000"; +Q: out UNSIGNED (15 downto 0):= "0000000000000000"; +RCO: out STD_LOGIC :='0'); +end v74161_16bit; + +architecture V74x161_arch of v74161_16bit is + signal IQ: UNSIGNED (15 downto 0) := "0000000000000000"; + signal IRCO: STD_LOGIC := '0'; + begin + +process (CLK, CLRN, IQ, ENT) +begin + +if CLRN='0' then IQ <= "0000000000000000"; +elsif rising_edge(CLK) then +if LDN='0' then + IQ <= D; +elsif (ENT and ENP)='1' then IQ <= IQ + 1; +end if; +end if; + +--if (IQ=15) and (ENT='1') then IRCO <= '1'; + +if (IQ=65535) and (ENT='1') then IRCO <= '1'; +else IRCO <= '0'; +end if; + +end process; + + +Q <= IQ; +RCO <= IRCO; + +end V74x161_arch; diff --git a/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/video_mixer.sv b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Custom Hardware/ComputerSpace_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Custom Hardware/Galaga_MIST/README.txt b/Arcade/Custom Hardware/Galaga_MIST/README.txt new file mode 100644 index 00000000..82a73631 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Galaga for MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- Copyright (c) DAR - Dez 2016 +-- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/galaga/ +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE : Fire +-- ARROW KEYS : Movement +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- \ No newline at end of file diff --git a/Arcade/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf b/Arcade/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf new file mode 100644 index 00000000..4a52e67d Binary files /dev/null and b/Arcade/Custom Hardware/Galaga_MIST/Release/galaga_mist.rbf differ diff --git a/Arcade/Custom Hardware/Galaga_MIST/clean.bat b/Arcade/Custom Hardware/Galaga_MIST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.qpf b/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.qpf new file mode 100644 index 00000000..0ec77b14 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 20:10:08 November 14, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "20:10:08 November 14, 2016" + +# Revisions + +PROJECT_REVISION = "galaga_mist" diff --git a/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.qsf b/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.qsf new file mode 100644 index 00000000..274d00aa --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.qsf @@ -0,0 +1,203 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 08:30:59 December 07, 2015 +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY galaga_mist +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON + +# Fitter Assignments +# ================== +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------ +# start ENTITY(galaga_mist) + +# Pin & Location Assignments +# ========================== + +# Fitter Assignments +# ================== +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 + +# end ENTITY(galaga_mist) +# ---------------------- +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE rtl/ROM/sp_palette.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/sp_graphx.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/sound_seq.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/sound_samples.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaga_cpu3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaga_cpu2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/galaga_cpu1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/bg_palette.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/bg_graphx.vhd +set_global_assignment -name VHDL_FILE rtl/CPU/T80se.vhd +set_global_assignment -name VHDL_FILE rtl/CPU/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/CPU/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/CPU/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/CPU/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/CPU/T80.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/stars_machine.vhd +set_global_assignment -name VHDL_FILE rtl/stars.vhd +set_global_assignment -name VHDL_FILE rtl/sound_machine.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/rgb.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_video.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/galaga_mist.vhd +set_global_assignment -name VHDL_FILE rtl/galaga.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.sdc b/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.sdc new file mode 100644 index 00000000..3eba3b05 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/galaga_mist.sdc @@ -0,0 +1,33 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# +#************************************************************ + +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] +create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_ALU.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_MCode.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Pack.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Reg.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80se.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80se.vhd new file mode 100644 index 00000000..ac8886a8 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/CPU/T80se.vhd @@ -0,0 +1,184 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/bg_graphx.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/bg_graphx.vhd new file mode 100644 index 00000000..f62270b7 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/bg_graphx.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_graphx is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_graphx is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"CC",X"22",X"22",X"66",X"CC",X"88",X"00",X"33",X"77",X"CC",X"88",X"88",X"77",X"33",X"00", + X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"00",X"00",X"FF",X"FF",X"44",X"00",X"00",X"00", + X"22",X"22",X"AA",X"AA",X"EE",X"EE",X"66",X"00",X"66",X"FF",X"BB",X"99",X"99",X"CC",X"44",X"00", + X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"88",X"DD",X"FF",X"BB",X"99",X"88",X"00",X"00", + X"88",X"EE",X"EE",X"88",X"88",X"88",X"88",X"00",X"00",X"FF",X"FF",X"CC",X"66",X"33",X"11",X"00", + X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"11",X"BB",X"AA",X"AA",X"AA",X"EE",X"EE",X"00", + X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"00",X"99",X"99",X"99",X"DD",X"77",X"33",X"00", + X"00",X"00",X"00",X"EE",X"EE",X"00",X"00",X"00",X"CC",X"EE",X"BB",X"99",X"88",X"CC",X"CC",X"00", + X"CC",X"EE",X"AA",X"AA",X"22",X"22",X"CC",X"00",X"00",X"66",X"99",X"99",X"BB",X"FF",X"66",X"00", + X"88",X"CC",X"66",X"22",X"22",X"22",X"00",X"00",X"77",X"FF",X"99",X"99",X"99",X"FF",X"66",X"00", + X"EE",X"EE",X"88",X"88",X"88",X"EE",X"EE",X"00",X"33",X"77",X"CC",X"88",X"CC",X"77",X"33",X"00", + X"CC",X"EE",X"22",X"22",X"22",X"EE",X"EE",X"00",X"66",X"FF",X"99",X"99",X"99",X"FF",X"FF",X"00", + X"44",X"66",X"22",X"22",X"66",X"CC",X"88",X"00",X"44",X"CC",X"88",X"88",X"CC",X"77",X"33",X"00", + X"88",X"CC",X"66",X"22",X"22",X"EE",X"EE",X"00",X"33",X"77",X"CC",X"88",X"88",X"FF",X"FF",X"00", + X"22",X"22",X"22",X"22",X"EE",X"EE",X"00",X"00",X"88",X"99",X"99",X"99",X"FF",X"FF",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"00",X"88",X"99",X"99",X"99",X"99",X"FF",X"FF",X"00", + X"EE",X"EE",X"22",X"22",X"66",X"CC",X"88",X"00",X"99",X"99",X"99",X"88",X"CC",X"77",X"33",X"00", + X"EE",X"EE",X"00",X"00",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"11",X"11",X"FF",X"FF",X"00", + X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"88",X"88",X"FF",X"FF",X"88",X"88",X"00",X"00", + X"CC",X"EE",X"22",X"22",X"22",X"66",X"44",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00", + X"22",X"66",X"EE",X"CC",X"88",X"EE",X"EE",X"00",X"88",X"CC",X"66",X"33",X"11",X"FF",X"FF",X"00", + X"22",X"22",X"22",X"22",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00", + X"EE",X"EE",X"00",X"88",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"77",X"33",X"77",X"FF",X"FF",X"00", + X"EE",X"EE",X"CC",X"88",X"00",X"EE",X"EE",X"00",X"FF",X"FF",X"11",X"33",X"77",X"FF",X"FF",X"00", + X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00",X"77",X"FF",X"88",X"88",X"88",X"FF",X"77",X"00", + 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X"40",X"40",X"40",X"40",X"40",X"20",X"20",X"20",X"19",X"19",X"19",X"19",X"19",X"19",X"15",X"15", + X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22", + X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22", + X"20",X"20",X"20",X"40",X"40",X"40",X"40",X"40",X"15",X"15",X"19",X"19",X"19",X"19",X"19",X"19", + X"00",X"00",X"44",X"54",X"54",X"98",X"A8",X"A8",X"00",X"00",X"00",X"02",X"02",X"04",X"04",X"04", + X"20",X"20",X"20",X"20",X"10",X"10",X"10",X"00",X"04",X"04",X"02",X"02",X"02",X"02",X"00",X"00", + X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"19",X"19",X"19",X"19",X"19",X"15",X"15",X"15", + X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22", + X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"81",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22", + X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"15",X"15",X"15",X"19",X"19",X"19",X"19",X"19", + X"00",X"10",X"10",X"10",X"20",X"20",X"20",X"20",X"00",X"00",X"02",X"02",X"02",X"02",X"04",X"04"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/bg_palette.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/bg_palette.vhd new file mode 100644 index 00000000..b7edf1e5 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/bg_palette.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_palette is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of bg_palette is + type rom is array(0 to 255) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"F",X"0",X"0",X"6",X"F",X"D",X"1",X"0",X"F",X"2",X"C",X"D",X"F",X"B",X"1",X"0", + X"F",X"1",X"0",X"1",X"F",X"0",X"0",X"2",X"F",X"0",X"0",X"3",X"F",X"0",X"0",X"5", + X"F",X"0",X"0",X"9",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"F",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"F",X"B",X"7",X"6",X"F",X"6",X"B",X"7",X"F",X"7",X"6",X"B",X"F",X"F",X"F",X"1", + X"F",X"F",X"B",X"F",X"F",X"2",X"F",X"F",X"F",X"6",X"6",X"B",X"F",X"6",X"B",X"B", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu1.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu1.vhd new file mode 100644 index 00000000..1fe98b38 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity galaga_cpu1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of galaga_cpu1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3E",X"10",X"32",X"00",X"71",X"C3",X"C4",X"02",X"87",X"30",X"05",X"24",X"C3",X"10",X"00",X"FF", + X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF", + X"7B",X"D6",X"20",X"5F",X"D0",X"15",X"C9",X"FF",X"21",X"00",X"91",X"06",X"F0",X"AF",X"DF",X"C9", + X"37",X"08",X"C3",X"B5",X"13",X"FF",X"FF",X"FF",X"C3",X"37",X"02",X"E9",X"21",X"00",X"93",X"06", + X"80",X"AF",X"DF",X"21",X"00",X"9B",X"06",X"80",X"DF",X"21",X"00",X"88",X"3E",X"80",X"06",X"80", + X"DF",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"D9",X"ED",X"A0",X"EA",X"8F",X"00",X"F5",X"21",X"00",X"71", + X"36",X"10",X"3A",X"B9",X"9A",X"A7",X"28",X"16",X"AF",X"32",X"B9",X"9A",X"21",X"92",X"00",X"11", + X"00",X"70",X"01",X"04",X"00",X"D9",X"3E",X"A8",X"32",X"00",X"71",X"F1",X"ED",X"45",X"F1",X"D9", + X"ED",X"45",X"10",X"10",X"20",X"20",X"3A",X"08",X"3B",X"08",X"B2",X"17",X"00",X"17",X"86",X"1A", + X"6A",X"08",X"3A",X"08",X"3A",X"08",X"24",X"29",X"EC",X"1D",X"9E",X"2A",X"B9",X"1D",X"EB",X"23", + X"AA",X"1E",X"38",X"1D",X"48",X"09",X"6B",X"1B",X"B2",X"19",X"7C",X"1D",X"3A",X"08",X"8B",X"1F", + X"0A",X"1F",X"3A",X"08",X"D8",X"1D",X"30",X"22",X"D9",X"21",X"3A",X"08",X"3A",X"08",X"F2",X"20", + X"00",X"20",X"3A",X"08",X"8A",X"09",X"11",X"ED",X"83",X"21",X"B9",X"02",X"01",X"05",X"00",X"ED", + X"B0",X"1E",X"CB",X"21",X"EB",X"00",X"0E",X"11",X"ED",X"B0",X"C9",X"0E",X"1B",X"18",X"0C",X"1C", + X"24",X"11",X"10",X"12",X"11",X"24",X"24",X"24",X"24",X"19",X"1E",X"01",X"FF",X"FF",X"FF",X"FF", + X"14",X"06",X"14",X"0C",X"14",X"08",X"14",X"0A",X"1C",X"00",X"1C",X"12",X"1E",X"00",X"1E",X"12", + X"1C",X"02",X"1C",X"10",X"1E",X"02",X"1E",X"10",X"1C",X"04",X"1C",X"0E",X"1E",X"04",X"1E",X"0E", + X"1C",X"06",X"1C",X"0C",X"1E",X"06",X"1E",X"0C",X"1C",X"08",X"1C",X"0A",X"1E",X"08",X"1E",X"0A", + X"16",X"06",X"16",X"0C",X"16",X"08",X"16",X"0A",X"18",X"00",X"18",X"12",X"1A",X"00",X"1A",X"12", + X"18",X"02",X"18",X"10",X"1A",X"02",X"1A",X"10",X"18",X"04",X"18",X"0E",X"1A",X"04",X"1A",X"0E", + X"18",X"06",X"18",X"0C",X"1A",X"06",X"1A",X"0C",X"18",X"08",X"18",X"0A",X"1A",X"08",X"1A",X"0A", + X"21",X"40",X"80",X"11",X"41",X"80",X"01",X"7F",X"03",X"36",X"24",X"ED",X"B0",X"21",X"40",X"84", + X"11",X"41",X"84",X"01",X"7F",X"03",X"36",X"00",X"ED",X"B0",X"3E",X"04",X"06",X"20",X"DF",X"3E", + X"4E",X"06",X"20",X"DF",X"C9",X"21",X"21",X"98",X"34",X"7E",X"3C",X"E6",X"03",X"32",X"25",X"98", + X"28",X"10",X"0E",X"06",X"F7",X"EB",X"3A",X"21",X"98",X"6F",X"26",X"00",X"CD",X"66",X"0A",X"AF", + X"18",X"0A",X"0E",X"07",X"F7",X"3E",X"01",X"32",X"AD",X"9A",X"3E",X"08",X"32",X"A8",X"92",X"3E", + X"03",X"32",X"AE",X"92",X"32",X"0B",X"92",X"3A",X"25",X"98",X"A7",X"08",X"CD",X"7F",X"11",X"3A", + X"AE",X"92",X"A7",X"20",X"FA",X"3E",X"78",X"32",X"AE",X"92",X"CD",X"A4",X"28",X"CD",X"B0",X"25", + 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galaga_cpu2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of galaga_cpu2 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"00",X"91",X"C3",X"7C",X"05",X"FF",X"FF",X"87",X"30",X"05",X"24",X"C3",X"10",X"00",X"FF", + X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"C9",X"23",X"06",X"16", + X"23",X"00",X"19",X"F7",X"4B",X"00",X"23",X"F0",X"02",X"F0",X"5E",X"00",X"23",X"F0",X"24",X"FB", + X"23",X"00",X"FF",X"FF",X"E9",X"FF",X"FF",X"FF",X"C3",X"13",X"05",X"BE",X"05",X"BF",X"05",X"D3", + X"08",X"BE",X"05",X"F5",X"06",X"EE",X"05",X"BE",X"05",X"CA",X"0E",X"23",X"F0",X"26",X"23",X"14", + X"13",X"FE",X"0D",X"0B",X"0A",X"08",X"06",X"04",X"03",X"01",X"23",X"FF",X"FF",X"FF",X"44",X"E4", + X"18",X"FB",X"44",X"00",X"FF",X"FF",X"C9",X"23",X"08",X"08",X"23",X"03",X"1B",X"23",X"08",X"0F", + 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if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu3.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu3.vhd new file mode 100644 index 00000000..d8dd82f2 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu3.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity galaga_cpu3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of galaga_cpu3 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"00",X"9B",X"C3",X"7B",X"00",X"FF",X"FF",X"87",X"30",X"05",X"24",X"18",X"02",X"FF",X"FF", + X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"8A",X"04",X"86",X"04",X"82",X"04",X"8B",X"04",X"89",X"04",X"82",X"04",X"FF",X"00",X"00",X"03", + X"75",X"18",X"75",X"18",X"75",X"18",X"71",X"0C",X"75",X"0C",X"73",X"18",X"73",X"18",X"72",X"18", + X"76",X"0C",X"78",X"0C",X"FF",X"FB",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sound_samples.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sound_samples.vhd new file mode 100644 index 00000000..b983efbd --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sound_samples.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity sound_samples is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of sound_samples is + type rom is array(0 to 255) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"7",X"9",X"A",X"B",X"C",X"D",X"D",X"E",X"E",X"E",X"D",X"D",X"C",X"B",X"A",X"9", + X"7",X"5",X"4",X"3",X"2",X"1",X"1",X"0",X"0",X"0",X"1",X"1",X"2",X"3",X"4",X"5", + X"7",X"9",X"A",X"B",X"7",X"D",X"D",X"7",X"E",X"7",X"D",X"D",X"7",X"B",X"A",X"9", + X"7",X"5",X"7",X"3",X"7",X"1",X"7",X"0",X"7",X"0",X"7",X"1",X"7",X"3",X"7",X"5", + X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"B",X"D",X"E",X"D",X"C",X"A",X"8",X"8",X"8",X"A",X"C",X"D",X"E",X"D",X"B",X"8", + X"4",X"2",X"1",X"2",X"3",X"5",X"7",X"7",X"7",X"5",X"3",X"2",X"1",X"2",X"4",X"7", + X"7",X"A",X"C",X"D",X"E",X"D",X"C",X"A",X"7",X"4",X"2",X"1",X"0",X"1",X"2",X"4", + X"7",X"B",X"D",X"E",X"D",X"B",X"7",X"3",X"1",X"0",X"1",X"3",X"7",X"E",X"7",X"0", + X"7",X"E",X"C",X"9",X"C",X"E",X"A",X"7",X"C",X"F",X"D",X"8",X"A",X"B",X"7",X"2", + X"8",X"D",X"9",X"4",X"5",X"7",X"2",X"0",X"3",X"8",X"5",X"1",X"3",X"6",X"3",X"1", + X"7",X"8",X"A",X"C",X"E",X"D",X"C",X"C",X"B",X"A",X"8",X"7",X"5",X"6",X"7",X"8", + X"8",X"9",X"A",X"B",X"9",X"8",X"6",X"5",X"4",X"4",X"3",X"2",X"4",X"6",X"8",X"9", + X"A",X"C",X"C",X"A",X"7",X"7",X"8",X"B",X"D",X"E",X"D",X"A",X"6",X"5",X"5",X"7", + X"9",X"9",X"8",X"4",X"1",X"0",X"1",X"3",X"6",X"7",X"7",X"4",X"2",X"2",X"4",X"7"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sound_seq.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sound_seq.vhd new file mode 100644 index 00000000..50ca39f7 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sound_seq.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity sound_seq is +port ( + clk : in std_logic; + addr : in std_logic_vector(6 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of sound_seq is + type rom is array(0 to 127) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F", + X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F", + X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F", + X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F", + X"7",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D", + X"F",X"F",X"E",X"D",X"F",X"F",X"F",X"B",X"7",X"F",X"E",X"D",X"F",X"F",X"E",X"D", + X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"F",X"B",X"7",X"F",X"E",X"D", + X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"F",X"B"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sp_graphx.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sp_graphx.vhd new file mode 100644 index 00000000..c163a322 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sp_graphx.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity sp_graphx is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of sp_graphx is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"CC",X"EE",X"FF",X"BB",X"99",X"18",X"19",X"11",X"1D",X"3F",X"BF",X"FF",X"DF",X"CF",X"E7", + X"00",X"06",X"8E",X"BF",X"FF",X"7F",X"7E",X"FD",X"22",X"66",X"EE",X"EE",X"AA",X"22",X"02",X"02", + X"11",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"77",X"33",X"33",X"33",X"33",X"11",X"11",X"11", + X"DD",X"89",X"89",X"88",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"11",X"11",X"33",X"33",X"22",X"02",X"00",X"00",X"00",X"00",X"8B",X"8B",X"EF",X"77",X"E7",X"EB", + X"00",X"00",X"44",X"CF",X"CF",X"DF",X"FF",X"7F",X"00",X"00",X"00",X"11",X"33",X"EE",X"EE",X"44", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AB",X"3B",X"33",X"77",X"77",X"22",X"22",X"22", + X"FE",X"EE",X"AA",X"02",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"01",X"02",X"00",X"00",X"00",X"44",X"CC",X"CC",X"CD",X"EF",X"77",X"77",X"DF", + X"00",X"00",X"00",X"2A",X"EE",X"EF",X"CF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"FF", + X"01",X"00",X"00",X"00",X"00",X"11",X"11",X"00",X"C7",X"77",X"FF",X"FF",X"CC",X"88",X"00",X"00", + X"FF",X"FF",X"EA",X"04",X"00",X"00",X"00",X"00",X"EE",X"04",X"08",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"11",X"33",X"77",X"3B",X"33",X"77",X"FB",X"23", + X"00",X"00",X"00",X"0C",X"9D",X"EE",X"EF",X"FF",X"00",X"00",X"00",X"88",X"00",X"00",X"08",X"08", + X"00",X"00",X"00",X"00",X"11",X"22",X"00",X"00",X"23",X"77",X"EE",X"CC",X"00",X"00",X"00",X"00", + X"7F",X"FF",X"62",X"44",X"09",X"00",X"00",X"00",X"FF",X"EE",X"44",X"08",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"13",X"15",X"33",X"77",X"7B",X"77", + X"CC",X"88",X"88",X"88",X"8E",X"BF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"08", + X"00",X"00",X"11",X"33",X"66",X"00",X"00",X"00",X"EF",X"EF",X"FF",X"DC",X"01",X"00",X"00",X"00", + X"EF",X"7F",X"FF",X"99",X"00",X"01",X"00",X"00",X"08",X"00",X"FF",X"EE",X"08",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"10",X"7F",X"33",X"77", + X"11",X"77",X"EE",X"66",X"EF",X"CF",X"FF",X"7F",X"88",X"00",X"00",X"00",X"08",X"08",X"CC",X"88", + X"11",X"FF",X"11",X"00",X"00",X"00",X"00",X"00",X"EF",X"FF",X"88",X"13",X"00",X"00",X"00",X"00", + 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X"FC",X"B1",X"91",X"91",X"32",X"F0",X"68",X"00",X"C0",X"CC",X"88",X"88",X"E0",X"E0",X"00",X"00", + X"00",X"00",X"00",X"00",X"30",X"70",X"F0",X"F1",X"00",X"00",X"12",X"10",X"E0",X"F0",X"F8",X"FC", + X"00",X"00",X"F0",X"F0",X"77",X"33",X"91",X"B0",X"00",X"00",X"C0",X"C0",X"00",X"88",X"CC",X"C3", + X"1F",X"F1",X"F0",X"70",X"30",X"00",X"00",X"00",X"7E",X"FC",X"F8",X"F0",X"E0",X"10",X"12",X"00", + X"FF",X"B0",X"91",X"33",X"77",X"F0",X"F0",X"00",X"F0",X"C3",X"CC",X"88",X"00",X"C0",X"C0",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sp_palette.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sp_palette.vhd new file mode 100644 index 00000000..006b8ab1 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/ROM/sp_palette.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity sp_palette is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) +); +end entity; + +architecture prom of sp_palette is + type rom is array(0 to 255) of std_logic_vector(3 downto 0); + signal rom_data: rom := ( + X"F",X"8",X"E",X"2",X"F",X"5",X"B",X"C",X"F",X"0",X"B",X"1",X"F",X"1",X"B",X"2", + X"F",X"8",X"D",X"2",X"F",X"6",X"1",X"4",X"F",X"9",X"1",X"5",X"F",X"7",X"B",X"1", + X"F",X"1",X"6",X"B",X"F",X"1",X"B",X"0",X"F",X"1",X"2",X"0",X"F",X"0",X"1",X"6", + X"F",X"0",X"0",X"6",X"F",X"3",X"B",X"9",X"F",X"6",X"2",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0", + X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/dac.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/galaga.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/galaga.vhd new file mode 100644 index 00000000..b6d04f39 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/galaga.vhd @@ -0,0 +1,1112 @@ +--------------------------------------------------------------------------------- +-- Galaga Midway by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +----------------- +-- Galaga releases +-- +-- Release 0.1 - 04/11/2017 - Dar +-- fixes 2 ships bullet bug (swap 2xH/2xV command bits) +-- +-- Release 0.0 - December 2016 - Dar +-- initial release +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok, Ship explode missing (custom chip 0x54XX todo) +-- Starfield from MAME information + +-- Use with MAME roms from galagamw.zip +-- +-- Use make_galaga_proms.bat to build vhd file from binaries + +-- galaga_cpu1.vhd : 3200a.bin, 3300b.bin, 3400c.bin,3500d.bin, +-- galaga_cpu2.vhd : 3600e.bin +-- galaga_cpu3.vhd : 3700g.bin +-- bg_graphx.vhd : 2600j.bin +-- sp_graphx.vhd : 2800l.bin, 2700k.bin +-- rgb.vhd : prom-5.5n +-- bg_palette.vhd : prom-4.2n +-- sp_palette.vhd : prom-3.1c +-- sound_seq.vhd : prom-2.5c +-- sound_samples.vhd : prom-1.1d + +-- Galaga Hardware caracteristics : +-- +-- 3xZ80 CPU accessing each own program rom and shared ram/devices +-- +-- One char tile map 32x28 (called background/bg although being front of other layers) +-- 3 colors/64sets among 16 colors +-- 1Ko ram, 4Ko rom graphics, 4pixels of 2bits/byte +-- full emulation in vhdl +-- +-- 64 sprites with priorities, flip H/V, 2x size H/V, +-- 3 colors/64sets among 16 colors (different of char colors). +-- 8Ko rom graphics, 4pixels of 2bits/byte +-- full emulation in vhdl (improved capabilities : more sprites/scanline) +-- +-- Namco 05XX Starfield +-- 4 sets, 63 stars/set, 2 set displayed at one time for blinking +-- 6bits colors: 2red/2green/2blue +-- full emulation in vhdl (from MAME information) +-- +-- Char/sprites color palette 2x16 colors among 256 colors +-- 8bits 3red/3green/2blue +-- full emulation in vhdl +-- +-- Namco 06XX for 51/54XX control +-- simplified emulation in vhdl +-- +-- Namco 51XX for coin/credit management +-- simplified emulation in vhdl : 1coin/1credit, 1 or 2 players start +-- +-- Namco 54XX for sound effects +-- no emulation in vhdl atm +-- +-- Namco sound waveform and frequency synthetizer +-- full original emulation in vhdl +-- +-- Namco 00XX,04XX,02XX,07XX,08XX address generator, H/V counters and shift registers +-- full emulation in vhdl from what I think they should do. +-- +-- Working ram : 3x1Kx8bits shared +-- Sprites ram : 1 scan line delay flip/flop 512x4bits +-- Sound registers ram : 2x16x4bits +-- Sound sequencer rom : 256x4bits (3 sequential 4 bits adders) +-- Sound wavetable rom : 256x4bits 8 waveform of 32 samples of 4bits/level +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity galaga is +port( + clock_18 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_hs : out std_logic; + video_vs : out std_logic; + video_blankn : out std_logic; + pix_ce : out std_logic; + audio : out std_logic_vector(9 downto 0); + + b_test : in std_logic; + b_svce : in std_logic; + coin : in std_logic; + start1 : in std_logic; + left1 : in std_logic; + right1 : in std_logic; + fire1 : in std_logic; + start2 : in std_logic; + left2 : in std_logic; + right2 : in std_logic; + fire2 : in std_logic + ); +end galaga; + +architecture struct of galaga is + + signal reset_n: std_logic; + signal clock_18n : std_logic; + + signal hcnt : std_logic_vector(8 downto 0); + signal vcnt : std_logic_vector(8 downto 0); + signal ena_vidgen : std_logic; + signal ena_snd_machine : std_logic; + signal cpu1_ena : std_logic; + signal cpu2_ena : std_logic; + signal cpu3_ena : std_logic; + + signal cpu1_addr : std_logic_vector(15 downto 0); + signal cpu1_di : std_logic_vector( 7 downto 0); + signal cpu1_do : std_logic_vector( 7 downto 0); + signal cpu1_wr_n : std_logic; + signal cpu1_mreq_n : std_logic; + signal cpu1_irq_n : std_logic; + signal cpu1_nmi_n : std_logic; + + + signal cpu2_addr : std_logic_vector(15 downto 0); + signal cpu2_di : std_logic_vector( 7 downto 0); + signal cpu2_do : std_logic_vector( 7 downto 0); + signal cpu2_wr_n : std_logic; + signal cpu2_mreq_n : std_logic; + signal cpu2_irq_n : std_logic; + + + signal cpu3_addr : std_logic_vector(15 downto 0); + signal cpu3_di : std_logic_vector( 7 downto 0); + signal cpu3_do : std_logic_vector( 7 downto 0); + signal cpu3_wr_n : std_logic; + signal cpu3_mreq_n : std_logic; + signal cpu3_nmi_n : std_logic; + + + signal bgtile_addr : std_logic_vector(15 downto 0); + signal sprite_addr : std_logic_vector(15 downto 0); + + signal cpu1_rom_do : std_logic_vector( 7 downto 0); + signal cpu2_rom_do : std_logic_vector( 7 downto 0); + signal cpu3_rom_do : std_logic_vector( 7 downto 0); + + signal bgram_do : std_logic_vector( 7 downto 0); + signal bgram_we : std_logic; + signal wram1_do : std_logic_vector( 7 downto 0); + signal wram1_we : std_logic; + signal wram2_do : std_logic_vector( 7 downto 0); + signal wram2_we : std_logic; + signal wram3_do : std_logic_vector( 7 downto 0); + signal wram3_we : std_logic; + signal port_we : std_logic; + + signal slot : std_logic_vector(2 downto 0) := (others => '0'); + signal mux_addr : std_logic_vector(15 downto 0); + signal mux_cpu_do : std_logic_vector( 7 downto 0); + signal mux_cpu_we : std_logic; + signal mux_cpu_mreq : std_logic; + signal latch_we : std_logic; + signal io_we : std_logic; + + signal cs06XX_control : std_logic_vector( 7 downto 0); + signal cs06XX_do : std_logic_vector( 7 downto 0); + signal cs06XX_di : std_logic_vector( 7 downto 0); + + signal cs51XX_data_cnt : std_logic_vector( 1 downto 0); + signal cs51XX_coin_mode_cnt : std_logic_vector( 2 downto 0); + signal cs51XX_switch_mode : std_logic; + signal cs51XX_credit_mode : std_logic; + signal cs51XX_do : std_logic_vector( 7 downto 0); + signal cs51XX_switch_mode_do : std_logic_vector( 7 downto 0); + signal cs51XX_non_switch_mode_do : std_logic_vector( 7 downto 0); + signal change_next : std_logic; + signal credit_bcd_0 : std_logic_vector( 3 downto 0); + signal credit_bcd_1 : std_logic_vector( 3 downto 0); + + signal cs54XX_cmd : std_logic_vector( 3 downto 0); + signal cs54XX_do : std_logic_vector( 7 downto 0); + + signal cs05XX_ctrl : std_logic_vector( 5 downto 0); + + signal dip_switch_a : std_logic_vector (7 downto 0); + signal dip_switch_b : std_logic_vector (7 downto 0); + signal dip_switch_do : std_logic_vector (1 downto 0); + + signal bgtile_num : std_logic_vector( 7 downto 0); + signal bgtile_num_r : std_logic_vector( 7 downto 0); + signal bgtile_color : std_logic_vector( 7 downto 0); + signal bgtile_color_r : std_logic_vector( 7 downto 0); + signal bggraphx_addr : std_logic_vector(11 downto 0); + signal bggraphx_do : std_logic_vector( 7 downto 0); + signal bgpalette_addr : std_logic_vector( 7 downto 0); + signal bgpalette_do : std_logic_vector( 3 downto 0); + signal bgbits : std_logic_vector( 3 downto 0); + + signal rgb_palette_addr : std_logic_vector( 4 downto 0); + signal rgb_palette_do : std_logic_vector( 7 downto 0); + + signal sprite_num : std_logic_vector(5 downto 0); + signal sprite_state : std_logic_vector(2 downto 0); + signal sprite_line : std_logic_vector(7 downto 0); + signal sptile_num : std_logic_vector(7 downto 0); + signal sptile_color : std_logic_vector(7 downto 0); + signal spdata : std_logic_vector(3 downto 0); + signal spvcnt : std_logic_vector(4 downto 0); + signal sphcnt : std_logic_vector(4 downto 0); + signal spram_wr_addr : std_logic_vector(8 downto 0); + signal spram_rd_addr : std_logic_vector(8 downto 0); + signal spram_we : std_logic; + signal spram_clr : std_logic; + signal spgraphx_addr : std_logic_vector(12 downto 0); + signal spgraphx_do : std_logic_vector(7 downto 0); + signal sppalette_addr : std_logic_vector(7 downto 0); + signal sppalette_do : std_logic_vector(3 downto 0); + signal spbits_wr : std_logic_vector(3 downto 0); + signal spbits_rd : std_logic_vector(3 downto 0); + signal spflip_V ,spflip_H : std_logic; + signal spflip_2V,spflip_2H : std_logic_vector(1 downto 0); + signal spflip_3V,spflip_3H : std_logic_vector(2 downto 0); + signal spflips : std_logic_vector(12 downto 0); + + signal flip_h : std_logic; + + signal spram1_addr : std_logic_vector(8 downto 0); + signal spram1_di : std_logic_vector(3 downto 0); + signal spram1_do : std_logic_vector(3 downto 0); + signal spram1_we : std_logic; + signal spram2_addr : std_logic_vector(8 downto 0); + signal spram2_di : std_logic_vector(3 downto 0); + signal spram2_do : std_logic_vector(3 downto 0); + signal spram2_we : std_logic; + + signal stars_hcnt : std_logic_vector( 8 downto 0); + signal stars_vcnt : std_logic_vector( 8 downto 0); + signal stars_offset : std_logic_vector( 7 downto 0); + signal stars_set0_addr : std_logic_vector( 6 downto 0); + signal stars_set0_data : std_logic_vector(15 downto 0); + signal star_color_set0 : std_logic_vector( 5 downto 0); + signal stars_set1_addr : std_logic_vector( 6 downto 0); + signal stars_set1_data : std_logic_vector(15 downto 0); + signal star_color_set1 : std_logic_vector( 5 downto 0); + signal stars_set2_addr : std_logic_vector( 6 downto 0); + signal stars_set2_data : std_logic_vector(15 downto 0); + signal star_color_set2 : std_logic_vector( 5 downto 0); + signal stars_set3_addr : std_logic_vector( 6 downto 0); + signal stars_set3_data : std_logic_vector(15 downto 0); + signal star_color_set3 : std_logic_vector( 5 downto 0); + signal star_color : std_logic_vector( 5 downto 0); + + signal irq1_clr_n : std_logic; + signal irq2_clr_n : std_logic; + signal nmion_n : std_logic; + signal reset_cpu_n : std_logic; + + signal snd_ram_0_we : std_logic; + signal snd_ram_1_we : std_logic; + + signal coin_r : std_logic; + signal start1_r : std_logic; + signal start2_r : std_logic; + +begin + +pix_ce <= ena_vidgen; +clock_18n <= not clock_18; +reset_n <= not reset; + +dip_switch_a <= "11110111"; -- cab:7 / na:6 / test:5 / freeze:4 / demo sound:3 / na:2 / difficulty:1-0 +dip_switch_b <= "10010111"; --lives:7-6/ bonus:5-3 / coinage:2-0 +dip_switch_do <= dip_switch_a(to_integer(unsigned(mux_addr(3 downto 0)))) & + dip_switch_b(to_integer(unsigned(mux_addr(3 downto 0)))); + +-- make access slots from 18MHz +-- 6MHz for pixel clock and sound machine +-- 3MHz for cpu, background and sprite machine + +-- slots | 0 | 1 | 2 | 3 | 4 | 5 | +-- wram access | cpu1 | cpu2 | cpu3 | bgram | spram | n.u. | +-- sound access | cpu1 | cpu2 | cpu3 | sndram | n.u. | sndram| + +-- enable signals are one slot early + +process (clock_18) +begin + if rising_edge(clock_18) then + ena_vidgen <= '0'; + ena_snd_machine <= '0'; + cpu1_ena <= '0'; + cpu2_ena <= '0'; + cpu3_ena <= '0'; + + if slot = "101" then + slot <= (others => '0'); + else + slot <= std_logic_vector(unsigned(slot) + 1); + end if; + + if slot = "101" or slot = "010" then ena_vidgen <= '1'; end if; + if slot = "010" or slot = "100" then ena_snd_machine <= '1'; end if; + if slot = "101" then cpu1_ena <= '1'; end if; + if slot = "000" then cpu2_ena <= '1'; end if; + if slot = "001" then cpu3_ena <= '1'; end if; + + end if; +end process; + +--- SPRITES MACHINE --- +----------------------- + +-- 0x8B80 - 0x8BFF : 64 sprites tile num, tile color +-- 0x9380 - 0x93FF : 64 sprites pos v, pos h lsb +-- 0x9B80 - 0x9BFF : 64 sprites 2xH, 2xV, flip H, flip V + +sprite_addr <= X"03"&'1' & sprite_num & sprite_state(0); +sprite_line <= wram2_do + vcnt(7 downto 0); + +process (clock_18, slot) +begin + if rising_edge(clock_18) then + if hcnt = std_logic_vector(to_unsigned(191,9)) then + sprite_num <= "000000"; + sprite_state <= "000"; + spram_rd_addr<= "111101111"; + end if; + + if slot = "100" and sprite_state = "000" then + sptile_num <= wram1_do; + spdata <= wram3_do(3 downto 0); + spvcnt <= sprite_line(4 downto 0); + if sprite_line(7 downto 4) = "1111" or -- size V x 1 + (sprite_line(7 downto 5) = "111" and wram3_do(3)='1' )then -- size V x 2 -- fixed Dar : 04/11/2017 +-- (sprite_line(7 downto 5) = "111" and wram3_do(2)='1' )then -- size V x 2 + sprite_state <= "001"; + else + if sprite_num = "111111" then + sprite_state <= "111"; + else + sprite_num <= sprite_num + "000001"; + sprite_state <= "000"; + end if; + end if; + end if; + + if slot = "100" and sprite_state = "001" then + sptile_color <= wram1_do; + spram_wr_addr <= wram3_do(0) & wram2_do; + sphcnt <= "00000"; + sprite_state <= "010"; + end if; + + if sprite_state = "010" then + sphcnt <= sphcnt + "00001"; + sprite_state <= "011"; + end if; + + if sprite_state = "011" then + sphcnt <= sphcnt + "00001"; + spram_wr_addr <= spram_wr_addr + "000000001"; + if (sphcnt = "01111" and spdata(2) = '0' ) or -- size H x 1 -- fixed Dar : 04/11/2017 + (sphcnt = "11111" and spdata(2) = '1' ) then -- size H x 2 -- fixed Dar : 04/11/2017 +-- if (sphcnt = "01111" and spdata(3) = '0' ) or -- size H x 1 +-- (sphcnt = "11111" and spdata(3) = '1' ) then -- size H x 2 + if sprite_num = "111111" then + sprite_state <= "111"; + else + sprite_num <= sprite_num + "000001"; + sprite_state <= "000"; + end if; + end if; + end if; + + if slot = "000" or slot = "011" then + if vcnt(0) = '1' then + spbits_rd <= spram2_do; + else + spbits_rd <= spram1_do; + end if; + end if; + + spram_clr <= '0'; + if slot = "001" or slot = "100" then + spram_clr <= '1'; + end if; + + if slot = "010" or slot = "101" then + spram_rd_addr <= spram_rd_addr + "000000001"; + end if; + + end if; +end process; + +spram_we <= '1' when sprite_state = "011" and spbits_wr /= "1111" else '0'; + +spram1_addr <= spram_wr_addr when vcnt(0) = '1' else spram_rd_addr; +spram2_addr <= spram_wr_addr when vcnt(0) = '0' else spram_rd_addr; + +spram1_di <= spbits_wr when vcnt(0) = '1' else "1111"; +spram2_di <= spbits_wr when vcnt(0) = '0' else "1111"; + +spram1_we <= spram_we when vcnt(0) = '1' else spram_clr; +spram2_we <= spram_we when vcnt(0) = '0' else spram_clr; + +spflip_H <= spdata(0) xor flip_h; spflip_2H <= spflip_H & spflip_H; +spflip_V <= spdata(1); spflip_2V <= spflip_V & spflip_V; + +with spdata(3 downto 2) select +spflips <= "0000000" & spflip_V & spflip_2H & spflip_V & spflip_2V when "00", + "000000" & spflip_H & spflip_V & spflip_2H & spflip_V & spflip_2V when "01", + "00000" & spflip_V & '0' & spflip_V & spflip_2H & spflip_V & spflip_2V when "10", + "00000" & spflip_V & spflip_H & spflip_V & spflip_2H & spflip_V & spflip_2V when others; + +with spdata(3 downto 2) select +spgraphx_addr <= (sptile_num(6 downto 0) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "00", + (sptile_num(6 downto 1) & sphcnt(4) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "01", + (sptile_num(6 downto 2) & spvcnt(4) & sptile_num(0) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "10", + (sptile_num(6 downto 2) & spvcnt(4) & sphcnt(4) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when others; + +sppalette_addr <= sptile_color(5 downto 0) & + spgraphx_do(to_integer(unsigned('1' & ((not sphcnt(1 downto 0)) xor spflip_2H )))) & + spgraphx_do(to_integer(unsigned('0' & ((not sphcnt(1 downto 0)) xor spflip_2H )))); + +spbits_wr <= sppalette_do; + +--- BACKGROUND TILES MACHINE --- +-----------------------_-------- + +-- 0x8000-0x83FF : tile num +-- 0x8400-0x87FF : tile color + +bgtile_addr <= "10000" & hcnt(1) & vcnt(7 downto 3) & hcnt(7 downto 3) when (hcnt(8)='1' and flip_h='0') else + "10000" & hcnt(1) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(3) & vcnt(7 downto 3) when (hcnt(8)='0' and flip_h='0') else + "10000" & hcnt(1) & not( vcnt(7 downto 3) & hcnt(7 downto 3)) when (hcnt(8)='1' and flip_h='1') else + "10000" & hcnt(1) & not( hcnt(4) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(3) & vcnt(7 downto 3)); + + +-- Attention : slot et hcnt ne sont pas entierement synchronisés +-- slot |0 |1 | 2 |3 |4 |5 | ... +-- hcnt | 0 or 1 | 1 or 2 | ... + +process (clock_18, slot) +begin + if rising_edge(clock_18) then + if slot = "011" and hcnt(2 downto 1) = "00" then + bgtile_num <= bgram_do; + end if; + if slot = "011" and hcnt(2 downto 1) = "01" then + bgtile_color <= bgram_do; + end if; + if (slot = "000" or slot = "011") and hcnt(2 downto 0) = "111" then + bgtile_num_r <= bgtile_num; + bgtile_color_r <= bgtile_color; + end if; + end if; +end process; + +bggraphx_addr <= '1' & bgtile_num_r(6 downto 0) & not hcnt(2) & vcnt(2 downto 0) when flip_h='0' else + '1' & bgtile_num_r(6 downto 0) & hcnt(2) & not vcnt(2 downto 0); + +bgpalette_addr <= bgtile_color_r(5 downto 0) & + bggraphx_do(to_integer(unsigned('1' & (hcnt(1 downto 0)) xor (flip_h & flip_h)))) & + bggraphx_do(to_integer(unsigned('0' & (hcnt(1 downto 0)) xor (flip_h & flip_h)))); + +bgbits <= bgpalette_do; + +--- STARS MACHINE --- +--------------------- + +stars_data : entity work.stars +port map( + clk => clock_18n, + addr_set0 => stars_set0_addr, + data_set0 => stars_set0_data, + addr_set1 => stars_set1_addr, + data_set1 => stars_set1_data, + addr_set2 => stars_set2_addr, + data_set2 => stars_set2_data, + addr_set3 => stars_set3_addr, + data_set3 => stars_set3_data +); + +stars_machine_0 : entity work.stars_machine +port map( + clk => clock_18, + ena_hcnt => ena_vidgen, + hcnt => stars_hcnt, + vcnt => stars_vcnt, + stars_set_addr_o => stars_set0_addr, + stars_set_data => stars_set0_data, + offset_y => stars_offset, + star_color => star_color_set0 +); + +stars_machine_1 : entity work.stars_machine +port map( + clk => clock_18, + ena_hcnt => ena_vidgen, + hcnt => stars_hcnt, + vcnt => stars_vcnt, + stars_set_addr_o => stars_set1_addr, + stars_set_data => stars_set1_data, + offset_y => stars_offset, + star_color => star_color_set1 +); + +stars_machine_2 : entity work.stars_machine +port map( + clk => clock_18, + ena_hcnt => ena_vidgen, + hcnt => stars_hcnt, + vcnt => stars_vcnt, + stars_set_addr_o => stars_set2_addr, + stars_set_data => stars_set2_data, + offset_y => stars_offset, + star_color => star_color_set2 +); + +stars_machine_3 : entity work.stars_machine +port map( + clk => clock_18, + ena_hcnt => ena_vidgen, + hcnt => stars_hcnt, + vcnt => stars_vcnt, + stars_set_addr_o => stars_set3_addr, + stars_set_data => stars_set3_data, + offset_y => stars_offset, + star_color => star_color_set3 +); + +process (clock_18) + subtype speed is integer range -3 to 3; + type speed_array is array(0 to 7) of speed; + constant speeds : speed_array := ( -1, -2, -3, 0, 3, 2, 1, 0 ); +begin + if rising_edge(clock_18) then + + if ena_vidgen = '1' then + if hcnt = std_logic_vector(to_unsigned(256+8,9)) then + stars_hcnt <= "000000000"; + stars_vcnt <= stars_vcnt + "000000001"; + if vcnt = std_logic_vector(to_unsigned(128+6,9)) then + stars_vcnt <= "000000000"; + stars_offset <= stars_offset + + std_logic_vector(to_signed(speeds(to_integer(unsigned(cs05XX_ctrl(2 downto 0)))),8)); + end if; + else + stars_hcnt <= stars_hcnt + "000000001"; + end if; + end if; + + star_color <= "000000"; + if cs05XX_ctrl(5) = '1' then + if cs05XX_ctrl(4 downto 3) = "00" then star_color <= star_color_set0 or star_color_set2; end if; + if cs05XX_ctrl(4 downto 3) = "01" then star_color <= star_color_set1 or star_color_set2; end if; + if cs05XX_ctrl(4 downto 3) = "10" then star_color <= star_color_set0 or star_color_set3; end if; + if cs05XX_ctrl(4 downto 3) = "11" then star_color <= star_color_set1 or star_color_set3; end if; + end if; + + end if; +end process; + +--- VIDEO MUX --- +----------------- + +rgb_palette_addr <= ('0' & spbits_rd) when bgbits = "1111" else ('1' & bgbits); + +process (clock_18) begin + if rising_edge(clock_18) then + if ena_vidgen = '1' then + if rgb_palette_addr(3 downto 0) = "1111" then + video_r <= star_color(1 downto 0) & star_color(1); + video_g <= star_color(3 downto 2) & star_color(3); + video_b <= star_color(5 downto 4); + else + video_r <= rgb_palette_do(2 downto 0); + video_g <= rgb_palette_do(5 downto 3); + video_b <= rgb_palette_do(7 downto 6); + end if; + end if; + end if; +end process; + + +--- SOUND MACHINE --- +--------------------- + +sound_machine : entity work.sound_machine +port map( +clock_18 => clock_18, +ena => ena_snd_machine, +hcnt => hcnt(5 downto 0), +cpu_addr => mux_addr(3 downto 0), +cpu_do => mux_cpu_do(3 downto 0), +ram_0_we => snd_ram_0_we, +ram_1_we => snd_ram_1_we, +audio => audio +); + +--- CPUS ------------- +---------------------- + +with slot select +mux_addr <= cpu1_addr when "000", + cpu2_addr when "001", + cpu3_addr when "010", + bgtile_addr when "011", + sprite_addr when "100", + X"5555" when others; + +with slot select +mux_cpu_do <= cpu1_do when "000", + cpu2_do when "001", + cpu3_do when "010", + X"00" when others; + +mux_cpu_we <= (not cpu1_wr_n and cpu1_ena)or + (not cpu2_wr_n and cpu2_ena)or + (not cpu3_wr_n and cpu3_ena); + +mux_cpu_mreq <= (not cpu1_mreq_n and cpu1_ena) or + (not cpu2_mreq_n and cpu2_ena) or + (not cpu3_mreq_n and cpu3_ena); + +latch_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "01101" else '0'; +io_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "01110" else '0'; +bgram_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "10000" else '0'; +wram1_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "10001" else '0'; +wram2_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "10010" else '0'; +wram3_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "10011" else '0'; +port_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "10100" else '0'; + +snd_ram_0_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "01101" and mux_addr(5 downto 4) = "00" else '0'; +snd_ram_1_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "01101" and mux_addr(5 downto 4) = "01" else '0'; + +process (reset, clock_18n, io_we) + variable cs06XX_nmi_cnt : natural range 0 to 1000; +begin + if reset='1' then + irq1_clr_n <= '0'; + irq2_clr_n <= '0'; + nmion_n <= '0'; + reset_cpu_n <= '0'; + cpu1_irq_n <= '1'; + cpu2_irq_n <= '1'; + cs51XX_coin_mode_cnt <= "000"; + cs51XX_data_cnt <= "00"; + cs05XX_ctrl <= "000000"; + flip_h <= '0'; + else + if rising_edge(clock_18n) then + if latch_we ='1' and mux_addr(5 downto 4) = "10" then + if mux_addr(2 downto 0) = "000" then irq1_clr_n <= mux_cpu_do(0); end if; + if mux_addr(2 downto 0) = "001" then irq2_clr_n <= mux_cpu_do(0); end if; + if mux_addr(2 downto 0) = "010" then nmion_n <= mux_cpu_do(0); end if; + if mux_addr(2 downto 0) = "011" then reset_cpu_n <= mux_cpu_do(0); end if; + end if; + + if port_we ='1' then + if mux_addr(2 downto 0) < "110" then cs05XX_ctrl(to_integer(unsigned(mux_addr(2 downto 0)))) <= mux_cpu_do(0); end if; + if mux_addr(2 downto 0) = "111" then flip_h <= mux_cpu_do(0); end if; + end if; + + if irq1_clr_n = '0' then + cpu1_irq_n <= '1'; + elsif vcnt = std_logic_vector(to_unsigned(240,9)) then cpu1_irq_n <= '0'; + end if; + if irq2_clr_n = '0' then + cpu2_irq_n <= '1'; + elsif vcnt = std_logic_vector(to_unsigned(240,9)) then cpu2_irq_n <= '0'; + end if; + + -- write to cs06XX + if io_we = '1' then + -- write to data register (0x7000) + if mux_addr(8) = '0' then + -- write data to device#1 (cs51XX) + if cs06XX_control(3 downto 0) = "0001" then + -- when not in coin mode + if cs51XX_coin_mode_cnt = "000" then + -- if data = 1 enter coin mode for next 4 write operations + if mux_cpu_do(2 downto 0) = "001" then + cs51XX_coin_mode_cnt <= "100"; + end if; + -- if data = 2 enter credit mode + if mux_cpu_do(2 downto 0) = "010" then + cs51XX_switch_mode <= '0'; + cs51XX_credit_mode <= '1'; + cs51XX_data_cnt <= "00"; + end if; + -- if data = 5 enter switch mode + if mux_cpu_do(2 downto 0) = "101" then + cs51XX_switch_mode <= '1'; + cs51XX_credit_mode <= '0'; + cs51XX_data_cnt <= "00"; + end if; + -- when in coin mode + else + -- written coin/credit data are ignored atm + -- only count down to exit coin_mode (request 4 write operations) + cs51XX_coin_mode_cnt <= cs51XX_coin_mode_cnt - "001"; + end if; + end if; + end if; + + -- write to control register (0x7100) + if mux_addr(8) = '1' then + cs06XX_control <= mux_cpu_do; + -- start/stop nmi timer + if mux_cpu_do(3 downto 0) = "0000" then + cs06XX_nmi_cnt := 0; + cpu1_nmi_n <= '1'; + else + cs06XX_nmi_cnt := 1; + end if; + end if; + end if; + + -- generate periodic nmi when timer is on + if cs06XX_nmi_cnt >= 1 then + if cpu1_ena = '1' then -- to get 333ns tick + -- 600 * 333ns = 200µs + if cs06XX_nmi_cnt < 600 then + cs06XX_nmi_cnt := cs06XX_nmi_cnt + 1; + cpu1_nmi_n <= '1'; + else + cs06XX_nmi_cnt := 1; + cpu1_nmi_n <= '0'; + end if; + end if; + end if; + + -- manage cs06XX data read + change_next <= '0'; + if mux_cpu_mreq = '1' and mux_cpu_we ='0' and mux_addr(15 downto 11) = "01110" then + if mux_addr(8) = '0' then + change_next <= '1'; + end if; + end if ; + -- cycle data_cnt at each read + if change_next = '1' then + if cs06XX_control(3 downto 0) = "0001" then + if cs51XX_data_cnt = "10" then cs51XX_data_cnt <= "00"; + else cs51XX_data_cnt <= cs51XX_data_cnt + "01"; end if; + end if; + end if; + + -- manage credit count (bcd) + -- increase at each coin up to 99 + coin_r <= coin; + start1_r <= start1; + start2_r <= start2; + if coin = '1' and coin_r = '0' then + if credit_bcd_0 = "1001" then + if credit_bcd_1 /= "1001" then + credit_bcd_1 <= credit_bcd_1 + "0001"; + credit_bcd_0 <= "0000"; + end if; + else + credit_bcd_0 <= credit_bcd_0 + "0001"; + end if; + end if; + + -- decrease only when in credit mode + if cs51XX_credit_mode = '1' then + if (start1 = '1' and start1_r = '0') then + cs51XX_credit_mode <= '0'; + if credit_bcd_0 = "0000" then + if credit_bcd_1 /= "0000" then + credit_bcd_1 <= credit_bcd_1 - "0001"; + credit_bcd_0 <= "1001"; + end if; + else + credit_bcd_0 <= credit_bcd_0 - "0001"; + end if; + end if; + + if (start2 = '1' and start2_r = '0') then + if credit_bcd_0 = "0000" or credit_bcd_0 = "0001" then + if credit_bcd_1 /= "0000" then + cs51XX_credit_mode <= '0'; + credit_bcd_1 <= credit_bcd_1 - "0001"; + if credit_bcd_0 = "0000" then + credit_bcd_0 <= "1000"; + else + credit_bcd_0 <= "1001"; + end if; + end if; + else + cs51XX_credit_mode <= '0'; + credit_bcd_0 <= credit_bcd_0 - "0010"; + end if; + end if; + end if; + + end if; + end if; +end process; + +with cs51XX_data_cnt select +cs51XX_switch_mode_do <= not (left2 & '0' & right2 & '0' & left1 & '0' & right1 & '0' ) when "00", + not (b_test & b_svce & '0' & coin & start2 & start1 & fire2 & fire1) when "01", + X"00" when others; + +with cs51XX_data_cnt select +cs51XX_non_switch_mode_do <= credit_bcd_1 & credit_bcd_0 when "00", -- credits (cpu spy this) + not ("110" & fire1 & left1 & '0' & right1 & '0' ) when "01", + not ("110" & fire2 & left2 & '0' & right2 & '0' ) when "10", + X"00" when "11"; -- N.U. + +cs51XX_do <= cs51XX_switch_mode_do when cs51XX_switch_mode = '1' else cs51XX_non_switch_mode_do; + +cs54XX_do <= X"FF"; -- todo (maybe) + +with cs06XX_control(3 downto 0) select +cs06XX_di <= cs51XX_do when "0001", + cs54XX_do when "1000", + X"00" when others; + +cs06XX_do <= cs06XX_di when mux_addr(8)= '0' else cs06XX_control; + +process (clock_18, nmion_n) +begin + if nmion_n = '1' then + elsif rising_edge(clock_18) then + if ena_vidgen = '1' then + if hcnt = "100000000" then + if vcnt = "001000000" or vcnt = "011000000" then cpu3_nmi_n <= '0'; end if; + if vcnt = "001000001" or vcnt = "011000001" then cpu3_nmi_n <= '1'; end if; + end if; + end if; + end if; +end process; + +with cpu1_addr(15 downto 11) select +cpu1_di <= cpu1_rom_do when "00000", + cpu1_rom_do when "00001", + cpu1_rom_do when "00010", + cpu1_rom_do when "00011", + cpu1_rom_do when "00100", + cpu1_rom_do when "00101", + cpu1_rom_do when "00110", + cpu1_rom_do when "00111", + "000000" & dip_switch_do when "01101", + cs06XX_do when "01110", + bgram_do when "10000", + wram1_do when "10001", + wram2_do when "10010", + wram3_do when "10011", + X"00" when others; + +with cpu2_addr(15 downto 11) select +cpu2_di <= cpu2_rom_do when "00000", + cpu2_rom_do when "00001", + "000000" & dip_switch_do when "01101", + cs06XX_do when "01110", + bgram_do when "10000", + wram1_do when "10001", + wram2_do when "10010", + wram3_do when "10011", + X"00" when others; + +with cpu3_addr(15 downto 11) select +cpu3_di <= cpu3_rom_do when "00000", + cpu3_rom_do when "00001", + "000000" & dip_switch_do when "01101", + cs06XX_do when "01110", + bgram_do when "10000", + wram1_do when "10001", + wram2_do when "10010", + wram3_do when "10011", + X"00" when others; + +-- video address/sync generator +gen_video : entity work.gen_video +port map( +clk => clock_18, +enable => ena_vidgen, +hcnt => hcnt, +vcnt => vcnt, +hsync => video_hs, +vsync => video_vs, +blankn => video_blankn +); + +-- microprocessor Z80 - 1 +cpu1 : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_18, + CLKEN => cpu1_ena, + WAIT_n => '1', + INT_n => cpu1_irq_n, + NMI_n => cpu1_nmi_n, + BUSRQ_n => '1', + M1_n => open, + MREQ_n => cpu1_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu1_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu1_addr, + DI => cpu1_di, + DO => cpu1_do +); + +-- microprocessor Z80 - 2 +cpu2 : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( +-- RESET_n => reset_n, + RESET_n => reset_cpu_n, + CLK_n => clock_18, + CLKEN => cpu2_ena, + WAIT_n => '1', + INT_n => cpu2_irq_n, + NMI_n => '1', --cpu_int_n, + BUSRQ_n => '1', + M1_n => open, + MREQ_n => cpu2_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu2_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu2_addr, + DI => cpu2_di, + DO => cpu2_do +); + +-- microprocessor Z80 - 3 +cpu3 : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( +-- RESET_n => reset_n, + RESET_n => reset_cpu_n, + CLK_n => clock_18, + CLKEN => cpu3_ena, + WAIT_n => '1', + INT_n => '1', + NMI_n => cpu3_nmi_n, + BUSRQ_n => '1', + M1_n => open, + MREQ_n => cpu3_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu3_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu3_addr, + DI => cpu3_di, + DO => cpu3_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.galaga_cpu1 +port map( + clk => clock_18n, + addr => mux_addr(13 downto 0), + data => cpu1_rom_do +); + +-- cpu2 program ROM +rom_cpu2 : entity work.galaga_cpu2 +port map( + clk => clock_18n, + addr => mux_addr(11 downto 0), + data => cpu2_rom_do +); + +-- cpu3 program ROM +rom_cpu3 : entity work.galaga_cpu3 +port map( + clk => clock_18n, + addr => mux_addr(11 downto 0), + data => cpu3_rom_do +); +-- background graphics ROM +bg_graphics : entity work.bg_graphx +port map( + clk => clock_18n, + addr => bggraphx_addr(11 downto 0), + data => bggraphx_do +); + +-- background palette ROM +bg_palette : entity work.bg_palette +port map( + clk => clock_18, + addr => bgpalette_addr, + data => bgpalette_do +); + +-- background char RAM 0x8000-0x87FF +bgram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_18n, + we => bgram_we, + addr => mux_addr(10 downto 0), + d => mux_cpu_do, + q => bgram_do +); +-- working/sprite register RAM1 0x8800-0x8BFF / 0x8C00-0x8FFF +wram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_18n, + we => wram1_we, + addr => mux_addr(9 downto 0), + d => mux_cpu_do, + q => wram1_do +); +-- working/sprite register RAM2 0x9000-0x93FF / 0x9400-0x97FF +wram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_18n, + we => wram2_we, + addr => mux_addr(9 downto 0), + d => mux_cpu_do, + q => wram2_do +); +-- working/sprite register RAM3 0x9800-0x9BFF / 0x9C00-0x9FFF +wram3 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_18n, + we => wram3_we, + addr => mux_addr(9 downto 0), + d => mux_cpu_do, + q => wram3_do +); + +-- sprite RAM1 +spram1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 9) +port map( + clk => clock_18, + we => spram1_we, + addr => spram1_addr, + d => spram1_di, + q => spram1_do +); + +-- sprite RAM2 +spram2 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 9) +port map( + clk => clock_18, + we => spram2_we, + addr => spram2_addr, + d => spram2_di, + q => spram2_do +); + +-- sprite graphics ROM +sp_graphics : entity work.sp_graphx +port map( + clk => clock_18n, + addr => spgraphx_addr, + data => spgraphx_do +); + +-- sprite palette ROM +sp_palette : entity work.sp_palette +port map( + clk => clock_18, + addr => sppalette_addr, + data => sppalette_do +); + +-- RGB palette ROM +rgb_palette : entity work.rgb +port map( + clk => clock_18, + addr => rgb_palette_addr, + data => rgb_palette_do +); + +end struct; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd new file mode 100644 index 00000000..6e089ceb --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd @@ -0,0 +1,277 @@ +--------------------------------------------------------------------------------- +-- Mist FPGA Top level for Galaga Midway by Gehstock. Original DE2 Toplevel by Dar (darfpga@aol.fr) (December 2016) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- +-- Main features : +-- PS2 keyboard input +-- Joystick input +-- Sigma Delta sound output +-- NO board SRAM/Flash used +-- +-- Uses 1 pll for 18MHz, 11MHz and 14khz generation from 27MHz +-- +-- Board key : +-- 0 : reset +-- +-- Keyboard inputs : +-- ESC : Add coin +-- 1 : Start 1 player +-- 2 : Start 2 players +-- SPACE : Fire player 1 & 2 +-- UP arrow : Move right player 1 & 2 +-- DOWN arrow : Move left player 1 & 2 +-- +-- Dip switch and other details : see galaga.vhd + +--------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + +entity galaga_mist is +port( + CLOCK_27 : in std_logic; + LED : out std_logic; + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0); + VGA_HS : out std_logic; + VGA_VS : out std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic + +); +end galaga_mist; + +architecture struct of galaga_mist is + signal clock_72 : std_logic; + signal clock_18 : std_logic; + signal pll_locked : std_logic; + signal r : std_logic_vector(2 downto 0); + signal g : std_logic_vector(2 downto 0); + signal b : std_logic_vector(1 downto 0); + signal hsync : std_logic; + signal vsync : std_logic; + signal blankn : std_logic; + signal pix_ce : std_logic; + signal audio : std_logic_vector(9 downto 0); + signal audio_pwm : std_logic; + signal reset : std_logic; + signal scanlines : std_logic_vector(1 downto 0); + signal hq2x : std_logic; + + -- User IO + signal buttons : std_logic_vector(1 downto 0); + signal joy0 : std_logic_vector(7 downto 0); + signal joy1 : std_logic_vector(7 downto 0); + signal status : std_logic_vector(31 downto 0); + signal scandoubler_disable : std_logic; + signal ypbpr : std_logic; + + signal kbd_joy : std_logic_vector(7 downto 0); + signal mright : std_logic; + signal mleft : std_logic; + signal ps2Clk : std_logic; + signal ps2Data : std_logic; + signal ps2_scancode : std_logic_vector(7 downto 0); + + signal VGA_R_O : std_logic_vector(2 downto 0); + signal VGA_G_O : std_logic_vector(2 downto 0); + signal VGA_B_O : std_logic_vector(2 downto 0); + + constant CONF_STR : string := + "Galaga;;O4,Screen Direction,Upright,Normal;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;"; + + function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + end function; + + component mist_io + generic ( STRLEN : integer := 0 ); + port ( + clk_sys :in std_logic; + SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; + SPI_DO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + buttons : out std_logic_vector(1 downto 0); + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + status : out std_logic_vector(31 downto 0); + scandoubler_disable, ypbpr : out std_logic; + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); + end component mist_io; + + component video_mixer + generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 ); + port ( + clk_sys, ce_pix, ce_pix_actual : in std_logic; + SPI_SCK, SPI_SS3, SPI_DI : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; + + R, G, B : in std_logic_vector(2 downto 0); + HSync, VSync, line_start, mono : in std_logic; + + VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); + VGA_VS, VGA_HS : out std_logic + ); + end component video_mixer; + + component keyboard + PORT( + clk : in std_logic; + reset : in std_logic; + ps2_kbd_clk : in std_logic; + ps2_kbd_data : in std_logic; + joystick : out std_logic_vector (7 downto 0) + ); + end component; + +begin + +reset <= status(0) or status(5) or buttons(1) or not pll_locked; + +pll : entity work.pll + port map( + inclk0 => CLOCK_27, + c0 => clock_72, + c1 => clock_18, + locked => pll_locked +); + +scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0'; +scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0'; +hq2x <= '1' when status(9 downto 8) = "01" else '0'; + +vmixer : video_mixer + port map ( + clk_sys => clock_72, + ce_pix => pix_ce, + ce_pix_actual => pix_ce, + + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + + scanlines => scanlines, + scandoubler_disable => scandoubler_disable, + hq2x => hq2x, + ypbpr => ypbpr, + ypbpr_full => '1', + + R => VGA_R_O, + G => VGA_G_O, + B => VGA_B_O, + HSync => hsync, + VSync => vsync, + line_start => '0', + mono => '0', + + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_VS => VGA_VS, + VGA_HS => VGA_HS +); + +mist_io_inst : mist_io + generic map (STRLEN => CONF_STR'length) + port map ( + clk_sys => clock_18, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_DI => SPI_DI, + SPI_DO => SPI_DO, + conf_str => to_slv(CONF_STR), + buttons => buttons, + scandoubler_disable => scandoubler_disable, + ypbpr => ypbpr, + joystick_1 => joy1, + joystick_0 => joy0, + status => status, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data +); + + mleft <= joy0(1) or joy1(1) or kbd_joy(6) when status(4) = '0' else joy0(2) or joy1(2) or kbd_joy(5); + mright <= joy0(0) or joy1(0) or kbd_joy(7) when status(4) = '0' else joy0(3) or joy1(3) or kbd_joy(4); + +galaga : entity work.galaga + port map( + clock_18 => clock_18, + reset => reset, + video_r => r, + video_g => g, + video_b => b, + video_blankn => blankn, + video_hs => hsync, + video_vs => vsync, + pix_ce => pix_ce, + + audio => audio, + b_test => '0', --no Function at all + b_svce => '0', --no Function at all + coin => kbd_joy(3) or status(1), + start1 => kbd_joy(1) or status(2), + start2 => kbd_joy(2) or status(3), + left1 => mleft, + right1 => mright, + fire1 => joy0(4) or joy1(4) or kbd_joy(0), + left2 => mleft, + right2 => mright, + fire2 => joy0(4) or joy1(4) or kbd_joy(0) +); + +VGA_R_O <= r when blankn = '1' else "000"; +VGA_G_O <= g when blankn = '1' else "000"; +VGA_B_O <= b & b(1) when blankn = '1' else "000"; + +u_dac : entity work.dac + port map( + clk_i => clock_18, + res_n_i => not reset, + dac_i => audio, + dac_o => audio_pwm +); + +AUDIO_L <= audio_pwm; +AUDIO_R <= audio_pwm; + +u_keyboard : keyboard + port map( + clk => clock_18, + reset => reset, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data, + joystick => kbd_joy +); + +LED <= '1'; + +end struct; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/gen_ram.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd new file mode 100644 index 00000000..47379532 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/gen_video.vhd @@ -0,0 +1,82 @@ +--------------------------------------------------------------------------------- +-- Galaga video horizontal/vertical and sync generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.ALL; + +entity gen_video is +port( + clk : in std_logic; + enable : in std_logic; + hcnt : out std_logic_vector(8 downto 0); + vcnt : out std_logic_vector(8 downto 0); + hsync : out std_logic; + vsync : out std_logic; + blankn : out std_logic +); +end gen_video; + +architecture struct of gen_video is + signal hblank : std_logic; + signal vblank : std_logic; + signal hcntReg : unsigned (8 DOWNTO 0) := to_unsigned(000,9); + signal vcntReg : unsigned (8 DOWNTO 0) := to_unsigned(015,9); +begin + +hcnt <= std_logic_vector(hcntReg); +vcnt <= std_logic_vector(vcntReg); + +-- Compteur horizontal : 511-128+1=384 pixels (48 tiles) +-- 192 à 255 : 64 pixels debut de ligne (8 dont 2 dernières tiles affichées) +-- 256 à 511 : 256 pixels centre de ligne (32 tiles affichées) +-- 128 à 191 : 64 pixels fin de ligne (8 dont 2 premières tiles affichées) + +-- Compteur vertical : 263-000+1=264 lignes (33 tiles) +-- 000 à 015 : 16 lignes debut de trame (2 tiles) +-- 016 à 239 : 224 lignes centrales (28 tiles affichées) +-- 240 à 263 : 24 lignes fin de trame (3 tiles + +-- Synchro horizontale : hcnt=[176 à 204] (29 pixels) +-- Synchro verticale : vcnt=[260 à 003] ( 8 lignes) + +process(clk) begin + if rising_edge(clk) then -- clk & ena at 6MHz + if enable = '1' then + + if hcntReg = 511 then + hcntReg <= to_unsigned (128,9); + else + hcntReg <= hcntReg + 1; + end if; + + if hcntReg = 191 then + if vcntReg = 261 then + vcntReg <= to_unsigned(0,9); + else + vcntReg <= vcntReg + 1; + end if; + end if; + + if hcntReg = (175+ 0-8+8) then hsync <= '1'; -- 1 + elsif hcntReg = (175+29-8+8) then hsync <= '0'; + end if; + + if vcntReg = 252 then vsync <= '1'; + elsif vcntReg = 260 then vsync <= '0'; + end if; + + if hcntReg = (127+16+8) then hblank <= '1'; + elsif hcntReg = (255-17+8+1) then hblank <= '0'; + end if; + + if vcntReg = (240+1-1) then vblank <= '1'; + elsif vcntReg = (015+1) then vblank <= '0'; + end if; + + blankn <= not (hblank or vblank); + end if; + end if; +end process; + +end architecture; \ No newline at end of file diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/hq2x.sv b/Arcade/Custom Hardware/Galaga_MIST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/keyboard.v b/Arcade/Custom Hardware/Galaga_MIST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/mist_io.v b/Arcade/Custom Hardware/Galaga_MIST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/osd.v b/Arcade/Custom Hardware/Galaga_MIST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/pll.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/pll.vhd new file mode 100644 index 00000000..ce065a7b --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/pll.vhd @@ -0,0 +1,389 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + clk1_divide_by => 3, + clk1_duty_cycle => 50, + clk1_multiply_by => 2, + clk1_phase_shift => "0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NO_COMPENSATION", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "ON", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "13500" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/rgb.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/rgb.vhd new file mode 100644 index 00000000..cb86d09f --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/rgb.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rgb is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rgb is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F6",X"07",X"3F",X"27",X"2F",X"C7",X"F8",X"ED",X"16",X"38",X"21",X"D8",X"C4",X"C0",X"A0",X"00", + X"F6",X"07",X"3F",X"27",X"00",X"C7",X"F8",X"E8",X"00",X"38",X"00",X"D8",X"C5",X"C0",X"00",X"00"); +begin + +data <= rom_data(to_integer(unsigned(addr))); + +end architecture; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/scandoubler.v b/Arcade/Custom Hardware/Galaga_MIST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd new file mode 100644 index 00000000..e8df4c1a --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd @@ -0,0 +1,153 @@ +--------------------------------------------------------------------------------- +-- Galaga sound machine by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- 3 voices frequency/waveform synthetizer +-- +-- Original hardware done with only one 4 bits sequential adder to realise +-- one 20 bits adder and two 16 bits adder. +-- +-- Too nice and clever to be done another way, just doing it the same way! +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity sound_machine is +port( + clock_18 : in std_logic; + hcnt : in std_logic_vector(5 downto 0); + ena : in std_logic; + cpu_addr : in std_logic_vector(3 downto 0); + cpu_do : in std_logic_vector(3 downto 0); + ram_0_we : in std_logic; + ram_1_we : in std_logic; + audio : out std_logic_vector(9 downto 0) +); +end sound_machine; + +architecture struct of sound_machine is + + signal clock_18n : std_logic; + signal snd_ram_addr : std_logic_vector(3 downto 0); + signal snd_ram_di : std_logic_vector(3 downto 0); + signal snd_ram_0_we : std_logic; + signal snd_ram_1_we : std_logic; + signal snd_ram_0_do : std_logic_vector(3 downto 0); + signal snd_ram_1_do : std_logic_vector(3 downto 0); + + signal snd_seq_do : std_logic_vector(3 downto 0); + + signal snd_samples_addr : std_logic_vector(7 downto 0); + signal snd_samples_do : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(4 downto 0) := (others => '0'); + signal sum_r : std_logic_vector(4 downto 0) := (others => '0'); + signal sum_3_rr : std_logic := '0'; + + signal samples_ch0 : std_logic_vector(3 downto 0); + signal samples_ch1 : std_logic_vector(3 downto 0); + signal samples_ch2 : std_logic_vector(3 downto 0); + signal volume_ch0 : std_logic_vector(3 downto 0); + signal volume_ch1 : std_logic_vector(3 downto 0); + signal volume_ch2 : std_logic_vector(3 downto 0); + +begin + +clock_18n <= not clock_18; + +snd_ram_addr <= cpu_addr when (ram_0_we = '1' or ram_1_we = '1') else hcnt(5 downto 2); +snd_ram_di <= cpu_do when (ram_0_we = '1' or ram_1_we = '1') else sum_r(3 downto 0); + +snd_ram_0_we <= (not snd_seq_do(1) and ena) or ram_0_we ; +snd_ram_1_we <= ram_1_we; + +sum <= ('0' & snd_ram_0_do) + ('0' & snd_ram_1_do) + ("0000" & sum_r(4)); + +process (clock_18) + function mul4x4(arg1, arg2: std_logic_vector(3 downto 0)) return std_logic_vector is + variable rval: std_logic_vector(9 downto 0); + begin + rval := "0000000000"; + if arg2(3) = '1' then rval := rval + (arg1 & "000"); end if; + if arg2(2) = '1' then rval := rval + (arg1 & "00"); end if; + if arg2(1) = '1' then rval := rval + (arg1 & "0"); end if; + if arg2(0) = '1' then rval := rval + arg1; end if; + return rval; + end mul4x4; +begin + if rising_edge(clock_18) then + if ena = '1' then + if snd_seq_do(3) = '0' then + sum_r <= (others => '0'); + sum_3_rr <= '0'; + elsif snd_seq_do(0) = '0' then + sum_r <= sum; + sum_3_rr <= sum_r(3); + end if ; + + snd_samples_addr <= snd_ram_0_do(2 downto 0) & sum_r(3 downto 0) & sum_3_rr; + + if snd_seq_do(2) = '0' then + if hcnt(5 downto 2) = X"5" then + samples_ch0 <= snd_samples_do(3 downto 0); + volume_ch0 <= snd_ram_1_do; + end if; + if hcnt(5 downto 2) = X"A" then + samples_ch1 <= snd_samples_do(3 downto 0); + volume_ch1 <= snd_ram_1_do; + end if; + if hcnt(5 downto 2) = X"F" then + samples_ch2 <= snd_samples_do(3 downto 0); + volume_ch2 <= snd_ram_1_do; + end if; + end if; + + audio <= mul4x4(samples_ch0, volume_ch0) + + mul4x4(samples_ch1, volume_ch1) + + mul4x4(samples_ch2, volume_ch2); + end if; + end if; +end process; + +-- sound register RAM0 +sound_ram_0 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 4) +port map( + clk => clock_18n, + we => snd_ram_0_we, + addr => snd_ram_addr, + d => snd_ram_di, + q => snd_ram_0_do +); + +-- sound register RAM1 +sound_ram_1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 4) +port map( + clk => clock_18n, + we => snd_ram_1_we, + addr => snd_ram_addr, + d => snd_ram_di, + q => snd_ram_1_do +); + +-- sound samples ROM +sound_samples : entity work.sound_samples +port map( + clk => clock_18n, + addr => snd_samples_addr, + data => snd_samples_do +); + +-- sound compute sequencer ROM +sound_seq : entity work.sound_seq +port map( + clk => clock_18n, + addr => not ram_0_we & hcnt(5 downto 0), + data => snd_seq_do +); + +end struct; diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/stars.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/stars.vhd new file mode 100644 index 00000000..ba229cb1 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/stars.vhd @@ -0,0 +1,587 @@ +--------------------------------------------------------------------------------- +-- Galaga stars sets generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- Done from only available MAME information +-- +-- star set data description +-- +-- | 8 bits | 8 bits | +-- |------------------------------------| +-- | 0x80 | scan line number | 0x80 id for line number +-- | star 1 color | star 1 position | star color alway < 0x40 +-- | star 2 color | star 2 position | +-- | 0x80 | scan line number | +-- | star 1 color | star 1 position | +-- | 0x80 | scan line number | +-- | star 1 color | star 1 position | from 1 up to 3 stars for +-- | star 2 color | star 2 position | the given scan lien number +-- | star 3 color | star 3 position | +-- ... +-- | 0xC0 | N.U. | end of list +-- +-- Scan line number are 1 less than MAME list because of way of realisation +-- Scan line number are ordered from lower to higher. +-- There are 4 sets of 63 stars max. There can be up to 3 stars max for a given scan line. + + +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity stars is +port ( + clk : in std_logic; + addr_set0 : in std_logic_vector( 6 downto 0); + data_set0 : out std_logic_vector(15 downto 0); + addr_set1 : in std_logic_vector( 6 downto 0); + data_set1 : out std_logic_vector(15 downto 0); + addr_set2 : in std_logic_vector( 6 downto 0); + data_set2 : out std_logic_vector(15 downto 0); + addr_set3 : in std_logic_vector( 6 downto 0); + data_set3 : out std_logic_vector(15 downto 0) +); +end entity; + +architecture stars_table of stars is + +type table0 is array(0 to 127) of std_logic_vector(15 downto 0); +signal data0 : table0 := ( +X"8006", -- line 0x06 +X"3584", -- one star at 0x84, color is 0x35 +X"8008", -- line 0x08 +X"308E", -- one star at 0x8E, color is 0x30 +X"801B", -- ... +X"07E4", +X"801C", +X"3121", +X"8025", +X"1DE4", +X"8026", +X"2914", +X"802D", +X"3B7F", +X"802E", +X"1C96", +X"803B", +X"05B9", +X"803D", +X"3635", +X"8044", -- line 0x44 +X"0956", -- fist star at 0x56, color is 0x09 +X"3DCE", -- second star at 0xCE, color is 0x3D +X"804E", +X"2760", +X"8064", +X"1A86", +X"17D5", +X"806C", +X"3C0A", +X"806D", +X"2405", +X"806E", +X"3A17", +X"8079", +X"23A8", +X"807B", +X"1189", +X"8080", +X"0CD5", +X"8082", +X"3F66", +X"8083", +X"3838", +X"1471", +X"8084", +X"16EB", +X"8085", +X"108D", +X"8088", +X"251F", +X"808A", +X"0F94", +X"808D", +X"000D", +X"8091", +X"2E05", +X"8094", +X"0D06", +X"8097", +X"0BAD", +X"8098", +X"2DFF", +X"809B", +X"0185", +X"80A1", +X"3457", +X"3EFD", +X"80A8", +X"1FA1", +X"80AA", +X"0A40", +X"80AC", +X"323E", +X"03DD", +X"80B9", +X"26D3", +X"80BB", +X"1B6C", +X"80BD", +X"3961", +X"80BE", +X"18C8", +X"80C1", +X"046B", +X"80C3", +X"2158", +X"80CC", +X"0E5F", +X"1290", +X"80CF", +X"063E", +X"22F6", +X"80D0", +X"3343", +X"80D2", +X"0833", +X"80D9", +X"20D2", +X"80DD", +X"3770", +X"80E1", +X"2C72", +X"80E3", +X"2FB8", +X"80E4", +X"13A8", +X"80E7", +X"19D2", +X"80ED", +X"0236", +X"80F4", +X"15BC", +X"80F6", +X"280E", +X"80F7", +X"2B4E", +X"80FF", +X"2AFA", +X"C000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000" +); + +type table1 is array(0 to 127) of std_logic_vector(15 downto 0); +signal data1 : table1 := ( +X"8004", +X"3DFD", +X"8006", +X"10C3", +X"8007", +X"2D1D", +X"800B", +X"1F82", +X"800D", +X"3C2D", +X"800E", +X"001E", +X"2CD7", +X"800F", +X"1702", +X"8011", +X"3F94", +X"8017", +X"3569", +X"02CB", +X"8018", +X"32FF", +X"801D", +X"3691", +X"8021", +X"04E2", +X"802D", +X"372E", +X"802F", +X"0CEF", +X"803E", +X"069A", +X"804C", +X"07A3", +X"804D", +X"13E9", +X"804E", +X"2183", +X"8052", +X"0F32", +X"8053", +X"0E6F", +X"8059", +X"0805", +X"8060", +X"2880", +X"8061", +X"2936", +X"8067", +X"2F8E", +X"806A", +X"1D1A", +X"807C", +X"12BE", +X"807F", +X"3150", +X"8086", +X"2560", +X"808F", +X"0D69", +X"8091", +X"1969", +X"8092", +X"058F", +X"8096", +X"243A", +X"8097", +X"0A8B", +X"8099", +X"0305", +X"3837", +X"18A7", +X"80A6", +X"2075", +X"1CAC", +X"1EEB", +X"80AC", +X"1585", +X"80AF", +X"3E77", +X"80B3", +X"097A", +X"80B8", +X"3926", +X"80C2", +X"2387", +X"80C3", +X"3A43", +X"80C5", +X"34CE", +X"80C9", +X"3034", +X"80D1", +X"3B6D", +X"80D7", +X"16D5", +X"80D9", +X"2B39", +X"80E0", +X"11AA", +X"80E2", +X"1BDF", +X"80E6", +X"0B6E", +X"80E8", +X"14B7", +X"1AD8", +X"22F8", +X"80F1", +X"2E03", +X"80F8", +X"2648", +X"80F9", +X"010F", +X"80FB", +X"3338", +X"80FC", +X"2727", +X"C000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000" +); + +type table2 is array(0 to 127) of std_logic_vector(15 downto 0); +signal data2 : table2 := ( +X"8006", +X"19F9", +X"8007", +X"2DE3", +X"800A", +X"0371", +X"801B", +X"0083", +X"801D", +X"29B9", +X"8022", +X"04E2", +X"8026", +X"2AD0", +X"8032", +X"3088", +X"8036", +X"275A", +X"803A", +X"3683", +X"803F", +X"0D52", +X"8040", +X"1D07", +X"1A54", +X"8041", +X"31A9", +X"2BFA", +X"8046", +X"16BB", +X"8052", +X"3992", +X"8057", +X"10B8", +X"8059", +X"2853", +X"805A", +X"01E5", +X"805D", +X"1BA6", +X"805E", +X"352C", +X"8062", +X"2113", +X"806D", +X"1F68", +X"806F", +X"0BCD", +X"8075", +X"2FDE", +X"8077", +X"12CA", +X"807C", +X"234D", +X"8084", +X"0F49", +X"8086", +X"2511", +X"808C", +X"3267", +X"8095", +X"2002", +X"809C", +X"1709", +X"80A3", +X"085A", +X"80A4", +X"3E5E", +X"2E71", +X"80A6", +X"06CB", +X"80AB", +X"0C89", +X"80AD", +X"26DF", +X"80AF", +X"0AF2", +X"80B4", +X"1374", +X"80B7", +X"1167", +X"80C2", +X"2C6C", +X"80C3", +X"1475", +X"80C4", +X"1ECE", +X"80C5", +X"1C03", +X"80C6", +X"3F12", +X"80C7", +X"3CB8", +X"80D7", +X"3404", +X"3A94", +X"80D8", +X"02FB", +X"80DC", +X"09E6", +X"80E1", +X"051C", +X"80E6", +X"3304", +X"80E9", +X"3B1B", +X"80ED", +X"37A1", +X"80EE", +X"0727", +X"80EF", +X"18DC", +X"80F0", +X"386C", +X"80F2", +X"0EA0", +X"80F7", +X"3D73", +X"80F9", +X"2268", +X"80FF", +X"243E", +X"C000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000" +); + +type table3 is array(0 to 127) of std_logic_vector(15 downto 0); +signal data3 : table3 := ( +X"8010", +X"3470", +X"8011", +X"23AE", +X"8014", +X"269F", +X"8017", +X"0201", +X"8019", +X"314A", +X"801C", +X"0E92", +X"801E", +X"251A", +X"8020", +X"2E31", +X"3AED", +X"8022", +X"2F78", +X"8023", +X"176B", +X"8025", +X"11BB", +X"8029", +X"3040", +X"802E", +X"321B", +X"8031", +X"01B8", +X"8032", +X"0582", +X"803A", +X"1294", +X"803F", +X"070C", +X"8041", +X"331F", +X"8045", +X"2C91", +X"8047", +X"08D3", +X"804B", +X"2DA0", +X"3BD1", +X"8052", +X"24D5", +X"805F", +X"1C99", +X"8060", +X"3D15", +X"8063", +X"1F19", +X"8066", +X"28CC", +X"8067", +X"10FE", +X"8069", +X"2034", +X"806C", +X"048E", +X"2AC9", +X"8074", +X"0959", +X"8078", +X"385F", +X"8079", +X"1E71", +X"807F", +X"2936", +X"8080", +X"1411", +X"8082", +X"2B28", +X"8098", +X"3683", +X"8099", +X"3731", +X"80A0", +X"19BA", +X"80A3", +X"3E3D", +X"80A6", +X"1A49", +X"80A7", +X"2128", +X"80B7", +X"229C", +X"80B9", +X"156B", +X"80C0", +X"0A0B", +X"80C3", +X"0FC1", +X"80C9", +X"0D2E", +X"80CE", +X"16D1", +X"0BF2", +X"80CF", +X"2774", +X"80D5", +X"3519", +X"80D6", +X"3925", +X"80DA", +X"3C7F", +X"80DD", +X"00A8", +X"80EB", +X"03BB", +X"80EF", +X"1B31", +X"80F0", +X"3F66", +X"80F1", +X"18EE", +X"80F3", +X"0CA7", +X"80F9", +X"1DDD", +X"80FA", +X"132B", +X"C000", +X"0000", +X"0000", +X"0000", +X"0000", +X"0000" +); + +begin +process(clk) +begin + if rising_edge(clk) then + data_set0 <= data0(to_integer(unsigned(addr_set0))); + data_set1 <= data1(to_integer(unsigned(addr_set1))); + data_set2 <= data2(to_integer(unsigned(addr_set2))); + data_set3 <= data3(to_integer(unsigned(addr_set3))); + end if; +end process; +end architecture; + diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/stars_machine.vhd b/Arcade/Custom Hardware/Galaga_MIST/rtl/stars_machine.vhd new file mode 100644 index 00000000..e5f51e48 --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/stars_machine.vhd @@ -0,0 +1,126 @@ +--------------------------------------------------------------------------------- +-- Galaga starfield generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- Done from only available MAME information +-- +-- star set data description +-- +-- | 8 bits | 8 bits | +-- |------------------------------------| +-- | 0x80 | scan line number | 0x80 id for line number +-- | star 1 color | star 1 position | star color alway < 0x40 +-- | star 2 color | star 2 position | +-- | 0x80 | scan line number | +-- | star 1 color | star 1 position | +-- | 0x80 | scan line number | +-- | star 1 color | star 1 position | from 1 up to 3 stars for +-- | star 2 color | star 2 position | the given scan lien number +-- | star 3 color | star 3 position | +-- ... +-- | 0xC0 | N.U. | end of list +-- +-- Scan line number are 1 less than MAME list because of way of realisation +-- Scan line number are ordered from lower to higher. + +-- Machine wait for current scan line number to be reach by vcnt then it read +-- from 1 to 3 stars (stop reading if reaching next 0x80). After that machine +-- is ready to wait for next scan line, and so on. Machine loops at start of +-- list if 0xC0 is reached. + +library ieee; +use ieee.std_logic_1164.all,ieee.std_logic_unsigned.all,ieee.numeric_std.all; + +entity stars_machine is +port ( + clk : in std_logic; + ena_hcnt : in std_logic; + hcnt : in std_logic_vector( 8 downto 0); + vcnt : in std_logic_vector( 8 downto 0); + stars_set_addr_o : out std_logic_vector( 6 downto 0); + stars_set_data : in std_logic_vector(15 downto 0); + offset_y : in std_logic_vector( 7 downto 0); + star_color : out std_logic_vector( 5 downto 0) +); +end entity; + +architecture behaviour of stars_machine is + + signal stars_set_addr : std_logic_vector( 6 downto 0); + signal stars_state : std_logic_vector( 2 downto 0); + signal star_0 : std_logic_vector(13 downto 0); + signal star_1 : std_logic_vector(13 downto 0); + signal star_2 : std_logic_vector(13 downto 0); + +begin + +stars_set_addr_o <= stars_set_addr; + +process (clk) +begin + if rising_edge(clk) then + -- chercher la ligne suivante + if stars_state = "000" then + if stars_set_data(15) = '1' then + if stars_set_data(14) = '1' then + stars_set_addr <= "0000000"; + else + stars_state <= "001"; + end if; + else + stars_set_addr <= stars_set_addr + "0000001"; + end if; + end if; + -- attendre que la ligne soit jouée + if stars_state = "001" then + if stars_set_data(7 downto 0) = vcnt(7 downto 0) then + stars_state <= "010"; + stars_set_addr <= stars_set_addr + "0000001"; + end if; + end if; + -- oublier toutes les étoiles en début de balayage ligne + -- attendre que la ligne soit jouée + if hcnt = std_logic_vector(to_unsigned(256,9)) and ena_hcnt = '1' then + star_0 <= (others => '0'); + star_1 <= (others => '0'); + star_2 <= (others => '0'); + if stars_state = "010" then + stars_state <= "011"; + end if; + end if; + -- récupérer la première étoile + if stars_state = "011" then + if stars_set_data(15) = '0' then + star_0 <= stars_set_data(13 downto 0); + stars_set_addr <= stars_set_addr + "0000001"; + end if; + stars_state <= "100"; + end if; + -- récupérer la seconde étoile si il y en a une + if stars_state = "100"then + if stars_set_data(15) = '0' then + star_1 <= stars_set_data(13 downto 0); + stars_set_addr <= stars_set_addr + "0000001"; + end if; + stars_state <= "101"; + end if; + -- récupérer la troisième étoile si il y en a une + if stars_state = "101" then + if stars_set_data(15) = '0' then + star_2 <= stars_set_data(13 downto 0); + stars_set_addr <= stars_set_addr + "0000001"; + end if; + stars_state <= "000"; + end if; + + -- jouer les étoiles récupérées + star_color <= "000000"; + if (hcnt(7 downto 0)- offset_y = star_0(7 downto 0)) and hcnt(8) = '0' then star_color <= star_0(13 downto 8); end if; + if (hcnt(7 downto 0)- offset_y = star_1(7 downto 0)) and hcnt(8) = '0' then star_color <= star_1(13 downto 8); end if; + if (hcnt(7 downto 0)- offset_y = star_2(7 downto 0)) and hcnt(8) = '0' then star_color <= star_2(13 downto 8); end if; + + end if; +end process; +end architecture; + diff --git a/Arcade/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv b/Arcade/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Custom Hardware/Phoenix_MIST/README.txt b/Arcade/Custom Hardware/Phoenix_MIST/README.txt new file mode 100644 index 00000000..35a7077c --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Phoenix for MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- Copyright (c) DAR - Feb 2016 +-- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/phoenix/ +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE : Fire +-- ARROW KEYS : Movement/Shield +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Custom Hardware/Phoenix_MIST/Release/phoenix_mist.rbf b/Arcade/Custom Hardware/Phoenix_MIST/Release/phoenix_mist.rbf new file mode 100644 index 00000000..5f78ba38 Binary files /dev/null and b/Arcade/Custom Hardware/Phoenix_MIST/Release/phoenix_mist.rbf differ diff --git a/Arcade/Custom Hardware/Phoenix_MIST/clean.bat b/Arcade/Custom Hardware/Phoenix_MIST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.qpf b/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.qpf new file mode 100644 index 00000000..2b8ba3ed --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 02:40:30 January 25, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "02:40:30 January 25, 2017" + +# Revisions + +PROJECT_REVISION = "phoenix_mist" \ No newline at end of file diff --git a/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.qsf b/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.qsf new file mode 100644 index 00000000..32fafe8e --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.qsf @@ -0,0 +1,334 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 08:30:59 December 07, 2015 +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY phoenix_mist +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON + +# Fitter Assignments +# ================== +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------ +# start ENTITY(Phoenix_mist) + +# Pin & Location Assignments +# ========================== + +# Fitter Assignments +# ================== + +# end ENTITY(Phoenix_mist) +# ---------------------- +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_palette_ic41.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_palette_ic40.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic40.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic39.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic24.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_ic23.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/pll27.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_video.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_prog.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_music.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_mist.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_effect3.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_effect2.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix_effect1.vhd +set_global_assignment -name VHDL_FILE rtl/phoenix.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.sdc b/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.sdc new file mode 100644 index 00000000..3eba3b05 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/phoenix_mist.sdc @@ -0,0 +1,33 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# +#************************************************************ + +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] +create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic23.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic23.vhd new file mode 100644 index 00000000..230b2a85 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic23.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_ic23 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_ic23 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00", + X"00",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"20",X"00",X"00", + X"00",X"00",X"40",X"00",X"00",X"04",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"40",X"00",X"00", + X"00",X"00",X"20",X"00",X"0C",X"0C",X"00",X"00",X"00",X"20",X"70",X"20",X"00",X"00",X"00",X"00", + X"00",X"00",X"08",X"08",X"3E",X"08",X"08",X"00",X"10",X"10",X"10",X"FE",X"10",X"10",X"10",X"00", + X"00",X"44",X"00",X"00",X"20",X"00",X"02",X"00",X"10",X"00",X"40",X"08",X"02",X"80",X"04",X"00", + X"01",X"40",X"04",X"10",X"82",X"04",X"50",X"02",X"82",X"48",X"02",X"A0",X"08",X"45",X"20",X"02", + X"3C",X"7E",X"DF",X"AF",X"D7",X"AF",X"56",X"3C",X"3C",X"42",X"99",X"BD",X"BD",X"99",X"42",X"3C", + X"88",X"20",X"04",X"90",X"2A",X"56",X"0F",X"03",X"24",X"18",X"65",X"9A",X"1D",X"A0",X"56",X"28", + X"3C",X"5A",X"AB",X"AD",X"D5",X"D3",X"6A",X"3C",X"38",X"68",X"DC",X"FA",X"2E",X"3F",X"16",X"0C", + X"01",X"2A",X"54",X"2A",X"54",X"2A",X"54",X"80",X"3C",X"46",X"F9",X"8F",X"F3",X"9D",X"62",X"3C", + X"08",X"08",X"1C",X"7F",X"1C",X"08",X"08",X"00",X"1C",X"3A",X"6D",X"75",X"77",X"36",X"1C",X"00", + X"00",X"18",X"3C",X"7E",X"7E",X"3C",X"18",X"00",X"38",X"50",X"E8",X"F8",X"F0",X"D8",X"60",X"38", + X"08",X"2A",X"1C",X"7F",X"1C",X"2A",X"08",X"00",X"38",X"4C",X"9D",X"BD",X"BD",X"B9",X"32",X"1C", + X"62",X"91",X"09",X"3A",X"5C",X"90",X"89",X"46",X"3C",X"5E",X"EB",X"FF",X"DF",X"F7",X"7E",X"3C", + X"FE",X"FC",X"F8",X"C0",X"80",X"10",X"60",X"80",X"F0",X"1C",X"06",X"83",X"C3",X"E3",X"F7",X"FE", + X"FF",X"FF",X"BB",X"EE",X"EE",X"BC",X"F8",X"E0",X"E0",X"F8",X"FC",X"F6",X"BE",X"FF",X"6F",X"6B", + X"40",X"10",X"80",X"C0",X"00",X"00",X"00",X"00",X"21",X"88",X"22",X"10",X"84",X"21",X"88",X"54", + X"E5",X"D0",X"85",X"20",X"94",X"40",X"01",X"A0",X"40",X"10",X"44",X"90",X"02",X"A8",X"C5",X"E8", + X"C0",X"E8",X"60",X"14",X"48",X"04",X"2A",X"01",X"00",X"00",X"80",X"28",X"40",X"10",X"C0",X"D0", + X"FC",X"FC",X"F8",X"FC",X"F2",X"D9",X"0F",X"07",X"00",X"00",X"C0",X"C0",X"98",X"38",X"7C",X"FC", + X"BB",X"D6",X"77",X"E6",X"8E",X"3C",X"F8",X"E0",X"E0",X"F8",X"3C",X"8E",X"66",X"F7",X"F6",X"EB", + X"F8",X"F8",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"03",X"05",X"0A",X"D4",X"E8",X"D0",X"B8",X"78", + X"7F",X"EF",X"C7",X"C3",X"41",X"60",X"30",X"0F",X"01",X"06",X"08",X"01",X"03",X"1F",X"3F",X"7F", + X"E7",X"E4",X"FC",X"7F",X"77",X"37",X"1E",X"07",X"07",X"1F",X"3D",X"7E",X"5E",X"FB",X"BE",X"BE", + X"19",X"16",X"28",X"76",X"7B",X"FC",X"F8",X"E0",X"00",X"00",X"00",X"00",X"02",X"02",X"0C",X"0A", + X"27",X"93",X"29",X"44",X"12",X"24",X"09",X"02",X"05",X"10",X"01",X"44",X"12",X"89",X"23",X"97", + X"03",X"0B",X"10",X"05",X"12",X"00",X"00",X"00",X"80",X"48",X"20",X"15",X"28",X"06",X"27",X"13", + X"39",X"33",X"07",X"0F",X"0F",X"03",X"00",X"00",X"E0",X"D0",X"CB",X"6F",X"3F",X"1F",X"3E",X"3C", + X"DF",X"CB",X"ED",X"67",X"71",X"3C",X"1F",X"07",X"07",X"1F",X"3C",X"71",X"67",X"ED",X"CF",X"DA", + X"1E",X"1D",X"0B",X"17",X"2B",X"50",X"A0",X"C0",X"00",X"00",X"00",X"03",X"07",X"0F",X"1F",X"1F", + X"20",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"77",X"22",X"77",X"22",X"77", + X"77",X"22",X"77",X"22",X"F7",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"20", + X"F0",X"07",X"FF",X"77",X"27",X"72",X"27",X"70",X"70",X"27",X"72",X"27",X"77",X"FF",X"07",X"F0", + X"0F",X"E0",X"FF",X"77",X"27",X"77",X"20",X"70",X"70",X"20",X"77",X"27",X"77",X"FF",X"E0",X"0F", + X"00",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"00",X"E0",X"F0",X"F0",X"FF",X"FF",X"FF",X"FF", + X"F0",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"E7",X"E7",X"81",X"81",X"E7",X"E7",X"FF", + X"01",X"03",X"01",X"01",X"07",X"03",X"01",X"03",X"1F",X"03",X"1F",X"0F",X"07",X"1F",X"03",X"0F", + X"7F",X"0F",X"7F",X"3F",X"0F",X"7F",X"1F",X"3F",X"FF",X"3F",X"7F",X"FF",X"3F",X"FF",X"3F",X"7F", + X"C4",X"CE",X"C4",X"CE",X"C0",X"C0",X"C0",X"C0",X"00",X"FF",X"FF",X"CE",X"C4",X"CE",X"C4",X"CE", + X"CE",X"C4",X"CE",X"C4",X"CE",X"FF",X"FF",X"00",X"C0",X"C0",X"C0",X"C0",X"CE",X"C4",X"CE",X"C4", + X"F0",X"07",X"FF",X"CE",X"C4",X"CE",X"C4",X"CE",X"0E",X"04",X"0E",X"04",X"0E",X"FF",X"07",X"F0", + X"0F",X"E0",X"FF",X"CE",X"C4",X"CE",X"C4",X"CE",X"CE",X"C4",X"CE",X"C4",X"CE",X"FF",X"E0",X"0F", + X"F0",X"F0",X"F0",X"F0",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"F0",X"F0",X"E0",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"F0",X"FF",X"E7",X"E7",X"FF",X"FF",X"E7",X"E7",X"FF", + X"FF",X"FF",X"7E",X"3C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"7E",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"C3",X"C3",X"FF",X"FF",X"C3",X"C3",X"FF",X"00",X"00",X"00",X"00",X"FF",X"C3",X"C3",X"FF", + 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if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic24.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic24.vhd new file mode 100644 index 00000000..f420697f --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic24.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_ic24 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_ic24 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_ic39 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7C",X"12",X"12",X"12",X"7E",X"7C",X"00", + X"00",X"34",X"4A",X"4A",X"4A",X"7E",X"7E",X"00",X"00",X"24",X"42",X"42",X"42",X"7E",X"3C",X"00", + X"00",X"3C",X"42",X"42",X"42",X"7E",X"7E",X"00",X"00",X"42",X"4A",X"4A",X"4A",X"7E",X"7E",X"00", + X"00",X"02",X"0A",X"0A",X"0A",X"7E",X"7E",X"00",X"00",X"34",X"52",X"52",X"42",X"7E",X"3C",X"00", + X"00",X"7E",X"08",X"08",X"08",X"7E",X"7E",X"00",X"00",X"42",X"42",X"7E",X"7E",X"42",X"42",X"00", + X"00",X"7E",X"7E",X"7E",X"40",X"40",X"30",X"00",X"00",X"42",X"24",X"18",X"08",X"7E",X"7E",X"00", + X"00",X"40",X"40",X"40",X"40",X"7E",X"7E",X"00",X"00",X"7E",X"02",X"7C",X"02",X"7E",X"7E",X"00", + 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X"1F",X"E0",X"0F",X"7F",X"F0",X"80",X"00",X"00",X"F8",X"07",X"F0",X"FE",X"0F",X"01",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic40.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic40.vhd new file mode 100644 index 00000000..ab29736f --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic40.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_ic40 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_ic40 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"0C",X"1C",X"18",X"18",X"38",X"30",X"30",X"30",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0E", + X"30",X"38",X"1C",X"0E",X"07",X"03",X"00",X"00",X"C0",X"C0",X"C0",X"C0",X"E0",X"60",X"60",X"70", + X"70",X"60",X"60",X"E0",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"03",X"07",X"0E",X"1C",X"38",X"30", + X"00",X"00",X"03",X"1F",X"FE",X"F0",X"00",X"00",X"00",X"00",X"C0",X"F8",X"7F",X"0F",X"00",X"00", + X"00",X"00",X"0F",X"7F",X"F8",X"C0",X"00",X"00",X"00",X"00",X"F0",X"FE",X"1F",X"03",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"0F",X"FF",X"F8",X"00",X"00",X"00",X"00",X"80",X"F0",X"7F",X"1F", + X"1F",X"FF",X"F0",X"80",X"00",X"00",X"00",X"00",X"F8",X"FF",X"0F",X"01",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic40.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic40.vhd new file mode 100644 index 00000000..422d60cc --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic40.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_palette_ic40 is +port ( + clk : in std_logic; + addr : in std_logic_vector(6 downto 0); + data : out std_logic_vector(2 downto 0) +); +end entity; + +architecture prom of prom_palette_ic40 is + type rom is array(0 to 127) of std_logic_vector(2 downto 0); + signal rom_data: rom := ( + "000","000","000","000","000","000","000","000","010","010","100","010","101","010","010","010", + "000","001","010","000","010","001","001","001","000","001","001","001","110","100","100","100", + "000","000","000","000","000","000","000","000","100","001","001","011","011","011","001","000", + "010","101","101","001","001","001","111","000","110","111","111","101","101","101","011","111", + "000","000","000","000","000","000","000","000","010","010","100","010","001","001","001","001", + "000","001","010","000","010","010","010","010","000","001","001","001","100","100","100","100", + "000","000","000","000","000","000","000","000","100","001","001","100","100","100","011","100", + "010","101","101","101","101","101","111","000","101","111","111","011","011","011","101","111"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic41.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic41.vhd new file mode 100644 index 00000000..5dcb18d9 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic41.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_palette_ic41 is +port ( + clk : in std_logic; + addr : in std_logic_vector(6 downto 0); + data : out std_logic_vector(2 downto 0) +); +end entity; + +architecture prom of prom_palette_ic41 is + type rom is array(0 to 127) of std_logic_vector(2 downto 0); + signal rom_data: rom := ( + "000","000","000","000","000","000","000","000","010","110","101","011","101","110","110","110", + "001","011","011","110","010","011","011","011","111","101","101","011","111","101","101","101", + "000","000","000","000","000","000","000","000","110","001","001","011","011","011","001","100", + "110","101","101","111","111","111","111","011","110","111","111","101","101","101","011","111", + "000","000","000","000","000","000","000","000","010","010","101","011","011","011","011","011", + "001","011","011","110","110","110","110","110","101","101","101","011","101","101","101","101", + "000","000","000","000","000","000","000","000","110","001","001","100","100","100","011","100", + "110","101","101","101","101","101","111","011","101","111","111","111","111","111","101","111"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T8080se.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T8080se.vhd new file mode 100644 index 00000000..3fbf4ebd --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T8080se.vhd @@ -0,0 +1,185 @@ +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_ALU.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_MCode.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_Pack.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_Reg.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/dac.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/dac.vhd new file mode 100644 index 00000000..9685a6cc --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 12 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/gen_ram.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/gen_ram.vhd new file mode 100644 index 00000000..0794fdc0 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/gen_ram.vhd @@ -0,0 +1,82 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- + q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; + qReg <= ram(to_integer(unsigned(addr))); + end if; + end process; +end architecture; + diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/hq2x.sv b/Arcade/Custom Hardware/Phoenix_MIST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/keyboard.v b/Arcade/Custom Hardware/Phoenix_MIST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/mist_io.v b/Arcade/Custom Hardware/Phoenix_MIST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/osd.v b/Arcade/Custom Hardware/Phoenix_MIST/rtl/osd.v new file mode 100644 index 00000000..7f712178 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/osd.v @@ -0,0 +1,180 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out, + + output reg osd_enabled +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enabled <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix.vhd new file mode 100644 index 00000000..9fc4d8ea --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix.vhd @@ -0,0 +1,458 @@ +--------------------------------------------------------------------------------- +-- DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + +entity phoenix is +generic ( + C_test_picture: boolean := false; + C_tile_rom: boolean := true; -- false: disable tile ROM to try game logic on small FPGA + -- reduce ROMs: 14 is normal game, 13 will draw initial screen, 12 will repeatedly blink 1 line of garbage + C_autofire: boolean := true; + -- C_audio: boolean := true; + C_prog_rom_addr_bits: integer range 12 to 14 := 14 +); +port( + clk : in std_logic; -- 11 MHz for TV, 25 MHz for VGA + reset : in std_logic; + ce_pix : out std_logic; + + dip_switch : in std_logic_vector(7 downto 0); + -- game controls, normal logic '1':pressed, '0':released + + btn_coin: in std_logic; + btn_player_start: in std_logic_vector(1 downto 0); + btn_fire, btn_left, btn_right, btn_barrier: in std_logic; + + video_r : out std_logic_vector(1 downto 0); + video_g : out std_logic_vector(1 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_vblank, video_hblank_bg, video_hblank_fg: out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + + sound_fire : out std_logic; -- '1' when missile fires + sound_explode: out std_logic; -- '1' when ship explodes + sound_burn : out std_logic; -- bird burns + sound_fireball: out std_logic; -- bird explodes in 2 fireballs + sound_ab : out std_logic_vector(15 downto 0); + audio_select : in std_logic_vector(2 downto 0) := (others => '0'); + audio : out std_logic_vector(11 downto 0) +); +end phoenix; + +architecture struct of phoenix is + + signal reset_n: std_logic; + + signal hcnt : std_logic_vector(9 downto 1); + signal vcnt : std_logic_vector(8 downto 1); + signal sync : std_logic; + signal adrsel : std_logic; + signal rdy : std_logic := '1'; + signal vblank : std_logic; + signal hblank_bkgrd : std_logic; + signal hblank_frgrd : std_logic; + signal ce_pix1 : std_logic; + + signal cpu_adr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal prog_do : std_logic_vector( 7 downto 0); + signal S_prog_rom_addr : std_logic_vector(13 downto 0); + + signal frgnd_horz_cnt : std_logic_vector(7 downto 0) := (others =>'0'); + signal bkgnd_horz_cnt : std_logic_vector(7 downto 0) := (others =>'0'); + signal vert_cnt : std_logic_vector(7 downto 0) := (others =>'0'); + + signal frgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0'); + signal bkgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0'); + signal frgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0'); + signal bkgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0'); + signal frgnd_ram_we : std_logic := '0'; + signal bkgnd_ram_we : std_logic := '0'; + + signal frgnd_graph_adr : std_logic_vector(10 downto 0) := (others =>'0'); + signal bkgnd_graph_adr : std_logic_vector(10 downto 0) := (others =>'0'); + signal palette_adr : std_logic_vector( 7 downto 0) := (others =>'0'); + + signal frgnd_clk : std_logic; + signal bkgnd_clk : std_logic; + + signal frgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0'); + signal bkgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0'); + + signal frgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0'); + signal frgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0'); + signal bkgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0'); + signal bkgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0'); + + signal frgnd_bit0_graph_r : std_logic_vector(7 downto 0) := (others =>'0'); + signal frgnd_bit1_graph_r : std_logic_vector(7 downto 0) := (others =>'0'); + signal bkgnd_bit0_graph_r : std_logic_vector(7 downto 0) := (others =>'0'); + signal bkgnd_bit1_graph_r : std_logic_vector(7 downto 0) := (others =>'0'); + + signal fr_bit0 : std_logic; + signal fr_bit1 : std_logic; + signal bk_bit0 : std_logic; + signal bk_bit1 : std_logic; + signal fr_lin : std_logic_vector(2 downto 0); + signal bk_lin : std_logic_vector(2 downto 0); + + signal color_set : std_logic; + signal color_id : std_logic_vector(5 downto 0); + signal rgb_0 : std_logic_vector(2 downto 0); + signal rgb_1 : std_logic_vector(2 downto 0); + + signal player2 : std_logic := '0'; + signal pl2_cocktail : std_logic := '0'; + signal bkgnd_offset : std_logic_vector(7 downto 0) := (others =>'0'); + signal sound_a : std_logic_vector(7 downto 0) := (others =>'0'); + signal sound_b : std_logic_vector(7 downto 0) := (others =>'0'); + + signal clk10 : std_logic; + signal snd1 : std_logic_vector( 7 downto 0) := (others =>'0'); + signal snd2 : std_logic_vector( 1 downto 0) := (others =>'0'); + signal snd3 : std_logic_vector( 7 downto 0) := (others =>'0'); + signal song : std_logic_vector( 7 downto 0) := (others =>'0'); + signal mixed : std_logic_vector(11 downto 0) := (others =>'0'); + signal sound_string : std_logic_vector(31 downto 0); + + signal coin : std_logic; + signal player_start : std_logic_vector(1 downto 0); + signal buttons : std_logic_vector(3 downto 0); + signal R_autofire : std_logic_vector(21 downto 0); +begin + +-- game core uses inverted control logic +coin <= not btn_coin; -- insert coin +player_start <= not btn_player_start; -- select 1 or 2 players +buttons(1) <= not btn_right; -- Right +buttons(2) <= not btn_left; -- Left +buttons(3) <= not btn_barrier; -- Protection + +G_not_autofire: if not C_autofire generate + buttons(0) <= not btn_fire; -- Fire +end generate; + +G_yes_autofire: if C_autofire generate + process(clk) + begin + if rising_edge(clk) then + if btn_fire='1' then + R_autofire <= R_autofire-1; + else + R_autofire <= (others => '0'); + end if; + end if; + end process; + buttons(0) <= not R_autofire(R_autofire'high); +end generate; + + video: entity work.phoenix_video + port map + ( + clk11 => clk, + ce_pix => ce_pix1, + hcnt => hcnt, + vcnt => vcnt, + sync_hs => video_hs, + sync_vs => video_vs, + adrsel => adrsel, -- RAM address selector ('0')cpu / ('1')video_generator + rdy => rdy, -- Ready ('1')cpu can access RAMs read/write + vblank => vblank, + hblank_frgrd => hblank_frgrd, + hblank_bkgrd => hblank_bkgrd, + reset => reset + ); + reset_n <= not reset; + ce_pix <= ce_pix1; + +-- microprocessor 8085 +cpu8085 : entity work.T8080se +generic map +( + Mode => 2, + T2Write => 0 +) +port map( + RESET_n => reset_n, + CLK => clk, + CLKEN => '1', -- fixme: use it to make 5.5 MHz clock average + READY => rdy, + HOLD => '1', + INT => '1', + INTE => open, + DBIN => open, + SYNC => open, + VAIT => open, + HLDA => open, + WR_n => cpu_wr_n, + A => cpu_adr, + DI => cpu_di, + DO => cpu_do +); + +-- mux prog, ram, vblank, switch... to processor data bus in +cpu_di <= prog_do when cpu_adr(14) = '0' else + frgnd_ram_do when cpu_adr(13 downto 10) = 2#00_00# else + bkgnd_ram_do when cpu_adr(13 downto 10) = 2#00_10# else + buttons & '0' & player_start & coin when cpu_adr(13 downto 10) = 2#11_00# else--buttons & '1' + not vblank & dip_switch(6 downto 0) when cpu_adr(13 downto 10) = 2#11_10# else + prog_do; + +-- write enable to RAMs from cpu +frgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(14 downto 10) = "10000" and adrsel = '0' else '0'; +bkgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(14 downto 10) = "10010" and adrsel = '0' else '0'; + +-- RAMs address mux cpu/video_generator, bank0 for player1, bank1 for player2 +frgnd_ram_adr <= player2 & cpu_adr(9 downto 0) when adrsel ='0' else player2 & vert_cnt(7 downto 3) & frgnd_horz_cnt(7 downto 3); +bkgnd_ram_adr <= player2 & cpu_adr(9 downto 0) when adrsel ='0' else player2 & vert_cnt(7 downto 3) & bkgnd_horz_cnt(7 downto 3); + +-- demux cpu data to registers : background scrolling, sound control, +-- player id (1/2), palette color set. +process (clk) +begin + if rising_edge(clk) then + if cpu_wr_n = '0' then + case cpu_adr(14 downto 10) is + when "10110" => bkgnd_offset <= cpu_do; + when "11000" => sound_b <= cpu_do; + when "11010" => sound_a <= cpu_do; + when "10100" => player2 <= cpu_do(0); + color_set <= cpu_do(1); + when others => null; + end case; + end if; + end if; +end process; + +-- player2 and cocktail mode (flip horizontal/vertical) +pl2_cocktail <= player2 and dip_switch(7); + +-- horizontal scan video RAMs address background and foreground +-- with flip and scroll offset +frgnd_horz_cnt <= hcnt(8 downto 1) when pl2_cocktail = '0' else not hcnt(8 downto 1); +bkgnd_horz_cnt <= frgnd_horz_cnt + bkgnd_offset; + +-- vertical scan video RAMs address +vert_cnt <= vcnt(8 downto 1) when pl2_cocktail = '0' else not (vcnt(8 downto 1) + X"30"); + +-- get tile_ids from RAMs +frgnd_tile_id <= frgnd_ram_do; +bkgnd_tile_id <= bkgnd_ram_do; + +-- address graphix ROMs with tile_ids and line counter +frgnd_graph_adr <= frgnd_tile_id & vert_cnt(2 downto 0); +bkgnd_graph_adr <= bkgnd_tile_id & vert_cnt(2 downto 0); + +-- latch foreground/background next graphix byte, high bit and low bit +-- and palette_ids (fr_lin, bklin) +process (clk) +begin + if rising_edge(clk) then + if (pl2_cocktail = '0' and (frgnd_horz_cnt(2 downto 0) = "111")) or + (pl2_cocktail = '1' and (frgnd_horz_cnt(2 downto 0) = "000")) then + frgnd_bit0_graph_r <= frgnd_bit0_graph; + frgnd_bit1_graph_r <= frgnd_bit1_graph; + fr_lin <= frgnd_tile_id(7 downto 5); + end if; + if (pl2_cocktail = '0' and (bkgnd_horz_cnt(2 downto 0) = "111")) or + (pl2_cocktail = '1' and (bkgnd_horz_cnt(2 downto 0) = "000")) then + bkgnd_bit0_graph_r <= bkgnd_bit0_graph; + bkgnd_bit1_graph_r <= bkgnd_bit1_graph; + bk_lin <= bkgnd_tile_id(7 downto 5); + end if; + end if; +end process; + +-- demux background and foreground pixel bits (0/1) from graphix byte with horizontal counter +-- and apply horizontal and vertical blanking +fr_bit0 <= frgnd_bit0_graph_r(to_integer(unsigned(frgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_frgrd)= '0' else '0'; +fr_bit1 <= frgnd_bit1_graph_r(to_integer(unsigned(frgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_frgrd)= '0' else '0'; +bk_bit0 <= bkgnd_bit0_graph_r(to_integer(unsigned(bkgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_bkgrd)= '0' else '0'; +bk_bit1 <= bkgnd_bit1_graph_r(to_integer(unsigned(bkgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_bkgrd)= '0' else '0'; + +-- select pixel bits and palette_id with foreground priority +color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 or fr_bit1) = '1' else + (fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin; + +-- address palette with pixel bits color and color set +palette_adr <= '0' & color_set & color_id; + +-- output video to top level +video_vblank <= vblank; +video_hblank_fg <= hblank_frgrd; +video_hblank_bg <= hblank_bkgrd; +video_r <= rgb_1(0) & rgb_0(0) when (hcnt>=192) else "00"; +video_g <= rgb_1(2) & rgb_0(2) when (hcnt>=192) else "00"; +video_b <= rgb_1(1) & rgb_0(1) when (hcnt>=192) else "00"; + +G_yes_tile_rom: if C_tile_rom generate +-- foreground graphix ROM bit0 +frgnd_bit0 : entity work.prom_ic39 +port map( + clk => clk, + addr => frgnd_graph_adr, + data => frgnd_bit0_graph +); + +-- foreground graphix ROM bit1 +frgnd_bit1 : entity work.prom_ic40 +port map( + clk => clk, + addr => frgnd_graph_adr, + data => frgnd_bit1_graph +); + +-- background graphix ROM bit0 +bkgnd_bit0 : entity work.prom_ic23 +port map( + clk => clk, + addr => bkgnd_graph_adr, + data => bkgnd_bit0_graph +); + +-- background graphix ROM bit1 +bkgnd_bit1 : entity work.prom_ic24 +port map( + clk => clk, + addr => bkgnd_graph_adr, + data => bkgnd_bit1_graph +); + +-- color palette ROM RBG low intensity +palette_0 : entity work.prom_palette_ic40 +port map( + clk => clk, + addr => palette_adr(6 downto 0), + data => rgb_0 +); + +-- color palette ROM RBG high intensity +palette_1 : entity work.prom_palette_ic41 +port map( + clk => clk, + addr => palette_adr(6 downto 0), + data => rgb_1 +); +end generate; + +G_no_tile_rom: if not C_tile_rom generate + -- dummy replacement for missing tile ROMs + frgnd_bit0_graph <= frgnd_graph_adr(10 downto 3); + frgnd_bit1_graph <= "00000000"; + bkgnd_bit0_graph <= bkgnd_graph_adr(10 downto 3); + bkgnd_bit1_graph <= "00000000"; + rgb_0 <= palette_adr(2 downto 0); + rgb_1 <= palette_adr(2 downto 0); +end generate; + +-- Program PROM +S_prog_rom_addr(C_prog_rom_addr_bits-1 downto 0) <= cpu_adr(C_prog_rom_addr_bits-1 downto 0); +prog : entity work.phoenix_prog +port map( + clk => clk, + addr => S_prog_rom_addr, + data => prog_do +); + +-- foreground RAM 0x4000-0x433F +-- cpu working area 0x4340-0x43FF +frgnd_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clk, + we => frgnd_ram_we, + addr => frgnd_ram_adr, + d => cpu_do, + q => frgnd_ram_do +); + +-- background RAM 0x4800-0x4B3F +-- cpu working area 0x4B40-0x4BFF +-- stack pointer downward from 0x4BFF +bkgnd_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clk, + we => bkgnd_ram_we, + addr => bkgnd_ram_adr, + d => cpu_do, + q => bkgnd_ram_do +); + + +effect1: entity work.phoenix_effect1 +port map +( + clk => clk, + reset => '0', + trigger => sound_a(4), + filter => sound_a(5), + divider => sound_a(3 downto 0), + snd => snd1 +); + +effect2 : entity work.phoenix_effect2 +port map +( + clk => clk, + reset => '0', + trigger1 => sound_b(4), + trigger2 => sound_b(5), + divider => sound_b(3 downto 0), + snd => snd2 +); + +effect3 : entity work.phoenix_effect3 +port map +( + clk => clk, + reset => '0', + trigger1 => sound_b(6), + trigger2 => sound_b(7), + snd => snd3 +); + +sound_burn <= sound_b(4); +sound_fire <= sound_b(6); -- '1' when fire sound +sound_explode <= sound_b(7); -- '1' when explode sound +sound_fireball <= sound_a(1) and not sound_a(0); -- ambiguity: mothership descend also triggers this +sound_ab <= sound_b & sound_a; + +music: entity work.phoenix_music +port map +( + clk => clk, + reset => '0', + trigger => sound_a(7), + sel_song => sound_a(6), + snd => song +); + +-- mix effects and music +mixed <= std_logic_vector + ( + unsigned("00" & snd1 & "00") + + unsigned("0" & snd2 & "000000000") + + unsigned("00" & snd3 & "00") + + unsigned("00" & song & "00" ) + ); + +-- select sound or/and effect +with audio_select select +audio <= "00" & snd1 & "00" when "100", + "0" & snd2 & "000000000" when "101", + "00" & snd3 & "00" when "110", + "00" & song & "00" when "111", + mixed when others; + + +end struct; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect1.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect1.vhd new file mode 100644 index 00000000..43c9433b --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect1.vhd @@ -0,0 +1,230 @@ +--------------------------------------------------------------------------------- +-- Phoenix sound effect1 by Dar (darfpga@aol.fr) (April 2016) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +-- this module generates sound how the birds fly +-- how they burn and the ship's barrier activation sound +-- it is most often heard module througut all levels of the game + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity phoenix_effect1 is +generic( + -- Command + Cmd_Fs: real := 11.0; -- MHz + Cmd_V: real := 12.0; -- V + Cmd_Vd: real := 0.46; -- V + Cmd_Vce: real := 0.2; -- V + Cmd_R1: real := 100.0; -- k + Cmd_R2: real := 33.0; -- k + Cmd_R3: real := 0.47; -- k + Cmd_C: real := 6.8; -- uF + Cmd_Div2n: integer := 8; -- bits divisor + Cmd_bits: integer := 16; -- bits counter + -- Oscillator + Osc_Fs: real := 11.0; -- MHz + Osc_Vb: real := 5.0; -- V + Osc_Vce: real := 0.2; -- V + Osc_R1: real := 47.0; -- k + Osc_R2: real := 47.0; -- k + Osc_C: real := 0.001; -- uF + Osc_Div2n: integer := 7; -- bits divisor + Osc_bits: integer := 6; -- bits counter + -- Filter + Filt_Fs: real := 11.0; -- MHz + Filt_V1: real := 5.0; -- V + Filt_V2: real := 0.0; -- V + Filt_R1: real := 100.0; -- k + Filt_R2: real := 10.0; -- k + Filt_C: real := 0.047; -- uF + Filt_Div2n: integer := 7; -- bits divisor + Filt_bits: integer := 8; -- bits counter + + Vmax: real := 5.0; -- V + Vmax_bits: integer := 16 -- number of bits to represent vmax +); +port( + clk : in std_logic; + reset : in std_logic; + trigger : in std_logic; + filter : in std_logic; + divider : in std_logic_vector(3 downto 0); + snd : out std_logic_vector(7 downto 0) +); +end phoenix_effect1; + +architecture struct of phoenix_effect1 is + +-- integer representation of voltage, full range +constant IVmax: integer := integer(2**Vmax_bits)-1; +-- command -- +constant Cmd_div: integer := integer(2**Cmd_Div2n); +-- command charge +constant Cmd_VFc: real := (Cmd_V*Cmd_R2 + Cmd_Vd*Cmd_R1)/(Cmd_R1 + Cmd_R2); -- V +constant Cmd_RCc: real := Cmd_R1*Cmd_R2/(Cmd_R1 + Cmd_R2)*Cmd_C/1000.0; -- s +constant Cmd_ikc: integer := integer(Cmd_Fs * 1.0E6 * Cmd_RCc / 2.0**Cmd_Div2n); +constant Cmd_iVFc: integer := integer(Cmd_VFc * real(IVmax)/Vmax); +-- command discharge +constant Cmd_VFd: real := (Cmd_V/Cmd_R1+Cmd_Vd/Cmd_R2+(Cmd_Vd+Cmd_Vce)/Cmd_R3)/(1.0/Cmd_R1+1.0/Cmd_R2+1.0/Cmd_R3); -- V +constant Cmd_RCd: real := 1.0/(1.0/Cmd_R1+1.0/Cmd_R2+1.0/Cmd_R3)*Cmd_C/1000.0; -- s +constant Cmd_ikd: integer := integer(Cmd_Fs * 1.0E6 * Cmd_RCd / 2.0**Cmd_Div2n); +constant Cmd_iVFd: integer := integer(Cmd_VFd * real(IVmax)/Vmax); + +-- oscillator +constant Osc_div: integer := integer(2**Osc_Div2n); +-- oscillator charge +constant Osc_VFc: real := Osc_Vb; -- V +constant Osc_RCc: real := (Osc_R1+Osc_R2)*Osc_C/1000.0; -- s +constant Osc_ikc: integer := integer(Osc_Fs * 1.0E6 * Osc_RCc / 2.0**Osc_Div2n); +constant Osc_iVFc: integer := integer(Osc_VFc * real(IVmax)/Vmax); +-- oscillator discharge +constant Osc_VFd: real := Osc_Vce; -- V +constant Osc_RCd: real := Osc_R2*Osc_C/1000.0; -- s +constant Osc_ikd: integer := integer(Osc_Fs * 1.0E6 * Osc_RCd / 2.0**Osc_Div2n); +constant Osc_iVFd: integer := integer(Osc_VFd * real(IVmax)/Vmax); + +-- filter +constant Filt_div: integer := integer(2**Filt_Div2n); +-- filter charge +constant Filt_VFc: real := Filt_V1; -- V +constant Filt_RCc: real := 1.0/(1.0/Filt_R1+1.0/Filt_R2)*Filt_C/1000.0; -- s +constant Filt_ikc: integer := integer(Filt_Fs * 1.0E6 * Filt_RCc / 2.0**Filt_Div2n); +constant Filt_iVFc: integer := integer(Filt_VFc * real(IVmax)/Vmax); +-- filter discharge +constant Filt_VFd: real := Filt_V2; -- V +constant Filt_RCd: real := Filt_RCc; -- s +constant Filt_ikd: integer := integer(Filt_Fs * 1.0E6 * Filt_RCd / 2.0**Filt_Div2n); +constant Filt_iVFd: integer := integer(Filt_VFd * real(IVmax)/Vmax); + +function imax(x,y: integer) return integer is begin + if x > y then + return x; + else + return y; + end if; +end imax; + +signal u_c1 : unsigned(15 downto 0) := (others => '0'); +signal u_c2 : unsigned(15 downto 0) := (others => '0'); +signal flip : std_logic := '0'; + +signal u_cf : unsigned(15 downto 0) := (others => '0'); +signal sound : std_logic := '0'; + +begin + +-- Commande +-- R1 = 100k, R2 = 33k, R3 = 0.47k C=6.8e-6 SR=10MHz +-- Charge : VF1 = 43559, k1 = 6591 (R1//R2) +-- Decharge : VF2 = 9300, k2 = 123 (R1//R2//R3) +-- Div = 2^8 + +process (clk) + variable cnt: integer range 0 to imax(Cmd_ikc,Cmd_ikd) := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c1 <= (others => '0'); + else + cnt := cnt + 1; + if trigger = '1' then + if cnt = Cmd_ikc then + cnt := 0; + u_c1 <= u_c1 + (Cmd_iVFc - u_c1)/Cmd_div; + end if; + else + if cnt = Cmd_ikd then + cnt := 0; + u_c1 <= u_c1 - (u_c1 - Cmd_iVFd)/Cmd_div; + end if; + end if; + end if; + end if; +end process; + +-- Oscillateur +-- R1 = 47k, R2 = 47k, C=0.001e-6 SR=50MHz +-- Charge : VF1 = 65535, k1 = 37 (R1+R2) +-- Decharge : VF2 = 2621, k2 = 18 (R2) +-- Div = 2^7 + +-- Diviseur +-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF) +-- LS74 : Divide by 2 + +process (clk) + variable cnt: integer range 0 to imax(Osc_ikc,Osc_ikd) := 0; + variable cnt2: unsigned(3 downto 0) := (others => '0'); +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c2 <= (others => '0'); + flip <= '0'; + else + if u_c2 > u_c1 then flip <= '0'; end if; + if u_c2 < u_c1/2 then + flip <= '1'; + if flip = '0' then + cnt2 := cnt2 + 1; + if cnt2 = "0000" then + cnt2 := unsigned(divider); + if divider /= "1111" then sound <= not sound; end if; + end if; + end if; + end if; + cnt := cnt + 1; + if flip = '1' then + if cnt = Osc_ikc then + cnt := 0; + u_c2 <= u_c2 + (Osc_iVFc - u_c2)/Osc_div; + end if; + else + if cnt = Osc_ikd then + cnt := 0; + u_c2 <= u_c2 - (u_c2 - Osc_iVFd)/Osc_div; + end if; + end if; + end if; + end if; +end process; + +-- filter +-- R1 = 10k, R2 = 100k, C=0.047e-6, SR=10MHz +-- Charge : VF1= 65535, k1 = 33 (R1//R2) +-- Decharge : VF2= 0 , k2 = 33 (R1//R2) +-- Div = 2^7 + +process (clk) + variable cnt: integer range 0 to imax(Filt_ikc,Filt_ikd) := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_cf <= (others => '0'); + else + cnt := cnt + 1; + if sound = '1' then + if cnt = Filt_ikc then + cnt := 0; + u_cf <= u_cf + (Filt_iVFc - u_cf)/Filt_div; + end if; + else + if cnt = Filt_ikd then + cnt := 0; + u_cf <= u_cf - (u_cf - Filt_iVFd)/Filt_div; + end if; + end if; + end if; + end if; +end process; + +with filter select snd <= std_logic_vector(u_cf(15 downto 8)) when '1', sound&"0000000" when others; + +end struct; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect2.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect2.vhd new file mode 100644 index 00000000..097f4aa9 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect2.vhd @@ -0,0 +1,387 @@ +--------------------------------------------------------------------------------- +-- Phoenix sound effect2 by Dar (darfpga@aol.fr) (April 2016) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +-- this module outputs sound of mothership's descend +-- it could be heard at beginning of level 5 +-- the prrrrr...vioooouuuuu sound +-- fixme: +-- the VCO control levels are too coarse (quantized) +-- frequency transitions are heard in large steps +-- instead of continous sweep + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity phoenix_effect2 is +generic( + -- Oscillator 1 + Osc1_Fs: real := 11.0; -- MHz + Osc1_Vb: real := 5.0; -- V + Osc1_Vce: real := 0.2; -- V + Osc1_R1: real := 47.0; -- k + Osc1_R2: real := 100.0; -- k + Osc1_C1: real := 0.01; -- uF + Osc1_C2: real := 0.47; -- uF + Osc1_C3: real := 1.0; -- uF + Osc1_Div2n: integer := 8; -- bits divisor + Osc1_bits: integer := 16; -- bits counter + -- Oscillator 2 + Osc2_Fs: real := 11.0; -- MHz + Osc2_Vb: real := 5.0; -- V + Osc2_Vce: real := 0.2; -- V + Osc2_R1: real := 510.0; -- k + Osc2_R2: real := 510.0; -- k + Osc2_C: real := 1.0; -- uF + Osc2_Div2n: integer := 8; -- bits divisor + Osc2_bits: integer := 17; -- bits counter + -- Filter 2 + Filt2_Fs: real := 11.0; -- MHz + Filt2_V: real := 5.0; -- V + Filt2_R1: real := 10.0; -- k + Filt2_R2: real := 5.1; -- k + Filt2_R3: real := 5.1; -- k + Filt2_R4: real := 5.0; -- k + Filt2_R5: real := 10.0; -- k + Filt2_C: real := 100.0; -- uF + Filt2_Div2n: integer := 8; -- bits divisor + Filt2_bits: integer := 16; -- bits counter + -- Oscillator 3 + Osc3_Fs: real := 11.0; -- MHz + Osc3_Vb: real := 5.0; -- V + Osc3_Vce: real := 0.2; -- V + Osc3_R1: real := 20.0; -- k + Osc3_R2: real := 20.0; -- k + Osc3_C: real := 0.001; -- uF + Osc3_Div2n: integer := 6; -- bits divisor + Osc3_bits: integer := 6; -- bits counter + + C_flip1_0: integer := 22020; + C_flip1_1: integer := 33063; + C_flip1_scale: integer := 84; -- ?? + + + Vmax: real := 5.0; -- V + Vmax_bits: integer := 16 -- number of bits to represent Vmax +); + +port( + clk : in std_logic; + reset : in std_logic; + trigger1 : in std_logic; + trigger2 : in std_logic; + divider : in std_logic_vector(3 downto 0); + snd : out std_logic_vector(1 downto 0) +); +end phoenix_effect2; + +architecture struct of phoenix_effect2 is + +function imax(x,y: integer) return integer is begin + if x > y then + return x; + else + return y; + end if; +end imax; + +-- integer representation of voltage, full range +constant IVmax: integer := integer(2**Vmax_bits)-1; +-- Oscillator1 -- +constant Osc1_div: integer := integer(2**Osc1_Div2n); +-- Oscillator1 charge/discharge voltages +constant Osc1_VFc: real := Osc1_Vb; -- V +constant Osc1_iVFc: integer := integer(Osc1_VFc * real(IVmax)/Vmax); +constant Osc1_VFd: real := Osc1_Vce; -- V +constant Osc1_iVFd: integer := integer(Osc1_VFd * real(IVmax)/Vmax); +-- Oscillator1 charge/discharge time constants +constant Osc1_T0_RCc: real := (Osc1_R1+Osc1_R2)*Osc1_C1/1000.0; -- s +constant Osc1_T0_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T0_RCc / 2.0**Osc1_Div2n); +constant Osc1_T0_RCd: real := Osc1_R2*Osc1_C1/1000.0; -- s +constant Osc1_T0_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T0_RCd / 2.0**Osc1_Div2n); + +constant Osc1_T1_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C2)/1000.0; -- s +constant Osc1_T1_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T1_RCc / 2.0**Osc1_Div2n); +constant Osc1_T1_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C2)/1000.0; -- s +constant Osc1_T1_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T1_RCd / 2.0**Osc1_Div2n); + +constant Osc1_T2_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C3)/1000.0; -- s +constant Osc1_T2_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T2_RCc / 2.0**Osc1_Div2n); +constant Osc1_T2_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C3)/1000.0; -- s +constant Osc1_T2_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T2_RCd / 2.0**Osc1_Div2n); + +constant Osc1_T3_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C2+Osc1_C3)/1000.0; -- s +constant Osc1_T3_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T3_RCc / 2.0**Osc1_Div2n); +constant Osc1_T3_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C2+Osc1_C3)/1000.0; -- s +constant Osc1_T3_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T3_RCd / 2.0**Osc1_Div2n); + +constant Osc1_ik_max: integer := imax( imax(Osc1_T1_ikc,Osc1_T1_ikd), imax(Osc1_T3_ikc,Osc1_T3_ikd)); + +-- Oscillator2 -- +constant Osc2_div: integer := integer(2**Osc2_Div2n); +-- Oscillator2 charge/discharge voltages +constant Osc2_VFc: real := Osc2_Vb; -- V +constant Osc2_iVFc: integer := integer(Osc2_VFc * real(IVmax)/Vmax); +constant Osc2_VFd: real := Osc2_Vce; -- V +constant Osc2_iVFd: integer := integer(Osc2_VFd * real(IVmax)/Vmax); +-- Oscillator2 charge/discharge time constants +constant Osc2_RCc: real := (Osc2_R1+Osc2_R2)*Osc2_C/1000.0; -- s +constant Osc2_ikc: integer := integer(Osc2_Fs * 1.0E6 * Osc2_RCc / 2.0**Osc2_Div2n); +constant Osc2_RCd: real := Osc2_R2*Osc2_C/1000.0; -- s +constant Osc2_ikd: integer := integer(Osc2_Fs * 1.0E6 * Osc2_RCd / 2.0**Osc2_Div2n); + +-- Filter2 -- +constant Filt2_div: integer := integer(2**Filt2_Div2n); +constant Filt2_R4p: real := 1.0/(1.0/Filt2_R1+1.0/Filt2_R4); -- k +constant Filt2_R5p: real := 1.0/(1.0/Filt2_R1+1.0/Filt2_R5); -- k +constant Filt2_Rp: real := 1.0/(1.0/Filt2_R3+1.0/Filt2_R4+1.0/Filt2_R5p); -- k +constant Filt2_Rs: real := 1.0/(1.0/Filt2_R2+1.0/Filt2_R3-Filt2_Rp/(Filt2_R3**2)); -- k +constant Filt2_RC: real := Filt2_Rs*Filt2_C/1000.0; -- s +constant Filt2_ik: integer := integer(Filt2_Fs*1.0E6*Filt2_RC / 2.0**Filt2_Div2n); +-- Filter2 voltages +constant Filt2_V0: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4); -- V +constant Filt2_iV0: integer := integer(Filt2_V0 * real(IVmax)/Vmax); +constant Filt2_V1: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R4p*Filt2_R3); -- V +constant Filt2_iV1: integer := integer(Filt2_V1 * real(IVmax)/Vmax); +constant Filt2_V2: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4)+Filt2_V*Filt2_Rs/Filt2_R2; -- V +constant Filt2_iV2: integer := integer(Filt2_V2 * real(IVmax)/Vmax); +constant Filt2_V3: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4p)+Filt2_V*Filt2_Rs/Filt2_R2; -- V +constant Filt2_iV3: integer := integer(Filt2_V3 * real(IVmax)/Vmax); + +-- Oscillator3 -- +constant Osc3_div: integer := integer(2**Osc3_Div2n); +-- Oscillator3 charge/discharge voltages +constant Osc3_VFc: real := Osc3_Vb; -- V +constant Osc3_iVFc: integer := integer(Osc3_VFc * real(IVmax)/Vmax); +constant Osc3_VFd: real := Osc3_Vce; -- V +constant Osc3_iVFd: integer := integer(Osc3_VFd * real(IVmax)/Vmax); +-- Oscillator3 charge/discharge time constants +constant Osc3_RCc: real := (Osc3_R1+Osc3_R2)*Osc3_C/1000.0; -- s +constant Osc3_ikc: integer := integer(Osc3_Fs * 1.0E6 * Osc3_RCc / 2.0**Osc3_Div2n); +constant Osc3_RCd: real := Osc3_R2*Osc3_C/1000.0; -- s +constant Osc3_ikd: integer := integer(Osc3_Fs * 1.0E6 * Osc3_RCd / 2.0**Osc3_Div2n); + +signal u_c1 : unsigned(15 downto 0) := (others => '0'); +signal u_c2 : unsigned(15 downto 0) := (others => '0'); +signal u_c3 : unsigned(16 downto 0) := (others => '0'); +signal flip1 : std_logic := '0'; +signal flip2 : std_logic := '0'; +signal flip3 : std_logic := '0'; + +signal triggers : std_logic_vector(1 downto 0) := "00"; +--signal kc : unsigned(15 downto 0) := (others =>'0'); +--signal kd : unsigned(15 downto 0) := (others =>'0'); +signal kc : integer range 0 to Osc1_ik_max; +signal kd : integer range 0 to Osc1_ik_max; + +signal u_cf : unsigned(15 downto 0) := (others => '0'); +signal flips : std_logic_vector(1 downto 0) := "00"; +signal vf : unsigned(15 downto 0) := (others =>'0'); + +signal u_cf_scaled : unsigned(23 downto 0) := (others => '0'); +signal u_ctrl : unsigned(15 downto 0) := (others => '0'); + +signal sound: std_logic := '0'; + +begin + +-- Oscillateur1 +-- R1 = 47k, R2 = 100k, C1=0.01e-6, C2=0.047e-6, C3=1.000e-6 SR=10MHz +-- Div = 2^8 + +-- trigger = 00 +-- Charge : VF1 = 65535, k1 = 57 (R1+R2, C1) +-- Decharge : VF2 = 2621, k2 = 39 (R2, C1) +-- trigger = 01 +-- Charge : VF1 = 65535, k1 = 2756 (R1+R2, C1+C2) +-- Decharge : VF2 = 2621, k2 = 1875 (R2, C1+C2) +-- trigger = 10 +-- Charge : VF1 = 65535, k1 = 5800 (R1+R2, C1+C3) +-- Decharge : VF2 = 2621, k2 = 3945 (R2, C1+C3) +-- trigger = 11 +-- Charge : VF1 = 65535, k1 = 8498 (R1+R2, C1+C2+C3) +-- Decharge : VF2 = 2621, k2 = 5781 (R2, C1+C2+C3) + +triggers <= trigger2 & trigger1; + +with triggers select +kc <= Osc1_T0_ikc when "00", + Osc1_T1_ikc when "01", + Osc1_T2_ikc when "10", + Osc1_T3_ikc when others; + +with triggers select +kd <= Osc1_T0_ikd when "00", + Osc1_T1_ikd when "01", + Osc1_T2_ikd when "10", + Osc1_T3_ikd when others; + +process (clk) + variable cnt: integer range 0 to Osc1_ik_max := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c1 <= (others => '0'); + else + if u_c1 > X"AAAA" then flip1 <= '0'; end if; + if u_c1 < X"5555" then flip1 <= '1'; end if; + cnt := cnt + 1; + if flip1 = '1' then + if cnt = kc then + cnt := 0; + u_c1 <= u_c1 + (Osc1_iVFc - u_c1)/Osc1_div; + end if; + else + if cnt = kd then + cnt := 0; + u_c1 <= u_c1 - (u_c1 - Osc1_iVFd)/Osc1_div; + end if; + end if; + end if; + end if; +end process; + +-- Oscillateur2 +-- R1 = 510k, R2 = 510k, C=1.000e-6, SR=10MHz +-- Charge : VF1 = 65535, k1 = 39844 (R1+R2, C) +-- Decharge : VF2 = 2621, k2 = 19922 (R2, C) +-- Div = 2^8 + +process (clk) + variable cnt: integer range 0 to imax(Osc2_ikc,Osc2_ikd) := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c2 <= (others => '0'); + else + if u_c2 > X"AAAA" then flip2 <= '0'; end if; + if u_c2 < X"5555" then flip2 <= '1'; end if; + cnt := cnt + 1; + if flip2 = '1' then + if cnt = Osc2_ikc then + cnt := 0; + u_c2 <= u_c2 + (Osc2_iVFc - u_c2)/Osc2_div; + end if; + else + if cnt = Osc2_ikd then + cnt := 0; + u_c2 <= u_c2 - (u_c2 - Osc2_iVFd)/Osc2_div; + end if; + end if; + end if; + end if; +end process; + +-- Filtre +-- V1 = 5V +-- R1 = 10k, R2 = 5.1k, R3 = 5.1k, R4 = 5k, R5 = 10k, C=100.0e-6, SR=10MHz +-- Rp = R3//R4//R4//R1 = 1.68k +-- Rs = 1/(1/R2 + 1/R3 - Rp/(R3*R3)) = 3.05k +-- k = 11922 (Rs*C) +-- Div = 2^8 + +-- VF00 = 13159 (V*Rp*Rs)/(R4*R3) +-- VF01 = 19738 (V*Rp*Rs)/(R4p*R3) +-- VF10 = 52377 (V*Rp*Rs)/(R4*R3) + V*Rs/R2 +-- VF11 = 58957 (V*Rp*Rs)/(R4p*R3) + V*Rs/R2 + +flips <= flip2 & flip1; + +with flips select + +vf <= to_unsigned(Filt2_iV0,16) when "00", + to_unsigned(Filt2_iV1,16) when "01", + to_unsigned(Filt2_iV2,16) when "10", + to_unsigned(Filt2_iV3,16) when others; + +process (clk) + variable cnt: integer range 0 to Filt2_ik := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_cf <= (others => '0'); + else + cnt := cnt + 1; + if vf > u_cf then + if cnt = Filt2_ik then + cnt := 0; + u_cf <= u_cf + (vf - u_cf)/Filt2_div; + end if; + else + if cnt = Filt2_ik then + cnt := 0; + u_cf <= u_cf - (u_cf - vf)/Filt2_div; + end if; + end if; + end if; + end if; +end process; + +-- U_CTRL + +-- flip1 = 0 u_ctrl = 5V*Rp/R4 + u_cf*Rp/R3 # 22020 + u_cf*84/256 +-- flip1 = 1 u_ctrl = 5V*Rp/R4p + u_cf*Rp/R3 # 33063 + u_cf*84/256 + +u_cf_scaled <= u_cf*to_unsigned(C_flip1_scale,8); + +with flip1 select + u_ctrl <= to_unsigned(C_flip1_0,16)+u_cf_scaled(23 downto 8) when '0', + to_unsigned(C_flip1_1,16)+u_cf_scaled(23 downto 8) when others; + +-- Oscillateur3 +-- R1 = 20k, R2 = 20k, C=0.001e-6 SR=50MHz +-- Charge : VF1 = 65535, k1 = 31 (R1+R2) +-- Decharge : VF2 = 2621, k2 = 16 (R2) +-- Div = 2^6 + +-- Diviseur +-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF) +-- LS74 : Divide by 2 + +process (clk) + variable cnt: integer range 0 to imax(Osc3_ikc,Osc3_ikd) := 0; + variable cnt2: unsigned(3 downto 0) := (others => '0'); +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c3 <= (others => '0'); + flip3 <= '0'; + else + if u_c3 > u_ctrl then flip3 <= '0'; end if; + if u_c3 < u_ctrl/2 then + flip3 <= '1'; + if flip3 = '0' then + cnt2 := cnt2 + 1; + if cnt2 = "0000" then + cnt2 := unsigned(divider); + if divider /= "1111" then sound <= not sound; end if; + end if; + end if; + end if; + cnt := cnt + 1; + if flip3 = '1' then + if cnt = Osc3_ikc then + cnt := 0; + u_c3 <= u_c3 + (Osc3_iVFc - u_c3)/Osc3_div; + end if; + else + if cnt = Osc3_ikd then + cnt := 0; + u_c3 <= u_c3 - (u_c3 - Osc3_iVFd)/Osc3_div; + end if; + end if; + end if; + end if; +end process; + +with trigger2 select snd <= '0'&sound when '1', sound&'0' when others; + +end struct; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect3.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect3.vhd new file mode 100644 index 00000000..c5bc2e77 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_effect3.vhd @@ -0,0 +1,290 @@ +--------------------------------------------------------------------------------- +-- Phoenix sound effect3 (noise) by Dar (darfpga@aol.fr) (April 2016) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +-- this module generates noisy sound of ship missile shooting +-- ship explosions and enemy mothership explosion +-- it is often head throught all the levels of the game + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + +entity phoenix_effect3 is +generic( + -- Command 1 + Cmd1_Fs: real := 11.0; -- MHz + Cmd1_V: real := 5.0; -- V + Cmd1_Vd: real := 0.46; -- V + Cmd1_Vce: real := 0.2; -- V + Cmd1_R1: real := 1.0; -- k + Cmd1_R2: real := 0.33; -- k + Cmd1_R3: real := 20.0; -- k + Cmd1_C: real := 6.8; -- uF + Cmd1_Div2n: integer := 8; -- bits divisor + --Cmd1_bits: integer := 16; -- bits counter + -- Command 2 + Cmd2_Fs: real := 11.0; -- MHz + Cmd2_V: real := 5.0; -- V + Cmd2_Vd: real := 0.46; -- V + Cmd2_Vce: real := 0.2; -- V + Cmd2_R1: real := 1.0; -- k + Cmd2_R2: real := 0.33; -- k + Cmd2_R3: real := 47.0; -- k + Cmd2_C: real := 6.8; -- uF + Cmd2_Div2n: integer := 8; -- bits divisor + --Cmd2_bits: integer := 16; -- bits counter + -- Oscillator + Osc_Fs: real := 11.0; -- MHz + Osc_Vb: real := 5.0; -- V + Osc_Vce: real := 0.2; -- V + Oscmin_R1a: real := 47.0; -- k + Oscmin_R2: real := 0.33; -- k + Oscmin_C: real := 0.05; -- uF + Oscmin_bits: integer := 16; -- bits counter + Oscmax_R1a: real := 2.553; -- k + Oscmax_R2: real := 1.0; -- k + Oscmax_C: real := 0.05; -- uF + Osc_Div2n: integer := 7; -- bits divisor + --Osc_bits: integer := 16; -- bits counter + + C_commande2_chop_k: integer := 62500; + + Vmax: real := 5.0; -- V + Vmax_bits: integer := 16 -- number of bits to represent Vmax +); +port( + clk : in std_logic; + reset : in std_logic; + trigger1 : in std_logic; + trigger2 : in std_logic; + snd : out std_logic_vector(7 downto 0) +); +end phoenix_effect3; + +architecture struct of phoenix_effect3 is + +-- integer representation of voltage, full range +constant IVmax: integer := integer(2**Vmax_bits)-1; +-- Command1 -- +constant Cmd1_div: integer := integer(2**Cmd1_Div2n); +-- Command1 charge/discharge voltages +constant Cmd1_VFc: real := Cmd1_V-Cmd1_Vd; -- V +constant Cmd1_iVFc: integer := integer(Cmd1_VFc * real(IVmax)/Vmax); +constant Cmd1_VFd: real := Cmd1_Vce+Cmd1_Vd; -- V +constant Cmd1_iVFd: integer := integer(Cmd1_VFd * real(IVmax)/Vmax); +-- Command1 charge/discharge time constants +constant Cmd1_RCc: real := (Cmd1_R1+Cmd1_R2+Cmd1_R3)*Cmd1_C/1000.0; -- s +constant Cmd1_ikc: integer := integer(Cmd1_Fs * 1.0E6 * Cmd1_RCc / 2.0**Cmd1_Div2n); +constant Cmd1_RCd: real := Cmd1_R2*Cmd1_C/1000.0; -- s +constant Cmd1_ikd: integer := integer(Cmd1_Fs * 1.0E6 * Cmd1_RCd / 2.0**Cmd1_Div2n); +-- Command2 -- +constant Cmd2_div: integer := integer(2**Cmd2_Div2n); +-- Command2 charge/discharge voltages +constant Cmd2_VFc: real := (Cmd2_V-Cmd2_Vd)*Cmd2_R3/(Cmd2_R1+Cmd2_R2+Cmd2_R3); -- V +constant Cmd2_iVFc: integer := integer(Cmd2_VFc * real(IVmax)/Vmax); +constant Cmd2_VFd: real := 0.0; -- V +constant Cmd2_iVFd: integer := integer(Cmd2_VFd * real(IVmax)/Vmax); +-- Command2 charge/discharge time constants +constant Cmd2_RCc: real := (Cmd2_R1+Cmd2_R2)*Cmd2_R3/(Cmd2_R1+Cmd2_R2+Cmd2_R3)*Cmd2_C/1000.0; -- s +constant Cmd2_ikc: integer := integer(Cmd2_Fs * 1.0E6 * Cmd2_RCc / 2.0**Cmd2_Div2n); +constant Cmd2_RCd: real := Cmd2_R3*Cmd2_C/1000.0; -- s +constant Cmd2_ikd: integer := integer(Cmd2_Fs * 1.0E6 * Cmd2_RCd / 2.0**Cmd2_Div2n); +-- Oscillator -- +constant Osc_div: integer := integer(2**Osc_Div2n); +-- Oscillator charge/discharge voltages +constant Osc_VFc: real := Osc_Vb; -- V +constant Osc_iVFc: integer := integer(Osc_VFc * real(IVmax)/Vmax); +constant Osc_VFd: real := Osc_Vce; -- V +constant Osc_iVFd: integer := integer(Osc_VFd * real(IVmax)/Vmax); +-- Oscillator min charge/discharge time constants +constant Oscmin_RCc: real := (Oscmin_R1a+Oscmin_R2)*Oscmin_C/1000.0; -- s +constant Oscmin_ikc: integer := integer(Osc_Fs * 1.0E6 * Oscmin_RCc / 2.0**Osc_Div2n); +constant Oscmin_RCd: real := Oscmin_R2*Oscmin_C/1000.0; -- s +constant Oscmin_ikd: integer := integer(Osc_Fs * 1.0E6 * Oscmin_RCd / 2.0**Osc_Div2n); +-- Oscillator max charge/discharge time constants +constant Oscmax_RCc: real := (Oscmax_R1a+Oscmax_R2)*Oscmax_C/1000.0; -- s +constant Oscmax_ikc: integer := integer(Osc_Fs * 1.0E6 * Oscmax_RCc / 2.0**Osc_Div2n); +constant Oscmax_RCd: real := Oscmax_R2*Oscmax_C/1000.0; -- s +constant Oscmax_ikd: integer := integer(Osc_Fs * 1.0E6 * Oscmax_RCd / 2.0**Osc_Div2n); + +function imax(x,y: integer) return integer is begin + if x > y then + return x; + else + return y; + end if; +end imax; + +signal u_c1 : unsigned(15 downto 0) := (others => '0'); +signal u_c2 : unsigned(15 downto 0) := (others => '0'); +signal u_c3 : unsigned(15 downto 0) := (others => '0'); +signal flip3 : std_logic := '0'; + +signal k_ch : unsigned(25 downto 0) := (others =>'0'); + +signal u_ctrl1 : unsigned(15 downto 0) := (others => '0'); +signal u_ctrl2 : unsigned(15 downto 0) := (others => '0'); +signal u_ctrl1_f : unsigned( 7 downto 0) := (others => '0'); +signal u_ctrl2_f : unsigned( 7 downto 0) := (others => '0'); +signal sound : unsigned( 7 downto 0) := (others => '0'); + +signal shift_reg : std_logic_vector(17 downto 0) := (others => '0'); + +begin + +-- Commande1 +-- R1 = 1k, R2 = 0.33k, R3 = 20k C=6.8e-6 SR=10MHz +-- Charge : VF1 = 59507, k1 = 5666 (R1+R2+R3) +-- Decharge : VF2 = 8651, k2 = 88 (R2) +-- Div = 2^8 + +process (clk) + -- variable cnt : unsigned(15 downto 0) := (others => '0'); + variable cnt: integer range 0 to imax(Cmd1_ikc,Cmd1_ikd)*2 := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c1 <= (others => '0'); + else + cnt := cnt + 1; + if trigger1 = '1' then + -- if cnt > C_commande1_k1 then + if cnt > Cmd1_ikc then + cnt := 0; + -- u_c1 <= u_c1 + (C_commande1_VF1 - u_c1)/256; + u_c1 <= u_c1 + (Cmd1_iVFc - u_c1)/Cmd1_div; + end if; + else + -- if cnt > C_commande1_k2 then + if cnt > Cmd1_ikd then + cnt := 0; + -- u_c1 <= u_c1 - (u_c1 - C_commande1_VF2)/256; + u_c1 <= u_c1 - (u_c1 - Cmd1_iVFd)/Cmd1_div; + end if; + end if; + end if; + end if; +end process; + +-- Commande2 +-- R1 = 1k, R2 = 0.33k, R3 = 47k C=6.8e-6 SR=10MHz +-- Charge : VF1 = 57869, k1 = 344 (R1+R2)//R3 +-- Decharge : VF2 = 0, k2 = 12484 (R3) +-- Div = 2^8 + +process (clk) + -- variable cnt : unsigned(15 downto 0) := (others => '0'); + variable cnt: integer range 0 to imax(Cmd2_ikc,Cmd2_ikd)*2 := 0; +begin + if rising_edge(clk) then + if reset = '1' then + -- cnt := (others => '0'); + cnt := 0; + u_c2 <= (others => '0'); + else + cnt := cnt + 1; + if trigger2 = '1' then + -- if cnt > C_commande2_k1 then + if cnt > Cmd2_ikc then + -- cnt := (others => '0'); + cnt := 0; + -- u_c2 <= u_c2 + (C_commande2_VF1 - u_c2)/256; + u_c2 <= u_c2 + (Cmd2_iVFc - u_c2)/Cmd2_div; + end if; + else + -- if cnt > C_commande2_k2 then + if cnt > Cmd2_ikd then + -- cnt := (others => '0'); + cnt := 0; + -- u_c2 <= u_c2 - (u_c2 - C_commande2_VF2)/256; + u_c2 <= u_c2 - (u_c2 - Cmd2_iVFd)/Cmd2_div; + end if; + end if; + end if; + end if; +end process; + +-- control voltage from command1 is R3 voltage (not u_c1 voltage) +with trigger1 select +-- u_ctrl1 <= (to_unsigned(C_commande1_VF1,16) - u_c1) when '1', (others=>'0') when others; +u_ctrl1 <= (to_unsigned(Cmd1_iVFc,16) - u_c1) when '1', (others=>'0') when others; + +-- control voltage from command2 is u_c2 voltage +u_ctrl2 <= u_c2; + +-- sum up and scaled both control voltages to vary R1 resistor of oscillator +-- k_ch <= shift_right(((u_ctrl1/2 + u_ctrl2/2) * to_unsigned(C_oscillateur_min_k1-C_oscillateur_max_k1,10)),15) + C_oscillateur_max_k1; +k_ch <= shift_right(((u_ctrl1/2 + u_ctrl2/2) * to_unsigned(Oscmin_ikc-Oscmax_ikc,10)),15) + Oscmax_ikc; + +-- Oscillateur +-- R1 = 47k..2.533k, R2 = 1k, C=0.05e-6, SR=50MHz +-- Charge : VF1 = 65536, k_ch = 938..69 (R1+R2, C) +-- Decharge : VF2 = 2621, k2 = 20 (R2, C) +-- Div = 2^7 + +-- noise generator triggered by oscillator output + +process (clk) + variable cnt: integer range 0 to imax(imax(Oscmin_ikc,Oscmin_ikd), imax(Oscmax_ikc,Oscmax_ikd))+256 := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + u_c3 <= (others => '0'); + else + if u_c3 > X"AAAA" then flip3 <= '0'; end if; + if u_c3 < X"5555" then + flip3 <= '1'; + if flip3 = '0' then + shift_reg <= shift_reg(16 downto 0) & not(shift_reg(17) xor shift_reg(16)); + end if; + end if; + cnt := cnt + 1; + if flip3 = '1' then + if cnt > k_ch then + cnt := 0; + u_c3 <= u_c3 + (Osc_iVFc - u_c3)/Osc_div; + end if; + else + if cnt > Oscmax_ikd then + cnt := 0; + u_c3 <= u_c3 - (u_c3 - Osc_iVFd)/Osc_div; + end if; + end if; + end if; + end if; +end process; + +-- modulated (chop) command1 voltage with noise generator output +with shift_reg(17) xor shift_reg(16) select +u_ctrl1_f <= u_ctrl1(15 downto 8)/2 when '0', (others => '0') when others; + + +-- modulated (chop) command2 voltage with noise generator output +-- and add 400Hz filter (raw sub-sampling) +-- f=10 MHz, k = 25000 +process (clk) + variable cnt : unsigned(15 downto 0) := (others => '0'); +begin + if rising_edge(clk) then + cnt := cnt + 1; + if cnt > C_commande2_chop_k then + cnt := (others => '0'); + if (shift_reg(17) xor shift_reg(16)) = '0' then + u_ctrl2_f <= u_ctrl2(15 downto 8)/2; + else + u_ctrl2_f <= (others => '0'); + end if; + end if; + end if; +end process; + +-- mix modulated noises 1 and 2 +sound <= u_ctrl1_f + u_ctrl2_f; +snd <= std_logic_vector(sound); + +end struct; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_mist.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_mist.vhd new file mode 100644 index 00000000..8a320e0e --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_mist.vhd @@ -0,0 +1,309 @@ +--------------------------------------------------------------------------------- +-- DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr) (April 2016) +-- http://darfpga.blogspot.fr +-- +-- Main features +-- PS2 keyboard input +-- wm8731 sound output +-- NO board SRAM used +-- +-- sw 0: on/off hdmi-audio +-- +-- Board switch : ---- todo fixme switches note +-- 1 - 4 : dip switch +-- 0-1 : lives 3-6 +-- 3-2 : bonus life 30K-60K +-- 4 : coin 1-2 +-- 6-5 : unkonwn +-- 7 : upright-cocktail +-- 8 -10 : sound_select +-- 0XX : all mixed (normal) +-- 100 : sound1 only +-- 101 : sound2 only +-- 110 : sound3 only +-- 111 : melody only +-- Board key : +-- 0 : reset +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + +entity phoenix_mist is +port +( + CLOCK_27 : in std_logic; + LED : out std_logic; + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0); + VGA_HS : out std_logic; + VGA_VS : out std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + SPI_SS2 : in std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic +); +end; + +architecture struct of phoenix_mist is + + signal clk : std_logic; + signal clk_88m : std_logic; + signal reset : std_logic; + signal clock_stable : std_logic; + + signal audio : std_logic_vector(11 downto 0); + signal video_r, video_g, video_b: std_logic_vector(1 downto 0); + signal vsync, hsync : std_logic; + + signal dip_switch : std_logic_vector(7 downto 0);-- := (others => '0'); + signal status : std_logic_vector(31 downto 0); + signal buttons : std_logic_vector(1 downto 0); + signal scandoubler_disable : std_logic; + signal ypbpr : std_logic; + signal ce_pix : std_logic; + + signal scanlines : std_logic_vector(1 downto 0); + signal hq2x : std_logic; + + signal coin : std_logic; + signal player_start : std_logic_vector(1 downto 0); + signal button_left, button_right, button_protect, button_fire: std_logic; + signal joy0 : std_logic_vector(7 downto 0); + signal joy1 : std_logic_vector(7 downto 0); + signal ps2Clk : std_logic; + signal ps2Data : std_logic; + signal kbd_joy : std_logic_vector(7 downto 0); + signal upjoyL : std_logic; + signal upjoyR : std_logic; + signal upjoyB : std_logic; +-- config string used by the io controller to fill the OSD + constant CONF_STR : string := "PHOENIX;;O4,Screen Direction,Upright,Normal;O67,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.0;"; + + function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + end function; + + component mist_io + generic ( STRLEN : integer := 0 ); + port ( + clk_sys :in std_logic; + SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; + SPI_DO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + buttons : out std_logic_vector(1 downto 0); + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + status : out std_logic_vector(31 downto 0); + scandoubler_disable, ypbpr : out std_logic; + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); + end component mist_io; + + component video_mixer + generic ( LINE_LENGTH : integer := 352; HALF_DEPTH : integer := 1 ); + port ( + clk_sys, ce_pix, ce_pix_actual : in std_logic; + SPI_SCK, SPI_SS3, SPI_DI : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; + + R, G, B : in std_logic_vector(2 downto 0); + HSync, VSync, line_start, mono : in std_logic; + + VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); + VGA_VS, VGA_HS : out std_logic + ); + end component video_mixer; + + component keyboard + PORT( + clk : in std_logic; + reset : in std_logic; + ps2_kbd_clk : in std_logic; + ps2_kbd_data : in std_logic; + joystick : out std_logic_vector (7 downto 0) + ); + end component; + + +begin + +-- SWITCH 1: SWITCH 2: NUMBER OF SPACESHIPS: +-- --------- --------- --------------------- +-- OFF OFF 6 +-- ON OFF 5 +-- OFF ON 4 +-- ON ON 3 +-- FIRST FREE SECOND FREE +-- SWITCH 3: SWITCH 4: SHIP SCORE: SHIP SCORE: +-- --------- --------- ----------- ----------- +-- OFF OFF 6,000 60,000 +-- ON OFF 5,000 50,000 +-- OFF ON 4,000 40,000 +-- ON ON 3,000 30,000 + + --Cocktail,Factory,Factory,Factory,Bonus2,Bonus1,Ships2,Ships1 + dip_switch <= "00001111"; + + mist_io_inst : mist_io + generic map (STRLEN => CONF_STR'length) + port map ( + clk_sys => clk, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_DI => SPI_DI, + SPI_DO => SPI_DO, + conf_str => to_slv(CONF_STR), + buttons => buttons, + scandoubler_disable => scandoubler_disable, + ypbpr => ypbpr, + joystick_1 => joy1, + joystick_0 => joy0, + status => status, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data + ); + + -- + -- Audio + -- + u_dac1 : entity work.dac + port map( + clk_i => clk_88m, + res_n_i => not reset, + dac_i => audio, + dac_o => AUDIO_L + ); + + u_dac2 : entity work.dac + port map( + clk_i => clk_88m, + res_n_i => not reset, + dac_i => audio, + dac_o => AUDIO_R + ); + + + pll: entity work.pll27 + port map( + inclk0 => CLOCK_27, + c0 => clk_88m, + c1 => clk, + locked => clock_stable + ); + + reset <= status(0) or status(5) or buttons(1) or not clock_stable; + + u_keyboard : keyboard + port map( + clk => clk, + reset => reset, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data, + joystick => kbd_joy + ); + + process(clk_88m) + variable cnt: integer range 0 to 6000000 := 0; + begin + if rising_edge(clk_88m) then + if status(3 downto 1) /= "000" then + cnt := 0; + coin <= status(1); + player_start <= status(3 downto 2); + else + if cnt < 6000000 then + cnt := cnt + 1; + else + coin <= '0'; + player_start <= "00"; + end if; + end if; + end if; + end process; + + upjoyB <= joy0(2) or joy1(2) when status(4) = '0' else joy0(0) or joy1(0); + upjoyL <= joy0(1) or joy1(1) or kbd_joy(6) when status(4) = '0' else joy0(2) or joy1(2) or kbd_joy(5); + upjoyR <= joy0(0) or joy1(0) or kbd_joy(7) when status(4) = '0' else joy0(3) or joy1(3) or kbd_joy(4); + + phoenix : entity work.phoenix + port map + ( + clk => clk, + reset => reset, + ce_pix => ce_pix, + dip_switch => dip_switch, + btn_coin => kbd_joy(3) or coin,--ESC + btn_player_start(0) => kbd_joy(1) or player_start(0),--1 + btn_player_start(1) => kbd_joy(2) or player_start(1),--2 + btn_left => upjoyL, + btn_right => upjoyR, + btn_barrier => upjoyB or kbd_joy(2),--TAB + btn_fire => joy0(4) or joy1(4) or kbd_joy(0),--space + video_r => video_r, + video_g => video_g, + video_b => video_b, + video_hs => hsync, + video_vs => vsync, + audio_select => "000", + audio => audio + ); + + scanlines(0) <= '1' when status(7 downto 6) = "10" else '0'; + scanlines(1) <= '1' when status(7 downto 6) = "11" else '0'; + hq2x <= '1' when status(7 downto 6) = "01" else '0'; + + vmixer : video_mixer + port map ( + clk_sys => clk_88m, + ce_pix => ce_pix, + ce_pix_actual => ce_pix, + + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + + scanlines => scanlines, + scandoubler_disable => scandoubler_disable, + hq2x => hq2x, + ypbpr => ypbpr, + ypbpr_full => '1', + + R => video_r & video_r(1), + G => video_g & video_g(1), + B => video_b & video_b(1), + HSync => hsync, + VSync => vsync, + line_start => '0', + mono => '0', + + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_VS => VGA_VS, + VGA_HS => VGA_HS + ); + + LED <= '1'; + +end struct; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_music.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_music.vhd new file mode 100644 index 00000000..56d6c594 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_music.vhd @@ -0,0 +1,241 @@ +--------------------------------------------------------------------------------- +-- Phoenix music by Dar (darfpga@aol.fr) (April 2016) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity phoenix_music is +generic( + C_clk_freq: real := 11.0 -- MHz +); +port( + clk : in std_logic; + reset : in std_logic; + trigger : in std_logic; + sel_song : in std_logic; + snd : out std_logic_vector(7 downto 0) +); +end phoenix_music; + +architecture struct of phoenix_music is + +constant C_voice_attack: integer := integer(230.0 * C_clk_freq); -- larger value is faster +constant C_song0_tempo: integer := integer(2200.0 * C_clk_freq); -- larger value is faster +constant C_song1_tempo: integer := integer(1700.0 * C_clk_freq); -- larger value is faster +constant C_voice_down_rate: integer := integer(4000.0 / C_clk_freq); -- larger value is slower + +type voice_array is array (0 to 94) of integer range 0 to 127; +-- main voice1 (Jeux Interdits) +constant voice1 : voice_array := ( +32,96,32,96,32,96,32,96,26,90,24,88,24,88,23,87,21,85,21,85,24,88,32,96,37,101,101,101,101,101,37,101,35,99,33,97,33,97,32,96,26,90,26,90,32,96,33,97,32,96,33,97,32,96,36,100,33,97,32,96,32,96,26,90,24,88,24,88,23,87,21,85,23,87,23,87,23,87,23,87,24,88,23,87,21,85,24,88,32,96,37,101,101,101,101); +-- accompagnement voice1 +constant voice2 : voice_array := ( +5,69,69,69,69,69,16,80,80,80,80,80,8,72,8,72,8,72,16,80,80,80,80,80,5,69,5,8,16,21,5,69,69,69,69,69,17,81,81,81,81,81,10,74,74,74,74,74,16,80,80,80,80,80,16,80,80,80,80,80,8,72,72,72,72,72,5,69,69,69,69,69,7,71,71,71,71,71,17,81,81,81,8,72,5,69,16,80,8,72,5,69,69,69,69); + +-- voice1, voice2 and voice3 value description +-- bit3-bit0 : tone from 0(La/A) to 11(Sol/G#) +-- bit5-bit4 : octave from 0(220Hz)to 2(880Hz) +-- bit6 : 0 = strike (restart) the tone, 1 = don't strike (hold) the tone + +type voice_array2 is array (0 to 45) of integer range 0 to 127; +-- main voice3 (La lettre a Elise) +constant voice3 : voice_array2 := ( +37,36,37,36,37,32,35,33,26,5,10,17,21,26,32,5,16,21,25,32,33,5,10,17,37,36,37,36,37,32,35,33,26,5,10,17,21,26,32,5,16,21,33,32,26,90); + +type period_array is array (0 to 11) of integer range 0 to 65535; +-- Octave 220Hz @ 10MHz +constant tone_period : period_array := ( + 45455, -- ton 0 La (A ) + 42903, -- ton 1 La# (A#) + 40495, -- ton 2 Si (B ) + 38223, -- ton 3 Do (C ) + 36077, -- ton 4 Do# (C#) + 34052, -- ton 5 Re (D ) + 32141, -- ton 6 Re# (D#) + 30337, -- ton 7 Mi (E ) + 28635, -- ton 8 Fa (F ) + 27027, -- ton 9 Fa# (F#) + 25511, -- ton 10 Sol (G ) + 24079 -- ton 11 Sol# (G#) +); + +signal tempo_period : integer range 0 to C_song0_tempo := C_song1_tempo; --0.19s @ 100kHz + +signal voice1_tone : integer range 0 to 65535 := 0; +signal voice1_tone_div : integer range 0 to 65535 := 0; +signal voice1_code : unsigned(6 downto 0) := "0000000"; +signal voice1_vol : unsigned(7 downto 0) := "00000000"; +signal voice1_snd : std_logic := '0'; + +signal voice2_tone : integer range 0 to 65535 := 0; +signal voice2_tone_div : integer range 0 to 65535 := 0; +signal voice2_code : unsigned(6 downto 0) := "0000000"; +signal voice2_vol : unsigned(7 downto 0) := "00000000"; +signal voice2_snd : std_logic := '0'; + +signal snd1 : unsigned(7 downto 0) := "00000000"; +signal snd2 : unsigned(7 downto 0) := "00000000"; + +signal trigger_r : std_logic := '0'; +signal max_step : integer range 0 to 94 := 94; +signal sel_song_r: std_logic := '1'; + +begin + +process (clk) + variable cnt : integer range 0 to 127 := 0; + variable step : integer range 0 to 94 := 94; + variable tempo : integer range 0 to C_song0_tempo := 0; + variable voice1_code_v : unsigned(6 downto 0) := "0000000"; + variable voice2_code_v : unsigned(6 downto 0) := "0000000"; + variable voice1_down_rate : integer range 0 to C_voice_down_rate := 0; + variable voice2_down_rate : integer range 0 to C_voice_down_rate := 0; +begin + if rising_edge(clk) then + trigger_r <= trigger; + + if reset = '1' then + cnt := 0; + step := 94; + voice1_vol <= X"00"; + voice2_vol <= X"00"; + elsif trigger ='1' and trigger_r ='0' and step = 94 then -- restart music on edge trigger if not already playing + cnt := 0; + step := 0; + voice1_vol <= X"00"; + voice2_vol <= X"00"; + sel_song_r <= sel_song; + if sel_song = '1' then + max_step <= 94; + tempo_period <= C_song1_tempo; + else + max_step <= 46; + tempo_period <= C_song0_tempo; + end if; + else + cnt := cnt +1; + if cnt >= 100 then + cnt := 0; + tempo := tempo +1; + if tempo >= tempo_period then -- next beat + tempo := 0; + if step < max_step then -- if not end of music get next note + if sel_song_r = '1' then + voice1_code_v := to_unsigned(voice1(step),7); + voice2_code_v := to_unsigned(voice2(step),7); + else + voice1_code_v := to_unsigned(voice3(step),7); + voice2_code_v := to_unsigned(voice3(step),7); + end if; + voice1_code <= voice1_code_v; + voice2_code <= voice2_code_v; + step := step + 1; + else -- if end cut-off volume + voice1_vol <= X"00"; + voice2_vol <= X"00"; + step := 94; + end if; + end if; + if (step < 94) then -- if not end of music + -- manage voice1 volume + -- ramp up fast to xF0 at begining of beat when new strike + if (tempo < C_voice_attack) and (voice1_code_v(6)='0') then + if voice1_vol < X"F0" then voice1_vol <= voice1_vol + X"01"; end if; + voice1_down_rate := 0; + -- ramp down slowly after a while, down to x80 + else + if voice1_vol > X"80" then + voice1_down_rate := voice1_down_rate+1; + if voice1_down_rate >= C_voice_down_rate then + voice1_down_rate := 0; + voice1_vol <= voice1_vol - X"01"; + end if; + end if; + end if; + -- manage voice2 volume + if (tempo < C_voice_attack) and (voice2_code_v(6)='0') then + if voice2_vol < X"F0" then voice2_vol <= voice2_vol + X"01"; end if; + voice2_down_rate := 0; + else + if voice2_vol > X"80" then + voice2_down_rate := voice2_down_rate+1; + if voice2_down_rate >= C_voice_down_rate then + voice2_down_rate := 0; + voice2_vol <= voice2_vol - X"01"; + end if; + end if; + end if; + end if; + end if; + end if; + end if; +end process; + +-- get voice1 raw tone +voice1_tone <= tone_period(to_integer(voice1_code(3 downto 0))); + +-- get voice1 tone w.r.t octave +with voice1_code(5 downto 4) select +voice1_tone_div <= voice1_tone when "00", + voice1_tone/2 when "01", + voice1_tone/4 when others; + +-- generate voice1 frequency +voice1_frequency: process (clk) + variable cnt : integer range 0 to 65535 := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + else + cnt := cnt+1; + if cnt >= voice1_tone_div then + cnt := 0; + voice1_snd <= not voice1_snd; + end if; + end if; + end if; +end process; + +-- get voice2 raw tone +voice2_tone <= tone_period(to_integer(voice2_code(3 downto 0))); + +-- get voice2 tone w.r.t octave +with voice2_code(5 downto 4) select +voice2_tone_div <= voice2_tone when "00", + voice2_tone/2 when "01", + voice2_tone/4 when others; + +-- generate voice2 frequency +voice2_frequency: process (clk) + variable cnt : integer range 0 to 65535 := 0; +begin + if rising_edge(clk) then + if reset = '1' then + cnt := 0; + else + cnt := cnt+1; + if cnt >= voice2_tone_div then + cnt := 0; + voice2_snd <= not voice2_snd; + end if; + end if; + end if; +end process; + +-- modulate voice1 volume with voice1 frequency +with voice1_snd select snd1 <= voice1_vol when '1', X"00" when others; + +-- modulate voice2 volume with voice2 frequency +with voice2_snd select snd2 <= voice2_vol when '1', X"00" when others; + +-- mix voice1 and voice 2 +snd <= std_logic_vector(('0'&snd1(7 downto 1)) + ('0'&snd2(7 downto 1))); + +end struct; + diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_prog.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_prog.vhd new file mode 100644 index 00000000..5278aeb3 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_prog.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity phoenix_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of phoenix_prog is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"31",X"FF",X"4B",X"26",X"50",X"36",X"00",X"CD", + X"50",X"00",X"21",X"00",X"18",X"0E",X"03",X"CD",X"D0",X"01",X"CD",X"80",X"00",X"3A",X"A2",X"43", + X"A7",X"CA",X"2D",X"00",X"CD",X"00",X"04",X"CD",X"00",X"27",X"C3",X"1A",X"00",X"3E",X"0F",X"26", + X"60",X"77",X"26",X"68",X"77",X"CD",X"77",X"03",X"00",X"CD",X"E0",X"17",X"A7",X"CA",X"46",X"00", + X"CD",X"88",X"02",X"C3",X"1A",X"00",X"CD",X"E3",X"00",X"C3",X"1A",X"00",X"FF",X"FF",X"FF",X"FF", + X"26",X"68",X"36",X"00",X"26",X"60",X"36",X"00",X"26",X"58",X"36",X"00",X"CD",X"6B",X"00",X"26", + X"50",X"36",X"01",X"CD",X"6B",X"00",X"26",X"50",X"36",X"00",X"C9",X"21",X"F8",X"4B",X"3E",X"3F", + X"36",X"00",X"2B",X"BC",X"C2",X"70",X"00",X"C9",X"CD",X"96",X"01",X"C3",X"F0",X"06",X"FF",X"FF", + X"26",X"78",X"7E",X"E6",X"80",X"CA",X"80",X"00",X"7E",X"E6",X"80",X"C2",X"88",X"00",X"26",X"70", + X"7E",X"21",X"A0",X"43",X"46",X"77",X"2C",X"70",X"2E",X"9B",X"CD",X"00",X"02",X"2E",X"8F",X"7E", + X"FE",X"09",X"C8",X"D2",X"00",X"00",X"06",X"01",X"CD",X"BB",X"00",X"C8",X"2E",X"8F",X"34",X"7E", + X"C6",X"20",X"32",X"42",X"41",X"C9",X"00",X"C9",X"FF",X"FF",X"FF",X"21",X"A0",X"43",X"7E",X"2F", + X"A0",X"2C",X"A6",X"C9",X"7E",X"E6",X"0F",X"F6",X"20",X"12",X"CD",X"10",X"02",X"05",X"C8",X"7E", + X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"F6",X"20",X"12",X"CD",X"10",X"02",X"2B",X"05",X"C2",X"C4", + X"00",X"C9",X"FF",X"21",X"99",X"43",X"CD",X"00",X"02",X"01",X"01",X"00",X"CD",X"58",X"02",X"CA", + X"E1",X"01",X"01",X"02",X"00",X"11",X"1F",X"01",X"CD",X"60",X"02",X"D2",X"96",X"01",X"01",X"20", + X"01",X"CD",X"58",X"02",X"CA",X"CA",X"0B",X"0E",X"B0",X"CD",X"58",X"02",X"CA",X"E1",X"01",X"0E", + X"B8",X"CD",X"58",X"02",X"CA",X"80",X"05",X"0E",X"C0",X"11",X"DF",X"02",X"CD",X"60",X"02",X"D2", + X"78",X"00",X"01",X"00",X"03",X"11",X"AF",X"03",X"CD",X"60",X"02",X"D2",X"DC",X"21",X"01",X"E6", + X"03",X"11",X"FF",X"FF",X"CD",X"60",X"02",X"D2",X"B0",X"03",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF", + X"CD",X"A0",X"03",X"CD",X"80",X"00",X"CD",X"80",X"03",X"21",X"A3",X"43",X"36",X"02",X"2C",X"36", + X"00",X"00",X"00",X"00",X"2E",X"B8",X"06",X"08",X"CD",X"D8",X"05",X"2E",X"BA",X"36",X"10",X"2E", + X"BE",X"3A",X"00",X"78",X"E6",X"0C",X"07",X"07",X"C6",X"30",X"77",X"26",X"58",X"36",X"00",X"CD", + X"80",X"00",X"C9",X"7E",X"E6",X"7F",X"06",X"CE",X"FE",X"1F",X"D8",X"06",X"FE",X"C8",X"06",X"AE", + X"FE",X"5F",X"D8",X"06",X"FE",X"C8",X"06",X"CE",X"FE",X"7F",X"D8",X"06",X"FE",X"2D",X"7E",X"FE", + X"09",X"C0",X"06",X"7E",X"C9",X"FF",X"7E",X"E6",X"1F",X"FE",X"06",X"D8",X"5F",X"7E",X"E6",X"E0", + X"4F",X"2D",X"46",X"2E",X"A8",X"70",X"2C",X"71",X"01",X"60",X"18",X"CD",X"06",X"02",X"7E",X"2D", + X"66",X"6F",X"7B",X"56",X"2C",X"5E",X"2D",X"4F",X"85",X"6F",X"79",X"D6",X"06",X"4F",X"CA",X"C8", + X"01",X"CD",X"17",X"02",X"0D",X"C2",X"C1",X"01",X"7E",X"12",X"C3",X"E0",X"14",X"C2",X"C0",X"01", + X"56",X"2C",X"5E",X"7D",X"C6",X"05",X"6F",X"06",X"1A",X"CD",X"ED",X"01",X"0D",X"C2",X"D0",X"01", + X"C9",X"CD",X"40",X"01",X"21",X"60",X"19",X"0E",X"03",X"C3",X"D0",X"01",X"FF",X"7E",X"12",X"23", + X"CD",X"17",X"02",X"05",X"C2",X"ED",X"01",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"34",X"C0",X"2D",X"34",X"2C",X"C9",X"7E",X"81",X"77",X"2D",X"7E",X"88",X"77",X"2C",X"C9",X"FF", + X"7B",X"C6",X"20",X"5F",X"D0",X"14",X"C9",X"7B",X"D6",X"20",X"5F",X"D0",X"15",X"C9",X"FF",X"FF", + X"AF",X"7E",X"81",X"27",X"77",X"2D",X"7E",X"88",X"27",X"77",X"2D",X"7E",X"CE",X"00",X"27",X"77", + X"2C",X"2C",X"C9",X"FF",X"FF",X"FF",X"37",X"3E",X"99",X"CE",X"00",X"91",X"86",X"27",X"77",X"2D", + X"3E",X"99",X"CE",X"00",X"90",X"86",X"27",X"77",X"2D",X"3E",X"99",X"CE",X"00",X"86",X"27",X"77", + X"2C",X"2C",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"7E",X"B9",X"C0",X"2D",X"7E",X"2C",X"B8",X"C9", + X"CD",X"70",X"02",X"D8",X"CD",X"77",X"02",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"7E",X"91",X"2D",X"7E",X"98",X"2C",X"C9",X"7B",X"96",X"2D",X"7A",X"9E",X"2C",X"C9",X"FF",X"FF", + X"7D",X"B9",X"C0",X"7C",X"B8",X"C9",X"FF",X"FF",X"CD",X"40",X"01",X"21",X"C0",X"19",X"0E",X"02", + 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X"00",X"00",X"00",X"00",X"9C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A3",X"A5",X"A4",X"A6", + X"00",X"00",X"9C",X"00",X"00",X"00",X"00",X"00",X"9D",X"00",X"9E",X"00",X"00",X"00",X"9F",X"00", + X"A0",X"00",X"00",X"00",X"A1",X"00",X"A2",X"00",X"00",X"00",X"96",X"00",X"00",X"00",X"00",X"00", + X"97",X"00",X"93",X"00",X"00",X"00",X"98",X"00",X"99",X"00",X"00",X"00",X"9A",X"00",X"9B",X"00", + X"00",X"00",X"90",X"00",X"00",X"00",X"00",X"00",X"91",X"00",X"00",X"00",X"00",X"00",X"92",X"00", + X"93",X"00",X"00",X"00",X"94",X"00",X"95",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"08",X"00", + X"00",X"00",X"0A",X"00",X"00",X"00",X"0B",X"00",X"0C",X"0C",X"0E",X"FF",X"0D",X"0E",X"0D",X"FF", + X"06",X"70",X"07",X"70",X"08",X"70",X"08",X"70",X"08",X"70",X"07",X"78",X"06",X"80",X"05",X"88", + X"04",X"90",X"03",X"98",X"02",X"A0",X"01",X"A8",X"02",X"70",X"03",X"70",X"04",X"70",X"05",X"70", + X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"34",X"2C",X"26",X"20",X"1C",X"18",X"14",X"12",X"0F", + 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X"10",X"60",X"07",X"1F",X"37",X"0A",X"36",X"C0",X"F0",X"10",X"0B",X"1A",X"37",X"0A",X"36",X"C0", + X"40",X"FF",X"04",X"FF",X"36",X"EA",X"36",X"C0",X"10",X"FF",X"08",X"FF",X"36",X"EA",X"36",X"C0", + X"40",X"10",X"0F",X"17",X"37",X"0A",X"36",X"C0",X"10",X"FF",X"0A",X"FF",X"36",X"EA",X"35",X"E0", + X"FF",X"FF",X"FF",X"FF",X"36",X"CC",X"35",X"E0",X"FF",X"FF",X"FF",X"FF",X"36",X"CC",X"35",X"E0", + X"10",X"FF",X"06",X"FF",X"36",X"EA",X"35",X"E0",X"10",X"10",X"07",X"79",X"37",X"0A",X"35",X"E0", + X"01",X"48",X"EE",X"00",X"10",X"B0",X"10",X"20",X"01",X"49",X"2C",X"00",X"10",X"A0",X"00",X"B0", + X"01",X"49",X"6A",X"00",X"10",X"90",X"00",X"B8",X"01",X"49",X"A8",X"00",X"10",X"80",X"00",X"C0", + X"01",X"49",X"E6",X"00",X"10",X"70",X"00",X"C8",X"01",X"4A",X"24",X"00",X"10",X"60",X"00",X"C8", + X"01",X"4A",X"62",X"00",X"10",X"50",X"00",X"C8",X"01",X"4A",X"A0",X"00",X"10",X"40",X"00",X"C8", + X"01",X"4A",X"CE",X"00",X"10",X"38",X"00",X"B0",X"01",X"48",X"CC",X"00",X"10",X"B8",X"10",X"20", + X"01",X"4A",X"CA",X"00",X"10",X"38",X"00",X"B8",X"01",X"48",X"C8",X"00",X"10",X"B8",X"10",X"18", + X"01",X"4A",X"C6",X"00",X"10",X"38",X"00",X"C0",X"01",X"48",X"C4",X"00",X"10",X"B8",X"10",X"10", + X"01",X"4A",X"C2",X"00",X"10",X"38",X"00",X"C8",X"01",X"48",X"C0",X"00",X"10",X"B8",X"10",X"08"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_video.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_video.vhd new file mode 100644 index 00000000..9f7ac60d --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/phoenix_video.vhd @@ -0,0 +1,160 @@ +--------------------------------------------------------------------------------- +-- Phoenix video generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + +entity phoenix_video is +port( + clk11 : in std_logic; + reset : in std_logic; + ce_pix : out std_logic; + hcnt : out std_logic_vector(9 downto 1); + vcnt : out std_logic_vector(8 downto 1); + sync_hs : out std_logic; + sync_vs : out std_logic; + adrsel : out std_logic; + rdy : out std_logic; + vblank : out std_logic; + hblank_frgrd : out std_logic; + hblank_bkgrd : out std_logic +); +end phoenix_video; + +architecture struct of phoenix_video is + signal hclk_i : std_logic := '0'; + signal hstb_i : std_logic := '0'; + signal hcnt_i : unsigned(9 downto 1) := (others=>'0'); + signal vcnt_i : unsigned(9 downto 1) := (others=>'0'); + signal vcnt2 : std_logic_vector(8 downto 1) := (others=>'0'); + signal vblank_n : std_logic := '0'; + + signal rdy1_i : std_logic; + signal rdy2_i : std_logic; + signal j1 : std_logic; + signal k1 : std_logic; + signal q1 : std_logic; + signal j2 : std_logic; + signal k2 : std_logic; + signal q2 : std_logic; + +begin + +-- horizontal counter clock (pixel clock) +process(clk11) begin + if falling_edge(clk11) then + hclk_i <= not hclk_i; + end if; +end process; + +-- horizontal counter from 0x0A0 to 0x1FF : 352 pixels +process(clk11) begin + if rising_edge(clk11) then + if hclk_i = '1' then + if reset = '1' then + hcnt_i <= (others=>'0'); + vcnt_i <= (others=>'0'); + else + hcnt_i <= hcnt_i +1; + if hcnt_i = 511 then + hcnt_i <= to_unsigned(160,9); + vcnt_i <= vcnt_i +1; + if vcnt_i = 261 then + vcnt_i <= to_unsigned(0,9); + end if; + end if; + end if; + end if; + end if; +end process; + +-- vertical counter clock (line clock) = hblank +process(clk11) begin + if rising_edge(clk11) then + if hclk_i = '1' then + if (hcnt_i(3) and hcnt_i(2) and hcnt_i(1)) = '1' then hstb_i <= not hcnt_i(9); end if; + end if; + end if; +end process; + +-- vertical blanking +vblank_n <= + not(vcnt2(8) and vcnt2(7)) + or + ( not + ( not (vcnt2(8) and vcnt2(7) and not vcnt2(6) and not vcnt2(5) and not vcnt2(4)) + and + not (vcnt2(8) and vcnt2(7) and not vcnt2(6) and not vcnt2(5) and vcnt2(4)) + ) +); + +-- ready signal for microprocessor +rdy1_i <= not( not(hcnt_i(9)) and not hcnt_i(7) and hcnt_i(6) and not hcnt_i(5)); +rdy2_i <= not( not(hcnt_i(9)) and hcnt_i(7) and hcnt_i(6) and hcnt_i(5)); + +-- background horizontal blanking +j1 <= hcnt_i(6) and hcnt_i(4); +k1 <= hstb_i; + +process(clk11) begin + if rising_edge(clk11) then + if hclk_i = '1' then + if (j1 xor k1) = '1' then + q1 <= j1; + elsif j1 = '1' then + q1 <= not q1; + else + q1 <= q1; + end if; + end if; + end if; +end process; + +j2 <= not hcnt_i(6) and hcnt_i(5); +k2 <= hcnt_i(8) and hcnt_i(7) and hcnt_i(6) and hcnt_i(4); + +process(clk11) begin + if rising_edge(clk11) then + if hclk_i = '1' then + if (j2 xor k2) = '1' then + q2 <= j2; + elsif j2 = '1' then + q2 <= not q2; + else + q2 <= q2; + end if; + end if; + end if; +end process; + +-- output +ce_pix <= hclk_i; +hcnt <= std_logic_vector(hcnt_i); +vcnt2 <= std_logic_vector(vcnt_i(8 downto 1)) when vcnt_i < 255 else "11111111"; +vcnt <= vcnt2; +--sync <= not(sync1_i xor sync2_i) ; original syncs +rdy <= not(vblank_n and (not (rdy1_i and rdy2_i and not hcnt_i(9)))); +adrsel <= vblank_n and hcnt_i(9); + +vblank <= not vblank_n; +hblank_frgrd <= hstb_i; +hblank_bkgrd <= not(hcnt_i(9) and q1) and not(hcnt_i(9) and (q2)); + +process(clk11) begin + if rising_edge(clk11) then + if hclk_i = '1' then + if hcnt_i = 191 then + sync_hs <= '1'; + if vcnt_i = 230 then sync_vs <= '1'; end if; + if vcnt_i = 237 then sync_vs <= '0'; end if; + end if; + if hcnt_i = 217 then sync_hs <= '0'; end if; + end if; + end if; +end process; + +end struct; diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/pll27.vhd b/Arcade/Custom Hardware/Phoenix_MIST/rtl/pll27.vhd new file mode 100644 index 00000000..d418b79c --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/pll27.vhd @@ -0,0 +1,389 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll27.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll27 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll27; + + +ARCHITECTURE SYN OF pll27 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 88, + clk0_phase_shift => "0", + clk1_divide_by => 27, + clk1_duty_cycle => 50, + clk1_multiply_by => 11, + clk1_phase_shift => "0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll27", + lpm_type => "altpll", + operation_mode => "NO_COMPENSATION", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "ON", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "169715" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "88.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "88" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "88.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll27.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "88" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/scandoubler.v b/Arcade/Custom Hardware/Phoenix_MIST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/Phoenix_MIST/rtl/video_mixer.sv b/Arcade/Custom Hardware/Phoenix_MIST/rtl/video_mixer.sv new file mode 100644 index 00000000..57b24fed --- /dev/null +++ b/Arcade/Custom Hardware/Phoenix_MIST/rtl/video_mixer.sv @@ -0,0 +1,244 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + output osd_enabled, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/README.md b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/README.md new file mode 100644 index 00000000..c6f9a396 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/README.md @@ -0,0 +1,11 @@ +# RiverRaid-Clone-Mist + +A simple RiverRaid Clone(https://habrahabr.ru/post/313092/) + +-Controls Keyboard + +-VGA Only + +-no Joystick (left,right Controls needs a fix) + +-added simple Shooting Sound Effect diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/Release/RiverRaid.rbf b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/Release/RiverRaid.rbf new file mode 100644 index 00000000..d81fa285 Binary files /dev/null and b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/Release/RiverRaid.rbf differ diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/RiverRaid.qpf b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/RiverRaid.qpf new file mode 100644 index 00000000..748fc85c --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/RiverRaid.qpf @@ -0,0 +1,32 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition +# Date created = 10:36:41 October 08, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.0" +DATE = "10:36:41 October 08, 2016" + +# Revisions + +PROJECT_REVISION = "RiverRaid" +PROJECT_REVISION = "RiverRaid" diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/RiverRaid.qsf b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/RiverRaid.qsf new file mode 100644 index 00000000..7f324412 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/RiverRaid.qsf @@ -0,0 +1,191 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 09:49:07 August 24, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RiverRaid_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:26:34 JANUARY 27, 2011" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS OFF +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY RiverRaid +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_blast_fpga) +# --------------------------------------- + + # Analysis & Synthesis Assignments + # ================================ +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + +# end EDA_TOOL_SETTINGS(eda_blast_fpga) +# ------------------------------------- + +# ----------------------- +# start ENTITY(RiverRaid) + + # start LOGICLOCK_REGION(Root Region) + # ----------------------------------- + + # LogicLock Region Assignments + # ============================ +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + + # end LOGICLOCK_REGION(Root Region) + # --------------------------------- + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(RiverRaid) +# --------------------- + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VERILOG_FILE rtl/pll_108.v +set_global_assignment -name VERILOG_FILE rtl/altera_up_ps2_data_in.v +set_global_assignment -name VERILOG_FILE rtl/altera_up_ps2_command_out.v +set_global_assignment -name VERILOG_FILE rtl/RiverRaid.sv +set_global_assignment -name VERILOG_INCLUDE_FILE rtl/defs.vh +set_global_assignment -name VERILOG_FILE rtl/vga_time_generator.v +set_global_assignment -name VERILOG_FILE rtl/sprite_ship.v +set_global_assignment -name VERILOG_FILE rtl/sprite_player.v +set_global_assignment -name VERILOG_FILE rtl/sprite_plane.v +set_global_assignment -name VERILOG_FILE rtl/sprite_helicopter.v +set_global_assignment -name VERILOG_FILE rtl/sprite_fuel.v +set_global_assignment -name VERILOG_FILE rtl/sprite_building.v +set_global_assignment -name VERILOG_FILE rtl/ps2_controller.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/mist/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/mist/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/hq2x.sv +set_global_assignment -name VERILOG_FILE rtl/mist/mist_io.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/clean.bat b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/clean.bat new file mode 100644 index 00000000..c9a2cb06 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/RiverRaid.sv b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/RiverRaid.sv new file mode 100644 index 00000000..2a989dd7 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/RiverRaid.sv @@ -0,0 +1,969 @@ +`include "defs.vh" + + + +`define POINT_IN_BOX(box1, box2)\ +(box1.x >= box2.x) && (box1.x < (box2.x+box2.width)) &&\ +(box1.y >= box2.y) && (box1.y < (box2.y+box2.height)) + +`define Y_CROSSES_BOX(box1, box2)\ +(box1.y >= box2.y) && (box1.y < (box2.y+box2.height)) + + +`define BOX_CROSS(box1, box2)\ +(box1.x < (box2.x+box2.width)) &&\ +(box2.x < (box1.x+box1.width)) &&\ +(box1.y < (box2.y+box2.height)) &&\ +(box2.y < (box1.y+box1.height)) + + + + +typedef struct { + logic [10:0] x; + logic [10:0] y; + logic [10:0] width; + logic [10:0] height; + logic [3:0] exact_x; + logic signed [7:0] movement; + entity_type_t etype; + logic show; + logic [7:0] die_step; +} entity_t; + + +typedef struct { + logic [24:0] scroll_pos; + logic signed [10:0] change_x; +} river_flow_t; + +typedef struct { + logic [24:0] scroll_pos; + entity_type_t etype; + logic [10:0] x; + logic signed [7:0] movement; +} entity_flow_t; + + +typedef struct { + logic [24:0] pos; + logic [24:0] river_addr; // Ð°Ð´Ñ€ÐµÑ Ð² river_flow Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ð¾Ð³Ð¾ + // в данный момент идет прориÑовка реки + logic [10:0] river_x_start; + logic [24:0] island_addr; + logic [10:0] island_x_start; + logic [24:0] entity_addr;// Ð°Ð´Ñ€ÐµÑ Ð² entity_flow Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ð¾Ð³Ð¾ в данный момент + // беретÑÑ Ð¸Ð½Ñ„Ð¾Ñ€Ð¼Ð°Ñ†Ð¸Ñ Ð¿Ð¾ кораблÑм, Ñамолетам, ... +} scroll_t; + + +typedef struct { + bit [(`SPRITE_MISSILE_WIDTH*4)-1:0] missile [0:`SPRITE_MISSILE_HEIGHT-1]; +} sprites_t; + +typedef struct { + logic [31:0] ship_addr; + logic [31:0] plane_addr; + logic [31:0] helicopter_addr; + logic [31:0] building_addr; + logic [31:0] fuel_addr; +} rom_sprites_t; + +typedef struct { + logic [3:0] ship; + logic [3:0] plane; + logic [3:0] helicopter; + logic [3:0] building; + logic [3:0] fuel; + logic [3:0] player; +} rgb_sprites_t; + +typedef struct { + logic [10:0] x; + logic [10:0] y; + logic [10:0] width; + logic [10:0] height; + logic [7:0] die_step; +} box_t; + +typedef struct { + logic [10:0] x; + logic [10:0] missile_x; + logic signed [11:0] missile_y; + logic [7:0] die_step; + logic signed [15:0] fuel; + logic [31:0] sprite_addr; +} player_t; + + +typedef struct { + logic signed [10:0] movement; + logic shot; + logic slow; +} cmd_t; + + +typedef struct { + scroll_t scroll; + river_flow_t river_flow [`RIVER_FLOW_SIZE]; + river_flow_t island_flow [`ISLAND_FLOW_SIZE]; + entity_flow_t entity_flow [`ENTITY_FLOW_SIZE]; + entity_t entities [`ENTITIES_ON_FRAME]; + sprites_t sprites; + rom_sprites_t rom_sprites; + rgb_sprites_t rgb_sprites; + player_t player; + box_t player_box; + box_t missile_box; + cmd_t cmd; + logic play; +} game_t; + + + + +typedef struct { + logic [10:0] x; + logic [10:0] y; + logic rgb_enable; + logic H_SYNC_CLK; + logic V_SYNC_CLK; +} screen_t; + + +`define GET_RGB(sprite, entity)\ +entity.die_step[1]? 4'b000 :\ +(sprite[screen.y-entity.y] >> ((screen.x-entity.x)<<2)) & 4'b1111 + +`define ROM_RGB(sprite_addr, rgb_sprite, shift_width, entity)\ +begin\ + sprite_addr = ((screen.y - entity.y) << shift_width) +\ + (entity.movement <= 0 ? (screen.x - entity.x) : (entity.width - screen.x + entity.x - 1));\ + rgb <= entity.die_step[1]? 4'b000 : rgb_sprite;\ +end + + +module draw_sprites ( + output logic [3:0] rgb, + output rom_sprites_t rom_sprites, + input clk, + input entity_t entities [`ENTITIES_ON_FRAME], + input sprites_t sprites, + input screen_t screen, + input game_t game +); + always @(posedge clk) + begin + for( int i = 0; i <= `ENTITIES_ON_FRAME; i = i + 1 ) + begin + if( i == `ENTITIES_ON_FRAME ) + rgb <= 0; + else if( entities[i].show && `POINT_IN_BOX(screen, entities[i]) ) + begin + case( entities[i].etype ) + SHIP: `ROM_RGB(rom_sprites.ship_addr, game.rgb_sprites.ship, 7, entities[i]) + BUILDING: `ROM_RGB(rom_sprites.building_addr, game.rgb_sprites.building, 6, entities[i]) + PLANE: `ROM_RGB(rom_sprites.plane_addr, game.rgb_sprites.plane, 7, entities[i]) + HELICOPTER: `ROM_RGB(rom_sprites.helicopter_addr, game.rgb_sprites.helicopter, 6, entities[i]) + FUEL: `ROM_RGB(rom_sprites.fuel_addr, game.rgb_sprites.fuel, 6, entities[i]) + BRIDGE: rgb <= entities[i].die_step[1]? 4'b000 : + ((screen.y - entities[i].y) > (`BRIDGE_HEIGHT/2-3) && + (screen.y - entities[i].y) < (`BRIDGE_HEIGHT/2+3)) ? 4'b0110 : 4'b1000; + default: + begin + rgb <= 0; + end + endcase + break; + end + end + end +endmodule + + +module draw_player ( + output logic [3:0] rgb, + output logic [31:0] player_addr, + input clk, + input game_t game, + input screen_t screen +); + box_t fuel_box; + box_t fuel_gauge_box; + + // РиÑка на индикаторе топлива + assign fuel_gauge_box.x = `FUEL_EMPTY_X + game.player.fuel[15:4]; + assign fuel_gauge_box.y = `FUEL_Y + 2; + assign fuel_gauge_box.width = 5; + assign fuel_gauge_box.height = `FUEL_HEIGHT - 4; + + // Индикатор топлива + assign fuel_box.x = `FUEL_EMPTY_X; + assign fuel_box.y = `FUEL_Y; + assign fuel_box.width = `FUEL_WIDTH; + assign fuel_box.height = `FUEL_HEIGHT; + + always @(posedge clk) + begin + if( `POINT_IN_BOX(screen, game.player_box) ) + begin + player_addr = ((screen.y-game.player_box.y) << 6) + (screen.x - game.player_box.x); + rgb <= game.player_box.die_step[1]? 4'b000 : game.rgb_sprites.player; + end + else + begin + player_addr = 0; + if( `POINT_IN_BOX(screen, fuel_gauge_box) ) + rgb <= 4'b0011; + else if( `POINT_IN_BOX(screen, fuel_box) ) + rgb <= 4'b1000; + else + rgb <= 4'b0000; + end + end +endmodule + +module draw_missile ( + output logic [3:0] rgb, + input clk, + input game_t game, + input sprites_t sprites, + input screen_t screen +); + always @(posedge clk) + begin + if( game.missile_box.x && `POINT_IN_BOX(screen, game.missile_box) ) + rgb <= `GET_RGB(sprites.missile, game.missile_box); + else + rgb <= 0; + end +endmodule + + +module play ( + input clk, + input rst, + input screen_t screen, + input game_t game, + input entity_flow_t entity_flow [`ENTITY_FLOW_SIZE], + output wire play_game, + output wire [2:0] rgb, + output scroll_t scroll, + output entity_t entities [`ENTITIES_ON_FRAME], + output player_t player, + output rom_sprites_t rom_sprites +); + wire [10:0] x; + wire [10:0] y; + reg [7:0] line_end; + reg [3:0] step; + reg [3:0] scroll_counter; + reg [31:0] frame_counter; + + reg [10:0] river_x; + reg [10:0] river_x2; + reg [24:0] river_addr; + + reg [10:0] island_x; + reg [24:0] island_addr; + wire [10:0] island_x_left; + wire [10:0] island_x_right; + + reg [7:0] ship_index; + wire [3:0] rgb_sprite; + wire [2:0] rgb_world; + wire [3:0] rgb_player; + wire [3:0] rgb_missile; + wire slow; + + assign x = screen.x; + assign y = screen.y; + assign river_x2 = `SCREEN_MAX_X - river_x; + assign island_x_left = `SCREEN_CENTER_X - island_x; + assign island_x_right = `SCREEN_CENTER_X + island_x; + + assign rgb = rgb_missile ? rgb_missile[2:0] : + rgb_player ? rgb_player[2:0] : + rgb_sprite ? rgb_sprite[2:0] : + rgb_world; + + assign slow = game.cmd.slow && (scroll_counter < `SLOW_SCROLL_SPEED); + + + draw_sprites draw_sprites ( + .rgb ( rgb_sprite ), + .rom_sprites ( rom_sprites ), + .entities ( entities ), + .sprites ( game.sprites ), + .screen ( screen ), + .game ( game ), + .clk ( clk ) + ); + + draw_player draw_player ( + .rgb ( rgb_player ), + .player_addr ( player.sprite_addr ), + .game ( game ), + .screen ( screen ), + .clk ( clk ) + ); + + draw_missile draw_missile ( + .rgb ( rgb_missile ), + .game ( game ), + .sprites ( game.sprites ), + .screen ( screen ), + .clk ( clk ) + ); + + always @(posedge clk) + begin + if( (x == `SCREEN_MAX_X) && (y == `SCREEN_MAX_Y) && (step == 0) ) + begin + step <= 4'h1; + scroll_counter <= '0; + end + case( step ) + 4'h1 : + begin + step <= 4'h2; + if( !play_game ) + begin + play_game <= 1; + scroll.pos <= 0; + scroll.river_addr <= 0; + scroll.river_x_start <= 0; + scroll.island_addr <= 0; + scroll.island_x_start <= 0; + scroll.entity_addr <= 0; + player.die_step <= 0; + player.missile_x <= 0; + player.x <= 0; + player.fuel <= `FUEL_FULL; + for( int i = 0; i < `ENTITIES_ON_FRAME; i = i + 1 ) + entities[i].show <= 0; + end + end + 4'h2 : // ЗакончилаÑÑŒ прориÑовка фрейма + if( frame_counter >= (`SCROLL_EVERY_FRAMES-1) ) + begin + frame_counter <= 0; + if( slow ) + step <= 4'h6; + else + begin + step <= 4'h3; + scroll.pos <= scroll.pos + 'd1; + end + end + else + // ЕÑли надо ничего не делать неÑколько фреймов (очень Ð¼ÐµÐ´Ð»ÐµÐ½Ð½Ð°Ñ Ð¸Ð³Ñ€Ð°) + begin + step <= 4'h8; + frame_counter <= frame_counter + 'd1; + end + 4'h3 : + begin + step <= 4'h4; + // Дошли до точки Ð¸Ð·Ð¼ÐµÐ½ÐµÐ½Ð¸Ñ Ð½Ð°Ð¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ñ€ÐµÐºÐ¸ в river_flow ? + if( scroll.pos >= game.river_flow[scroll.river_addr+1].scroll_pos ) + scroll.river_addr <= scroll.river_addr + 1; + // Изменение Ð½Ð°Ð¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð±ÐµÑ€ÐµÐ³Ð° оÑтрова + if( scroll.pos >= game.island_flow[scroll.island_addr+1].scroll_pos ) + scroll.island_addr <= scroll.island_addr + 1; + // ПоÑвилÑÑ Ð½Ð¾Ð²Ñ‹Ð¹ враг? Сдвинем FIFO объектов, Ñамый Ñтарый выкинем + if( scroll.pos == entity_flow[scroll.entity_addr].scroll_pos ) + entities[1:`ENTITIES_ON_FRAME-1] <= entities[0:`ENTITIES_ON_FRAME-2]; + end + 4'h4 : // ЕÑли на предыдущем шаге поÑвилÑÑ Ð½Ð¾Ð²Ñ‹Ð¹ враг - закинем в FIFO его данные + begin + step <= 4'h5; + if( scroll.pos == entity_flow[scroll.entity_addr].scroll_pos ) + begin + entities[0].show <= 1; + entities[0].x <= entity_flow[scroll.entity_addr].x; + entities[0].exact_x <= 0; + entities[0].y <= 0; + entities[0].etype <= entity_flow[scroll.entity_addr].etype; + entities[0].movement <= entity_flow[scroll.entity_addr].movement; + entities[0].die_step <= 0; + + case( entity_flow[scroll.entity_addr].etype ) + SHIP: + begin + entities[0].width <= `SPRITE_SHIP_WIDTH; + entities[0].height <= `SPRITE_SHIP_HEIGHT; + end + PLANE: + begin + entities[0].width <= `SPRITE_PLANE_WIDTH; + entities[0].height <= `SPRITE_PLANE_HEIGHT; + // Самолеты будут вылетать Ñ ÐºÑ€Ð°Ñ Ñкрана + entities[0].x <= entity_flow[scroll.entity_addr].movement > 0? 0 : `SCREEN_MAX_X; + // Рполе X переназначим на отложенный вылет + entities[0].y <= entity_flow[scroll.entity_addr].x; + end + HELICOPTER: + begin + entities[0].width <= `SPRITE_HELICOPTER_WIDTH; + entities[0].height <= `SPRITE_HELICOPTER_HEIGHT; + end + FUEL: + begin + entities[0].width <= `SPRITE_FUEL_WIDTH; + entities[0].height <= `SPRITE_FUEL_HEIGHT; + end + BRIDGE: + begin + entities[0].x <= scroll.river_x_start + `LAND_START_POS; + entities[0].width <= `SCREEN_MAX_X - scroll.river_x_start - `LAND_START_POS + - scroll.river_x_start - `LAND_START_POS; + entities[0].height <= `BRIDGE_HEIGHT; + end + BUILDING: + begin + entities[0].width <= `SPRITE_BUILDING_WIDTH; + entities[0].height <= `SPRITE_BUILDING_HEIGHT; + end + default: + begin + entities[0].width <= 0; + entities[0].height <= 0; + end + endcase + + scroll.entity_addr <= scroll.entity_addr + 1; + end + end + 4'h5 : + begin + step <= 4'h6; + if( player.fuel > `FUEL_FULL ) + player.fuel <= `FUEL_FULL; + scroll.river_x_start <= scroll.river_x_start + game.river_flow[scroll.river_addr].change_x; + scroll.island_x_start <= scroll.island_x_start + game.island_flow[scroll.island_addr].change_x; + end + 4'h6 : // Перемещение, подбитие, таран врагов + begin + step <= 4'h7; + for( int i = 0; i < `ENTITIES_ON_FRAME; i = i + 1 ) + begin + // Враг ранее был подбит + if( entities[i].die_step ) + // Подержим в таком ÑоÑтоÑнии немного на Ñкране + if( entities[i].die_step == 100 ) + entities[i].show <= 0; + else + begin // Уменьшаем Ñкролинг - получаем Ñффект отлета от ракеты + if( (entities[i].etype == BRIDGE) || scroll_counter[0] ) + entities[i].y <= entities[i].y + 1; + entities[i].die_step <= entities[i].die_step + 1; + end + else if( (entities[i].y < `SCREEN_MAX_Y) && entities[i].show ) + begin + // Ракета попала в объект + if( `BOX_CROSS(game.missile_box, entities[i]) ) + begin + entities[i].die_step <= 1; + player.missile_x <= 0; + end + // Игрок врезалÑÑ Ð² объект + else if( `BOX_CROSS(game.player_box, entities[i]) ) + begin + if( entities[i].etype == FUEL ) + begin + player.fuel <= player.fuel + `FUEL_UP_SPEED; + entities[i].y <= entities[i].y + 1; + end + else + begin + // ЕÑли игрок уже погиб, не менÑем Ð²Ñ€ÐµÐ¼Ñ Ð´Ð¾ реÑтарта + if( !player.die_step ) + player.die_step <= 1; + entities[i].die_step <= 1; + end + end + else if( !slow ) + entities[i].y <= entities[i].y + 1; + end + else + entities[i].show <= 0; + + // Перемещение = movement/16 пикÑелей на фрейм, Ñ‚.е можно < 1 + {entities[i].x, entities[i].exact_x} <= + {entities[i].x, entities[i].exact_x} + 15'(signed'(entities[i].movement)); + end + end + 4'h7 : // ВозвращаемÑÑ Ð½Ð° шаг 1 еÑли нужно Ñделать неÑколько Ñкроллингов за 1 фрейм + begin + if( (scroll.pos < `SCREEN_MAX_Y) && (scroll_counter < `START_SCROLL_SPEED) ) + begin + scroll_counter <= scroll_counter + 4'd1; + step <= 4'h1; + end + else if( scroll_counter < `FRAME_EVERY_SCROLLS ) + begin + scroll_counter <= scroll_counter + 4'd1; + step <= 4'h1; + end + else + step <= 4'h8; + end + 4'h8 : + begin + step <= 4'h9; + // Перемещение игрока + if( !player.die_step ) + player.x <= player.x + game.cmd.movement; + // Уменьшение топлива. Уменьшаем Ñ Ð¾Ð±Ñ‹Ñ‡Ð½Ð¾Ð¹ ÑкороÑтью вÑегда, чтобы не замедлÑли полет поÑтоÑнно + player.fuel <= player.fuel - `FUEL_DOWN_SPEED; + end + 4'h9 : + begin + step <= 4'ha; + // Ð’Ñ‹Ñтрел игрока + if( game.cmd.shot && (player.missile_y < `REMISSILE_Y_POS) ) + begin + player.missile_x <= game.player_box.x + `PLAYER_WIDTH/2 - `SPRITE_MISSILE_WIDTH/2; + player.missile_y <= `MISSILE_Y_START; + end + else if( player.missile_y > 0 ) + player.missile_y <= player.missile_y - `MISSILE_SPEED; + else + player.missile_x <= 0; + // ЗакончилоÑÑŒ топливо + if( (player.fuel <= 0) && !(player.die_step) ) + begin + player.fuel <= 0; + player.die_step <= 1; + end + end + 4'ha : // Стартовые Ð·Ð½Ð°Ñ‡ÐµÐ½Ð¸Ñ Ð´Ð»Ñ Ð¿Ñ€Ð¾Ñ€Ð¸Ñовки фрейма + begin + step <= 4'hb; + river_x <= scroll.river_x_start + `LAND_START_POS; + river_addr <= scroll.river_addr; + island_x <= scroll.island_x_start; + island_addr <= scroll.island_addr; + end + 4'hb : + begin + step <= 4'hc; + if( player.die_step ) + begin + if( player.die_step == 60 ) + begin + play_game <= 0; + end + else + player.die_step <= player.die_step + 1; + end + end + default: + begin + if( x == 0 ) + step <= 4'h0; + if( (x == `SCREEN_MAX_X) && (line_end == 0) ) + line_end <= 8'd1; + case ( line_end ) + 8'd1 : + begin + line_end <= 8'd2; + if( (y < `SCREEN_MAX_Y) && (scroll.pos >= y) ) + begin + if( (scroll.pos - y) < game.river_flow[river_addr].scroll_pos ) + river_addr <= river_addr - 1; + if( (scroll.pos - y) < game.island_flow[island_addr].scroll_pos ) + island_addr <= island_addr - 1; + end + end + 8'd2: + begin + line_end <= 8'd3; + if( (river_addr >= 0) && (y < `SCREEN_MAX_Y)) + river_x <= river_x - game.river_flow[river_addr].change_x; + if( (island_addr >= 0) && (y < `SCREEN_MAX_Y)) + island_x <= island_x - game.island_flow[island_addr].change_x; + end + 8'd3: // Ð˜Ð½Ð´ÐµÐºÑ ÐºÐ¾Ñ€Ð°Ð±Ð»Ñ Ð¿Ð¾ текущему Y чтобы на Ñледующем шаге проверÑÑ‚ÑŒ доплытие до берега + // Это Ñкономней чем делать вÑе в цикле, но добавлÑетÑÑ Ð¾Ð³Ñ€Ð°Ð½Ð¸Ñ‡ÐµÐ½Ð¸Ðµ: 1 корабль на одной позиции Y + begin + for( int i = 0; i <= `ENTITIES_ON_FRAME; i = i + 1 ) + if( i == `ENTITIES_ON_FRAME ) + begin + //ship_index <= 0; + line_end <= 8'd6; + end + else if( `Y_CROSSES_BOX(screen, entities[i]) && ( + (entities[i].etype == SHIP) || + (entities[i].etype == HELICOPTER) + )) + begin + ship_index <= i; + line_end <= 8'd4; + break; + end + end + 8'd4: // Корабль доплыл до берега? + begin + if( entities[ship_index].x < (river_x + `SAND_WIDTH) ) + begin + entities[ship_index].x <= river_x + `SAND_WIDTH; + line_end <= 8'd5; + end + else if( (entities[ship_index].x + entities[ship_index].width) > (river_x2 - `SAND_WIDTH) ) + begin + entities[ship_index].x <= river_x2 - `SAND_WIDTH - entities[ship_index].width; + line_end <= 8'd5; + end + else + line_end <= 8'd6; + end + 8'd5: // Корабль доплыл до берега. Изменим направление + begin + line_end <= 8'd6; + entities[ship_index].movement <= -entities[ship_index].movement; + end + 8'd6: // Игрок врезалÑÑ Ð² берег или оÑтров? + begin + line_end <= 8'd7; + if( + (!player.die_step) && + `Y_CROSSES_BOX(screen, game.player_box) && + ( + (game.player_box.x <= river_x) || + ((game.player_box.x + game.player_box.width) > river_x2) || + ( + island_x && + (game.player_box.x >= island_x_left) && + ((game.player_box.x + game.player_box.width) < island_x_right) + ) + ) + ) + player.die_step <= 1; + // Ракета попала в берег или оÑтров? + if( + `Y_CROSSES_BOX(screen, game.missile_box) && + ( + (game.missile_box.x <= river_x) || + ((game.missile_box.x + game.missile_box.width) > river_x2) || + ( + island_x && + (game.missile_box.x >= island_x_left) && + ((game.missile_box.x + game.missile_box.width) < island_x_right) + ) + ) + ) + player.missile_x <= 0; + end + default: + begin + if( x == 0 ) + line_end <= 3'd0; + if( scroll.pos > y ) + rgb_world <= + (x < river_x) ? `LAND_COLOR : + (x < (river_x + `SAND_WIDTH)) ? `SAND_COLOR : + (x < island_x_left) ? `RIVER_COLOR : + (x < island_x_right) ? `LAND_COLOR : + (x < (river_x2 - `SAND_WIDTH)) ? `RIVER_COLOR : + (x >= river_x2) ? `LAND_COLOR : `SAND_COLOR ; + else + rgb_world <= `TRANSPARENT_COLOR; + end + endcase + end + endcase + end +endmodule + + +module init ( + input clk, + input rst, + output river_flow_t river_flow [`RIVER_FLOW_SIZE], + output river_flow_t island_flow [`ISLAND_FLOW_SIZE], + output entity_flow_t entity_flow [`ENTITY_FLOW_SIZE], + output sprites_t sprites +); + always @(posedge clk) + if( !rst ) + begin + river_flow <= `RIVER_FLOW; + island_flow <= `ISLAND_FLOW; + entity_flow <= `ENTITY_FLOW; + sprites.missile <= `MISSILE_SPRITE; + end +endmodule + +module RiverRaid ( + input CLOCK_27, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output LED, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0 +); + +`include "rtl\build_id.v" + + localparam CONF_STR = { + "River Raid;;", + "O23,Scandoubler Fx,None,CRT 25%,CRT 50%;", + //"T5,Reset;", + "V,v0.1.",`BUILD_DATE +}; + + game_t game; + screen_t screen; + wire clk; + wire clk_pix; + wire rst = status[0] | status[5] |buttons[1]; + wire [2:0] cur_rgb; + + logic [7:0] ps2_received_data; + logic ps2_received_data_en; + logic ps2_key_up_action; + + wire HSync = screen.H_SYNC_CLK; + wire VSync = screen.V_SYNC_CLK; + wire r = screen.rgb_enable? cur_rgb[0] : 1'b0; + wire g = screen.rgb_enable? cur_rgb[1] : 1'b0; + wire b = screen.rgb_enable? cur_rgb[2] : 1'b0; + wire [2:0] VGA_BO ={r,r,r}; + wire [2:0] VGA_GO ={g,g,g}; + wire [2:0] VGA_RO ={b,b,b}; + assign game.player_box.x = game.player.x + `PLAYER_START_X; + assign game.player_box.y = `PLAYER_Y; + assign game.player_box.width = `PLAYER_WIDTH; + assign game.player_box.height = `PLAYER_HEIGHT; + assign game.player_box.die_step = game.player.die_step; + + assign game.missile_box.x = game.player.missile_x; + assign game.missile_box.y = game.player.missile_y[10:0]; + assign game.missile_box.width = `SPRITE_MISSILE_WIDTH; + assign game.missile_box.height = `SPRITE_MISSILE_HEIGHT; + + wire scandoubler_disable; + wire ypbpr; + wire ps2_kbd_clk, ps2_kbd_data; + wire [31:0] status; + wire [1:0] buttons; + wire [1:0] switches; + wire [7:0] joyA; + wire [7:0] joyB; + wire [7:0] kbd_joy; + wire vga_clk; + + assign LED = 1'b1; + + mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys(clk), + .conf_str(CONF_STR), + .CONF_DATA0(CONF_DATA0), + .SPI_SCK(SPI_SCK), + .SPI_SS2(SPI_SS2), + .SPI_DO(SPI_DO), + .SPI_DI(SPI_DI), + .scandoubler_disable(scandoubler_disable), + .status(status), + .buttons(buttons), + .switches(switches), + .joystick_0(joyA), + .joystick_1(joyB), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .ypbpr(ypbpr) +); + +video_mixer #(.LINE_LENGTH(1024), .HALF_DEPTH(1)) video_mixer +( + .*, + .clk_sys(clk), + .ce_pix(vga_clk), + .ce_pix_actual(vga_clk), + .scanlines({status[3:2] == 2, status[3:2] == 1}), + .scandoubler_disable(1), + .ypbpr(ypbpr), + .ypbpr_full(1), + .line_start(0), + .mono(0), + .hq2x(), + .R(VGA_RO), + .G(VGA_GO), + .B(VGA_BO) +); + + pll_108 pll_108 ( + .inclk0 ( CLOCK_27 ), + .c0 ( vga_clk ), + .c1 ( clk ), + .areset ( rst ) + ); + + vga_time_generator vga_time_generator ( + .clk ( vga_clk ), + .reset_n ( 1 ), + .h_disp ( `H_DISP ), + .h_fporch ( `H_FPORCH ), + .h_sync ( `H_SYNC ), + .h_bporch ( `H_BPORCH ), + + .v_disp ( `V_DISP ), + .v_fporch ( `V_FPORCH ), + .v_sync ( `V_SYNC ), + .v_bporch ( `V_BPORCH ), + .hs_polarity ( 1'b0 ), + .vs_polarity ( 1'b0 ), + .frame_interlaced ( 1'b0 ), + + .vga_hs ( screen.H_SYNC_CLK ), + .vga_vs ( screen.V_SYNC_CLK ), + .vga_de ( screen.rgb_enable ), + .pixel_x ( screen.x ), + .pixel_y ( screen.y ) + ); + + sprite_ship sprite_ship ( + .clock ( vga_clk ), + .address ( game.rom_sprites.ship_addr ), + .q ( game.rgb_sprites.ship ) + ); + + sprite_plane sprite_plane ( + .clock ( vga_clk ), + .address ( game.rom_sprites.plane_addr ), + .q ( game.rgb_sprites.plane ) + ); + + sprite_helicopter sprite_helicopter ( + .clock ( vga_clk ), + .address ( game.rom_sprites.helicopter_addr ), + .q ( game.rgb_sprites.helicopter ) + ); + + + sprite_building sprite_building ( + .clock ( vga_clk ), + .address ( game.rom_sprites.building_addr ), + .q ( game.rgb_sprites.building ) + ); + + sprite_fuel sprite_fuel ( + .clock ( vga_clk ), + .address ( game.rom_sprites.fuel_addr ), + .q ( game.rgb_sprites.fuel ) + ); + + sprite_player sprite_player ( + .clock ( vga_clk ), + .address ( game.player.sprite_addr ), + .q ( game.rgb_sprites.player ) + ); + + play play ( + .clk ( vga_clk ), + .rst ( rst ), + .rgb ( cur_rgb ), + .screen ( screen ), + .game ( game ), + .scroll ( game.scroll ), + .entity_flow ( game.entity_flow ), + .entities ( game.entities ), + .rom_sprites ( game.rom_sprites ), + .player ( game.player ), + .play_game ( game.play ) + ); + + + init init ( + .clk ( vga_clk ), + .rst ( rst ), + .river_flow ( game.river_flow ), + .island_flow ( game.island_flow ), + .entity_flow ( game.entity_flow ), + .sprites ( game.sprites ) + ); +//will be removed fix Keyboard module down below + PS2_Controller ps2( + .CLOCK_50 ( clk ), + .reset ( 0 ), + .PS2_CLK ( ps2_kbd_clk ), + .PS2_DAT ( ps2_kbd_data ), + .received_data ( ps2_received_data ), + .received_data_en ( ps2_received_data_en ) + ); + + // Inaccurate + /* keyboard keyboard + ( + .clk(clk), + .reset(0), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbd_joy), + .code( ps2_received_data ), + .input_strobe( ps2_received_data_en ) + );*/ + + +//Joystick +/* always @(posedge clk) + begin + game.cmd.shot = kbd_joy[0] | joyA[4] |joyB[4]; + game.cmd.slow = kbd_joy[5] | joyA[2] |joyB[2]; +// this will not work +// if (kbd_joy[6])// | joyA[1] |joyB[1]) +// if( game.cmd.movement < 0 ) game.cmd.movement <= 0; else game.cmd.movement <= -`PLAYER_SPEED; +// if (kbd_joy[7])// | joyA[3] |joyB[3]) +// if( game.cmd.movement > 0 ) game.cmd.movement <= 0; else game.cmd.movement <= +`PLAYER_SPEED; + end*/ + + //will be remooved +reg [15:0] counter; + always @(posedge ps2_received_data_en) + begin + + if( ps2_received_data == 8'hF0 ) + ps2_key_up_action <= 1; + else begin + ps2_key_up_action <=0; + if( ps2_key_up_action ) + case( ps2_received_data ) + 8'h6B : if( game.cmd.movement < 0 ) game.cmd.movement <= 0;//left + 8'h74 : if( game.cmd.movement > 0 ) game.cmd.movement <= 0;//right + 8'h29 : game.cmd.shot <= 0;//Fire + 8'h72 : game.cmd.slow <= 0;//down + endcase + else begin + case( ps2_received_data ) + 8'h6B : game.cmd.movement <= -`PLAYER_SPEED; + 8'h74 : game.cmd.movement <= `PLAYER_SPEED; + 8'h29 : game.cmd.shot <= 1; + 8'h72 : game.cmd.slow <= 1; + endcase + end + end + + end + + always @(posedge clk) + if (game.cmd.shot==1) + if(counter==56817) counter <= 0; + else counter <= counter+1; + + assign AUDIO_L = counter[15]; + assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/altera_up_ps2_command_out.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/altera_up_ps2_command_out.v new file mode 100644 index 00000000..66b12093 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/altera_up_ps2_command_out.v @@ -0,0 +1,303 @@ +/***************************************************************************** + * * + * Module: Altera_UP_PS2_Command_Out * + * Description: * + * This module sends commands out to the PS2 core. * + * * + *****************************************************************************/ + + +module Altera_UP_PS2_Command_Out ( + // Inputs + clk, + reset, + + the_command, + send_command, + + ps2_clk_posedge, + ps2_clk_negedge, + + // Bidirectionals + PS2_CLK, + PS2_DAT, + + // Outputs + command_was_sent, + error_communication_timed_out +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +// Timing info for initiating Host-to-Device communication +// when using a 50MHz system clock +parameter CLOCK_CYCLES_FOR_101US = 5050; +parameter NUMBER_OF_BITS_FOR_101US = 13; +parameter COUNTER_INCREMENT_FOR_101US = 13'h0001; + +//parameter CLOCK_CYCLES_FOR_101US = 50; +//parameter NUMBER_OF_BITS_FOR_101US = 6; +//parameter COUNTER_INCREMENT_FOR_101US = 6'h01; + +// Timing info for start of transmission error +// when using a 50MHz system clock +parameter CLOCK_CYCLES_FOR_15MS = 750000; +parameter NUMBER_OF_BITS_FOR_15MS = 20; +parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001; + +// Timing info for sending data error +// when using a 50MHz system clock +parameter CLOCK_CYCLES_FOR_2MS = 100000; +parameter NUMBER_OF_BITS_FOR_2MS = 17; +parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001; + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input [7:0] the_command; +input send_command; + +input ps2_clk_posedge; +input ps2_clk_negedge; + +// Bidirectionals +inout PS2_CLK; +inout PS2_DAT; + +// Outputs +output reg command_was_sent; +output reg error_communication_timed_out; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ +// states +parameter PS2_STATE_0_IDLE = 3'h0, + PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1, + PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2, + PS2_STATE_3_TRANSMIT_DATA = 3'h3, + PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4, + PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5, + PS2_STATE_6_COMMAND_WAS_SENT = 3'h6, + PS2_STATE_7_TRANSMISSION_ERROR = 3'h7; + +/***************************************************************************** + * Internal wires and registers Declarations * + *****************************************************************************/ +// Internal Wires + +// Internal Registers +reg [3:0] cur_bit; +reg [8:0] ps2_command; + +reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter; + +reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter; +reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter; + +// State Machine Registers +reg [2:0] ns_ps2_transmitter; +reg [2:0] s_ps2_transmitter; + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset == 1'b1) + s_ps2_transmitter <= PS2_STATE_0_IDLE; + else + s_ps2_transmitter <= ns_ps2_transmitter; +end + +always @(*) +begin + // Defaults + ns_ps2_transmitter = PS2_STATE_0_IDLE; + + case (s_ps2_transmitter) + PS2_STATE_0_IDLE: + begin + if (send_command == 1'b1) + ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION; + else + ns_ps2_transmitter = PS2_STATE_0_IDLE; + end + PS2_STATE_1_INITIATE_COMMUNICATION: + begin + if (command_initiate_counter == CLOCK_CYCLES_FOR_101US) + ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK; + else + ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION; + end + PS2_STATE_2_WAIT_FOR_CLOCK: + begin + if (ps2_clk_negedge == 1'b1) + ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA; + else if (waiting_counter == CLOCK_CYCLES_FOR_15MS) + ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR; + else + ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK; + end + PS2_STATE_3_TRANSMIT_DATA: + begin + if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1)) + ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT; + else if (transfer_counter == CLOCK_CYCLES_FOR_2MS) + ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR; + else + ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA; + end + PS2_STATE_4_TRANSMIT_STOP_BIT: + begin + if (ps2_clk_negedge == 1'b1) + ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT; + else if (transfer_counter == CLOCK_CYCLES_FOR_2MS) + ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR; + else + ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT; + end + PS2_STATE_5_RECEIVE_ACK_BIT: + begin + if (ps2_clk_posedge == 1'b1) + ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT; + else if (transfer_counter == CLOCK_CYCLES_FOR_2MS) + ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR; + else + ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT; + end + PS2_STATE_6_COMMAND_WAS_SENT: + begin + if (send_command == 1'b0) + ns_ps2_transmitter = PS2_STATE_0_IDLE; + else + ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT; + end + PS2_STATE_7_TRANSMISSION_ERROR: + begin + if (send_command == 1'b0) + ns_ps2_transmitter = PS2_STATE_0_IDLE; + else + ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR; + end + default: + begin + ns_ps2_transmitter = PS2_STATE_0_IDLE; + end + endcase +end + +/***************************************************************************** + * Sequential logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset == 1'b1) + ps2_command <= 9'h000; + else if (s_ps2_transmitter == PS2_STATE_0_IDLE) + ps2_command <= {(^the_command) ^ 1'b1, the_command}; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}}; + else if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) && + (command_initiate_counter != CLOCK_CYCLES_FOR_101US)) + command_initiate_counter <= + command_initiate_counter + COUNTER_INCREMENT_FOR_101US; + else if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION) + command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}}; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}}; + else if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) && + (waiting_counter != CLOCK_CYCLES_FOR_15MS)) + waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS; + else if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK) + waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}}; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}}; + else + begin + if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) || + (s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) || + (s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT)) + begin + if (transfer_counter != CLOCK_CYCLES_FOR_2MS) + transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS; + end + else + transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}}; + end +end + +always @(posedge clk) +begin + if (reset == 1'b1) + cur_bit <= 4'h0; + else if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) && + (ps2_clk_negedge == 1'b1)) + cur_bit <= cur_bit + 4'h1; + else if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA) + cur_bit <= 4'h0; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + command_was_sent <= 1'b0; + else if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT) + command_was_sent <= 1'b1; + else if (send_command == 1'b0) + command_was_sent <= 1'b0; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + error_communication_timed_out <= 1'b0; + else if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR) + error_communication_timed_out <= 1'b1; + else if (send_command == 1'b0) + error_communication_timed_out <= 1'b0; +end + +/***************************************************************************** + * Combinational logic * + *****************************************************************************/ + +assign PS2_CLK = + (s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ? + 1'b0 : + 1'bz; + +assign PS2_DAT = + (s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] : + (s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 : + ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) && + (command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 : + 1'bz; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +endmodule + diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/altera_up_ps2_data_in.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/altera_up_ps2_data_in.v new file mode 100644 index 00000000..f2c57556 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/altera_up_ps2_data_in.v @@ -0,0 +1,198 @@ +/***************************************************************************** + * * + * Module: Altera_UP_PS2_Data_In * + * Description: * + * This module accepts incoming data from a PS2 core. * + * * + *****************************************************************************/ + + +module Altera_UP_PS2_Data_In ( + // Inputs + clk, + reset, + + wait_for_incoming_data, + start_receiving_data, + + ps2_clk_posedge, + ps2_clk_negedge, + ps2_data, + + // Bidirectionals + + // Outputs + received_data, + received_data_en // If 1 - new data has been received +); + + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input wait_for_incoming_data; +input start_receiving_data; + +input ps2_clk_posedge; +input ps2_clk_negedge; +input ps2_data; + +// Bidirectionals + +// Outputs +output reg [7:0] received_data; + +output reg received_data_en; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ +// states +localparam PS2_STATE_0_IDLE = 3'h0, + PS2_STATE_1_WAIT_FOR_DATA = 3'h1, + PS2_STATE_2_DATA_IN = 3'h2, + PS2_STATE_3_PARITY_IN = 3'h3, + PS2_STATE_4_STOP_IN = 3'h4; + +/***************************************************************************** + * Internal wires and registers Declarations * + *****************************************************************************/ +// Internal Wires +reg [3:0] data_count; +reg [7:0] data_shift_reg; + +// State Machine Registers +reg [2:0] ns_ps2_receiver; +reg [2:0] s_ps2_receiver; + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset == 1'b1) + s_ps2_receiver <= PS2_STATE_0_IDLE; + else + s_ps2_receiver <= ns_ps2_receiver; +end + +always @(*) +begin + // Defaults + ns_ps2_receiver = PS2_STATE_0_IDLE; + + case (s_ps2_receiver) + PS2_STATE_0_IDLE: + begin + if ((wait_for_incoming_data == 1'b1) && + (received_data_en == 1'b0)) + ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA; + else if ((start_receiving_data == 1'b1) && + (received_data_en == 1'b0)) + ns_ps2_receiver = PS2_STATE_2_DATA_IN; + else + ns_ps2_receiver = PS2_STATE_0_IDLE; + end + PS2_STATE_1_WAIT_FOR_DATA: + begin + if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1)) + ns_ps2_receiver = PS2_STATE_2_DATA_IN; + else if (wait_for_incoming_data == 1'b0) + ns_ps2_receiver = PS2_STATE_0_IDLE; + else + ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA; + end + PS2_STATE_2_DATA_IN: + begin + if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1)) + ns_ps2_receiver = PS2_STATE_3_PARITY_IN; + else + ns_ps2_receiver = PS2_STATE_2_DATA_IN; + end + PS2_STATE_3_PARITY_IN: + begin + if (ps2_clk_posedge == 1'b1) + ns_ps2_receiver = PS2_STATE_4_STOP_IN; + else + ns_ps2_receiver = PS2_STATE_3_PARITY_IN; + end + PS2_STATE_4_STOP_IN: + begin + if (ps2_clk_posedge == 1'b1) + ns_ps2_receiver = PS2_STATE_0_IDLE; + else + ns_ps2_receiver = PS2_STATE_4_STOP_IN; + end + default: + begin + ns_ps2_receiver = PS2_STATE_0_IDLE; + end + endcase +end + +/***************************************************************************** + * Sequential logic * + *****************************************************************************/ + + +always @(posedge clk) +begin + if (reset == 1'b1) + data_count <= 3'h0; + else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) && + (ps2_clk_posedge == 1'b1)) + data_count <= data_count + 3'h1; + else if (s_ps2_receiver != PS2_STATE_2_DATA_IN) + data_count <= 3'h0; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + data_shift_reg <= 8'h00; + else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) && + (ps2_clk_posedge == 1'b1)) + data_shift_reg <= {ps2_data, data_shift_reg[7:1]}; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + received_data <= 8'h00; + else if (s_ps2_receiver == PS2_STATE_4_STOP_IN) + received_data <= data_shift_reg; +end + +always @(posedge clk) +begin + if (reset == 1'b1) + received_data_en <= 1'b0; + else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) && + (ps2_clk_posedge == 1'b1)) + received_data_en <= 1'b1; + else + received_data_en <= 1'b0; +end + +/***************************************************************************** + * Combinational logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +endmodule + diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/build_id.tcl b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/build_id.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/build_id.v new file mode 100644 index 00000000..a966c8e6 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "061557" diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/defs.vh b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/defs.vh new file mode 100644 index 00000000..c62125e2 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/defs.vh @@ -0,0 +1,288 @@ +`ifndef RIVERRAID_DEFS +`define RIVERRAID_DEFS + +// КоличеÑтво объектов в маÑÑиве берегов, оÑтровов и врагов +// Ð’Ñ‹ÑтавлÑÑ‚ÑŒ ÑоответÑтвенно кол-ву Ñлементов в RIVER_FLOW, ISLAND_FLOW и ENTITY_FLOW +`define RIVER_FLOW_SIZE 66 +`define ISLAND_FLOW_SIZE 24 +`define ENTITY_FLOW_SIZE 47 + +// Format PixelClock ActiveVideo FrontPorch SyncPulse BackPorch ActiveVideo FrontPorch SyncPulse BackPorch +// 1024x768,60Hz 65.000 1024 24 136 160 768 3 6 29 +// Параметры Ð´Ð»Ñ VGA генератора +//`define H_DISP 1024 +//`define H_FPORCH 24 +//`define H_SYNC 136 +//`define H_BPORCH 160 +//`define V_DISP 768 +//`define V_FPORCH 3 +//`define V_SYNC 6 +//`define V_BPORCH 29 +//`define SCREEN_WIDTH 11'd1024 +//`define SCREEN_HEIGHT 11'd768 + +//1280x1024 +`define H_DISP 1280 +`define H_FPORCH 48 +`define H_SYNC 112 +`define H_BPORCH 248 +`define V_DISP 1024 +`define V_FPORCH 1 +`define V_SYNC 3 +`define V_BPORCH 38 +`define SCREEN_WIDTH 11'd1280 +`define SCREEN_HEIGHT 11'd1024 + +`define SCREEN_MAX_X (`SCREEN_WIDTH - 1) +`define SCREEN_MAX_Y (`SCREEN_HEIGHT - 1) +`define SCREEN_CENTER_X (`SCREEN_WIDTH/2 - 1) + +// СкороÑÑ‚ÑŒ Ñкролинга. За 1 прориÑовку Ñкрана будет Ñкролинг на +// (FRAME_EVERY_SCROLLS / SCROLL_EVERY_FRAMES) пикÑелей +`define FRAME_EVERY_SCROLLS 4 +`define SCROLL_EVERY_FRAMES 1 +// СкороÑÑ‚ÑŒ Ñкролинга когда игрок замедлÑет полет +`define SLOW_SCROLL_SPEED (`FRAME_EVERY_SCROLLS/2) +// СкороÑÑ‚ÑŒ Ñкролинга в начале раунда +`define START_SCROLL_SPEED 8 + +// МакÑимальное одновременное количеÑтво врагов и домов на Ñкране +`define ENTITIES_ON_FRAME 10 +// Ширина и выÑота Ñпрайта "корабль" +`define SPRITE_SHIP_WIDTH 128 +`define SPRITE_SHIP_HEIGHT 28 +// Ширина и выÑота Ñпрайта "Ñамолет" +`define SPRITE_PLANE_WIDTH 128 +`define SPRITE_PLANE_HEIGHT 31 +// Ширина и выÑота Ñпрайта "вертолет" +`define SPRITE_HELICOPTER_WIDTH 64 +`define SPRITE_HELICOPTER_HEIGHT 26 +// Ширина и выÑота Ñпрайта "Ñтроение" +`define SPRITE_BUILDING_WIDTH 64 +`define SPRITE_BUILDING_HEIGHT 107 + +`define SPRITE_FUEL_WIDTH 64 +`define SPRITE_FUEL_HEIGHT 122 + +`define BRIDGE_HEIGHT 80 + +// Ширина и выÑота выпущенной ракеты +`define SPRITE_MISSILE_WIDTH 5 +`define SPRITE_MISSILE_HEIGHT 22 +`define MISSILE_SPEED 20 +`define MISSILE_Y_START (`PLAYER_Y - `SPRITE_MISSILE_HEIGHT) +// Ðа какое раÑÑтоÑние должна отлететь ракета чтобы можно было выпуÑтить новую +`define REMISSILE_DISTANCE 300 +`define REMISSILE_Y_POS (`PLAYER_Y - `SPRITE_MISSILE_HEIGHT - `REMISSILE_DISTANCE) + +// Ширина берега в пикÑелÑÑ… +`define SAND_WIDTH 11'd7 +`define TRANSPARENT_COLOR 3'b000 +`define LAND_START_POS 11'd200 +`define LAND_COLOR 3'b010 +`define SAND_COLOR 3'b110 +`define RIVER_COLOR 3'b001 + +`define PLAYER_WIDTH 64 +`define PLAYER_HEIGHT 86 +`define PLAYER_START_X 640 +`define PLAYER_Y 895 +`define PLAYER_SPEED 7 + +// Ширина датчика топлива +`define FUEL_WIDTH 250 +`define FUEL_HEIGHT 24 +`define FUEL_Y 1000 +`define FUEL_EMPTY_X (`SCREEN_WIDTH - `FUEL_WIDTH)/ 2 +// СкороÑÑ‚ÑŒ траты топлива +`define FUEL_DOWN_SPEED 3 +`define FUEL_UP_SPEED 9 +// 1 пикÑель индикатора топлива = 16 единицам топлива +`define FUEL_FULL (`FUEL_WIDTH * 16) + + + +typedef enum { + NONE, + SHIP, + PLANE, + HELICOPTER, + BRIDGE, + FUEL, + BUILDING +} entity_type_t; + + +`define RIVER_FLOW '{\ + '{'d0, 'd0 },\ + '{'d600, 'd1 },\ + '{'d620, 'd4 },\ + '{'d650, 'd0 },\ + '{'d900, 'd1 },\ + '{'d910, 'd2 },\ + '{'d955, 'd0 },\ + '{'d1060, -'d1 },\ + '{'d1120, -'d2 },\ + '{'d1150, -'d4 },\ + '{'d1170, -'d3 },\ + '{'d1210, 'd0 },\ + '{'d1820, 'd2 },\ + '{'d1840, 'd0 },\ + '{'d1910, 'd1 },\ + '{'d1930, 'd0 },\ + '{'d2070, 'd1 },\ + '{'d2090, 'd5 },\ + '{'d2130, 'd2 },\ + '{'d2160, 'd0 },\ + '{'d2260, -'d2 },\ + '{'d2310, -'d1 },\ + '{'d2370, 'd0 },\ + '{'d2880, 'd1 },\ + '{'d2900, 'd2 },\ + '{'d2940, 'd1 },\ + '{'d2960, 'd2 },\ + '{'d2976, 'd0 },\ + '{'d3280, -'d1 },\ + '{'d3290, -'d14 },\ + '{'d3294, 'd0 },\ + '{'d3640, 'd12 },\ + '{'d3648, 'd0 },\ + '{'d4500, -'d3 },\ + '{'d4580, 'd0 },\ + '{'d5300, 'd1 },\ + '{'d5320, 'd3 },\ + '{'d5340, 'd1 },\ + '{'d5370, 'd0 },\ + '{'d5700, 'd2 },\ + '{'d5720, 'd0 },\ + '{'d5820, 'd2 },\ + '{'d5840, 'd0 },\ + '{'d5900, 'd2 },\ + '{'d5920, 'd0 },\ + '{'d6500, 'd2 },\ + '{'d6546, 'd0 },\ + '{'d7100, -'d4 },\ + '{'d7240, 'd0 },\ + '{'d9000, 'd4 },\ + '{'d9138, 'd0 },\ + '{'d10000, -'d1 },\ + '{'d10030, -'d6 },\ + '{'d10060, 'd0 },\ + '{'d10300, -'d1 },\ + '{'d10310, -'d2 },\ + '{'d10320, 'd0 },\ + '{'d11000, 'd1 },\ + '{'d11010, 'd2 },\ + '{'d11020, 'd3 },\ + '{'d11040, 'd0 },\ + '{'d11050, -'d3 },\ + '{'d11060, -'d2 },\ + '{'d11070, -'d1 },\ + '{'d11080, 'd0 },\ + '{24'hffffff, 'd0 }\ +} + +`define ISLAND_FLOW '{\ + '{'d0, 'd0 },\ + '{'d1420, 'd4 },\ + '{'d1470, 'd2 },\ + '{'d1510, 'd1 },\ + '{'d1546, 'd0 },\ + '{'d1750, -'d1 },\ + '{'d1770, -'d2 },\ + '{'d1820, -'d4 },\ + '{'d1860, 'd0 },\ + '{'d1866, -'d4 },\ + '{'d1875, 'd0 },\ + '{'d2500, 'd3 },\ + '{'d2520, 'd0 },\ + '{'d2600, -'d3 },\ + '{'d2620, 'd0 },\ + '{'d5400, 'd8 },\ + '{'d5420, 'd0 },\ + '{'d5500, -'d2 },\ + '{'d5520, 'd0 },\ + '{'d5600, -'d2 },\ + '{'d5620, 'd0 },\ + '{'d5700, -'d4 },\ + '{'d5720, 'd0 },\ + '{'d9000000, 'd0 }\ +} + +`define ENTITY_FLOW '{\ + '{'d530, SHIP, 'd460, 'd2 },\ + '{'d630, SHIP, 'd880, 'd0 },\ + '{'d750, BUILDING, 'd220, 'd0 },\ + '{'d840, HELICOPTER, 'd790, -'d2 },\ + '{'d1100, SHIP, 'd630, 'd9 },\ + '{'d1450, SHIP, 'd810, 'd1 },\ + '{'d1525, BUILDING, 'd610, 'd0 },\ + '{'d1755, PLANE, 'd50, 'd16 },\ + '{'d2050, SHIP, 'd700, 'd3 },\ + '{'d2250, BRIDGE, 'd0, 'd0 },\ + '{'d2590, FUEL, 'd430, 'd0 },\ + '{'d3030, SHIP, 'd610, 'd8 },\ + '{'d3240, BUILDING, 'd1020, 'd0 },\ + '{'d3250, SHIP, 'd700, 'd4 },\ + '{'d3450, SHIP, 'd900, -'d6 },\ + '{'d3580, SHIP, 'd300, -'d5 },\ + '{'d3600, PLANE, 'd50, -'d10 },\ + '{'d3710, SHIP, 'd660, 'd6 },\ + '{'d3930, FUEL, 'd600, 'd0 },\ + '{'d4450, BRIDGE, 'd0, 'd0 },\ + '{'d4455, BUILDING, 'd400, 'd0 },\ + '{'d4470, PLANE, 'd615, 'd20 },\ + '{'d4630, SHIP, 'd620, 'd16 },\ + '{'d4730, HELICOPTER, 'd620, 'd18 },\ + '{'d4860, SHIP, 'd620, 'd22 },\ + '{'d5050, HELICOPTER, 'd620, 'd26 },\ + '{'d5580, FUEL, 'd820, 'd0 },\ + '{'d5581, FUEL, 'd400, 'd0 },\ + '{'d5815, BRIDGE, 'd0, 'd0 },\ + '{'d6010, PLANE, 'd510, -'d20 },\ + '{'d6060, SHIP, 'd580, 'd0 },\ + '{'d6870, PLANE, 'd410, -'d16 },\ + '{'d7010, BUILDING, 'd720, 'd0 },\ + '{'d7030, BUILDING, 'd780, 'd0 },\ + '{'d7300, PLANE, 'd0, 'd10 },\ + '{'d7350, PLANE, 'd0, -'d10 },\ + '{'d7420, SHIP, 'd60, 'd9 },\ + '{'d7600, SHIP, 'd600, 'd0 },\ + '{'d7800, SHIP, 'd950, 'd0 },\ + '{'d8090, SHIP, 'd350, 'd0 },\ + '{'d8270, HELICOPTER, 'd200, -'d12 },\ + '{'d8460, HELICOPTER, 'd900, 'd12 },\ + '{'d8650, FUEL, 'd100, 'd0 },\ + '{'d9400, FUEL, 'd610, 'd0 },\ + '{'d9500, HELICOPTER, 'd580, 'd0 },\ + '{'d9560, HELICOPTER, 'd630, 'd0 },\ + '{'d10500, SHIP, 'd420, -'d32 }\ +} + + +`define MISSILE_SPRITE '{\ + 20'h00700,\ + 20'h07770,\ + 20'h87770,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h07770,\ + 20'h07770,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h77777,\ + 20'h74447,\ + 20'h74447,\ + 20'h04440,\ + 20'h04440\ +} + +`endif \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/hq2x.sv b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/keyboard.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/keyboard.v new file mode 100644 index 00000000..a9a03f56 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/keyboard.v @@ -0,0 +1,83 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + output [7:0] code, + output input_strobe, + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +//reg [7:0] code; +//reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/mist_io.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/mist_io.v new file mode 100644 index 00000000..ab9ef8ad --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/mist_io.v @@ -0,0 +1,532 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // ARM -> FPGA download + input ioctl_force_erase, + output reg ioctl_download = 0, // signal indicating an active download + output reg ioctl_erasing = 0, // signal indicating an active erase + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr = 0, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + case(ioctl_index) + 0: addr <= 'h080000; // BOOT ROM + 'h01: addr <= 'h000100; // ROM file + 'h41: addr <= 'h000100; // COM file + 'h81: addr <= 'h000000; // C00 file + 'hC1: addr <= 'h010000; // EDD file + default: addr <= 'h100000; // FDD file + endcase + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +reg [24:0] erase_mask; +wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask; + +always@(posedge clk_sys) begin + reg rclkD, rclkD2; + reg old_force = 0; + reg [5:0] erase_clk_div; + reg [24:0] end_addr; + reg erase_trigger = 0; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wr <= 0; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wr <= 1; + end + + if(ioctl_download) begin + old_force <= 0; + ioctl_erasing <= 0; + erase_trigger <= (ioctl_index == 1); + end else begin + + old_force <= ioctl_force_erase; + + // start erasing + if(erase_trigger) begin + erase_trigger <= 0; + erase_mask <= 'hFFFF; + end_addr <= 'h0100; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if((ioctl_force_erase & ~old_force)) begin + erase_trigger <= 0; + ioctl_addr <= 'h1FFFFFF; + erase_mask <= 'h1FFFFFF; + end_addr <= 'h0050000; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if(ioctl_erasing) begin + erase_clk_div <= erase_clk_div + 1'd1; + if(!erase_clk_div) begin + if(next_erase == end_addr) ioctl_erasing <= 0; + else begin + ioctl_addr <= next_erase; + ioctl_dout <= 0; + ioctl_wr <= 1; + end + end + end + end +end + +endmodule \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/osd.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/scandoubler.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/scandoubler.v new file mode 100644 index 00000000..9414a959 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/sigma_delta_dac.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/sigma_delta_dac.v new file mode 100644 index 00000000..bba2c552 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=7) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= 1; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= ~SigmaLatch[MSBI+2]; + end +end + +endmodule diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/video_mixer.sv b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/video_mixer.sv new file mode 100644 index 00000000..d7d79263 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/mist/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd7, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/pll_108.qip b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/pll_108.qip new file mode 100644 index 00000000..a91d3991 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/pll_108.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_108.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_108.ppf"] diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/pll_108.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/pll_108.v new file mode 100644 index 00000000..dbab9989 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/pll_108.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_108.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_108 ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 4, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 2, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_108", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "40" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "54.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "77" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "54.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_108.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_108_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/ps2_controller.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/ps2_controller.v new file mode 100644 index 00000000..46abe825 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/ps2_controller.v @@ -0,0 +1,269 @@ +/***************************************************************************** + * * + * Module: Altera_UP_PS2 * + * Description: * + * This module communicates with the PS2 core. * + * * + *****************************************************************************/ + +module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) ( + // Inputs + CLOCK_50, + reset, + + the_command, + send_command, + + // Bidirectionals + PS2_CLK, // PS2 Clock + PS2_DAT, // PS2 Data + + // Outputs + command_was_sent, + error_communication_timed_out, + + received_data, + received_data_en // If 1 - new data has been received +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input CLOCK_50; +input reset; + +input [7:0] the_command; +input send_command; + +// Bidirectionals +inout PS2_CLK; +inout PS2_DAT; + +// Outputs +output command_was_sent; +output error_communication_timed_out; + +output [7:0] received_data; +output received_data_en; + +wire [7:0] the_command_w; +wire send_command_w, command_was_sent_w, error_communication_timed_out_w; + +generate + if(INITIALIZE_MOUSE) begin + assign the_command_w = init_done ? the_command : 8'hf4; + assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w); + assign command_was_sent = init_done ? command_was_sent_w : 0; + assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1; + + reg init_done; + + always @(posedge CLOCK_50) + if(reset) init_done <= 0; + else if(command_was_sent_w) init_done <= 1; + + end else begin + assign the_command_w = the_command; + assign send_command_w = send_command; + assign command_was_sent = command_was_sent_w; + assign error_communication_timed_out = error_communication_timed_out_w; + end +endgenerate + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ +// states +localparam PS2_STATE_0_IDLE = 3'h0, + PS2_STATE_1_DATA_IN = 3'h1, + PS2_STATE_2_COMMAND_OUT = 3'h2, + PS2_STATE_3_END_TRANSFER = 3'h3, + PS2_STATE_4_END_DELAYED = 3'h4; + +/***************************************************************************** + * Internal wires and registers Declarations * + *****************************************************************************/ +// Internal Wires +wire ps2_clk_posedge; +wire ps2_clk_negedge; + +wire start_receiving_data; +wire wait_for_incoming_data; + +// Internal Registers +reg [7:0] idle_counter; + +reg ps2_clk_reg; +reg ps2_data_reg; +reg last_ps2_clk; + +// State Machine Registers +reg [2:0] ns_ps2_transceiver; +reg [2:0] s_ps2_transceiver; + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + +always @(posedge CLOCK_50) +begin + if (reset == 1'b1) + s_ps2_transceiver <= PS2_STATE_0_IDLE; + else + s_ps2_transceiver <= ns_ps2_transceiver; +end + +always @(*) +begin + // Defaults + ns_ps2_transceiver = PS2_STATE_0_IDLE; + + case (s_ps2_transceiver) + PS2_STATE_0_IDLE: + begin + if ((idle_counter == 8'hFF) && + (send_command == 1'b1)) + ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT; + else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1)) + ns_ps2_transceiver = PS2_STATE_1_DATA_IN; + else + ns_ps2_transceiver = PS2_STATE_0_IDLE; + end + PS2_STATE_1_DATA_IN: + begin + if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/) + ns_ps2_transceiver = PS2_STATE_0_IDLE; + else + ns_ps2_transceiver = PS2_STATE_1_DATA_IN; + end + PS2_STATE_2_COMMAND_OUT: + begin + if ((command_was_sent == 1'b1) || + (error_communication_timed_out == 1'b1)) + ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER; + else + ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT; + end + PS2_STATE_3_END_TRANSFER: + begin + if (send_command == 1'b0) + ns_ps2_transceiver = PS2_STATE_0_IDLE; + else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1)) + ns_ps2_transceiver = PS2_STATE_4_END_DELAYED; + else + ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER; + end + PS2_STATE_4_END_DELAYED: + begin + if (received_data_en == 1'b1) + begin + if (send_command == 1'b0) + ns_ps2_transceiver = PS2_STATE_0_IDLE; + else + ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER; + end + else + ns_ps2_transceiver = PS2_STATE_4_END_DELAYED; + end + default: + ns_ps2_transceiver = PS2_STATE_0_IDLE; + endcase +end + +/***************************************************************************** + * Sequential logic * + *****************************************************************************/ + +always @(posedge CLOCK_50) +begin + if (reset == 1'b1) + begin + last_ps2_clk <= 1'b1; + ps2_clk_reg <= 1'b1; + + ps2_data_reg <= 1'b1; + end + else + begin + last_ps2_clk <= ps2_clk_reg; + ps2_clk_reg <= PS2_CLK; + + ps2_data_reg <= PS2_DAT; + end +end + +always @(posedge CLOCK_50) +begin + if (reset == 1'b1) + idle_counter <= 6'h00; + else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) && + (idle_counter != 8'hFF)) + idle_counter <= idle_counter + 6'h01; + else if (s_ps2_transceiver != PS2_STATE_0_IDLE) + idle_counter <= 6'h00; +end + +/***************************************************************************** + * Combinational logic * + *****************************************************************************/ + +assign ps2_clk_posedge = + ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0; +assign ps2_clk_negedge = + ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0; + +assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN); +assign wait_for_incoming_data = + (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER); + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +Altera_UP_PS2_Data_In PS2_Data_In ( + // Inputs + .clk (CLOCK_50), + .reset (reset), + + .wait_for_incoming_data (wait_for_incoming_data), + .start_receiving_data (start_receiving_data), + + .ps2_clk_posedge (ps2_clk_posedge), + .ps2_clk_negedge (ps2_clk_negedge), + .ps2_data (ps2_data_reg), + + // Bidirectionals + + // Outputs + .received_data (received_data), + .received_data_en (received_data_en) +); + +Altera_UP_PS2_Command_Out PS2_Command_Out ( + // Inputs + .clk (CLOCK_50), + .reset (reset), + + .the_command (the_command_w), + .send_command (send_command_w), + + .ps2_clk_posedge (ps2_clk_posedge), + .ps2_clk_negedge (ps2_clk_negedge), + + // Bidirectionals + .PS2_CLK (PS2_CLK), + .PS2_DAT (PS2_DAT), + + // Outputs + .command_was_sent (command_was_sent_w), + .error_communication_timed_out (error_communication_timed_out_w) +); + +endmodule + diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_building.mif b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_building.mif new file mode 100644 index 00000000..279f6f6d --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_building.mif @@ -0,0 +1,6858 @@ +WIDTH=4; +DEPTH=8000; + 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: 0; + 6839 : 0; + 6840 : 0; + 6841 : 0; + 6842 : 0; + 6843 : 0; + 6844 : 0; + 6845 : 0; + 6846 : 0; + 6847 : 0; + [6848..7999] : 0; +END; \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_building.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_building.v new file mode 100644 index 00000000..cb26b386 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_building.v @@ -0,0 +1,161 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: sprite_building.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sprite_building ( + address, + clock, + q); + + input [12:0] address; + input clock; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({4{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sprite_building.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8000, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sprite_building.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8000" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sprite_building.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8000" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_building.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_building.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_building.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_building.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_building_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_building_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_fuel.mif b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_fuel.mif new file mode 100644 index 00000000..708dd137 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_fuel.mif @@ -0,0 +1,7818 @@ +WIDTH=4; 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+END; \ No newline at end of file diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_fuel.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_fuel.v new file mode 100644 index 00000000..e978f066 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_fuel.v @@ -0,0 +1,161 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: sprite_fuel.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sprite_fuel ( + address, + clock, + q); + + input [12:0] address; + input clock; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({4{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sprite_fuel.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8000, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sprite_fuel.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8000" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sprite_fuel.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8000" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_fuel.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_fuel.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_fuel.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_fuel.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_fuel_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_fuel_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_helicopter.mif b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_helicopter.mif new file mode 100644 index 00000000..78c73e96 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_helicopter.mif @@ -0,0 +1,1674 @@ +WIDTH=4; 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DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sprite_helicopter ( + address, + clock, + q); + + input [10:0] address; + input clock; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({4{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sprite_helicopter.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2000, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 11, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sprite_helicopter.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2000" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sprite_helicopter.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2000" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_helicopter.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_helicopter.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_helicopter.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_helicopter.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_helicopter_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_helicopter_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_plane.mif b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_plane.mif new file mode 100644 index 00000000..e397a81c --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_plane.mif @@ -0,0 +1,3978 @@ +WIDTH=4; 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DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sprite_plane ( + address, + clock, + q); + + input [11:0] address; + input clock; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({4{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sprite_plane.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4000, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sprite_plane.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4000" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sprite_plane.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4000" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_plane.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_plane.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_plane.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_plane.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_plane_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_plane_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_player.mif b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_player.mif new file mode 100644 index 00000000..391e11b0 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_player.mif @@ -0,0 +1,5514 @@ +WIDTH=4; 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DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sprite_player ( + address, + clock, + q); + + input [12:0] address; + input clock; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({4{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sprite_player.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 5600, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sprite_player.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "5600" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sprite_player.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "5600" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_player.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_player.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_player.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_player.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_player_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_player_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_ship.mif b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_ship.mif new file mode 100644 index 00000000..56f7696a --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/sprite_ship.mif @@ -0,0 +1,3595 @@ +WIDTH=4; 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DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module sprite_ship ( + address, + clock, + q); + + input [12:0] address; + input clock; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({4{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sprite_ship.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8000, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.ram_block_type = "M9K", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sprite_ship.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8000" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sprite_ship.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8000" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ship.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ship.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ship.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ship.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ship_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL sprite_ship_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/vga_time_generator.v b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/vga_time_generator.v new file mode 100644 index 00000000..b8c42ac9 --- /dev/null +++ b/Arcade/Custom Hardware/RiverRaid_MiST(Clone)/rtl/vga_time_generator.v @@ -0,0 +1,358 @@ +// ============================================================================ +// Copyright (c) 2012 by Terasic Technologies Inc. +// ============================================================================ +// +// Permission: +// +// Terasic grants permission to use and modify this code for use +// in synthesis for all Terasic Development Boards and Altera Development +// Kits made by Terasic. Other use of this code, including the selling +// ,duplication, or modification of any portion is strictly prohibited. +// +// Disclaimer: +// +// This VHDL/Verilog or C/C++ source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Terasic provides no warranty regarding the use +// or functionality of this code. +// +// ============================================================================ +// +// Terasic Technologies Inc +// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan +// +// +// +// web: http://www.terasic.com/ +// email: support@terasic.com +// +// ============================================================================ + +/* + +Horizonal Timing +A (us) Scanline +B (us) Sync pulse +C (us) Back porchch +D (us) Active video +E (us) Front porcch +E+B+C = blanking + + ______________________ _________ +________| VIDEO |________| VIDEO (next line) + |-C-|----------D-----------|-E-| +__ _______________________________ ___________ + |_| |_| + |B| + |---------------A-----------------| + + +Vertical Timing +O (ms) Total frame +P (ms) Sync length +Q (ms) Back porch +R (ms) Active video +S (ms) Front porch + ______________________ ________ +________| VIDEO |________| VIDEO (next fram + |-Q-|----------R-----------|-S-| +__ ______________________________ ___________ + |_| |_| + |P| + |---------------O----------------| + + +VGA 640x480@60Hz + +Reference: +http://www.epanorama.net/documents/pc/vga_timing.html + +"VGA industry standard" 640x480 pixel mode + +example: 640x480@60 +General characteristics +Clock frequency 25.175 MHz +Line frequency 31469 Hz +Field frequency 59.94 Hz + +One line + 8 pixels front porch + 96 pixels horizontal sync + 40 pixels back porch + 8 pixels left border +640 pixels video + 8 pixels right border +--- +800 pixels total per line + +One field + 2 lines front porch + 2 lines vertical sync + 25 lines back porch + 8 lines top border +480 lines video + 8 lines bottom border +--- +525 lines total per field + +Other details +Sync polarity: H negative, V negative +Scan type: non interlaced. + + + +*/ + +module vga_time_generator( + + clk, + reset_n, + + h_disp, + h_fporch, + h_sync, + h_bporch, + + v_disp, + v_fporch, + v_sync, + v_bporch, + + hs_polarity, + vs_polarity, + frame_interlaced, + + vga_hs, + vga_vs, + vga_de, + + pixel_i_odd_frame, + pixel_x, + pixel_y + + +); + +//////////////////////////////////////////////// +/////// Port Declare +//////////////////////////////////////////////// +input clk; +input reset_n; + +input [11:0] h_disp; +input [11:0] h_fporch; +input [11:0] h_sync; +input [11:0] h_bporch; + +input [11:0] v_disp; +input [11:0] v_fporch; +input [11:0] v_sync; +input [11:0] v_bporch; + +input hs_polarity; +input vs_polarity; +input frame_interlaced; + +output reg vga_hs; +output reg vga_vs; +output vga_de; + +output reg pixel_i_odd_frame; +output reg [11:0] pixel_x; +output reg [11:0] pixel_y; + + + + +//////////////////////////////////////////////// +///////h sync//////// +//////////////////////////////////////////////// +//h total sum// +reg [11:0] h_total; +reg [11:0] h_total_half; +reg [11:0] h_pixel_start; +reg [11:0] h_pixel_end; +reg h_sync_polarity; +reg vga_h_de; + +wire h_de; +wire [11:0] h_valid_pixel_count; +wire h_last_pixel; +assign h_de = (h_counter >= h_pixel_start && h_counter < h_pixel_end)?1'b1:1'b0; +assign h_valid_pixel_count = h_counter - h_pixel_start; +assign h_last_pixel = (h_counter+1 == h_total)?1'b1:1'b0; + + +//h counter gen // +reg [11:0]h_counter; +reg [11:0] h_cur_disp; + + +// H_Sync, H_Blank Generator, +always @(posedge clk or negedge reset_n) +begin + if (!reset_n) + begin + h_counter <= 12'h000; + vga_hs <= hs_polarity?1'b1:1'b0; + vga_h_de <= 1'b0; + pixel_x <= 12'hfff; + h_cur_disp <= 0; + end + else if (h_cur_disp != h_disp) + begin + h_cur_disp <= h_disp; + // + h_total <= h_disp+h_fporch+h_sync+h_bporch; + h_total_half <= (h_disp+h_fporch+h_sync+h_bporch ) >> 1; + h_pixel_start <= h_sync+h_bporch; + h_pixel_end <= h_sync+h_bporch+h_disp; + h_sync_polarity <= hs_polarity; + // + h_counter <= 12'h000; + vga_hs <= hs_polarity?1'b1:1'b0; + vga_h_de <= 1'b0; + pixel_x <= 12'hfff; + end + else + begin + // h_counter + if (!h_last_pixel) + h_counter <= h_counter+1'b1; + else + h_counter <= 0; + + // h sync generator + if (h_counter < h_sync) + vga_hs <= h_sync_polarity?1'b1:1'b0; + else + vga_hs <= h_sync_polarity?1'b0:1'b1; + + // de + pixel_x <= (h_de)?h_valid_pixel_count:12'hfff; + vga_h_de <= h_de; + + end +end + + +//////////////////////////////////////////////// +/////v sync///// +//////////////////////////////////////////////// +//v total sum// +reg vga_v_de; +reg [11:0]v_total; +reg [11:0]v_pixel_start; +reg [11:0]v_pixel_end; +reg v_sync_polarity; +reg v_interlaced; +reg gen_field1_sync; +reg f0_to_f1; + +wire [11:0] v_field_total; +wire [11:0] v_field_disp; +wire [11:0] v_valid_line_count; +wire v_de; +assign v_de = (v_counter >= v_pixel_start && v_counter < v_pixel_end)?1'b1:1'b0; +assign v_valid_line_count = v_counter - v_pixel_start; +assign v_field_disp = (frame_interlaced)?(v_disp >> 1):v_disp; +assign v_field_total = v_sync+v_bporch+v_field_disp+v_fporch; + +//v counter gen +reg [11:0] v_counter; +reg [11:0] v_cur_disp; + +// H_Sync, H_Blank Generator, +always @(posedge clk or negedge reset_n) +begin + if (!reset_n) + begin + v_counter <= 12'h000; + vga_vs <= vs_polarity?1'b1:1'b0; + vga_v_de <= 1'b0; + pixel_y <= 12'hfff; + pixel_i_odd_frame <= 1'b0; + v_cur_disp <= 0; + end + else if (v_cur_disp != v_disp) + begin + v_cur_disp <= v_disp; + // + v_pixel_start <= v_sync+v_bporch; + v_pixel_end <= v_sync+v_bporch+v_field_disp; + v_total <= v_field_total;// + frame_interlaced; + v_sync_polarity <= vs_polarity; + v_interlaced <= frame_interlaced; + f0_to_f1 <= 1'b0; + // + v_counter <= 12'h000; + vga_vs <= vs_polarity?1'b1:1'b0; + vga_v_de <= 1'b0; + pixel_y <= 12'hfff; + pixel_i_odd_frame <= 1'b0; + end + else if (h_counter == 0 && f0_to_f1) + f0_to_f1 <= 1'b0; // line between field0 and filed1 + else if (h_counter == h_total_half && (f0_to_f1 || pixel_i_odd_frame)) + begin // generate sync for filed1 + // v sync generator + if (f0_to_f1) + pixel_i_odd_frame <= 1'b1; + else + begin + if (v_counter < v_sync) // v_counter, 0,1,2,3.... + vga_vs <= v_sync_polarity?1'b1:1'b0; + else + vga_vs <= v_sync_polarity?1'b0:1'b1; + end + end + else if (h_counter == 0) + begin + // v_counter + if (v_counter+1 < v_total) + v_counter <= v_counter+1'b1; + else + begin + v_counter <= 0; + // + if (v_interlaced) + begin + if (pixel_i_odd_frame) + pixel_i_odd_frame <= 1'b0; + else + f0_to_f1 <= 1'b1; + end + end + + // v sync generator + if (!pixel_i_odd_frame) + begin + if (v_counter < v_sync) + vga_vs <= v_sync_polarity?1'b1:1'b0; + else + vga_vs <= v_sync_polarity?1'b0:1'b1; + end + + // blank + vga_v_de <= v_de; + if (!v_de) + pixel_y <= 12'hfff; + else if (!v_interlaced) + pixel_y <= v_valid_line_count; + else if (pixel_i_odd_frame) + pixel_y <= (v_valid_line_count << 1) + 1; // odd frame, 1, 3, 5, ... + else + pixel_y <= v_valid_line_count << 1; // even frame, 0, 2, 4, ... + + end +end + +//sync timing output// + + +assign vga_de = vga_h_de & vga_v_de; + + +endmodule diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/README.txt b/Arcade/Data East Cassette/Burger_Time_MiST/README.txt new file mode 100644 index 00000000..59aadefd --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/README.txt @@ -0,0 +1,246 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Burger Time for MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- Copyright (c) DAR - Dez 2017 +-- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/burger_time/ +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE : Pepper +-- LALT : +-- ARROW KEYS : Movement +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + +--------------------------------------------------------------------------------- +-- Burger Time by Dar (darfpga@aol.fr) (27/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burger_time_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +-- +-- Main features : +-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection) +-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection) +-- +-- Uses 1 pll for 12MHz generation from 50MHz +-- +-- Board key : +-- 0 : reset game +-- +-- Keyboard players inputs : +-- +-- F3 : Add coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : pepper +-- RIGHT arrow : move right +-- LEFT arrow : move left +-- UP arrow : move up +-- DOWN arrow : move down +-- +-- Other details : see burger_time.vhd +-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite +--------------------------------------------------------------------------------- +-- Use burger_time_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok +-- No external RAM/SDRAM required + +-- Use with MAME roms from btime.zip +-- +-- Use make_burger_time_proms.bat to build vhd file from binaries + +-- Burger Time Hardware caracteristics : +-- +-- VIDEO : 1x6502@750kHz CPU accessing its program rom, working ram, +-- foreground and sprite data ram, I/O, sound board register and trigger. +-- 16Kx8bits program rom +-- 2Kb8bits working ram +-- +-- One char 8x8 tile map 32x30 + sprites data +-- 1Kx8bits + 1Kx2bits +-- 3x8Kx8bits graphics rom 3bits/pixel +-- 8 colors with ram palette +-- +-- 8 sprites 16*16 with priorities and flip H/V +-- use char graphics rom and colors +-- +-- Char/sprites 8 colors among 256 colors +-- 8bits 3red/3green/2blue +-- +-- Sprites buffer rams 3x256bits +-- +-- Background static tile map with scroll +-- 2K*8bits tile map rom +-- 3x2K*8bits graphics rom 3bits/pixel +-- 8 colors with ram palette +-- 16x16 tiles +-- +-- SOUND : 1x6502@500kHz CPU accessing its program rom, working ram, 2x-AY3-8910, +-- command registers, triggers. +-- 2Kx8bits working ram +-- 4Kx8bits program rom +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- Pass band active filter on channel A of AY#2 +-- ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Wed Dec 27 10:02:23 2017 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; burger_time_de10_lite ; +; Top-level Entity Name ; burger_time_de10_lite ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 3,540 / 49,760 ( 7 % ) ; +; Total combinational functions ; 3,382 / 49,760 ( 7 % ) ; +; Dedicated logic registers ; 1,090 / 49,760 ( 2 % ) ; +; Total registers ; 1090 ; +; Total pins ; 105 / 360 ( 29 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 465,792 / 1,677,312 ( 28 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + +--------------- +VHDL File list +--------------- + +max10_pll_12M.vhd Pll 12MHz and 14 MHz from 50MHz altera mf + +rtl_dar/burger_time_de10_lite.vhd Top level for de10_lite board + +rtl_dar/burger_time.vhd Main video board logic +rtl_dar/burger_time_sound.vhd Main sound board logic + +rtl_mikej/YM2149_linmix_sep.vhd Copyright (c) MikeJ - Jan 2005 + +t65/T65.vhd Copyright (c) MikeJ - Jan 2005t65/T65_Pack.vhdt65/T65_MCode.vhdt65/T65_ALU.vhd +rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input +rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) +rtl_dar/decodeur_7_seg.vhd 7 segments display decoder + +burger_time_prog.vhd Burger Time video board PROMs +fg_sp_graphx_3.vhd +fg_sp_graphx_2.vhd +fg_sp_graphx_1.vhd +bg_map.vhd +bg_graphx_3.vhd +bg_graphx_2.vhd +bg_graphx_1.vhd + +burger_time_sound_prog.vhd Burger Time sound board PROM + +---------------------- +Quartus project files +---------------------- +de10_lite/burger_time_de10_lite.sdc Timequest constraints file +de10_lite/burger_time_de10_lite.qsf de10_lite settings (files,pins...) +de10_lite/burger_time_de10_lite.qpf de10_lite project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 15 ROMs binary files from btime.zip (MAME) + +aa04.9b, aa06.13b, aa05.10b, aa07.15b +aa12.7k, ab13.9k +ab10.10k, ab11.12k +aa8.13k, ab9.15k +ab00.1b +ab01.3b +ab02.4b +ab03.6b +ab14.12h + +------ +Tools +------ +You need to build vhdl files from the binary file : + - Unzip the roms file in the tools/burger_time_unzip directory + - Double click (execute) the script tools/make_burger_time_proms.bat to get the following files + +burger_time_prog.vhd : aa04.9b + aa06.13b + aa05.10b + aa07.15b +fg_sp_graphx_1.vhd : aa12.7k + ab13.9k +fg_sp_graphx_2.vhd : ab10.10k + ab11.12k +fg_sp_graphx_3.vhd : aa8.13k + ab9.15k +bg_graphx_1.vhd : ab00.1b +bg_graphx_2.vhd : ab01.3b +bg_graphx_3.vhd : ab02.4b +bg_map.vhd : ab03.6b +burger_time_sound_prog.vhd : ab14.12h + +*DO NOT REDISTRIBUTE THESE FILES* + +VHDL files are needed to compile and include roms into the project + +The script make_burger_time_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c is also delivered. + +--------------------------------- +Compiling for de10_lite +--------------------------------- +You can build the project with ROM image embeded in the sof file. +*DO NOT REDISTRIBUTE THESE FILES* + +3 steps + + - put the VHDL ROM files (.vhd) into the rtl_dar directory + - build burger_time_de10_lite + - program burger_time_de10_lite.sof + +------------------------ +------------------------ +End of file +------------------------ diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/Release/burger_time_mist.rbf b/Arcade/Data East Cassette/Burger_Time_MiST/Release/burger_time_mist.rbf new file mode 100644 index 00000000..092f9af3 Binary files /dev/null and b/Arcade/Data East Cassette/Burger_Time_MiST/Release/burger_time_mist.rbf differ diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/burger_time_mist.qpf b/Arcade/Data East Cassette/Burger_Time_MiST/burger_time_mist.qpf new file mode 100644 index 00000000..233545f9 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/burger_time_mist.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 21:51:49 December 06, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "21:51:49 December 06, 2017" + +# Revisions + +PROJECT_REVISION = "burger_time_mist" diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/burger_time_mist.qsf b/Arcade/Data East Cassette/Burger_Time_MiST/burger_time_mist.qsf new file mode 100644 index 00000000..8a687e0b --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/burger_time_mist.qsf @@ -0,0 +1,176 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:52:55 December 26, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# burnin_rubber_mist_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY burger_time_mist +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------------------- +# start ENTITY(burnin_rubber_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(burnin_rubber_mist) +# ------------------------------ +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name SYSTEMVERILOG_FILE rtl/burger_time_mist.sv +set_global_assignment -name VHDL_FILE rtl/burger_time.vhd +set_global_assignment -name VHDL_FILE "rtl/burger_time _sound.vhd" +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/fg_sp_graphx_3.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/fg_sp_graphx_2.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/fg_sp_graphx_1.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/burger_time_sound_prog.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/burger_time_prog.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/bg_map.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/bg_graphx_3.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/bg_graphx_2.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/bg_graphx_1.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/clean.bat b/Arcade/Data East Cassette/Burger_Time_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_1.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_1.vhd new file mode 100644 index 00000000..12ded815 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_1.vhd @@ -0,0 +1,143 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_graphx_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_graphx_1 is + type rom is array(0 to 1935) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",X"AA",X"AA",X"AA", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"8A",X"8A",X"8A",X"8A",X"8A", + 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X"FE",X"92",X"FE",X"00",X"FE",X"82",X"FE",X"00",X"FE",X"82",X"FE",X"00",X"FE",X"82",X"FE",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"02",X"FE",X"00",X"FE",X"92",X"F6",X"00",X"FE",X"82",X"FE",X"82",X"FE",X"82",X"FE",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_2.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_2.vhd new file mode 100644 index 00000000..6eb2514b --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_2.vhd @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_graphx_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_graphx_2 is + type rom is array(0 to 447) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"60", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"60",X"60",X"60",X"60",X"60",X"60",X"60", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_3.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_3.vhd new file mode 100644 index 00000000..f7b1ad2f --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_graphx_3.vhd @@ -0,0 +1,143 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_graphx_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_graphx_3 is + type rom is array(0 to 1935) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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Cassette/Burger_Time_MiST/rtl/Roms/bg_map.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_map.vhd new file mode 100644 index 00000000..2c98fc15 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/bg_map.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_map is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_map is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"01",X"0B",X"09",X"0A",X"0B",X"09",X"0A",X"0B",X"09",X"0A",X"0B",X"09",X"0A",X"02",X"00", + X"00",X"05",X"06",X"00",X"05",X"06",X"07",X"05",X"06",X"00",X"05",X"06",X"00",X"05",X"06",X"00", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/burger_time_prog.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/burger_time_prog.vhd new file mode 100644 index 00000000..96b584de --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/burger_time_prog.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity burger_time_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of burger_time_prog is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"4C",X"3C",X"CF",X"4C",X"0F",X"C0",X"85",X"F5",X"EA",X"4C",X"03",X"B0",X"85",X"F5",X"EA",X"78", + X"D8",X"A2",X"FF",X"9A",X"AD",X"03",X"40",X"29",X"10",X"F0",X"EE",X"A9",X"00",X"85",X"01",X"85", + X"F9",X"8D",X"00",X"40",X"20",X"32",X"C3",X"20",X"1D",X"C3",X"A9",X"01",X"85",X"01",X"A9",X"00", + X"85",X"1A",X"20",X"0D",X"C7",X"85",X"F7",X"EA",X"A9",X"FE",X"8D",X"05",X"50",X"A9",X"00",X"8D", + X"02",X"40",X"85",X"1B",X"85",X"20",X"A9",X"00",X"85",X"1C",X"20",X"16",X"C4",X"A2",X"FF",X"20", + X"2C",X"CA",X"20",X"D9",X"C3",X"A2",X"FF",X"20",X"2C",X"CA",X"20",X"78",X"C4",X"A2",X"3F",X"20", + X"2C",X"CA",X"20",X"61",X"C5",X"85",X"F5",X"EA",X"20",X"0D",X"C7",X"20",X"48",X"C7",X"A9",X"01", + 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Cassette/Burger_Time_MiST/rtl/Roms/burger_time_sound_prog.vhd new file mode 100644 index 00000000..4dc5a5f9 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/burger_time_sound_prog.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity burger_time_sound_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of burger_time_sound_prog is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"4C",X"7A",X"F0",X"4C",X"09",X"F0",X"4C",X"55",X"F2",X"78",X"D8",X"A2",X"FF",X"9A",X"A2",X"EF", + X"A9",X"00",X"95",X"00",X"CA",X"D0",X"FB",X"20",X"2A",X"F0",X"A9",X"08",X"85",X"1E",X"A9",X"FF", + X"8D",X"00",X"C0",X"58",X"20",X"4A",X"F0",X"4C",X"27",X"F0",X"A9",X"00",X"85",X"05",X"AA",X"A5", + X"05",X"8D",X"00",X"40",X"8D",X"00",X"80",X"BD",X"64",X"F0",X"8D",X"00",X"20",X"8D",X"00",X"60", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"F0",X"37",X"FC",X"06",X"F0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_1.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_1.vhd new file mode 100644 index 00000000..126eac41 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_1.vhd @@ -0,0 +1,470 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity fg_sp_graphx_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of fg_sp_graphx_1 is + type rom is array(0 to 7167) of std_logic_vector(7 downto 0); + signal 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if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_2.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_2.vhd new file mode 100644 index 00000000..7d0d60c0 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_2.vhd @@ -0,0 +1,438 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity fg_sp_graphx_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of fg_sp_graphx_2 is + type rom is array(0 to 6655) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"00",X"1F",X"01",X"01",X"03",X"02",X"02",X"02",X"02",X"03",X"02",X"02",X"02",X"03",X"02",X"02", + X"03",X"02",X"02",X"02",X"03",X"02",X"02",X"02",X"03",X"02",X"02",X"03",X"01",X"01",X"1F",X"00", + X"00",X"3E",X"02",X"02",X"07",X"04",X"04",X"04",X"04",X"06",X"04",X"05",X"04",X"06",X"05",X"04", + X"06",X"04",X"04",X"04",X"06",X"04",X"05",X"04",X"06",X"04",X"05",X"06",X"03",X"02",X"3E",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_3.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_3.vhd new file mode 100644 index 00000000..caa478b3 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/Roms/fg_sp_graphx_3.vhd @@ -0,0 +1,470 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity fg_sp_graphx_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of fg_sp_graphx_3 is + type rom is array(0 to 7167) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"FE",X"F4",X"7C",X"3A",X"7C",X"FE",X"FA",X"7C",X"F8",X"FC",X"7A",X"74",X"FE",X"BC",X"78",X"00", + X"A0",X"F0",X"78",X"FC",X"E8",X"F4",X"F8",X"F0",X"F8",X"F4",X"FC",X"F8",X"74",X"F8",X"E8",X"FC", + X"FC",X"E8",X"F8",X"74",X"F8",X"FC",X"F4",X"F8",X"F0",X"F8",X"F4",X"E8",X"FC",X"78",X"F0",X"00", + X"40",X"E0",X"F0",X"F8",X"D0",X"E8",X"F0",X"E0",X"F0",X"E8",X"F8",X"F0",X"E8",X"F0",X"D0",X"F8", + X"F8",X"D0",X"F0",X"E8",X"F0",X"F8",X"E8",X"F0",X"E0",X"F0",X"E8",X"D0",X"F8",X"F0",X"E0",X"00", + X"80",X"C0",X"E0",X"F0",X"A0",X"D0",X"E0",X"C0",X"E0",X"D0",X"F0",X"E0",X"D0",X"E0",X"A0",X"F0", + X"F0",X"A0",X"E0",X"D0",X"E0",X"F0",X"D0",X"E0",X"C0",X"E0",X"D0",X"A0",X"F0",X"E0",X"C0",X"00", + X"00",X"80",X"C0",X"E0",X"40",X"A0",X"C0",X"80",X"C0",X"A0",X"E0",X"C0",X"A0",X"C0",X"40",X"E0", + X"E0",X"40",X"C0",X"A0",X"C0",X"E0",X"A0",X"C0",X"80",X"C0",X"A0",X"40",X"E0",X"C0",X"80",X"00", + X"00",X"00",X"80",X"C0",X"80",X"40",X"80",X"00",X"80",X"40",X"C0",X"80",X"40",X"80",X"80",X"C0", + X"C0",X"80",X"80",X"40",X"80",X"C0",X"40",X"80",X"00",X"80",X"40",X"80",X"C0",X"80",X"00",X"00", + X"00",X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"80",X"80",X"00",X"80",X"00",X"00",X"80", + X"80",X"00",X"00",X"80",X"00",X"80",X"80",X"00",X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"01",X"01",X"00",X"00",X"00",X"01",X"01", + X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00", + X"03",X"01",X"02",X"03",X"01",X"01",X"03",X"03",X"01",X"03",X"03",X"01",X"00",X"01",X"03",X"03", + X"03",X"03",X"01",X"00",X"01",X"03",X"03",X"01",X"03",X"03",X"01",X"01",X"03",X"02",X"01",X"00", + X"06",X"03",X"05",X"07",X"03",X"03",X"07",X"07",X"03",X"07",X"07",X"03",X"01",X"03",X"07",X"07", + X"07",X"07",X"03",X"01",X"03",X"07",X"07",X"03",X"07",X"07",X"03",X"03",X"07",X"05",X"03",X"00", + X"0D",X"07",X"0B",X"0F",X"07",X"07",X"0F",X"0F",X"07",X"0F",X"0F",X"07",X"03",X"07",X"0F",X"0F", + X"0F",X"0F",X"07",X"03",X"07",X"0F",X"0F",X"07",X"0F",X"0F",X"07",X"07",X"0F",X"0B",X"07",X"00", + X"1A",X"0F",X"17",X"1F",X"0E",X"0F",X"1F",X"1F",X"0F",X"1F",X"1F",X"0F",X"07",X"0F",X"1E",X"1F", + X"1F",X"1E",X"0F",X"07",X"0F",X"1F",X"1F",X"0F",X"1F",X"1F",X"0F",X"0E",X"1F",X"17",X"0F",X"00", + X"34",X"1E",X"2F",X"3F",X"1D",X"1E",X"3F",X"3E",X"1F",X"3E",X"3F",X"1F",X"0E",X"1F",X"3D",X"3F", + X"3F",X"3D",X"1F",X"0E",X"1F",X"3F",X"3E",X"1F",X"3E",X"3F",X"1E",X"1D",X"3F",X"2F",X"1E",X"00", + X"68",X"3C",X"5E",X"7F",X"3A",X"3D",X"7E",X"7C",X"3E",X"7D",X"7F",X"3E",X"1D",X"3E",X"7A",X"7F", + X"7F",X"7A",X"3E",X"1D",X"3E",X"7F",X"7D",X"3E",X"7C",X"7E",X"3D",X"3A",X"7F",X"5E",X"3C",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/build_id.tcl b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/build_id.v b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/build_id.v new file mode 100644 index 00000000..ec08380d --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171227" +`define BUILD_TIME "140251" diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time _sound.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time _sound.vhd new file mode 100644 index 00000000..cbddd6bf --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time _sound.vhd @@ -0,0 +1,426 @@ +--------------------------------------------------------------------------------- +-- burger time sound by Dar (darfpga@aol.fr) (27/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burger_time_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity burger_time_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end burger_time_sound; + +architecture syn of burger_time_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.burger_time_sound_prog +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time.vhd new file mode 100644 index 00000000..89595a55 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time.vhd @@ -0,0 +1,803 @@ +--------------------------------------------------------------------------------- +-- burger time by Dar (darfpga@aol.fr) (27/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burger_timer_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity burger_time is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + + video_hs : out std_logic; + video_vs : out std_logic; + video_blankn : out std_logic; + video_csync : out std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + + fire1 : in std_logic; + right1 : in std_logic; + left1 : in std_logic; + down1 : in std_logic; + up1 : in std_logic; + + fire2 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + down2 : in std_logic; + up2 : in std_logic; + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end burger_time; + +architecture syn of burger_time is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_6 : std_logic := '0'; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_sync : std_logic; + signal cpu_ena : std_logic; + signal had_written : std_logic := '0'; + signal decrypt : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- foreground ram signals + signal fg_ram_cs : std_logic; + signal fg_ram_low_we : std_logic; + signal fg_ram_high_we : std_logic; + signal fg_ram_addr_sel : std_logic_vector(1 downto 0); + signal fg_ram_addr : std_logic_vector(9 downto 0); + signal fg_ram_low_do : std_logic_vector(7 downto 0); + signal fg_ram_high_do : std_logic_vector(1 downto 0); + + + -- video scan counter + signal hcnt : std_logic_vector(8 downto 0); + signal vcnt : std_logic_vector(8 downto 0); + signal hsync0 : std_logic; + signal hsync1 : std_logic; + signal hsync2 : std_logic; + signal csync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic; + + signal hcnt_flip : std_logic_vector(8 downto 0); + signal vcnt_flip : std_logic_vector(8 downto 0); + signal cocktail_we : std_logic; + signal cocktail_flip : std_logic := '0'; + signal hcnt8_r : std_logic; + signal hcnt8_rr : std_logic; + + -- io + signal io_cs : std_logic; + signal dip_sw1 : std_logic_vector(7 downto 0); + signal dip_sw2 : std_logic_vector(7 downto 0); + signal btn_p1 : std_logic_vector(7 downto 0); + signal btn_p2 : std_logic_vector(7 downto 0); + signal btn_system : std_logic_vector(7 downto 0); + + -- foreground and sprite graphix + signal sprite_attr : std_logic_vector( 2 downto 0); + signal sprite_tile : std_logic_vector( 7 downto 0); + signal sprite_line : std_logic_vector( 7 downto 0); + signal sprite_buffer_addr : std_logic_vector( 7 downto 0); + signal sprite_buffer_addr_flip : std_logic_vector( 7 downto 0); + signal sprite_buffer_di : std_logic_vector( 2 downto 0); + signal sprite_buffer_do : std_logic_vector( 2 downto 0); + signal fg_grphx_addr : std_logic_vector(12 downto 0); + signal fg_grphx_addr_early : std_logic_vector(12 downto 0); + signal fg_grphx_1_do : std_logic_vector( 7 downto 0); + signal fg_grphx_2_do : std_logic_vector( 7 downto 0); + signal fg_grphx_3_do : std_logic_vector( 7 downto 0); + signal fg_sp_grphx_1 : std_logic_vector( 7 downto 0); + signal fg_sp_grphx_2 : std_logic_vector( 7 downto 0); + signal fg_sp_grphx_3 : std_logic_vector( 7 downto 0); + signal display_tile : std_logic; + signal fg_low_priority : std_logic; + signal fg_sp_bits : std_logic_vector( 2 downto 0); + signal sp_bits_out : std_logic_vector( 2 downto 0); + signal fg_bits : std_logic_vector( 2 downto 0); + + -- color palette + signal palette_addr : std_logic_vector(3 downto 0); + signal palette_cs : std_logic; + signal palette_we : std_logic; + signal palette_do : std_logic_vector(7 downto 0); + + -- background map rom + signal bg_map_addr : std_logic_vector(10 downto 0); + signal bg_map_do : std_logic_vector(7 downto 0); + + -- background control + signal scroll1_we : std_logic; + signal scroll1 : std_logic_vector(4 downto 0); + signal scroll2_we : std_logic; + signal scroll2 : std_logic_vector(7 downto 0); + + signal bg_hcnt : std_logic_vector( 7 downto 0); + signal bg_scan_hcnt : std_logic_vector( 9 downto 0); + signal bg_scan_addr : std_logic_vector( 9 downto 0); + signal bg_grphx_addr : std_logic_vector(10 downto 0); + signal bg_grphx_1_do : std_logic_vector( 7 downto 0); + signal bg_grphx_2_do : std_logic_vector( 7 downto 0); + signal bg_grphx_3_do : std_logic_vector( 7 downto 0); + signal bg_grphx_1 : std_logic_vector( 7 downto 0); + signal bg_grphx_2 : std_logic_vector( 7 downto 0); + signal bg_grphx_3 : std_logic_vector( 7 downto 0); + signal bg_bits : std_logic_vector( 2 downto 0); + + -- misc + signal raz_nmi_we : std_logic; + signal coin1_r : std_logic; + signal sound_req : std_logic; + +begin + +--process (clock_12, cpu_sync) +--begin +-- if rising_edge(clock_12) then +-- if cpu_sync = '1' then +-- dbg_cpu_addr <= cpu_addr(15 downto 0); +-- end if; +-- end if; +--end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_6 <= '0'; + else + if rising_edge(clock_12) then + clock_6 <= not clock_6; + end if; + end if; +end process; + +------------------- +-- Video scanner -- +------------------- + +-- make hcnt and vcnt video scanner (from schematics !) +-- +-- hcnt [0..255,256..383] => 384 pixels, 384/6Mhz => 1 line is 64us (15.625KHz) +-- vcnt [8..255,256..279] => 272 lines, 1 frame is 272 x 64us = 17.41ms (57.44Hz) + +process (reset, clock_12) +begin + if reset='1' then + hcnt <= (others => '0'); + vcnt <= (others => '0'); + else + if rising_edge(clock_12) and clock_6 = '1' then + hcnt <= hcnt + '1'; + if hcnt = 383 then + hcnt <= (others => '0'); + if vcnt = 260 then -- total should be 272 from Bump&Jump schematics ! + vcnt <= (others => '0'); + else + vcnt <= vcnt + '1'; + end if; + end if; + end if; + + end if; +end process; + +hcnt_flip <= hcnt when cocktail_flip = '0' else not hcnt; +vcnt_flip <= not vcnt when cocktail_flip = '0' else vcnt; + +--ROM_START( btime ) +-- ROM_REGION( 0x10000, "maincpu", 0 ) +-- ROM_LOAD( "aa04.9b", 0xc000, 0x1000, CRC(368a25b5) SHA1(ed3f3712423979dcb351941fa85dce6a0a7bb16b) ) +-- ROM_LOAD( "aa06.13b", 0xd000, 0x1000, CRC(b4ba400d) SHA1(8c77397e934907bc47a739f263196a0f2f81ba3d) ) +-- ROM_LOAD( "aa05.10b", 0xe000, 0x1000, CRC(8005bffa) SHA1(d0da4e360039f6a8d8142a4e8e05c1f90c0af68a) ) +-- ROM_LOAD( "aa07.15b", 0xf000, 0x1000, CRC(086440ad) SHA1(4a32bc92f8ff5fbe112f56e62d2c03da8851a7b9) ) +-- +-- ROM_REGION( 0x10000, "audiocpu", 0 ) +-- ROM_LOAD( "ab14.12h", 0xe000, 0x1000, CRC(f55e5211) SHA1(27940026d0c6212d1138d2fd88880df697218627) ) +-- +-- ROM_REGION( 0x6000, "gfx1", 0 ) +-- ROM_LOAD( "aa12.7k", 0x0000, 0x1000, CRC(c4617243) SHA1(24204d591aa2c264a852ee9ba8c4be63efd97728) ) /* charset #1 */ +-- ROM_LOAD( "ab13.9k", 0x1000, 0x1000, CRC(ac01042f) SHA1(e64b6381a9298eaf74e79fa5f1ea8e9596c58a49) ) +-- ROM_LOAD( "ab10.10k", 0x2000, 0x1000, CRC(854a872a) SHA1(3d2ecfd54a5a9d68b53cf4b4ee1f2daa6aef2123) ) +-- ROM_LOAD( "ab11.12k", 0x3000, 0x1000, CRC(d4848014) SHA1(0a55b091cd4e7f317c35defe13d5051b26042eee) ) +-- ROM_LOAD( "aa8.13k", 0x4000, 0x1000, CRC(8650c788) SHA1(d9b1ee2d1f2fd66705d497c80252861b49aa9254) ) +-- ROM_LOAD( "ab9.15k", 0x5000, 0x1000, CRC(8dec15e6) SHA1(b72633de6268ce16742bba4dcba835df860d6c2f) ) +-- +-- ROM_REGION( 0x1800, "gfx2", 0 ) +-- ROM_LOAD( "ab00.1b", 0x0000, 0x0800, CRC(c7a14485) SHA1(6a0a8e6b7860859f22daa33634e34fbf91387659) ) /* charset #2 */ +-- ROM_LOAD( "ab01.3b", 0x0800, 0x0800, CRC(25b49078) SHA1(4abdcbd4f3362c3e4463a1274731289f1a72d2e6) ) +-- ROM_LOAD( "ab02.4b", 0x1000, 0x0800, CRC(b8ef56c3) SHA1(4a03bf011dc1fb2902f42587b1174b880cf06df1) ) +-- +-- ROM_REGION( 0x0800, "bg_map", 0 ) /* background tilemaps */ +-- ROM_LOAD( "ab03.6b", 0x0000, 0x0800, CRC(d26bc1f3) SHA1(737af6e264183a1f151f277a07cf250d6abb3fd8) ) +--ROM_END + +--static ADDRESS_MAP_START( btime_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("rambase") +-- AM_RANGE(0x0c00, 0x0c0f) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") +-- AM_RANGE(0x1000, 0x13ff) AM_RAM AM_SHARE("videoram") +-- AM_RANGE(0x1400, 0x17ff) AM_RAM AM_SHARE("colorram") +-- AM_RANGE(0x1800, 0x1bff) AM_READWRITE(btime_mirrorvideoram_r, btime_mirrorvideoram_w) +-- AM_RANGE(0x1c00, 0x1fff) AM_READWRITE(btime_mirrorcolorram_r, btime_mirrorcolorram_w) +-- AM_RANGE(0x4000, 0x4000) AM_READ_PORT("P1") AM_WRITENOP +-- AM_RANGE(0x4001, 0x4001) AM_READ_PORT("P2") +-- AM_RANGE(0x4002, 0x4002) AM_READ_PORT("SYSTEM") AM_WRITE(btime_video_control_w) +-- AM_RANGE(0x4003, 0x4003) AM_READ_PORT("DSW1") AM_WRITE(audio_command_w) +-- AM_RANGE(0x4004, 0x4004) AM_READ_PORT("DSW2") AM_WRITE(bnj_scroll1_w) +-- AM_RANGE(0xb000, 0xffff) AM_ROM +--ADDRESS_MAP_END + +-- dip_sw1 -- unkown/cocktail/hatch/test/coinage_b[2]/coinage_a[2] +-- dip_sw2 -- off/off/off/eol pepper/enemies/bonus[2]/lives +-- btn_p1 -- nu/nu/unkonw/jump/down/up/left/right +-- btn_p2 -- nu/nu/unkonw/jump/down/up/left/right +-- btn_system -- coin2/coin1/unknown/unknown/unkown/tilt/start2/start1 + +dip_sw1 <= "00111111"; +dip_sw2 <= "11101011"; +btn_p1 <= not("000"&fire1 & down1 & up1 & left1 & right1); +btn_p2 <= not("000"&fire2 & down2 & up2 & left2 & right2); +btn_system <= ('0'&coin1) & not("0000"&start2&start1); + +-- misc (coin, nmi, cocktail) +process (reset,clock_12) +begin + if reset = '1' then + cpu_nmi_n <= '1'; + had_written <='0'; + cocktail_flip <= '0'; + else + if rising_edge(clock_12)then + coin1_r <= coin1; + if coin1_r = '0' and coin1 = '1' then + cpu_nmi_n <= '0'; + end if; + if raz_nmi_we = '1' then + cpu_nmi_n <= '1'; + end if; + if cpu_ena = '1' then + if cpu_rw_n = '0' then + had_written <= '1'; + elsif cpu_sync = '1' then + had_written <= '0'; + end if; + end if; + if cocktail_we = '1' then + cocktail_flip <= dip_sw1(6) and cpu_do(0); + end if; + end if; + end if; +end process; + + +cpu_ena <= '1' when hcnt(2 downto 0) = "111" and clock_6 = '1' else '0'; + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 11) = "00000" else '0'; -- working ram 0000-07ff +io_cs <= '1' when cpu_addr(15 downto 3) = "0100000000000" else '0'; -- player/dip_sw 4000-4007 (4004) +fg_ram_cs <= '1' when cpu_addr(15 downto 12) = "0001" else '0'; -- foreground ram 1000-1fff +palette_cs <= '1' when cpu_addr(15 downto 4) = "000011000000" else '0'; -- palette ram 0c00-0c0f +prog_rom_cs <= '1' when cpu_addr(15 downto 14) = "11" else '0'; -- program rom c000-ffff + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 0000-07ff +raz_nmi_we <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "000" and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 4000 +scroll1_we <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "100" and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 4004 +scroll2_we <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "101" and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 4005 +cocktail_we <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "010" and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 4002 +sound_req <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "011" and cpu_rw_n = '0' else '0'; -- 4003 +fg_ram_low_we <= '1' when fg_ram_cs = '1' and cpu_addr(10) = '0' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 1000-13ff & 1800-4bff +fg_ram_high_we <= '1' when fg_ram_cs = '1' and cpu_addr(10) = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 1400-17ff & 1c00-4fff +palette_we <= '1' when palette_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 0c00-0c0f + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + vblank&dip_sw1(6 downto 0) when (io_cs = '1') and (cpu_addr(2 downto 0) = "011") else + dip_sw2 when (io_cs = '1') and (cpu_addr(2 downto 0) = "100") else + btn_p1 when (io_cs = '1') and (cpu_addr(2 downto 0) = "000") else + btn_p2 when (io_cs = '1') and (cpu_addr(2 downto 0) = "001") else + btn_system when (io_cs = '1') and (cpu_addr(2 downto 0) = "010") else + fg_ram_low_do when (fg_ram_cs = '1') and (cpu_addr(10) = '0') else + "000000"&fg_ram_high_do when (fg_ram_cs = '1') and (cpu_addr(10) = '1') else + X"FF"; + +-- decrypt fetched instruction +decrypt <= '1' when ((cpu_addr(15 downto 0) and X"0104") = X"0104") and (cpu_sync = '1') and (had_written = '1') else '0'; +cpu_di_dec <= cpu_di when decrypt = '0' else + cpu_di(6) & cpu_di(5) & cpu_di(3) & cpu_di(4) & cpu_di(2) & cpu_di(7) & cpu_di(1 downto 0); + +---------------------------- +-- foreground and sprites -- +---------------------------- + +-- foreground ram addr +fg_ram_addr_sel <= "00" when cpu_ena = '1' and cpu_addr(11) = '0' else + "01" when cpu_ena = '1' and cpu_addr(11) = '1' else + "10" when cpu_ena = '0' and hcnt(8) = '0' else + "11"; + +with fg_ram_addr_sel select +fg_ram_addr <= cpu_addr(4 downto 0) & cpu_addr(9 downto 5) when "00", -- cpu mirrored addressing + cpu_addr(9 downto 0) when "01", -- cpu normal addressing + vcnt_flip(7 downto 3) & hcnt_flip(7 downto 3) when "10", -- foreground tile scan addressing + "00000" & hcnt(6 downto 2) when others; -- sprite data scan addressing + +-- latch sprite data, +-- manage fg and sprite graphix rom address +-- manage sprite line buffer address +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + + if hcnt(3 downto 0) = "0000" then + sprite_attr <= fg_ram_low_do(2 downto 0); + end if; + if hcnt(3 downto 0) = "0100" then + sprite_tile <= fg_ram_low_do(7 downto 0); + end if; + if hcnt(3 downto 0) = "1000" then + if sprite_attr(1) = '0' then + sprite_line <= vcnt_flip(7 downto 0) - 0 + fg_ram_low_do(7 downto 0); + else + sprite_line <= (vcnt_flip(7 downto 0) - 0 + fg_ram_low_do(7 downto 0)) xor X"0F"; -- flip V + end if; + end if; + + if hcnt(2 downto 0) = "100" then + hcnt8_r <= hcnt(8); + fg_grphx_addr_early <= fg_ram_high_do & fg_ram_low_do & vcnt_flip(2 downto 0); -- fg_ram_low_do(7) = '1' => low priority foreground + if hcnt8_r = '1' then + fg_grphx_addr <= sprite_tile & not (sprite_attr(2) xor hcnt_flip(3) xor cocktail_flip) & sprite_line(3 downto 0); + if hcnt(3) = '1' then + if (sprite_line(7 downto 4) = "1111") and (sprite_attr(0) = '1') then + display_tile <= '1'; + else + display_tile <= '0'; + end if; + end if; + else + fg_grphx_addr <= fg_grphx_addr_early; + display_tile <= '1'; + end if; + end if; + + if hcnt8_r = '1' then + if hcnt(3 downto 0) = X"D" then + sprite_buffer_addr <= fg_ram_low_do(7 downto 0); + hcnt8_rr <= '1'; + else + sprite_buffer_addr <= sprite_buffer_addr + '1'; + end if; + else + if hcnt(7 downto 0) = X"0D" then + sprite_buffer_addr <= X"01"; -- (others => '0'); + hcnt8_rr <= '0'; + else + sprite_buffer_addr <= sprite_buffer_addr + '1'; + end if; + end if; + + end if; +end process; + +sprite_buffer_addr_flip <= not (sprite_buffer_addr) when hcnt8_rr = '0' and cocktail_flip = '1' else sprite_buffer_addr; + +-- latch and shift foreground and sprite graphics +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + if hcnt(2 downto 0) = "101" then + if display_tile = '1' then + fg_sp_grphx_1 <= fg_grphx_1_do; + fg_sp_grphx_2 <= fg_grphx_2_do; + fg_sp_grphx_3 <= fg_grphx_3_do; + fg_low_priority <= '1'; --fg_grphx_addr(10); -- #fg_ram_low_do(7) (always 1 for burger time) + else + fg_sp_grphx_1 <= (others =>'0'); + fg_sp_grphx_2 <= (others =>'0'); + fg_sp_grphx_3 <= (others =>'0'); + end if; + elsif cocktail_flip = '0' or hcnt8_rr = '1' then + fg_sp_grphx_1 <= '0' & fg_sp_grphx_1(7 downto 1); + fg_sp_grphx_2 <= '0' & fg_sp_grphx_2(7 downto 1); + fg_sp_grphx_3 <= '0' & fg_sp_grphx_3(7 downto 1); + else + fg_sp_grphx_1 <= fg_sp_grphx_1(6 downto 0) & '0'; + fg_sp_grphx_2 <= fg_sp_grphx_2(6 downto 0) & '0'; + fg_sp_grphx_3 <= fg_sp_grphx_3(6 downto 0) & '0'; + end if; + end if; +end process; + +fg_sp_bits <= fg_sp_grphx_3(0) & fg_sp_grphx_2(0) & fg_sp_grphx_1(0) when cocktail_flip = '0' or hcnt8_rr = '1' else + fg_sp_grphx_3(7) & fg_sp_grphx_2(7) & fg_sp_grphx_1(7); + +-- data to sprite buffer +sprite_buffer_di <= "000" when hcnt8_rr = '0' else -- clear ram after read + sprite_buffer_do when fg_sp_bits = "000" else fg_sp_bits; -- sp vs sp priority rules + +-- read sprite buffer +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '0' then + if hcnt8_rr = '0' then + sp_bits_out <= sprite_buffer_do; + else + sp_bits_out <= "000"; + end if; + end if; +end process; + +-- mux foreground and sprite buffer output with priorities +fg_bits <= sp_bits_out when (fg_sp_bits = "000") or (sp_bits_out/="000" and fg_low_priority = '1') else fg_sp_bits; + +---------------- +-- background -- +---------------- + +-- latch scroll1 & 2 data +process (clock_12n) +begin + if rising_edge(clock_12n) and clock_6 = '1' then + if scroll1_we = '1' then + scroll1 <= cpu_do(4 downto 0); + end if; + if scroll2_we = '1' then + scroll2 <= cpu_do; + end if; + end if; +end process; + +-- manage background rom map address +bg_scan_hcnt <= (hcnt_flip) + (scroll1(1 downto 0)&scroll2) + "0011110010" when cocktail_flip = '0' else + (hcnt_flip) + (scroll1(1 downto 0)&scroll2) + "1100000101"; + +bg_map_addr <= scroll1(2) & bg_scan_hcnt(9 downto 4) & vcnt_flip(7 downto 4); + +-- manage background graphics rom address +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '0' then + if bg_scan_hcnt(2 downto 0) = "000" then + bg_grphx_addr <= bg_map_do(5 downto 0) & bg_scan_hcnt(3) & vcnt_flip(3 downto 0); + end if; + end if; +end process; + +-- latch and shift background graphics +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + if scroll1(4) = '0' then + bg_grphx_1 <= (others => '0'); + bg_grphx_2 <= (others => '0'); + bg_grphx_3 <= (others => '0'); + else + if bg_scan_hcnt(2 downto 0) = "000" then + bg_grphx_1 <= bg_grphx_1_do; + bg_grphx_2 <= bg_grphx_2_do; + bg_grphx_3 <= bg_grphx_3_do; + elsif cocktail_flip = '0' then + bg_grphx_1 <= '0' & bg_grphx_1(7 downto 1); + bg_grphx_2 <= '0' & bg_grphx_2(7 downto 1); + bg_grphx_3 <= '0' & bg_grphx_3(7 downto 1); + else + bg_grphx_1 <= bg_grphx_1(6 downto 0) & '0'; + bg_grphx_2 <= bg_grphx_2(6 downto 0) & '0'; + bg_grphx_3 <= bg_grphx_3(6 downto 0) & '0'; + end if; + end if; + end if; +end process; + +bg_bits <= bg_grphx_3(0) & bg_grphx_2(0) & bg_grphx_1(0) when cocktail_flip = '0' else + bg_grphx_3(7) & bg_grphx_2(7) & bg_grphx_1(7); + +-- manage color palette address +palette_addr <= cpu_addr(3 downto 0) when palette_we = '1' else + '1'&bg_bits when fg_bits = "000" else + '0'&fg_bits; + +-- get palette output +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '0' then + video_r <= not palette_do(2 downto 0); + video_g <= not palette_do(5 downto 3); + video_b <= not palette_do(7 downto 6); + end if; +end process; + +---------------------------- +-- video syncs and blanks -- +---------------------------- + +video_csync <= csync; + +process(clock_12) + constant hcnt_base : integer := 312; --320 + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + +if rising_edge(clock_12) and clock_6 = '1' then + + if hcnt = hcnt_base+0 then hsync0 <= '0'; + elsif hcnt = hcnt_base+24 then hsync0 <= '1'; + end if; + + if hcnt = hcnt_base+0 then hsync1 <= '0'; + elsif hcnt = hcnt_base+12 then hsync1 <= '1'; + elsif hcnt = hcnt_base+192-384 then hsync1 <= '0'; + elsif hcnt = hcnt_base+204-384 then hsync1 <= '1'; + end if; + + if hcnt = hcnt_base+0 then hsync2 <= '0'; + elsif hcnt = hcnt_base+192-12-384 then hsync2 <= '1'; + elsif hcnt = hcnt_base+192-384 then hsync2 <= '0'; + elsif hcnt = hcnt_base+0-12 then hsync2 <= '1'; + end if; + + if hcnt = hcnt_base then + if vcnt = 246 then + vsync_cnt := X"0"; + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if; + end if; + end if; + + if vsync_cnt = 0 then csync <= hsync1; + elsif vsync_cnt = 1 then csync <= hsync1; + elsif vsync_cnt = 2 then csync <= hsync1; + elsif vsync_cnt = 3 then csync <= hsync2; + elsif vsync_cnt = 4 then csync <= hsync2; + elsif vsync_cnt = 5 then csync <= hsync2; + elsif vsync_cnt = 6 then csync <= hsync1; + elsif vsync_cnt = 7 then csync <= hsync1; + elsif vsync_cnt = 8 then csync <= hsync1; + else csync <= hsync0; + end if; + + if hcnt = 267 then hblank <= '1'; + elsif hcnt = 14 then hblank <= '0'; + end if; + + if vcnt = 248 then vblank <= '1'; + elsif vcnt = 8 then vblank <= '0'; + end if; + + -- external sync and blank outputs + video_blankn <= not (hblank or vblank); + + video_hs <= hsync0; + + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 8 then video_vs <= '1'; + end if; + +end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => cpu_ena, + Clk => clock_12, + Rdy => '1', + Abort_n => '1', + IRQ_n => '1',--cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di_dec, + DO => cpu_do +); + + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr( 10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.burger_time_prog +port map( + clk => clock_12n, + addr => cpu_addr(13 downto 0), + data => prog_rom_do +); + +-- foreground ram low +fg_ram_low : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_12n, + we => fg_ram_low_we, + addr => fg_ram_addr, + d => cpu_do, + q => fg_ram_low_do +); + +-- foreground ram high +fg_ram_high : entity work.gen_ram +generic map( dWidth => 2, aWidth => 10) +port map( + clk => clock_12n, + we => fg_ram_high_we, + addr => fg_ram_addr, + d => cpu_do(1 downto 0), + q => fg_ram_high_do +); + +-- foreground and sprite graphix rom bit #1 +fg_sp_graphx_1: entity work.fg_sp_graphx_1 +port map( + clk => clock_12n, + addr => fg_grphx_addr, + data => fg_grphx_1_do +); + +-- foreground and sprite graphix rom bit #2 +fg_sp_graphx_2: entity work.fg_sp_graphx_2 +port map( + clk => clock_12n, + addr => fg_grphx_addr, + data => fg_grphx_2_do +); + +-- foreground and sprite graphix rom bit #3 +fg_sp_graphx_3: entity work.fg_sp_graphx_3 +port map( + clk => clock_12n, + addr => fg_grphx_addr, + data => fg_grphx_3_do +); + +-- sprite buffer ram +sprite_buffer_ram : entity work.gen_ram +generic map( dWidth => 3, aWidth => 8) +port map( + clk => clock_12n, + we => clock_6, + addr => sprite_buffer_addr_flip, + d => sprite_buffer_di, + q => sprite_buffer_do +); + +-- color palette ram +color_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 4) +port map( + clk => clock_12n, + we => palette_we, + addr => palette_addr, + d => cpu_do, + q => palette_do +); + +-- background map rom +bg_map: entity work.bg_map +port map( + clk => clock_12n, + addr => bg_map_addr, + data => bg_map_do +); + +-- background graphix rom bit #1 +bg_graphx_1: entity work.bg_graphx_1 +port map( + clk => clock_12n, + addr => bg_grphx_addr, + data => bg_grphx_1_do +); + +-- background graphix rom bit #2 +bg_graphx_2: entity work.bg_graphx_2 +port map( + clk => clock_12n, + addr => bg_grphx_addr, + data => bg_grphx_2_do +); + +-- background graphix rom bit #3 +bg_graphx_3: entity work.bg_graphx_3 +port map( + clk => clock_12n, + addr => bg_grphx_addr, + data => bg_grphx_3_do +); + +-- burger time sound part +burger_tiime_sound: entity work.burger_time_sound +port map( + clock_12 => clock_12, + reset => reset, + + sound_req => sound_req, + sound_code_in => cpu_do, + sound_timing => vcnt(3), + + audio_out => audio_out, + + dbg_cpu_addr => dbg_cpu_addr +); + +end SYN; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time_mist.sv b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time_mist.sv new file mode 100644 index 00000000..6415acb9 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/burger_time_mist.sv @@ -0,0 +1,167 @@ +module burger_time_mist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "BurgerTime;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_48, clk_12, clk_6, clk_24; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_48), + .c1(clk_12), + .c2(clk_6), + .c3(clk_24) +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +burger_time burger_time( + .clock_12(clk_12), + .reset(status[0] | status[6] | buttons[1]), + .video_r(r), + .video_g(g), + .video_b(b), + .video_csync(), + .video_blankn(blankn), + .video_hs(hs), + .video_vs(vs), + .audio_out(audio), + .start2(m_start2), + .start1(m_start1), + .coin1(m_coin), + .fire1(m_fire), + .right1(m_right), + .left1(m_left), + .down1(m_down), + .up1(m_up), + .fire2(m_fire), + .right2(m_right), + .left2(m_left), + .down2(m_down), + .up2(m_up), + .dbg_cpu_addr() +); + +wire [10:0] audio; + +dac dac ( + .clk_i(clk_48), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g; +wire [1:0] b; +wire blankn; + +video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_48), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r&r : "000000"), + .G(blankn ? g&g : "000000"), + .B(blankn ? b&b : "0000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_48 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_48), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule + + + + diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/dac.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/gen_ram.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/hq2x.sv b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/keyboard.v b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/mist_io.v b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/osd.v b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/pll.qip b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/pll.v b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/pll.v new file mode 100644 index 00000000..fe052027 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/pll.v @@ -0,0 +1,396 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + c2, + c3); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output c3; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire c3 = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire6), + .clk (sub_wire0), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 16, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 4, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 9, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 2, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 9, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 8, + altpll_component.clk3_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/scandoubler.v b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_ALU.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_MCode.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_Pack.vhd b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/t65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Data East Cassette/Burger_Time_MiST/rtl/video_mixer.sv b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Data East Cassette/Burger_Time_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/README.txt b/Arcade/Data East Cassette/Burnin Rubber_MiST/README.txt new file mode 100644 index 00000000..26859cf2 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/README.txt @@ -0,0 +1,242 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Burnin Rubber for MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- Copyright (c) DAR - Dez 2017 +-- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/burnin_rubber/ +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE : Turbo +-- LALT : Turbo +-- ARROW KEYS : Movement +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + + + +--------------------------------------------------------------------------------- +-- burnin rubber by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +-- +-- Main features : +-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection) +-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection) +-- +-- Uses 1 pll for 12MHz generation from 50MHz +-- +-- Board key : +-- 0 : reset game +-- +-- Keyboard players inputs : +-- +-- F3 : Add coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Jump +-- RIGHT arrow : move right +-- LEFT arrow : move left +-- UP arrow : accelerate +-- DOWN arrow : slow down +-- +-- Other details : see burnin_rubber.vhd +-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok +-- No external RAM/SDRAM required + +-- Use with MAME roms from rbubber.zip +-- +-- Use make_burnin_rubber_proms.bat to build vhd file from binaries + +-- Burnin' Rubber Hardware caracteristics : +-- +-- VIDEO : 1x6502@750kHz CPU accessing its program rom, working ram, +-- foreground and sprite data ram, I/O, sound board register and trigger. +-- 16Kx8bits program rom +-- 2Kb8bits working ram +-- +-- One char 8x8 tile map 32x30 + sprites data +-- 1Kx8bits + 1Kx2bits +-- 3x8Kx8bits graphics rom 3bits/pixel +-- 8 colors with ram palette +-- +-- 8 sprites 16*16 with priorities and flip H/V +-- use char graphics rom and colors +-- +-- Char/sprites 8 colors among 256 colors +-- 8bits 3red/3green/2blue +-- +-- Sprites buffer rams 3x256bits +-- +-- Background tile map with scroll 0-511 pixels +-- 1K*4bits ram +-- 4K*8bits + 4K*4bits graphics rom 3bits/pixel +-- 8 colors with ram palette +-- 16x16 tiles +-- +-- SOUND : 1x6502@500kHz CPU accessing its program rom, working ram, 2x-AY3-8910, +-- command registers, triggers. +-- 2Kx8bits working ram +-- 4Kx8bits program rom +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- Pass band active filter on channel A of AY#2 +-- ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Fri Dec 22 17:53:19 2017 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; burnin_rubber_de10_lite ; +; Top-level Entity Name ; burnin_rubber_de10_lite ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 3,565 / 49,760 ( 7 % ) ; +; Total combinational functions ; 3,392 / 49,760 ( 7 % ) ; +; Dedicated logic registers ; 1,099 / 49,760 ( 2 % ) ; +; Total registers ; 1099 ; +; Total pins ; 105 / 360 ( 29 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 433,024 / 1,677,312 ( 26 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + +--------------- +VHDL File list +--------------- + +max10_pll_12M.vhd Pll 12MHz and 14 MHz from 50MHz altera mf + +rtl_dar/burnin_rubber_de10_lite.vhd Top level for de10_lite board + +rtl_dar/burnin_rubber.vhd Main video board logic +rtl_dar/burnin_rubber _sound.vhd Main sound board logic + +rtl_mikej/YM2149_linmix_sep.vhd Copyright (c) MikeJ - Jan 2005 + +t65/T65.vhd Copyright (c) MikeJ - Jan 2005t65/T65_Pack.vhdt65/T65_MCode.vhdt65/T65_ALU.vhd +rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input +rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) +rtl_dar/decodeur_7_seg.vhd 7 segments display decoder + +burnin_rubber_prog.vhd Burnin' rubber video board PROMs +fg_sp_graphx_3.vhd +fg_sp_graphx_2.vhd +fg_sp_graphx_1.vhd +bg_graphx_2.vhd +bg_graphx_1.vhd + +burnin_rubber_sound_prog.vhd Burnin' rubber sound board PROM + +---------------------- +Quartus project files +---------------------- +de10_lite/burnin_rubber_de10_lite.sdc Timequest constraints file +de10_lite/burnin_rubber__de10_lite.qsf de10_lite settings (files,pins...) +de10_lite/burnin_rubber__de10_lite.qpf de10_lite project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 8 ROMs binary files from brubber.zip (MAME) + +brubber.12c,brubber.12d +bnj4e +bnj4f +bnj4h +bnj10e +bnj10f +bnj6c + +------ +Tools +------ +You need to build vhdl files from the binary file : + - Unzip the roms file in the tools/burnin_rubber_unzip directory + - Double click (execute) the script tools/make_burnin_rubber_proms.bat to get the following files + +burnin_rubber_prog.vhd : brubber.12c,brubber.12d +fg_sp_graphx_1.vhd : bnj4e +fg_sp_graphx_2.vhd : bnj4f +fg_sp_graphx_3.vhd : bnj4h +bg_graphx_1.vhd : bnj10e +bg_graphx_2.vhd : bnj10f +burnin_rubber_prog_sound_prog.vhd : bnj6c + +*DO NOT REDISTRIBUTE THESE FILES* + +VHDL files are needed to compile and include roms into the project + +The script make_burnin_rubber_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c is also delivered. + +--------------------------------- +Compiling for de10_lite +--------------------------------- +You can build the project with ROM image embeded in the sof file. +*DO NOT REDISTRIBUTE THESE FILES* + +3 steps + + - put the VHDL ROM files (.vhd) into the rtl_dar directory + - build burnin_rubber_de10_lite + - program burnin_rubber_de10_lite.sof + +------------------------ +------------------------ +End of file +------------------------ diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/Release/burnin_rubber_mist.rbf b/Arcade/Data East Cassette/Burnin Rubber_MiST/Release/burnin_rubber_mist.rbf new file mode 100644 index 00000000..048e218b Binary files /dev/null and b/Arcade/Data East Cassette/Burnin Rubber_MiST/Release/burnin_rubber_mist.rbf differ diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/burnin_rubber_mist.qpf b/Arcade/Data East Cassette/Burnin Rubber_MiST/burnin_rubber_mist.qpf new file mode 100644 index 00000000..eabe62fd --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/burnin_rubber_mist.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 21:51:49 December 06, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "21:51:49 December 06, 2017" + +# Revisions + +PROJECT_REVISION = "burnin_rubber_mist" diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/burnin_rubber_mist.qsf b/Arcade/Data East Cassette/Burnin Rubber_MiST/burnin_rubber_mist.qsf new file mode 100644 index 00000000..adbc6efc --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/burnin_rubber_mist.qsf @@ -0,0 +1,174 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:52:55 December 26, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# burnin_rubber_mist_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name SYSTEMVERILOG_FILE rtl/burnin_rubber_mist.sv +set_global_assignment -name VHDL_FILE rtl/burnin_rubber.vhd +set_global_assignment -name VHDL_FILE "rtl/burnin_rubber _sound.vhd" +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/fg_sp_graphx_3.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/fg_sp_graphx_2.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/fg_sp_graphx_1.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/burnin_rubber_sound_prog.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/burnin_rubber_prog.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/bg_graphx_2.vhd +set_global_assignment -name VHDL_FILE rtl/Roms/bg_graphx_1.vhd +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY burnin_rubber_mist +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------------------- +# start ENTITY(burnin_rubber_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(burnin_rubber_mist) +# ------------------------------ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/clean.bat b/Arcade/Data East Cassette/Burnin Rubber_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/bg_graphx_1.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/bg_graphx_1.vhd new file mode 100644 index 00000000..6d1ac246 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/bg_graphx_1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_graphx_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_graphx_1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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Rubber_MiST/rtl/Roms/bg_graphx_2.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/bg_graphx_2.vhd new file mode 100644 index 00000000..9770363a --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/bg_graphx_2.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity bg_graphx_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of bg_graphx_2 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"FF",X"7F",X"FF",X"FF",X"8F",X"5F",X"CF",X"1F",X"EF",X"1F",X"7F",X"7F",X"F3",X"C0",X"90",X"C0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0C",X"00",X"00",X"00", + X"1F",X"AF",X"1F",X"BF",X"1F",X"9F",X"1F",X"9F",X"1F",X"CF",X"1F",X"EF",X"0F",X"FF",X"06",X"F0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/burnin_rubber_prog.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/burnin_rubber_prog.vhd new file mode 100644 index 00000000..ba70502e --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/burnin_rubber_prog.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity burnin_rubber_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of burnin_rubber_prog is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"2C",X"FF",X"C0",X"28",X"8A",X"28",X"98",X"28",X"B8",X"C5",X"02",X"F0",X"46",X"CD",X"01",X"10", + X"29",X"FF",X"49",X"E0",X"85",X"03",X"2A",X"2A",X"2A",X"2A",X"2A",X"85",X"01",X"40",X"E4",X"C0", + X"CD",X"04",X"10",X"29",X"FF",X"49",X"C0",X"F0",X"2A",X"85",X"04",X"40",X"E4",X"C0",X"CD",X"04", + X"10",X"29",X"FF",X"45",X"04",X"F0",X"1C",X"40",X"E4",X"C0",X"CD",X"04",X"10",X"29",X"FF",X"45", + X"04",X"F0",X"10",X"40",X"E4",X"C0",X"CD",X"04",X"10",X"29",X"FF",X"45",X"04",X"F0",X"04",X"C9", + X"FF",X"85",X"00",X"8D",X"00",X"10",X"68",X"C8",X"68",X"CA",X"68",X"20",X"28",X"8A",X"28",X"98", + X"28",X"C5",X"00",X"F0",X"40",X"CD",X"04",X"10",X"49",X"C0",X"45",X"04",X"F0",X"37",X"E6",X"06", + X"C9",X"02",X"8D",X"02",X"10",X"C4",X"01",X"C5",X"03",X"A9",X"80",X"F0",X"2E",X"C2",X"00",X"CD", + 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East Cassette/Burnin Rubber_MiST/rtl/Roms/burnin_rubber_sound_prog.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity burnin_rubber_sound_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of burnin_rubber_sound_prog is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"78",X"D8",X"A2",X"FF",X"9A",X"A2",X"72",X"A9",X"00",X"95",X"00",X"CA",X"D0",X"FB",X"20",X"1D", + X"F0",X"AD",X"00",X"A0",X"A9",X"FF",X"8D",X"00",X"C0",X"58",X"4C",X"1A",X"F0",X"A2",X"0F",X"8E", + X"00",X"40",X"8E",X"00",X"80",X"BD",X"50",X"F0",X"8D",X"00",X"20",X"8D",X"00",X"60",X"CA",X"10", + X"EE",X"60",X"A2",X"0A",X"8E",X"00",X"40",X"BD",X"50",X"F0",X"8D",X"00",X"20",X"CA",X"10",X"F4", + X"60",X"A2",X"0A",X"8E",X"00",X"80",X"BD",X"50",X"F0",X"8D",X"00",X"60",X"CA",X"10",X"F4",X"60", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/fg_sp_graphx_2.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/fg_sp_graphx_2.vhd new file mode 100644 index 00000000..ad10ab3a --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/fg_sp_graphx_2.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity fg_sp_graphx_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of fg_sp_graphx_2 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/fg_sp_graphx_3.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/fg_sp_graphx_3.vhd new file mode 100644 index 00000000..ed0cb8c9 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/Roms/fg_sp_graphx_3.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity fg_sp_graphx_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of fg_sp_graphx_3 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/build_id.tcl b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/build_id.v b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/build_id.v new file mode 100644 index 00000000..c76bbf65 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171226" +`define BUILD_TIME "145326" diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber _sound.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber _sound.vhd new file mode 100644 index 00000000..8a619de8 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber _sound.vhd @@ -0,0 +1,426 @@ +--------------------------------------------------------------------------------- +-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity burnin_rubber_sound is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + sound_req : in std_logic; + sound_code_in : in std_logic_vector(7 downto 0); + sound_timing : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end burnin_rubber_sound; + +architecture syn of burnin_rubber_sound is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0'); + signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0'); + signal clock_500K : std_logic; + signal ayx_clock : std_logic; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_sync : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- sound req management + signal nmi_reg : std_logic; + signal nmi_reg_cs : std_logic; + signal nmi_reg_we : std_logic; + signal sound_code : std_logic_vector(7 downto 0); + signal sound_code_cs : std_logic; + + -- ay-3-8910 signal + signal ay1_bc1 : std_logic; + signal ay1_bdir : std_logic; + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_audio_muxed: std_logic_vector(7 downto 0); + signal ay1_chan_a: std_logic_vector(7 downto 0); + signal ay1_chan_b: std_logic_vector(7 downto 0); + signal ay1_chan_c: std_logic_vector(7 downto 0); + + signal ay2_bc1 : std_logic; + signal ay2_bdir : std_logic; + signal ay2_audio_chan : std_logic_vector(1 downto 0); + signal ay2_audio_muxed: std_logic_vector(7 downto 0); + signal ay2_chan_a: std_logic_vector(7 downto 0); + signal ay2_chan_b: std_logic_vector(7 downto 0); + signal ay2_chan_c: std_logic_vector(7 downto 0); + + -- digital filtering AY2 channel A + signal uin : integer range -256 to 255; + signal u3 : integer range -32768 to 32767; + signal u4 : integer range -32768 to 32767; + signal du3 : integer range -32768*4096 to 32767*4096; + signal du4 : integer range -32768*4096 to 32767*4096; + signal uout : integer range -32768 to 32767; + signal uout_lim : integer range -128 to 127; + +begin + +process (clock_12, cpu_sync) +begin + if rising_edge(clock_12) then + if cpu_sync = '1' then + dbg_cpu_addr <= cpu_addr(15 downto 0); + end if; + end if; +end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_div1 <= (others => '0'); + clock_div2 <= (others => '0'); + else + if rising_edge(clock_12) then + if clock_div1 = "111111111" then -- divide by 512 (23.437kHz) + clock_div1 <= "000000000"; + else + clock_div1 <= clock_div1 + '1'; + end if; + if clock_div2 = "10111" then -- divide by 24 + clock_div2 <= "00000"; + else + clock_div2 <= clock_div2 + '1'; + end if; + end if; + end if; +end process; + +clock_500K <= clock_div2(4); --12MHz/24 = 500kHz +ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz + +--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase") +-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w) +-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w) +-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w) +-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w) +-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r) +-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w) +-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM +--ADDRESS_MAP_END + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff +ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0'; +ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0'; +ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0'; +ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0'; +sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0'; +nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0'; +prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0'; + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0'; +nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0'; + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + sound_code when sound_code_cs = '1' else + X"FF"; + +-- regsiter sound code and irq management +process (clock_12) +begin + if rising_edge(clock_12) then + if sound_req = '1' then + sound_code <= sound_code_in; + cpu_irq_n <= '0'; + end if; + if sound_code_cs = '1' then + cpu_irq_n <= '1'; + end if; + end if; +end process; + +-- nmi autorisation management +process (reset, clock_12) +begin + if reset = '1' then + nmi_reg <= '0'; + else + if rising_edge(clock_12) then + if nmi_reg_we = '1' then + nmi_reg <= cpu_do(0); + end if; + end if; + end if; +end process; + +-- nmi +cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1'; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- AOP Rauch passe bande filter +-- +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- R1 = 5000; +-- R2 = 10000; +-- C3 = 0.068e-6; +-- C4 = 0.068e-6; +-- R5 = 47000; +-- +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 627 +-- +-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192 +-- = (u4-u3)*109 +-- +-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192 +-- = -u3(514+1027-109) - uin*1027 - u4*109 +-- = -(u4*109 + u3*1432 + uin*1027) +-- + +-- down sample to 23.437kHz and filter AY2 channel A +uin <= to_integer(unsigned(ay2_chan_a)); + +process (clock_12) +begin + if rising_edge(clock_12) then + + if clock_div1 = "000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin + end if; + + if clock_div1 = "000000001" then + u3 <= u3 + du3/8192; + u4 <= u4 - du4/8192; + end if; + + if clock_div1 = "000000010" then + uout <= (u4 - u3) / 8; -- adjust output gain + end if; + + -- limit signed dynamique before return to unsigned + if clock_div1 = "000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div1 = "000000100" then + + audio_out <= ("000"&ay1_chan_a(7 downto 0)) + + ("000"&ay1_chan_b(7 downto 0)) + + ("000"&ay1_chan_c(7 downto 0)) + + ("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+ + ("000"&ay2_chan_b(7 downto 0)) + + ("000"&ay2_chan_c(7 downto 0)); + end if; + + end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => '1', + Clk => clock_500K, + Rdy => '1', + Abort_n => '1', + IRQ_n => cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr(10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.burnin_rubber_sound_prog +port map( + clk => clock_12n, + addr => cpu_addr(11 downto 0), + data => prog_rom_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => X"00", -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => X"00", -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => open, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => '0', -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end SYN; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber.vhd new file mode 100644 index 00000000..06231f08 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber.vhd @@ -0,0 +1,817 @@ +--------------------------------------------------------------------------------- +-- burnin rubber by Dar (darfpga@aol.fr) (05/12/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T65(b) core.Ver 301 by MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity burnin_rubber is +port +( + clock_12 : in std_logic; + reset : in std_logic; + + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + + video_hs : out std_logic; + video_vs : out std_logic; + video_blankn : out std_logic; + video_csync : out std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + + fire1 : in std_logic; + right1 : in std_logic; + left1 : in std_logic; + down1 : in std_logic; + up1 : in std_logic; + + fire2 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + down2 : in std_logic; + up2 : in std_logic; + + dbg_cpu_addr: out std_logic_vector(15 downto 0) + ); +end burnin_rubber; + +architecture syn of burnin_rubber is + + -- clocks, reset + signal clock_12n : std_logic; + signal clock_6 : std_logic := '0'; + signal reset_n : std_logic; + + -- cpu signals + signal cpu_addr : std_logic_vector(23 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_di_dec : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw_n : std_logic; + signal cpu_nmi_n : std_logic; + signal cpu_sync : std_logic; + signal cpu_ena : std_logic; + + -- program rom signals + signal prog_rom_cs : std_logic; + signal prog_rom_do : std_logic_vector(7 downto 0); + + -- working ram signals + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + -- foreground ram signals + signal fg_ram_cs : std_logic; + signal fg_ram_low_we : std_logic; + signal fg_ram_high_we : std_logic; + signal fg_ram_addr_sel : std_logic_vector(1 downto 0); + signal fg_ram_addr : std_logic_vector(9 downto 0); + signal fg_ram_low_do : std_logic_vector(7 downto 0); + signal fg_ram_high_do : std_logic_vector(1 downto 0); + + + -- video scan counter + signal hcnt : std_logic_vector(8 downto 0); + signal vcnt : std_logic_vector(8 downto 0); + signal hsync0 : std_logic; + signal hsync1 : std_logic; + signal hsync2 : std_logic; + signal csync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic; + + signal hcnt_flip : std_logic_vector(8 downto 0); + signal vcnt_flip : std_logic_vector(8 downto 0); + signal cocktail_we : std_logic; + signal cocktail_flip : std_logic := '0'; + signal hcnt8_r : std_logic; + signal hcnt8_rr : std_logic; + + -- io + signal io_cs : std_logic; + signal dip_sw1 : std_logic_vector(7 downto 0); + signal dip_sw2 : std_logic_vector(7 downto 0); + signal btn_p1 : std_logic_vector(7 downto 0); + signal btn_p2 : std_logic_vector(7 downto 0); + signal btn_system : std_logic_vector(7 downto 0); + + -- foreground and sprite graphix + signal sprite_attr : std_logic_vector( 2 downto 0); + signal sprite_tile : std_logic_vector( 7 downto 0); + signal sprite_line : std_logic_vector( 7 downto 0); + signal sprite_buffer_addr : std_logic_vector( 7 downto 0); + signal sprite_buffer_addr_flip : std_logic_vector( 7 downto 0); + signal sprite_buffer_di : std_logic_vector( 2 downto 0); + signal sprite_buffer_do : std_logic_vector( 2 downto 0); + signal fg_grphx_addr : std_logic_vector(12 downto 0); + signal fg_grphx_addr_early : std_logic_vector(12 downto 0); + signal fg_grphx_1_do : std_logic_vector( 7 downto 0); + signal fg_grphx_2_do : std_logic_vector( 7 downto 0); + signal fg_grphx_3_do : std_logic_vector( 7 downto 0); + signal fg_sp_grphx_1 : std_logic_vector( 7 downto 0); + signal fg_sp_grphx_2 : std_logic_vector( 7 downto 0); + signal fg_sp_grphx_3 : std_logic_vector( 7 downto 0); + signal display_tile : std_logic; + signal fg_low_priority : std_logic; + signal fg_sp_bits : std_logic_vector( 2 downto 0); + signal sp_bits_out : std_logic_vector( 2 downto 0); + signal fg_bits : std_logic_vector( 2 downto 0); + + -- color palette + signal palette_addr : std_logic_vector(3 downto 0); + signal palette_cs : std_logic; + signal palette_we : std_logic; + signal palette_do : std_logic_vector(7 downto 0); + + -- background ram + signal bg_ram_addr : std_logic_vector(9 downto 0); + signal bg_ram_cs : std_logic; + signal bg_ram_we : std_logic; + signal bg_ram_do : std_logic_vector(3 downto 0); + + -- background control + signal bport_cs : std_logic; + signal bport_we : std_logic; + signal scroll1 : std_logic_vector(3 downto 0); + signal bshift_cs : std_logic; + signal bshift_we : std_logic; + signal scroll2 : std_logic_vector(7 downto 0); + + signal bg_hcnt : std_logic_vector( 7 downto 0); + signal bg_scan_hcnt : std_logic_vector( 8 downto 0); + signal bg_scan_addr : std_logic_vector( 9 downto 0); + signal bg_grphx_addr : std_logic_vector(11 downto 0); + signal bg_grphx_1_do : std_logic_vector( 7 downto 0); + signal bg_grphx_2_do : std_logic_vector( 7 downto 0); + signal bg_grphx_1 : std_logic_vector( 7 downto 0); + signal bg_grphx_2 : std_logic_vector( 3 downto 0); + signal bg_bits : std_logic_vector( 2 downto 0); + signal bg_bits_skew_0: std_logic_vector( 2 downto 0); + signal bg_bits_skew_1: std_logic_vector( 2 downto 0); + signal bg_bits_skew_2: std_logic_vector( 2 downto 0); + signal bg_bits_skew_3: std_logic_vector( 2 downto 0); + signal bg_bits_skew_4: std_logic_vector( 2 downto 0); + signal bg_bits_skew_5: std_logic_vector( 2 downto 0); + + -- misc + signal raz_nmi_we : std_logic; + signal coin1_r : std_logic; + signal sound_req : std_logic; + +begin + +--process (clock_12, cpu_sync) +--begin +-- if rising_edge(clock_12) then +-- if cpu_sync = '1' then +-- dbg_cpu_addr <= cpu_addr(15 downto 0); +-- end if; +-- end if; +--end process; + +reset_n <= not reset; +clock_12n <= not clock_12; + +process (clock_12, reset) + begin + if reset='1' then + clock_6 <= '0'; + else + if rising_edge(clock_12) then + clock_6 <= not clock_6; + end if; + end if; +end process; + +------------------- +-- Video scanner -- +------------------- + +-- make hcnt and vcnt video scanner (from schematics !) +-- +-- hcnt [0..255,256..383] => 384 pixels, 384/6Mhz => 1 line is 64us (15.625KHz) +-- vcnt [8..255,256..279] => 272 lines, 1 frame is 272 x 64us = 17.41ms (57.44Hz) + +process (reset, clock_12) +begin + if reset='1' then + hcnt <= (others => '0'); + vcnt <= (others => '0'); + else + if rising_edge(clock_12) and clock_6 = '1' then + hcnt <= hcnt + '1'; + if hcnt = 383 then + hcnt <= (others => '0'); + if vcnt = 260 then -- total should be 272 from Bump&Jump schematics ! + vcnt <= (others => '0'); + else + vcnt <= vcnt + '1'; + end if; + end if; + end if; + + end if; +end process; + +hcnt_flip <= hcnt when cocktail_flip = '0' else not hcnt; +vcnt_flip <= not vcnt when cocktail_flip = '0' else vcnt; + +--static ADDRESS_MAP_START( bnj_map, AS_PROGRAM, 8, btime_state ) +-- AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("rambase") +-- AM_RANGE(0x1000, 0x1000) AM_READ_PORT("DSW1") +-- AM_RANGE(0x1001, 0x1001) AM_READ_PORT("DSW2") AM_WRITE(bnj_video_control_w) +-- AM_RANGE(0x1002, 0x1002) AM_READ_PORT("P1") AM_WRITE(audio_command_w) +-- AM_RANGE(0x1003, 0x1003) AM_READ_PORT("P2") +-- AM_RANGE(0x1004, 0x1004) AM_READ_PORT("SYSTEM") +-- AM_RANGE(0x4000, 0x43ff) AM_RAM AM_SHARE("videoram") +-- AM_RANGE(0x4400, 0x47ff) AM_RAM AM_SHARE("colorram") +-- AM_RANGE(0x4800, 0x4bff) AM_READWRITE(btime_mirrorvideoram_r, btime_mirrorvideoram_w) +-- AM_RANGE(0x4c00, 0x4fff) AM_READWRITE(btime_mirrorcolorram_r, btime_mirrorcolorram_w) +-- AM_RANGE(0x5000, 0x51ff) AM_RAM_WRITE(bnj_background_w) AM_SHARE("bnj_bgram") +-- AM_RANGE(0x5200, 0x53ff) AM_RAM +-- AM_RANGE(0x5400, 0x5400) AM_WRITE(bnj_scroll1_w) +-- AM_RANGE(0x5800, 0x5800) AM_WRITE(bnj_scroll2_w) +-- AM_RANGE(0x5c00, 0x5c0f) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") +-- AM_RANGE(0xa000, 0xffff) AM_ROM +--ADDRESS_MAP_END + +--ROM_START( brubber ) +-- ROM_REGION( 0x10000, "maincpu", 0 ) +-- /* a000-bfff space for the service ROM */ +-- ROM_LOAD( "brubber.12c", 0xc000, 0x2000, CRC(b5279c70) SHA1(5fb1c50040dc4e9444aed440e2c3cf4c79b72311) ) +-- ROM_LOAD( "brubber.12d", 0xe000, 0x2000, CRC(b2ce51f5) SHA1(5e38ea24bcafef1faba023def96532abd6f97d38) ) +-- +-- ROM_REGION( 0x10000, "audiocpu", 0 ) +-- ROM_LOAD( "bnj6c.bin", 0xe000, 0x1000, CRC(8c02f662) SHA1(1279d564e65fd3ccac25b1f9fbb40d910de2b544) ) +-- +-- ROM_REGION( 0x6000, "gfx1", 0 ) +-- ROM_LOAD( "bnj4e.bin", 0x0000, 0x2000, CRC(b864d082) SHA1(cacf71fa6c0f7121d077381a0ff6222f534295ab) ) +-- ROM_LOAD( "bnj4f.bin", 0x2000, 0x2000, CRC(6c31d77a) SHA1(5e52554f594f569527af4768d244cc40a7b4460a) ) +-- ROM_LOAD( "bnj4h.bin", 0x4000, 0x2000, CRC(5824e6fb) SHA1(e98f0eb476b8f033f5cc70a6e503afc4e651fd45) ) +-- +-- ROM_REGION( 0x2000, "gfx2", 0 ) +-- ROM_LOAD( "bnj10e.bin", 0x0000, 0x1000, CRC(f4e9eb49) SHA1(b356512d2ebd4e2005e76496b434e5ecebadb251) ) +-- ROM_LOAD( "bnj10f.bin", 0x1000, 0x1000, CRC(a9ffacb4) SHA1(49d5f9c0b695f474197fbb761bacc065b6b5808a) ) +--ROM_END + +-- dip_sw1 -- cocktail/unkown/unkown/test/coinage_b[2]/coinage_a[2] +-- dip_sw2 -- off/off/off/easy/no_continue/bonus[3]/lives +-- btn_p1 -- nu/nu/unkonw/jump/down/up/left/right +-- btn_p2 -- nu/nu/unkonw/jump/down/up/left/right +-- btn_system -- coin2/coin1/unkown/start2/start1/unknown/unknown/tilt + +dip_sw1 <= "00001111"; +dip_sw2 <= "00010111"; +btn_p1 <= not("000"&fire1 & down1 & up1 & left1 & right1); +btn_p2 <= not("000"&fire2 & down2 & up2 & left2 & right2); +btn_system <= not('0'&coin1&'0'&start2&start1&"000"); + +-- misc (coin, nmi, cocktail) +process (reset,clock_12) +begin + if reset = '1' then + cpu_nmi_n <= '1'; + cocktail_flip <= '0'; + else + if rising_edge(clock_12)then + coin1_r <= coin1; + if coin1_r = '0' and coin1 = '1' then + cpu_nmi_n <= '0'; + end if; + if raz_nmi_we = '1' then + cpu_nmi_n <= '1'; + end if; + if cocktail_we = '1' then + cocktail_flip <= dip_sw1(7) and cpu_do(0); + end if; + end if; + end if; +end process; + + +cpu_ena <= '1' when hcnt(2 downto 0) = "111" and clock_6 = '1' else '0'; + +-- chip select +wram_cs <= '1' when cpu_addr(15 downto 11) = "00000" else '0'; -- working ram 0000-07ff +io_cs <= '1' when cpu_addr(15 downto 3) = "0001000000000" else '0'; -- player/dip_sw 1000-1007 (1004) +fg_ram_cs <= '1' when cpu_addr(15 downto 12) = "0100" else '0'; -- foreground ram 4000-4fff +bg_ram_cs <= '1' when cpu_addr(15 downto 9) = "0101000" else '0'; -- background ram 5000-51ff +bport_cs <= '1' when cpu_addr(15 downto 8) = "01010100" else '0'; -- scroll 1 54xX +bshift_cs <= '1' when cpu_addr(15 downto 8) = "01011000" else '0'; -- scroll 2 58xX +palette_cs <= '1' when cpu_addr(15 downto 4) = "010111000000" else '0'; -- palette ram 5c00-5c0f +prog_rom_cs <= '1' when cpu_addr(15 downto 14) = "11" else '0'; -- program rom c000-ffff + +-- write enable +wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 0000-07ff +raz_nmi_we <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "000" and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 1000 +cocktail_we <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "001" and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 1001 +sound_req <= '1' when io_cs = '1' and cpu_addr(2 downto 0) = "010" and cpu_rw_n = '0' else '0'; -- 1002 +fg_ram_low_we <= '1' when fg_ram_cs = '1' and cpu_addr(10) = '0' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 4000-43ff & 4800-4bff +fg_ram_high_we <= '1' when fg_ram_cs = '1' and cpu_addr(10) = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 4400-47ff & 4c00-4fff +bg_ram_we <= '1' when bg_ram_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 5000-51ff +bport_we <= '1' when bport_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 54xx +bshift_we <= '1' when bshift_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 58XX +palette_we <= '1' when palette_cs = '1' and cpu_rw_n = '0' and cpu_ena = '1' else '0'; -- 5c00-5c0f + +-- cpu di mux +cpu_di <= wram_do when wram_cs = '1' else + prog_rom_do when prog_rom_cs = '1' else + vblank&dip_sw1(6 downto 0) when (io_cs = '1') and (cpu_addr(2 downto 0) = "000") else + dip_sw2 when (io_cs = '1') and (cpu_addr(2 downto 0) = "001") else + btn_p1 when (io_cs = '1') and (cpu_addr(2 downto 0) = "010") else + btn_p2 when (io_cs = '1') and (cpu_addr(2 downto 0) = "011") else + btn_system when (io_cs = '1') and (cpu_addr(2 downto 0) = "100") else + fg_ram_low_do when fg_ram_cs = '1' else + bg_ram_do&X"0" when bg_ram_cs = '1' else + X"FF"; + +-- decrypt fetched instruction +cpu_di_dec <= cpu_di when cpu_sync = '0' else + cpu_di(7) & cpu_di(5) & cpu_di(6) & cpu_di(4 downto 0); + +---------------------------- +-- foreground and sprites -- +---------------------------- + +-- foreground ram addr +fg_ram_addr_sel <= "00" when cpu_ena = '1' and cpu_addr(11) = '0' else + "01" when cpu_ena = '1' and cpu_addr(11) = '1' else + "10" when cpu_ena = '0' and hcnt(8) = '0' else + "11"; + +with fg_ram_addr_sel select +fg_ram_addr <= cpu_addr(4 downto 0) & cpu_addr(9 downto 5) when "00", -- cpu mirrored addressing + cpu_addr(9 downto 0) when "01", -- cpu normal addressing + vcnt_flip(7 downto 3) & hcnt_flip(7 downto 3) when "10", -- foreground tile scan addressing + "00000" & hcnt(6 downto 2) when others; -- sprite data scan addressing + +-- latch sprite data, +-- manage fg and sprite graphix rom address +-- manage sprite line buffer address +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + + if hcnt(3 downto 0) = "0000" then + sprite_attr <= fg_ram_low_do(2 downto 0); + end if; + if hcnt(3 downto 0) = "0100" then + sprite_tile <= fg_ram_low_do(7 downto 0); + end if; + if hcnt(3 downto 0) = "1000" then + if sprite_attr(1) = '0' then + sprite_line <= vcnt_flip(7 downto 0) - 1 + fg_ram_low_do(7 downto 0); + else + sprite_line <= (vcnt_flip(7 downto 0) - 1 + fg_ram_low_do(7 downto 0)) xor X"0F"; -- flip V + end if; + end if; + + if hcnt(2 downto 0) = "100" then + hcnt8_r <= hcnt(8); + fg_grphx_addr_early <= fg_ram_high_do & fg_ram_low_do & vcnt_flip(2 downto 0); -- fg_ram_low_do(7) = '1' => low priority foreground + if hcnt8_r = '1' then + fg_grphx_addr <= sprite_tile & not (sprite_attr(2) xor hcnt_flip(3) xor cocktail_flip) & sprite_line(3 downto 0); + if hcnt(3) = '1' then + if (sprite_line(7 downto 4) = "1111") and (sprite_attr(0) = '1') then + display_tile <= '1'; + else + display_tile <= '0'; + end if; + end if; + else + fg_grphx_addr <= fg_grphx_addr_early; + display_tile <= '1'; + end if; + end if; + + if hcnt8_r = '1' then + if hcnt(3 downto 0) = X"D" then + sprite_buffer_addr <= fg_ram_low_do(7 downto 0); + hcnt8_rr <= '1'; + else + sprite_buffer_addr <= sprite_buffer_addr + '1'; + end if; + else + if hcnt(7 downto 0) = X"0D" then + sprite_buffer_addr <= (others => '0'); + hcnt8_rr <= '0'; + else + sprite_buffer_addr <= sprite_buffer_addr + '1'; + end if; + end if; + + end if; +end process; + +sprite_buffer_addr_flip <= not (sprite_buffer_addr) when hcnt8_rr = '0' and cocktail_flip = '1' else sprite_buffer_addr; + +-- latch and shift foreground and sprite graphics +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + if hcnt(2 downto 0) = "101" then + if display_tile = '1' then + fg_sp_grphx_1 <= fg_grphx_1_do; + fg_sp_grphx_2 <= fg_grphx_2_do; + fg_sp_grphx_3 <= fg_grphx_3_do; + fg_low_priority <= fg_grphx_addr(10); -- #fg_ram_low_do(7) + else + fg_sp_grphx_1 <= (others =>'0'); + fg_sp_grphx_2 <= (others =>'0'); + fg_sp_grphx_3 <= (others =>'0'); + end if; + elsif cocktail_flip = '0' or hcnt8_rr = '1' then + fg_sp_grphx_1 <= '0' & fg_sp_grphx_1(7 downto 1); + fg_sp_grphx_2 <= '0' & fg_sp_grphx_2(7 downto 1); + fg_sp_grphx_3 <= '0' & fg_sp_grphx_3(7 downto 1); + else + fg_sp_grphx_1 <= fg_sp_grphx_1(6 downto 0) & '0'; + fg_sp_grphx_2 <= fg_sp_grphx_2(6 downto 0) & '0'; + fg_sp_grphx_3 <= fg_sp_grphx_3(6 downto 0) & '0'; + end if; + end if; +end process; + +fg_sp_bits <= fg_sp_grphx_3(0) & fg_sp_grphx_2(0) & fg_sp_grphx_1(0) when cocktail_flip = '0' or hcnt8_rr = '1' else + fg_sp_grphx_3(7) & fg_sp_grphx_2(7) & fg_sp_grphx_1(7); + +-- data to sprite buffer +sprite_buffer_di <= "000" when hcnt8_rr = '0' else -- clear ram after read + sprite_buffer_do when fg_sp_bits = "000" else fg_sp_bits; -- sp vs sp priority rules + +-- read sprite buffer +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '0' then + if hcnt8_rr = '0' then + sp_bits_out <= sprite_buffer_do; + else + sp_bits_out <= "000"; + end if; + end if; +end process; + +-- mux foreground and sprite buffer output with priorities +fg_bits <= sp_bits_out when (fg_sp_bits = "000") or (sp_bits_out/="000" and fg_low_priority = '1') else fg_sp_bits; + +---------------- +-- background -- +---------------- +bg_hcnt(2 downto 0) <= hcnt_flip(2 downto 0); + +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + + -- M4H latch hcnt bit 3 to 7 (8 pixels delay) + if hcnt(2 downto 0) = "111" then + bg_hcnt(7 downto 3) <= hcnt_flip(7 downto 3); + end if; + + end if; +end process; + +-- latch scroll1 & 2 data +process (clock_12n) +begin + if rising_edge(clock_12n) and clock_6 = '1' then + if bport_we = '1' then + scroll1 <= cpu_do(3 downto 0); + end if; + if bshift_we = '1' then + scroll2 <= cpu_do; + end if; + end if; +end process; + +-- manage background ram address +bg_scan_hcnt <= ('0'&bg_hcnt) + (scroll1(1)&scroll2); + +bg_scan_addr <= '0' & bg_scan_hcnt(8) & vcnt_flip(7) & bg_scan_hcnt(7 downto 4) & vcnt_flip(6 downto 4); + +bg_ram_addr <= cpu_addr(9 downto 0) when cpu_ena = '1' else bg_scan_addr; + +-- manage background rom address +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '0' then + if bg_scan_hcnt(1 downto 0) = "00" then + bg_grphx_addr <= '1' & vcnt_flip(7) & bg_ram_do & bg_scan_hcnt(3 downto 2) & vcnt_flip(3 downto 0); + end if; + end if; +end process; + +-- latch and shift background graphics +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + if scroll1 = "0000" then + bg_grphx_1 <= (others => '0'); + bg_grphx_2 <= (others => '0'); + else + if bg_scan_hcnt(1 downto 0) = "00" then + bg_grphx_1 <= bg_grphx_1_do; + bg_grphx_2 <= bg_grphx_2_do(3 downto 0); + elsif cocktail_flip = '0' then + bg_grphx_1 <= '0' & bg_grphx_1(7 downto 1); + bg_grphx_2 <= '0' & bg_grphx_2(3 downto 1); + else + bg_grphx_1 <= bg_grphx_1(6 downto 0) & '0'; + bg_grphx_2 <= bg_grphx_2(2 downto 0) & '0'; + end if; + end if; + end if; +end process; + +bg_bits_skew_0 <= bg_grphx_2(0) & bg_grphx_1(4) & bg_grphx_1(0) when cocktail_flip = '0' else + bg_grphx_2(3) & bg_grphx_1(7) & bg_grphx_1(3); + +-- delay background graphics w.r.t. foreground graphics +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '1' then + bg_bits_skew_1 <= bg_bits_skew_0; + bg_bits_skew_2 <= bg_bits_skew_1; + bg_bits_skew_3 <= bg_bits_skew_2; + bg_bits_skew_4 <= bg_bits_skew_3; + bg_bits_skew_5 <= bg_bits_skew_4; + end if; +end process; + +-- manage color palette address +palette_addr <= cpu_addr(3 downto 0) when palette_we = '1' else + '1'&bg_bits_skew_4 when fg_bits = "000" else + '0'&fg_bits; + +-- get palette output +process (clock_12) +begin + if rising_edge(clock_12) and clock_6 = '0' then + video_r <= not palette_do(2 downto 0); + video_g <= not palette_do(5 downto 3); + video_b <= not palette_do(7 downto 6); + end if; +end process; + +---------------------------- +-- video syncs and blanks -- +---------------------------- + +video_csync <= csync; + +process(clock_12) + constant hcnt_base : integer := 312; --320 + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + +if rising_edge(clock_12) and clock_6 = '1' then + + if hcnt = hcnt_base+0 then hsync0 <= '0'; + elsif hcnt = hcnt_base+24 then hsync0 <= '1'; + end if; + + if hcnt = hcnt_base+0 then hsync1 <= '0'; + elsif hcnt = hcnt_base+12 then hsync1 <= '1'; + elsif hcnt = hcnt_base+192-384 then hsync1 <= '0'; + elsif hcnt = hcnt_base+204-384 then hsync1 <= '1'; + end if; + + if hcnt = hcnt_base+0 then hsync2 <= '0'; + elsif hcnt = hcnt_base+192-12-384 then hsync2 <= '1'; + elsif hcnt = hcnt_base+192-384 then hsync2 <= '0'; + elsif hcnt = hcnt_base+0-12 then hsync2 <= '1'; + end if; + + if hcnt = hcnt_base then + if vcnt = 240 then + vsync_cnt := X"0"; + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if; + end if; + end if; + + if vsync_cnt = 0 then csync <= hsync1; + elsif vsync_cnt = 1 then csync <= hsync1; + elsif vsync_cnt = 2 then csync <= hsync1; + elsif vsync_cnt = 3 then csync <= hsync2; + elsif vsync_cnt = 4 then csync <= hsync2; + elsif vsync_cnt = 5 then csync <= hsync2; + elsif vsync_cnt = 6 then csync <= hsync1; + elsif vsync_cnt = 7 then csync <= hsync1; + elsif vsync_cnt = 8 then csync <= hsync1; + else csync <= hsync0; + end if; + + if hcnt = 267 then hblank <= '1'; + elsif hcnt = 14 then hblank <= '0'; + end if; + + if vcnt = 248 then vblank <= '1'; + elsif vcnt = 8 then vblank <= '0'; + end if; + + -- external sync and blank outputs + video_blankn <= not (hblank or vblank); + + video_hs <= hsync0; + + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 8 then video_vs <= '1'; + end if; + +end if; +end process; + +--------------------------- +-- components +--------------------------- + +cpu_inst : entity work.T65 +port map +( + Mode => "00", -- 6502 + Res_n => reset_n, + Enable => cpu_ena, + Clk => clock_12, + Rdy => '1', + Abort_n => '1', + IRQ_n => '1',--cpu_irq_n, + NMI_n => cpu_nmi_n, + SO_n => '1',--cpu_so_n, + R_W_n => cpu_rw_n, + Sync => cpu_sync, -- open + EF => open, + MF => open, + XF => open, + ML_n => open, + VP_n => open, + VDA => open, + VPA => open, + A => cpu_addr, + DI => cpu_di_dec, + DO => cpu_do +); + + +-- working ram +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram_we, + addr => cpu_addr( 10 downto 0), + d => cpu_do, + q => wram_do +); + +-- program rom +program_rom: entity work.burnin_rubber_prog +port map( + clk => clock_12n, + addr => cpu_addr(13 downto 0), + data => prog_rom_do +); + +-- foreground ram low +fg_ram_low : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_12n, + we => fg_ram_low_we, + addr => fg_ram_addr, + d => cpu_do, + q => fg_ram_low_do +); + +-- foreground ram high +fg_ram_high : entity work.gen_ram +generic map( dWidth => 2, aWidth => 10) +port map( + clk => clock_12n, + we => fg_ram_high_we, + addr => fg_ram_addr, + d => cpu_do(1 downto 0), + q => fg_ram_high_do +); + +-- foreground and sprite graphix rom bit #1 +fg_sp_graphx_1: entity work.fg_sp_graphx_1 +port map( + clk => clock_12n, + addr => fg_grphx_addr, + data => fg_grphx_1_do +); + +-- foreground and sprite graphix rom bit #2 +fg_sp_graphx_2: entity work.fg_sp_graphx_2 +port map( + clk => clock_12n, + addr => fg_grphx_addr, + data => fg_grphx_2_do +); + +-- foreground and sprite graphix rom bit #3 +fg_sp_graphx_3: entity work.fg_sp_graphx_3 +port map( + clk => clock_12n, + addr => fg_grphx_addr, + data => fg_grphx_3_do +); + +-- sprite buffer ram +sprite_buffer_ram : entity work.gen_ram +generic map( dWidth => 3, aWidth => 8) +port map( + clk => clock_12n, + we => clock_6, + addr => sprite_buffer_addr_flip, + d => sprite_buffer_di, + q => sprite_buffer_do +); + +-- color palette ram +color_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 4) +port map( + clk => clock_12n, + we => palette_we, + addr => palette_addr, + d => cpu_do, + q => palette_do +); + +-- background ram +background_ram : entity work.gen_ram +generic map( dWidth => 4, aWidth => 10) +port map( + clk => clock_12n, + we => bg_ram_we, + addr => bg_ram_addr, + d => cpu_do(7 downto 4), + q => bg_ram_do +); + +-- background graphix rom bit #3&2 +bg_graphx_1: entity work.bg_graphx_1 +port map( + clk => clock_12n, + addr => bg_grphx_addr, + data => bg_grphx_1_do +); + +-- background graphix rom bit #1 +bg_graphx_2: entity work.bg_graphx_2 +port map( + clk => clock_12n, + addr => bg_grphx_addr, + data => bg_grphx_2_do +); + +-- burnin rubber sound part +burnin_rubber_sound: entity work.burnin_rubber_sound +port map( + clock_12 => clock_12, + reset => reset, + + sound_req => sound_req, + sound_code_in => cpu_do, + sound_timing => vcnt(3), + + audio_out => audio_out, + + dbg_cpu_addr => dbg_cpu_addr +); + +end SYN; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber_mist.sv b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber_mist.sv new file mode 100644 index 00000000..aa5d8daa --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/burnin_rubber_mist.sv @@ -0,0 +1,167 @@ +module burnin_rubber_mist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Burn.Rubb;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_48, clk_12, clk_6, clk_24; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_48), + .c1(clk_12), + .c2(clk_6), + .c3(clk_24) +); + +wire m_up = ~status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = ~status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = ~status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = ~status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +burnin_rubber burnin_rubber( + .clock_12(clk_12), + .reset(status[0] | status[6] | buttons[1]), + .video_r(r), + .video_g(g), + .video_b(b), + .video_csync(), + .video_blankn(blankn), + .video_hs(hs), + .video_vs(vs), + .audio_out(audio), + .start2(m_start2), + .start1(m_start1), + .coin1(m_coin), + .fire1(m_fire), + .right1(m_right), + .left1(m_left), + .down1(m_down), + .up1(m_up), + .fire2(m_fire), + .right2(m_right), + .left2(m_left), + .down2(m_down), + .up2(m_up), + .dbg_cpu_addr() +); + +wire [10:0] audio; + +dac dac ( + .clk_i(clk_48), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g; +wire [1:0] b; +wire blankn; + +video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_48), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? r&r : "000000"), + .G(blankn ? g&g : "000000"), + .B(blankn ? b&b : "0000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_48 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_48), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule + + + + diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/dac.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/gen_ram.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/hq2x.sv b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/keyboard.v b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/mist_io.v b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/osd.v b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/pll.qip b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/pll.v b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/pll.v new file mode 100644 index 00000000..fe052027 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/pll.v @@ -0,0 +1,396 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + c2, + c3); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output c3; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire c3 = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire6), + .clk (sub_wire0), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 16, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 4, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 9, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 2, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 9, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 8, + altpll_component.clk3_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/scandoubler.v b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65.vhd new file mode 100644 index 00000000..09253fe0 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65.vhd @@ -0,0 +1,564 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 more merging +-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust* +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 and 65C816 modes are incomplete +-- Undocumented instructions are not supported +-- Some interface signals behaves incorrect +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use work.T65_Pack.all; + +-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use +-- the ready signal to limit the CPU. +entity T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T65; + +architecture rtl of T65 is + + -- Registers + signal ABC, X, Y, D : std_logic_vector(15 downto 0); + signal P, AD, DL : std_logic_vector(7 downto 0) := x"00"; + signal BAH : std_logic_vector(7 downto 0); + signal BAL : std_logic_vector(8 downto 0); + signal PBR : std_logic_vector(7 downto 0); + signal DBR : std_logic_vector(7 downto 0); + signal PC : unsigned(15 downto 0); + signal S : unsigned(15 downto 0); + signal EF_i : std_logic; + signal MF_i : std_logic; + signal XF_i : std_logic; + + signal IR : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + + signal Mode_r : std_logic_vector(1 downto 0); + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Write_Data_r : std_logic_vector(2 downto 0); + signal Set_Addr_To_r : std_logic_vector(1 downto 0); + signal PCAdder : unsigned(8 downto 0); + + signal RstCycle : std_logic; + signal IRQCycle : std_logic; + signal NMICycle : std_logic; + + signal B_o : std_logic; + signal SO_n_o : std_logic; + signal IRQ_n_o : std_logic; + signal NMI_n_o : std_logic; + signal NMIAct : std_logic; + + signal Break : std_logic; + + -- ALU signals + signal BusA : std_logic_vector(7 downto 0); + signal BusA_r : std_logic_vector(7 downto 0); + signal BusB : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal P_Out : std_logic_vector(7 downto 0); + + -- Micro code outputs + signal LCycle : std_logic_vector(2 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(2 downto 0); + signal Set_Addr_To : std_logic_vector(1 downto 0); + signal Write_Data : std_logic_vector(2 downto 0); + signal Jump : std_logic_vector(1 downto 0); + signal BAAdd : std_logic_vector(1 downto 0); + signal BreakAtNA : std_logic; + signal ADAdd : std_logic; + signal AddY : std_logic; + signal PCAdd : std_logic; + signal Inc_S : std_logic; + signal Dec_S : std_logic; + signal LDA : std_logic; + signal LDP : std_logic; + signal LDX : std_logic; + signal LDY : std_logic; + signal LDS : std_logic; + signal LDDI : std_logic; + signal LDALU : std_logic; + signal LDAD : std_logic; + signal LDBAL : std_logic; + signal LDBAH : std_logic; + signal SaveP : std_logic; + signal Write : std_logic; + + signal really_rdy : std_logic; + signal R_W_n_i : std_logic; + +begin + -- ehenciak : gate Rdy with read/write to make an "OK, it's + -- really OK to stop the processor now if Rdy is + -- deasserted" signal + really_rdy <= Rdy or not(R_W_n_i); + + -- ehenciak : Drive R_W_n_i off chip. + R_W_n <= R_W_n_i; + + Sync <= '1' when MCycle = "000" else '0'; + EF <= EF_i; + MF <= MF_i; + XF <= XF_i; + ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; + VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! + VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! + + mcode : T65_MCode + port map( + Mode => Mode_r, + IR => IR, + MCycle => MCycle, + P => P, + LCycle => LCycle, + ALU_Op => ALU_Op, + Set_BusA_To => Set_BusA_To, + Set_Addr_To => Set_Addr_To, + Write_Data => Write_Data, + Jump => Jump, + BAAdd => BAAdd, + BreakAtNA => BreakAtNA, + ADAdd => ADAdd, + AddY => AddY, + PCAdd => PCAdd, + Inc_S => Inc_S, + Dec_S => Dec_S, + LDA => LDA, + LDP => LDP, + LDX => LDX, + LDY => LDY, + LDS => LDS, + LDDI => LDDI, + LDALU => LDALU, + LDAD => LDAD, + LDBAL => LDBAL, + LDBAH => LDBAH, + SaveP => SaveP, + Write => Write + ); + + alu : T65_ALU + port map( + Mode => Mode_r, + Op => ALU_Op_r, + BusA => BusA_r, + BusB => BusB, + P_In => P, + P_Out => P_Out, + Q => ALU_Q + ); + + process (Res_n, Clk) + begin + if Res_n = '0' then + PC <= (others => '0'); -- Program Counter + IR <= "00000000"; + S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!! + D <= (others => '0'); + PBR <= (others => '0'); + DBR <= (others => '0'); + + Mode_r <= (others => '0'); + ALU_Op_r <= "1100"; + Write_Data_r <= "000"; + Set_Addr_To_r <= "00"; + + R_W_n_i <= '1'; + EF_i <= '1'; + MF_i <= '1'; + XF_i <= '1'; + + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + R_W_n_i <= not Write or RstCycle; + + D <= (others => '1'); -- Dummy + PBR <= (others => '1'); -- Dummy + DBR <= (others => '1'); -- Dummy + EF_i <= '0'; -- Dummy + MF_i <= '0'; -- Dummy + XF_i <= '0'; -- Dummy + + if MCycle = "000" then + Mode_r <= Mode; + + if IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + + if IRQCycle = '1' or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DI; + end if; + end if; + + ALU_Op_r <= ALU_Op; + Write_Data_r <= Write_Data; + if Break = '1' then + Set_Addr_To_r <= "00"; + else + Set_Addr_To_r <= Set_Addr_To; + end if; + + if Inc_S = '1' then + S <= S + 1; + end if; + if Dec_S = '1' and RstCycle = '0' then + S <= S - 1; + end if; + if LDS = '1' then + S(7 downto 0) <= unsigned(ALU_Q); + end if; + + if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then + PC <= PC + 1; + end if; + -- + -- jump control logic + -- + case Jump is + when "01" => + PC <= PC + 1; + + when "10" => + PC <= unsigned(DI & DL); + + when "11" => + if PCAdder(8) = '1' then + if DL(7) = '0' then + PC(15 downto 8) <= PC(15 downto 8) + 1; + else + PC(15 downto 8) <= PC(15 downto 8) - 1; + end if; + end if; + PC(7 downto 0) <= PCAdder(7 downto 0); + + when others => null; + end case; + end if; + end if; + end if; + end process; + + PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' + else "0" & PC(7 downto 0); + + process (Clk) + begin + if Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = "000" then + if LDA = '1' then + ABC(7 downto 0) <= ALU_Q; + end if; + if LDX = '1' then + X(7 downto 0) <= ALU_Q; + end if; + if LDY = '1' then + Y(7 downto 0) <= ALU_Q; + end if; + if (LDA or LDX or LDY) = '1' then + P <= P_Out; + end if; + end if; + if SaveP = '1' then + P <= P_Out; + end if; + if LDP = '1' then + P <= ALU_Q; + end if; + if IR(4 downto 0) = "11000" then + case IR(7 downto 5) is + when "000" => + P(Flag_C) <= '0'; + when "001" => + P(Flag_C) <= '1'; + when "010" => + P(Flag_I) <= '0'; + when "011" => + P(Flag_I) <= '1'; + when "101" => + P(Flag_V) <= '0'; + when "110" => + P(Flag_D) <= '0'; + when "111" => + P(Flag_D) <= '1'; + when others => + end case; + end if; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; + end if; + + if SO_n_o = '1' and SO_n = '0' then + P(Flag_V) <= '1'; + end if; + if RstCycle = '1' and Mode_r /= "00" then + P(Flag_1) <= '1'; + P(Flag_D) <= '0'; + P(Flag_I) <= '1'; + end if; + P(Flag_1) <= '1'; + + B_o <= P(Flag_B); + SO_n_o <= SO_n; + IRQ_n_o <= IRQ_n; + NMI_n_o <= NMI_n; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + BusA_r <= (others => '0'); + BusB <= (others => '0'); + AD <= (others => '0'); + BAL <= (others => '0'); + BAH <= (others => '0'); + DL <= (others => '0'); + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (Rdy = '1') then + BusA_r <= BusA; + BusB <= DI; + + case BAAdd is + when "01" => + -- BA Inc + AD <= std_logic_vector(unsigned(AD) + 1); + BAL <= std_logic_vector(unsigned(BAL) + 1); + when "10" => + -- BA Add + BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9)); + when "11" => + -- BA Adj + if BAL(8) = '1' then + BAH <= std_logic_vector(unsigned(BAH) + 1); + end if; + when others => + end case; + + -- ehenciak : modified to use Y register as well (bugfix) + if ADAdd = '1' then + if (AddY = '1') then + AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0))); + else + AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0))); + end if; + end if; + + if IR = "00000000" then + BAL <= (others => '1'); + BAH <= (others => '1'); + if RstCycle = '1' then + BAL(2 downto 0) <= "100"; + elsif NMICycle = '1' then + BAL(2 downto 0) <= "010"; + else + BAL(2 downto 0) <= "110"; + end if; + if Set_addr_To_r = "11" then + BAL(0) <= '1'; + end if; + end if; + + + if LDDI = '1' then + DL <= DI; + end if; + if LDALU = '1' then + DL <= ALU_Q; + end if; + if LDAD = '1' then + AD <= DI; + end if; + if LDBAL = '1' then + BAL(7 downto 0) <= DI; + end if; + if LDBAH = '1' then + BAH <= DI; + end if; + end if; + end if; + end if; + end process; + + Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8)); + + + with Set_BusA_To select + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; + + with Set_Addr_To_r select + A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", + DBR & "00000000" & AD when "10", + "00000000" & BAH & BAL(7 downto 0) when "11", + PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others; + + with Write_Data_r select + DO <= DL when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + std_logic_vector(PC(7 downto 0)) when "110", + std_logic_vector(PC(15 downto 8)) when others; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + + process (Res_n, Clk) + begin + if Res_n = '0' then + MCycle <= "001"; + RstCycle <= '1'; + IRQCycle <= '0'; + NMICycle <= '0'; + NMIAct <= '0'; + elsif Clk'event and Clk = '1' then + if (Enable = '1') then + if (really_rdy = '1') then + if MCycle = LCycle or Break = '1' then + MCycle <= "000"; + RstCycle <= '0'; + IRQCycle <= '0'; + NMICycle <= '0'; + if NMIAct = '1' then + NMICycle <= '1'; + elsif IRQ_n_o = '0' and P(Flag_I) = '0' then + IRQCycle <= '1'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + + if NMICycle = '1' then + NMIAct <= '0'; + end if; + if NMI_n_o = '1' and NMI_n = '0' then + NMIAct <= '1'; + end if; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_ALU.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_ALU.vhd new file mode 100644 index 00000000..b1f6d632 --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_ALU.vhd @@ -0,0 +1,260 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 6502 compatible microprocessor core +-- +-- Version : 0245 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0245 : First version +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_ALU is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); +end T65_ALU; + +architecture rtl of T65_ALU is + + -- AddSub variables (temporary signals) + signal ADC_Z : std_logic; + signal ADC_C : std_logic; + signal ADC_V : std_logic; + signal ADC_N : std_logic; + signal ADC_Q : std_logic_vector(7 downto 0); + signal SBC_Z : std_logic; + signal SBC_C : std_logic; + signal SBC_V : std_logic; + signal SBC_N : std_logic; + signal SBC_Q : std_logic_vector(7 downto 0); + +begin + + process (P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(6 downto 0); + variable C : std_logic; + begin + AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7); + AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + ADC_Z <= '1'; + else + ADC_Z <= '0'; + end if; + + if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AL(6 downto 1) := AL(6 downto 1) + 6; + end if; + + C := AL(6) or AL(5); + AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7); + + ADC_N <= AH(4); + ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7)); + +-- pragma translate_off + if is_x(std_logic_vector(AH)) then AH := "0000000"; end if; +-- pragma translate_on + + if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then + AH(6 downto 1) := AH(6 downto 1) + 6; + end if; + + ADC_C <= AH(6) or AH(5); + + ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB) + variable AL : unsigned(6 downto 0); + variable AH : unsigned(5 downto 0); + variable C : std_logic; + begin + C := P_In(Flag_C) or not Op(0); + AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6); + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6); + +-- pragma translate_off + if is_x(std_logic_vector(AL)) then AL := "0000000"; end if; + if is_x(std_logic_vector(AH)) then AH := "000000"; end if; +-- pragma translate_on + + if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then + SBC_Z <= '1'; + else + SBC_Z <= '0'; + end if; + + SBC_C <= not AH(5); + SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7)); + SBC_N <= AH(4); + + if P_In(Flag_D) = '1' then + if AL(5) = '1' then + AL(5 downto 1) := AL(5 downto 1) - 6; + end if; + AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6); + if AH(5) = '1' then + AH(5 downto 1) := AH(5 downto 1) - 6; + end if; + end if; + + SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1)); + end process; + + process (Op, P_In, BusA, BusB, + ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q, + SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q) + variable Q_t : std_logic_vector(7 downto 0); + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + P_Out <= P_In; + Q_t := BusA; + case Op(3 downto 0) is + when "0000" => + -- ORA + Q_t := BusA or BusB; + when "0001" => + -- AND + Q_t := BusA and BusB; + when "0010" => + -- EOR + Q_t := BusA xor BusB; + when "0011" => + -- ADC + P_Out(Flag_V) <= ADC_V; + P_Out(Flag_C) <= ADC_C; + Q_t := ADC_Q; + when "0101" | "1101" => + -- LDA + when "0110" => + -- CMP + P_Out(Flag_C) <= SBC_C; + when "0111" => + -- SBC + P_Out(Flag_V) <= SBC_V; + P_Out(Flag_C) <= SBC_C; + Q_t := SBC_Q; + when "1000" => + -- ASL + Q_t := BusA(6 downto 0) & "0"; + P_Out(Flag_C) <= BusA(7); + when "1001" => + -- ROL + Q_t := BusA(6 downto 0) & P_In(Flag_C); + P_Out(Flag_C) <= BusA(7); + when "1010" => + -- LSR + Q_t := "0" & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1011" => + -- ROR + Q_t := P_In(Flag_C) & BusA(7 downto 1); + P_Out(Flag_C) <= BusA(0); + when "1100" => + -- BIT + P_Out(Flag_V) <= BusB(6); + when "1110" => + -- DEC + Q_t := std_logic_vector(unsigned(BusA) - 1); + when "1111" => + -- INC + Q_t := std_logic_vector(unsigned(BusA) + 1); + when others => + end case; + + case Op(3 downto 0) is + when "0011" => + P_Out(Flag_N) <= ADC_N; + P_Out(Flag_Z) <= ADC_Z; + when "0110" | "0111" => + P_Out(Flag_N) <= SBC_N; + P_Out(Flag_Z) <= SBC_Z; + when "0100" => + when "1100" => + P_Out(Flag_N) <= BusB(7); + if (BusA and BusB) = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + when others => + P_Out(Flag_N) <= Q_t(7); + if Q_t = "00000000" then + P_Out(Flag_Z) <= '1'; + else + P_Out(Flag_Z) <= '0'; + end if; + end case; + + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_MCode.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_MCode.vhd new file mode 100644 index 00000000..6c6c864a --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_MCode.vhd @@ -0,0 +1,1052 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 302 minor timing fixes +-- Ver 301 Jump timing fixed +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 + fix +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- 65C02 +-- supported : inc, dec, phx, plx, phy, ply +-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8 +-- +-- File history : +-- +-- 0246 : First release +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T65_Pack.all; + +entity T65_MCode is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); +end T65_MCode; + +architecture rtl of T65_MCode is + + signal Branch : std_logic; + +begin + + with IR(7 downto 5) select + Branch <= not P(Flag_N) when "000", + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; + + process (IR, MCycle, P, Branch, Mode) + begin + LCycle <= "001"; + Set_BusA_To <= "001"; -- A + Set_Addr_To <= (others => '0'); + Write_Data <= (others => '0'); + Jump <= (others => '0'); + BAAdd <= "00"; + BreakAtNA <= '0'; + ADAdd <= '0'; + PCAdd <= '0'; + Inc_S <= '0'; + Dec_S <= '0'; + LDA <= '0'; + LDP <= '0'; + LDX <= '0'; + LDY <= '0'; + LDS <= '0'; + LDDI <= '0'; + LDALU <= '0'; + LDAD <= '0'; + LDBAL <= '0'; + LDBAH <= '0'; + SaveP <= '0'; + Write <= '0'; + AddY <= '0'; + + case IR(7 downto 5) is + when "100" => + --{{{ + case IR(1 downto 0) is + when "00" => + Set_BusA_To <= "011"; -- Y + Write_Data <= "011"; -- Y + when "10" => + Set_BusA_To <= "010"; -- X + Write_Data <= "010"; -- X + when others => + Write_Data <= "001"; -- A + end case; + --}}} + when "101" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) /= '1' or IR(2) /= '0' then + LDY <= '1'; + end if; + when "10" => + LDX <= '1'; + when others => + LDA <= '1'; + end case; + Set_BusA_To <= "000"; -- DI + --}}} + when "110" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDY <= '1'; + end if; + Set_BusA_To <= "011"; -- Y + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when "111" => + --{{{ + case IR(1 downto 0) is + when "00" => + if IR(4) = '0' then + LDX <= '1'; + end if; + Set_BusA_To <= "010"; -- X + when others => + Set_BusA_To <= "001"; -- A + end case; + --}}} + when others => + end case; + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + Set_BusA_To <= "000"; -- DI + end if; + + case IR(4 downto 0) is + when "00000" | "01000" | "01010" | "11000" | "11010" => + --{{{ + -- Implied + case IR is + when "00000000" => + -- BRK + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 2 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "101"; -- P + Write <= '1'; + when 4 => + Dec_S <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDDI <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + Jump <= "10"; -- DIDL + when others => + end case; + when "00100000" => + -- JSR + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Set_Addr_To <= "01"; -- S + Write_Data <= "111"; -- PCH + Write <= '1'; + when 3 => + Dec_S <= '1'; + Set_Addr_To <= "01"; -- S + Write_Data <= "110"; -- PCL + Write <= '1'; + when 4 => + Dec_S <= '1'; + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01000000" => + -- RTI + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + Set_BusA_To <= "000"; -- DI + when 4 => + LDP <= '1'; + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 5 => + Jump <= "10"; -- DIDL + when others => + end case; + when "01100000" => + -- RTS + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Inc_S <= '1'; + LDDI <= '1'; + Set_Addr_To <= "01"; -- S + when 4 => + Jump <= "10"; -- DIDL + when 5 => + Jump <= "01"; + when others => + end case; + when "00001000" | "01001000" | "01011010" | "11011010" => + -- PHP, PHA, PHY*, PHX* + LCycle <= "010"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + case IR(7 downto 4) is + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => + end case; + Write <= '1'; + Set_Addr_To <= "01"; -- S + when 2 => + Dec_S <= '1'; + when others => + end case; + when "00101000" | "01101000" | "01111010" | "11111010" => + -- PLP, PLA, PLY*, PLX* + LCycle <= "011"; + if Mode = "00" and IR(1) = '1' then + LCycle <= "001"; + end if; + case IR(7 downto 4) is + when "0010" => + LDP <= '1'; + when "0110" => + LDA <= '1'; + when "0111" => + if Mode /= "00" then + LDY <= '1'; + end if; + when "1111" => + if Mode /= "00" then + LDX <= '1'; + end if; + when others => + end case; + case to_integer(unsigned(MCycle)) is + when 0 => + SaveP <= '1'; + when 1 => + Set_Addr_To <= "01"; -- S + when 2 => + Inc_S <= '1'; + Set_Addr_To <= "01"; -- S + when 3 => + Set_BusA_To <= "000"; -- DI + when others => + end case; + when "10100000" | "11000000" | "11100000" => + -- LDY, CPY, CPX + -- Immediate + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + when "10001000" => + -- DEY + LDY <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "011"; -- Y + when others => + end case; + when "11001010" => + -- DEX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "010"; -- X + when others => + end case; + when "00011010" | "00111010" => + -- INC*, DEC* + if Mode /= "00" then + LDA <= '1'; -- A + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + when "00001010" | "00101010" | "01001010" | "01101010" => + -- ASL, ROL, LSR, ROR + LDA <= '1'; -- A + Set_BusA_To <= "001"; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10001010" | "10011000" => + -- TYA, TXA + LDA <= '1'; -- A + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + when others => + end case; + when "10101010" | "10101000" => + -- TAX, TAY + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "001"; -- A + when others => + end case; + when "10011010" => + -- TXS + case to_integer(unsigned(MCycle)) is + when 0 => + LDS <= '1'; + when 1 => + when others => + end case; + when "10111010" => + -- TSX + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Set_BusA_To <= "100"; -- S + when others => + end case; + + -- when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" => + -- -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX + -- case to_integer(unsigned(MCycle)) is + -- when 1 => + -- when others => + -- end case; + when others => + case to_integer(unsigned(MCycle)) is + when 0 => + when others => + end case; + end case; + --}}} + + when "00001" | "00011" => + --{{{ + -- Zero Page Indexed Indirect (d,x) + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + BAAdd <= "01"; -- DB Inc + LDBAL <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "01001" | "01011" => + --{{{ + -- Immediate + LDA <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + when others => + end case; + + --}}} + + when "00010" | "10010" => + --{{{ + -- Immediate, KIL + LDX <= '1'; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + if IR = "10100010" then + -- LDX + Jump <= "01"; + else + -- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!! + end if; + when others => + end case; + --}}} + + when "00100" => + --{{{ + -- Zero Page + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + --}}} + + when "00101" | "00110" | "00111" => + --{{{ + -- Zero Page + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + when others => + end case; + else + LCycle <= "010"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 2 => + when others => + end case; + end if; + --}}} + + when "01100" => + --{{{ + -- Absolute + if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then + -- JMP + if IR(5) = '0' then + --LCycle <= "011"; + LCycle <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + when 2 => + Jump <= "10"; -- DIDL + when others => + end case; + else + --LCycle <= "101"; + LCycle <= "100"; -- mikej + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDDI <= '1'; + LDBAL <= '1'; + when 2 => + LDBAH <= '1'; + if Mode /= "00" then + Jump <= "10"; -- DIDL + end if; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + end if; + when 3 => + LDDI <= '1'; + if Mode = "00" then + Set_Addr_To <= "11"; -- BA + BAAdd <= "01"; -- DB Inc + else + Jump <= "01"; + end if; + when 4 => + Jump <= "10"; -- DIDL + when others => + end case; + end if; + else + LCycle <= "011"; + case to_integer(unsigned(MCycle)) is + when 0 => + if IR(7 downto 5) = "001" then + SaveP <= '1'; + end if; + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "01101" | "01110" | "01111" => + --{{{ + -- Absolute + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + Write <= '1'; + LDALU <= '1'; + SaveP <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + SaveP <= '0'; -- MIKEJ was 1 + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + LDBAH <= '1'; + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 3 => + when others => + end case; + end if; + --}}} + + when "10000" => + --{{{ + -- Relative + + -- This circuit dictates when the last + -- microcycle occurs for the branch depending on + -- whether or not the branch is taken and if a page + -- is crossed... + if (Branch = '1') then + + LCycle <= "011"; -- We're done @ T3 if branching...upper + -- level logic will stop at T2 if no page cross + -- (See the Break signal) + else + + LCycle <= "001"; + + end if; + + -- This decodes the current microcycle and takes the + -- proper course of action... + case to_integer(unsigned(MCycle)) is + + -- On the T1 microcycle, increment the program counter + -- and instruct the upper level logic to fetch the offset + -- from the Din bus and store it in the data latches. This + -- will be the last microcycle if the branch isn't taken. + when 1 => + + Jump <= "01"; -- Increments the PC by one (PC will now be PC+2) + -- from microcycle T0. + + LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route + -- the Din bus to the memory data latch (DL) + -- so that the branch offset is fetched. + + -- In microcycle T2, tell the logic in the top level to + -- add the offset. If the most significant byte of the + -- program counter (i.e. the current "page") does not need + -- updating, we are done here...the Break signal at the + -- T65.vhd level takes care of that... + when 2 => + + Jump <= "11"; -- Tell the PC Jump logic to use relative mode. + + PCAdd <= '1'; -- This tells the PC adder to update itself with + -- the current offset recently fetched from + -- memory. + + -- The following is microcycle T3 : + -- The program counter should be completely updated + -- on this cycle after the page cross is detected. + -- We don't need to do anything here... + when 3 => + + + when others => null; -- Do nothing. + + end case; + --}}} + + when "10001" | "10011" => + --{{{ + -- Zero Page Indirect Indexed (d),y + LCycle <= "101"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + LDBAL <= '1'; + BAAdd <= "01"; -- DB Inc + Set_Addr_To <= "10"; -- AD + when 3 => + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 4 => + BAAdd <= "11"; -- BA Adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 5 => + when others => + end case; + --}}} + + when "10100" | "10101" | "10110" | "10111" => + --{{{ + -- Zero Page, X + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + Set_Addr_To <= "10"; -- AD + when 3 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 4 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "10"; -- AD + when 5 => + when others => + end case; + else + LCycle <= "011"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDAD <= '1'; + Set_Addr_To <= "10"; -- AD + when 2 => + ADAdd <= '1'; + -- Added this check for Y reg. use... + if (IR(3 downto 0) = "0110") then + AddY <= '1'; + end if; + + if IR(7 downto 5) = "100" then + Write <= '1'; + end if; + Set_Addr_To <= "10"; -- AD + when 3 => null; + when others => + end case; + end if; + --}}} + + when "11001" | "11011" => + --{{{ + -- Absolute Y + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "011"; -- Y + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + --}}} + + when "11100" | "11101" | "11110" | "11111" => + --{{{ + -- Absolute X + + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + -- Read-Modify-Write + LCycle <= "110"; + case to_integer(unsigned(MCycle)) is + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + Set_BusA_To <= "010"; -- X + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + Set_Addr_To <= "11"; -- BA + when 4 => + LDDI <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 5 => + LDALU <= '1'; + SaveP <= '1'; + Write <= '1'; + Set_Addr_To <= "11"; -- BA + when 6 => + when others => + end case; + else + LCycle <= "100"; + if IR(7 downto 6) /= "10" then + LDA <= '1'; + end if; + case to_integer(unsigned(MCycle)) is + when 0 => + when 1 => + Jump <= "01"; + LDBAL <= '1'; + when 2 => + Jump <= "01"; + -- mikej + -- special case 0xBE which uses Y reg as index!! + if (IR = "10111110") then + Set_BusA_To <= "011"; -- Y + else + Set_BusA_To <= "010"; -- X + end if; + BAAdd <= "10"; -- BA Add + LDBAH <= '1'; + Set_Addr_To <= "11"; -- BA + when 3 => + BAAdd <= "11"; -- BA adj + if IR(7 downto 5) = "100" then + Write <= '1'; + else + BreakAtNA <= '1'; + end if; + Set_Addr_To <= "11"; -- BA + when 4 => + when others => + end case; + end if; + --}}} + when others => + end case; + end process; + + process (IR, MCycle) + begin + -- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC + -- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC + case IR(1 downto 0) is + when "00" => + --{{{ + case IR(4 downto 2) is + when "000" | "001" | "011" => + case IR(7 downto 5) is + when "110" | "111" => + -- CP + ALU_Op <= "0110"; + when "101" => + -- LD + ALU_Op <= "0101"; + when "001" => + -- BIT + ALU_Op <= "1100"; + when others => + -- NOP/ST + ALU_Op <= "0100"; + end case; + when "010" => + case IR(7 downto 5) is + when "111" | "110" => + -- IN + ALU_Op <= "1111"; + when "100" => + -- DEY + ALU_Op <= "1110"; + when others => + -- LD + ALU_Op <= "1101"; + end case; + when "110" => + case IR(7 downto 5) is + when "100" => + -- TYA + ALU_Op <= "1101"; + when others => + ALU_Op <= "----"; + end case; + when others => + case IR(7 downto 5) is + when "101" => + -- LD + ALU_Op <= "1101"; + when others => + ALU_Op <= "0100"; + end case; + end case; + --}}} + when "01" => -- OR + --{{{ + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + --}}} + when "10" => + --{{{ + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + case IR(7 downto 5) is + when "000" => + if IR(4 downto 2) = "110" then + -- INC + ALU_Op <= "1111"; + end if; + when "001" => + if IR(4 downto 2) = "110" then + -- DEC + ALU_Op <= "1110"; + end if; + when "100" => + if IR(4 downto 2) = "010" then + -- TXA + ALU_Op <= "0101"; + else + ALU_Op <= "0100"; + end if; + when others => + end case; + --}}} + when others => + --{{{ + case IR(7 downto 5) is + when "100" => + ALU_Op <= "0100"; + when others => + if MCycle = "000" then + ALU_Op(3) <= '0'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + else + ALU_Op(3) <= '1'; + ALU_Op(2 downto 0) <= IR(7 downto 5); + end if; + end case; + --}}} + end case; + end process; + +end; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_Pack.vhd b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_Pack.vhd new file mode 100644 index 00000000..e025e1bf --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/t65/T65_Pack.vhd @@ -0,0 +1,117 @@ +-- **** +-- T65(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 Bugfixes by ehenciak added +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 65xx compatible microprocessor core +-- +-- Version : 0246 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t65/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T65_Pack is + + constant Flag_C : integer := 0; + constant Flag_Z : integer := 1; + constant Flag_I : integer := 2; + constant Flag_D : integer := 3; + constant Flag_B : integer := 4; + constant Flag_1 : integer := 5; + constant Flag_V : integer := 6; + constant Flag_N : integer := 7; + + component T65_MCode + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816 + IR : in std_logic_vector(7 downto 0); + MCycle : in std_logic_vector(2 downto 0); + P : in std_logic_vector(7 downto 0); + LCycle : out std_logic_vector(2 downto 0); + ALU_Op : out std_logic_vector(3 downto 0); + Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P + Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA + Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH + Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel + BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj + BreakAtNA : out std_logic; + ADAdd : out std_logic; + AddY : out std_logic; + PCAdd : out std_logic; + Inc_S : out std_logic; + Dec_S : out std_logic; + LDA : out std_logic; + LDP : out std_logic; + LDX : out std_logic; + LDY : out std_logic; + LDS : out std_logic; + LDDI : out std_logic; + LDALU : out std_logic; + LDAD : out std_logic; + LDBAL : out std_logic; + LDBAH : out std_logic; + SaveP : out std_logic; + Write : out std_logic + ); + end component; + + component T65_ALU + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Op : in std_logic_vector(3 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + P_In : in std_logic_vector(7 downto 0); + P_Out : out std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/video_mixer.sv b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Data East Cassette/Burnin Rubber_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.qpf b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.qpf new file mode 100644 index 00000000..43a9e280 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "Azurian" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.qsf b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.qsf new file mode 100644 index 00000000..77a1506b --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaxian_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Azurian +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Azurian.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.srf b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.srf new file mode 100644 index 00000000..14cddd5e --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Azurian.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/README.txt b/Arcade/Galaxian Hardware/AzurianAttack_MiST/README.txt new file mode 100644 index 00000000..6609ce77 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Azurian Attack port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/Release/Azurian.rbf b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Release/Azurian.rbf new file mode 100644 index 00000000..67d2cd86 Binary files /dev/null and b/Arcade/Galaxian Hardware/AzurianAttack_MiST/Release/Azurian.rbf differ diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/clean.bat b/Arcade/Galaxian Hardware/AzurianAttack_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/Azurian.sv b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/Azurian.sv new file mode 100644 index 00000000..78042604 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/Azurian.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Azurian +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Azurian +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Azurian Att.;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5) +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian azurian +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..6f39d31b --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,280 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"08",x"58",x"F0",x"F0", -- 0x0058 + x"00",x"00",x"00",x"02",x"07",x"07",x"06",x"00", -- 0x0060 + x"06",x"1E",x"3E",x"1A",x"19",x"3F",x"3F",x"7D", -- 0x0068 + x"37",x"36",x"32",x"76",x"74",x"1E",x"06",x"00", -- 0x0070 + x"00",x"07",x"02",x"3E",x"3E",x"02",x"07",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"02",x"02",x"07",x"02",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0170 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"0F",x"0F",x"0F",x"07",x"07",x"07",x"03",x"01", -- 0x0180 + x"30",x"20",x"00",x"00",x"00",x"00",x"00",x"1C", -- 0x0188 + x"70",x"78",x"7C",x"7E",x"7F",x"7E",x"7E",x"3C", -- 0x0190 + x"00",x"00",x"00",x"00",x"00",x"40",x"40",x"20", -- 0x0198 + x"03",x"03",x"01",x"01",x"01",x"01",x"01",x"00", -- 0x01A0 + x"03",x"03",x"03",x"07",x"07",x"03",x"03",x"03", -- 0x01A8 + x"02",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 + x"F8",x"FE",x"7F",x"7C",x"3C",x"1C",x"0E",x"06", -- 0x01B8 + x"00",x"80",x"C0",x"E0",x"E0",x"E0",x"F0",x"F0", -- 0x01C0 + x"FF",x"7F",x"1F",x"0F",x"93",x"F8",x"F0",x"58", -- 0x01C8 + x"00",x"01",x"01",x"03",x"03",x"03",x"00",x"00", -- 0x01D0 + x"FC",x"F0",x"F8",x"F8",x"F8",x"FC",x"7D",x"1C", -- 0x01D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FB",x"F1",x"F8", -- 0x01E0 + x"FF",x"FF",x"FE",x"FC",x"FE",x"FE",x"FF",x"FF", -- 0x01E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"0F", -- 0x01F0 + x"00",x"00",x"00",x"00",x"08",x"3C",x"7E",x"FF", -- 0x01F8 + x"00",x"00",x"00",x"02",x"06",x"0F",x"10",x"0F", -- 0x0200 + x"06",x"0E",x"1E",x"38",x"78",x"88",x"08",x"88", -- 0x0208 + x"06",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"78",x"38",x"1E",x"0E",x"06",x"00",x"00",x"00", -- 0x0218 + x"01",x"02",x"06",x"0E",x"02",x"02",x"02",x"02", -- 0x0220 + x"00",x"80",x"C0",x"E0",x"80",x"80",x"80",x"80", -- 0x0228 + x"06",x"04",x"0C",x"0C",x"1C",x"3F",x"38",x"38", -- 0x0230 + x"C0",x"40",x"60",x"60",x"70",x"F8",x"38",x"38", -- 0x0238 + x"F8",x"B0",x"90",x"D0",x"E8",x"E4",x"97",x"10", -- 0x0240 + x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"E0", -- 0x0248 + x"09",x"08",x"0A",x"0C",x"0C",x"0E",x"0C",x"08", -- 0x0250 + x"40",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"01",x"03",x"66",x"9C",x"9C",x"66",x"03",x"01", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"3F",x"83",x"86",x"BC",x"BC",x"86",x"83",x"3F", -- 0x0298 + x"01",x"02",x"05",x"0B",x"17",x"2C",x"5C",x"9F", -- 0x02A0 + x"80",x"40",x"A0",x"D0",x"E8",x"34",x"3A",x"F9", -- 0x02A8 + x"9F",x"5C",x"2C",x"17",x"0B",x"05",x"02",x"01", -- 0x02B0 + x"F9",x"3A",x"34",x"E8",x"D0",x"A0",x"40",x"80", -- 0x02B8 + x"01",x"21",x"70",x"20",x"03",x"03",x"0F",x"CF", -- 0x02C0 + x"80",x"84",x"0E",x"04",x"C0",x"C0",x"F0",x"F3", -- 0x02C8 + x"CF",x"0F",x"03",x"03",x"20",x"70",x"21",x"01", -- 0x02D0 + x"F3",x"F0",x"C0",x"C0",x"04",x"0E",x"84",x"80", -- 0x02D8 + x"00",x"3E",x"7E",x"7F",x"7E",x"7E",x"7E",x"7E", -- 0x02E0 + x"00",x"80",x"C0",x"E0",x"70",x"B8",x"DC",x"EE", -- 0x02E8 + x"7E",x"7C",x"7C",x"0C",x"3C",x"7C",x"7F",x"7F", -- 0x02F0 + x"F6",x"FF",x"FE",x"EF",x"D6",x"EE",x"DE",x"DE", -- 0x02F8 + x"00",x"00",x"00",x"C0",x"F0",x"F8",x"7E",x"1F", -- 0x0300 + x"00",x"00",x"00",x"03",x"0F",x"1F",x"7E",x"F8", -- 0x0308 + x"1F",x"7E",x"F8",x"F0",x"C0",x"00",x"00",x"00", -- 0x0310 + x"F8",x"7E",x"1F",x"0F",x"03",x"00",x"00",x"00", -- 0x0318 + x"07",x"03",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0320 + x"00",x"00",x"00",x"00",x"01",x"03",x"03",x"07", -- 0x0328 + x"00",x"3F",x"3F",x"1D",x"1D",x"0D",x"0F",x"07", -- 0x0330 + x"07",x"0F",x"0D",x"1D",x"1D",x"3F",x"3F",x"00", -- 0x0338 + x"E0",x"FC",x"FF",x"3F",x"07",x"00",x"00",x"00", -- 0x0340 + x"00",x"00",x"00",x"07",x"3F",x"FF",x"FC",x"E0", -- 0x0348 + x"03",x"1F",x"FF",x"FE",x"F0",x"E0",x"E0",x"E0", -- 0x0350 + x"E0",x"E0",x"E0",x"F0",x"FE",x"FF",x"1F",x"03", -- 0x0358 + x"E3",x"E1",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0360 + x"E0",x"F0",x"F8",x"FC",x"FE",x"FF",x"EF",x"E7", -- 0x0368 + x"07",x"07",x"07",x"07",x"07",x"07",x"87",x"C7", -- 0x0370 + x"E7",x"F7",x"FF",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0378 + x"00",x"00",x"00",x"02",x"05",x"00",x"03",x"0C", -- 0x0380 + x"00",x"00",x"00",x"10",x"50",x"68",x"88",x"C8", -- 0x0388 + x"03",x"0A",x"03",x"01",x"04",x"03",x"00",x"00", -- 0x0390 + x"F4",x"A0",x"C0",x"70",x"40",x"20",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"02",x"0A",x"04",x"00", -- 0x03A0 + x"00",x"00",x"00",x"00",x"50",x"A0",x"00",x"20", -- 0x03A8 + x"00",x"09",x"01",x"02",x"00",x"00",x"00",x"00", -- 0x03B0 + x"38",x"10",x"00",x"40",x"20",x"00",x"00",x"00", -- 0x03B8 + x"00",x"02",x"01",x"01",x"01",x"40",x"13",x"01", -- 0x03C0 + x"00",x"00",x"00",x"04",x"0C",x"18",x"80",x"90", -- 0x03C8 + x"00",x"08",x"00",x"00",x"02",x"04",x"00",x"00", -- 0x03D0 + x"82",x"CC",x"00",x"10",x"98",x"84",x"00",x"00", -- 0x03D8 + x"08",x"04",x"00",x"02",x"8C",x"0E",x"07",x"0F", -- 0x03E0 + x"01",x"12",x"00",x"04",x"00",x"C0",x"C8",x"E0", -- 0x03E8 + x"07",x"03",x"21",x"00",x"80",x"21",x"48",x"81", -- 0x03F0 + x"C2",x"80",x"01",x"00",x"22",x"00",x"02",x"01", -- 0x03F8 + x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"3F",x"1E", -- 0x0400 + x"8F",x"CF",x"9F",x"BF",x"3F",x"FF",x"FF",x"FF", -- 0x0408 + x"E0",x"F8",x"FE",x"FF",x"FF",x"FF",x"FE",x"E0", -- 0x0410 + x"E0",x"E0",x"C0",x"C0",x"80",x"80",x"00",x"00", -- 0x0418 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FC",x"F0", -- 0x0420 + x"00",x"80",x"F8",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0428 + x"00",x"00",x"00",x"00",x"E0",x"80",x"00",x"00", -- 0x0430 + x"FC",x"F8",x"F8",x"F0",x"E0",x"00",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"80",x"E0",x"F0",x"F8",x"FC", -- 0x0440 + x"0F",x"1F",x"3F",x"3F",x"7F",x"7F",x"FF",x"FF", -- 0x0448 + x"00",x"00",x"00",x"00",x"01",x"01",x"04",x"0E", -- 0x0450 + x"3F",x"9F",x"9F",x"CF",x"CF",x"CF",x"E7",x"E7", -- 0x0458 + x"00",x"03",x"1F",x"7F",x"FF",x"FF",x"FF",x"7F", -- 0x0460 + x"FC",x"FC",x"FE",x"FE",x"FE",x"FF",x"FF",x"FF", -- 0x0468 + x"00",x"38",x"AF",x"CB",x"E5",x"F2",x"F9",x"F9", -- 0x0470 + x"BE",x"BF",x"5F",x"5F",x"5F",x"2F",x"2F",x"2F", -- 0x0478 + x"00",x"00",x"00",x"C0",x"F0",x"F8",x"7C",x"7E", -- 0x0480 + x"00",x"00",x"80",x"80",x"C0",x"C0",x"C0",x"00", -- 0x0488 + x"01",x"01",x"01",x"03",x"03",x"03",x"07",x"07", -- 0x0490 + x"07",x"0F",x"0F",x"0F",x"1F",x"1F",x"1F",x"1F", -- 0x0498 + x"1F",x"3F",x"3F",x"7F",x"7F",x"7F",x"FF",x"FF", -- 0x04A0 + x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x04A8 + x"0F",x"0F",x"0F",x"1F",x"1F",x"3F",x"3F",x"7F", -- 0x04B0 + x"7F",x"7E",x"FE",x"FE",x"FE",x"FC",x"FC",x"FC", -- 0x04B8 + x"00",x"00",x"00",x"00",x"01",x"01",x"03",x"03", -- 0x04C0 + x"07",x"07",x"0F",x"0F",x"1F",x"1F",x"3F",x"3F", -- 0x04C8 + x"07",x"07",x"0F",x"0F",x"1F",x"3F",x"3F",x"7F", -- 0x04D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FE",x"FE", -- 0x04D8 + x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x04E0 + x"FC",x"FC",x"3C",x"18",x"08",x"00",x"00",x"00", -- 0x04E8 + x"E0",x"C0",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x04F0 + x"FE",x"FE",x"FC",x"FC",x"F0",x"F0",x"F0",x"F0", -- 0x04F8 + x"7F",x"7F",x"FF",x"FF",x"FF",x"FF",x"FE",x"FE", -- 0x0500 + x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FE",x"FE", -- 0x0508 + x"FF",x"FF",x"FF",x"FF",x"C3",x"01",x"01",x"00", -- 0x0510 + x"33",x"3F",x"1F",x"00",x"00",x"00",x"00",x"00", -- 0x0518 + x"C0",x"80",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"C0",x"40",x"40",x"40",x"60",x"60",x"40",x"C0", -- 0x0528 + x"00",x"00",x"80",x"80",x"80",x"C0",x"C0",x"C0", -- 0x0530 + x"F8",x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"80", -- 0x0538 + x"FF",x"F8",x"E0",x"C0",x"80",x"00",x"00",x"00", -- 0x0540 + x"E0",x"E0",x"E0",x"E0",x"F0",x"F0",x"FE",x"FF", -- 0x0548 + x"F8",x"F8",x"F8",x"F0",x"F0",x"F0",x"F0",x"E0", -- 0x0550 + x"E0",x"E0",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0560 + x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0568 + x"F0",x"F8",x"FC",x"FE",x"1F",x"0F",x"07",x"07", -- 0x0570 + x"07",x"07",x"0F",x"1F",x"FE",x"FC",x"F8",x"F0", -- 0x0578 + x"E1",x"E1",x"E1",x"E1",x"FF",x"FF",x"FF",x"FF", -- 0x0580 + x"1E",x"3F",x"7F",x"FF",x"F3",x"E1",x"E1",x"E1", -- 0x0588 + x"07",x"0F",x"9F",x"FF",x"FC",x"F8",x"F0",x"E0", -- 0x0590 + x"C0",x"C0",x"C0",x"C0",x"FF",x"FF",x"FF",x"FF", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x05A0 + x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 + x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"01",x"07", -- 0x05B0 + x"1F",x"7F",x"FE",x"F8",x"FF",x"FF",x"FF",x"FF", -- 0x05B8 + x"FF",x"FF",x"FF",x"FF",x"1F",x"7F",x"FE",x"F8", -- 0x05C0 + x"E0",x"80",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x05C8 + x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"FF",x"FF", -- 0x05D0 + x"FF",x"FF",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x05D8 + x"38",x"78",x"F8",x"F8",x"F0",x"E0",x"E0",x"E0", -- 0x05E0 + x"E0",x"E0",x"E0",x"F0",x"FF",x"FF",x"7F",x"3F", -- 0x05E8 + x"1C",x"1E",x"1F",x"1F",x"0F",x"07",x"07",x"07", -- 0x05F0 + x"07",x"07",x"07",x"0F",x"FF",x"FF",x"FE",x"FC", -- 0x05F8 + x"80",x"C0",x"E0",x"F0",x"F8",x"7C",x"3E",x"1F", -- 0x0600 + x"0F",x"07",x"03",x"03",x"FF",x"FF",x"FF",x"FF", -- 0x0608 + x"01",x"03",x"07",x"0F",x"1F",x"3E",x"7C",x"F8", -- 0x0610 + x"F0",x"E0",x"C0",x"C0",x"FF",x"FF",x"FF",x"FF", -- 0x0618 + x"00",x"00",x"00",x"00",x"81",x"87",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"00", -- 0x0628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 + x"10",x"10",x"30",x"30",x"30",x"60",x"40",x"C0", -- 0x0638 + x"03",x"0F",x"1F",x"1B",x"39",x"70",x"73",x"37", -- 0x0640 + x"C0",x"C0",x"E8",x"FC",x"FC",x"9C",x"9C",x"EE", -- 0x0648 + x"3F",x"1F",x"07",x"1F",x"1E",x"0F",x"0F",x"01", -- 0x0650 + x"DE",x"DF",x"9F",x"A7",x"47",x"AF",x"FC",x"E0", -- 0x0658 + x"7F",x"7E",x"7E",x"7F",x"7F",x"7F",x"7E",x"78", -- 0x0660 + x"FE",x"EE",x"EE",x"F8",x"E0",x"80",x"00",x"00", -- 0x0668 + x"62",x"0E",x"3E",x"7E",x"7A",x"73",x"6B",x"59", -- 0x0670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 + x"00",x"80",x"40",x"20",x"10",x"08",x"04",x"02", -- 0x0680 + x"00",x"10",x"08",x"08",x"1C",x"0C",x"00",x"00", -- 0x0688 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 + x"E0",x"E0",x"70",x"06",x"02",x"00",x"60",x"20", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"02", -- 0x06A0 + x"00",x"04",x"08",x"18",x"30",x"20",x"E0",x"40", -- 0x06A8 + x"00",x"00",x"71",x"12",x"11",x"16",x"04",x"04", -- 0x06B0 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"70", -- 0x06B8 + x"31",x"08",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x06C0 + x"C0",x"00",x"00",x"00",x"40",x"C0",x"78",x"00", -- 0x06C8 + x"01",x"06",x"0C",x"08",x"08",x"10",x"20",x"00", -- 0x06D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"00",x"00",x"00",x"00",x"00",x"0A",x"0F",x"03", -- 0x06E0 + x"38",x"1E",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x06E8 + x"03",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"B0",x"30",x"30",x"1C",x"0C",x"04",x"02",x"00", -- 0x06F8 + x"00",x"80",x"40",x"30",x"08",x"05",x"07",x"03", -- 0x0700 + x"80",x"40",x"20",x"10",x"6C",x"90",x"0E",x"21", -- 0x0708 + x"01",x"01",x"03",x"06",x"04",x"04",x"1B",x"3A", -- 0x0710 + x"48",x"38",x"0E",x"1F",x"0F",x"07",x"01",x"D9", -- 0x0718 + x"00",x"00",x"00",x"00",x"00",x"06",x"04",x"09", -- 0x0720 + x"01",x"02",x"06",x"0C",x"38",x"70",x"58",x"AC", -- 0x0728 + x"D3",x"C6",x"87",x"6B",x"F4",x"A4",x"08",x"CC", -- 0x0730 + x"C8",x"D0",x"10",x"40",x"80",x"80",x"00",x"CF", -- 0x0738 + x"C5",x"02",x"00",x"06",x"02",x"01",x"00",x"02", -- 0x0740 + x"3F",x"8F",x"07",x"02",x"08",x"15",x"C7",x"F5", -- 0x0748 + x"02",x"06",x"0C",x"18",x"30",x"20",x"40",x"00", -- 0x0750 + x"74",x"22",x"01",x"00",x"02",x"04",x"08",x"10", -- 0x0758 + x"EF",x"EE",x"79",x"28",x"84",x"91",x"0B",x"15", -- 0x0760 + x"98",x"30",x"20",x"20",x"C0",x"00",x"40",x"F8", -- 0x0768 + x"94",x"C4",x"28",x"D0",x"30",x"00",x"00",x"00", -- 0x0770 + x"70",x"08",x"04",x"02",x"01",x"00",x"00",x"00", -- 0x0778 + x"00",x"80",x"60",x"10",x"0C",x"07",x"03",x"01", -- 0x0780 + x"20",x"20",x"10",x"10",x"08",x"9C",x"FF",x"FF", -- 0x0788 + x"10",x"0D",x"03",x"01",x"00",x"03",x"07",x"FF", -- 0x0790 + x"FF",x"FF",x"FB",x"FB",x"F7",x"E1",x"F0",x"E0", -- 0x0798 + x"00",x"00",x"40",x"41",x"42",x"46",x"DC",x"FD", -- 0x07A0 + x"00",x"02",x"04",x"18",x"20",x"60",x"C0",x"80", -- 0x07A8 + x"FF",x"FF",x"FF",x"FF",x"C7",x"03",x"07",x"00", -- 0x07B0 + x"80",x"04",x"18",x"20",x"C0",x"80",x"E0",x"FF", -- 0x07B8 + x"01",x"00",x"00",x"01",x"03",x"0F",x"18",x"60", -- 0x07C0 + x"80",x"F0",x"F0",x"F8",x"FC",x"7D",x"7F",x"FF", -- 0x07C8 + x"01",x"03",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x07D0 + x"E7",x"83",x"01",x"01",x"00",x"00",x"00",x"00", -- 0x07D8 + x"0F",x"00",x"00",x"0B",x"0E",x"07",x"FF",x"FB", -- 0x07E0 + x"C0",x"00",x"40",x"C0",x"38",x"0C",x"80",x"80", -- 0x07E8 + x"F8",x"F8",x"DC",x"8C",x"86",x"82",x"82",x"80", -- 0x07F0 + x"C0",x"60",x"20",x"10",x"08",x"04",x"00",x"00" -- 0x07F8 + ); + +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..942316be --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,280 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1K is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"08",x"FE",x"F0",x"F0", -- 0x0058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0060 + x"00",x"00",x"00",x"04",x"06",x"00",x"00",x"02", -- 0x0068 + x"08",x"08",x"0C",x"08",x"08",x"00",x"00",x"00", -- 0x0070 + x"00",x"27",x"62",x"C0",x"90",x"62",x"27",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"02",x"07",x"02",x"00",x"00",x"00",x"00", -- 0x0160 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0180 + x"0F",x"1F",x"3F",x"3F",x"1F",x"1F",x"1F",x"03", -- 0x0188 + x"0F",x"07",x"03",x"01",x"00",x"01",x"01",x"03", -- 0x0190 + x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"3F",x"1F", -- 0x0198 + x"1C",x"1C",x"3E",x"3E",x"3E",x"3E",x"7E",x"7F", -- 0x01A0 + x"00",x"00",x"00",x"00",x"00",x"0C",x"0C",x"1C", -- 0x01A8 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 + x"07",x"01",x"00",x"03",x"03",x"03",x"01",x"01", -- 0x01B8 + x"FF",x"7F",x"3F",x"1F",x"1F",x"1F",x"0F",x"0F", -- 0x01C0 + x"00",x"80",x"E0",x"F0",x"6C",x"07",x"0F",x"A7", -- 0x01C8 + x"FF",x"FE",x"FE",x"3C",x"0C",x"00",x"00",x"00", -- 0x01D0 + x"03",x"0F",x"07",x"07",x"07",x"03",x"82",x"E3", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"04",x"0E",x"07", -- 0x01E0 + x"00",x"00",x"01",x"03",x"01",x"01",x"00",x"00", -- 0x01E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"FF",x"FF",x"FF",x"FF",x"F7",x"C3",x"81",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"03",x"0F",x"03", -- 0x0200 + x"3C",x"18",x"18",x"38",x"78",x"F8",x"F8",x"F8", -- 0x0208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"78",x"38",x"18",x"18",x"3C",x"00",x"00",x"00", -- 0x0218 + x"00",x"01",x"01",x"03",x"03",x"03",x"03",x"03", -- 0x0220 + x"00",x"00",x"00",x"80",x"80",x"80",x"80",x"80", -- 0x0228 + x"07",x"07",x"2F",x"3F",x"3F",x"3F",x"20",x"00", -- 0x0230 + x"C0",x"C0",x"E8",x"F8",x"F8",x"F8",x"08",x"00", -- 0x0238 + x"00",x"40",x"70",x"30",x"38",x"3C",x"1F",x"1F", -- 0x0240 + x"00",x"00",x"00",x"40",x"60",x"70",x"C0",x"80", -- 0x0248 + x"0F",x"0E",x"0E",x"0C",x"38",x"30",x"10",x"00", -- 0x0250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"18",x"18",x"78",x"9C",x"9C",x"78",x"18",x"18", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"3F",x"0F",x"1E",x"44",x"44",x"1E",x"0F",x"3F", -- 0x0298 + x"01",x"02",x"04",x"09",x"11",x"23",x"47",x"8E", -- 0x02A0 + x"80",x"40",x"20",x"90",x"88",x"C4",x"E2",x"71", -- 0x02A8 + x"8E",x"47",x"23",x"11",x"09",x"04",x"02",x"01", -- 0x02B0 + x"71",x"E2",x"C4",x"88",x"90",x"20",x"40",x"80", -- 0x02B8 + x"00",x"00",x"07",x"1C",x"1B",x"32",x"2E",x"2C", -- 0x02C0 + x"00",x"00",x"E0",x"38",x"D8",x"4C",x"34",x"34", -- 0x02C8 + x"2C",x"2E",x"32",x"1B",x"1C",x"07",x"00",x"00", -- 0x02D0 + x"34",x"34",x"4C",x"D8",x"38",x"E0",x"00",x"00", -- 0x02D8 + x"FF",x"FF",x"FF",x"80",x"AF",x"A5",x"DB",x"81", -- 0x02E0 + x"80",x"60",x"B0",x"58",x"EC",x"76",x"3B",x"5D", -- 0x02E8 + x"9D",x"87",x"FF",x"FB",x"DB",x"C3",x"DE",x"F6", -- 0x02F0 + x"69",x"76",x"47",x"D6",x"A9",x"9F",x"B7",x"F7", -- 0x02F8 + x"03",x"06",x"0C",x"FC",x"CE",x"E7",x"71",x"3C", -- 0x0300 + x"C0",x"60",x"30",x"3F",x"73",x"E7",x"8E",x"3C", -- 0x0308 + x"3C",x"71",x"E7",x"CE",x"FC",x"0C",x"06",x"03", -- 0x0310 + x"3C",x"8E",x"E7",x"73",x"3E",x"30",x"60",x"C0", -- 0x0318 + x"0E",x"0E",x"07",x"07",x"03",x"03",x"07",x"01", -- 0x0320 + x"01",x"01",x"03",x"03",x"07",x"07",x"0E",x"0E", -- 0x0328 + x"FF",x"FF",x"70",x"7E",x"3A",x"3E",x"1C",x"1C", -- 0x0330 + x"1C",x"1C",x"3E",x"3A",x"7E",x"70",x"FF",x"FF", -- 0x0338 + x"E0",x"FC",x"FF",x"3F",x"07",x"00",x"00",x"00", -- 0x0340 + x"00",x"00",x"00",x"07",x"3F",x"FF",x"FC",x"E0", -- 0x0348 + x"03",x"1F",x"FF",x"FE",x"F0",x"E0",x"E0",x"E0", -- 0x0350 + x"E0",x"E0",x"E0",x"F0",x"FE",x"FF",x"1F",x"03", -- 0x0358 + x"E3",x"E1",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0360 + x"E0",x"F0",x"F8",x"FC",x"FE",x"FF",x"EF",x"E7", -- 0x0368 + x"07",x"07",x"07",x"07",x"07",x"07",x"87",x"C7", -- 0x0370 + x"E7",x"F7",x"FF",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0378 + x"00",x"01",x"03",x"07",x"03",x"07",x"0F",x"3F", -- 0x0380 + x"80",x"80",x"D8",x"F8",x"F8",x"F0",x"F0",x"F0", -- 0x0388 + x"1F",x"1F",x"1F",x"0F",x"03",x"07",x"07",x"01", -- 0x0390 + x"F8",x"F8",x"F0",x"E0",x"F8",x"FC",x"78",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"04",x"01",x"03", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"90", -- 0x03A8 + x"07",x"02",x"02",x"08",x"00",x"00",x"00",x"00", -- 0x03B0 + x"C0",x"80",x"A0",x"10",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"04",x"24",x"04",x"4E",x"27", -- 0x03C0 + x"00",x"00",x"20",x"40",x"11",x"80",x"A4",x"C8", -- 0x03C8 + x"07",x"03",x"25",x"00",x"08",x"00",x"00",x"00", -- 0x03D0 + x"C0",x"20",x"90",x"A0",x"20",x"50",x"00",x"00", -- 0x03D8 + x"00",x"00",x"42",x"20",x"04",x"0F",x"E7",x"3F", -- 0x03E0 + x"00",x"20",x"44",x"C8",x"80",x"80",x"D0",x"EC", -- 0x03E8 + x"07",x"07",x"0D",x"1D",x"29",x"42",x"01",x"00", -- 0x03F0 + x"C0",x"A0",x"B0",x"88",x"44",x"20",x"10",x"08", -- 0x03F8 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"E1", -- 0x0400 + x"70",x"30",x"60",x"40",x"C0",x"00",x"00",x"00", -- 0x0408 + x"1F",x"07",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x0410 + x"1F",x"1F",x"3F",x"3F",x"7F",x"7F",x"FF",x"FF", -- 0x0418 + x"00",x"00",x"00",x"00",x"00",x"00",x"03",x"0F", -- 0x0420 + x"FF",x"7F",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0428 + x"FF",x"FF",x"FF",x"F8",x"00",x"00",x"00",x"00", -- 0x0430 + x"03",x"07",x"07",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0438 + x"FF",x"FF",x"FF",x"7F",x"1F",x"0F",x"07",x"03", -- 0x0440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 + x"00",x"00",x"00",x"00",x"00",x"02",x"03",x"01", -- 0x0450 + x"C0",x"60",x"60",x"30",x"30",x"30",x"18",x"18", -- 0x0458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0460 + x"03",x"03",x"01",x"01",x"01",x"00",x"00",x"00", -- 0x0468 + x"00",x"C0",x"50",x"34",x"1A",x"0D",x"06",x"06", -- 0x0470 + x"40",x"40",x"A0",x"A0",x"A0",x"D0",x"D0",x"D0", -- 0x0478 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0490 + x"FF",x"FF",x"FE",x"FE",x"FE",x"FC",x"FC",x"FC", -- 0x0498 + x"F8",x"F8",x"F8",x"F8",x"F0",x"F0",x"F0",x"F0", -- 0x04A0 + x"E0",x"E0",x"C0",x"C0",x"C0",x"80",x"80",x"80", -- 0x04A8 + x"FF",x"FF",x"FF",x"FE",x"FE",x"FC",x"FC",x"F8", -- 0x04B0 + x"F8",x"F8",x"F0",x"F0",x"E0",x"E0",x"C0",x"C0", -- 0x04B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x04C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FE",x"FE",x"FC", -- 0x04C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FE",x"FE",x"FC", -- 0x04D0 + x"FC",x"F8",x"F8",x"F0",x"E0",x"C0",x"C0",x"80", -- 0x04D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 + x"C0",x"80",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"FC",x"F8",x"F8",x"F0",x"F0",x"E0",x"E0",x"E0", -- 0x0500 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"01",x"01",x"00", -- 0x0510 + x"33",x"3F",x"1F",x"00",x"00",x"00",x"00",x"00", -- 0x0518 + x"C0",x"80",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"C0",x"40",x"40",x"40",x"60",x"60",x"40",x"C0", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"C0", -- 0x0530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"0F",x"38",x"E0",x"C0",x"80",x"00",x"00",x"00", -- 0x0540 + x"00",x"00",x"00",x"00",x"00",x"00",x"06",x"07", -- 0x0548 + x"C0",x"C0",x"C0",x"C0",x"C0",x"80",x"80",x"00", -- 0x0550 + x"E0",x"E0",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0560 + x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0568 + x"F0",x"F8",x"FC",x"FE",x"1F",x"0F",x"07",x"07", -- 0x0570 + x"07",x"07",x"0F",x"1F",x"FE",x"FC",x"F8",x"F0", -- 0x0578 + x"E1",x"E1",x"E1",x"E1",x"FF",x"FF",x"FF",x"FF", -- 0x0580 + x"1E",x"3F",x"7F",x"FF",x"F3",x"E1",x"E1",x"E1", -- 0x0588 + x"07",x"0F",x"9F",x"FF",x"FC",x"F8",x"F0",x"E0", -- 0x0590 + x"C0",x"C0",x"C0",x"C0",x"FF",x"FF",x"FF",x"FF", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x05A0 + x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 + x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"01",x"07", -- 0x05B0 + x"1F",x"7F",x"FE",x"F8",x"FF",x"FF",x"FF",x"FF", -- 0x05B8 + x"FF",x"FF",x"FF",x"FF",x"1F",x"7F",x"FE",x"F8", -- 0x05C0 + x"E0",x"80",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x05C8 + x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"FF",x"FF", -- 0x05D0 + x"FF",x"FF",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x05D8 + x"38",x"78",x"F8",x"F8",x"F0",x"E0",x"E0",x"E0", -- 0x05E0 + x"E0",x"E0",x"E0",x"F0",x"FF",x"FF",x"7F",x"3F", -- 0x05E8 + x"1C",x"1E",x"1F",x"1F",x"0F",x"07",x"07",x"07", -- 0x05F0 + x"07",x"07",x"07",x"0F",x"FF",x"FF",x"FE",x"FC", -- 0x05F8 + x"80",x"C0",x"E0",x"F0",x"F8",x"7C",x"3E",x"1F", -- 0x0600 + x"0F",x"07",x"03",x"03",x"FF",x"FF",x"FF",x"FF", -- 0x0608 + x"01",x"03",x"07",x"0F",x"1F",x"3E",x"7C",x"F8", -- 0x0610 + x"F0",x"E0",x"C0",x"C0",x"FF",x"FF",x"FF",x"FF", -- 0x0618 + x"00",x"00",x"C3",x"2C",x"10",x"11",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"80",x"40",x"20",x"10",x"10", -- 0x0628 + x"00",x"FE",x"FF",x"FE",x"70",x"E0",x"FC",x"F0", -- 0x0630 + x"08",x"08",x"14",x"14",x"28",x"48",x"10",x"20", -- 0x0638 + x"00",x"00",x"00",x"04",x"06",x"0F",x"0C",x"08", -- 0x0640 + x"00",x"00",x"00",x"00",x"67",x"06",x"06",x"01", -- 0x0648 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"00", -- 0x0650 + x"20",x"20",x"60",x"58",x"B8",x"50",x"00",x"00", -- 0x0658 + x"F0",x"E7",x"FF",x"DE",x"D0",x"C6",x"FD",x"F7", -- 0x0660 + x"C7",x"D7",x"7F",x"00",x"DC",x"70",x"C0",x"00", -- 0x0668 + x"DF",x"FF",x"FD",x"F9",x"F5",x"ED",x"C7",x"A7", -- 0x0670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 + x"00",x"00",x"00",x"00",x"18",x"0D",x"02",x"04", -- 0x0688 + x"00",x"00",x"00",x"00",x"00",x"01",x"01",x"02", -- 0x0690 + x"62",x"27",x"10",x"E6",x"92",x"0C",x"68",x"20", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"C0",x"61",x"13", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 + x"12",x"04",x"F1",x"52",x"31",x"36",x"05",x"04", -- 0x06B0 + x"C0",x"20",x"A0",x"20",x"20",x"40",x"40",x"80", -- 0x06B8 + x"05",x"04",x"02",x"01",x"00",x"01",x"01",x"01", -- 0x06C0 + x"C0",x"40",x"40",x"40",x"C0",x"C0",x"FC",x"8A", -- 0x06C8 + x"01",x"06",x"08",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 + x"72",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"00",x"00",x"00",x"00",x"00",x"08",x"0C",x"02", -- 0x06E0 + x"00",x"78",x"20",x"20",x"10",x"10",x"20",x"20", -- 0x06E8 + x"13",x"0F",x"E3",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"70",x"D0",x"10",x"0C",x"04",x"00",x"00",x"00", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"01",x"01",x"03", -- 0x0700 + x"00",x"00",x"00",x"10",x"7C",x"FF",x"FF",x"DF", -- 0x0708 + x"03",x"07",x"07",x"09",x"0F",x"0F",x"05",x"0D", -- 0x0710 + x"37",x"8F",x"C7",x"82",x"01",x"87",x"E1",x"F9", -- 0x0718 + x"00",x"00",x"00",x"00",x"00",x"0F",x"9F",x"FF", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"40",x"B8",x"78", -- 0x0728 + x"9C",x"2F",x"74",x"F8",x"F1",x"A7",x"0F",x"CF", -- 0x0730 + x"70",x"60",x"F0",x"E0",x"E0",x"C0",x"C0",x"E0", -- 0x0738 + x"0E",x"07",x"07",x"0B",x"07",x"03",x"01",x"01", -- 0x0740 + x"FF",x"7F",x"EF",x"F6",x"74",x"8F",x"8B",x"8E", -- 0x0748 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"DF",x"77",x"23",x"03",x"03",x"03",x"00",x"00", -- 0x0758 + x"EF",x"EF",x"7F",x"2F",x"8F",x"9F",x"3F",x"7E", -- 0x0760 + x"E0",x"D0",x"F0",x"F0",x"E0",x"E0",x"80",x"10", -- 0x0768 + x"6E",x"3E",x"DC",x"F8",x"F8",x"30",x"00",x"00", -- 0x0770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"00",x"00",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0780 + x"00",x"00",x"00",x"00",x"00",x"94",x"F7",x"33", -- 0x0788 + x"00",x"01",x"00",x"00",x"00",x"03",x"02",x"00", -- 0x0790 + x"1A",x"8E",x"C8",x"FA",x"D6",x"33",x"7D",x"FF", -- 0x0798 + x"00",x"00",x"00",x"00",x"00",x"02",x"14",x"35", -- 0x07A0 + x"00",x"00",x"00",x"00",x"00",x"40",x"80",x"00", -- 0x07A8 + x"24",x"28",x"49",x"DF",x"D7",x"77",x"CE",x"F8", -- 0x07B0 + x"00",x"00",x"00",x"00",x"80",x"80",x"20",x"00", -- 0x07B8 + x"01",x"00",x"00",x"01",x"00",x"01",x"00",x"00", -- 0x07C0 + x"87",x"FB",x"8E",x"19",x"F7",x"63",x"42",x"9C", -- 0x07C8 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 + x"66",x"82",x"01",x"01",x"00",x"00",x"00",x"00", -- 0x07D8 + x"FF",x"FF",x"F8",x"EA",x"AE",x"79",x"DC",x"4A", -- 0x07E0 + x"C0",x"80",x"40",x"00",x"00",x"00",x"80",x"00", -- 0x07E8 + x"40",x"70",x"58",x"08",x"00",x"00",x"00",x"00", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x07F8 + ); + +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..69425a6e --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + x"00",x"7A",x"36",x"07",x"00",x"F0",x"38",x"1F", -- 0x0000 + x"00",x"C7",x"F0",x"3F",x"00",x"DB",x"C6",x"38", -- 0x0008 + x"00",x"36",x"07",x"F0",x"00",x"33",x"3F",x"DB", -- 0x0010 + x"00",x"3F",x"57",x"C6",x"00",x"C6",x"3F",x"FF" -- 0x0018 + ); + +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", + X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", + X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", + X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", + X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", + X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", + X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", + X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", + X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", + X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", + X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", + X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", + 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out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", + X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", + X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", + X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", + X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70", + 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X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", + X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", + X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..5a0cf5cd --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1560 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 12287) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + x"00",x"AF",x"32",x"01",x"70",x"C3",x"C8",x"00", -- 0x0000 + x"41",x"5A",x"55",x"52",x"49",x"41",x"4E",x"20", -- 0x0008 + x"41",x"54",x"54",x"41",x"43",x"4B",x"20",x"43", -- 0x0010 + x"4F",x"50",x"59",x"52",x"49",x"47",x"48",x"54", -- 0x0018 + x"20",x"52",x"41",x"49",x"54",x"20",x"45",x"4C", -- 0x0020 + x"45",x"43",x"54",x"52",x"4F",x"4E",x"49",x"43", -- 0x0028 + x"53",x"20",x"4C",x"54",x"44",x"20",x"31",x"39", -- 0x0030 + x"38",x"32",x"20",x"41",x"4C",x"4C",x"20",x"52", -- 0x0038 + x"49",x"47",x"48",x"54",x"53",x"20",x"52",x"45", -- 0x0040 + x"53",x"45",x"52",x"56",x"45",x"44",x"00",x"00", -- 0x0048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0058 + x"00",x"00",x"00",x"00",x"00",x"00",x"F5",x"C5", -- 0x0060 + x"D5",x"E5",x"DD",x"E5",x"FD",x"E5",x"3A",x"00", -- 0x0068 + x"78",x"AF",x"32",x"01",x"70",x"21",x"B6",x"40", -- 0x0070 + x"35",x"21",x"C0",x"41",x"11",x"00",x"58",x"01", -- 0x0078 + x"80",x"00",x"ED",x"B0",x"3A",x"AF",x"40",x"CB", -- 0x0080 + x"67",x"28",x"14",x"11",x"04",x"00",x"06",x"04", -- 0x0088 + x"21",x"63",x"58",x"3E",x"F3",x"96",x"77",x"19", -- 0x0090 + x"3E",x"5E",x"96",x"77",x"19",x"10",x"F4",x"CD", -- 0x0098 + x"F4",x"0F",x"3A",x"BF",x"40",x"A7",x"C4",x"CD", -- 0x00A0 + x"04",x"DD",x"21",x"AF",x"40",x"DD",x"CB",x"00", -- 0x00A8 + x"4E",x"C2",x"C3",x"18",x"CD",x"66",x"22",x"3E", -- 0x00B0 + x"FF",x"32",x"01",x"70",x"FD",x"E1",x"DD",x"E1", -- 0x00B8 + x"E1",x"D1",x"C1",x"F1",x"ED",x"45",x"00",x"00", -- 0x00C0 + x"31",x"00",x"44",x"CD",x"F4",x"12",x"AF",x"21", -- 0x00C8 + x"00",x"60",x"06",x"04",x"77",x"23",x"10",x"FC", -- 0x00D0 + x"3C",x"06",x"04",x"77",x"23",x"10",x"FC",x"AF", -- 0x00D8 + x"06",x"08",x"21",x"00",x"68",x"77",x"23",x"10", -- 0x00E0 + x"FC",x"06",x"08",x"21",x"01",x"70",x"77",x"23", -- 0x00E8 + x"10",x"FC",x"3D",x"32",x"00",x"78",x"21",x"16", -- 0x00F0 + x"11",x"11",x"00",x"40",x"01",x"00",x"01",x"ED", -- 0x00F8 + x"B0",x"06",x"01",x"3A",x"00",x"70",x"CB",x"47", -- 0x0100 + x"28",x"01",x"04",x"78",x"32",x"B2",x"40",x"32", -- 0x0108 + x"B1",x"40",x"CD",x"42",x"13",x"C3",x"BE",x"01", -- 0x0110 + x"31",x"00",x"44",x"DD",x"CB",x"00",x"DE",x"DD", -- 0x0118 + x"CB",x"00",x"96",x"DD",x"CB",x"00",x"8E",x"AF", -- 0x0120 + x"32",x"BF",x"40",x"32",x"EE",x"40",x"32",x"EF", -- 0x0128 + x"40",x"CD",x"42",x"13",x"CD",x"F4",x"12",x"CD", -- 0x0130 + x"B6",x"12",x"DD",x"36",x"1F",x"05",x"DD",x"36", -- 0x0138 + x"1E",x"04",x"21",x"A7",x"01",x"FD",x"21",x"0F", -- 0x0140 + x"53",x"06",x"11",x"CD",x"3F",x"12",x"DD",x"21", -- 0x0148 + x"AF",x"40",x"3A",x"00",x"68",x"CB",x"47",x"20", -- 0x0150 + x"06",x"CB",x"4F",x"20",x"2A",x"18",x"EF",x"DD", -- 0x0158 + x"CB",x"00",x"FE",x"DD",x"CB",x"00",x"B6",x"21", -- 0x0160 + x"D9",x"40",x"CB",x"DE",x"21",x"B8",x"01",x"FD", -- 0x0168 + x"21",x"01",x"51",x"06",x"06",x"CD",x"3F",x"12", -- 0x0170 + x"3A",x"B0",x"40",x"D6",x"01",x"27",x"32",x"B0", -- 0x0178 + x"40",x"CD",x"9E",x"12",x"C3",x"A9",x"05",x"3A", -- 0x0180 + x"B0",x"40",x"FE",x"02",x"38",x"C0",x"21",x"D9", -- 0x0188 + x"40",x"CB",x"DE",x"DD",x"CB",x"00",x"BE",x"DD", -- 0x0190 + x"CB",x"00",x"F6",x"D6",x"02",x"27",x"32",x"B0", -- 0x0198 + x"40",x"CD",x"9E",x"12",x"C3",x"A9",x"05",x"50", -- 0x01A0 + x"55",x"53",x"48",x"40",x"53",x"54",x"41",x"52", -- 0x01A8 + x"54",x"40",x"42",x"55",x"54",x"54",x"4F",x"4E", -- 0x01B0 + x"40",x"40",x"40",x"40",x"40",x"40",x"DD",x"21", -- 0x01B8 + x"C0",x"41",x"CD",x"F4",x"12",x"3E",x"64",x"CD", -- 0x01C0 + x"38",x"13",x"DD",x"36",x"07",x"01",x"DD",x"36", -- 0x01C8 + x"06",x"04",x"FD",x"21",x"23",x"53",x"3E",x"02", -- 0x01D0 + x"CD",x"38",x"13",x"11",x"E0",x"FF",x"21",x"7D", -- 0x01D8 + x"04",x"06",x"14",x"CD",x"64",x"04",x"3E",x"14", -- 0x01E0 + x"CD",x"38",x"13",x"DD",x"36",x"0F",x"02",x"FD", -- 0x01E8 + x"21",x"67",x"52",x"21",x"91",x"04",x"06",x"08", -- 0x01F0 + x"CD",x"64",x"04",x"3E",x"50",x"CD",x"38",x"13", -- 0x01F8 + x"DD",x"36",x"20",x"FC",x"DD",x"36",x"22",x"FC", -- 0x0200 + x"DD",x"36",x"1C",x"00",x"DD",x"36",x"3E",x"00", -- 0x0208 + x"DD",x"36",x"3F",x"01",x"21",x"B0",x"52",x"11", -- 0x0210 + x"99",x"04",x"06",x"0D",x"1A",x"77",x"13",x"23", -- 0x0218 + x"1A",x"77",x"13",x"23",x"23",x"23",x"1A",x"77", -- 0x0220 + x"13",x"23",x"1A",x"77",x"13",x"D5",x"11",x"DB", -- 0x0228 + x"FF",x"19",x"D1",x"10",x"E7",x"3E",x"24",x"32", -- 0x0230 + x"0E",x"51",x"3E",x"1D",x"32",x"EE",x"50",x"21", -- 0x0238 + x"D5",x"03",x"11",x"E0",x"FF",x"FD",x"21",x"BF", -- 0x0240 + x"52",x"06",x"0E",x"CD",x"73",x"04",x"21",x"DD", -- 0x0248 + x"41",x"22",x"C0",x"40",x"21",x"08",x"03",x"22", -- 0x0250 + x"C2",x"40",x"21",x"BF",x"40",x"CB",x"C6",x"CB", -- 0x0258 + x"CE",x"3E",x"FF",x"CD",x"38",x"13",x"CB",x"86", -- 0x0260 + x"CB",x"8E",x"CD",x"F4",x"12",x"3E",x"32",x"CD", -- 0x0268 + x"38",x"13",x"DD",x"36",x"00",x"FC",x"DD",x"36", -- 0x0270 + x"02",x"FC",x"DD",x"36",x"3E",x"00",x"DD",x"36", -- 0x0278 + x"3F",x"01",x"21",x"A0",x"52",x"11",x"99",x"04", -- 0x0280 + x"06",x"0D",x"1A",x"77",x"13",x"23",x"1A",x"77", -- 0x0288 + x"13",x"13",x"13",x"D5",x"11",x"DF",x"FF",x"19", -- 0x0290 + x"D1",x"10",x"EF",x"21",x"C1",x"41",x"22",x"C0", -- 0x0298 + x"40",x"21",x"03",x"02",x"22",x"C2",x"40",x"21", -- 0x02A0 + x"BF",x"40",x"CB",x"C6",x"DD",x"36",x"09",x"03", -- 0x02A8 + x"21",x"B3",x"03",x"FD",x"21",x"C4",x"52",x"06", -- 0x02B0 + x"0E",x"CD",x"3F",x"12",x"21",x"D5",x"03",x"11", -- 0x02B8 + x"E0",x"FF",x"FD",x"21",x"BF",x"52",x"06",x"0E", -- 0x02C0 + x"CD",x"73",x"04",x"3E",x"32",x"CD",x"38",x"13", -- 0x02C8 + x"11",x"00",x"42",x"21",x"C1",x"03",x"01",x"14", -- 0x02D0 + x"00",x"ED",x"B0",x"21",x"CE",x"41",x"06",x"10", -- 0x02D8 + x"36",x"60",x"23",x"36",x"04",x"23",x"10",x"F8", -- 0x02E0 + x"06",x"06",x"36",x"00",x"23",x"36",x"04",x"23", -- 0x02E8 + x"10",x"F8",x"DD",x"21",x"BF",x"40",x"DD",x"CB", -- 0x02F0 + x"00",x"DE",x"21",x"E3",x"03",x"06",x"05",x"C5", -- 0x02F8 + x"11",x"C4",x"40",x"01",x"0A",x"00",x"ED",x"B0", -- 0x0300 + x"FD",x"2A",x"CC",x"40",x"EB",x"2A",x"CA",x"40", -- 0x0308 + x"EB",x"DD",x"CB",x"00",x"D6",x"1A",x"BE",x"20", -- 0x0310 + x"FC",x"23",x"FD",x"36",x"00",x"01",x"DD",x"CB", -- 0x0318 + x"00",x"56",x"20",x"FA",x"C1",x"10",x"D8",x"3E", -- 0x0320 + x"32",x"CD",x"38",x"13",x"FD",x"21",x"B8",x"52", -- 0x0328 + x"DD",x"21",x"B8",x"51",x"21",x"4C",x"04",x"11", -- 0x0330 + x"E0",x"FF",x"06",x"02",x"FD",x"E5",x"DD",x"E5", -- 0x0338 + x"C5",x"7E",x"FD",x"77",x"00",x"23",x"FD",x"19", -- 0x0340 + x"7E",x"FD",x"77",x"00",x"23",x"3E",x"32",x"CD", -- 0x0348 + x"38",x"13",x"06",x"0A",x"7E",x"DD",x"77",x"00", -- 0x0350 + x"23",x"DD",x"19",x"10",x"F7",x"3E",x"32",x"CD", -- 0x0358 + x"38",x"13",x"C1",x"DD",x"E1",x"FD",x"E1",x"DD", -- 0x0360 + x"23",x"DD",x"23",x"DD",x"23",x"FD",x"23",x"FD", -- 0x0368 + x"23",x"FD",x"23",x"10",x"C7",x"3E",x"FF",x"CD", -- 0x0370 + x"38",x"13",x"AF",x"32",x"BF",x"40",x"CD",x"F4", -- 0x0378 + x"12",x"3E",x"32",x"CD",x"38",x"13",x"CD",x"B6", -- 0x0380 + x"12",x"CD",x"AA",x"12",x"3A",x"BC",x"40",x"3C", -- 0x0388 + x"FE",x"05",x"20",x"02",x"3E",x"01",x"32",x"BC", -- 0x0390 + x"40",x"32",x"1E",x"40",x"21",x"AF",x"40",x"CB", -- 0x0398 + x"D6",x"E5",x"CD",x"93",x"06",x"E1",x"CB",x"8E", -- 0x03A0 + x"3E",x"40",x"CD",x"38",x"13",x"CD",x"AA",x"12", -- 0x03A8 + x"C3",x"BE",x"01",x"46",x"41",x"54",x"41",x"4C", -- 0x03B0 + x"49",x"54",x"59",x"40",x"53",x"43",x"4F",x"52", -- 0x03B8 + x"45",x"00",x"14",x"03",x"3F",x"00",x"18",x"00", -- 0x03C0 + x"5C",x"00",x"13",x"06",x"6F",x"00",x"15",x"06", -- 0x03C8 + x"8B",x"00",x"32",x"04",x"A2",x"13",x"1F",x"20", -- 0x03D0 + x"29",x"22",x"19",x"17",x"18",x"24",x"10",x"01", -- 0x03D8 + x"09",x"08",x"02",x"1A",x"04",x"A9",x"51",x"0A", -- 0x03E0 + x"01",x"D2",x"41",x"00",x"42",x"50",x"24",x"04", -- 0x03E8 + x"AC",x"51",x"0A",x"01",x"D8",x"41",x"04",x"42", -- 0x03F0 + x"4C",x"2E",x"04",x"AF",x"51",x"0A",x"01",x"DE", -- 0x03F8 + x"41",x"08",x"42",x"50",x"38",x"04",x"B2",x"51", -- 0x0400 + x"0A",x"01",x"E4",x"41",x"0C",x"42",x"4C",x"42", -- 0x0408 + x"04",x"B5",x"51",x"0A",x"01",x"EA",x"41",x"10", -- 0x0410 + x"42",x"4C",x"10",x"05",x"03",x"10",x"20",x"1F", -- 0x0418 + x"19",x"1E",x"24",x"23",x"01",x"00",x"00",x"10", -- 0x0420 + x"20",x"1F",x"19",x"1E",x"24",x"23",x"02",x"00", -- 0x0428 + x"00",x"10",x"20",x"1F",x"19",x"1E",x"24",x"23", -- 0x0430 + x"01",x"05",x"00",x"10",x"20",x"1F",x"19",x"1E", -- 0x0438 + x"24",x"23",x"10",x"03",x"00",x"10",x"20",x"1F", -- 0x0440 + x"19",x"1E",x"24",x"23",x"0C",x"10",x"01",x"00", -- 0x0448 + x"00",x"10",x"20",x"1F",x"19",x"1E",x"24",x"23", -- 0x0450 + x"0D",x"10",x"10",x"05",x"00",x"10",x"20",x"1F", -- 0x0458 + x"19",x"1E",x"24",x"23",x"7E",x"FD",x"77",x"00", -- 0x0460 + x"23",x"FD",x"19",x"3E",x"0A",x"CD",x"38",x"13", -- 0x0468 + x"10",x"F2",x"C9",x"7E",x"FD",x"77",x"00",x"23", -- 0x0470 + x"FD",x"19",x"10",x"F7",x"C9",x"22",x"11",x"19", -- 0x0478 + x"24",x"10",x"15",x"1C",x"15",x"13",x"24",x"22", -- 0x0480 + x"1F",x"1E",x"19",x"13",x"23",x"10",x"1C",x"24", -- 0x0488 + x"14",x"20",x"22",x"15",x"23",x"15",x"1E",x"24", -- 0x0490 + x"23",x"68",x"6B",x"68",x"6B",x"69",x"6A",x"69", -- 0x0498 + x"6A",x"6C",x"6F",x"BB",x"B5",x"6D",x"6E",x"BA", -- 0x04A0 + x"B4",x"AC",x"AF",x"BB",x"B5",x"AD",x"AE",x"BA", -- 0x04A8 + x"B4",x"B0",x"B3",x"68",x"6B",x"B1",x"B2",x"69", -- 0x04B0 + x"6A",x"0A",x"0A",x"BD",x"BF",x"68",x"6B",x"BC", -- 0x04B8 + x"BE",x"69",x"6A",x"C1",x"C3",x"B7",x"B9",x"C0", -- 0x04C0 + x"C2",x"B6",x"B8",x"10",x"10",x"0F",x"DC",x"13", -- 0x04C8 + x"05",x"0F",x"DC",x"E0",x"04",x"0F",x"F5",x"DC", -- 0x04D0 + x"2F",x"05",x"F1",x"0F",x"DC",x"63",x"05",x"C9", -- 0x04D8 + x"DD",x"21",x"37",x"40",x"FD",x"21",x"04",x"42", -- 0x04E0 + x"DD",x"CB",x"00",x"56",x"F5",x"C4",x"D6",x"1C", -- 0x04E8 + x"F1",x"C0",x"F5",x"CD",x"67",x"0B",x"E6",x"0F", -- 0x04F0 + x"6F",x"26",x"00",x"29",x"11",x"89",x"05",x"19", -- 0x04F8 + x"7E",x"FD",x"77",x"00",x"23",x"7E",x"FD",x"77", -- 0x0500 + x"03",x"FD",x"36",x"01",x"13",x"DD",x"36",x"00", -- 0x0508 + x"07",x"F1",x"C9",x"21",x"C3",x"40",x"35",x"C0", -- 0x0510 + x"F5",x"36",x"03",x"2B",x"46",x"2A",x"C0",x"40", -- 0x0518 + x"7E",x"3C",x"FE",x"08",x"20",x"02",x"3E",x"01", -- 0x0520 + x"77",x"23",x"23",x"10",x"FB",x"F1",x"C9",x"2A", -- 0x0528 + x"CC",x"40",x"7E",x"A7",x"28",x"01",x"34",x"2A", -- 0x0530 + x"CA",x"40",x"35",x"20",x"05",x"21",x"BF",x"40", -- 0x0538 + x"CB",x"96",x"21",x"C9",x"40",x"35",x"C0",x"36", -- 0x0540 + x"08",x"2B",x"7E",x"A7",x"C8",x"35",x"2A",x"C6", -- 0x0548 + x"40",x"EB",x"2A",x"C4",x"40",x"7E",x"12",x"23", -- 0x0550 + x"22",x"C4",x"40",x"21",x"E0",x"FF",x"19",x"22", -- 0x0558 + x"C6",x"40",x"C9",x"3A",x"92",x"51",x"FE",x"10", -- 0x0560 + x"C8",x"21",x"45",x"40",x"FD",x"21",x"0C",x"42", -- 0x0568 + x"34",x"7E",x"E6",x"18",x"20",x"0A",x"FD",x"36", -- 0x0570 + x"02",x"07",x"3E",x"05",x"32",x"92",x"51",x"C9", -- 0x0578 + x"FD",x"36",x"02",x"06",x"AF",x"32",x"92",x"51", -- 0x0580 + x"C9",x"28",x"94",x"B8",x"94",x"AB",x"76",x"A0", -- 0x0588 + x"A6",x"40",x"A8",x"40",x"78",x"63",x"63",x"85", -- 0x0590 + x"6B",x"73",x"7C",x"59",x"8C",x"79",x"93",x"79", -- 0x0598 + x"99",x"89",x"A4",x"95",x"9C",x"60",x"A0",x"54", -- 0x05A0 + x"A8",x"DD",x"CB",x"00",x"EE",x"CD",x"17",x"13", -- 0x05A8 + x"CD",x"AA",x"12",x"06",x"03",x"3A",x"00",x"68", -- 0x05B0 + x"4F",x"CB",x"7F",x"28",x"02",x"06",x"05",x"78", -- 0x05B8 + x"32",x"1D",x"40",x"06",x"04",x"CB",x"71",x"28", -- 0x05C0 + x"02",x"06",x"02",x"3A",x"00",x"70",x"0F",x"0F", -- 0x05C8 + x"E6",x"01",x"EE",x"01",x"80",x"32",x"F4",x"40", -- 0x05D0 + x"21",x"1D",x"40",x"11",x"00",x"41",x"01",x"1A", -- 0x05D8 + x"00",x"ED",x"B0",x"21",x"A9",x"40",x"06",x"03", -- 0x05E0 + x"AF",x"77",x"23",x"10",x"FC",x"CD",x"4E",x"12", -- 0x05E8 + x"3A",x"AF",x"40",x"CB",x"7F",x"20",x"0D",x"21", -- 0x05F0 + x"AC",x"40",x"06",x"03",x"AF",x"77",x"23",x"10", -- 0x05F8 + x"FC",x"CD",x"57",x"12",x"21",x"BE",x"40",x"06", -- 0x0600 + x"50",x"3A",x"00",x"70",x"CB",x"4F",x"28",x"02", -- 0x0608 + x"06",x"70",x"78",x"F6",x"03",x"77",x"21",x"AF", -- 0x0610 + x"40",x"4E",x"06",x"00",x"CB",x"A6",x"CB",x"69", -- 0x0618 + x"20",x"0B",x"3A",x"00",x"70",x"CB",x"5F",x"28", -- 0x0620 + x"04",x"06",x"01",x"CB",x"E6",x"78",x"32",x"06", -- 0x0628 + x"70",x"32",x"07",x"70",x"11",x"E0",x"FF",x"21", -- 0x0630 + x"9F",x"53",x"06",x"06",x"3E",x"10",x"77",x"19", -- 0x0638 + x"10",x"FC",x"3A",x"1D",x"40",x"32",x"BF",x"53", -- 0x0640 + x"A7",x"28",x"0A",x"47",x"21",x"9F",x"53",x"3E", -- 0x0648 + x"0F",x"77",x"19",x"10",x"FC",x"DD",x"21",x"C0", -- 0x0650 + x"41",x"DD",x"36",x"13",x"02",x"DD",x"36",x"12", -- 0x0658 + x"04",x"DD",x"36",x"17",x"06",x"CD",x"2E",x"08", -- 0x0660 + x"06",x"06",x"C5",x"21",x"02",x"08",x"FD",x"21", -- 0x0668 + x"49",x"52",x"06",x"05",x"CD",x"3F",x"12",x"3E", -- 0x0670 + x"10",x"CD",x"38",x"13",x"21",x"F2",x"07",x"FD", -- 0x0678 + x"21",x"49",x"52",x"06",x"05",x"CD",x"3F",x"12", -- 0x0680 + x"3E",x"0A",x"CD",x"38",x"13",x"C1",x"10",x"DA", -- 0x0688 + x"CD",x"17",x"13",x"21",x"16",x"11",x"11",x"00", -- 0x0690 + x"40",x"01",x"15",x"00",x"ED",x"B0",x"21",x"4D", -- 0x0698 + x"11",x"11",x"37",x"40",x"01",x"70",x"00",x"ED", -- 0x06A0 + x"B0",x"21",x"95",x"0E",x"3A",x"1E",x"40",x"E6", -- 0x06A8 + x"03",x"20",x"03",x"21",x"40",x"10",x"CD",x"07", -- 0x06B0 + x"14",x"CD",x"C4",x"13",x"21",x"AF",x"40",x"CB", -- 0x06B8 + x"CE",x"CD",x"B9",x"07",x"3A",x"01",x"40",x"CB", -- 0x06C0 + x"47",x"C2",x"D2",x"06",x"CD",x"83",x"09",x"C3", -- 0x06C8 + x"C1",x"06",x"DD",x"21",x"37",x"40",x"06",x"07", -- 0x06D0 + x"11",x"10",x"00",x"DD",x"CB",x"00",x"FE",x"DD", -- 0x06D8 + x"19",x"10",x"F8",x"CD",x"B9",x"07",x"3A",x"16", -- 0x06E0 + x"40",x"A7",x"20",x"F7",x"3A",x"01",x"40",x"CB", -- 0x06E8 + x"57",x"28",x"F0",x"21",x"AF",x"40",x"CB",x"56", -- 0x06F0 + x"C0",x"CB",x"8E",x"3E",x"40",x"CD",x"38",x"13", -- 0x06F8 + x"21",x"00",x"68",x"AF",x"06",x"03",x"77",x"23", -- 0x0700 + x"10",x"FC",x"CD",x"17",x"13",x"3A",x"AF",x"40", -- 0x0708 + x"CB",x"77",x"C2",x"45",x"07",x"3A",x"1D",x"40", -- 0x0710 + x"A7",x"C2",x"95",x"07",x"CD",x"46",x"08",x"CD", -- 0x0718 + x"14",x"21",x"3A",x"1D",x"40",x"A7",x"C2",x"95", -- 0x0720 + x"07",x"21",x"06",x"70",x"AF",x"77",x"23",x"77", -- 0x0728 + x"21",x"AF",x"40",x"CB",x"A6",x"CD",x"07",x"08", -- 0x0730 + x"3E",x"64",x"CD",x"38",x"13",x"21",x"AF",x"40", -- 0x0738 + x"CB",x"9E",x"C3",x"BE",x"01",x"3A",x"1D",x"40", -- 0x0740 + x"A7",x"20",x"28",x"CD",x"07",x"08",x"DD",x"36", -- 0x0748 + x"17",x"06",x"3A",x"AF",x"40",x"4F",x"CD",x"2E", -- 0x0750 + x"08",x"3E",x"30",x"CD",x"38",x"13",x"CD",x"46", -- 0x0758 + x"08",x"CD",x"14",x"21",x"3A",x"00",x"41",x"A7", -- 0x0760 + x"20",x"10",x"3A",x"1D",x"40",x"A7",x"20",x"03", -- 0x0768 + x"C3",x"29",x"07",x"3A",x"00",x"41",x"A7",x"CA", -- 0x0770 + x"95",x"07",x"21",x"1D",x"40",x"11",x"00",x"41", -- 0x0778 + x"06",x"1A",x"1A",x"4F",x"7E",x"12",x"71",x"13", -- 0x0780 + x"23",x"10",x"F7",x"21",x"AF",x"40",x"3E",x"20", -- 0x0788 + x"AE",x"77",x"C3",x"95",x"07",x"3A",x"1E",x"40", -- 0x0790 + x"E6",x"03",x"CA",x"16",x"06",x"FD",x"21",x"37", -- 0x0798 + x"40",x"3D",x"20",x"06",x"FD",x"34",x"F7",x"C3", -- 0x07A0 + x"16",x"06",x"3D",x"20",x"06",x"FD",x"34",x"FC", -- 0x07A8 + x"C3",x"16",x"06",x"FD",x"34",x"FA",x"C3",x"16", -- 0x07B0 + x"06",x"3A",x"1E",x"40",x"E6",x"03",x"28",x"1F", -- 0x07B8 + x"CD",x"18",x"0B",x"CD",x"C4",x"08",x"CD",x"F6", -- 0x07C0 + x"25",x"CD",x"96",x"28",x"CD",x"11",x"1F",x"CD", -- 0x07C8 + x"7D",x"20",x"CD",x"08",x"14",x"CD",x"00",x"0C", -- 0x07D0 + x"CD",x"73",x"08",x"CD",x"F2",x"24",x"C9",x"CD", -- 0x07D8 + x"73",x"08",x"CD",x"08",x"14",x"CD",x"30",x"17", -- 0x07E0 + x"CD",x"7F",x"19",x"CD",x"54",x"0E",x"CD",x"4B", -- 0x07E8 + x"25",x"C9",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x07F0 + x"40",x"40",x"40",x"40",x"50",x"4C",x"41",x"59", -- 0x07F8 + x"45",x"52",x"52",x"45",x"41",x"44",x"59",x"DD", -- 0x0800 + x"21",x"C0",x"41",x"DD",x"36",x"13",x"02",x"DD", -- 0x0808 + x"36",x"12",x"04",x"3E",x"01",x"CD",x"38",x"13", -- 0x0810 + x"21",x"25",x"08",x"FD",x"21",x"89",x"52",x"06", -- 0x0818 + x"09",x"CD",x"3F",x"12",x"C9",x"47",x"41",x"4D", -- 0x0820 + x"45",x"40",x"4F",x"56",x"45",x"52",x"21",x"FC", -- 0x0828 + x"07",x"FD",x"21",x"6B",x"52",x"06",x"06",x"CD", -- 0x0830 + x"3F",x"12",x"3E",x"01",x"CB",x"69",x"20",x"02", -- 0x0838 + x"3E",x"02",x"32",x"8B",x"51",x"C9",x"11",x"A9", -- 0x0840 + x"40",x"3A",x"AF",x"40",x"4F",x"CB",x"6F",x"20", -- 0x0848 + x"03",x"11",x"AC",x"40",x"D5",x"21",x"B3",x"40", -- 0x0850 + x"E5",x"06",x"03",x"1A",x"BE",x"38",x"11",x"20", -- 0x0858 + x"04",x"23",x"13",x"10",x"F6",x"D1",x"E1",x"01", -- 0x0860 + x"03",x"00",x"ED",x"B0",x"CD",x"60",x"12",x"C9", -- 0x0868 + x"E1",x"E1",x"C9",x"06",x"01",x"11",x"A9",x"40", -- 0x0870 + x"3A",x"AF",x"40",x"CB",x"6F",x"20",x"05",x"11", -- 0x0878 + x"AC",x"40",x"CB",x"20",x"21",x"BE",x"40",x"78", -- 0x0880 + x"A6",x"C8",x"1A",x"A7",x"20",x"08",x"13",x"7E", -- 0x0888 + x"E6",x"F0",x"4F",x"1A",x"B9",x"D8",x"78",x"AE", -- 0x0890 + x"77",x"21",x"1D",x"40",x"34",x"11",x"E0",x"FF", -- 0x0898 + x"21",x"9F",x"53",x"06",x"06",x"3E",x"10",x"77", -- 0x08A0 + x"19",x"10",x"FC",x"3A",x"1D",x"40",x"32",x"BF", -- 0x08A8 + x"53",x"A7",x"28",x"0A",x"47",x"21",x"9F",x"53", -- 0x08B0 + x"3E",x"0F",x"77",x"19",x"10",x"FC",x"21",x"D9", -- 0x08B8 + x"40",x"CB",x"E6",x"C9",x"3A",x"01",x"40",x"CB", -- 0x08C0 + x"47",x"C0",x"DD",x"21",x"37",x"40",x"FD",x"21", -- 0x08C8 + x"04",x"42",x"3A",x"1E",x"40",x"E6",x"03",x"FE", -- 0x08D0 + x"01",x"CA",x"74",x"25",x"FE",x"02",x"CA",x"4B", -- 0x08D8 + x"27",x"FE",x"03",x"CA",x"58",x"1F",x"C9",x"1E", -- 0x08E0 + x"00",x"3A",x"00",x"42",x"FD",x"96",x"00",x"30", -- 0x08E8 + x"04",x"ED",x"44",x"CB",x"C3",x"47",x"3A",x"03", -- 0x08F0 + x"42",x"FD",x"96",x"03",x"30",x"04",x"ED",x"44", -- 0x08F8 + x"CB",x"CB",x"4F",x"B8",x"38",x"04",x"CB",x"FB", -- 0x0900 + x"48",x"47",x"CB",x"21",x"CB",x"21",x"78",x"B9", -- 0x0908 + x"30",x"0B",x"CB",x"20",x"80",x"30",x"0C",x"0E", -- 0x0910 + x"01",x"06",x"01",x"18",x"0A",x"0E",x"00",x"06", -- 0x0918 + x"02",x"18",x"04",x"0E",x"01",x"06",x"02",x"CB", -- 0x0920 + x"7B",x"28",x"03",x"78",x"41",x"4F",x"CB",x"43", -- 0x0928 + x"28",x"04",x"78",x"ED",x"44",x"47",x"CB",x"4B", -- 0x0930 + x"28",x"04",x"79",x"ED",x"44",x"4F",x"C9",x"DD", -- 0x0938 + x"21",x"37",x"40",x"FD",x"21",x"04",x"42",x"DD", -- 0x0940 + x"7E",x"DF",x"FE",x"07",x"C8",x"06",x"07",x"DD", -- 0x0948 + x"CB",x"00",x"56",x"CA",x"07",x"14",x"CD",x"78", -- 0x0950 + x"09",x"10",x"F4",x"C9",x"DD",x"21",x"37",x"40", -- 0x0958 + x"FD",x"21",x"04",x"42",x"06",x"07",x"FD",x"BE", -- 0x0960 + x"01",x"F5",x"C5",x"E5",x"CC",x"07",x"14",x"E1", -- 0x0968 + x"C1",x"F1",x"CD",x"78",x"09",x"10",x"EF",x"C9", -- 0x0970 + x"11",x"10",x"00",x"DD",x"19",x"11",x"04",x"00", -- 0x0978 + x"FD",x"19",x"C9",x"3A",x"1E",x"40",x"E6",x"03", -- 0x0980 + x"FE",x"01",x"CA",x"98",x"09",x"FE",x"02",x"CA", -- 0x0988 + x"B3",x"09",x"FE",x"03",x"CA",x"CE",x"09",x"C9", -- 0x0990 + x"21",x"2E",x"40",x"7E",x"A7",x"C0",x"3A",x"18", -- 0x0998 + x"40",x"FE",x"01",x"D0",x"21",x"CF",x"40",x"35", -- 0x09A0 + x"C0",x"23",x"35",x"C0",x"36",x"02",x"21",x"1E", -- 0x09A8 + x"40",x"34",x"C9",x"21",x"33",x"40",x"7E",x"A7", -- 0x09B0 + x"C0",x"21",x"16",x"40",x"7E",x"A7",x"C0",x"21", -- 0x09B8 + x"CF",x"40",x"35",x"C0",x"23",x"35",x"C0",x"36", -- 0x09C0 + x"02",x"21",x"1E",x"40",x"34",x"C9",x"21",x"31", -- 0x09C8 + x"40",x"7E",x"A7",x"C0",x"3A",x"19",x"40",x"A7", -- 0x09D0 + x"C0",x"01",x"00",x"01",x"C5",x"CD",x"B9",x"07", -- 0x09D8 + x"3A",x"16",x"40",x"A7",x"20",x"F7",x"C1",x"0B", -- 0x09E0 + x"78",x"B1",x"20",x"F0",x"21",x"AF",x"40",x"CB", -- 0x09E8 + x"8E",x"21",x"00",x"42",x"11",x"01",x"42",x"01", -- 0x09F0 + x"40",x"00",x"36",x"00",x"ED",x"B0",x"3E",x"50", -- 0x09F8 + x"CD",x"38",x"13",x"CD",x"17",x"13",x"3E",x"08", -- 0x0A00 + x"CD",x"38",x"13",x"3A",x"1E",x"40",x"3C",x"32", -- 0x0A08 + x"1E",x"40",x"CD",x"40",x"10",x"3E",x"20",x"CD", -- 0x0A10 + x"38",x"13",x"11",x"00",x"42",x"21",x"29",x"0A", -- 0x0A18 + x"01",x"04",x"00",x"ED",x"B0",x"E1",x"C3",x"BC", -- 0x0A20 + x"06",x"E0",x"11",x"01",x"E0",x"21",x"AF",x"40", -- 0x0A28 + x"CB",x"8E",x"21",x"00",x"68",x"AF",x"77",x"23", -- 0x0A30 + x"77",x"23",x"77",x"31",x"00",x"44",x"21",x"28", -- 0x0A38 + x"40",x"FD",x"21",x"05",x"53",x"AF",x"ED",x"67", -- 0x0A40 + x"FD",x"77",x"00",x"ED",x"67",x"FD",x"77",x"20", -- 0x0A48 + x"ED",x"67",x"2B",x"AF",x"ED",x"67",x"FD",x"77", -- 0x0A50 + x"40",x"ED",x"67",x"FD",x"77",x"60",x"ED",x"67", -- 0x0A58 + x"3E",x"60",x"CD",x"38",x"13",x"21",x"D1",x"41", -- 0x0A60 + x"22",x"C0",x"40",x"21",x"12",x"03",x"22",x"C2", -- 0x0A68 + x"40",x"3E",x"01",x"32",x"BF",x"40",x"06",x"11", -- 0x0A70 + x"FD",x"21",x"05",x"53",x"21",x"EF",x"40",x"E5", -- 0x0A78 + x"CB",x"FE",x"3E",x"01",x"CD",x"38",x"13",x"21", -- 0x0A80 + x"28",x"40",x"7E",x"90",x"27",x"77",x"F5",x"AF", -- 0x0A88 + x"ED",x"67",x"FD",x"77",x"00",x"ED",x"67",x"FD", -- 0x0A90 + x"77",x"20",x"ED",x"67",x"2B",x"F1",x"7E",x"DE", -- 0x0A98 + x"00",x"27",x"77",x"AF",x"ED",x"67",x"FD",x"77", -- 0x0AA0 + x"40",x"ED",x"67",x"FD",x"77",x"60",x"ED",x"67", -- 0x0AA8 + x"16",x"00",x"58",x"E5",x"C5",x"FD",x"E5",x"CD", -- 0x0AB0 + x"72",x"19",x"FD",x"E1",x"C1",x"E1",x"7E",x"A7", -- 0x0AB8 + x"20",x"C0",x"06",x"01",x"23",x"7E",x"A7",x"20", -- 0x0AC0 + x"B9",x"E1",x"CB",x"BE",x"3E",x"60",x"CD",x"38", -- 0x0AC8 + x"13",x"21",x"D1",x"41",x"3E",x"04",x"BE",x"20", -- 0x0AD0 + x"FD",x"AF",x"32",x"BF",x"40",x"21",x"14",x"0B", -- 0x0AD8 + x"FD",x"21",x"65",x"53",x"06",x"04",x"CD",x"3F", -- 0x0AE0 + x"12",x"3E",x"78",x"CD",x"38",x"13",x"CD",x"17", -- 0x0AE8 + x"13",x"21",x"1E",x"40",x"34",x"7E",x"E6",x"C0", -- 0x0AF0 + x"28",x"03",x"3E",x"3D",x"77",x"CD",x"7F",x"26", -- 0x0AF8 + x"21",x"00",x"42",x"36",x"80",x"23",x"36",x"10", -- 0x0B00 + x"23",x"36",x"01",x"23",x"36",x"80",x"CD",x"95", -- 0x0B08 + x"0E",x"C3",x"BC",x"06",x"48",x"4F",x"4D",x"45", -- 0x0B10 + x"DD",x"21",x"37",x"40",x"FD",x"21",x"04",x"42", -- 0x0B18 + x"21",x"16",x"40",x"06",x"07",x"AF",x"77",x"23", -- 0x0B20 + x"10",x"FC",x"06",x"07",x"DD",x"CB",x"00",x"56", -- 0x0B28 + x"28",x"17",x"DD",x"CB",x"00",x"46",x"20",x"11", -- 0x0B30 + x"FD",x"7E",x"01",x"D6",x"13",x"FE",x"07",x"30", -- 0x0B38 + x"08",x"21",x"16",x"40",x"34",x"85",x"6F",x"23", -- 0x0B40 + x"34",x"CD",x"78",x"09",x"10",x"DE",x"C9",x"DD", -- 0x0B48 + x"CB",x"00",x"46",x"C0",x"AF",x"FD",x"77",x"00", -- 0x0B50 + x"FD",x"77",x"01",x"FD",x"77",x"03",x"DD",x"CB", -- 0x0B58 + x"00",x"8E",x"DD",x"CB",x"00",x"96",x"C9",x"E5", -- 0x0B60 + x"21",x"A7",x"40",x"7E",x"0F",x"AE",x"07",x"23", -- 0x0B68 + x"34",x"86",x"EA",x"76",x"0B",x"34",x"2B",x"77", -- 0x0B70 + x"E1",x"C9",x"05",x"20",x"05",x"20",x"05",x"20", -- 0x0B78 + x"05",x"20",x"05",x"20",x"05",x"21",x"05",x"22", -- 0x0B80 + x"05",x"12",x"05",x"02",x"05",x"12",x"05",x"11", -- 0x0B88 + x"05",x"FE",x"05",x"20",x"05",x"2F",x"05",x"1F", -- 0x0B90 + x"05",x"1E",x"05",x"0E",x"05",x"1E",x"05",x"1F", -- 0x0B98 + x"05",x"2F",x"05",x"20",x"05",x"21",x"05",x"11", -- 0x0BA0 + x"05",x"12",x"05",x"02",x"05",x"F2",x"05",x"F1", -- 0x0BA8 + x"05",x"E1",x"05",x"E0",x"05",x"E1",x"05",x"F1", -- 0x0BB0 + x"05",x"F1",x"05",x"F1",x"05",x"F1",x"05",x"F1", -- 0x0BB8 + x"05",x"E1",x"05",x"E0",x"05",x"E1",x"05",x"F1", -- 0x0BC0 + x"05",x"F2",x"05",x"02",x"05",x"12",x"05",x"11", -- 0x0BC8 + x"05",x"21",x"05",x"20",x"05",x"2F",x"05",x"1F", -- 0x0BD0 + x"05",x"1E",x"05",x"0E",x"05",x"FE",x"05",x"FF", -- 0x0BD8 + x"05",x"EF",x"05",x"E0",x"05",x"E0",x"05",x"FF", -- 0x0BE0 + x"05",x"FF",x"05",x"FF",x"05",x"FF",x"05",x"FF", -- 0x0BE8 + x"05",x"FF",x"05",x"FF",x"05",x"FE",x"05",x"0E", -- 0x0BF0 + x"05",x"1E",x"05",x"1F",x"05",x"1E",x"05",x"20", -- 0x0BF8 + x"3A",x"01",x"40",x"CB",x"47",x"C0",x"FD",x"21", -- 0x0C00 + x"00",x"42",x"FD",x"66",x"00",x"FD",x"6E",x"03", -- 0x0C08 + x"DD",x"21",x"37",x"40",x"FD",x"21",x"04",x"42", -- 0x0C10 + x"06",x"07",x"DD",x"CB",x"00",x"56",x"E5",x"C5", -- 0x0C18 + x"C4",x"2B",x"0C",x"C1",x"E1",x"CD",x"78",x"09", -- 0x0C20 + x"10",x"F0",x"C9",x"DD",x"CB",x"00",x"46",x"C0", -- 0x0C28 + x"7C",x"FD",x"96",x"00",x"57",x"30",x"02",x"ED", -- 0x0C30 + x"44",x"FE",x"10",x"D0",x"47",x"3E",x"10",x"90", -- 0x0C38 + x"47",x"7D",x"FD",x"96",x"03",x"4F",x"30",x"02", -- 0x0C40 + x"ED",x"44",x"FE",x"10",x"D0",x"7A",x"F5",x"21", -- 0x0C48 + x"AC",x"14",x"FD",x"7E",x"01",x"D6",x"13",x"FE", -- 0x0C50 + x"06",x"D2",x"C8",x"0C",x"0F",x"0F",x"0F",x"5F", -- 0x0C58 + x"16",x"00",x"19",x"E5",x"21",x"D9",x"0C",x"3A", -- 0x0C60 + x"01",x"42",x"BE",x"28",x"05",x"23",x"23",x"23", -- 0x0C68 + x"18",x"F8",x"23",x"5E",x"23",x"56",x"E1",x"F1", -- 0x0C70 + x"A7",x"FA",x"AF",x"0C",x"CB",x"27",x"85",x"6F", -- 0x0C78 + x"3E",x"00",x"8C",x"67",x"EB",x"1A",x"81",x"C6", -- 0x0C80 + x"20",x"23",x"BE",x"DA",x"BC",x"0C",x"2B",x"13", -- 0x0C88 + x"1A",x"81",x"C6",x"20",x"BE",x"28",x"03",x"D2", -- 0x0C90 + x"C2",x"0C",x"3A",x"1E",x"40",x"E6",x"03",x"CA", -- 0x0C98 + x"79",x"0E",x"CD",x"EB",x"18",x"DD",x"CB",x"00", -- 0x0CA0 + x"C6",x"21",x"01",x"40",x"CB",x"C6",x"C9",x"ED", -- 0x0CA8 + x"44",x"CB",x"27",x"83",x"5F",x"3E",x"00",x"8A", -- 0x0CB0 + x"57",x"C3",x"84",x"0C",x"13",x"13",x"23",x"10", -- 0x0CB8 + x"C4",x"C9",x"23",x"23",x"13",x"10",x"BE",x"C9", -- 0x0CC0 + x"21",x"F1",x"0D",x"FD",x"7E",x"01",x"11",x"20", -- 0x0CC8 + x"00",x"BE",x"23",x"CA",x"63",x"0C",x"19",x"18", -- 0x0CD0 + x"F8",x"10",x"F1",x"0C",x"50",x"11",x"0D",x"11", -- 0x0CD8 + x"31",x"0D",x"91",x"51",x"0D",x"12",x"71",x"0D", -- 0x0CE0 + x"52",x"91",x"0D",x"92",x"B1",x"0D",x"D2",x"D1", -- 0x0CE8 + x"0D",x"25",x"21",x"24",x"21",x"24",x"21",x"29", -- 0x0CF0 + x"23",x"2A",x"23",x"2B",x"23",x"2C",x"23",x"2B", -- 0x0CF8 + x"23",x"2A",x"23",x"29",x"23",x"24",x"21",x"24", -- 0x0D00 + x"21",x"25",x"21",x"50",x"50",x"50",x"50",x"50", -- 0x0D08 + x"50",x"50",x"50",x"50",x"50",x"50",x"50",x"2E", -- 0x0D10 + x"2A",x"2E",x"2B",x"2E",x"2B",x"2C",x"26",x"2C", -- 0x0D18 + x"25",x"2C",x"24",x"2C",x"23",x"2C",x"24",x"2C", -- 0x0D20 + x"25",x"2C",x"26",x"2E",x"2B",x"2E",x"2B",x"2E", -- 0x0D28 + x"2A",x"2C",x"22",x"2C",x"22",x"2C",x"22",x"2C", -- 0x0D30 + x"22",x"2C",x"22",x"2C",x"22",x"29",x"25",x"29", -- 0x0D38 + x"25",x"28",x"26",x"28",x"26",x"28",x"26",x"28", -- 0x0D40 + x"26",x"2A",x"24",x"29",x"25",x"28",x"26",x"27", -- 0x0D48 + x"27",x"28",x"28",x"29",x"27",x"2A",x"26",x"2B", -- 0x0D50 + x"25",x"29",x"27",x"29",x"27",x"29",x"27",x"29", -- 0x0D58 + x"27",x"2A",x"26",x"2A",x"26",x"2D",x"23",x"2D", -- 0x0D60 + x"23",x"2D",x"23",x"2D",x"23",x"2D",x"23",x"2D", -- 0x0D68 + x"23",x"2B",x"2B",x"2B",x"2A",x"2B",x"29",x"2D", -- 0x0D70 + x"2A",x"2B",x"2A",x"2B",x"29",x"2B",x"29",x"2B", -- 0x0D78 + x"26",x"2C",x"25",x"2F",x"24",x"2F",x"24",x"2F", -- 0x0D80 + x"25",x"2F",x"26",x"2F",x"2C",x"2F",x"2C",x"2F", -- 0x0D88 + x"2B",x"24",x"24",x"25",x"22",x"26",x"22",x"25", -- 0x0D90 + x"22",x"25",x"24",x"26",x"24",x"26",x"24",x"29", -- 0x0D98 + x"24",x"2A",x"23",x"2B",x"20",x"2B",x"20",x"2A", -- 0x0DA0 + x"20",x"29",x"20",x"23",x"20",x"23",x"20",x"24", -- 0x0DA8 + x"20",x"2F",x"2B",x"2F",x"2C",x"2F",x"2C",x"2F", -- 0x0DB0 + x"26",x"2F",x"25",x"2F",x"24",x"2F",x"24",x"2C", -- 0x0DB8 + x"25",x"2B",x"26",x"2B",x"29",x"2B",x"29",x"2B", -- 0x0DC0 + x"2A",x"2D",x"2A",x"2B",x"29",x"2B",x"2A",x"2B", -- 0x0DC8 + x"2B",x"24",x"20",x"23",x"20",x"23",x"20",x"29", -- 0x0DD0 + x"20",x"2A",x"20",x"2B",x"20",x"2B",x"20",x"2A", -- 0x0DD8 + x"23",x"29",x"24",x"26",x"24",x"26",x"24",x"25", -- 0x0DE0 + x"24",x"25",x"22",x"26",x"22",x"25",x"22",x"24", -- 0x0DE8 + x"24",x"33",x"0F",x"08",x"0F",x"08",x"0F",x"08", -- 0x0DF0 + x"0F",x"08",x"0F",x"08",x"0F",x"08",x"0F",x"08", -- 0x0DF8 + x"0F",x"08",x"0F",x"08",x"0F",x"06",x"0F",x"04", -- 0x0E00 + x"0F",x"02",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x0E08 + x"0F",x"00",x"B3",x"0F",x"00",x"0F",x"00",x"0F", -- 0x0E10 + x"00",x"0F",x"00",x"0F",x"02",x"0F",x"04",x"0F", -- 0x0E18 + x"06",x"0F",x"08",x"0F",x"08",x"0F",x"08",x"0F", -- 0x0E20 + x"08",x"0F",x"08",x"0F",x"08",x"0F",x"08",x"0F", -- 0x0E28 + x"08",x"0F",x"08",x"97",x"0F",x"06",x"0F",x"05", -- 0x0E30 + x"0F",x"04",x"0F",x"03",x"0F",x"02",x"0F",x"01", -- 0x0E38 + x"0F",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x0E40 + x"0F",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x0E48 + x"0F",x"00",x"0F",x"00",x"3A",x"01",x"40",x"CB", -- 0x0E50 + x"47",x"C0",x"FD",x"21",x"00",x"42",x"FD",x"66", -- 0x0E58 + x"00",x"FD",x"6E",x"03",x"FD",x"21",x"04",x"42", -- 0x0E60 + x"06",x"04",x"E5",x"C5",x"CD",x"30",x"0C",x"C1", -- 0x0E68 + x"E1",x"11",x"04",x"00",x"FD",x"19",x"10",x"F2", -- 0x0E70 + x"C9",x"E1",x"E1",x"E1",x"FD",x"7E",x"01",x"FE", -- 0x0E78 + x"33",x"28",x"0A",x"FE",x"B3",x"28",x"06",x"21", -- 0x0E80 + x"01",x"40",x"CB",x"C6",x"C9",x"1A",x"FE",x"08", -- 0x0E88 + x"20",x"F5",x"C3",x"2D",x"0A",x"0E",x"02",x"21", -- 0x0E90 + x"C4",x"41",x"11",x"F0",x"0F",x"1A",x"47",x"13", -- 0x0E98 + x"1A",x"13",x"36",x"00",x"23",x"77",x"23",x"10", -- 0x0EA0 + x"F9",x"0D",x"20",x"F1",x"21",x"11",x"0F",x"46", -- 0x0EA8 + x"23",x"C5",x"5E",x"23",x"56",x"23",x"46",x"23", -- 0x0EB0 + x"4E",x"23",x"D5",x"C5",x"06",x"00",x"ED",x"B0", -- 0x0EB8 + x"C1",x"D1",x"E5",x"21",x"20",x"00",x"19",x"EB", -- 0x0EC0 + x"E1",x"10",x"EF",x"C1",x"10",x"E3",x"3E",x"2C", -- 0x0EC8 + x"06",x"26",x"21",x"A0",x"0F",x"5E",x"23",x"56", -- 0x0ED0 + x"23",x"12",x"10",x"F9",x"C9",x"3A",x"B6",x"40", -- 0x0ED8 + x"A7",x"C0",x"3E",x"0A",x"32",x"B6",x"40",x"3A", -- 0x0EE0 + x"09",x"40",x"CB",x"27",x"21",x"A0",x"0F",x"5F", -- 0x0EE8 + x"16",x"00",x"19",x"5E",x"23",x"56",x"3E",x"2C", -- 0x0EF0 + x"12",x"CD",x"67",x"0B",x"E6",x"1F",x"32",x"09", -- 0x0EF8 + x"40",x"CB",x"27",x"21",x"A0",x"0F",x"5F",x"16", -- 0x0F00 + x"00",x"19",x"5E",x"23",x"56",x"3E",x"10",x"12", -- 0x0F08 + x"C9",x"03",x"42",x"50",x"0C",x"06",x"2D",x"2D", -- 0x0F10 + x"2D",x"92",x"AA",x"10",x"2D",x"2D",x"2D",x"93", -- 0x0F18 + x"A9",x"0B",x"2D",x"2D",x"2D",x"94",x"A8",x"AB", -- 0x0F20 + x"2D",x"2D",x"92",x"95",x"10",x"10",x"2D",x"2D", -- 0x0F28 + x"96",x"A7",x"10",x"10",x"2D",x"98",x"97",x"10", -- 0x0F30 + x"10",x"10",x"2D",x"99",x"A1",x"10",x"10",x"10", -- 0x0F38 + x"98",x"A0",x"A2",x"A6",x"10",x"10",x"9A",x"9F", -- 0x0F40 + x"10",x"A5",x"10",x"10",x"9B",x"9E",x"A3",x"A4", -- 0x0F48 + x"10",x"10",x"9C",x"10",x"10",x"10",x"10",x"10", -- 0x0F50 + x"9D",x"10",x"10",x"10",x"10",x"10",x"59",x"50", -- 0x0F58 + x"08",x"06",x"35",x"2E",x"3D",x"2D",x"2D",x"2D", -- 0x0F60 + x"34",x"2E",x"3C",x"81",x"85",x"88",x"33",x"39", -- 0x0F68 + x"3B",x"2E",x"84",x"87",x"32",x"2D",x"2D",x"80", -- 0x0F70 + x"83",x"2D",x"31",x"2D",x"2D",x"2D",x"2D",x"2D", -- 0x0F78 + x"30",x"38",x"2D",x"2D",x"2D",x"2D",x"2F",x"37", -- 0x0F80 + x"2D",x"3F",x"2D",x"2D",x"10",x"36",x"3A",x"3E", -- 0x0F88 + x"82",x"86",x"90",x"53",x"02",x"05",x"8A",x"8C", -- 0x0F90 + x"8E",x"90",x"10",x"89",x"8B",x"8D",x"8F",x"91", -- 0x0F98 + x"72",x"50",x"D1",x"50",x"EF",x"50",x"0E",x"51", -- 0x0FA0 + x"10",x"51",x"4E",x"51",x"94",x"51",x"F8",x"51", -- 0x0FA8 + x"19",x"52",x"83",x"53",x"5A",x"52",x"78",x"52", -- 0x0FB0 + x"9A",x"52",x"9E",x"52",x"B3",x"52",x"B9",x"52", -- 0x0FB8 + x"BB",x"52",x"DA",x"52",x"DD",x"52",x"FB",x"52", -- 0x0FC0 + x"43",x"53",x"18",x"53",x"1A",x"53",x"1C",x"53", -- 0x0FC8 + x"3D",x"53",x"3E",x"53",x"54",x"53",x"5C",x"53", -- 0x0FD0 + x"77",x"53",x"7D",x"53",x"9A",x"53",x"B8",x"53", -- 0x0FD8 + x"BB",x"53",x"BE",x"53",x"A2",x"53",x"44",x"53", -- 0x0FE0 + x"A7",x"53",x"28",x"53",x"00",x"50",x"00",x"50", -- 0x0FE8 + x"06",x"06",x"17",x"03",x"DD",x"21",x"AF",x"40", -- 0x0FF0 + x"3A",x"00",x"60",x"CB",x"67",x"C2",x"3A",x"10", -- 0x0FF8 + x"DD",x"CB",x"00",x"46",x"28",x"27",x"DD",x"7E", -- 0x1000 + x"01",x"FE",x"99",x"28",x"1C",x"DD",x"35",x"02", -- 0x1008 + x"20",x"17",x"DD",x"7E",x"01",x"C6",x"01",x"27", -- 0x1010 + x"DD",x"77",x"01",x"DD",x"7E",x"03",x"DD",x"77", -- 0x1018 + x"02",x"CD",x"9E",x"12",x"21",x"D9",x"40",x"CB", -- 0x1020 + x"D6",x"DD",x"CB",x"00",x"86",x"DD",x"7E",x"01", -- 0x1028 + x"A7",x"C8",x"DD",x"CB",x"00",x"5E",x"CA",x"18", -- 0x1030 + x"01",x"C9",x"DD",x"CB",x"00",x"C6",x"18",x"ED", -- 0x1038 + x"21",x"CB",x"41",x"36",x"02",x"23",x"23",x"06", -- 0x1040 + x"18",x"3E",x"04",x"77",x"23",x"23",x"10",x"FB", -- 0x1048 + x"21",x"C2",x"10",x"11",x"04",x"42",x"01",x"10", -- 0x1050 + x"00",x"ED",x"B0",x"3A",x"AF",x"40",x"CB",x"67", -- 0x1058 + x"28",x"0A",x"21",x"04",x"42",x"35",x"35",x"21", -- 0x1060 + x"08",x"42",x"35",x"35",x"11",x"E0",x"FF",x"21", -- 0x1068 + x"0E",x"11",x"FD",x"21",x"A5",x"53",x"06",x"08", -- 0x1070 + x"CD",x"73",x"04",x"21",x"BC",x"10",x"11",x"D2", -- 0x1078 + x"41",x"06",x"06",x"7E",x"12",x"13",x"13",x"12", -- 0x1080 + x"13",x"13",x"13",x"13",x"23",x"10",x"F4",x"21", -- 0x1088 + x"A9",x"53",x"DD",x"21",x"D2",x"10",x"06",x"1E", -- 0x1090 + x"E5",x"C5",x"DD",x"5E",x"00",x"DD",x"23",x"DD", -- 0x1098 + x"56",x"00",x"DD",x"23",x"06",x"06",x"73",x"23", -- 0x10A0 + x"72",x"23",x"23",x"10",x"F9",x"C1",x"E1",x"11", -- 0x10A8 + x"E0",x"FF",x"19",x"10",x"E3",x"21",x"99",x"99", -- 0x10B0 + x"22",x"27",x"40",x"C9",x"20",x"90",x"F7",x"63", -- 0x10B8 + x"AA",x"00",x"31",x"33",x"02",x"30",x"21",x"B3", -- 0x10C0 + x"02",x"30",x"10",x"97",x"02",x"30",x"40",x"17", -- 0x10C8 + x"02",x"30",x"10",x"0C",x"CA",x"CB",x"C8",x"C9", -- 0x10D0 + x"0C",x"10",x"10",x"0E",x"0C",x"0D",x"10",x"10", -- 0x10D8 + x"CA",x"CB",x"C8",x"C9",x"10",x"10",x"0D",x"0C", -- 0x10E0 + x"10",x"0E",x"0C",x"10",x"CA",x"CB",x"C8",x"C9", -- 0x10E8 + x"0E",x"10",x"CA",x"CB",x"C8",x"C9",x"0C",x"10", -- 0x10F0 + x"0E",x"0D",x"10",x"0C",x"CA",x"CB",x"C8",x"C9", -- 0x10F8 + x"CA",x"CB",x"C8",x"C9",x"0C",x"0E",x"0C",x"0D", -- 0x1100 + x"0E",x"10",x"0D",x"0C",x"0C",x"10",x"64",x"66", -- 0x1108 + x"18",x"1F",x"1D",x"15",x"67",x"65",x"03",x"00", -- 0x1110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1128 + x"00",x"00",x"00",x"03",x"01",x"0F",x"10",x"0A", -- 0x1130 + x"13",x"08",x"17",x"19",x"20",x"99",x"99",x"01", -- 0x1138 + x"00",x"3C",x"00",x"01",x"15",x"03",x"03",x"23", -- 0x1140 + x"02",x"0A",x"32",x"FF",x"10",x"00",x"00",x"00", -- 0x1148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x11A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x11A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x11B0 + x"00",x"00",x"00",x"00",x"00",x"AA",x"02",x"00", -- 0x11B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x11C0 + x"01",x"00",x"50",x"00",x"00",x"00",x"01",x"00", -- 0x11C8 + x"00",x"01",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x11D0 + x"00",x"03",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x11D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"03",x"01", -- 0x11E0 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"00", -- 0x11E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x11F0 + x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x11F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1200 + x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x1208 + x"00",x"00",x"00",x"00",x"00",x"00",x"21",x"23", -- 0x1210 + x"12",x"FD",x"21",x"A0",x"53",x"06",x"1C",x"CD", -- 0x1218 + x"3F",x"12",x"C9",x"53",x"43",x"4F",x"52",x"45", -- 0x1220 + x"5B",x"31",x"40",x"40",x"48",x"49",x"47",x"48", -- 0x1228 + x"40",x"53",x"43",x"4F",x"52",x"45",x"40",x"40", -- 0x1230 + x"53",x"43",x"4F",x"52",x"45",x"5B",x"32",x"11", -- 0x1238 + x"E0",x"FF",x"7E",x"23",x"D6",x"30",x"FD",x"77", -- 0x1240 + x"00",x"FD",x"19",x"10",x"F5",x"C9",x"21",x"A9", -- 0x1248 + x"40",x"FD",x"21",x"81",x"53",x"18",x"12",x"21", -- 0x1250 + x"AC",x"40",x"FD",x"21",x"01",x"51",x"18",x"09", -- 0x1258 + x"21",x"B3",x"40",x"FD",x"21",x"41",x"52",x"18", -- 0x1260 + x"00",x"06",x"03",x"11",x"E0",x"FF",x"0E",x"00", -- 0x1268 + x"7E",x"F5",x"1F",x"1F",x"1F",x"1F",x"CD",x"8A", -- 0x1270 + x"12",x"78",x"FE",x"01",x"CC",x"87",x"12",x"F1", -- 0x1278 + x"CD",x"8A",x"12",x"23",x"10",x"EA",x"C9",x"CB", -- 0x1280 + x"C1",x"C9",x"E6",x"0F",x"20",x"0C",x"CB",x"41", -- 0x1288 + x"20",x"08",x"3E",x"10",x"FD",x"77",x"00",x"FD", -- 0x1290 + x"19",x"C9",x"CB",x"C1",x"18",x"F6",x"FD",x"21", -- 0x1298 + x"7F",x"50",x"21",x"B0",x"40",x"06",x"01",x"C3", -- 0x12A0 + x"6B",x"12",x"21",x"16",x"11",x"11",x"00",x"40", -- 0x12A8 + x"01",x"A9",x"00",x"ED",x"B0",x"C9",x"DD",x"21", -- 0x12B0 + x"C0",x"41",x"DD",x"36",x"00",x"00",x"DD",x"36", -- 0x12B8 + x"01",x"03",x"CD",x"16",x"12",x"DD",x"36",x"02", -- 0x12C0 + x"00",x"DD",x"36",x"03",x"01",x"CD",x"4E",x"12", -- 0x12C8 + x"CD",x"57",x"12",x"CD",x"60",x"12",x"DD",x"36", -- 0x12D0 + x"3E",x"00",x"DD",x"36",x"3F",x"01",x"21",x"EE", -- 0x12D8 + x"12",x"FD",x"21",x"5F",x"51",x"06",x"06",x"CD", -- 0x12E0 + x"3F",x"12",x"CD",x"9E",x"12",x"C9",x"43",x"52", -- 0x12E8 + x"45",x"44",x"49",x"54",x"21",x"00",x"50",x"01", -- 0x12F0 + x"00",x"04",x"36",x"10",x"23",x"0B",x"79",x"B0", -- 0x12F8 + x"20",x"F8",x"21",x"C0",x"41",x"06",x"FF",x"36", -- 0x1300 + x"00",x"23",x"10",x"FB",x"21",x"00",x"42",x"06", -- 0x1308 + x"40",x"36",x"00",x"23",x"10",x"FB",x"C9",x"11", -- 0x1310 + x"03",x"00",x"21",x"02",x"50",x"0E",x"20",x"06", -- 0x1318 + x"1D",x"36",x"10",x"23",x"10",x"FB",x"19",x"0D", -- 0x1320 + x"20",x"F5",x"CD",x"0C",x"13",x"21",x"C4",x"41", -- 0x1328 + x"06",x"1D",x"AF",x"77",x"23",x"10",x"FC",x"C9", -- 0x1330 + x"32",x"B6",x"40",x"3A",x"B6",x"40",x"A7",x"C8", -- 0x1338 + x"18",x"F9",x"3E",x"FF",x"32",x"01",x"70",x"C9", -- 0x1340 + x"3A",x"AF",x"40",x"CB",x"57",x"20",x"23",x"CB", -- 0x1348 + x"6F",x"20",x"1B",x"3A",x"00",x"70",x"CB",x"5F", -- 0x1350 + x"28",x"14",x"3A",x"00",x"68",x"CB",x"3F",x"CB", -- 0x1358 + x"3F",x"47",x"CB",x"A8",x"3A",x"00",x"60",x"CB", -- 0x1360 + x"77",x"78",x"C8",x"CB",x"EF",x"C9",x"3A",x"00", -- 0x1368 + x"60",x"C9",x"21",x"B7",x"40",x"7E",x"23",x"35", -- 0x1370 + x"C0",x"23",x"5E",x"23",x"56",x"13",x"23",x"35", -- 0x1378 + x"20",x"05",x"11",x"96",x"13",x"36",x"14",x"1A", -- 0x1380 + x"47",x"13",x"1A",x"CB",x"EF",x"2B",x"72",x"2B", -- 0x1388 + x"73",x"2B",x"70",x"2B",x"77",x"C9",x"50",x"02", -- 0x1390 + x"5A",x"04",x"3C",x"09",x"46",x"00",x"28",x"02", -- 0x1398 + x"50",x"08",x"5A",x"00",x"5A",x"06",x"50",x"09", -- 0x13A0 + x"4B",x"0A",x"41",x"00",x"05",x"01",x"05",x"02", -- 0x13A8 + x"05",x"04",x"05",x"08",x"5A",x"01",x"50",x"02", -- 0x13B0 + x"46",x"05",x"63",x"01",x"63",x"05",x"3E",x"00", -- 0x13B8 + x"32",x"01",x"70",x"C9",x"11",x"00",x"42",x"21", -- 0x13C0 + x"FF",x"13",x"3A",x"1E",x"40",x"E6",x"03",x"20", -- 0x13C8 + x"03",x"21",x"03",x"14",x"01",x"04",x"00",x"ED", -- 0x13D0 + x"B0",x"21",x"1D",x"40",x"35",x"11",x"E0",x"FF", -- 0x13D8 + x"21",x"9F",x"53",x"06",x"06",x"3E",x"10",x"77", -- 0x13E0 + x"19",x"10",x"FC",x"3A",x"1D",x"40",x"32",x"BF", -- 0x13E8 + x"53",x"A7",x"28",x"0A",x"47",x"21",x"9F",x"53", -- 0x13F0 + x"3E",x"0F",x"77",x"19",x"10",x"FC",x"C9",x"80", -- 0x13F8 + x"10",x"01",x"80",x"E0",x"11",x"01",x"E0",x"E9", -- 0x1400 + x"3A",x"01",x"40",x"CB",x"47",x"C0",x"DD",x"21", -- 0x1408 + x"20",x"42",x"FD",x"21",x"06",x"40",x"06",x"04", -- 0x1410 + x"FD",x"7E",x"00",x"A7",x"28",x"45",x"DD",x"7E", -- 0x1418 + x"03",x"ED",x"44",x"D6",x"14",x"6F",x"DD",x"66", -- 0x1420 + x"01",x"0E",x"00",x"DD",x"E5",x"FD",x"E5",x"C5", -- 0x1428 + x"3A",x"1E",x"40",x"E6",x"03",x"CA",x"6C",x"15", -- 0x1430 + x"FD",x"21",x"04",x"42",x"DD",x"21",x"37",x"40", -- 0x1438 + x"06",x"07",x"DD",x"CB",x"00",x"4E",x"C4",x"70", -- 0x1440 + x"14",x"CD",x"78",x"09",x"10",x"F4",x"79",x"C1", -- 0x1448 + x"FD",x"E1",x"DD",x"E1",x"CB",x"47",x"28",x"0B", -- 0x1450 + x"AF",x"DD",x"77",x"01",x"DD",x"77",x"03",x"FD", -- 0x1458 + x"36",x"00",x"00",x"11",x"08",x"00",x"DD",x"19", -- 0x1460 + x"11",x"04",x"00",x"FD",x"19",x"10",x"A9",x"C9", -- 0x1468 + x"7C",x"FD",x"96",x"00",x"FE",x"10",x"D0",x"57", -- 0x1470 + x"7D",x"FD",x"96",x"03",x"ED",x"44",x"FE",x"10", -- 0x1478 + x"D0",x"5F",x"E5",x"21",x"AC",x"14",x"FD",x"7E", -- 0x1480 + x"01",x"D6",x"13",x"87",x"87",x"87",x"87",x"87", -- 0x1488 + x"CB",x"22",x"82",x"85",x"6F",x"3E",x"00",x"8C", -- 0x1490 + x"67",x"7B",x"BE",x"30",x"0D",x"23",x"BE",x"38", -- 0x1498 + x"09",x"0E",x"FF",x"CD",x"EB",x"18",x"DD",x"CB", -- 0x14A0 + x"00",x"C6",x"E1",x"C9",x"07",x"00",x"07",x"00", -- 0x14A8 + x"07",x"00",x"07",x"00",x"07",x"00",x"07",x"00", -- 0x14B0 + x"07",x"00",x"07",x"00",x"32",x"32",x"32",x"32", -- 0x14B8 + x"32",x"32",x"32",x"32",x"32",x"32",x"32",x"32", -- 0x14C0 + x"32",x"32",x"32",x"32",x"07",x"00",x"07",x"00", -- 0x14C8 + x"07",x"00",x"07",x"00",x"07",x"00",x"07",x"00", -- 0x14D0 + x"07",x"00",x"07",x"00",x"32",x"32",x"32",x"32", -- 0x14D8 + x"32",x"32",x"32",x"32",x"32",x"32",x"32",x"32", -- 0x14E0 + x"32",x"32",x"32",x"32",x"08",x"07",x"09",x"06", -- 0x14E8 + x"0A",x"05",x"0B",x"04",x"0C",x"03",x"0D",x"02", -- 0x14F0 + x"0E",x"01",x"0F",x"00",x"0F",x"00",x"0E",x"01", -- 0x14F8 + x"0D",x"02",x"0C",x"03",x"0B",x"04",x"0A",x"05", -- 0x1500 + x"09",x"06",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x1508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1520 + x"00",x"00",x"00",x"00",x"0F",x"00",x"0F",x"00", -- 0x1528 + x"0F",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x1530 + x"0F",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x1538 + x"0F",x"01",x"0F",x"02",x"0F",x"03",x"0F",x"04", -- 0x1540 + x"0F",x"05",x"0F",x"06",x"0C",x"03",x"0C",x"03", -- 0x1548 + x"0C",x"03",x"0C",x"03",x"0D",x"02",x"0E",x"01", -- 0x1550 + x"0F",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x1558 + x"0E",x"01",x"0D",x"02",x"0C",x"03",x"0C",x"03", -- 0x1560 + x"0C",x"03",x"0C",x"03",x"EB",x"7A",x"2F",x"57", -- 0x1568 + x"1D",x"1D",x"1D",x"CD",x"64",x"16",x"7E",x"FE", -- 0x1570 + x"10",x"28",x"44",x"E5",x"FD",x"E1",x"C5",x"D5", -- 0x1578 + x"21",x"B9",x"16",x"11",x"11",x"00",x"06",x"07", -- 0x1580 + x"BE",x"28",x"07",x"19",x"10",x"FA",x"D1",x"C1", -- 0x1588 + x"18",x"2D",x"23",x"D1",x"C1",x"78",x"CB",x"27", -- 0x1590 + x"85",x"6F",x"3E",x"00",x"8C",x"67",x"79",x"BE", -- 0x1598 + x"28",x"03",x"D2",x"BF",x"15",x"23",x"BE",x"DA", -- 0x15A0 + x"BF",x"15",x"D5",x"FD",x"7E",x"00",x"FE",x"0C", -- 0x15A8 + x"28",x"12",x"FE",x"0E",x"28",x"18",x"FE",x"0D", -- 0x15B0 + x"28",x"2A",x"E6",x"F8",x"20",x"3C",x"D1",x"0E", -- 0x15B8 + x"00",x"C3",x"4E",x"14",x"FD",x"36",x"00",x"10", -- 0x15C0 + x"11",x"00",x"01",x"C3",x"27",x"16",x"FD",x"36", -- 0x15C8 + x"00",x"10",x"11",x"50",x"00",x"FD",x"7E",x"E0", -- 0x15D0 + x"FE",x"0D",x"C2",x"27",x"16",x"FD",x"36",x"E0", -- 0x15D8 + x"10",x"C3",x"27",x"16",x"FD",x"36",x"00",x"10", -- 0x15E0 + x"11",x"50",x"00",x"FD",x"7E",x"20",x"FE",x"0E", -- 0x15E8 + x"C2",x"27",x"16",x"FD",x"36",x"20",x"10",x"C3", -- 0x15F0 + x"27",x"16",x"FD",x"7E",x"00",x"21",x"9B",x"16", -- 0x15F8 + x"06",x"04",x"BE",x"28",x"06",x"23",x"23",x"23", -- 0x1600 + x"10",x"F8",x"C7",x"23",x"5E",x"23",x"56",x"FD", -- 0x1608 + x"19",x"FD",x"36",x"00",x"10",x"FD",x"36",x"01", -- 0x1610 + x"10",x"FD",x"36",x"20",x"10",x"FD",x"36",x"21", -- 0x1618 + x"10",x"11",x"30",x"00",x"C3",x"27",x"16",x"CD", -- 0x1620 + x"72",x"19",x"DD",x"21",x"77",x"40",x"FD",x"21", -- 0x1628 + x"14",x"42",x"06",x"03",x"DD",x"CB",x"00",x"46", -- 0x1630 + x"28",x"0B",x"CD",x"78",x"09",x"10",x"F5",x"0E", -- 0x1638 + x"01",x"D1",x"C3",x"4E",x"14",x"DD",x"36",x"00", -- 0x1640 + x"01",x"FD",x"36",x"01",x"1C",x"FD",x"36",x"02", -- 0x1648 + x"06",x"D1",x"7A",x"2F",x"D6",x"08",x"FD",x"77", -- 0x1650 + x"00",x"3E",x"08",x"83",x"FD",x"77",x"03",x"0E", -- 0x1658 + x"01",x"C3",x"4E",x"14",x"7B",x"E6",x"07",x"4F", -- 0x1660 + x"3E",x"07",x"91",x"4F",x"7B",x"E6",x"F8",x"C6", -- 0x1668 + x"10",x"CB",x"3F",x"CB",x"3F",x"F5",x"21",x"C0", -- 0x1670 + x"41",x"85",x"6F",x"3E",x"00",x"8C",x"67",x"7A", -- 0x1678 + x"86",x"47",x"E6",x"F8",x"6F",x"78",x"E6",x"07", -- 0x1680 + x"47",x"26",x"00",x"29",x"29",x"F1",x"CB",x"3F", -- 0x1688 + x"85",x"6F",x"3E",x"00",x"85",x"6F",x"3E",x"50", -- 0x1690 + x"8C",x"67",x"C9",x"C8",x"00",x"00",x"C9",x"FF", -- 0x1698 + x"FF",x"CA",x"E0",x"FF",x"CB",x"DF",x"FF",x"B9", -- 0x16A0 + x"A9",x"17",x"A1",x"91",x"14",x"89",x"79",x"11", -- 0x16A8 + x"71",x"61",x"0E",x"59",x"49",x"0B",x"41",x"31", -- 0x16B0 + x"08",x"0D",x"04",x"00",x"06",x"00",x"06",x"00", -- 0x16B8 + x"06",x"00",x"06",x"00",x"06",x"00",x"06",x"00", -- 0x16C0 + x"07",x"00",x"0E",x"07",x"00",x"07",x"00",x"07", -- 0x16C8 + x"00",x"07",x"00",x"07",x"00",x"07",x"00",x"05", -- 0x16D0 + x"00",x"05",x"00",x"C8",x"00",x"00",x"00",x"03", -- 0x16D8 + x"00",x"03",x"00",x"04",x"00",x"04",x"00",x"02", -- 0x16E0 + x"00",x"04",x"00",x"05",x"C9",x"07",x"05",x"07", -- 0x16E8 + x"02",x"07",x"00",x"07",x"00",x"07",x"00",x"07", -- 0x16F0 + x"00",x"07",x"00",x"07",x"01",x"CA",x"05",x"00", -- 0x16F8 + x"06",x"00",x"06",x"00",x"05",x"00",x"04",x"00", -- 0x1700 + x"04",x"00",x"03",x"00",x"01",x"00",x"CB",x"07", -- 0x1708 + x"01",x"07",x"02",x"07",x"02",x"07",x"02",x"07", -- 0x1710 + x"02",x"07",x"03",x"07",x"06",x"07",x"06",x"0C", -- 0x1718 + x"32",x"32",x"07",x"01",x"07",x"01",x"07",x"01", -- 0x1720 + x"07",x"01",x"07",x"01",x"07",x"01",x"07",x"01", -- 0x1728 + x"3A",x"01",x"40",x"CB",x"47",x"C0",x"FD",x"21", -- 0x1730 + x"00",x"42",x"21",x"1B",x"18",x"11",x"15",x"00", -- 0x1738 + x"FD",x"7E",x"01",x"BE",x"28",x"03",x"19",x"18", -- 0x1740 + x"FA",x"06",x"0A",x"23",x"FD",x"7E",x"00",x"86", -- 0x1748 + x"ED",x"44",x"57",x"FD",x"7E",x"03",x"23",x"96", -- 0x1750 + x"23",x"5F",x"E5",x"C5",x"CD",x"64",x"16",x"7E", -- 0x1758 + x"FE",x"10",x"CA",x"14",x"18",x"E5",x"DD",x"E1", -- 0x1760 + x"C5",x"D5",x"21",x"B9",x"16",x"11",x"11",x"00", -- 0x1768 + x"06",x"07",x"BE",x"28",x"08",x"19",x"10",x"FA", -- 0x1770 + x"D1",x"C1",x"C3",x"14",x"18",x"23",x"D1",x"C1", -- 0x1778 + x"78",x"CB",x"27",x"85",x"6F",x"3E",x"00",x"8C", -- 0x1780 + x"67",x"79",x"BE",x"D2",x"14",x"18",x"23",x"BE", -- 0x1788 + x"DA",x"14",x"18",x"DD",x"7E",x"00",x"FE",x"0C", -- 0x1790 + x"28",x"0F",x"FE",x"0E",x"28",x"15",x"FE",x"0D", -- 0x1798 + x"28",x"27",x"E6",x"F8",x"20",x"39",x"C3",x"14", -- 0x17A0 + x"18",x"DD",x"36",x"00",x"10",x"11",x"00",x"01", -- 0x17A8 + x"C3",x"09",x"18",x"DD",x"36",x"00",x"10",x"11", -- 0x17B0 + x"50",x"00",x"DD",x"7E",x"E0",x"FE",x"0D",x"C2", -- 0x17B8 + x"09",x"18",x"DD",x"36",x"E0",x"10",x"C3",x"09", -- 0x17C0 + x"18",x"DD",x"36",x"00",x"10",x"11",x"50",x"00", -- 0x17C8 + x"DD",x"7E",x"20",x"FE",x"0E",x"C2",x"09",x"18", -- 0x17D0 + x"DD",x"36",x"20",x"10",x"C3",x"09",x"18",x"DD", -- 0x17D8 + x"7E",x"00",x"21",x"9B",x"16",x"06",x"04",x"BE", -- 0x17E0 + x"28",x"06",x"23",x"23",x"23",x"10",x"F8",x"C7", -- 0x17E8 + x"23",x"5E",x"23",x"56",x"DD",x"19",x"DD",x"36", -- 0x17F0 + x"00",x"10",x"DD",x"36",x"01",x"10",x"DD",x"36", -- 0x17F8 + x"20",x"10",x"DD",x"36",x"21",x"10",x"11",x"30", -- 0x1800 + x"00",x"CD",x"72",x"19",x"21",x"01",x"40",x"CB", -- 0x1808 + x"C6",x"C1",x"E1",x"C9",x"C1",x"E1",x"05",x"C2", -- 0x1810 + x"4C",x"17",x"C9",x"10",x"00",x"01",x"00",x"05", -- 0x1818 + x"02",x"01",x"03",x"09",x"06",x"03",x"06",x"0C", -- 0x1820 + x"0A",x"09",x"0B",x"02",x"0D",x"02",x"0D",x"06", -- 0x1828 + x"50",x"09",x"03",x"06",x"06",x"0C",x"06",x"03", -- 0x1830 + x"0A",x"0F",x"0A",x"09",x"0C",x"03",x"0E",x"05", -- 0x1838 + x"0E",x"0D",x"0E",x"0F",x"0E",x"11",x"00",x"03", -- 0x1840 + x"00",x"05",x"00",x"0B",x"00",x"0D",x"02",x"08", -- 0x1848 + x"05",x"03",x"05",x"0D",x"0C",x"05",x"0C",x"0B", -- 0x1850 + x"0F",x"08",x"D2",x"0F",x"04",x"0D",x"06",x"0C", -- 0x1858 + x"02",x"09",x"06",x"08",x"09",x"06",x"0B",x"03", -- 0x1860 + x"09",x"00",x"04",x"00",x"00",x"06",x"00",x"91", -- 0x1868 + x"0F",x"03",x"0F",x"05",x"0F",x"0B",x"0F",x"0D", -- 0x1870 + x"0D",x"08",x"0A",x"03",x"0A",x"0D",x"03",x"05", -- 0x1878 + x"03",x"0B",x"00",x"08",x"12",x"00",x"0B",x"02", -- 0x1880 + x"09",x"03",x"0D",x"06",x"09",x"07",x"06",x"09", -- 0x1888 + x"04",x"0C",x"06",x"0F",x"0B",x"0F",x"0F",x"09", -- 0x1890 + x"0F",x"92",x"0F",x"0B",x"0D",x"09",x"0C",x"0D", -- 0x1898 + x"09",x"09",x"08",x"06",x"06",x"04",x"03",x"06", -- 0x18A0 + x"00",x"0B",x"00",x"0F",x"06",x"0F",x"52",x"00", -- 0x18A8 + x"04",x"02",x"06",x"03",x"02",x"06",x"06",x"07", -- 0x18B0 + x"09",x"09",x"0B",x"0C",x"09",x"0F",x"04",x"00", -- 0x18B8 + x"00",x"09",x"00",x"CD",x"48",x"1B",x"CD",x"E7", -- 0x18C0 + x"1D",x"3A",x"1E",x"40",x"E6",x"03",x"28",x"09", -- 0x18C8 + x"CD",x"D6",x"1C",x"CD",x"DD",x"0E",x"C3",x"B4", -- 0x18D0 + x"00",x"CD",x"81",x"1A",x"CD",x"FF",x"19",x"CD", -- 0x18D8 + x"AE",x"1A",x"CD",x"E7",x"1A",x"CD",x"CA",x"1D", -- 0x18E0 + x"C3",x"B4",x"00",x"DD",x"CB",x"00",x"46",x"C0", -- 0x18E8 + x"3A",x"AF",x"40",x"CB",x"57",x"C0",x"FD",x"E5", -- 0x18F0 + x"C5",x"47",x"FD",x"7E",x"01",x"D6",x"13",x"CB", -- 0x18F8 + x"27",x"5F",x"16",x"00",x"21",x"39",x"19",x"19", -- 0x1900 + x"5E",x"23",x"56",x"EB",x"CD",x"07",x"14",x"21", -- 0x1908 + x"AB",x"40",x"CB",x"68",x"F5",x"20",x"03",x"21", -- 0x1910 + x"AE",x"40",x"7B",x"86",x"27",x"77",x"2B",x"7A", -- 0x1918 + x"8E",x"27",x"77",x"2B",x"3E",x"00",x"8E",x"27", -- 0x1920 + x"77",x"21",x"4E",x"12",x"F1",x"20",x"03",x"21", -- 0x1928 + x"57",x"12",x"CD",x"07",x"14",x"C1",x"FD",x"E1", -- 0x1930 + x"C9",x"45",x"19",x"4E",x"19",x"57",x"19",x"00", -- 0x1938 + x"00",x"00",x"00",x"69",x"19",x"11",x"00",x"02", -- 0x1940 + x"21",x"EE",x"40",x"CB",x"DE",x"C9",x"11",x"53", -- 0x1948 + x"00",x"21",x"EE",x"40",x"CB",x"DE",x"C9",x"21", -- 0x1950 + x"EE",x"40",x"CB",x"D6",x"FD",x"7E",x"02",x"11", -- 0x1958 + x"00",x"01",x"FE",x"06",x"C8",x"11",x"50",x"01", -- 0x1960 + x"C9",x"11",x"00",x"01",x"21",x"EE",x"40",x"CB", -- 0x1968 + x"D6",x"C9",x"3A",x"AF",x"40",x"CB",x"57",x"C0", -- 0x1970 + x"47",x"FD",x"E5",x"C5",x"C3",x"0F",x"19",x"3A", -- 0x1978 + x"01",x"40",x"CB",x"47",x"C0",x"FD",x"21",x"24", -- 0x1980 + x"42",x"06",x"04",x"DD",x"21",x"00",x"42",x"C5", -- 0x1988 + x"FD",x"7E",x"01",x"DD",x"96",x"00",x"FE",x"10", -- 0x1990 + x"30",x"5C",x"4F",x"FD",x"7E",x"03",x"2F",x"D6", -- 0x1998 + x"50",x"47",x"DD",x"7E",x"03",x"90",x"FA",x"AE", -- 0x19A0 + x"19",x"FE",x"10",x"30",x"49",x"AF",x"47",x"FD", -- 0x19A8 + x"7E",x"03",x"2F",x"D6",x"70",x"DD",x"96",x"03", -- 0x19B0 + x"F2",x"F6",x"19",x"FE",x"10",x"38",x"02",x"3E", -- 0x19B8 + x"10",x"F5",x"21",x"D9",x"0C",x"3A",x"01",x"42", -- 0x19C0 + x"BE",x"28",x"05",x"23",x"23",x"23",x"18",x"F8", -- 0x19C8 + x"23",x"5E",x"23",x"56",x"EB",x"79",x"CB",x"27", -- 0x19D0 + x"85",x"6F",x"3E",x"00",x"8C",x"67",x"F1",x"5F", -- 0x19D8 + x"78",x"C6",x"20",x"BE",x"D2",x"F6",x"19",x"23", -- 0x19E0 + x"7B",x"C6",x"20",x"BE",x"DA",x"F6",x"19",x"21", -- 0x19E8 + x"01",x"40",x"CB",x"C6",x"C1",x"C9",x"11",x"08", -- 0x19F0 + x"00",x"FD",x"19",x"C1",x"10",x"91",x"C9",x"DD", -- 0x19F8 + x"21",x"24",x"42",x"FD",x"21",x"2C",x"42",x"01", -- 0x1A00 + x"09",x"02",x"3A",x"29",x"40",x"5F",x"DD",x"7E", -- 0x1A08 + x"01",x"A7",x"F5",x"C4",x"35",x"1A",x"F1",x"CC", -- 0x1A10 + x"57",x"1A",x"FD",x"7E",x"01",x"A7",x"F5",x"C4", -- 0x1A18 + x"46",x"1A",x"F1",x"CC",x"6C",x"1A",x"05",x"C8", -- 0x1A20 + x"D5",x"11",x"10",x"00",x"DD",x"19",x"FD",x"19", -- 0x1A28 + x"D1",x"0E",x"35",x"18",x"D9",x"DD",x"7E",x"03", -- 0x1A30 + x"93",x"DD",x"77",x"03",x"D0",x"DD",x"36",x"01", -- 0x1A38 + x"00",x"DD",x"36",x"03",x"00",x"C9",x"FD",x"7E", -- 0x1A40 + x"03",x"93",x"FD",x"77",x"03",x"D0",x"FD",x"36", -- 0x1A48 + x"01",x"00",x"FD",x"36",x"03",x"00",x"C9",x"FD", -- 0x1A50 + x"7E",x"03",x"FE",x"2C",x"D0",x"DD",x"36",x"03", -- 0x1A58 + x"5E",x"21",x"0C",x"42",x"7E",x"81",x"3C",x"3C", -- 0x1A60 + x"DD",x"77",x"01",x"C9",x"DD",x"7E",x"03",x"FE", -- 0x1A68 + x"2C",x"D0",x"FD",x"36",x"03",x"5E",x"21",x"0C", -- 0x1A70 + x"42",x"7E",x"81",x"3D",x"3D",x"FD",x"77",x"01", -- 0x1A78 + x"C9",x"11",x"D2",x"41",x"FD",x"21",x"20",x"40", -- 0x1A80 + x"21",x"D2",x"40",x"06",x"06",x"0E",x"01",x"35", -- 0x1A88 + x"28",x"10",x"13",x"13",x"13",x"13",x"13",x"13", -- 0x1A90 + x"79",x"ED",x"44",x"4F",x"23",x"FD",x"23",x"10", -- 0x1A98 + x"EE",x"C9",x"FD",x"7E",x"00",x"77",x"1A",x"81", -- 0x1AA0 + x"12",x"13",x"13",x"12",x"18",x"E6",x"21",x"D8", -- 0x1AA8 + x"40",x"35",x"C0",x"3A",x"26",x"40",x"77",x"FD", -- 0x1AB0 + x"21",x"04",x"42",x"11",x"04",x"00",x"06",x"04", -- 0x1AB8 + x"21",x"D1",x"40",x"4E",x"FD",x"7E",x"00",x"81", -- 0x1AC0 + x"FD",x"77",x"00",x"FE",x"10",x"DC",x"E0",x"1A", -- 0x1AC8 + x"FE",x"E0",x"D4",x"E0",x"1A",x"FD",x"19",x"10", -- 0x1AD0 + x"EB",x"21",x"CA",x"41",x"7E",x"81",x"77",x"C9", -- 0x1AD8 + x"F5",x"7E",x"ED",x"44",x"77",x"F1",x"C9",x"3A", -- 0x1AE0 + x"01",x"40",x"CB",x"47",x"C0",x"3A",x"B6",x"40", -- 0x1AE8 + x"A7",x"F0",x"3A",x"2B",x"40",x"32",x"B6",x"40", -- 0x1AF0 + x"3A",x"65",x"53",x"FE",x"18",x"28",x"11",x"21", -- 0x1AF8 + x"0C",x"1B",x"FD",x"21",x"65",x"53",x"06",x"04", -- 0x1B00 + x"CD",x"3F",x"12",x"C9",x"48",x"4F",x"4D",x"45", -- 0x1B08 + x"FD",x"21",x"05",x"53",x"21",x"28",x"40",x"7E", -- 0x1B10 + x"D6",x"99",x"27",x"77",x"F5",x"AF",x"ED",x"67", -- 0x1B18 + x"FD",x"77",x"00",x"ED",x"67",x"FD",x"77",x"20", -- 0x1B20 + x"ED",x"67",x"2B",x"F1",x"7E",x"DE",x"00",x"27", -- 0x1B28 + x"77",x"AF",x"ED",x"67",x"FD",x"77",x"40",x"ED", -- 0x1B30 + x"67",x"FD",x"77",x"60",x"ED",x"67",x"7E",x"23", -- 0x1B38 + x"B6",x"C0",x"21",x"01",x"40",x"CB",x"C6",x"C9", -- 0x1B40 + x"DD",x"21",x"00",x"40",x"FD",x"21",x"00",x"42", -- 0x1B48 + x"DD",x"CB",x"01",x"46",x"C2",x"FD",x"1B",x"CD", -- 0x1B50 + x"48",x"13",x"E6",x"0F",x"DD",x"BE",x"02",x"C4", -- 0x1B58 + x"90",x"1B",x"FD",x"7E",x"03",x"DD",x"86",x"03", -- 0x1B60 + x"21",x"CE",x"1C",x"F5",x"3A",x"1E",x"40",x"E6", -- 0x1B68 + x"03",x"20",x"03",x"21",x"D2",x"1C",x"F1",x"BE", -- 0x1B70 + x"D0",x"23",x"BE",x"D8",x"23",x"47",x"FD",x"7E", -- 0x1B78 + x"00",x"DD",x"86",x"04",x"BE",x"D0",x"23",x"BE", -- 0x1B80 + x"D8",x"FD",x"77",x"00",x"FD",x"70",x"03",x"C9", -- 0x1B88 + x"DD",x"4E",x"02",x"DD",x"77",x"02",x"21",x"D9", -- 0x1B90 + x"1B",x"11",x"E2",x"1B",x"06",x"09",x"BE",x"28", -- 0x1B98 + x"07",x"23",x"13",x"13",x"13",x"10",x"F7",x"C9", -- 0x1BA0 + x"1A",x"A7",x"28",x"03",x"FD",x"77",x"01",x"13", -- 0x1BA8 + x"1A",x"DD",x"77",x"03",x"13",x"1A",x"DD",x"77", -- 0x1BB0 + x"04",x"3A",x"1E",x"40",x"E6",x"03",x"C0",x"CB", -- 0x1BB8 + x"79",x"20",x"0D",x"DD",x"CB",x"03",x"26",x"DD", -- 0x1BC0 + x"CB",x"04",x"26",x"DD",x"CB",x"02",x"FE",x"C9", -- 0x1BC8 + x"DD",x"CB",x"03",x"2E",x"DD",x"CB",x"04",x"2E", -- 0x1BD0 + x"C9",x"00",x"01",x"02",x"04",x"08",x"05",x"09", -- 0x1BD8 + x"06",x"0A",x"00",x"00",x"00",x"50",x"02",x"00", -- 0x1BE0 + x"10",x"FE",x"00",x"11",x"00",x"02",x"91",x"00", -- 0x1BE8 + x"FE",x"52",x"02",x"02",x"D2",x"02",x"FE",x"12", -- 0x1BF0 + x"FE",x"02",x"92",x"FE",x"FE",x"DD",x"CB",x"01", -- 0x1BF8 + x"56",x"C0",x"DD",x"CB",x"01",x"4E",x"CA",x"6C", -- 0x1C00 + x"1C",x"DD",x"35",x"00",x"C0",x"DD",x"36",x"00", -- 0x1C08 + x"08",x"FD",x"7E",x"02",x"FE",x"06",x"28",x"28", -- 0x1C10 + x"3E",x"04",x"FD",x"86",x"01",x"FE",x"40",x"28", -- 0x1C18 + x"33",x"FD",x"77",x"01",x"FD",x"35",x"02",x"FD", -- 0x1C20 + x"21",x"14",x"42",x"06",x"03",x"11",x"04",x"00", -- 0x1C28 + x"FD",x"7E",x"01",x"C6",x"04",x"FD",x"77",x"01", -- 0x1C30 + x"FD",x"35",x"02",x"FD",x"19",x"10",x"F1",x"C9", -- 0x1C38 + x"FD",x"34",x"02",x"FD",x"21",x"14",x"42",x"11", -- 0x1C40 + x"04",x"00",x"06",x"03",x"FD",x"34",x"02",x"FD", -- 0x1C48 + x"19",x"10",x"F9",x"C9",x"AF",x"06",x"04",x"FD", -- 0x1C50 + x"77",x"00",x"FD",x"23",x"10",x"F9",x"21",x"14", -- 0x1C58 + x"42",x"06",x"0C",x"77",x"23",x"10",x"FC",x"DD", -- 0x1C60 + x"CB",x"01",x"D6",x"C9",x"FD",x"56",x"00",x"FD", -- 0x1C68 + x"5E",x"03",x"7A",x"C6",x"08",x"FD",x"77",x"00", -- 0x1C70 + x"7B",x"D6",x"08",x"FD",x"77",x"03",x"FD",x"36", -- 0x1C78 + x"01",x"34",x"FD",x"36",x"02",x"06",x"DD",x"CB", -- 0x1C80 + x"01",x"CE",x"DD",x"36",x"00",x"08",x"21",x"D9", -- 0x1C88 + x"40",x"CB",x"C6",x"DD",x"21",x"77",x"40",x"FD", -- 0x1C90 + x"21",x"14",x"42",x"21",x"C5",x"1C",x"06",x"03", -- 0x1C98 + x"7A",x"86",x"FD",x"77",x"00",x"23",x"7E",x"FD", -- 0x1CA0 + x"77",x"01",x"23",x"FD",x"36",x"02",x"06",x"7B", -- 0x1CA8 + x"86",x"FD",x"77",x"03",x"23",x"DD",x"CB",x"00", -- 0x1CB0 + x"8E",x"DD",x"CB",x"00",x"96",x"D5",x"CD",x"78", -- 0x1CB8 + x"09",x"D1",x"10",x"DC",x"C9",x"08",x"35",x"08", -- 0x1CC0 + x"F8",x"36",x"F8",x"F8",x"37",x"08",x"D8",x"20", -- 0x1CC8 + x"D8",x"20",x"E8",x"34",x"E0",x"18",x"DD",x"21", -- 0x1CD0 + x"37",x"40",x"FD",x"21",x"04",x"42",x"DD",x"7E", -- 0x1CD8 + x"FF",x"A7",x"28",x"03",x"DD",x"35",x"FF",x"06", -- 0x1CE0 + x"07",x"DD",x"CB",x"00",x"4E",x"C5",x"C4",x"F8", -- 0x1CE8 + x"1C",x"C1",x"CD",x"78",x"09",x"10",x"F2",x"C9", -- 0x1CF0 + x"DD",x"CB",x"00",x"46",x"C2",x"1A",x"1D",x"DD", -- 0x1CF8 + x"6E",x"01",x"DD",x"66",x"02",x"CD",x"07",x"14", -- 0x1D00 + x"78",x"FD",x"86",x"00",x"FD",x"77",x"00",x"79", -- 0x1D08 + x"FD",x"86",x"03",x"FD",x"77",x"03",x"DD",x"35", -- 0x1D10 + x"0E",x"C9",x"DD",x"CB",x"00",x"5E",x"28",x"22", -- 0x1D18 + x"DD",x"35",x"05",x"C0",x"FD",x"7E",x"01",x"3C", -- 0x1D20 + x"FE",x"20",x"28",x"08",x"FD",x"77",x"01",x"DD", -- 0x1D28 + x"36",x"05",x"04",x"C9",x"AF",x"DD",x"77",x"00", -- 0x1D30 + x"FD",x"77",x"00",x"FD",x"77",x"03",x"FD",x"77", -- 0x1D38 + x"01",x"C9",x"3A",x"A7",x"40",x"32",x"36",x"40", -- 0x1D40 + x"FD",x"36",x"01",x"1C",x"FD",x"36",x"02",x"07", -- 0x1D48 + x"DD",x"36",x"05",x"04",x"DD",x"CB",x"00",x"DE", -- 0x1D50 + x"C9",x"DD",x"7E",x"0D",x"A7",x"20",x"0A",x"3A", -- 0x1D58 + x"F4",x"40",x"DD",x"77",x"0D",x"01",x"00",x"00", -- 0x1D60 + x"C9",x"DD",x"35",x"0D",x"DD",x"6E",x"03",x"DD", -- 0x1D68 + x"66",x"04",x"DD",x"35",x"05",x"20",x"0F",x"DD", -- 0x1D70 + x"35",x"06",x"23",x"7E",x"DD",x"77",x"05",x"23", -- 0x1D78 + x"DD",x"75",x"03",x"DD",x"74",x"04",x"7E",x"CB", -- 0x1D80 + x"2F",x"CB",x"2F",x"CB",x"2F",x"CB",x"2F",x"47", -- 0x1D88 + x"7E",x"E6",x"0F",x"CB",x"5F",x"28",x"02",x"F6", -- 0x1D90 + x"F0",x"4F",x"C9",x"DD",x"46",x"03",x"DD",x"4E", -- 0x1D98 + x"04",x"C9",x"CD",x"59",x"1D",x"DD",x"CB",x"0F", -- 0x1DA0 + x"46",x"28",x"04",x"78",x"ED",x"44",x"47",x"DD", -- 0x1DA8 + x"CB",x"0F",x"4E",x"28",x"04",x"79",x"ED",x"44", -- 0x1DB0 + x"4F",x"DD",x"CB",x"0F",x"56",x"28",x"02",x"CB", -- 0x1DB8 + x"20",x"DD",x"CB",x"0F",x"5E",x"28",x"02",x"CB", -- 0x1DC0 + x"21",x"C9",x"3A",x"01",x"40",x"CB",x"47",x"C0", -- 0x1DC8 + x"FD",x"21",x"14",x"42",x"DD",x"21",x"77",x"40", -- 0x1DD0 + x"06",x"03",x"DD",x"CB",x"00",x"46",x"C4",x"1A", -- 0x1DD8 + x"1D",x"CD",x"78",x"09",x"10",x"F4",x"C9",x"DD", -- 0x1DE0 + x"21",x"06",x"40",x"FD",x"21",x"20",x"42",x"06", -- 0x1DE8 + x"04",x"DD",x"7E",x"00",x"A7",x"CC",x"49",x"1E", -- 0x1DF0 + x"C4",x"0B",x"1E",x"11",x"04",x"00",x"DD",x"19", -- 0x1DF8 + x"11",x"08",x"00",x"FD",x"19",x"10",x"EA",x"CD", -- 0x1E00 + x"E9",x"1E",x"C9",x"C5",x"D5",x"DD",x"35",x"00", -- 0x1E08 + x"20",x"0F",x"FD",x"36",x"01",x"00",x"FD",x"36", -- 0x1E10 + x"03",x"00",x"DD",x"36",x"00",x"00",x"D1",x"C1", -- 0x1E18 + x"C9",x"FD",x"7E",x"03",x"FE",x"E0",x"30",x"EA", -- 0x1E20 + x"FE",x"08",x"38",x"E6",x"FD",x"7E",x"01",x"FE", -- 0x1E28 + x"F8",x"30",x"DF",x"FE",x"16",x"38",x"DB",x"DD", -- 0x1E30 + x"86",x"02",x"FD",x"77",x"01",x"FD",x"7E",x"03", -- 0x1E38 + x"DD",x"86",x"01",x"FD",x"77",x"03",x"D1",x"C1", -- 0x1E40 + x"C9",x"C5",x"D5",x"3A",x"01",x"40",x"CB",x"47", -- 0x1E48 + x"C2",x"46",x"1E",x"CD",x"48",x"13",x"CB",x"6F", -- 0x1E50 + x"CA",x"46",x"1E",x"21",x"06",x"40",x"06",x"04", -- 0x1E58 + x"11",x"04",x"00",x"0E",x"1C",x"3A",x"1E",x"40", -- 0x1E60 + x"E6",x"03",x"20",x"02",x"0E",x"01",x"79",x"BE", -- 0x1E68 + x"38",x"D4",x"19",x"10",x"FA",x"21",x"BF",x"1E", -- 0x1E70 + x"11",x"C7",x"1E",x"06",x"08",x"3A",x"01",x"42", -- 0x1E78 + x"BE",x"28",x"07",x"23",x"13",x"13",x"13",x"13", -- 0x1E80 + x"10",x"F6",x"EB",x"3A",x"00",x"42",x"86",x"FD", -- 0x1E88 + x"77",x"01",x"23",x"3A",x"03",x"42",x"47",x"3E", -- 0x1E90 + x"F0",x"90",x"86",x"FD",x"77",x"03",x"23",x"7E", -- 0x1E98 + x"DD",x"77",x"02",x"23",x"7E",x"DD",x"77",x"01", -- 0x1EA0 + x"21",x"E7",x"1E",x"3A",x"1E",x"40",x"E6",x"03", -- 0x1EA8 + x"20",x"01",x"23",x"7E",x"DD",x"77",x"00",x"21", -- 0x1EB0 + x"D9",x"40",x"CB",x"CE",x"D1",x"C1",x"C9",x"50", -- 0x1EB8 + x"10",x"11",x"91",x"52",x"D2",x"12",x"92",x"09", -- 0x1EC0 + x"FD",x"00",x"FC",x"09",x"08",x"00",x"04",x"10", -- 0x1EC8 + x"02",x"04",x"00",x"00",x"02",x"FC",x"00",x"0F", -- 0x1ED0 + x"FA",x"04",x"FC",x"00",x"FA",x"FC",x"FC",x"0F", -- 0x1ED8 + x"09",x"04",x"04",x"00",x"09",x"FC",x"04",x"20", -- 0x1EE0 + x"0B",x"FD",x"21",x"20",x"42",x"06",x"04",x"11", -- 0x1EE8 + x"08",x"00",x"FD",x"7E",x"01",x"FD",x"E5",x"C5", -- 0x1EF0 + x"05",x"28",x"0A",x"FD",x"19",x"FD",x"BE",x"01", -- 0x1EF8 + x"CC",x"0D",x"1F",x"18",x"F3",x"C1",x"FD",x"E1", -- 0x1F00 + x"FD",x"19",x"10",x"E6",x"C9",x"FD",x"34",x"01", -- 0x1F08 + x"C9",x"3A",x"17",x"40",x"A7",x"C8",x"3E",x"13", -- 0x1F10 + x"21",x"1F",x"1F",x"CD",x"5C",x"09",x"C9",x"DD", -- 0x1F18 + x"CB",x"08",x"66",x"C4",x"41",x"1F",x"FD",x"7E", -- 0x1F20 + x"03",x"FE",x"10",x"DA",x"4F",x"0B",x"FE",x"F0", -- 0x1F28 + x"D2",x"4F",x"0B",x"FD",x"7E",x"00",x"FE",x"10", -- 0x1F30 + x"DA",x"4F",x"0B",x"FE",x"F0",x"D8",x"C3",x"4F", -- 0x1F38 + x"0B",x"DD",x"7E",x"0E",x"A7",x"F0",x"DD",x"36", -- 0x1F40 + x"0E",x"02",x"CD",x"E7",x"08",x"CB",x"28",x"CB", -- 0x1F48 + x"29",x"DD",x"70",x"03",x"DD",x"71",x"04",x"C9", -- 0x1F50 + x"CD",x"5F",x"1F",x"CD",x"2D",x"20",x"C9",x"DD", -- 0x1F58 + x"7E",x"FA",x"A7",x"C8",x"DD",x"7E",x"E2",x"DD", -- 0x1F60 + x"BE",x"F9",x"D0",x"21",x"72",x"1F",x"CD",x"3F", -- 0x1F68 + x"09",x"C9",x"FD",x"36",x"01",x"15",x"FD",x"36", -- 0x1F70 + x"02",x"06",x"CD",x"67",x"0B",x"FE",x"10",x"30", -- 0x1F78 + x"02",x"CB",x"E7",x"FE",x"F0",x"38",x"02",x"D6", -- 0x1F80 + x"10",x"57",x"26",x"10",x"CD",x"67",x"0B",x"CB", -- 0x1F88 + x"57",x"20",x"02",x"26",x"F0",x"CB",x"4F",x"20", -- 0x1F90 + x"01",x"EB",x"FD",x"72",x"00",x"FD",x"74",x"03", -- 0x1F98 + x"DD",x"E5",x"D1",x"13",x"21",x"75",x"20",x"01", -- 0x1FA0 + x"08",x"00",x"ED",x"B0",x"CD",x"E7",x"08",x"78", -- 0x1FA8 + x"A7",x"20",x"02",x"06",x"01",x"79",x"A7",x"20", -- 0x1FB0 + x"02",x"0E",x"01",x"DD",x"70",x"03",x"DD",x"71", -- 0x1FB8 + x"04",x"21",x"31",x"40",x"35",x"DD",x"CB",x"00", -- 0x1FC0 + x"CE",x"DD",x"CB",x"00",x"D6",x"21",x"DC",x"1F", -- 0x1FC8 + x"FD",x"E5",x"DD",x"E5",x"CD",x"3F",x"09",x"DD", -- 0x1FD0 + x"E1",x"FD",x"E1",x"C9",x"E1",x"DD",x"E5",x"D1", -- 0x1FD8 + x"FD",x"E5",x"E1",x"DD",x"E1",x"FD",x"E1",x"CD", -- 0x1FE0 + x"F8",x"1F",x"DD",x"7E",x"03",x"77",x"23",x"DD", -- 0x1FE8 + x"7E",x"04",x"77",x"DD",x"CB",x"08",x"DE",x"C9", -- 0x1FF0 + x"D5",x"E5",x"DD",x"72",x"0C",x"DD",x"73",x"0B", -- 0x1FF8 + x"DD",x"74",x"0A",x"DD",x"75",x"09",x"21",x"81", -- 0x2000 + x"29",x"13",x"01",x"08",x"00",x"ED",x"B0",x"E1", -- 0x2008 + x"D1",x"FD",x"7E",x"00",x"C6",x"02",x"77",x"23", -- 0x2010 + x"36",x"13",x"23",x"36",x"01",x"23",x"FD",x"7E", -- 0x2018 + x"03",x"C6",x"08",x"77",x"EB",x"CB",x"CE",x"CB", -- 0x2020 + x"D6",x"23",x"23",x"23",x"C9",x"DD",x"21",x"37", -- 0x2028 + x"40",x"DD",x"7E",x"E2",x"A7",x"C8",x"3E",x"15", -- 0x2030 + x"21",x"3F",x"20",x"CD",x"5C",x"09",x"C9",x"DD", -- 0x2038 + x"CB",x"08",x"5E",x"C8",x"DD",x"66",x"0C",x"DD", -- 0x2040 + x"6E",x"0B",x"CB",x"46",x"C8",x"21",x"5C",x"20", -- 0x2048 + x"FD",x"E5",x"DD",x"E5",x"CD",x"3F",x"09",x"DD", -- 0x2050 + x"E1",x"FD",x"E1",x"C9",x"E1",x"DD",x"E5",x"D1", -- 0x2058 + x"FD",x"E5",x"E1",x"DD",x"E1",x"FD",x"E1",x"CD", -- 0x2060 + x"F8",x"1F",x"CD",x"E7",x"08",x"70",x"23",x"71", -- 0x2068 + x"DD",x"CB",x"08",x"DE",x"C9",x"9B",x"1D",x"00", -- 0x2070 + x"00",x"00",x"00",x"00",x"00",x"DD",x"21",x"37", -- 0x2078 + x"40",x"DD",x"7E",x"E2",x"A7",x"C8",x"3E",x"15", -- 0x2080 + x"21",x"E4",x"20",x"CD",x"5C",x"09",x"DD",x"21", -- 0x2088 + x"37",x"40",x"DD",x"7E",x"E0",x"A7",x"C8",x"DD", -- 0x2090 + x"21",x"37",x"40",x"FD",x"21",x"04",x"42",x"06", -- 0x2098 + x"07",x"DD",x"CB",x"00",x"46",x"DD",x"E5",x"FD", -- 0x20A0 + x"E5",x"C5",x"C4",x"B8",x"20",x"C1",x"FD",x"E1", -- 0x20A8 + x"DD",x"E1",x"CD",x"78",x"09",x"10",x"EA",x"C9", -- 0x20B0 + x"DD",x"CB",x"08",x"5E",x"C8",x"DD",x"66",x"0C", -- 0x20B8 + x"DD",x"6E",x"0B",x"CB",x"46",x"C0",x"CB",x"4E", -- 0x20C0 + x"C8",x"DD",x"56",x"0A",x"DD",x"5E",x"09",x"13", -- 0x20C8 + x"1A",x"FE",x"13",x"C0",x"E5",x"D5",x"FD",x"E1", -- 0x20D0 + x"DD",x"E1",x"CD",x"E7",x"08",x"DD",x"70",x"03", -- 0x20D8 + x"DD",x"71",x"04",x"C9",x"FD",x"7E",x"00",x"FE", -- 0x20E0 + x"10",x"DA",x"4F",x"0B",x"FE",x"F0",x"D2",x"4F", -- 0x20E8 + x"0B",x"FD",x"7E",x"03",x"FE",x"10",x"DA",x"4F", -- 0x20F0 + x"0B",x"FE",x"F0",x"D2",x"4F",x"0B",x"DD",x"CB", -- 0x20F8 + x"00",x"46",x"C0",x"DD",x"7E",x"0E",x"E6",x"18", -- 0x2100 + x"20",x"05",x"FD",x"36",x"02",x"07",x"C9",x"FD", -- 0x2108 + x"36",x"02",x"06",x"C9",x"DD",x"21",x"C0",x"41", -- 0x2110 + x"DD",x"36",x"1B",x"06",x"DD",x"36",x"1A",x"04", -- 0x2118 + x"DD",x"36",x"1F",x"06",x"DD",x"36",x"1E",x"00", -- 0x2120 + x"DD",x"36",x"31",x"02",x"DD",x"36",x"30",x"00", -- 0x2128 + x"DD",x"36",x"35",x"02",x"DD",x"36",x"34",x"04", -- 0x2130 + x"21",x"20",x"22",x"FD",x"21",x"4D",x"53",x"06", -- 0x2138 + x"15",x"CD",x"3F",x"12",x"21",x"35",x"22",x"FD", -- 0x2140 + x"21",x"38",x"52",x"06",x"04",x"CD",x"3F",x"12", -- 0x2148 + x"11",x"00",x"03",x"3A",x"B0",x"40",x"A7",x"20", -- 0x2150 + x"29",x"D5",x"21",x"39",x"22",x"3A",x"B1",x"40", -- 0x2158 + x"DD",x"36",x"1E",x"04",x"3D",x"28",x"07",x"DD", -- 0x2160 + x"36",x"1E",x"00",x"21",x"47",x"22",x"FD",x"21", -- 0x2168 + x"CF",x"52",x"06",x"0E",x"CD",x"3F",x"12",x"D1", -- 0x2170 + x"CD",x"F5",x"21",x"C2",x"53",x"21",x"CD",x"17", -- 0x2178 + x"13",x"C9",x"D5",x"DD",x"36",x"1E",x"04",x"21", -- 0x2180 + x"55",x"22",x"FD",x"21",x"0F",x"53",x"06",x"11", -- 0x2188 + x"CD",x"3F",x"12",x"D1",x"AF",x"3D",x"08",x"CD", -- 0x2190 + x"48",x"13",x"CB",x"6F",x"08",x"20",x"03",x"08", -- 0x2198 + x"20",x"0A",x"CD",x"F5",x"21",x"C2",x"97",x"21", -- 0x21A0 + x"CD",x"17",x"13",x"C9",x"3A",x"B0",x"40",x"D6", -- 0x21A8 + x"01",x"27",x"32",x"B0",x"40",x"CD",x"9E",x"12", -- 0x21B0 + x"3A",x"00",x"68",x"06",x"03",x"CB",x"7F",x"28", -- 0x21B8 + x"02",x"06",x"05",x"78",x"32",x"1D",x"40",x"CD", -- 0x21C0 + x"17",x"13",x"3A",x"AF",x"40",x"CB",x"6F",x"28", -- 0x21C8 + x"12",x"21",x"A9",x"40",x"AF",x"77",x"23",x"77", -- 0x21D0 + x"23",x"77",x"CD",x"4E",x"12",x"21",x"BE",x"40", -- 0x21D8 + x"CB",x"C6",x"C9",x"21",x"AC",x"40",x"AF",x"77", -- 0x21E0 + x"23",x"77",x"23",x"77",x"CD",x"57",x"12",x"21", -- 0x21E8 + x"BE",x"40",x"CB",x"CE",x"C9",x"3E",x"05",x"CD", -- 0x21F0 + x"38",x"13",x"FD",x"21",x"3A",x"52",x"7B",x"D6", -- 0x21F8 + x"01",x"27",x"5F",x"7A",x"DE",x"00",x"27",x"57", -- 0x2200 + x"FD",x"77",x"00",x"7B",x"E6",x"0F",x"FD",x"77", -- 0x2208 + x"C0",x"7B",x"CB",x"3F",x"CB",x"3F",x"CB",x"3F", -- 0x2210 + x"CB",x"3F",x"FD",x"77",x"E0",x"7B",x"B2",x"C9", -- 0x2218 + x"54",x"4F",x"40",x"43",x"4F",x"4E",x"54",x"49", -- 0x2220 + x"4E",x"55",x"45",x"40",x"59",x"4F",x"55",x"52", -- 0x2228 + x"40",x"47",x"41",x"4D",x"45",x"54",x"49",x"4D", -- 0x2230 + x"45",x"49",x"4E",x"53",x"45",x"52",x"54",x"40", -- 0x2238 + x"41",x"40",x"43",x"4F",x"49",x"4E",x"40",x"49", -- 0x2240 + x"4E",x"53",x"45",x"52",x"54",x"40",x"32",x"40", -- 0x2248 + x"43",x"4F",x"49",x"4E",x"53",x"50",x"52",x"45", -- 0x2250 + x"53",x"53",x"40",x"46",x"49",x"52",x"45",x"40", -- 0x2258 + x"42",x"55",x"54",x"54",x"4F",x"4E",x"3A",x"EE", -- 0x2260 + x"40",x"A7",x"C2",x"72",x"23",x"21",x"D9",x"40", -- 0x2268 + x"46",x"CB",x"18",x"DC",x"EC",x"22",x"CB",x"18", -- 0x2270 + x"DC",x"FA",x"22",x"CB",x"18",x"DC",x"08",x"23", -- 0x2278 + x"CB",x"18",x"DC",x"21",x"23",x"CB",x"18",x"DC", -- 0x2280 + x"3A",x"23",x"CB",x"18",x"DC",x"53",x"23",x"3E", -- 0x2288 + x"FF",x"32",x"E2",x"40",x"3A",x"EF",x"40",x"CB", -- 0x2290 + x"67",x"C4",x"8F",x"24",x"E6",x"EF",x"C2",x"4F", -- 0x2298 + x"24",x"3A",x"EF",x"40",x"CB",x"7F",x"C4",x"E2", -- 0x22A0 + x"24",x"21",x"DA",x"40",x"46",x"CB",x"18",x"DC", -- 0x22A8 + x"98",x"23",x"CB",x"18",x"DC",x"A6",x"23",x"CB", -- 0x22B0 + x"18",x"DC",x"B1",x"23",x"CB",x"18",x"DC",x"C9", -- 0x22B8 + x"23",x"CB",x"18",x"DC",x"21",x"24",x"CB",x"18", -- 0x22C0 + x"DC",x"37",x"24",x"3A",x"E2",x"40",x"32",x"00", -- 0x22C8 + x"78",x"3A",x"E3",x"40",x"21",x"06",x"68",x"77", -- 0x22D0 + x"0F",x"77",x"3A",x"AF",x"40",x"CB",x"57",x"C0", -- 0x22D8 + x"21",x"03",x"68",x"3A",x"DA",x"40",x"77",x"0F", -- 0x22E0 + x"23",x"23",x"77",x"C9",x"21",x"D9",x"40",x"CB", -- 0x22E8 + x"86",x"23",x"CB",x"C6",x"3E",x"30",x"32",x"DB", -- 0x22F0 + x"40",x"C9",x"21",x"D9",x"40",x"CB",x"8E",x"23", -- 0x22F8 + x"CB",x"CE",x"3E",x"04",x"32",x"DC",x"40",x"C9", -- 0x2300 + x"21",x"D9",x"40",x"CB",x"96",x"23",x"CB",x"D6", -- 0x2308 + x"21",x"1C",x"23",x"11",x"DD",x"40",x"01",x"06", -- 0x2310 + x"00",x"ED",x"B0",x"C9",x"B9",x"23",x"08",x"01", -- 0x2318 + x"02",x"21",x"D9",x"40",x"CB",x"9E",x"23",x"CB", -- 0x2320 + x"DE",x"21",x"35",x"23",x"11",x"E4",x"40",x"01", -- 0x2328 + x"06",x"00",x"ED",x"B0",x"C9",x"D1",x"23",x"28", -- 0x2330 + x"01",x"02",x"21",x"D9",x"40",x"CB",x"A6",x"23", -- 0x2338 + x"CB",x"E6",x"21",x"4E",x"23",x"11",x"E9",x"40", -- 0x2340 + x"01",x"06",x"00",x"ED",x"B0",x"C9",x"29",x"24", -- 0x2348 + x"07",x"01",x"01",x"3A",x"AF",x"40",x"CB",x"57", -- 0x2350 + x"C0",x"21",x"D9",x"40",x"CB",x"AE",x"23",x"CB", -- 0x2358 + x"EE",x"21",x"6D",x"23",x"11",x"E4",x"40",x"01", -- 0x2360 + x"06",x"00",x"ED",x"B0",x"C9",x"3F",x"24",x"08", -- 0x2368 + x"01",x"03",x"21",x"EE",x"40",x"CB",x"56",x"20", -- 0x2370 + x"12",x"CB",x"5E",x"CA",x"6D",x"22",x"CB",x"9E", -- 0x2378 + x"23",x"CB",x"DE",x"21",x"F3",x"40",x"36",x"E0", -- 0x2380 + x"C3",x"6D",x"22",x"CB",x"96",x"23",x"CB",x"D6", -- 0x2388 + x"21",x"F2",x"40",x"36",x"00",x"C3",x"6D",x"22", -- 0x2390 + x"21",x"DB",x"40",x"35",x"C0",x"21",x"DA",x"40", -- 0x2398 + x"CB",x"86",x"2B",x"CB",x"EE",x"C9",x"21",x"DC", -- 0x23A0 + x"40",x"35",x"C0",x"21",x"DA",x"40",x"CB",x"8E", -- 0x23A8 + x"C9",x"FD",x"21",x"DD",x"40",x"0E",x"04",x"CD", -- 0x23B0 + x"AD",x"24",x"C9",x"4B",x"06",x"FF",x"03",x"4B", -- 0x23B8 + x"06",x"FF",x"03",x"4B",x"06",x"FF",x"03",x"1C", -- 0x23C0 + x"0C",x"FD",x"21",x"E4",x"40",x"0E",x"08",x"CD", -- 0x23C8 + x"AD",x"24",x"C9",x"68",x"05",x"FF",x"02",x"68", -- 0x23D0 + x"05",x"FF",x"02",x"68",x"05",x"FF",x"02",x"68", -- 0x23D8 + x"13",x"FF",x"02",x"68",x"05",x"FF",x"02",x"68", -- 0x23E0 + x"05",x"FF",x"02",x"68",x"05",x"FF",x"02",x"68", -- 0x23E8 + x"08",x"FF",x"02",x"4B",x"08",x"FF",x"02",x"1C", -- 0x23F0 + x"08",x"FF",x"02",x"4B",x"08",x"FF",x"02",x"68", -- 0x23F8 + x"08",x"FF",x"02",x"4B",x"08",x"FF",x"02",x"1C", -- 0x2400 + x"08",x"FF",x"02",x"4B",x"08",x"FF",x"02",x"68", -- 0x2408 + x"13",x"FF",x"02",x"68",x"05",x"FF",x"02",x"68", -- 0x2410 + x"05",x"FF",x"02",x"68",x"05",x"FF",x"02",x"68", -- 0x2418 + x"13",x"FD",x"21",x"E9",x"40",x"0E",x"10",x"CD", -- 0x2420 + x"AD",x"24",x"C9",x"9A",x"05",x"FF",x"04",x"9A", -- 0x2428 + x"05",x"FF",x"04",x"8E",x"03",x"9A",x"0C",x"FD", -- 0x2430 + x"21",x"E4",x"40",x"0E",x"20",x"CD",x"AD",x"24", -- 0x2438 + x"C9",x"80",x"10",x"FF",x"06",x"70",x"08",x"68", -- 0x2440 + x"10",x"FF",x"06",x"55",x"08",x"40",x"18",x"3A", -- 0x2448 + x"EF",x"40",x"CB",x"5F",x"20",x"1F",x"CB",x"57", -- 0x2450 + x"CA",x"A1",x"22",x"21",x"F2",x"40",x"3E",x"10", -- 0x2458 + x"86",x"77",x"32",x"E2",x"40",x"3E",x"03",x"32", -- 0x2460 + x"E3",x"40",x"D2",x"A1",x"22",x"21",x"EF",x"40", -- 0x2468 + x"CB",x"96",x"C3",x"A1",x"22",x"21",x"F3",x"40", -- 0x2470 + x"7E",x"D6",x"10",x"77",x"32",x"E2",x"40",x"3E", -- 0x2478 + x"03",x"32",x"E3",x"40",x"D2",x"A1",x"22",x"21", -- 0x2480 + x"EF",x"40",x"CB",x"9E",x"C3",x"A1",x"22",x"F5", -- 0x2488 + x"21",x"F0",x"40",x"7E",x"32",x"E2",x"40",x"3E", -- 0x2490 + x"03",x"32",x"E3",x"40",x"F1",x"23",x"35",x"C0", -- 0x2498 + x"36",x"0A",x"2B",x"CB",x"56",x"28",x"03",x"36", -- 0x24A0 + x"B8",x"C9",x"36",x"B4",x"C9",x"FD",x"35",x"03", -- 0x24A8 + x"20",x"1F",x"FD",x"35",x"02",x"20",x"07",x"21", -- 0x24B0 + x"DA",x"40",x"7E",x"A9",x"77",x"C9",x"FD",x"6E", -- 0x24B8 + x"00",x"FD",x"66",x"01",x"23",x"23",x"FD",x"75", -- 0x24C0 + x"00",x"FD",x"74",x"01",x"23",x"7E",x"FD",x"77", -- 0x24C8 + x"03",x"FD",x"6E",x"00",x"FD",x"66",x"01",x"7E", -- 0x24D0 + x"32",x"E2",x"40",x"FD",x"7E",x"04",x"32",x"E3", -- 0x24D8 + x"40",x"C9",x"3A",x"28",x"40",x"E6",x"0F",x"C6", -- 0x24E0 + x"80",x"32",x"E2",x"40",x"3E",x"03",x"32",x"E3", -- 0x24E8 + x"40",x"C9",x"3A",x"17",x"40",x"A7",x"20",x"08", -- 0x24F0 + x"21",x"EF",x"40",x"CB",x"A6",x"C3",x"21",x"25", -- 0x24F8 + x"3A",x"01",x"40",x"CB",x"47",x"20",x"F1",x"21", -- 0x2500 + x"EF",x"40",x"CB",x"66",x"20",x"13",x"3A",x"1E", -- 0x2508 + x"40",x"E6",x"03",x"FE",x"02",x"20",x"0A",x"CB", -- 0x2510 + x"E6",x"21",x"F0",x"40",x"36",x"B8",x"23",x"36", -- 0x2518 + x"0A",x"3A",x"AF",x"40",x"CB",x"57",x"C0",x"3A", -- 0x2520 + x"16",x"40",x"A7",x"20",x"0A",x"AF",x"21",x"00", -- 0x2528 + x"68",x"77",x"23",x"77",x"23",x"77",x"C9",x"CB", -- 0x2530 + x"27",x"3C",x"ED",x"44",x"06",x"04",x"21",x"04", -- 0x2538 + x"60",x"77",x"23",x"0F",x"10",x"FB",x"3E",x"01", -- 0x2540 + x"C3",x"2E",x"25",x"3A",x"AF",x"40",x"CB",x"57", -- 0x2548 + x"C0",x"3E",x"01",x"06",x"04",x"21",x"00",x"68", -- 0x2550 + x"77",x"23",x"10",x"FC",x"3A",x"27",x"40",x"E6", -- 0x2558 + x"F0",x"0F",x"0F",x"0F",x"0F",x"47",x"3E",x"0F", -- 0x2560 + x"90",x"06",x"04",x"21",x"04",x"60",x"77",x"0F", -- 0x2568 + x"23",x"10",x"FB",x"C9",x"DD",x"7E",x"DF",x"A7", -- 0x2570 + x"28",x"05",x"DD",x"7E",x"FF",x"A7",x"C0",x"CD", -- 0x2578 + x"67",x"0B",x"E6",x"3F",x"DD",x"77",x"FF",x"DD", -- 0x2580 + x"7E",x"F7",x"A7",x"C8",x"DD",x"7E",x"E1",x"DD", -- 0x2588 + x"BE",x"F8",x"D0",x"21",x"9A",x"25",x"CD",x"3F", -- 0x2590 + x"09",x"C9",x"FD",x"36",x"00",x"10",x"FD",x"36", -- 0x2598 + x"01",x"14",x"06",x"03",x"3A",x"2E",x"40",x"FE", -- 0x25A0 + x"03",x"30",x"02",x"06",x"05",x"FD",x"70",x"02", -- 0x25A8 + x"CD",x"67",x"0B",x"FD",x"77",x"03",x"DD",x"E5", -- 0x25B0 + x"D1",x"13",x"21",x"EE",x"25",x"01",x"08",x"00", -- 0x25B8 + x"ED",x"B0",x"CD",x"67",x"0B",x"6F",x"26",x"00", -- 0x25C0 + x"3A",x"1F",x"40",x"4F",x"06",x"08",x"29",x"7C", -- 0x25C8 + x"91",x"38",x"02",x"67",x"2C",x"10",x"F7",x"7C", -- 0x25D0 + x"DD",x"77",x"07",x"3A",x"F4",x"40",x"DD",x"77", -- 0x25D8 + x"0E",x"21",x"2E",x"40",x"35",x"DD",x"CB",x"00", -- 0x25E0 + x"CE",x"DD",x"CB",x"00",x"D6",x"C9",x"59",x"1D", -- 0x25E8 + x"79",x"0B",x"01",x"2C",x"00",x"01",x"DD",x"21", -- 0x25F0 + x"37",x"40",x"DD",x"7E",x"E1",x"A7",x"C8",x"3E", -- 0x25F8 + x"14",x"21",x"08",x"26",x"CD",x"5C",x"09",x"C9", -- 0x2600 + x"DD",x"CB",x"08",x"46",x"28",x"3E",x"DD",x"CB", -- 0x2608 + x"00",x"7E",x"20",x"1A",x"DD",x"7E",x"06",x"A7", -- 0x2610 + x"C0",x"DD",x"36",x"06",x"43",x"11",x"79",x"0B", -- 0x2618 + x"DD",x"73",x"03",x"DD",x"72",x"04",x"DD",x"36", -- 0x2620 + x"05",x"01",x"DD",x"35",x"07",x"C0",x"DD",x"CB", -- 0x2628 + x"08",x"26",x"AF",x"32",x"01",x"70",x"DD",x"36", -- 0x2630 + x"01",x"9B",x"DD",x"36",x"02",x"1D",x"3C",x"32", -- 0x2638 + x"01",x"70",x"CD",x"E7",x"08",x"DD",x"70",x"03", -- 0x2640 + x"DD",x"71",x"04",x"C9",x"FD",x"7E",x"00",x"FE", -- 0x2648 + x"10",x"38",x"0E",x"FE",x"F0",x"30",x"0A",x"FD", -- 0x2650 + x"7E",x"03",x"FE",x"02",x"38",x"03",x"FE",x"F0", -- 0x2658 + x"D8",x"DD",x"CB",x"00",x"46",x"C0",x"DD",x"CB", -- 0x2660 + x"00",x"8E",x"DD",x"CB",x"00",x"96",x"AF",x"FD", -- 0x2668 + x"77",x"00",x"FD",x"77",x"01",x"FD",x"77",x"03", -- 0x2670 + x"CD",x"67",x"0B",x"32",x"36",x"40",x"C9",x"3A", -- 0x2678 + x"1E",x"40",x"E6",x"1F",x"CB",x"2F",x"CB",x"2F", -- 0x2680 + x"A7",x"28",x"01",x"3D",x"6F",x"26",x"00",x"29", -- 0x2688 + x"29",x"29",x"E5",x"29",x"D1",x"19",x"11",x"A3", -- 0x2690 + x"26",x"19",x"11",x"1F",x"40",x"01",x"18",x"00", -- 0x2698 + x"ED",x"B0",x"C9",x"0E",x"10",x"0A",x"09",x"07", -- 0x26A0 + x"15",x"07",x"1C",x"99",x"99",x"02",x"00",x"3B", -- 0x26A8 + x"00",x"02",x"1E",x"04",x"04",x"32",x"02",x"0E", -- 0x26B0 + x"28",x"00",x"10",x"0D",x"0A",x"09",x"06",x"07", -- 0x26B8 + x"13",x"08",x"18",x"99",x"99",x"02",x"00",x"3A", -- 0x26C0 + x"00",x"02",x"23",x"05",x"05",x"3C",x"02",x"10", -- 0x26C8 + x"1E",x"00",x"10",x"0C",x"09",x"08",x"05",x"06", -- 0x26D0 + x"0C",x"07",x"16",x"99",x"99",x"02",x"00",x"39", -- 0x26D8 + x"00",x"03",x"23",x"05",x"05",x"46",x"02",x"12", -- 0x26E0 + x"14",x"00",x"10",x"0B",x"09",x"08",x"05",x"06", -- 0x26E8 + x"0C",x"04",x"14",x"99",x"99",x"02",x"00",x"38", -- 0x26F0 + x"00",x"03",x"28",x"06",x"05",x"50",x"03",x"14", -- 0x26F8 + x"0A",x"00",x"10",x"0A",x"0A",x"04",x"07",x"07", -- 0x2700 + x"06",x"04",x"13",x"99",x"99",x"02",x"00",x"37", -- 0x2708 + x"00",x"03",x"32",x"07",x"06",x"5A",x"03",x"16", -- 0x2710 + x"08",x"00",x"10",x"09",x"08",x"05",x"07",x"04", -- 0x2718 + x"06",x"03",x"12",x"99",x"99",x"02",x"00",x"36", -- 0x2720 + x"00",x"03",x"32",x"07",x"07",x"64",x"04",x"19", -- 0x2728 + x"06",x"00",x"10",x"07",x"08",x"05",x"07",x"04", -- 0x2730 + x"06",x"03",x"11",x"99",x"99",x"03",x"00",x"1A", -- 0x2738 + x"00",x"03",x"32",x"07",x"07",x"78",x"04",x"19", -- 0x2740 + x"04",x"00",x"10",x"DD",x"21",x"37",x"40",x"DD", -- 0x2748 + x"E5",x"CD",x"EC",x"27",x"DD",x"E1",x"DD",x"7E", -- 0x2750 + x"FB",x"DD",x"BE",x"E5",x"C8",x"DD",x"7E",x"FC", -- 0x2758 + x"A7",x"C8",x"DD",x"7E",x"DF",x"A7",x"28",x"05", -- 0x2760 + x"DD",x"7E",x"FF",x"A7",x"C0",x"DD",x"7E",x"FD", -- 0x2768 + x"DD",x"77",x"FF",x"21",x"7A",x"27",x"CD",x"3F", -- 0x2770 + x"09",x"C9",x"DD",x"E5",x"D1",x"13",x"21",x"DD", -- 0x2778 + x"27",x"01",x"0F",x"00",x"ED",x"B0",x"CD",x"67", -- 0x2780 + x"0B",x"DD",x"77",x"0F",x"06",x"10",x"16",x"02", -- 0x2788 + x"CB",x"7F",x"28",x"04",x"06",x"F0",x"16",x"FE", -- 0x2790 + x"0E",x"10",x"1E",x"02",x"CB",x"77",x"28",x"04", -- 0x2798 + x"0E",x"F0",x"1E",x"FE",x"FD",x"70",x"00",x"FD", -- 0x27A0 + x"71",x"03",x"DD",x"72",x"03",x"DD",x"73",x"04", -- 0x27A8 + x"CD",x"67",x"0B",x"E6",x"3F",x"F6",x"07",x"DD", -- 0x27B0 + x"77",x"0E",x"FD",x"36",x"01",x"18",x"06",x"00", -- 0x27B8 + x"3A",x"33",x"40",x"FE",x"03",x"30",x"02",x"06", -- 0x27C0 + x"01",x"FD",x"70",x"02",x"DD",x"CB",x"00",x"CE", -- 0x27C8 + x"DD",x"CB",x"00",x"D6",x"21",x"33",x"40",x"35", -- 0x27D0 + x"DD",x"CB",x"08",x"DE",x"C9",x"9B",x"1D",x"00", -- 0x27D8 + x"00",x"01",x"11",x"00",x"01",x"00",x"00",x"00", -- 0x27E0 + x"00",x"00",x"04",x"00",x"3E",x"18",x"21",x"3D", -- 0x27E8 + x"28",x"CD",x"5C",x"09",x"DD",x"21",x"37",x"40", -- 0x27F0 + x"DD",x"7E",x"FF",x"A7",x"C0",x"DD",x"7E",x"E0", -- 0x27F8 + x"DD",x"BE",x"F6",x"D0",x"CD",x"67",x"0B",x"6F", -- 0x2800 + x"26",x"00",x"3A",x"1C",x"40",x"4F",x"06",x"08", -- 0x2808 + x"29",x"7C",x"91",x"38",x"02",x"67",x"2C",x"10", -- 0x2810 + x"F7",x"4C",x"0C",x"DD",x"21",x"37",x"40",x"FD", -- 0x2818 + x"21",x"04",x"42",x"06",x"07",x"FD",x"7E",x"01", -- 0x2820 + x"FE",x"18",x"20",x"03",x"0D",x"28",x"06",x"CD", -- 0x2828 + x"78",x"09",x"10",x"F1",x"C9",x"DD",x"CB",x"08", -- 0x2830 + x"66",x"C0",x"C3",x"4B",x"28",x"DD",x"CB",x"00", -- 0x2838 + x"46",x"C8",x"DD",x"CB",x"08",x"66",x"C0",x"DD", -- 0x2840 + x"CB",x"08",x"E6",x"FD",x"E5",x"21",x"56",x"28", -- 0x2848 + x"CD",x"3F",x"09",x"FD",x"E1",x"C9",x"D1",x"D1", -- 0x2850 + x"1A",x"47",x"3A",x"00",x"42",x"B8",x"38",x"04", -- 0x2858 + x"78",x"C6",x"E0",x"47",x"78",x"C6",x"10",x"FD", -- 0x2860 + x"77",x"00",x"FD",x"36",x"01",x"13",x"FD",x"36", -- 0x2868 + x"02",x"06",x"13",x"13",x"13",x"1A",x"FD",x"77", -- 0x2870 + x"03",x"DD",x"E5",x"D1",x"13",x"21",x"81",x"29", -- 0x2878 + x"01",x"08",x"00",x"ED",x"B0",x"DD",x"36",x"0E", -- 0x2880 + x"0A",x"DD",x"CB",x"08",x"E6",x"DD",x"CB",x"00", -- 0x2888 + x"CE",x"DD",x"CB",x"00",x"D6",x"C9",x"DD",x"21", -- 0x2890 + x"37",x"40",x"DD",x"7E",x"FB",x"A7",x"C8",x"3E", -- 0x2898 + x"18",x"21",x"A8",x"28",x"CD",x"5C",x"09",x"C9", -- 0x28A0 + x"DD",x"CB",x"08",x"5E",x"C2",x"E4",x"28",x"DD", -- 0x28A8 + x"CB",x"00",x"7E",x"C2",x"5F",x"29",x"CD",x"2F", -- 0x28B0 + x"29",x"FD",x"7E",x"00",x"FE",x"20",x"47",x"30", -- 0x28B8 + x"04",x"FD",x"36",x"00",x"20",x"78",x"FE",x"E0", -- 0x28C0 + x"38",x"04",x"FD",x"36",x"00",x"DF",x"FD",x"7E", -- 0x28C8 + x"03",x"FE",x"20",x"47",x"30",x"04",x"FD",x"36", -- 0x28D0 + x"03",x"20",x"78",x"FE",x"E0",x"38",x"04",x"FD", -- 0x28D8 + x"36",x"03",x"DF",x"C9",x"FD",x"7E",x"00",x"FE", -- 0x28E0 + x"08",x"DA",x"4F",x"0B",x"FE",x"F8",x"D2",x"4F", -- 0x28E8 + x"0B",x"FD",x"7E",x"03",x"FE",x"08",x"DA",x"4F", -- 0x28F0 + x"0B",x"FE",x"F8",x"D2",x"4F",x"0B",x"DD",x"7E", -- 0x28F8 + x"0E",x"A7",x"C0",x"DD",x"CB",x"08",x"9E",x"CD", -- 0x2900 + x"67",x"0B",x"F6",x"0F",x"DD",x"77",x"0E",x"21", -- 0x2908 + x"2B",x"29",x"DD",x"E5",x"D1",x"13",x"3E",x"00", -- 0x2910 + x"32",x"01",x"70",x"01",x"04",x"00",x"ED",x"B0", -- 0x2918 + x"3C",x"32",x"01",x"70",x"CD",x"67",x"0B",x"DD", -- 0x2920 + x"77",x"07",x"C9",x"A2",x"1D",x"C1",x"0B",x"DD", -- 0x2928 + x"7E",x"06",x"A7",x"C0",x"DD",x"36",x"06",x"11", -- 0x2930 + x"11",x"C1",x"0B",x"DD",x"73",x"03",x"DD",x"72", -- 0x2938 + x"04",x"DD",x"36",x"05",x"01",x"DD",x"46",x"0F", -- 0x2940 + x"CB",x"60",x"28",x"04",x"3E",x"02",x"A8",x"47", -- 0x2948 + x"CB",x"68",x"28",x"04",x"3E",x"08",x"A8",x"47", -- 0x2950 + x"DD",x"70",x"0F",x"DD",x"35",x"07",x"C0",x"DD", -- 0x2958 + x"E5",x"D1",x"13",x"21",x"DD",x"27",x"01",x"04", -- 0x2960 + x"00",x"AF",x"32",x"01",x"70",x"ED",x"B0",x"3C", -- 0x2968 + x"32",x"01",x"70",x"CD",x"E7",x"08",x"DD",x"70", -- 0x2970 + x"03",x"DD",x"71",x"04",x"DD",x"CB",x"08",x"DE", -- 0x2978 + x"C9",x"9B",x"1D",x"00",x"00",x"00",x"00",x"00", -- 0x2980 + x"00",x"7F",x"7E",x"7F",x"7E",x"7F",x"7E",x"7F", -- 0x2988 + x"7E",x"7F",x"7E",x"7F",x"7E",x"7F",x"7E",x"7F", -- 0x2990 + x"7E",x"7F",x"7E",x"7F",x"7E",x"7F",x"7E",x"7F", -- 0x2998 + x"7E",x"5F",x"5E",x"5F",x"5E",x"5F",x"5E",x"5F", -- 0x29A0 + x"5E",x"5F",x"5E",x"5F",x"5E",x"5F",x"5E",x"5F", -- 0x29A8 + x"5E",x"5F",x"5E",x"5F",x"5E",x"5F",x"5E",x"5F", -- 0x29B0 + x"5E",x"5F",x"5E",x"5F",x"5E",x"5F",x"5E",x"5F", -- 0x29B8 + x"5E",x"3F",x"3E",x"3F",x"3E",x"3F",x"3E",x"3F", -- 0x29C0 + x"3E",x"3F",x"3E",x"3F",x"3E",x"3F",x"3E",x"3F", -- 0x29C8 + x"3E",x"3F",x"3E",x"3F",x"3E",x"3F",x"3E",x"3F", -- 0x29D0 + x"3E",x"3F",x"3E",x"3F",x"3E",x"3F",x"3E",x"3F", -- 0x29D8 + x"3E",x"1F",x"1E",x"1F",x"1E",x"1F",x"1E",x"1F", -- 0x29E0 + x"1E",x"1F",x"1E",x"1F",x"1E",x"1F",x"1E",x"1F", -- 0x29E8 + x"1E",x"1F",x"1E",x"1F",x"1E",x"1F",x"1E",x"1F", -- 0x29F0 + x"1E",x"1F",x"1E",x"1F",x"1E",x"1F",x"1E",x"1F", -- 0x29F8 + x"1E",x"FF",x"FF",x"FD",x"FD",x"FF",x"FF",x"FD", -- 0x2A00 + x"FD",x"FF",x"FF",x"FD",x"FD",x"FF",x"FF",x"FD", -- 0x2A08 + x"FD",x"FF",x"FF",x"FD",x"FD",x"FF",x"FF",x"FD", -- 0x2A10 + x"FD",x"FF",x"FF",x"FD",x"FD",x"FF",x"FF",x"FD", -- 0x2A18 + x"FD",x"DF",x"DF",x"DD",x"DD",x"DF",x"DF",x"DD", -- 0x2A20 + x"DD",x"DF",x"DF",x"DD",x"DD",x"DF",x"DF",x"DD", -- 0x2A28 + x"DD",x"DF",x"DF",x"DD",x"DD",x"DF",x"DF",x"DD", -- 0x2A30 + x"DD",x"DF",x"DF",x"DD",x"DD",x"DF",x"DF",x"DD", -- 0x2A38 + x"DD",x"BF",x"BF",x"BD",x"BD",x"BF",x"BF",x"BD", -- 0x2A40 + x"BD",x"BF",x"BF",x"BD",x"BD",x"BF",x"BF",x"BD", -- 0x2A48 + x"BD",x"BF",x"BF",x"BD",x"BD",x"BF",x"BF",x"BD", -- 0x2A50 + x"BD",x"BF",x"BF",x"BD",x"BD",x"BF",x"BF",x"BD", -- 0x2A58 + x"BD",x"9F",x"9F",x"9D",x"9D",x"9F",x"9F",x"9D", -- 0x2A60 + x"9D",x"9F",x"9F",x"9D",x"9D",x"9F",x"9F",x"9D", -- 0x2A68 + x"9D",x"9F",x"9F",x"9D",x"9D",x"9F",x"9F",x"9D", -- 0x2A70 + x"9D",x"9F",x"9F",x"9D",x"9D",x"9F",x"9F",x"9D", -- 0x2A78 + x"9D",x"7F",x"7F",x"7D",x"7D",x"7F",x"7F",x"7D", -- 0x2A80 + x"7D",x"7F",x"7F",x"7D",x"7D",x"7F",x"7F",x"7D", -- 0x2A88 + x"7D",x"7F",x"7F",x"7D",x"7D",x"7F",x"7F",x"7D", -- 0x2A90 + x"7D",x"7F",x"7F",x"7D",x"7D",x"7F",x"7F",x"7D", -- 0x2A98 + x"7D",x"5F",x"5F",x"5D",x"5D",x"5F",x"5F",x"5D", -- 0x2AA0 + x"5D",x"5F",x"5F",x"5D",x"5D",x"5F",x"5F",x"5D", -- 0x2AA8 + x"5D",x"5F",x"5F",x"5D",x"5D",x"5F",x"5F",x"5D", -- 0x2AB0 + x"5D",x"5F",x"5F",x"5D",x"5D",x"5F",x"5F",x"5D", -- 0x2AB8 + x"5D",x"3F",x"3F",x"3D",x"3D",x"3F",x"3F",x"3D", -- 0x2AC0 + x"3D",x"3F",x"3F",x"3D",x"3D",x"3F",x"3F",x"3D", -- 0x2AC8 + x"3D",x"3F",x"3F",x"3D",x"3D",x"3F",x"3F",x"3D", -- 0x2AD0 + x"3D",x"3F",x"3F",x"3D",x"3D",x"3F",x"3F",x"3D", -- 0x2AD8 + x"3D",x"1F",x"1F",x"1D",x"1D",x"1F",x"1F",x"1D", -- 0x2AE0 + x"1D",x"1F",x"1F",x"1D",x"1D",x"1F",x"1F",x"1D", -- 0x2AE8 + x"1D",x"1F",x"1F",x"1D",x"1D",x"1F",x"1F",x"1D", -- 0x2AF0 + x"1D",x"1F",x"1F",x"1D",x"1D",x"1F",x"1F",x"1D", -- 0x2AF8 + x"1D",x"FF",x"FE",x"FD",x"FC",x"FF",x"FE",x"FD", -- 0x2B00 + x"FC",x"FF",x"FE",x"FD",x"FC",x"FF",x"FE",x"FD", -- 0x2B08 + x"FC",x"FF",x"FE",x"FD",x"FC",x"FF",x"FE",x"FD", -- 0x2B10 + x"FC",x"FF",x"FE",x"FD",x"FC",x"FF",x"FE",x"FD", -- 0x2B18 + x"FC",x"DF",x"DE",x"DD",x"DC",x"DF",x"DE",x"DD", -- 0x2B20 + x"DC",x"DF",x"DE",x"DD",x"DC",x"DF",x"DE",x"DD", -- 0x2B28 + x"DC",x"DF",x"DE",x"DD",x"DC",x"DF",x"DE",x"DD", -- 0x2B30 + x"DC",x"DF",x"DE",x"DD",x"DC",x"DF",x"DE",x"DD", -- 0x2B38 + x"DC",x"BF",x"BE",x"BD",x"BC",x"BF",x"BE",x"BD", -- 0x2B40 + x"BC",x"BF",x"BE",x"BD",x"BC",x"BF",x"BE",x"BD", -- 0x2B48 + x"BC",x"BF",x"BE",x"BD",x"BC",x"BF",x"BE",x"BD", -- 0x2B50 + x"BC",x"BF",x"BE",x"BD",x"BC",x"BF",x"BE",x"BD", -- 0x2B58 + x"BC",x"9F",x"9E",x"9D",x"9C",x"9F",x"9E",x"9D", -- 0x2B60 + x"9C",x"9F",x"9E",x"9D",x"9C",x"9F",x"9E",x"9D", -- 0x2B68 + x"9C",x"9F",x"9E",x"9D",x"9C",x"9F",x"9E",x"9D", -- 0x2B70 + x"9C",x"9F",x"9E",x"9D",x"9C",x"9F",x"9E",x"9D", -- 0x2B78 + x"9C",x"7F",x"7E",x"7D",x"7C",x"7F",x"7E",x"7D", -- 0x2B80 + x"7C",x"7F",x"7E",x"7D",x"7C",x"7F",x"7E",x"7D", -- 0x2B88 + x"7C",x"7F",x"7E",x"7D",x"7C",x"7F",x"7E",x"7D", -- 0x2B90 + x"7C",x"7F",x"7E",x"7D",x"7C",x"7F",x"7E",x"7D", -- 0x2B98 + x"7C",x"5F",x"5E",x"5D",x"5C",x"5F",x"5E",x"5D", -- 0x2BA0 + x"5C",x"5F",x"5E",x"5D",x"5C",x"5F",x"5E",x"5D", -- 0x2BA8 + x"5C",x"5F",x"5E",x"5D",x"5C",x"5F",x"5E",x"5D", -- 0x2BB0 + x"5C",x"5F",x"5E",x"5D",x"5C",x"5F",x"5E",x"5D", -- 0x2BB8 + x"5C",x"3F",x"3E",x"3D",x"3C",x"3F",x"3E",x"3D", -- 0x2BC0 + x"3C",x"3F",x"3E",x"3D",x"3C",x"3F",x"3E",x"3D", -- 0x2BC8 + x"3C",x"3F",x"3E",x"3D",x"3C",x"3F",x"3E",x"3D", -- 0x2BD0 + x"3C",x"3F",x"3E",x"3D",x"3C",x"3F",x"3E",x"3D", -- 0x2BD8 + x"3C",x"1F",x"1E",x"1D",x"1C",x"1F",x"1E",x"1D", -- 0x2BE0 + x"1C",x"1F",x"1E",x"1D",x"1C",x"1F",x"1E",x"1D", -- 0x2BE8 + x"1C",x"1F",x"1E",x"1D",x"1C",x"1F",x"1E",x"1D", -- 0x2BF0 + x"1C",x"1F",x"1E",x"1D",x"1C",x"1F",x"1E",x"1D", -- 0x2BF8 + x"1C",x"FF",x"FF",x"FF",x"FF",x"FB",x"FB",x"FB", -- 0x2C00 + x"FB",x"FF",x"FF",x"FF",x"FF",x"FB",x"FB",x"FB", -- 0x2C08 + x"FB",x"FF",x"FF",x"FF",x"FF",x"FB",x"FB",x"FB", -- 0x2C10 + x"FB",x"FF",x"FF",x"FF",x"FF",x"FB",x"FB",x"FB", -- 0x2C18 + x"FB",x"DF",x"DF",x"DF",x"DF",x"DB",x"DB",x"DB", -- 0x2C20 + x"DB",x"DF",x"DF",x"DF",x"DF",x"DB",x"DB",x"DB", -- 0x2C28 + x"DB",x"DF",x"DF",x"DF",x"DF",x"DB",x"DB",x"DB", -- 0x2C30 + x"DB",x"DF",x"DF",x"DF",x"DF",x"DB",x"DB",x"DB", -- 0x2C38 + x"DB",x"BF",x"BF",x"BF",x"BF",x"BB",x"BB",x"BB", -- 0x2C40 + x"BB",x"BF",x"BF",x"BF",x"BF",x"BB",x"BB",x"BB", -- 0x2C48 + x"BB",x"BF",x"BF",x"BF",x"BF",x"BB",x"BB",x"BB", -- 0x2C50 + x"BB",x"BF",x"BF",x"BF",x"BF",x"BB",x"BB",x"BB", -- 0x2C58 + x"BB",x"9F",x"9F",x"9F",x"9F",x"9B",x"9B",x"9B", -- 0x2C60 + x"9B",x"9F",x"9F",x"9F",x"9F",x"9B",x"9B",x"9B", -- 0x2C68 + x"9B",x"9F",x"9F",x"9F",x"9F",x"9B",x"9B",x"9B", -- 0x2C70 + x"9B",x"9F",x"9F",x"9F",x"9F",x"9B",x"9B",x"9B", -- 0x2C78 + x"9B",x"7F",x"7F",x"7F",x"7F",x"7B",x"7B",x"7B", -- 0x2C80 + x"7B",x"7F",x"7F",x"7F",x"7F",x"7B",x"7B",x"7B", -- 0x2C88 + x"7B",x"7F",x"7F",x"7F",x"7F",x"7B",x"7B",x"7B", -- 0x2C90 + x"7B",x"7F",x"7F",x"7F",x"7F",x"7B",x"7B",x"7B", -- 0x2C98 + x"7B",x"5F",x"5F",x"5F",x"5F",x"5B",x"5B",x"5B", -- 0x2CA0 + x"5B",x"5F",x"5F",x"5F",x"5F",x"5B",x"5B",x"5B", -- 0x2CA8 + x"5B",x"5F",x"5F",x"5F",x"5F",x"5B",x"5B",x"5B", -- 0x2CB0 + x"5B",x"5F",x"5F",x"5F",x"5F",x"5B",x"5B",x"5B", -- 0x2CB8 + x"5B",x"3F",x"3F",x"3F",x"3F",x"3B",x"3B",x"3B", -- 0x2CC0 + x"3B",x"3F",x"3F",x"3F",x"3F",x"3B",x"3B",x"3B", -- 0x2CC8 + x"3B",x"3F",x"3F",x"3F",x"3F",x"3B",x"3B",x"3B", -- 0x2CD0 + x"3B",x"3F",x"3F",x"3F",x"3F",x"3B",x"3B",x"3B", -- 0x2CD8 + x"3B",x"1F",x"1F",x"1F",x"1F",x"1B",x"1B",x"1B", -- 0x2CE0 + x"1B",x"1F",x"1F",x"1F",x"1F",x"1B",x"1B",x"1B", -- 0x2CE8 + x"1B",x"1F",x"1F",x"1F",x"1F",x"1B",x"1B",x"1B", -- 0x2CF0 + x"1B",x"1F",x"1F",x"1F",x"1F",x"1B",x"1B",x"1B", -- 0x2CF8 + x"1B",x"FF",x"FE",x"FF",x"FE",x"FB",x"FA",x"FB", -- 0x2D00 + x"FA",x"FF",x"FE",x"FF",x"FE",x"FB",x"FA",x"FB", -- 0x2D08 + x"FA",x"FF",x"FE",x"FF",x"FE",x"FB",x"FA",x"FB", -- 0x2D10 + x"FA",x"FF",x"FE",x"FF",x"FE",x"FB",x"FA",x"FB", -- 0x2D18 + x"FA",x"DF",x"DE",x"DF",x"DE",x"DB",x"DA",x"DB", -- 0x2D20 + x"DA",x"DF",x"DE",x"DF",x"DE",x"DB",x"DA",x"DB", -- 0x2D28 + x"DA",x"DF",x"DE",x"DF",x"DE",x"DB",x"DA",x"DB", -- 0x2D30 + x"DA",x"DF",x"DE",x"DF",x"DE",x"DB",x"DA",x"DB", -- 0x2D38 + x"DA",x"BF",x"BE",x"BF",x"BE",x"BB",x"BA",x"BB", -- 0x2D40 + x"BA",x"BF",x"BE",x"BF",x"BE",x"BB",x"BA",x"BB", -- 0x2D48 + x"BA",x"BF",x"BE",x"BF",x"BE",x"BB",x"BA",x"BB", -- 0x2D50 + x"BA",x"BF",x"BE",x"BF",x"BE",x"BB",x"BA",x"BB", -- 0x2D58 + x"BA",x"9F",x"9E",x"9F",x"9E",x"9B",x"9A",x"9B", -- 0x2D60 + x"9A",x"9F",x"9E",x"9F",x"9E",x"9B",x"9A",x"9B", -- 0x2D68 + x"9A",x"9F",x"9E",x"9F",x"9E",x"9B",x"9A",x"9B", -- 0x2D70 + x"9A",x"9F",x"9E",x"9F",x"9E",x"9B",x"9A",x"9B", -- 0x2D78 + x"9A",x"7F",x"7E",x"7F",x"7E",x"7B",x"7A",x"7B", -- 0x2D80 + x"7A",x"7F",x"7E",x"7F",x"7E",x"7B",x"7A",x"7B", -- 0x2D88 + x"7A",x"7F",x"7E",x"7F",x"7E",x"7B",x"7A",x"7B", -- 0x2D90 + x"7A",x"7F",x"7E",x"7F",x"7E",x"7B",x"7A",x"7B", -- 0x2D98 + x"7A",x"5F",x"5E",x"5F",x"5E",x"5B",x"5A",x"5B", -- 0x2DA0 + x"5A",x"5F",x"5E",x"5F",x"5E",x"5B",x"5A",x"5B", -- 0x2DA8 + x"5A",x"5F",x"5E",x"5F",x"5E",x"5B",x"5A",x"5B", -- 0x2DB0 + x"5A",x"5F",x"5E",x"5F",x"5E",x"5B",x"5A",x"5B", -- 0x2DB8 + x"5A",x"3F",x"3E",x"3F",x"3E",x"3B",x"3A",x"3B", -- 0x2DC0 + x"3A",x"3F",x"3E",x"3F",x"3E",x"3B",x"3A",x"3B", -- 0x2DC8 + x"3A",x"3F",x"3E",x"3F",x"3E",x"3B",x"3A",x"3B", -- 0x2DD0 + x"3A",x"3F",x"3E",x"3F",x"3E",x"3B",x"3A",x"3B", -- 0x2DD8 + x"3A",x"1F",x"1E",x"1F",x"1E",x"1B",x"1A",x"1B", -- 0x2DE0 + x"1A",x"1F",x"1E",x"1F",x"1E",x"1B",x"1A",x"1B", -- 0x2DE8 + x"1A",x"1F",x"1E",x"1F",x"1E",x"1B",x"1A",x"1B", -- 0x2DF0 + x"1A",x"1F",x"1E",x"1F",x"1E",x"1B",x"1A",x"1B", -- 0x2DF8 + x"1A",x"FF",x"FF",x"FD",x"FD",x"FB",x"FB",x"F9", -- 0x2E00 + x"F9",x"FF",x"FF",x"FD",x"FD",x"FB",x"FB",x"F9", -- 0x2E08 + x"F9",x"FF",x"FF",x"FD",x"FD",x"FB",x"FB",x"F9", -- 0x2E10 + x"F9",x"FF",x"FF",x"FD",x"FD",x"FB",x"FB",x"F9", -- 0x2E18 + x"F9",x"DF",x"DF",x"DD",x"DD",x"DB",x"DB",x"D9", -- 0x2E20 + x"D9",x"DF",x"DF",x"DD",x"DD",x"DB",x"DB",x"D9", -- 0x2E28 + x"D9",x"DF",x"DF",x"DD",x"DD",x"DB",x"DB",x"D9", -- 0x2E30 + x"D9",x"DF",x"DF",x"DD",x"DD",x"DB",x"DB",x"D9", -- 0x2E38 + x"D9",x"BF",x"BF",x"BD",x"BD",x"BB",x"BB",x"B9", -- 0x2E40 + x"B9",x"BF",x"BF",x"BD",x"BD",x"BB",x"BB",x"B9", -- 0x2E48 + x"B9",x"BF",x"BF",x"BD",x"BD",x"BB",x"BB",x"B9", -- 0x2E50 + x"B9",x"BF",x"BF",x"BD",x"BD",x"BB",x"BB",x"B9", -- 0x2E58 + x"B9",x"9F",x"9F",x"9D",x"9D",x"9B",x"9B",x"99", -- 0x2E60 + x"99",x"9F",x"9F",x"9D",x"9D",x"9B",x"9B",x"99", -- 0x2E68 + x"99",x"9F",x"9F",x"9D",x"9D",x"9B",x"9B",x"99", -- 0x2E70 + x"99",x"9F",x"9F",x"9D",x"9D",x"9B",x"9B",x"99", -- 0x2E78 + x"99",x"7F",x"7F",x"7D",x"7D",x"7B",x"7B",x"79", -- 0x2E80 + x"79",x"7F",x"7F",x"7D",x"7D",x"7B",x"7B",x"79", -- 0x2E88 + x"79",x"7F",x"7F",x"7D",x"7D",x"7B",x"7B",x"79", -- 0x2E90 + x"79",x"7F",x"7F",x"7D",x"7D",x"7B",x"7B",x"79", -- 0x2E98 + x"79",x"5F",x"5F",x"5D",x"5D",x"5B",x"5B",x"59", -- 0x2EA0 + x"59",x"5F",x"5F",x"5D",x"5D",x"5B",x"5B",x"59", -- 0x2EA8 + x"59",x"5F",x"5F",x"5D",x"5D",x"5B",x"5B",x"59", -- 0x2EB0 + x"59",x"5F",x"5F",x"5D",x"5D",x"5B",x"5B",x"59", -- 0x2EB8 + x"59",x"3F",x"3F",x"3D",x"3D",x"3B",x"3B",x"39", -- 0x2EC0 + x"39",x"3F",x"3F",x"3D",x"3D",x"3B",x"3B",x"39", -- 0x2EC8 + x"39",x"3F",x"3F",x"3D",x"3D",x"3B",x"3B",x"39", -- 0x2ED0 + x"39",x"3F",x"3F",x"3D",x"3D",x"3B",x"3B",x"39", -- 0x2ED8 + x"39",x"1F",x"1F",x"1D",x"1D",x"1B",x"1B",x"19", -- 0x2EE0 + x"19",x"1F",x"1F",x"1D",x"1D",x"1B",x"1B",x"19", -- 0x2EE8 + x"19",x"1F",x"1F",x"1D",x"1D",x"1B",x"1B",x"19", -- 0x2EF0 + x"19",x"1F",x"1F",x"1D",x"1D",x"1B",x"1B",x"19", -- 0x2EF8 + x"19",x"FF",x"FE",x"FD",x"FC",x"FB",x"FA",x"F9", -- 0x2F00 + x"F8",x"FF",x"FE",x"FD",x"FC",x"FB",x"FA",x"F9", -- 0x2F08 + x"F8",x"FF",x"FE",x"FD",x"FC",x"FB",x"FA",x"F9", -- 0x2F10 + x"F8",x"FF",x"FE",x"FD",x"FC",x"FB",x"FA",x"F9", -- 0x2F18 + x"F8",x"DF",x"DE",x"DD",x"DC",x"DB",x"DA",x"D9", -- 0x2F20 + x"D8",x"DF",x"DE",x"DD",x"DC",x"DB",x"DA",x"D9", -- 0x2F28 + x"D8",x"DF",x"DE",x"DD",x"DC",x"DB",x"DA",x"D9", -- 0x2F30 + x"D8",x"DF",x"DE",x"DD",x"DC",x"DB",x"DA",x"D9", -- 0x2F38 + x"D8",x"BF",x"BE",x"BD",x"BC",x"BB",x"BA",x"B9", -- 0x2F40 + x"B8",x"BF",x"BE",x"BD",x"BC",x"BB",x"BA",x"B9", -- 0x2F48 + x"B8",x"BF",x"BE",x"BD",x"BC",x"BB",x"BA",x"B9", -- 0x2F50 + x"B8",x"BF",x"BE",x"BD",x"BC",x"BB",x"BA",x"B9", -- 0x2F58 + x"B8",x"9F",x"9E",x"9D",x"9C",x"9B",x"9A",x"99", -- 0x2F60 + x"98",x"9F",x"9E",x"9D",x"9C",x"9B",x"9A",x"99", -- 0x2F68 + x"98",x"9F",x"9E",x"9D",x"9C",x"9B",x"9A",x"99", -- 0x2F70 + x"98",x"9F",x"9E",x"9D",x"9C",x"9B",x"9A",x"99", -- 0x2F78 + x"98",x"7F",x"7E",x"7D",x"7C",x"7B",x"7A",x"79", -- 0x2F80 + x"78",x"7F",x"7E",x"7D",x"7C",x"7B",x"7A",x"79", -- 0x2F88 + x"78",x"7F",x"7E",x"7D",x"7C",x"7B",x"7A",x"79", -- 0x2F90 + x"78",x"7F",x"7E",x"7D",x"7C",x"7B",x"7A",x"79", -- 0x2F98 + x"78",x"5F",x"5E",x"5D",x"5C",x"5B",x"5A",x"59", -- 0x2FA0 + x"58",x"5F",x"5E",x"5D",x"5C",x"5B",x"5A",x"59", -- 0x2FA8 + x"58",x"5F",x"5E",x"5D",x"5C",x"5B",x"5A",x"59", -- 0x2FB0 + x"58",x"5F",x"5E",x"5D",x"5C",x"5B",x"5A",x"59", -- 0x2FB8 + x"58",x"3F",x"3E",x"3D",x"3C",x"3B",x"3A",x"39", -- 0x2FC0 + x"38",x"3F",x"3E",x"3D",x"3C",x"3B",x"3A",x"39", -- 0x2FC8 + x"38",x"3F",x"3E",x"3D",x"3C",x"3B",x"3A",x"39", -- 0x2FD0 + x"38",x"3F",x"3E",x"3D",x"3C",x"3B",x"3A",x"39", -- 0x2FD8 + x"38",x"1F",x"1E",x"1D",x"1C",x"1B",x"1A",x"19", -- 0x2FE0 + x"18",x"1F",x"1E",x"1D",x"1C",x"1B",x"1A",x"19", -- 0x2FE8 + x"18",x"1F",x"1E",x"1D",x"1C",x"1B",x"1A",x"19", -- 0x2FF0 + x"18",x"1F",x"1E",x"1D",x"1C",x"1B",x"1A",x"19" -- 0x2FF8 + ); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; + diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.v new file mode 100644 index 00000000..2a638338 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180109" +`define BUILD_TIME "174542" diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..5f8a3a74 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + +-- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(3), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(2), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..5a4d0094 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..677a03d1 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0' & I_2P_SH & I_1P_SH & I_COIN1 & I_1P_LE & I_1P_RI & I_2P_LE & I_2P_RI; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "10" & I_1P_LE & I_1P_RI & I_2P_LE & I_2P_RI & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..e924e09e --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 0) = "11111010") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 0) = "11111010") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..dbe0d0d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.qip b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.vhd new file mode 100644 index 00000000..bb04a979 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..7b2b9717 --- /dev/null +++ b/Arcade/Galaxian Hardware/AzurianAttack_MiST/rtl/video_mixer.sv @@ -0,0 +1,246 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +// Scanline FIX +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +// Scanline FIX + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.qpf b/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.qpf new file mode 100644 index 00000000..fd1b9b51 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "BlackHole" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.qsf b/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.qsf new file mode 100644 index 00000000..a6ca2898 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# BlackHole_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlackHole.sv +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY BlackHole +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.srf b/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.srf new file mode 100644 index 00000000..063fa14d --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/BlackHole.srf @@ -0,0 +1,52 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/README.txt b/Arcade/Galaxian Hardware/BlackHole_MiST/README.txt new file mode 100644 index 00000000..e32c947b --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Black Hole port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/Release/BlackHole.rbf b/Arcade/Galaxian Hardware/BlackHole_MiST/Release/BlackHole.rbf new file mode 100644 index 00000000..1a6a8849 Binary files /dev/null and b/Arcade/Galaxian Hardware/BlackHole_MiST/Release/BlackHole.rbf differ diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/clean.bat b/Arcade/Galaxian Hardware/BlackHole_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/BlackHole.sv b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/BlackHole.sv new file mode 100644 index 00000000..6a436fca --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/BlackHole.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: BlackHole +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module BlackHole +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "BlackHole;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian blackhole +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,2'b00,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,2'b00,m_down,m_up}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..73af8474 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"22",X"3E",X"00",X"3E",X"2A",X"2A",X"2A",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22", + X"22",X"3E",X"00",X"02",X"3E",X"22",X"00",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22", + X"C0",X"E0",X"E0",X"F0",X"70",X"70",X"78",X"78",X"03",X"07",X"07",X"0F",X"0E",X"0E",X"1E",X"1E", + X"3C",X"3C",X"3E",X"1F",X"1F",X"0F",X"07",X"03",X"3C",X"3C",X"7C",X"F8",X"F8",X"F0",X"E0",X"C0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"01",X"43",X"12",X"06",X"0C",X"38",X"7A",X"C0",X"18",X"9A",X"28",X"1C",X"49",X"18",X"08",X"18", + X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00", + X"80",X"90",X"90",X"90",X"FE",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..b5bcbc4e --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1K is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"22",X"3E",X"00",X"3E",X"2A",X"2A",X"2A",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22", + X"22",X"3E",X"00",X"02",X"3E",X"22",X"00",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22", + X"00",X"18",X"18",X"0C",X"0C",X"0C",X"06",X"07",X"00",X"18",X"18",X"30",X"30",X"30",X"60",X"E0", + X"03",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"10",X"02",X"04",X"10",X"68",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"03",X"3F",X"7F",X"3F",X"3F",X"7F",X"3F",X"1F",X"CC",X"FC",X"FC",X"DC",X"5E",X"EE",X"EE",X"EE", + X"1F",X"3F",X"3F",X"3F",X"3F",X"7F",X"61",X"C0",X"FC",X"FC",X"FE",X"FF",X"FE",X"FE",X"FF",X"1D", + X"00",X"00",X"67",X"FF",X"7D",X"38",X"38",X"1C",X"03",X"36",X"FC",X"FC",X"B8",X"18",X"0E",X"1F", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..2f811f7d --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07", + X"00",X"C0",X"A0",X"07",X"00",X"00",X"00",X"07",X"00",X"F6",X"07",X"F0",X"00",X"76",X"07",X"C6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", + X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", + X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", + X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", + X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", + X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", + X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd new file mode 100644 index 00000000..7d2fd29c --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..3ca80bee --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,790 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 12287) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"70",X"C3",X"50",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/build_id.v new file mode 100644 index 00000000..bef80912 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "172130" diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..b881e738 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..014e6f7a --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..1d61cf9c --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_inport.vhd @@ -0,0 +1,72 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + +signal W_TABLE : std_logic := '1'; -- UP TYPE = 1; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else "000" & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000110"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..dbe0d0d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/pll.qip b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/BlackHole_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.qpf b/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.qpf new file mode 100644 index 00000000..3b0d4109 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "Catacomb" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.qsf b/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.qsf new file mode 100644 index 00000000..5e04b7ba --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaxian_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Catacomb +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Catacomb.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.srf b/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.srf new file mode 100644 index 00000000..14cddd5e --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/Catacomb.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/README.txt b/Arcade/Galaxian Hardware/Catacomb_MiST/README.txt new file mode 100644 index 00000000..f7001aa3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Catacomb port to MiST by Gehstock +-- 19 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/Release/Catacomb.rbf b/Arcade/Galaxian Hardware/Catacomb_MiST/Release/Catacomb.rbf new file mode 100644 index 00000000..9ec4c661 Binary files /dev/null and b/Arcade/Galaxian Hardware/Catacomb_MiST/Release/Catacomb.rbf differ diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/clean.bat b/Arcade/Galaxian Hardware/Catacomb_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/Catacomb.sv b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/Catacomb.sv new file mode 100644 index 00000000..0ee557ef --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/Catacomb.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Catacomb +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Catacomb +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Catacomb;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian catacomb +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..dec55c15 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,285 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1H is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1H is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"CF",x"0F",x"0F",x"0F",x"0F",x"0E",x"0C",x"08", -- 0x0050 + x"08",x"0C",x"0E",x"0E",x"0F",x"0F",x"0F",x"8F", -- 0x0058 + x"00",x"00",x"00",x"18",x"18",x"00",x"00",x"00", -- 0x0060 + x"18",x"28",x"38",x"2C",x"38",x"28",x"18",x"00", -- 0x0068 + x"40",x"20",x"10",x"08",x"04",x"02",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"0D",x"53",x"31",x"19",x"08",x"04",x"F2",x"00", -- 0x0168 + x"3C",x"42",x"A5",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0180 + x"00",x"00",x"00",x"00",x"03",x"07",x"07",x"7B", -- 0x0188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0190 + x"07",x"07",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 + x"F0",x"10",x"30",x"60",x"C0",x"C0",x"60",x"E0", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 + x"01",x"01",x"01",x"01",x"02",x"03",x"01",x"01", -- 0x01D0 + x"18",x"3C",x"7E",x"FF",x"3C",x"3C",x"3C",x"3C", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 + x"40",x"60",x"40",x"60",x"40",x"60",x"40",x"60", -- 0x01E8 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x01F0 + x"FF",x"9F",x"9F",x"9F",x"FF",x"91",x"91",x"91", -- 0x01F8 + x"80",x"40",x"20",x"10",x"00",x"02",x"26",x"24", -- 0x0200 + x"00",x"00",x"00",x"00",x"01",x"41",x"63",x"2F", -- 0x0208 + x"24",x"27",x"03",x"00",x"10",x"20",x"40",x"80", -- 0x0210 + x"2F",x"E3",x"C1",x"01",x"00",x"00",x"00",x"00", -- 0x0218 + x"07",x"08",x"08",x"08",x"07",x"00",x"07",x"08", -- 0x0220 + x"C0",x"20",x"20",x"20",x"C0",x"00",x"C0",x"20", -- 0x0228 + x"08",x"08",x"07",x"00",x"00",x"0F",x"04",x"00", -- 0x0230 + x"20",x"20",x"C0",x"00",x"20",x"E0",x"20",x"00", -- 0x0238 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0240 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0248 + x"07",x"00",x"06",x"09",x"08",x"08",x"04",x"00", -- 0x0250 + x"C0",x"00",x"20",x"20",x"A0",x"60",x"20",x"00", -- 0x0258 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0260 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0268 + x"07",x"00",x"07",x"09",x"09",x"08",x"04",x"00", -- 0x0270 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"40",x"00", -- 0x0278 + x"01",x"07",x"1F",x"3F",x"3F",x"7F",x"7F",x"FF", -- 0x0280 + x"80",x"E0",x"F0",x"F8",x"F8",x"FC",x"FC",x"FE", -- 0x0288 + x"FF",x"7F",x"7F",x"3F",x"3F",x"1F",x"07",x"01", -- 0x0290 + x"FE",x"FC",x"FC",x"F8",x"F8",x"F0",x"E0",x"80", -- 0x0298 + x"01",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x02A0 + x"80",x"C0",x"C0",x"C0",x"CE",x"D0",x"E0",x"E0", -- 0x02A8 + x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"01", -- 0x02B0 + x"E0",x"E0",x"D0",x"CE",x"C0",x"C0",x"C0",x"80", -- 0x02B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"0F", -- 0x02C0 + x"00",x"07",x"0F",x"1F",x"00",x"00",x"FF",x"FF", -- 0x02C8 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"FF",x"00",x"00",x"1F",x"0F",x"07",x"00",x"00", -- 0x02D8 + x"00",x"00",x"00",x"00",x"01",x"00",x"07",x"F8", -- 0x02E0 + x"00",x"00",x"00",x"00",x"C0",x"1C",x"FA",x"03", -- 0x02E8 + x"07",x"00",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 + x"FA",x"1C",x"C0",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"02",x"00", -- 0x0300 + x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E4", -- 0x0308 + x"00",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"E4",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0318 + x"0F",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0320 + x"F0",x"80",x"C0",x"E0",x"F0",x"F8",x"F8",x"F8", -- 0x0328 + x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0330 + x"F8",x"F8",x"F8",x"F0",x"E0",x"C0",x"80",x"F0", -- 0x0338 + x"0F",x"01",x"01",x"01",x"01",x"01",x"01",x"07", -- 0x0340 + x"C0",x"00",x"00",x"00",x"00",x"00",x"00",x"8F", -- 0x0348 + x"07",x"01",x"01",x"01",x"01",x"01",x"01",x"0F", -- 0x0350 + x"8F",x"00",x"00",x"00",x"00",x"00",x"00",x"E0", -- 0x0358 + x"01",x"07",x"1F",x"3F",x"3F",x"7F",x"7F",x"FF", -- 0x0360 + x"80",x"E0",x"F0",x"F8",x"F8",x"FC",x"FC",x"FE", -- 0x0368 + x"FF",x"7F",x"7F",x"3F",x"3F",x"1F",x"07",x"01", -- 0x0370 + x"FE",x"FC",x"FC",x"F8",x"F8",x"F0",x"E0",x"80", -- 0x0378 + x"00",x"00",x"0D",x"16",x"15",x"1B",x"3E",x"35", -- 0x0380 + x"00",x"E0",x"50",x"FC",x"AE",x"57",x"AB",x"F5", -- 0x0388 + x"6B",x"5E",x"75",x"2B",x"3D",x"16",x"0C",x"00", -- 0x0390 + x"5D",x"AB",x"F6",x"6E",x"DA",x"34",x"18",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"01",x"00",x"07",x"F8", -- 0x03A0 + x"00",x"00",x"00",x"01",x"C6",x"1E",x"FC",x"10", -- 0x03A8 + x"07",x"00",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 + x"E0",x"00",x"C0",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"00",x"01",x"00",x"07",x"F8", -- 0x03C0 + x"00",x"00",x"00",x"00",x"C0",x"00",x"F0",x"1C", -- 0x03C8 + x"07",x"00",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 + x"FE",x"03",x"C0",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"0A",x"1B",x"39",x"4D",x"4C",x"FA",x"FE",x"CA", -- 0x03E0 + x"01",x"E3",x"DD",x"00",x"38",x"FC",x"E1",x"E3", -- 0x03E8 + x"CA",x"FE",x"FA",x"4C",x"4D",x"39",x"1B",x"0A", -- 0x03F0 + x"E3",x"FD",x"3C",x"38",x"00",x"C1",x"E3",x"1D", -- 0x03F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0400 + x"81",x"81",x"81",x"81",x"81",x"81",x"81",x"FF", -- 0x0408 + x"81",x"81",x"81",x"81",x"81",x"81",x"81",x"81", -- 0x0410 + x"FF",x"81",x"81",x"81",x"81",x"81",x"81",x"81", -- 0x0418 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x0420 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"C0", -- 0x0428 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 + x"80",x"C0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"02",x"03",x"00",x"00",x"03",x"03",x"02",x"02", -- 0x0440 + x"E0",x"F0",x"F0",x"F0",x"B0",x"F0",x"B0",x"B0", -- 0x0448 + x"07",x"07",x"07",x"03",x"03",x"00",x"00",x"00", -- 0x0450 + x"F0",x"B0",x"B0",x"F0",x"B0",x"A0",x"E0",x"C0", -- 0x0458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0460 + x"00",x"00",x"00",x"00",x"00",x"40",x"C0",x"C0", -- 0x0468 + x"03",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0488 + x"03",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"02", -- 0x04A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"C0", -- 0x04A8 + x"03",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 + x"F0",x"C0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 + x"0A",x"1B",x"39",x"4D",x"7C",x"CA",x"CA",x"FE", -- 0x04C0 + x"00",x"F8",x"C7",x"00",x"20",x"30",x"F0",x"F8", -- 0x04C8 + x"FE",x"CA",x"CA",x"7C",x"4D",x"3D",x"1B",x"0A", -- 0x04D0 + x"F8",x"F7",x"30",x"20",x"00",x"C0",x"F8",x"07", -- 0x04D8 + x"0F",x"09",x"01",x"03",x"01",x"01",x"02",x"02", -- 0x04E0 + x"78",x"48",x"40",x"80",x"E0",x"60",x"A0",x"80", -- 0x04E8 + x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 + x"00",x"00",x"00",x"20",x"00",x"00",x"00",x"00", -- 0x04F8 + x"00",x"01",x"01",x"01",x"01",x"00",x"02",x"07", -- 0x0500 + x"80",x"C0",x"E0",x"E0",x"E0",x"C0",x"E0",x"D0", -- 0x0508 + x"06",x"26",x"3F",x"06",x"01",x"01",x"01",x"01", -- 0x0510 + x"C0",x"E0",x"C0",x"D0",x"E0",x"40",x"20",x"80", -- 0x0518 + x"0F",x"09",x"01",x"01",x"03",x"01",x"07",x"03", -- 0x0520 + x"78",x"48",x"40",x"E0",x"A0",x"E0",x"40",x"C0", -- 0x0528 + x"01",x"01",x"01",x"01",x"00",x"02",x"00",x"00", -- 0x0530 + x"C0",x"80",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"00",x"01",x"01",x"01",x"03",x"00",x"07",x"04", -- 0x0540 + x"80",x"C0",x"C0",x"C0",x"E0",x"C0",x"D0",x"F0", -- 0x0548 + x"04",x"07",x"04",x"00",x"03",x"01",x"03",x"07", -- 0x0550 + x"D0",x"D0",x"F0",x"C0",x"E0",x"C0",x"E0",x"F0", -- 0x0558 + x"0F",x"09",x"01",x"01",x"00",x"03",x"03",x"01", -- 0x0560 + x"78",x"48",x"00",x"C0",x"E0",x"A0",x"C0",x"40", -- 0x0568 + x"01",x"00",x"00",x"01",x"01",x"00",x"00",x"00", -- 0x0570 + x"C0",x"80",x"C0",x"60",x"20",x"40",x"00",x"00", -- 0x0578 + x"00",x"01",x"01",x"01",x"03",x"03",x"04",x"04", -- 0x0580 + x"80",x"C0",x"C0",x"C0",x"E0",x"E0",x"D0",x"D0", -- 0x0588 + x"07",x"04",x"04",x"03",x"02",x"01",x"03",x"07", -- 0x0590 + x"F0",x"D0",x"C0",x"E0",x"E0",x"C0",x"E0",x"F0", -- 0x0598 + x"0F",x"09",x"01",x"01",x"03",x"01",x"02",x"01", -- 0x05A0 + x"78",x"48",x"00",x"C0",x"E0",x"80",x"C0",x"00", -- 0x05A8 + x"01",x"01",x"02",x"01",x"01",x"01",x"00",x"00", -- 0x05B0 + x"C0",x"C0",x"80",x"80",x"00",x"00",x"80",x"80", -- 0x05B8 + x"00",x"01",x"01",x"01",x"03",x"00",x"04",x"07", -- 0x05C0 + x"80",x"C0",x"C0",x"C0",x"E0",x"C0",x"F0",x"D0", -- 0x05C8 + x"04",x"04",x"07",x"00",x"01",x"01",x"03",x"07", -- 0x05D0 + x"D0",x"F0",x"D0",x"C0",x"E0",x"40",x"60",x"70", -- 0x05D8 + x"0A",x"1B",x"39",x"4D",x"7C",x"CA",x"CA",x"FE", -- 0x05E0 + x"03",x"C7",x"EB",x"00",x"3F",x"3F",x"C7",x"C7", -- 0x05E8 + x"FE",x"CA",x"CA",x"7C",x"4D",x"39",x"1B",x"0A", -- 0x05F0 + x"C7",x"FF",x"3F",x"3F",x"00",x"C3",x"C7",x"3B", -- 0x05F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0600 + x"B6",x"6D",x"DB",x"B6",x"6D",x"DB",x"B6",x"6D", -- 0x0608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0628 + x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0630 + x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0638 + x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0640 + x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0648 + x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658 + x"01",x"03",x"04",x"03",x"27",x"3E",x"6C",x"F8", -- 0x0660 + x"86",x"CF",x"2F",x"C6",x"E0",x"70",x"36",x"1F", -- 0x0668 + x"FE",x"6F",x"3F",x"27",x"03",x"04",x"03",x"01", -- 0x0670 + x"7F",x"F6",x"F0",x"E0",x"C6",x"2F",x"CF",x"86", -- 0x0678 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0680 + x"E7",x"24",x"24",x"3C",x"3C",x"24",x"24",x"E7", -- 0x0688 + x"00",x"70",x"F0",x"9B",x"8B",x"C0",x"60",x"00", -- 0x0690 + x"FF",x"D3",x"81",x"C9",x"82",x"91",x"CB",x"F3", -- 0x0698 + x"00",x"00",x"00",x"01",x"01",x"03",x"04",x"06", -- 0x06A0 + x"80",x"80",x"00",x"00",x"80",x"C0",x"C0",x"A0", -- 0x06A8 + x"15",x"0B",x"0D",x"0F",x"02",x"07",x"01",x"01", -- 0x06B0 + x"88",x"78",x"F8",x"B0",x"E0",x"B0",x"E0",x"40", -- 0x06B8 + x"00",x"02",x"03",x"0E",x"16",x"23",x"17",x"0C", -- 0x06C0 + x"48",x"B0",x"20",x"44",x"98",x"20",x"A0",x"C0", -- 0x06C8 + x"0F",x"0C",x"17",x"23",x"16",x"0F",x"02",x"02", -- 0x06D0 + x"C0",x"C0",x"A0",x"20",x"98",x"44",x"B0",x"48", -- 0x06D8 + x"00",x"1D",x"0F",x"07",x"07",x"0F",x"0F",x"0F", -- 0x06E0 + x"00",x"C0",x"80",x"00",x"00",x"80",x"80",x"C0", -- 0x06E8 + x"1F",x"1F",x"1F",x"03",x"09",x"0F",x"00",x"00", -- 0x06F0 + x"C0",x"C0",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 + x"20",x"10",x"08",x"04",x"04",x"41",x"03",x"01", -- 0x0700 + x"00",x"00",x"01",x"02",x"1C",x"80",x"A2",x"60", -- 0x0708 + x"06",x"13",x"20",x"40",x"00",x"02",x"10",x"00", -- 0x0710 + x"40",x"CC",x"80",x"60",x"10",x"08",x"03",x"00", -- 0x0718 + x"08",x"04",x"04",x"02",x"81",x"43",x"22",x"15", -- 0x0720 + x"01",x"06",x"08",x"10",x"30",x"20",x"C0",x"A0", -- 0x0728 + x"0F",x"09",x"06",x"33",x"40",x"81",x"01",x"02", -- 0x0730 + x"50",x"DE",x"61",x"D0",x"10",x"18",x"08",x"04", -- 0x0738 + x"04",x"02",x"02",x"01",x"06",x"8F",x"76",x"1A", -- 0x0740 + x"04",x"08",x"10",x"C0",x"B0",x"E8",x"2F",x"98", -- 0x0748 + x"1B",x"1C",x"0A",x"07",x"07",x"08",x"08",x"10", -- 0x0750 + x"EC",x"CC",x"B8",x"F0",x"90",x"08",x"86",x"41", -- 0x0758 + x"80",x"40",x"25",x"1F",x"17",x"0D",x"5B",x"B2", -- 0x0760 + x"21",x"41",x"42",x"B4",x"FC",x"B0",x"D8",x"EE", -- 0x0768 + x"1A",x"0F",x"05",x"1E",x"1D",x"23",x"40",x"80", -- 0x0770 + x"E9",x"56",x"F8",x"DC",x"E8",x"4C",x"82",x"81", -- 0x0778 + x"00",x"03",x"0F",x"3F",x"3F",x"7F",x"FF",x"FF", -- 0x0780 + x"00",x"80",x"80",x"E0",x"E0",x"F0",x"F8",x"FE", -- 0x0788 + x"FF",x"FF",x"7F",x"7F",x"1F",x"0F",x"0F",x"06", -- 0x0790 + x"FF",x"FF",x"FE",x"FC",x"F0",x"E0",x"00",x"00", -- 0x0798 + x"28",x"44",x"00",x"08",x"08",x"10",x"00",x"40", -- 0x07A0 + x"00",x"20",x"00",x"66",x"02",x"00",x"20",x"44", -- 0x07A8 + x"0A",x"08",x"20",x"A0",x"41",x"08",x"0A",x"00", -- 0x07B0 + x"46",x"00",x"00",x"C0",x"00",x"04",x"10",x"10", -- 0x07B8 + x"20",x"0E",x"CD",x"FC",x"1F",x"E5",x"CD",x"58", -- 0x07C0 + x"3E",x"CD",x"62",x"3D",x"CD",x"F4",x"3C",x"E1", -- 0x07C8 + x"C5",x"D5",x"4F",x"CD",x"39",x"23",x"47",x"C5", -- 0x07D0 + x"E5",x"2A",x"71",x"0E",x"E3",x"06",x"82",x"C5", -- 0x07D8 + x"33",x"CD",x"2D",x"33",x"C4",x"03",x"19",x"22", -- 0x07E0 + x"79",x"0E",x"ED",x"73",x"7B",x"0E",x"7E",x"FE", -- 0x07E8 + x"3A",x"28",x"29",x"B7",x"C2",x"99",x"10",x"23", -- 0x07F0 + x"7E",x"23",x"B6",x"CA",x"37",x"10",x"23",x"5E" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..4ed5bb4c --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,285 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1K is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1K is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"CF",x"0F",x"0F",x"0F",x"0F",x"0E",x"0C",x"08", -- 0x0050 + x"08",x"0C",x"0E",x"0E",x"0F",x"0F",x"0F",x"8F", -- 0x0058 + x"00",x"00",x"00",x"18",x"18",x"00",x"00",x"00", -- 0x0060 + x"18",x"28",x"38",x"2C",x"38",x"28",x"18",x"00", -- 0x0068 + x"40",x"20",x"10",x"08",x"04",x"02",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"0D",x"13",x"11",x"09",x"00",x"00",x"F0",x"00", -- 0x0168 + x"3C",x"42",x"A5",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x0180 + x"00",x"00",x"00",x"03",x"04",x"08",x"78",x"FC", -- 0x0188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0190 + x"78",x"08",x"04",x"03",x"00",x"00",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"00",x"81",x"42",x"24",x"18", -- 0x01A0 + x"00",x"30",x"48",x"84",x"03",x"00",x"00",x"00", -- 0x01A8 + x"00",x"10",x"28",x"44",x"83",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"00",x"00",x"83",x"44",x"28",x"10", -- 0x01B8 + x"F0",x"10",x"30",x"60",x"C0",x"C0",x"60",x"E0", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 + x"01",x"01",x"01",x"01",x"02",x"03",x"01",x"01", -- 0x01D0 + x"18",x"3C",x"7E",x"FF",x"3C",x"3C",x"3C",x"3C", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 + x"40",x"60",x"40",x"60",x"40",x"60",x"40",x"60", -- 0x01E8 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x01F0 + x"FF",x"9F",x"9F",x"9F",x"FF",x"91",x"91",x"91", -- 0x01F8 + x"80",x"40",x"20",x"10",x"00",x"02",x"26",x"24", -- 0x0200 + x"00",x"00",x"00",x"00",x"01",x"41",x"63",x"2F", -- 0x0208 + x"24",x"27",x"03",x"00",x"10",x"20",x"40",x"80", -- 0x0210 + x"2F",x"E3",x"C1",x"01",x"00",x"00",x"00",x"00", -- 0x0218 + x"07",x"08",x"08",x"08",x"07",x"00",x"07",x"08", -- 0x0220 + x"C0",x"20",x"20",x"20",x"C0",x"00",x"C0",x"20", -- 0x0228 + x"08",x"08",x"07",x"00",x"00",x"0F",x"04",x"00", -- 0x0230 + x"20",x"20",x"C0",x"00",x"20",x"E0",x"20",x"00", -- 0x0238 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0240 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0248 + x"07",x"00",x"06",x"09",x"08",x"08",x"04",x"00", -- 0x0250 + x"C0",x"00",x"20",x"20",x"A0",x"60",x"20",x"00", -- 0x0258 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0260 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0268 + x"07",x"00",x"07",x"09",x"09",x"08",x"04",x"00", -- 0x0270 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"40",x"00", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 + x"00",x"00",x"01",x"00",x"08",x"1D",x"1C",x"1C", -- 0x02A0 + x"00",x"00",x"80",x"00",x"00",x"80",x"00",x"00", -- 0x02A8 + x"1C",x"1C",x"1D",x"08",x"00",x"01",x"00",x"00", -- 0x02B0 + x"00",x"00",x"80",x"00",x"00",x"80",x"00",x"00", -- 0x02B8 + x"00",x"00",x"00",x"00",x"00",x"01",x"1E",x"F0", -- 0x02C0 + x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x02C8 + x"1E",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 + x"00",x"00",x"00",x"01",x"02",x"07",x"F8",x"07", -- 0x02E0 + x"00",x"00",x"00",x"C0",x"00",x"DC",x"3A",x"C3", -- 0x02E8 + x"F8",x"07",x"02",x"01",x"00",x"00",x"00",x"00", -- 0x02F0 + x"3A",x"DC",x"00",x"C0",x"00",x"00",x"00",x"00", -- 0x02F8 + x"00",x"00",x"00",x"01",x"03",x"07",x"0D",x"1F", -- 0x0300 + x"00",x"00",x"10",x"10",x"18",x"18",x"1E",x"1A", -- 0x0308 + x"1F",x"0D",x"07",x"03",x"01",x"00",x"00",x"00", -- 0x0310 + x"1A",x"1E",x"18",x"18",x"10",x"10",x"00",x"00", -- 0x0318 + x"0F",x"07",x"05",x"06",x"07",x"07",x"03",x"05", -- 0x0320 + x"F0",x"80",x"C0",x"E0",x"70",x"B8",x"D8",x"EF", -- 0x0328 + x"05",x"03",x"07",x"07",x"06",x"05",x"07",x"0F", -- 0x0330 + x"EF",x"D8",x"B8",x"70",x"E0",x"C0",x"80",x"F0", -- 0x0338 + x"00",x"00",x"00",x"00",x"02",x"82",x"CE",x"FF", -- 0x0340 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"F0", -- 0x0348 + x"FF",x"CE",x"82",x"02",x"00",x"00",x"00",x"00", -- 0x0350 + x"F0",x"C0",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x0358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"00",x"00",x"00",x"0D",x"0B",x"0E",x"15",x"1E", -- 0x0380 + x"00",x"00",x"E0",x"A0",x"58",x"FC",x"5E",x"AA", -- 0x0388 + x"35",x"2B",x"3E",x"15",x"1A",x"0C",x"00",x"00", -- 0x0390 + x"F6",x"5E",x"A8",x"D4",x"2C",x"18",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"01",x"02",x"07",x"F8",x"07", -- 0x03A0 + x"00",x"00",x"00",x"C1",x"06",x"DE",x"3C",x"D0", -- 0x03A8 + x"F8",x"07",x"02",x"01",x"00",x"00",x"00",x"00", -- 0x03B0 + x"20",x"C0",x"00",x"C0",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"01",x"02",x"07",x"F8",x"07", -- 0x03C0 + x"00",x"00",x"00",x"C0",x"00",x"C0",x"30",x"DC", -- 0x03C8 + x"F8",x"07",x"02",x"01",x"00",x"00",x"00",x"00", -- 0x03D0 + x"3E",x"C3",x"00",x"C0",x"00",x"00",x"00",x"00", -- 0x03D8 + x"0A",x"1B",x"39",x"4D",x"4C",x"FA",x"FE",x"CA", -- 0x03E0 + x"01",x"E3",x"DD",x"00",x"38",x"FC",x"E1",x"E3", -- 0x03E8 + x"CA",x"FE",x"FA",x"4C",x"4D",x"39",x"1B",x"0A", -- 0x03F0 + x"E3",x"FD",x"3C",x"38",x"00",x"C1",x"E3",x"1D", -- 0x03F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0400 + x"81",x"81",x"81",x"81",x"81",x"81",x"81",x"FF", -- 0x0408 + x"81",x"81",x"81",x"81",x"81",x"81",x"81",x"81", -- 0x0410 + x"FF",x"81",x"81",x"81",x"81",x"81",x"81",x"81", -- 0x0418 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x0420 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"C0", -- 0x0428 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 + x"80",x"C0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"02",x"03",x"00",x"00",x"03",x"03",x"02",x"02", -- 0x0440 + x"E0",x"F0",x"F0",x"F0",x"B0",x"F0",x"B0",x"B0", -- 0x0448 + x"07",x"07",x"07",x"03",x"03",x"00",x"00",x"00", -- 0x0450 + x"F0",x"B0",x"B0",x"F0",x"B0",x"A0",x"E0",x"C0", -- 0x0458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0460 + x"00",x"00",x"00",x"00",x"00",x"40",x"C0",x"C0", -- 0x0468 + x"03",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0488 + x"03",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"02", -- 0x04A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"C0", -- 0x04A8 + x"03",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 + x"F0",x"C0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 + x"0A",x"1B",x"39",x"4D",x"7C",x"CA",x"CA",x"FE", -- 0x04C0 + x"00",x"F8",x"C7",x"00",x"20",x"30",x"F0",x"F8", -- 0x04C8 + x"FE",x"CA",x"CA",x"7C",x"4D",x"3D",x"1B",x"0A", -- 0x04D0 + x"F8",x"F7",x"30",x"20",x"00",x"C0",x"F8",x"07", -- 0x04D8 + x"0F",x"09",x"01",x"03",x"01",x"01",x"02",x"02", -- 0x04E0 + x"78",x"48",x"40",x"80",x"E0",x"60",x"A0",x"80", -- 0x04E8 + x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 + x"00",x"00",x"00",x"20",x"00",x"00",x"00",x"00", -- 0x04F8 + x"00",x"01",x"01",x"01",x"01",x"00",x"02",x"07", -- 0x0500 + x"80",x"C0",x"E0",x"E0",x"E0",x"C0",x"E0",x"D0", -- 0x0508 + x"06",x"26",x"3F",x"06",x"01",x"01",x"01",x"01", -- 0x0510 + x"C0",x"E0",x"C0",x"D0",x"E0",x"40",x"20",x"80", -- 0x0518 + x"0F",x"09",x"01",x"01",x"03",x"01",x"07",x"03", -- 0x0520 + x"78",x"48",x"40",x"E0",x"A0",x"E0",x"40",x"C0", -- 0x0528 + x"01",x"01",x"01",x"01",x"00",x"02",x"00",x"00", -- 0x0530 + x"C0",x"80",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"00",x"01",x"01",x"01",x"03",x"00",x"07",x"04", -- 0x0540 + x"80",x"C0",x"C0",x"C0",x"E0",x"C0",x"D0",x"F0", -- 0x0548 + x"04",x"07",x"04",x"00",x"03",x"01",x"03",x"07", -- 0x0550 + x"D0",x"D0",x"F0",x"C0",x"E0",x"C0",x"E0",x"F0", -- 0x0558 + x"0F",x"09",x"01",x"01",x"00",x"03",x"03",x"01", -- 0x0560 + x"78",x"48",x"00",x"C0",x"E0",x"A0",x"C0",x"40", -- 0x0568 + x"01",x"00",x"00",x"01",x"01",x"00",x"00",x"00", -- 0x0570 + x"C0",x"80",x"C0",x"60",x"20",x"40",x"00",x"00", -- 0x0578 + x"00",x"01",x"01",x"01",x"03",x"03",x"04",x"04", -- 0x0580 + x"80",x"C0",x"C0",x"C0",x"E0",x"E0",x"D0",x"D0", -- 0x0588 + x"07",x"04",x"04",x"03",x"02",x"01",x"03",x"07", -- 0x0590 + x"F0",x"D0",x"C0",x"E0",x"E0",x"C0",x"E0",x"F0", -- 0x0598 + x"0F",x"09",x"01",x"01",x"03",x"01",x"02",x"01", -- 0x05A0 + x"78",x"48",x"00",x"C0",x"E0",x"80",x"C0",x"00", -- 0x05A8 + x"01",x"01",x"02",x"01",x"01",x"01",x"00",x"00", -- 0x05B0 + x"C0",x"C0",x"80",x"80",x"00",x"00",x"80",x"80", -- 0x05B8 + x"00",x"01",x"01",x"01",x"03",x"00",x"04",x"07", -- 0x05C0 + x"80",x"C0",x"C0",x"C0",x"E0",x"C0",x"F0",x"D0", -- 0x05C8 + x"04",x"04",x"07",x"00",x"01",x"01",x"03",x"07", -- 0x05D0 + x"D0",x"F0",x"D0",x"C0",x"E0",x"40",x"60",x"70", -- 0x05D8 + x"0A",x"1B",x"39",x"4D",x"7C",x"CA",x"CA",x"FE", -- 0x05E0 + x"03",x"C7",x"EB",x"00",x"3F",x"3F",x"C7",x"C7", -- 0x05E8 + x"FE",x"CA",x"CA",x"7C",x"4D",x"39",x"1B",x"0A", -- 0x05F0 + x"C7",x"FF",x"3F",x"3F",x"00",x"C3",x"C7",x"3B", -- 0x05F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 + x"6D",x"DB",x"B6",x"6D",x"DB",x"B6",x"6D",x"DB", -- 0x0608 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0610 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0628 + x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0630 + x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0638 + x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0640 + x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0648 + x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658 + x"01",x"03",x"04",x"03",x"27",x"3E",x"6C",x"F8", -- 0x0660 + x"86",x"CF",x"2F",x"C6",x"E0",x"70",x"36",x"1F", -- 0x0668 + x"FE",x"6F",x"3F",x"27",x"03",x"04",x"03",x"01", -- 0x0670 + x"7F",x"F6",x"F0",x"E0",x"C6",x"2F",x"CF",x"86", -- 0x0678 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0680 + x"E7",x"24",x"24",x"3C",x"3C",x"24",x"24",x"E7", -- 0x0688 + x"00",x"70",x"F0",x"9B",x"8B",x"C0",x"60",x"00", -- 0x0690 + x"FF",x"D3",x"81",x"C9",x"82",x"91",x"CB",x"F3", -- 0x0698 + x"00",x"00",x"00",x"01",x"01",x"03",x"04",x"06", -- 0x06A0 + x"80",x"80",x"00",x"00",x"80",x"C0",x"C0",x"A0", -- 0x06A8 + x"15",x"0B",x"0D",x"0F",x"02",x"07",x"01",x"01", -- 0x06B0 + x"88",x"78",x"F8",x"B0",x"E0",x"B0",x"E0",x"40", -- 0x06B8 + x"00",x"02",x"03",x"0E",x"16",x"23",x"17",x"0C", -- 0x06C0 + x"48",x"B0",x"20",x"44",x"98",x"20",x"A0",x"C0", -- 0x06C8 + x"0F",x"0C",x"17",x"23",x"16",x"0F",x"02",x"02", -- 0x06D0 + x"C0",x"C0",x"A0",x"20",x"98",x"44",x"B0",x"48", -- 0x06D8 + x"00",x"1D",x"0F",x"07",x"07",x"0F",x"0F",x"0F", -- 0x06E0 + x"00",x"C0",x"80",x"00",x"00",x"80",x"80",x"C0", -- 0x06E8 + x"1F",x"1F",x"1F",x"03",x"09",x"0F",x"00",x"00", -- 0x06F0 + x"C0",x"C0",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 + x"20",x"10",x"08",x"04",x"04",x"41",x"03",x"01", -- 0x0700 + x"00",x"00",x"01",x"02",x"1C",x"80",x"A2",x"60", -- 0x0708 + x"06",x"13",x"20",x"40",x"00",x"02",x"10",x"00", -- 0x0710 + x"40",x"CC",x"80",x"60",x"10",x"08",x"03",x"00", -- 0x0718 + x"08",x"04",x"04",x"02",x"81",x"43",x"22",x"15", -- 0x0720 + x"01",x"06",x"08",x"10",x"30",x"20",x"C0",x"A0", -- 0x0728 + x"0F",x"09",x"06",x"33",x"40",x"81",x"01",x"02", -- 0x0730 + x"50",x"DE",x"61",x"D0",x"10",x"18",x"08",x"04", -- 0x0738 + x"04",x"02",x"02",x"01",x"06",x"8F",x"76",x"1A", -- 0x0740 + x"04",x"08",x"10",x"C0",x"B0",x"E8",x"2F",x"98", -- 0x0748 + x"1B",x"1C",x"0A",x"07",x"07",x"08",x"08",x"10", -- 0x0750 + x"EC",x"CC",x"B8",x"F0",x"90",x"08",x"86",x"41", -- 0x0758 + x"80",x"40",x"25",x"1F",x"17",x"0D",x"5B",x"B2", -- 0x0760 + x"21",x"41",x"42",x"B4",x"FC",x"B0",x"D8",x"EE", -- 0x0768 + x"1A",x"0F",x"05",x"1E",x"1D",x"23",x"40",x"80", -- 0x0770 + x"E9",x"56",x"F8",x"DC",x"E8",x"4C",x"82",x"81", -- 0x0778 + x"00",x"03",x"0F",x"3F",x"3F",x"7F",x"FF",x"FF", -- 0x0780 + x"00",x"80",x"80",x"E0",x"E0",x"F0",x"F8",x"FE", -- 0x0788 + x"FF",x"FF",x"7F",x"7F",x"1F",x"0F",x"0F",x"06", -- 0x0790 + x"FF",x"FF",x"FE",x"FC",x"F0",x"E0",x"00",x"00", -- 0x0798 + x"68",x"40",x"00",x"0C",x"10",x"00",x"00",x"48", -- 0x07A0 + x"00",x"00",x"65",x"44",x"00",x"00",x"64",x"85", -- 0x07A8 + x"14",x"0C",x"60",x"E0",x"01",x"08",x"14",x"08", -- 0x07B0 + x"04",x"02",x"00",x"40",x"80",x"10",x"0C",x"10", -- 0x07B8 + x"06",x"86",x"82",x"E6",x"FF",x"28",x"70",x"00", -- 0x07C0 + x"40",x"40",x"40",x"80",x"81",x"02",x"84",x"48", -- 0x07C8 + x"07",x"04",x"8B",x"4E",x"3B",x"37",x"2E",x"3D", -- 0x07D0 + x"F0",x"50",x"A0",x"6C",x"3E",x"D4",x"B0",x"54", -- 0x07D8 + x"10",x"08",x"05",x"02",x"01",x"87",x"4B",x"26", -- 0x07E0 + x"10",x"20",x"A0",x"60",x"D0",x"48",x"F1",x"B2", -- 0x07E8 + x"1C",x"0B",x"0F",x"3D",x"33",x"9E",x"75",x"57", -- 0x07F0 + x"DC",x"EC",x"74",x"BC",x"DD",x"76",x"D4",x"5E" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..e989225e --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,33 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_6L is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(4 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_6L is + + + type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"7A",x"36",x"07",x"00",x"F0",x"38",x"1F", -- 0x0000 + x"00",x"C7",x"F0",x"3F",x"00",x"DB",x"C6",x"38", -- 0x0008 + x"00",x"36",x"07",x"F0",x"00",x"33",x"3F",x"DB", -- 0x0010 + x"00",x"3F",x"57",x"C6",x"00",x"C6",x"3F",x"FF" -- 0x0018 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", + 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is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", + X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", + X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", + X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", + 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X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80", + X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80", + X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83", + X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78", + X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D", + X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", + X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80", + X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D", + X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78", + X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83", + X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78", + X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75", + X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D", + X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80", + X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78", + X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D", + X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D", + X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D", + X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78", + X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D", + X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D", + X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", + X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", + X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", + X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", + X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", + X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..8b3669d9 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,2077 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ROM_PGM_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM_0 is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"C3",x"16",x"0A",x"FF",x"FF",x"FF",x"FF",x"2F", -- 0x0000 + x"47",x"7E",x"70",x"2F",x"B0",x"2F",x"12",x"13", -- 0x0008 + x"23",x"C9",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0010 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0018 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0028 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0030 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0038 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0040 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0048 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0050 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0058 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"E5",x"F5", -- 0x0060 + x"21",x"13",x"40",x"34",x"AF",x"32",x"01",x"70", -- 0x0068 + x"3E",x"01",x"32",x"01",x"70",x"3A",x"00",x"78", -- 0x0070 + x"F1",x"E1",x"C9",x"F5",x"C5",x"D5",x"E5",x"DD", -- 0x0078 + x"E5",x"FD",x"E5",x"3A",x"00",x"78",x"CD",x"D3", -- 0x0080 + x"08",x"AF",x"32",x"01",x"70",x"21",x"14",x"40", -- 0x0088 + x"34",x"CB",x"5E",x"28",x"03",x"32",x"03",x"60", -- 0x0090 + x"3E",x"01",x"32",x"01",x"70",x"32",x"04",x"70", -- 0x0098 + x"21",x"13",x"40",x"7E",x"BE",x"28",x"FD",x"3A", -- 0x00A0 + x"05",x"40",x"32",x"06",x"70",x"32",x"07",x"70", -- 0x00A8 + x"06",x"08",x"DD",x"21",x"3B",x"40",x"FD",x"21", -- 0x00B0 + x"40",x"58",x"DD",x"7E",x"00",x"FD",x"77",x"00", -- 0x00B8 + x"DD",x"7E",x"01",x"FD",x"77",x"03",x"DD",x"7E", -- 0x00C0 + x"04",x"FD",x"77",x"02",x"DD",x"7E",x"05",x"FD", -- 0x00C8 + x"77",x"01",x"11",x"04",x"00",x"FD",x"19",x"11", -- 0x00D0 + x"0A",x"00",x"DD",x"19",x"10",x"DC",x"06",x"08", -- 0x00D8 + x"DD",x"21",x"CF",x"40",x"FD",x"21",x"60",x"58", -- 0x00E0 + x"CD",x"88",x"06",x"E6",x"01",x"DD",x"86",x"00", -- 0x00E8 + x"C6",x"08",x"FD",x"77",x"01",x"DD",x"7E",x"01", -- 0x00F0 + x"21",x"05",x"40",x"CB",x"46",x"20",x"04",x"C6", -- 0x00F8 + x"10",x"ED",x"44",x"FD",x"77",x"03",x"11",x"05", -- 0x0100 + x"00",x"DD",x"19",x"11",x"04",x"00",x"FD",x"19", -- 0x0108 + x"10",x"D6",x"21",x"8F",x"40",x"11",x"00",x"58", -- 0x0110 + x"01",x"40",x"00",x"ED",x"B0",x"3A",x"15",x"40", -- 0x0118 + x"FE",x"FA",x"38",x"23",x"3A",x"44",x"52",x"FE", -- 0x0120 + x"2B",x"20",x"1C",x"DD",x"21",x"31",x"52",x"3E", -- 0x0128 + x"27",x"DD",x"96",x"64",x"D6",x"0A",x"28",x"0F", -- 0x0130 + x"DD",x"21",x"7F",x"40",x"3E",x"FA",x"C6",x"1B", -- 0x0138 + x"DD",x"77",x"9C",x"AF",x"32",x"15",x"40",x"21", -- 0x0140 + x"06",x"40",x"11",x"09",x"40",x"3A",x"00",x"60", -- 0x0148 + x"CD",x"07",x"00",x"3A",x"00",x"68",x"CD",x"07", -- 0x0150 + x"00",x"0E",x"00",x"DD",x"21",x"63",x"10",x"CD", -- 0x0158 + x"C4",x"0F",x"20",x"06",x"0C",x"CD",x"C4",x"0F", -- 0x0160 + x"28",x"2E",x"3E",x"01",x"32",x"03",x"60",x"32", -- 0x0168 + x"14",x"40",x"3A",x"00",x"68",x"07",x"07",x"07", -- 0x0170 + x"E6",x"06",x"81",x"87",x"6F",x"26",x"00",x"11", -- 0x0178 + x"6B",x"10",x"19",x"3A",x"1C",x"40",x"86",x"27", -- 0x0180 + x"32",x"1C",x"40",x"23",x"3A",x"1B",x"40",x"8E", -- 0x0188 + x"27",x"30",x"02",x"3E",x"99",x"32",x"1B",x"40", -- 0x0190 + x"FD",x"E1",x"DD",x"E1",x"E1",x"D1",x"C1",x"F1", -- 0x0198 + x"C9",x"21",x"00",x"40",x"11",x"01",x"40",x"01", -- 0x01A0 + x"4E",x"01",x"36",x"00",x"ED",x"B0",x"C9",x"21", -- 0x01A8 + x"3B",x"40",x"11",x"3C",x"40",x"01",x"13",x"01", -- 0x01B0 + x"36",x"00",x"ED",x"B0",x"C9",x"CD",x"7B",x"00", -- 0x01B8 + x"21",x"00",x"50",x"11",x"01",x"50",x"01",x"FF", -- 0x01C0 + x"03",x"36",x"10",x"ED",x"B0",x"CD",x"AF",x"01", -- 0x01C8 + x"21",x"8F",x"40",x"06",x"20",x"23",x"70",x"23", -- 0x01D0 + x"10",x"FB",x"21",x"15",x"40",x"34",x"CD",x"7B", -- 0x01D8 + x"00",x"CD",x"7F",x"08",x"AF",x"32",x"3F",x"41", -- 0x01E0 + x"CD",x"8C",x"09",x"3D",x"32",x"00",x"78",x"C9", -- 0x01E8 + x"DD",x"6E",x"00",x"DD",x"66",x"01",x"DD",x"23", -- 0x01F0 + x"DD",x"23",x"7D",x"3C",x"C8",x"11",x"E0",x"FF", -- 0x01F8 + x"DD",x"7E",x"00",x"DD",x"23",x"FE",x"24",x"28", -- 0x0200 + x"E7",x"CB",x"7F",x"20",x"06",x"D6",x"30",x"77", -- 0x0208 + x"19",x"18",x"ED",x"DD",x"7E",x"FF",x"87",x"87", -- 0x0210 + x"CD",x"61",x"06",x"19",x"18",x"F2",x"DD",x"21", -- 0x0218 + x"CF",x"40",x"06",x"08",x"DD",x"7E",x"00",x"B7", -- 0x0220 + x"28",x"77",x"DD",x"7E",x"04",x"32",x"0C",x"40", -- 0x0228 + x"DD",x"7E",x"00",x"DD",x"86",x"02",x"DD",x"77", -- 0x0230 + x"00",x"E6",x"F8",x"20",x"06",x"DD",x"36",x"00", -- 0x0238 + x"00",x"18",x"5E",x"DD",x"7E",x"01",x"DD",x"86", -- 0x0240 + x"03",x"DD",x"77",x"01",x"2F",x"E6",x"F0",x"28", -- 0x0248 + x"EC",x"DD",x"6E",x"00",x"DD",x"66",x"01",x"DD", -- 0x0250 + x"E5",x"C5",x"0E",x"00",x"DD",x"7E",x"04",x"B7", -- 0x0258 + x"28",x"02",x"0E",x"80",x"CD",x"17",x"05",x"C1", -- 0x0260 + x"DD",x"E1",x"C2",x"3D",x"02",x"3A",x"00",x"40", -- 0x0268 + x"E6",x"01",x"20",x"2D",x"DD",x"56",x"01",x"DD", -- 0x0270 + x"5E",x"00",x"CD",x"BF",x"05",x"28",x"22",x"E6", -- 0x0278 + x"FC",x"FE",x"60",x"28",x"0F",x"FE",x"70",x"28", -- 0x0280 + x"0B",x"FE",x"64",x"28",x"07",x"3E",x"07",x"CD", -- 0x0288 + x"DE",x"06",x"18",x"A9",x"7E",x"CD",x"B3",x"02", -- 0x0290 + x"18",x"A3",x"C0",x"CD",x"88",x"06",x"E6",x"01", -- 0x0298 + x"C9",x"11",x"05",x"00",x"DD",x"19",x"05",x"C2", -- 0x02A0 + x"24",x"02",x"C9",x"00",x"00",x"FF",x"FF",x"E0", -- 0x02A8 + x"FF",x"DF",x"FF",x"F5",x"E6",x"03",x"87",x"E5", -- 0x02B0 + x"5F",x"16",x"00",x"21",x"AB",x"02",x"19",x"5E", -- 0x02B8 + x"23",x"56",x"E1",x"19",x"7D",x"E6",x"1F",x"FE", -- 0x02C0 + x"1C",x"30",x"2E",x"3E",x"E0",x"CD",x"61",x"06", -- 0x02C8 + x"DD",x"E5",x"CD",x"FB",x"02",x"20",x"06",x"DD", -- 0x02D0 + x"75",x"00",x"DD",x"74",x"01",x"DD",x"E1",x"F1", -- 0x02D8 + x"0E",x"03",x"E6",x"FC",x"FE",x"60",x"28",x"07", -- 0x02E0 + x"0C",x"FE",x"70",x"28",x"02",x"0E",x"03",x"79", -- 0x02E8 + x"CD",x"A8",x"09",x"3E",x"15",x"CD",x"DE",x"06", -- 0x02F0 + x"C9",x"F1",x"C9",x"DD",x"21",x"F7",x"40",x"DD", -- 0x02F8 + x"7E",x"01",x"3C",x"C8",x"3C",x"DD",x"23",x"DD", -- 0x0300 + x"23",x"20",x"F4",x"F6",x"01",x"C9",x"21",x"DD", -- 0x0308 + x"21",x"3B",x"40",x"06",x"08",x"AF",x"32",x"28", -- 0x0310 + x"40",x"DD",x"7E",x"00",x"E6",x"FC",x"20",x"0B", -- 0x0318 + x"DD",x"36",x"01",x"00",x"DD",x"36",x"07",x"03", -- 0x0320 + x"C3",x"6A",x"03",x"3A",x"00",x"40",x"DD",x"A6", -- 0x0328 + x"09",x"C2",x"6A",x"03",x"DD",x"7E",x"08",x"B7", -- 0x0330 + x"20",x"24",x"DD",x"7E",x"00",x"DD",x"86",x"02", -- 0x0338 + x"DD",x"77",x"00",x"E6",x"F8",x"20",x"07",x"DD", -- 0x0340 + x"36",x"00",x"00",x"C3",x"6A",x"03",x"DD",x"7E", -- 0x0348 + x"01",x"DD",x"86",x"03",x"DD",x"77",x"01",x"C6", -- 0x0350 + x"18",x"E6",x"E0",x"CA",x"47",x"03",x"DD",x"7E", -- 0x0358 + x"07",x"C5",x"DD",x"E5",x"CD",x"80",x"03",x"DD", -- 0x0360 + x"E1",x"C1",x"21",x"28",x"40",x"DD",x"7E",x"07", -- 0x0368 + x"FE",x"02",x"20",x"01",x"34",x"11",x"0A",x"00", -- 0x0370 + x"DD",x"19",x"05",x"C2",x"19",x"03",x"C9",x"31", -- 0x0378 + x"B7",x"CA",x"8F",x"03",x"FE",x"01",x"CA",x"DE", -- 0x0380 + x"03",x"FE",x"02",x"CA",x"05",x"04",x"C9",x"DD", -- 0x0388 + x"7E",x"05",x"FE",x"16",x"C0",x"DD",x"7E",x"02", -- 0x0390 + x"CB",x"2F",x"32",x"D1",x"40",x"32",x"D6",x"40", -- 0x0398 + x"DD",x"7E",x"02",x"B7",x"28",x"0A",x"CB",x"7F", -- 0x03A0 + x"3E",x"1E",x"28",x"1C",x"3E",x"1D",x"18",x"18", -- 0x03A8 + x"CD",x"88",x"06",x"CB",x"57",x"28",x"14",x"CB", -- 0x03B0 + x"4F",x"3E",x"17",x"28",x"0B",x"CD",x"88",x"06", -- 0x03B8 + x"CB",x"47",x"3E",x"1D",x"28",x"02",x"3E",x"1E", -- 0x03C0 + x"DD",x"77",x"0F",x"ED",x"5B",x"3B",x"40",x"CD", -- 0x03C8 + x"BF",x"05",x"C8",x"CD",x"75",x"05",x"DD",x"21", -- 0x03D0 + x"45",x"40",x"CD",x"75",x"05",x"C9",x"CD",x"88", -- 0x03D8 + x"06",x"E6",x"C0",x"DD",x"B6",x"05",x"DD",x"77", -- 0x03E0 + x"05",x"CD",x"88",x"06",x"DD",x"77",x"04",x"CD", -- 0x03E8 + x"88",x"06",x"E6",x"0F",x"C0",x"DD",x"34",x"05", -- 0x03F0 + x"DD",x"7E",x"05",x"E6",x"3F",x"FE",x"3C",x"C0", -- 0x03F8 + x"DD",x"36",x"00",x"00",x"C9",x"3A",x"00",x"40", -- 0x0400 + x"E6",x"07",x"20",x"26",x"3A",x"3B",x"40",x"DD", -- 0x0408 + x"BE",x"00",x"0E",x"FF",x"38",x"02",x"0E",x"01", -- 0x0410 + x"C6",x"20",x"E6",x"C0",x"20",x"02",x"0E",x"00", -- 0x0418 + x"DD",x"7E",x"02",x"81",x"4F",x"CB",x"7F",x"28", -- 0x0420 + x"02",x"ED",x"44",x"FE",x"04",x"28",x"03",x"DD", -- 0x0428 + x"71",x"02",x"CD",x"88",x"06",x"E6",x"03",x"20", -- 0x0430 + x"03",x"DD",x"34",x"01",x"CD",x"88",x"06",x"E6", -- 0x0438 + x"0F",x"20",x"11",x"DD",x"7E",x"03",x"FE",x"01", -- 0x0440 + x"20",x"07",x"CD",x"88",x"06",x"E6",x"0F",x"20", -- 0x0448 + x"03",x"DD",x"34",x"03",x"CD",x"9F",x"04",x"DD", -- 0x0450 + x"5E",x"00",x"DD",x"56",x"01",x"CD",x"BF",x"05", -- 0x0458 + x"C4",x"75",x"05",x"CD",x"88",x"06",x"E6",x"1F", -- 0x0460 + x"C0",x"3A",x"21",x"40",x"CB",x"5F",x"C8",x"DD", -- 0x0468 + x"5E",x"00",x"DD",x"7E",x"01",x"C6",x"10",x"57", -- 0x0470 + x"D5",x"DD",x"21",x"E3",x"40",x"06",x"06",x"11", -- 0x0478 + x"05",x"00",x"CD",x"DF",x"04",x"D1",x"C0",x"DD", -- 0x0480 + x"73",x"00",x"DD",x"72",x"01",x"DD",x"36",x"02", -- 0x0488 + x"00",x"DD",x"36",x"03",x"03",x"DD",x"36",x"04", -- 0x0490 + x"00",x"3E",x"20",x"CD",x"DE",x"06",x"C9",x"C5", -- 0x0498 + x"DD",x"5E",x"00",x"DD",x"56",x"01",x"7B",x"D6", -- 0x04A0 + x"0A",x"5F",x"D5",x"CD",x"C3",x"04",x"0E",x"02", -- 0x04A8 + x"D1",x"20",x"0B",x"7B",x"C6",x"14",x"5F",x"CD", -- 0x04B0 + x"C3",x"04",x"28",x"05",x"0E",x"FE",x"DD",x"71", -- 0x04B8 + x"02",x"C1",x"C9",x"06",x"07",x"7A",x"C6",x"12", -- 0x04C0 + x"7A",x"D6",x"06",x"57",x"C5",x"CD",x"BF",x"05", -- 0x04C8 + x"C1",x"C0",x"10",x"F4",x"AF",x"C9",x"11",x"05", -- 0x04D0 + x"00",x"06",x"08",x"DD",x"21",x"CF",x"40",x"DD", -- 0x04D8 + x"7E",x"00",x"B7",x"C8",x"DD",x"19",x"10",x"F7", -- 0x04E0 + x"F6",x"01",x"C9",x"11",x"0A",x"00",x"06",x"06", -- 0x04E8 + x"DD",x"21",x"4F",x"40",x"18",x"E9",x"DD",x"75", -- 0x04F0 + x"00",x"DD",x"74",x"01",x"DD",x"73",x"02",x"DD", -- 0x04F8 + x"72",x"03",x"DD",x"71",x"04",x"DD",x"70",x"05", -- 0x0500 + x"D9",x"DD",x"75",x"06",x"DD",x"74",x"07",x"DD", -- 0x0508 + x"73",x"08",x"DD",x"72",x"09",x"D9",x"C9",x"C5", -- 0x0510 + x"DD",x"E5",x"CB",x"81",x"06",x"08",x"DD",x"21", -- 0x0518 + x"3B",x"40",x"CB",x"79",x"20",x"07",x"DD",x"7E", -- 0x0520 + x"07",x"FE",x"02",x"28",x"0A",x"CD",x"9E",x"05", -- 0x0528 + x"20",x"05",x"CB",x"C1",x"CD",x"75",x"05",x"11", -- 0x0530 + x"0A",x"00",x"DD",x"19",x"10",x"E4",x"79",x"E6", -- 0x0538 + x"01",x"DD",x"E1",x"C1",x"C9",x"D5",x"7A",x"C6", -- 0x0540 + x"08",x"1F",x"1F",x"E6",x"3E",x"5F",x"16",x"00", -- 0x0548 + x"21",x"8F",x"40",x"19",x"7E",x"ED",x"44",x"D1", -- 0x0550 + x"D5",x"83",x"C6",x"08",x"ED",x"44",x"E6",x"F8", -- 0x0558 + x"6F",x"26",x"00",x"29",x"29",x"7A",x"C6",x"08", -- 0x0560 + x"5F",x"CB",x"3B",x"CB",x"3B",x"CB",x"3B",x"16", -- 0x0568 + x"50",x"19",x"7E",x"D1",x"C9",x"F5",x"C5",x"DD", -- 0x0570 + x"36",x"03",x"00",x"DD",x"7E",x"05",x"DD",x"36", -- 0x0578 + x"05",x"38",x"DD",x"36",x"07",x"01",x"0E",x"05", -- 0x0580 + x"FE",x"15",x"28",x"02",x"0E",x"04",x"79",x"CD", -- 0x0588 + x"A8",x"09",x"3E",x"15",x"CD",x"DE",x"06",x"AF", -- 0x0590 + x"32",x"0C",x"40",x"C1",x"F1",x"C9",x"DD",x"7E", -- 0x0598 + x"00",x"B7",x"28",x"18",x"95",x"C6",x"08",x"E6", -- 0x05A0 + x"F0",x"C0",x"DD",x"7E",x"01",x"94",x"C6",x"08", -- 0x05A8 + x"E6",x"F0",x"C0",x"DD",x"7E",x"07",x"FE",x"01", -- 0x05B0 + x"28",x"02",x"BF",x"C9",x"F6",x"FF",x"C9",x"CD", -- 0x05B8 + x"45",x"05",x"7E",x"FE",x"10",x"C8",x"FE",x"0C", -- 0x05C0 + x"C8",x"E6",x"FD",x"FE",x"34",x"7E",x"C8",x"E6", -- 0x05C8 + x"F0",x"FE",x"E0",x"7E",x"C9",x"01",x"01",x"01", -- 0x05D0 + x"18",x"03",x"01",x"06",x"04",x"7E",x"1F",x"1F", -- 0x05D8 + x"1F",x"1F",x"CD",x"ED",x"05",x"7E",x"CD",x"ED", -- 0x05E0 + x"05",x"23",x"10",x"F1",x"C9",x"0D",x"E6",x"0F", -- 0x05E8 + x"20",x"08",x"CB",x"79",x"20",x"04",x"3E",x"10", -- 0x05F0 + x"18",x"02",x"0E",x"FF",x"FD",x"77",x"00",x"11", -- 0x05F8 + x"E0",x"FF",x"FD",x"19",x"C9",x"E5",x"D5",x"C5", -- 0x0600 + x"F5",x"E5",x"87",x"87",x"6F",x"26",x"00",x"11", -- 0x0608 + x"2A",x"06",x"19",x"D1",x"13",x"13",x"13",x"06", -- 0x0610 + x"04",x"AF",x"1A",x"8E",x"27",x"12",x"2B",x"1B", -- 0x0618 + x"10",x"F8",x"F1",x"C1",x"D1",x"E1",x"C9",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"10",x"00", -- 0x0628 + x"00",x"01",x"03",x"00",x"00",x"03",x"45",x"00", -- 0x0630 + x"00",x"05",x"34",x"00",x"00",x"09",x"25",x"00", -- 0x0638 + x"00",x"16",x"22",x"11",x"FF",x"FF",x"B7",x"ED", -- 0x0640 + x"5A",x"20",x"F8",x"21",x"00",x"40",x"34",x"C9", -- 0x0648 + x"3A",x"0D",x"40",x"DD",x"86",x"00",x"DD",x"77", -- 0x0650 + x"00",x"E6",x"F8",x"C0",x"DD",x"36",x"00",x"00", -- 0x0658 + x"C9",x"F5",x"E5",x"77",x"23",x"3C",x"77",x"D5", -- 0x0660 + x"11",x"1F",x"00",x"19",x"3C",x"77",x"3C",x"23", -- 0x0668 + x"77",x"D1",x"E1",x"F1",x"C9",x"F5",x"E5",x"D5", -- 0x0670 + x"36",x"10",x"23",x"36",x"10",x"11",x"1F",x"00", -- 0x0678 + x"19",x"36",x"10",x"23",x"36",x"10",x"18",x"E9", -- 0x0680 + x"E5",x"2A",x"01",x"40",x"ED",x"5F",x"8C",x"CE", -- 0x0688 + x"A7",x"67",x"8D",x"88",x"CE",x"86",x"6F",x"22", -- 0x0690 + x"01",x"40",x"E1",x"C9",x"CD",x"7B",x"00",x"21", -- 0x0698 + x"83",x"10",x"0E",x"AC",x"1E",x"00",x"46",x"04", -- 0x06A0 + x"C8",x"23",x"7E",x"23",x"05",x"32",x"00",x"78", -- 0x06A8 + x"E5",x"1C",x"7B",x"E6",x"03",x"20",x"0C",x"79", -- 0x06B0 + x"E6",x"01",x"32",x"05",x"68",x"CB",x"09",x"AF", -- 0x06B8 + x"32",x"05",x"68",x"21",x"13",x"40",x"7E",x"BE", -- 0x06C0 + x"28",x"FD",x"E1",x"10",x"E3",x"3E",x"FF",x"32", -- 0x06C8 + x"00",x"78",x"3A",x"00",x"78",x"3E",x"05",x"10", -- 0x06D0 + x"FE",x"3D",x"20",x"FB",x"18",x"C8",x"C5",x"4F", -- 0x06D8 + x"3A",x"10",x"40",x"B7",x"79",x"C1",x"C0",x"FD", -- 0x06E0 + x"E5",x"FD",x"21",x"3F",x"41",x"CD",x"F3",x"06", -- 0x06E8 + x"FD",x"E1",x"C9",x"FE",x"20",x"28",x"1D",x"FE", -- 0x06F0 + x"23",x"28",x"22",x"FE",x"06",x"28",x"1E",x"FE", -- 0x06F8 + x"15",x"28",x"23",x"FE",x"21",x"28",x"28",x"FE", -- 0x0700 + x"08",x"28",x"2D",x"FE",x"12",x"28",x"32",x"FE", -- 0x0708 + x"07",x"28",x"3C",x"C9",x"FD",x"CB",x"00",x"D6", -- 0x0710 + x"FD",x"36",x"04",x"78",x"C9",x"FD",x"CB",x"00", -- 0x0718 + x"CE",x"FD",x"36",x"03",x"14",x"C9",x"FD",x"CB", -- 0x0720 + x"00",x"C6",x"FD",x"36",x"02",x"32",x"C9",x"FD", -- 0x0728 + x"CB",x"00",x"E6",x"FD",x"36",x"06",x"64",x"C9", -- 0x0730 + x"FD",x"CB",x"00",x"EE",x"FD",x"36",x"07",x"C8", -- 0x0738 + x"C9",x"FD",x"CB",x"00",x"F6",x"FD",x"36",x"08", -- 0x0740 + x"64",x"3E",x"01",x"CD",x"8C",x"09",x"C9",x"FD", -- 0x0748 + x"CB",x"00",x"FE",x"CD",x"88",x"06",x"E6",x"07", -- 0x0750 + x"C6",x"08",x"FD",x"77",x"09",x"C9",x"F5",x"E5", -- 0x0758 + x"21",x"03",x"40",x"34",x"7E",x"E6",x"3E",x"3C", -- 0x0760 + x"6F",x"26",x"00",x"D5",x"11",x"8F",x"40",x"19", -- 0x0768 + x"D1",x"3A",x"03",x"40",x"E6",x"C0",x"0F",x"0F", -- 0x0770 + x"0F",x"0F",x"0F",x"77",x"E1",x"F1",x"C9",x"45", -- 0x0778 + x"53",x"50",x"52",x"45",x"53",x"53",x"40",x"53", -- 0x0780 + x"54",x"41",x"52",x"54",x"40",x"42",x"55",x"54", -- 0x0788 + x"54",x"4F",x"4E",x"24",x"C8",x"52",x"4F",x"4E", -- 0x0790 + x"45",x"40",x"50",x"4C",x"41",x"59",x"45",x"52", -- 0x0798 + x"24",x"4A",x"52",x"4F",x"4E",x"4C",x"59",x"24", -- 0x07A0 + x"FF",x"FF",x"2A",x"53",x"4F",x"52",x"40",x"54", -- 0x07A8 + x"57",x"4F",x"40",x"50",x"4C",x"41",x"59",x"45", -- 0x07B0 + x"52",x"24",x"FF",x"FF",x"44",x"52",x"5B",x"50", -- 0x07B8 + x"4C",x"41",x"59",x"5B",x"24",x"0C",x"53",x"46", -- 0x07C0 + x"4F",x"52",x"40",x"41",x"4D",x"55",x"53",x"45", -- 0x07C8 + x"4D",x"45",x"4E",x"54",x"40",x"4F",x"4E",x"4C", -- 0x07D0 + x"59",x"24",x"D3",x"52",x"5E",x"40",x"31",x"39", -- 0x07D8 + x"38",x"32",x"24",x"D5",x"52",x"4D",x"54",x"4D", -- 0x07E0 + x"40",x"47",x"41",x"4D",x"45",x"53",x"24",x"FF", -- 0x07E8 + x"FF",x"43",x"41",x"54",x"41",x"43",x"4F",x"4D", -- 0x07F0 + x"42",x"C9",x"C4",x"52",x"53",x"43",x"4F",x"52", -- 0x07F8 + x"45",x"40",x"54",x"41",x"42",x"4C",x"45",x"5B", -- 0x0800 + x"24",x"C8",x"52",x"95",x"40",x"3C",x"3C",x"3C", -- 0x0808 + x"40",x"39",x"32",x"35",x"24",x"CB",x"52",x"98", -- 0x0810 + x"40",x"3C",x"3C",x"3C",x"40",x"33",x"34",x"35", -- 0x0818 + x"24",x"CE",x"52",x"9C",x"40",x"3C",x"3C",x"3C", -- 0x0820 + x"40",x"35",x"33",x"34",x"24",x"FF",x"FF",x"8A", -- 0x0828 + x"52",x"50",x"4C",x"41",x"59",x"45",x"52",x"40", -- 0x0830 + x"4F",x"4E",x"45",x"24",x"FF",x"FF",x"8A",x"52", -- 0x0838 + x"50",x"4C",x"41",x"59",x"45",x"52",x"40",x"54", -- 0x0840 + x"57",x"4F",x"24",x"FF",x"FF",x"8C",x"52",x"47", -- 0x0848 + x"41",x"4D",x"45",x"40",x"4F",x"56",x"45",x"52", -- 0x0850 + x"24",x"FF",x"FF",x"7F",x"53",x"43",x"52",x"45", -- 0x0858 + x"44",x"49",x"54",x"53",x"5B",x"24",x"21",x"53", -- 0x0860 + x"31",x"40",x"55",x"50",x"24",x"01",x"52",x"48", -- 0x0868 + x"49",x"47",x"48",x"24",x"FF",x"FF",x"E1",x"50", -- 0x0870 + x"32",x"40",x"55",x"50",x"24",x"FF",x"FF",x"DD", -- 0x0878 + x"21",x"5B",x"08",x"CD",x"F0",x"01",x"3A",x"17", -- 0x0880 + x"40",x"FE",x"01",x"20",x"07",x"DD",x"21",x"76", -- 0x0888 + x"08",x"CD",x"F0",x"01",x"FD",x"21",x"A0",x"53", -- 0x0890 + x"21",x"2C",x"40",x"CD",x"DA",x"05",x"FD",x"21", -- 0x0898 + x"80",x"52",x"21",x"1D",x"40",x"CD",x"DA",x"05", -- 0x08A0 + x"21",x"1B",x"40",x"01",x"01",x"01",x"FD",x"21", -- 0x08A8 + x"7F",x"52",x"CD",x"DD",x"05",x"3A",x"1C",x"40", -- 0x08B0 + x"FE",x"50",x"3E",x"10",x"20",x"02",x"3E",x"2D", -- 0x08B8 + x"FD",x"77",x"00",x"3A",x"17",x"40",x"B7",x"C8", -- 0x08C0 + x"FD",x"21",x"60",x"51",x"21",x"33",x"40",x"CD", -- 0x08C8 + x"DA",x"05",x"C9",x"FD",x"21",x"3F",x"41",x"FD", -- 0x08D0 + x"34",x"01",x"AF",x"32",x"03",x"68",x"32",x"05", -- 0x08D8 + x"68",x"3E",x"FF",x"32",x"00",x"78",x"3A",x"10", -- 0x08E0 + x"40",x"B7",x"C0",x"FD",x"CB",x"00",x"46",x"C4", -- 0x08E8 + x"16",x"09",x"FD",x"CB",x"00",x"4E",x"C4",x"37", -- 0x08F0 + x"09",x"FD",x"CB",x"00",x"56",x"C4",x"4B",x"09", -- 0x08F8 + x"FD",x"CB",x"00",x"6E",x"C4",x"6C",x"09",x"FD", -- 0x0900 + x"CB",x"00",x"76",x"C4",x"83",x"09",x"FD",x"CB", -- 0x0908 + x"00",x"7E",x"C4",x"96",x"09",x"C9",x"FD",x"CB", -- 0x0910 + x"02",x"56",x"20",x"05",x"3E",x"01",x"32",x"03", -- 0x0918 + x"68",x"CD",x"88",x"06",x"E6",x"0F",x"20",x"06", -- 0x0920 + x"CD",x"88",x"06",x"32",x"00",x"78",x"FD",x"35", -- 0x0928 + x"02",x"C0",x"FD",x"CB",x"00",x"86",x"C9",x"FD", -- 0x0930 + x"CB",x"03",x"4E",x"20",x"05",x"3E",x"01",x"32", -- 0x0938 + x"05",x"68",x"FD",x"35",x"03",x"C0",x"FD",x"CB", -- 0x0940 + x"00",x"8E",x"C9",x"FD",x"CB",x"01",x"46",x"C0", -- 0x0948 + x"FD",x"7E",x"04",x"D6",x"04",x"FD",x"77",x"04", -- 0x0950 + x"FD",x"7E",x"04",x"32",x"00",x"78",x"F0",x"FD", -- 0x0958 + x"CB",x"00",x"96",x"3E",x"FF",x"32",x"00",x"78", -- 0x0960 + x"FD",x"77",x"04",x"C9",x"FD",x"7E",x"01",x"E6", -- 0x0968 + x"04",x"3E",x"FF",x"20",x"02",x"3E",x"80",x"32", -- 0x0970 + x"00",x"78",x"FD",x"35",x"07",x"C0",x"FD",x"CB", -- 0x0978 + x"00",x"AE",x"C9",x"FD",x"35",x"08",x"C0",x"FD", -- 0x0980 + x"CB",x"00",x"B6",x"AF",x"32",x"00",x"68",x"32", -- 0x0988 + x"01",x"68",x"32",x"02",x"68",x"C9",x"FD",x"7E", -- 0x0990 + x"09",x"87",x"87",x"87",x"32",x"00",x"78",x"FD", -- 0x0998 + x"35",x"09",x"C0",x"FD",x"CB",x"00",x"BE",x"C9", -- 0x09A0 + x"DD",x"E5",x"F5",x"C5",x"D5",x"E5",x"F5",x"3A", -- 0x09A8 + x"10",x"40",x"B7",x"20",x"3F",x"3A",x"0C",x"40", -- 0x09B0 + x"B7",x"CA",x"F4",x"09",x"2A",x"24",x"40",x"F1", -- 0x09B8 + x"E5",x"CD",x"05",x"06",x"E1",x"11",x"1D",x"40", -- 0x09C0 + x"CD",x"FC",x"09",x"DD",x"2A",x"24",x"40",x"DD", -- 0x09C8 + x"CB",x"06",x"46",x"20",x"1E",x"DD",x"7E",x"00", -- 0x09D0 + x"DD",x"B6",x"01",x"20",x"16",x"DD",x"7E",x"02", -- 0x09D8 + x"FE",x"50",x"38",x"0F",x"DD",x"CB",x"06",x"C6", -- 0x09E0 + x"DD",x"34",x"05",x"CD",x"05",x"0D",x"3E",x"08", -- 0x09E8 + x"CD",x"DE",x"06",x"F5",x"F1",x"E1",x"D1",x"C1", -- 0x09F0 + x"F1",x"DD",x"E1",x"C9",x"E5",x"D5",x"06",x"04", -- 0x09F8 + x"1A",x"BE",x"20",x"06",x"23",x"13",x"10",x"F8", -- 0x0A00 + x"18",x"08",x"30",x"06",x"7E",x"12",x"23",x"13", -- 0x0A08 + x"10",x"FA",x"D1",x"E1",x"C9",x"31",x"31",x"00", -- 0x0A10 + x"44",x"CD",x"A1",x"01",x"21",x"F7",x"0C",x"22", -- 0x0A18 + x"24",x"40",x"11",x"2C",x"40",x"01",x"0E",x"00", -- 0x0A20 + x"ED",x"B0",x"31",x"00",x"44",x"AF",x"32",x"18", -- 0x0A28 + x"40",x"32",x"05",x"40",x"CD",x"73",x"0A",x"CD", -- 0x0A30 + x"AB",x"0A",x"CD",x"B9",x"0A",x"3E",x"01",x"32", -- 0x0A38 + x"10",x"40",x"21",x"DC",x"05",x"22",x"11",x"40", -- 0x0A40 + x"21",x"00",x"20",x"22",x"26",x"40",x"CD",x"D4", -- 0x0A48 + x"0A",x"3E",x"07",x"32",x"21",x"40",x"CD",x"95", -- 0x0A50 + x"0C",x"21",x"01",x"00",x"CD",x"BC",x"0A",x"3A", -- 0x0A58 + x"0E",x"40",x"B7",x"28",x"C5",x"2A",x"11",x"40", -- 0x0A60 + x"2B",x"22",x"11",x"40",x"7C",x"B5",x"20",x"E1", -- 0x0A68 + x"C3",x"2A",x"0A",x"CD",x"BD",x"01",x"DD",x"21", -- 0x0A70 + x"BC",x"07",x"CD",x"F0",x"01",x"3A",x"E5",x"07", -- 0x0A78 + x"FE",x"4D",x"C2",x"00",x"00",x"21",x"07",x"53", -- 0x0A80 + x"11",x"F1",x"07",x"01",x"C0",x"FF",x"1A",x"13", -- 0x0A88 + x"D6",x"30",x"77",x"09",x"D9",x"21",x"1E",x"00", -- 0x0A90 + x"CD",x"BC",x"0A",x"CD",x"7B",x"00",x"D9",x"1A", -- 0x0A98 + x"FE",x"C9",x"20",x"EA",x"CD",x"B9",x"0A",x"CD", -- 0x0AA0 + x"B9",x"0A",x"C9",x"CD",x"BD",x"01",x"DD",x"21", -- 0x0AA8 + x"FA",x"07",x"CD",x"F0",x"01",x"CD",x"B9",x"0A", -- 0x0AB0 + x"C9",x"21",x"90",x"01",x"E5",x"3A",x"1B",x"40", -- 0x0AB8 + x"B7",x"C2",x"6B",x"0B",x"7D",x"E6",x"01",x"CC", -- 0x0AC0 + x"7B",x"00",x"C4",x"5E",x"07",x"E1",x"2B",x"7C", -- 0x0AC8 + x"B5",x"20",x"E9",x"C9",x"CD",x"BD",x"01",x"21", -- 0x0AD0 + x"E3",x"0C",x"11",x"3B",x"40",x"01",x"14",x"00", -- 0x0AD8 + x"ED",x"B0",x"21",x"96",x"0E",x"11",x"23",x"41", -- 0x0AE0 + x"01",x"1C",x"00",x"ED",x"B0",x"21",x"00",x"20", -- 0x0AE8 + x"22",x"26",x"40",x"21",x"9F",x"10",x"22",x"22", -- 0x0AF0 + x"40",x"CD",x"10",x"0B",x"AF",x"32",x"21",x"40", -- 0x0AF8 + x"3E",x"50",x"32",x"0E",x"40",x"3E",x"32",x"32", -- 0x0B00 + x"3A",x"40",x"3E",x"01",x"32",x"04",x"70",x"C9", -- 0x0B08 + x"21",x"F7",x"40",x"06",x"29",x"36",x"FF",x"23", -- 0x0B10 + x"10",x"FB",x"36",x"FE",x"C9",x"3A",x"00",x"40", -- 0x0B18 + x"E6",x"03",x"C0",x"DD",x"21",x"F7",x"40",x"06", -- 0x0B20 + x"14",x"DD",x"7E",x"01",x"FE",x"FF",x"28",x"34", -- 0x0B28 + x"DD",x"34",x"00",x"DD",x"6E",x"00",x"7D",x"E6", -- 0x0B30 + x"1F",x"FE",x"1C",x"28",x"23",x"DD",x"66",x"01", -- 0x0B38 + x"CB",x"46",x"28",x"06",x"DD",x"35",x"00",x"DD", -- 0x0B40 + x"6E",x"00",x"7E",x"E6",x"F0",x"FE",x"E0",x"20", -- 0x0B48 + x"0F",x"7E",x"C6",x"04",x"FE",x"F0",x"28",x"05", -- 0x0B50 + x"CD",x"61",x"06",x"18",x"07",x"CD",x"75",x"06", -- 0x0B58 + x"DD",x"36",x"01",x"FF",x"DD",x"23",x"DD",x"23", -- 0x0B60 + x"10",x"BF",x"C9",x"31",x"00",x"44",x"AF",x"32", -- 0x0B68 + x"10",x"40",x"CD",x"BD",x"01",x"DD",x"21",x"7F", -- 0x0B70 + x"07",x"CD",x"F0",x"01",x"3A",x"1B",x"40",x"FE", -- 0x0B78 + x"01",x"DD",x"21",x"AA",x"07",x"C4",x"F0",x"01", -- 0x0B80 + x"CD",x"7B",x"00",x"CD",x"94",x"08",x"DD",x"21", -- 0x0B88 + x"5B",x"10",x"CD",x"C4",x"0F",x"01",x"99",x"00", -- 0x0B90 + x"28",x"0F",x"3A",x"1B",x"40",x"FE",x"01",x"28", -- 0x0B98 + x"D4",x"CD",x"C4",x"0F",x"01",x"98",x"01",x"20", -- 0x0BA0 + x"CC",x"3A",x"1B",x"40",x"81",x"27",x"32",x"1B", -- 0x0BA8 + x"40",x"78",x"32",x"17",x"40",x"AF",x"32",x"18", -- 0x0BB0 + x"40",x"21",x"F7",x"0C",x"11",x"2C",x"40",x"01", -- 0x0BB8 + x"0E",x"00",x"ED",x"B0",x"DD",x"21",x"7F",x"10", -- 0x0BC0 + x"CD",x"C4",x"0F",x"CA",x"D6",x"0B",x"3E",x"05", -- 0x0BC8 + x"32",x"31",x"40",x"32",x"38",x"40",x"3A",x"18", -- 0x0BD0 + x"40",x"B7",x"DD",x"21",x"2C",x"40",x"28",x"04", -- 0x0BD8 + x"DD",x"21",x"33",x"40",x"DD",x"22",x"24",x"40", -- 0x0BE0 + x"DD",x"7E",x"05",x"B7",x"CA",x"20",x"0C",x"CD", -- 0x0BE8 + x"7E",x"0C",x"3A",x"17",x"40",x"B7",x"06",x"14", -- 0x0BF0 + x"28",x"02",x"06",x"64",x"CD",x"7B",x"00",x"10", -- 0x0BF8 + x"FB",x"DD",x"2A",x"24",x"40",x"DD",x"35",x"05", -- 0x0C00 + x"CD",x"D4",x"0A",x"CD",x"05",x"0D",x"CD",x"F7", -- 0x0C08 + x"0F",x"CD",x"25",x"10",x"CD",x"9C",x"06",x"CD", -- 0x0C10 + x"95",x"0C",x"3A",x"0E",x"40",x"B7",x"20",x"F7", -- 0x0C18 + x"DD",x"7E",x"05",x"B7",x"20",x"11",x"CD",x"7E", -- 0x0C20 + x"0C",x"DD",x"21",x"4D",x"08",x"CD",x"F0",x"01", -- 0x0C28 + x"06",x"96",x"CD",x"7B",x"00",x"10",x"FB",x"3A", -- 0x0C30 + x"17",x"40",x"B7",x"3A",x"31",x"40",x"21",x"38", -- 0x0C38 + x"40",x"28",x"01",x"B6",x"B7",x"CA",x"6A",x"0C", -- 0x0C40 + x"3A",x"17",x"40",x"B7",x"28",x"88",x"3A",x"18", -- 0x0C48 + x"40",x"EE",x"01",x"32",x"18",x"40",x"32",x"05", -- 0x0C50 + x"40",x"DD",x"21",x"7B",x"10",x"CD",x"C4",x"0F", -- 0x0C58 + x"CA",x"D6",x"0B",x"AF",x"32",x"05",x"40",x"C3", -- 0x0C60 + x"D6",x"0B",x"CD",x"BD",x"01",x"DD",x"21",x"4D", -- 0x0C68 + x"08",x"CD",x"F0",x"01",x"06",x"64",x"CD",x"7B", -- 0x0C70 + x"00",x"10",x"FB",x"C3",x"2A",x"0A",x"CD",x"BD", -- 0x0C78 + x"01",x"3A",x"18",x"40",x"B7",x"DD",x"21",x"2F", -- 0x0C80 + x"08",x"28",x"04",x"DD",x"21",x"3E",x"08",x"CD", -- 0x0C88 + x"F0",x"01",x"C9",x"ED",x"4B",x"CD",x"7B",x"00", -- 0x0C90 + x"21",x"00",x"40",x"34",x"CD",x"1E",x"0D",x"CD", -- 0x0C98 + x"7F",x"0D",x"CD",x"B3",x"0E",x"CD",x"0F",x"03", -- 0x0CA0 + x"CD",x"1E",x"02",x"CD",x"6E",x"0F",x"3A",x"00", -- 0x0CA8 + x"40",x"E6",x"01",x"CC",x"94",x"08",x"CD",x"1D", -- 0x0CB0 + x"0B",x"3A",x"42",x"40",x"21",x"4C",x"40",x"BE", -- 0x0CB8 + x"28",x"16",x"DD",x"21",x"3B",x"40",x"CD",x"75", -- 0x0CC0 + x"05",x"DD",x"21",x"45",x"40",x"DD",x"7E",x"01", -- 0x0CC8 + x"D6",x"09",x"DD",x"77",x"01",x"CD",x"75",x"05", -- 0x0CD0 + x"21",x"0E",x"40",x"3A",x"42",x"40",x"B7",x"28", -- 0x0CD8 + x"01",x"35",x"C9",x"80",x"BE",x"00",x"00",x"04", -- 0x0CE0 + x"16",x"00",x"00",x"00",x"00",x"80",x"CE",x"00", -- 0x0CE8 + x"00",x"04",x"17",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 + x"00",x"00",x"00",x"00",x"03",x"00",x"00",x"00", -- 0x0CF8 + x"00",x"00",x"00",x"03",x"00",x"DD",x"2A",x"24", -- 0x0D00 + x"40",x"21",x"DE",x"51",x"DD",x"4E",x"05",x"79", -- 0x0D08 + x"B7",x"C8",x"0D",x"3E",x"30",x"CD",x"61",x"06", -- 0x0D10 + x"11",x"C0",x"FF",x"19",x"18",x"F1",x"3A",x"00", -- 0x0D18 + x"40",x"E6",x"03",x"C0",x"CD",x"5E",x"07",x"CD", -- 0x0D20 + x"5E",x"07",x"21",x"1C",x"50",x"3E",x"20",x"11", -- 0x0D28 + x"1D",x"50",x"01",x"1B",x"00",x"ED",x"B8",x"01", -- 0x0D30 + x"3B",x"00",x"09",x"EB",x"09",x"EB",x"3D",x"20", -- 0x0D38 + x"F1",x"CD",x"C5",x"0D",x"3E",x"C0",x"32",x"42", -- 0x0D40 + x"50",x"32",x"A2",x"53",x"3A",x"21",x"40",x"CB", -- 0x0D48 + x"47",x"C8",x"CD",x"88",x"06",x"E6",x"03",x"C0", -- 0x0D50 + x"CD",x"88",x"06",x"5F",x"16",x"10",x"CD",x"45", -- 0x0D58 + x"05",x"CD",x"B4",x"0D",x"C0",x"CD",x"88",x"06", -- 0x0D60 + x"E6",x"01",x"3E",x"70",x"28",x"02",x"3E",x"60", -- 0x0D68 + x"4F",x"CD",x"88",x"06",x"E6",x"07",x"79",x"20", -- 0x0D70 + x"02",x"3E",x"6C",x"CD",x"61",x"06",x"C9",x"3A", -- 0x0D78 + x"21",x"40",x"CB",x"67",x"C8",x"3A",x"00",x"40", -- 0x0D80 + x"E6",x"1F",x"C0",x"21",x"C3",x"50",x"CD",x"88", -- 0x0D88 + x"06",x"E6",x"01",x"20",x"03",x"21",x"E3",x"50", -- 0x0D90 + x"06",x"06",x"CD",x"B4",x"0D",x"20",x"0E",x"CD", -- 0x0D98 + x"88",x"06",x"E6",x"07",x"3E",x"68",x"28",x"02", -- 0x0DA0 + x"3E",x"64",x"CD",x"61",x"06",x"11",x"80",x"00", -- 0x0DA8 + x"19",x"10",x"E7",x"C9",x"E5",x"7E",x"23",x"B6", -- 0x0DB0 + x"C5",x"01",x"20",x"00",x"09",x"C1",x"B6",x"2B", -- 0x0DB8 + x"B6",x"FE",x"10",x"E1",x"C9",x"21",x"02",x"50", -- 0x0DC0 + x"06",x"20",x"11",x"20",x"00",x"36",x"10",x"19", -- 0x0DC8 + x"10",x"FB",x"2A",x"26",x"40",x"7E",x"FE",x"FE", -- 0x0DD0 + x"DD",x"2A",x"24",x"40",x"20",x"1C",x"3A",x"1E", -- 0x0DD8 + x"53",x"EE",x"1C",x"32",x"1E",x"53",x"E5",x"21", -- 0x0DE0 + x"96",x"0E",x"11",x"23",x"41",x"01",x"1C",x"00", -- 0x0DE8 + x"ED",x"B0",x"DD",x"34",x"04",x"CD",x"F7",x"0F", -- 0x0DF0 + x"E1",x"23",x"7E",x"3C",x"20",x"03",x"21",x"00", -- 0x0DF8 + x"20",x"4E",x"23",x"22",x"26",x"40",x"DD",x"21", -- 0x0E00 + x"23",x"41",x"06",x"04",x"C5",x"DD",x"7E",x"03", -- 0x0E08 + x"A1",x"2E",x"00",x"11",x"00",x"00",x"28",x"04", -- 0x0E10 + x"2C",x"11",x"20",x"00",x"DD",x"7E",x"04",x"A1", -- 0x0E18 + x"28",x"05",x"2E",x"02",x"11",x"E0",x"FF",x"DD", -- 0x0E20 + x"75",x"02",x"DD",x"6E",x"00",x"DD",x"66",x"01", -- 0x0E28 + x"19",x"DD",x"75",x"00",x"DD",x"74",x"01",x"DD", -- 0x0E30 + x"6E",x"05",x"DD",x"66",x"06",x"DD",x"5E",x"00", -- 0x0E38 + x"DD",x"56",x"01",x"B7",x"ED",x"52",x"28",x"3D", -- 0x0E40 + x"01",x"E0",x"FF",x"CB",x"7C",x"28",x"03",x"01", -- 0x0E48 + x"20",x"00",x"F5",x"E5",x"2A",x"22",x"40",x"23", -- 0x0E50 + x"7E",x"C6",x"C0",x"E1",x"19",x"77",x"22",x"29", -- 0x0E58 + x"40",x"09",x"B7",x"ED",x"52",x"20",x"F5",x"19", -- 0x0E60 + x"F1",x"E5",x"DD",x"7E",x"02",x"28",x"02",x"C6", -- 0x0E68 + x"03",x"6F",x"26",x"00",x"11",x"90",x"0E",x"19", -- 0x0E70 + x"5E",x"E1",x"7B",x"E6",x"FD",x"FE",x"6D",x"20", -- 0x0E78 + x"03",x"2A",x"29",x"40",x"73",x"C1",x"11",x"07", -- 0x0E80 + x"00",x"DD",x"19",x"05",x"C2",x"0C",x"0E",x"C9", -- 0x0E88 + x"34",x"6C",x"6D",x"36",x"6F",x"6E",x"82",x"53", -- 0x0E90 + x"00",x"80",x"40",x"82",x"53",x"02",x"52",x"00", -- 0x0E98 + x"20",x"10",x"02",x"52",x"E2",x"51",x"00",x"08", -- 0x0EA0 + x"04",x"E2",x"51",x"62",x"50",x"00",x"02",x"01", -- 0x0EA8 + x"62",x"50",x"01",x"3A",x"10",x"40",x"B7",x"C2", -- 0x0EB0 + x"31",x"0F",x"3A",x"42",x"40",x"B7",x"C0",x"FD", -- 0x0EB8 + x"21",x"3B",x"40",x"DD",x"21",x"47",x"10",x"AF", -- 0x0EC0 + x"FD",x"77",x"02",x"FD",x"77",x"03",x"CD",x"C4", -- 0x0EC8 + x"0F",x"CC",x"E7",x"0E",x"CD",x"C4",x"0F",x"CC", -- 0x0ED0 + x"F4",x"0E",x"3A",x"3D",x"40",x"32",x"47",x"40", -- 0x0ED8 + x"CD",x"C4",x"0F",x"C4",x"01",x"0F",x"C9",x"FD", -- 0x0EE0 + x"7E",x"00",x"E6",x"FE",x"FE",x"18",x"C8",x"FD", -- 0x0EE8 + x"36",x"02",x"FE",x"C9",x"FD",x"7E",x"00",x"E6", -- 0x0EF0 + x"FE",x"FE",x"D8",x"C8",x"FD",x"36",x"02",x"02", -- 0x0EF8 + x"C9",x"DD",x"21",x"CF",x"40",x"06",x"02",x"11", -- 0x0F00 + x"05",x"00",x"CD",x"DF",x"04",x"C0",x"ED",x"5B", -- 0x0F08 + x"3B",x"40",x"1D",x"1D",x"DD",x"73",x"00",x"7A", -- 0x0F10 + x"D6",x"10",x"DD",x"77",x"01",x"3A",x"3D",x"40", -- 0x0F18 + x"DD",x"77",x"02",x"DD",x"36",x"03",x"FA",x"DD", -- 0x0F20 + x"36",x"04",x"01",x"3E",x"06",x"CD",x"DE",x"06", -- 0x0F28 + x"C9",x"CD",x"88",x"06",x"E6",x"1F",x"CC",x"01", -- 0x0F30 + x"0F",x"DD",x"21",x"3B",x"40",x"3A",x"3D",x"40", -- 0x0F38 + x"32",x"47",x"40",x"3A",x"3B",x"40",x"0E",x"FF", -- 0x0F40 + x"FE",x"C0",x"30",x"14",x"0E",x"01",x"FE",x"40", -- 0x0F48 + x"38",x"0E",x"CD",x"88",x"06",x"E6",x"3F",x"20", -- 0x0F50 + x"0B",x"CD",x"88",x"06",x"E6",x"02",x"3D",x"4F", -- 0x0F58 + x"79",x"32",x"3D",x"40",x"CD",x"9F",x"04",x"3A", -- 0x0F60 + x"3D",x"40",x"32",x"47",x"40",x"C9",x"CD",x"88", -- 0x0F68 + x"06",x"E6",x"3F",x"C0",x"21",x"21",x"40",x"CB", -- 0x0F70 + x"4E",x"C8",x"0E",x"01",x"CB",x"56",x"28",x"02", -- 0x0F78 + x"0E",x"03",x"3A",x"28",x"40",x"B9",x"D0",x"CD", -- 0x0F80 + x"8B",x"0F",x"C9",x"DD",x"21",x"4F",x"40",x"06", -- 0x0F88 + x"06",x"11",x"0A",x"00",x"CD",x"DF",x"04",x"C0", -- 0x0F90 + x"3E",x"12",x"CD",x"DE",x"06",x"CD",x"88",x"06", -- 0x0F98 + x"E6",x"7F",x"C6",x"40",x"5F",x"16",x"28",x"CD", -- 0x0FA0 + x"BF",x"05",x"20",x"F1",x"EB",x"11",x"01",x"01", -- 0x0FA8 + x"01",x"00",x"15",x"CD",x"88",x"06",x"E6",x"07", -- 0x0FB0 + x"4F",x"D9",x"21",x"00",x"02",x"11",x"00",x"00", -- 0x0FB8 + x"D9",x"C3",x"F6",x"04",x"D5",x"E5",x"DD",x"E5", -- 0x0FC0 + x"3A",x"18",x"40",x"B7",x"28",x"04",x"DD",x"23", -- 0x0FC8 + x"DD",x"23",x"DD",x"66",x"00",x"CB",x"7C",x"20", -- 0x0FD0 + x"11",x"2E",x"00",x"7E",x"2F",x"DD",x"A6",x"01", -- 0x0FD8 + x"DD",x"E1",x"11",x"04",x"00",x"DD",x"19",x"E1", -- 0x0FE0 + x"D1",x"C9",x"7C",x"E6",x"7F",x"6F",x"26",x"00", -- 0x0FE8 + x"11",x"09",x"40",x"19",x"7E",x"18",x"E6",x"F5", -- 0x0FF0 + x"D5",x"E5",x"DD",x"E5",x"DD",x"2A",x"24",x"40", -- 0x0FF8 + x"DD",x"7E",x"04",x"FE",x"08",x"20",x"04",x"DD", -- 0x1000 + x"36",x"04",x"07",x"DD",x"7E",x"04",x"E6",x"07", -- 0x1008 + x"6F",x"26",x"00",x"11",x"9F",x"10",x"29",x"19", -- 0x1010 + x"7E",x"32",x"21",x"40",x"22",x"22",x"40",x"DD", -- 0x1018 + x"E1",x"E1",x"D1",x"F1",x"C9",x"DD",x"2A",x"24", -- 0x1020 + x"40",x"DD",x"7E",x"04",x"E6",x"07",x"21",x"00", -- 0x1028 + x"20",x"4F",x"22",x"26",x"40",x"0D",x"F8",x"7E", -- 0x1030 + x"FE",x"FF",x"20",x"03",x"21",x"00",x"20",x"7E", -- 0x1038 + x"FE",x"FE",x"23",x"20",x"F2",x"18",x"EB",x"60", -- 0x1040 + x"04",x"68",x"04",x"60",x"08",x"68",x"08",x"80", -- 0x1048 + x"10",x"81",x"10",x"60",x"80",x"60",x"40",x"60", -- 0x1050 + x"20",x"61",x"20",x"68",x"01",x"68",x"01",x"68", -- 0x1058 + x"02",x"68",x"02",x"80",x"01",x"80",x"01",x"80", -- 0x1060 + x"02",x"80",x"02",x"50",x"00",x"00",x"03",x"00", -- 0x1068 + x"01",x"00",x"03",x"50",x"00",x"00",x"05",x"00", -- 0x1070 + x"01",x"00",x"05",x"70",x"08",x"70",x"08",x"70", -- 0x1078 + x"04",x"70",x"04",x"14",x"FF",x"0A",x"10",x"05", -- 0x1080 + x"00",x"0A",x"20",x"05",x"00",x"0A",x"30",x"05", -- 0x1088 + x"00",x"28",x"30",x"05",x"20",x"05",x"10",x"28", -- 0x1090 + x"00",x"14",x"FF",x"0A",x"E0",x"FF",x"FF",x"E2", -- 0x1098 + x"00",x"E1",x"01",x"EB",x"02",x"FB",x"03",x"EF", -- 0x10A0 + x"00",x"FF",x"00",x"ED",x"00",x"EE",x"00",x"FF", -- 0x10A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x10F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1100 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1108 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1110 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1118 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1120 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1128 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1130 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1138 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1140 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1148 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1150 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1158 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1160 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1168 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1170 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1178 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1180 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1188 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1190 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1198 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x11C8 + 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x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1658 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1660 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1668 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1670 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1678 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1680 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1688 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1690 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1698 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x16F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1700 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1708 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1710 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1718 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1720 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1728 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1730 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1738 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1740 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1748 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1750 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1758 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1760 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1768 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1770 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1778 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1780 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1788 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1790 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1798 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x17F8 + x"DD",x"7E",x"04",x"FE",x"08",x"20",x"04",x"DD", -- 0x1800 + x"36",x"04",x"07",x"DD",x"7E",x"04",x"E6",x"07", -- 0x1808 + x"6F",x"26",x"00",x"11",x"9F",x"10",x"29",x"19", -- 0x1810 + x"7E",x"32",x"21",x"40",x"22",x"22",x"40",x"DD", -- 0x1818 + x"E1",x"E1",x"D1",x"F1",x"C9",x"DD",x"2A",x"24", -- 0x1820 + x"40",x"DD",x"7E",x"04",x"E6",x"07",x"21",x"00", -- 0x1828 + x"20",x"4F",x"22",x"26",x"40",x"0D",x"F8",x"7E", -- 0x1830 + x"FE",x"FF",x"20",x"03",x"21",x"00",x"20",x"7E", -- 0x1838 + x"FE",x"FE",x"23",x"20",x"F2",x"18",x"EB",x"60", -- 0x1840 + x"04",x"68",x"04",x"60",x"08",x"68",x"08",x"80", -- 0x1848 + x"10",x"81",x"10",x"60",x"80",x"60",x"40",x"60", -- 0x1850 + x"20",x"61",x"20",x"68",x"01",x"68",x"01",x"68", -- 0x1858 + x"02",x"68",x"02",x"80",x"01",x"80",x"01",x"80", -- 0x1860 + x"02",x"80",x"02",x"50",x"00",x"00",x"03",x"00", -- 0x1868 + x"01",x"00",x"03",x"50",x"00",x"00",x"05",x"00", -- 0x1870 + x"01",x"00",x"05",x"70",x"08",x"70",x"08",x"70", -- 0x1878 + x"04",x"70",x"04",x"14",x"FF",x"0A",x"10",x"05", -- 0x1880 + x"00",x"0A",x"20",x"05",x"00",x"0A",x"30",x"05", -- 0x1888 + x"00",x"28",x"30",x"05",x"20",x"05",x"10",x"28", -- 0x1890 + x"00",x"14",x"FF",x"0A",x"E0",x"FF",x"FF",x"E2", -- 0x1898 + x"00",x"E1",x"01",x"EB",x"02",x"FB",x"03",x"EF", -- 0x18A0 + x"00",x"FF",x"00",x"ED",x"00",x"EE",x"00",x"FF", -- 0x18A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x18F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1900 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1908 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1910 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1918 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1920 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1928 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1930 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1938 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1940 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1948 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1950 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1958 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1960 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1968 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1970 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1978 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1980 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1988 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1990 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1998 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x19F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1A98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1AF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1B98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1BF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1C98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1CF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1D98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1DF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FF8 + x"00",x"42",x"42",x"42",x"02",x"00",x"00",x"00", -- 0x2000 + x"02",x"02",x"02",x"02",x"02",x"40",x"41",x"41", -- 0x2008 + x"00",x"41",x"41",x"01",x"01",x"01",x"41",x"40", -- 0x2010 + x"40",x"40",x"02",x"82",x"82",x"80",x"80",x"80", -- 0x2018 + x"81",x"80",x"80",x"80",x"81",x"80",x"24",x"24", -- 0x2020 + x"00",x"24",x"21",x"20",x"01",x"81",x"00",x"00", -- 0x2028 + x"42",x"02",x"10",x"12",x"42",x"04",x"12",x"00", -- 0x2030 + x"40",x"68",x"18",x"00",x"00",x"00",x"6A",x"10", -- 0x2038 + x"00",x"5A",x"90",x"00",x"00",x"00",x"00",x"00", -- 0x2040 + x"80",x"01",x"80",x"00",x"00",x"00",x"00",x"40", -- 0x2048 + x"42",x"00",x"02",x"40",x"42",x"40",x"02",x"00", -- 0x2050 + x"40",x"02",x"00",x"40",x"01",x"01",x"41",x"00", -- 0x2058 + x"00",x"81",x"82",x"80",x"82",x"80",x"81",x"00", -- 0x2060 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x2068 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x2070 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x2078 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x2080 + x"FE",x"00",x"42",x"42",x"42",x"02",x"00",x"00", -- 0x2088 + x"00",x"02",x"02",x"02",x"02",x"02",x"40",x"41", -- 0x2090 + x"41",x"00",x"41",x"41",x"01",x"01",x"01",x"41", -- 0x2098 + x"40",x"40",x"40",x"02",x"82",x"82",x"80",x"80", -- 0x20A0 + x"80",x"81",x"80",x"80",x"80",x"81",x"80",x"00", -- 0x20A8 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x20B0 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x20B8 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x20C0 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x20C8 + x"FE",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x20D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x20D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x20E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x20E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x20F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x20F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x2100 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x2108 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x2110 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x2118 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x2120 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x2128 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x2130 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x2138 + x"00",x"FE",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21C8 + x"00",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x21D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x21D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x21E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x21E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x21F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x21F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x2200 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x2208 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x2210 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x2218 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x2220 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x2228 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x2230 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x2238 + x"00",x"FE",x"FF",x"FE",x"FF",x"FE",x"FF",x"FE", -- 0x2240 + x"00",x"00",x"00",x"00",x"FE",x"FF",x"FF",x"FF", -- 0x2248 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2250 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2258 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2260 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2268 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2270 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2278 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2280 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2288 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2290 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2298 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x22F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2300 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2308 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2310 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2318 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2320 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2328 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2330 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2338 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2340 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2348 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2350 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2358 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2360 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2368 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2370 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2378 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2380 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2388 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2390 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2398 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x23F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2400 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2408 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2410 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2418 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2420 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2428 + x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2430 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2438 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2440 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2448 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2450 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2458 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2460 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2468 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2470 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2478 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2480 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2488 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2490 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2498 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x24F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2500 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2508 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2510 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2518 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2520 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2528 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2530 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2538 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2540 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2548 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2550 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2558 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2560 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2568 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2570 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2578 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2580 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2588 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2590 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2598 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x25F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2600 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2608 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2610 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2618 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2620 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2628 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2630 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2638 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2640 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2648 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2658 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2660 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2668 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2670 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2678 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2680 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2688 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2690 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2698 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x26F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2700 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2708 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2710 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2718 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2720 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2728 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2730 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2738 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2740 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2748 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2750 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2758 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2760 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2768 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2770 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2778 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2780 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2788 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2790 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2798 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x27F8 + x"00",x"42",x"42",x"42",x"02",x"00",x"00",x"00", -- 0x2800 + x"02",x"02",x"02",x"02",x"02",x"40",x"41",x"41", -- 0x2808 + x"00",x"41",x"41",x"01",x"01",x"01",x"41",x"40", -- 0x2810 + x"40",x"40",x"02",x"82",x"82",x"80",x"80",x"80", -- 0x2818 + x"81",x"80",x"80",x"80",x"81",x"80",x"24",x"24", -- 0x2820 + x"00",x"24",x"21",x"20",x"01",x"81",x"00",x"00", -- 0x2828 + x"42",x"02",x"10",x"12",x"42",x"04",x"12",x"00", -- 0x2830 + x"40",x"68",x"18",x"00",x"00",x"00",x"6A",x"10", -- 0x2838 + x"00",x"5A",x"90",x"00",x"00",x"00",x"00",x"00", -- 0x2840 + x"80",x"01",x"80",x"00",x"00",x"00",x"00",x"40", -- 0x2848 + x"42",x"00",x"02",x"40",x"42",x"40",x"02",x"00", -- 0x2850 + x"40",x"02",x"00",x"40",x"01",x"01",x"41",x"00", -- 0x2858 + x"00",x"81",x"82",x"80",x"82",x"80",x"81",x"00", -- 0x2860 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x2868 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x2870 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x2878 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x2880 + x"FE",x"00",x"42",x"42",x"42",x"02",x"00",x"00", -- 0x2888 + x"00",x"02",x"02",x"02",x"02",x"02",x"40",x"41", -- 0x2890 + x"41",x"00",x"41",x"41",x"01",x"01",x"01",x"41", -- 0x2898 + x"40",x"40",x"40",x"02",x"82",x"82",x"80",x"80", -- 0x28A0 + x"80",x"81",x"80",x"80",x"80",x"81",x"80",x"00", -- 0x28A8 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x28B0 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x28B8 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x28C0 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x28C8 + x"FE",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x28D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x28D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x28E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x28E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x28F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x28F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x2900 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x2908 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x2910 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x2918 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x2920 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x2928 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x2930 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x2938 + x"00",x"FE",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C8 + x"00",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x29D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x29D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x29E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x29E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x29F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x29F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x2A00 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x2A08 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x2A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x2A18 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x2A20 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x2A28 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x2A30 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x2A38 + x"00",x"FE",x"FF",x"FE",x"FF",x"FE",x"FF",x"FE", -- 0x2A40 + x"00",x"00",x"00",x"00",x"FE",x"FF",x"FF",x"FF", -- 0x2A48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C28 + x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF8 + x"00",x"42",x"42",x"42",x"02",x"00",x"00",x"00", -- 0x3000 + x"02",x"02",x"02",x"02",x"02",x"40",x"41",x"41", -- 0x3008 + x"00",x"41",x"41",x"01",x"01",x"01",x"41",x"40", -- 0x3010 + x"40",x"40",x"02",x"82",x"82",x"80",x"80",x"80", -- 0x3018 + x"81",x"80",x"80",x"80",x"81",x"80",x"24",x"24", -- 0x3020 + x"00",x"24",x"21",x"20",x"01",x"81",x"00",x"00", -- 0x3028 + x"42",x"02",x"10",x"12",x"42",x"04",x"12",x"00", -- 0x3030 + x"40",x"68",x"18",x"00",x"00",x"00",x"6A",x"10", -- 0x3038 + x"00",x"5A",x"90",x"00",x"00",x"00",x"00",x"00", -- 0x3040 + x"80",x"01",x"80",x"00",x"00",x"00",x"00",x"40", -- 0x3048 + x"42",x"00",x"02",x"40",x"42",x"40",x"02",x"00", -- 0x3050 + x"40",x"02",x"00",x"40",x"01",x"01",x"41",x"00", -- 0x3058 + x"00",x"81",x"82",x"80",x"82",x"80",x"81",x"00", -- 0x3060 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x3068 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x3070 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x3078 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x3080 + x"FE",x"00",x"42",x"42",x"42",x"02",x"00",x"00", -- 0x3088 + x"00",x"02",x"02",x"02",x"02",x"02",x"40",x"41", -- 0x3090 + x"41",x"00",x"41",x"41",x"01",x"01",x"01",x"41", -- 0x3098 + x"40",x"40",x"40",x"02",x"82",x"82",x"80",x"80", -- 0x30A0 + x"80",x"81",x"80",x"80",x"80",x"81",x"80",x"00", -- 0x30A8 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x30B0 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x30B8 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x30C0 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x30C8 + x"FE",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x30D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x30D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x30E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x30E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x30F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x30F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x3100 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x3108 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x3110 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x3118 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x3120 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x3128 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x3130 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x3138 + x"00",x"FE",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C8 + x"00",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x31D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x31D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x31E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x31E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x31F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x31F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x3200 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x3208 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x3210 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x3218 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x3220 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x3228 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x3230 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x3238 + x"00",x"FE",x"FF",x"FE",x"FF",x"FE",x"FF",x"FE", -- 0x3240 + x"00",x"00",x"00",x"00",x"FE",x"FF",x"FF",x"FF", -- 0x3248 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3250 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3258 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3260 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3268 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3270 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3278 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3280 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3288 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3290 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3298 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x32F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3300 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3308 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3310 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3318 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3320 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3328 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3330 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3338 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3340 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3348 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3350 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3358 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3360 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3368 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3370 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3378 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3380 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3388 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3390 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3398 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x33F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3400 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3408 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3410 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3418 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3420 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3428 + x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3430 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3438 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3440 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3448 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3450 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3458 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3460 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3468 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3470 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3478 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3480 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3488 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3490 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3498 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x34F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3500 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3508 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3510 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3518 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3520 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3528 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3530 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3538 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3540 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3548 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3550 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3558 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3560 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3568 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3570 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3578 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3580 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3588 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3590 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3598 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3600 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3608 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3610 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3618 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3620 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3628 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3630 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3638 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3640 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3648 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3658 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3660 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3668 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3670 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3678 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3680 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3688 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3690 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3698 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3700 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3708 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3710 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3718 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3720 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3728 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3730 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3738 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3740 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3748 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3750 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3758 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3760 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3768 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3770 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3778 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3780 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3788 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3790 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3798 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37F8 + x"00",x"42",x"42",x"42",x"02",x"00",x"00",x"00", -- 0x3800 + x"02",x"02",x"02",x"02",x"02",x"40",x"41",x"41", -- 0x3808 + x"00",x"41",x"41",x"01",x"01",x"01",x"41",x"40", -- 0x3810 + x"40",x"40",x"02",x"82",x"82",x"80",x"80",x"80", -- 0x3818 + x"81",x"80",x"80",x"80",x"81",x"80",x"24",x"24", -- 0x3820 + x"00",x"24",x"21",x"20",x"01",x"81",x"00",x"00", -- 0x3828 + x"42",x"02",x"10",x"12",x"42",x"04",x"12",x"00", -- 0x3830 + x"40",x"68",x"18",x"00",x"00",x"00",x"6A",x"10", -- 0x3838 + x"00",x"5A",x"90",x"00",x"00",x"00",x"00",x"00", -- 0x3840 + x"80",x"01",x"80",x"00",x"00",x"00",x"00",x"40", -- 0x3848 + x"42",x"00",x"02",x"40",x"42",x"40",x"02",x"00", -- 0x3850 + x"40",x"02",x"00",x"40",x"01",x"01",x"41",x"00", -- 0x3858 + x"00",x"81",x"82",x"80",x"82",x"80",x"81",x"00", -- 0x3860 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x3868 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x3870 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x3878 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x3880 + x"FE",x"00",x"42",x"42",x"42",x"02",x"00",x"00", -- 0x3888 + x"00",x"02",x"02",x"02",x"02",x"02",x"40",x"41", -- 0x3890 + x"41",x"00",x"41",x"41",x"01",x"01",x"01",x"41", -- 0x3898 + x"40",x"40",x"40",x"02",x"82",x"82",x"80",x"80", -- 0x38A0 + x"80",x"81",x"80",x"80",x"80",x"81",x"80",x"00", -- 0x38A8 + x"82",x"00",x"80",x"24",x"A4",x"01",x"81",x"04", -- 0x38B0 + x"04",x"11",x"04",x"05",x"04",x"11",x"28",x"60", -- 0x38B8 + x"28",x"58",x"10",x"A4",x"00",x"40",x"10",x"1A", -- 0x38C0 + x"40",x"00",x"08",x"88",x"AA",x"98",x"01",x"80", -- 0x38C8 + x"FE",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x38D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x38D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x38E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x38E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x38F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x38F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x3900 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x3908 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x3910 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x3918 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x3920 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x3928 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x3930 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x3938 + x"00",x"FE",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C8 + x"00",x"24",x"24",x"00",x"24",x"21",x"20",x"01", -- 0x39D0 + x"81",x"00",x"00",x"42",x"02",x"10",x"12",x"42", -- 0x39D8 + x"04",x"12",x"00",x"40",x"68",x"18",x"00",x"00", -- 0x39E0 + x"00",x"6A",x"10",x"50",x"5A",x"80",x"00",x"42", -- 0x39E8 + x"42",x"42",x"02",x"00",x"00",x"00",x"02",x"02", -- 0x39F0 + x"02",x"02",x"02",x"40",x"41",x"41",x"00",x"41", -- 0x39F8 + x"41",x"01",x"01",x"01",x"41",x"40",x"40",x"40", -- 0x3A00 + x"02",x"82",x"82",x"80",x"80",x"80",x"81",x"80", -- 0x3A08 + x"80",x"80",x"81",x"80",x"00",x"00",x"00",x"00", -- 0x3A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"01", -- 0x3A18 + x"80",x"00",x"00",x"00",x"00",x"40",x"42",x"00", -- 0x3A20 + x"02",x"40",x"42",x"40",x"02",x"00",x"40",x"02", -- 0x3A28 + x"00",x"40",x"01",x"01",x"41",x"00",x"00",x"81", -- 0x3A30 + x"82",x"80",x"82",x"80",x"81",x"00",x"00",x"00", -- 0x3A38 + x"00",x"FE",x"FF",x"FE",x"FF",x"FE",x"FF",x"FE", -- 0x3A40 + x"00",x"00",x"00",x"00",x"FE",x"FF",x"FF",x"FF", -- 0x3A48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3A98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3AF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3B98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3BF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C28 + x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3C98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3CF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/build_id.v new file mode 100644 index 00000000..d4de7b4b --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180108" +`define BUILD_TIME "213440" diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..08fc21b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + +-- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..5a4d0094 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..87a5b3b1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..d06e75ad --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1H VID-Rom + k_rom : entity work.GALAXIAN_1H + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + + -- 1K VID-Rom + h_rom : entity work.GALAXIAN_1K + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/Catacomb_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.qpf b/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.qpf new file mode 100644 index 00000000..a6d5b3bc --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "Galaxian" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.qsf b/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.qsf new file mode 100644 index 00000000..d789a9f3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaxian_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian.sv +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Galaxian +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.srf b/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.srf new file mode 100644 index 00000000..14cddd5e --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/Galaxian.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/README.txt b/Arcade/Galaxian Hardware/Galaxian_MiST/README.txt new file mode 100644 index 00000000..2d3e4abb --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Galaxian port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/Release/Galaxian.rbf b/Arcade/Galaxian Hardware/Galaxian_MiST/Release/Galaxian.rbf new file mode 100644 index 00000000..e2c1c682 Binary files /dev/null and b/Arcade/Galaxian Hardware/Galaxian_MiST/Release/Galaxian.rbf differ diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/clean.bat b/Arcade/Galaxian Hardware/Galaxian_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/Galaxian.sv b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/Galaxian.sv new file mode 100644 index 00000000..3d264181 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/Galaxian.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Galaxian +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Galaxian +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Galaxian;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxiant galaxiant +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..2bfaccd3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00", + X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00", + X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00", + X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00", + X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00", + X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00", + X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00", + X"FC",X"FE",X"02",X"02",X"02",X"06",X"04",X"00",X"82",X"C6",X"6E",X"3C",X"18",X"FE",X"FE",X"00", + X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00", + 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X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"82",X"01",X"01",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"F8",X"EA",X"AE",X"79",X"DC",X"4A",X"C0",X"80",X"40",X"00",X"00",X"00",X"80",X"00", + X"40",X"70",X"58",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..bf31894a --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1K is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00", + X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00", + X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..2f811f7d --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07", + X"00",X"C0",X"A0",X"07",X"00",X"00",X"00",X"07",X"00",X"F6",X"07",X"F0",X"00",X"76",X"07",X"C6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GAL_HIT.vhd new file mode 100644 index 00000000..7d2fd29c --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/GAL_HIT.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..ee7591a2 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,662 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 10239) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"70",X"C3",X"55",X"1A",X"FF",X"3A",X"07",X"40",X"0F",X"D0",X"33",X"33",X"C9", + X"77",X"23",X"10",X"FC",X"C9",X"FF",X"9F",X"FF",X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"87",X"E1",X"5F",X"16",X"00",X"19",X"5E",X"23", + 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00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/build_id.v new file mode 100644 index 00000000..43fddd44 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "171607" diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..16453e8f --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxiant is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxiant is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..5a4d0094 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..69a20cbe --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..dbe0d0d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/Galaxian_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qpf b/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qpf new file mode 100644 index 00000000..35d49f9b --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "MoonCresta" +PROJECT_REVISION = "Arcade-MoonCresta" diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qsf b/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qsf new file mode 100644 index 00000000..49d7e724 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.qsf @@ -0,0 +1,143 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY MoonCresta +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/MoonCresta.sv +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.srf b/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/MoonCresta.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/README.txt b/Arcade/Galaxian Hardware/MoonCresta_MiST/README.txt new file mode 100644 index 00000000..9291cb56 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Moon Cresta port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + +ToDo: Video Fix/Rotate \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/Release/MoonCresta.rbf b/Arcade/Galaxian Hardware/MoonCresta_MiST/Release/MoonCresta.rbf new file mode 100644 index 00000000..faa2c01a Binary files /dev/null and b/Arcade/Galaxian Hardware/MoonCresta_MiST/Release/MoonCresta.rbf differ diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/clean.bat b/Arcade/Galaxian Hardware/MoonCresta_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/MoonCresta.sv b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/MoonCresta.sv new file mode 100644 index 00000000..fc063551 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/MoonCresta.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Moon Cresta +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module MoonCresta +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "MoonCresta;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian mooncresta +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..b9ce0580 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + 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X"50",X"90",X"50",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"60",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"60",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"40",X"A0",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"60",X"A0",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..9cf7380a --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7A",X"36",X"07",X"00",X"F0",X"38",X"1F",X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38", + X"00",X"36",X"07",X"F0",X"00",X"33",X"3F",X"DB",X"00",X"3F",X"57",X"C6",X"00",X"C6",X"3F",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", + 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GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", + X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", + X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", + X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", + 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+entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"70",X"C3",X"AD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"F5",X"3A",X"00",X"78",X"AF",X"32",X"01",X"70",X"F1",X"C3", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.v new file mode 100644 index 00000000..77b57328 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "171046" diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..b881e738 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..014e6f7a --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..69a20cbe --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..6c7c3250 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mc_video.vhd @@ -0,0 +1,447 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + + type bank_a is array(0 to 3) of std_logic_vector(7 downto 0); + signal bank : bank_a; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + if I_DRIVER_WR = '1' and I_A(2) = '0' then + bank(to_integer(unsigned(I_A(1 downto 0)))) <= I_BD; + end if; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= '1' & bank(0)(0) & bank(1)(0) & W_OBJ_ROM_A(5 downto 0) & W_1M(2 downto 0) + when (bank(2) /= X"00" and W_OBJ_ROM_A(7 downto 6) = "10") else + '0' & W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..2a921604 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/scandoubler.v @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/MoonCresta_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qpf b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qpf new file mode 100644 index 00000000..842b51ab --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "MrDoNightmare" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qsf b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qsf new file mode 100644 index 00000000..bc2e9fc5 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# MrDoNightmare_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDoNightmare.sv +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY MrDoNightmare +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.srf b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.srf new file mode 100644 index 00000000..cdf208db --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/MrDoNightmare.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No output dependent on input pin \"SPI_SS2\"" { } { } 0 15610 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at MrDoNightmare.sv(86): object \"m_bomb\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/README.txt b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/README.txt new file mode 100644 index 00000000..bdd3a884 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Mr. Do´s Nightmare port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/Release/MrDoNightmare.rbf b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/Release/MrDoNightmare.rbf new file mode 100644 index 00000000..7720684a Binary files /dev/null and b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/Release/MrDoNightmare.rbf differ diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/clean.bat b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/MrDoNightmare.sv b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/MrDoNightmare.sv new file mode 100644 index 00000000..2c0dc7f9 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/MrDoNightmare.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: MrDoNightmare +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module MrDoNightmare +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "MrDoNightmare;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian mrdo +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,2'b00,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,2'b00,m_up ,m_down }), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..df224504 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00", + X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00", + X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00", + X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00", + X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00", + X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00", + X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00", + X"FC",X"FE",X"02",X"02",X"02",X"06",X"04",X"00",X"82",X"C6",X"6E",X"3C",X"18",X"FE",X"FE",X"00", + X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00", + X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00", + X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"7A",X"FC",X"8E",X"8A",X"82",X"FE",X"7C",X"00", + X"72",X"F6",X"9E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00", + X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00", + X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"F8",X"FE",X"1C",X"38",X"1C",X"FE",X"F8",X"00", + X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"C0",X"F0",X"1E",X"1E",X"F0",X"C0",X"00",X"00", + X"C2",X"E2",X"F2",X"BA",X"9E",X"8E",X"86",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00", + X"FF",X"FF",X"F7",X"FF",X"FF",X"FE",X"FF",X"FF",X"F7",X"FF",X"FF",X"FF",X"FF",X"DF",X"FF",X"FD", + X"BF",X"F7",X"FF",X"FF",X"FF",X"FF",X"DF",X"FF",X"FF",X"FF",X"FF",X"DF",X"FF",X"FF",X"FB",X"FF", + X"B0",X"C0",X"82",X"C3",X"C2",X"81",X"83",X"81",X"03",X"07",X"1F",X"77",X"EB",X"ED",X"36",X"DB", + X"C3",X"82",X"C1",X"81",X"82",X"C3",X"A0",X"F0",X"67",X"36",X"6D",X"E3",X"7F",X"DF",X"07",X"03", + X"FF",X"FF",X"DF",X"AF",X"A1",X"BE",X"A9",X"D4",X"F7",X"FF",X"E7",X"DB",X"A1",X"40",X"C0",X"18", + X"FA",X"FD",X"FE",X"FF",X"FF",X"FD",X"DF",X"FF",X"21",X"C0",X"40",X"00",X"81",X"C3",X"E7",X"FF", + X"F0",X"EF",X"DF",X"BF",X"BF",X"BF",X"BF",X"3F",X"0F",X"E7",X"E3",X"F1",X"F8",X"F0",X"F0",X"F8", + X"0F",X"BF",X"BF",X"BF",X"BF",X"DF",X"EF",X"F0",X"F0",X"E0",X"F8",X"F0",X"F1",X"E3",X"E7",X"1F", + X"FF",X"FD",X"F2",X"F2",X"E9",X"CF",X"C9",X"D5",X"F7",X"FF",X"FF",X"7F",X"3F",X"9F",X"CF",X"F5", + X"9F",X"C9",X"C7",X"E1",X"F6",X"FA",X"DD",X"FF",X"F7",X"CF",X"9F",X"3F",X"7F",X"FF",X"FB",X"FF", + X"F8",X"C0",X"B0",X"78",X"48",X"48",X"B0",X"C0",X"00",X"00",X"60",X"20",X"21",X"61",X"40",X"40", + X"C0",X"B0",X"48",X"48",X"78",X"B0",X"C0",X"F8",X"40",X"40",X"61",X"21",X"20",X"60",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE", + 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X"C3",X"80",X"C3",X"80",X"82",X"C3",X"A0",X"F0",X"61",X"82",X"61",X"01",X"A3",X"E1",X"01",X"03", + X"00",X"10",X"70",X"E0",X"80",X"80",X"80",X"E0",X"00",X"08",X"08",X"04",X"04",X"04",X"04",X"04", + X"E0",X"80",X"80",X"80",X"E0",X"70",X"10",X"00",X"04",X"04",X"04",X"04",X"04",X"08",X"08",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..25afe613 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1K is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00", + X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00", + X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00", + 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X"23",X"24",X"24",X"C4",X"05",X"05",X"09",X"11",X"CF",X"30",X"00",X"8F",X"90",X"A0",X"A0",X"A0", + X"02",X"04",X"F8",X"00",X"00",X"00",X"00",X"00",X"09",X"09",X"09",X"09",X"09",X"09",X"11",X"E1", + X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"09",X"12",X"09",X"09",X"09",X"09",X"09",X"09",X"09", + X"0A",X"12",X"14",X"24",X"48",X"88",X"C4",X"22",X"0A",X"09",X"09",X"05",X"05",X"05",X"09",X"09", + X"E2",X"04",X"08",X"10",X"C8",X"24",X"14",X"12",X"05",X"85",X"85",X"85",X"05",X"05",X"09",X"11", + X"09",X"30",X"42",X"23",X"02",X"40",X"63",X"40",X"48",X"04",X"02",X"E2",X"00",X"02",X"E0",X"02", + X"23",X"40",X"23",X"40",X"42",X"23",X"18",X"05",X"62",X"80",X"62",X"02",X"A0",X"E2",X"00",X"24", + X"00",X"10",X"70",X"E0",X"E0",X"C0",X"C0",X"E0",X"00",X"08",X"09",X"05",X"05",X"07",X"06",X"04", + X"E0",X"C0",X"C0",X"E0",X"E0",X"70",X"10",X"00",X"04",X"06",X"07",X"05",X"05",X"09",X"08",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..9d5c2fdc --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(31 downto 0) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C6",X"07",X"76",X"00",X"C0",X"80",X"1E",X"00",X"80",X"C0",X"1E",X"00",X"76",X"C0",X"F6",X"00", + X"07",X"C4",X"C0",X"00",X"A4",X"07",X"F6",X"00",X"F6",X"07",X"C0",X"00",X"F6",X"21",X"1E",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; + + diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd new file mode 100644 index 00000000..7d2fd29c --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..1b828ed1 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,662 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 10239) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"70",X"C3",X"D0",X"00",X"3A",X"36",X"40",X"3C",X"E6",X"07",X"32",X"36",X"40", + X"20",X"1A",X"06",X"1A",X"11",X"09",X"58",X"1A",X"FE",X"05",X"28",X"09",X"FE",X"06",X"20",X"08", + X"3E",X"05",X"12",X"18",X"03",X"3E",X"06",X"12",X"13",X"13",X"10",X"EB",X"C9",X"FF",X"FF",X"FF", + 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X"11",X"13",X"21",X"13",X"11",X"11",X"21",X"11",X"21",X"11",X"AC",X"AA",X"2C",X"AA",X"2C",X"AA", + X"78",X"77",X"78",X"77",X"78",X"77",X"9B",X"99",X"2B",X"99",X"2B",X"99",X"51",X"11",X"26",X"11", + X"21",X"11",X"AA",X"CA",X"2A",X"1A",X"2A",X"CA",X"77",X"87",X"77",X"87",X"77",X"87",X"99",X"B9", + X"29",X"B9",X"29",X"B9",X"11",X"11",X"21",X"11",X"21",X"11",X"11",X"1F",X"23",X"11",X"11",X"13", + X"11",X"EE",X"23",X"31",X"21",X"33",X"06",X"00",X"01",X"01",X"01",X"11",X"13",X"10",X"00",X"00", + X"11",X"13",X"11",X"13",X"00",X"00",X"11",X"FD",X"ED",X"E1",X"00",X"00",X"01",X"11",X"C1",X"10", + X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"01",X"B1",X"11",X"60",X"00",X"00",X"3E", + X"DE",X"D1",X"11",X"00",X"00",X"11",X"31",X"31",X"11",X"00",X"00",X"01",X"11",X"C1",X"10",X"00", + X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"01",X"B1",X"11",X"10",X"00",X"00",X"5E",X"DE", + X"D1",X"11",X"00",X"00",X"13",X"13",X"13",X"16",X"07",X"01",X"05",X"04",X"00",X"11",X"11",X"11", + X"11",X"00",X"01",X"3D",X"F1",X"1D",X"E3",X"10",X"13",X"DE",X"31",X"1E",X"DE",X"31",X"1D",X"E3", + X"11",X"11",X"3D",X"E1",X"11",X"11",X"11",X"11",X"11",X"11",X"1D",X"12",X"22",X"22",X"21",X"D1", + X"1D",X"11",X"31",X"13",X"11",X"D1",X"4D",X"1D",X"DD",X"DD",X"D1",X"D4",X"1D",X"11",X"16",X"61", + X"11",X"D1",X"4D",X"1E",X"EE",X"EE",X"E1",X"D4",X"1D",X"11",X"31",X"13",X"11",X"D1",X"1D",X"12", + X"22",X"22",X"21",X"D1",X"11",X"11",X"15",X"51",X"11",X"11",X"07",X"01",X"05",X"08",X"11",X"11", + X"11",X"11",X"11",X"15",X"1D",X"DD",X"D1",X"1E",X"EE",X"F1",X"1D",X"33",X"31",X"13",X"33",X"E1", + X"1D",X"32",X"21",X"12",X"23",X"E1",X"1D",X"12",X"41",X"61",X"21",X"E1",X"AA",X"CA",X"AA",X"AA", + X"AC",X"AA",X"77",X"87",X"77",X"77",X"78",X"77",X"99",X"B9",X"99",X"99",X"9B",X"99",X"1E",X"12", + X"11",X"14",X"21",X"D1",X"1E",X"32",X"21",X"12",X"23",X"D1",X"1E",X"33",X"31",X"13",X"33",X"D1", + X"1E",X"EE",X"E1",X"1D",X"DD",X"D1",X"51",X"11",X"11",X"11",X"11",X"11",X"07",X"01",X"02",X"0C", + X"00",X"25",X"11",X"11",X"12",X"00",X"02",X"55",X"11",X"11",X"11",X"20",X"22",X"22",X"22",X"22", + X"21",X"22",X"24",X"44",X"11",X"21",X"44",X"42",X"24",X"14",X"21",X"21",X"41",X"42",X"24",X"44", + X"21",X"21",X"44",X"42",X"21",X"11",X"21",X"11",X"11",X"12",X"22",X"21",X"22",X"22",X"22",X"22", + X"E1",X"E1",X"11",X"11",X"1E",X"1F",X"AA",X"AA",X"AA",X"AA",X"AA",X"CA",X"77",X"77",X"77",X"77", + X"77",X"87",X"99",X"99",X"99",X"99",X"99",X"B9",X"11",X"16",X"16",X"16",X"11",X"11",X"07",X"01", + X"02",X"06",X"EE",X"11",X"11",X"D1",X"11",X"11",X"F1",X"11",X"11",X"D1",X"11",X"11",X"11",X"11", + X"D1",X"D1",X"11",X"61",X"11",X"11",X"D1",X"D1",X"11",X"11",X"DD",X"D1",X"D1",X"D1",X"61",X"11", + X"11",X"11",X"D1",X"D1",X"11",X"11",X"11",X"11",X"D1",X"D1",X"11",X"61",X"11",X"11",X"D1",X"D1", + X"11",X"11",X"1D",X"DD",X"D1",X"D1",X"61",X"11",X"11",X"11",X"D1",X"D1",X"11",X"11",X"15",X"55", + X"D1",X"D1",X"11",X"61",X"11",X"55",X"D1",X"11",X"11",X"11",X"11",X"11",X"D1",X"11",X"11",X"11", + X"07",X"00",X"00",X"0C",X"33",X"33",X"33",X"33",X"33",X"3F",X"30",X"00",X"00",X"01",X"00",X"00", + X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"10",X"00",X"00",X"03",X"33",X"33",X"33",X"33", + X"33",X"33",X"30",X"00",X"00",X"01",X"00",X"00",X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00", + X"10",X"00",X"00",X"03",X"33",X"33",X"33",X"33",X"33",X"33",X"30",X"00",X"00",X"01",X"00",X"00", + X"33",X"33",X"33",X"33",X"33",X"33",X"00",X"00",X"10",X"00",X"00",X"03",X"13",X"33",X"33",X"33", + X"33",X"33",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.v new file mode 100644 index 00000000..004d8e2f --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "170728" diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..b881e738 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..014e6f7a --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..496f01ad --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_inport.vhd @@ -0,0 +1,71 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else "00" & '0' & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..dbe0d0d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/MrDoNightmare_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/Omega_MiST/Omega.qpf b/Arcade/Galaxian Hardware/Omega_MiST/Omega.qpf new file mode 100644 index 00000000..12eceeac --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/Omega.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "Omega" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/Omega.qsf b/Arcade/Galaxian Hardware/Omega_MiST/Omega.qsf new file mode 100644 index 00000000..c61a11a7 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/Omega.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaxian_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Omega +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Omega.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/Omega.srf b/Arcade/Galaxian Hardware/Omega_MiST/Omega.srf new file mode 100644 index 00000000..14cddd5e --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/Omega.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/Omega_MiST/README.txt b/Arcade/Galaxian Hardware/Omega_MiST/README.txt new file mode 100644 index 00000000..4bf7bde9 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Omega port to MiST by Gehstock +-- 8 Januar 2018 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + +ToDo: Video Fix/Rotate \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/Release/Omega.rbf b/Arcade/Galaxian Hardware/Omega_MiST/Release/Omega.rbf new file mode 100644 index 00000000..f4056f23 Binary files /dev/null and b/Arcade/Galaxian Hardware/Omega_MiST/Release/Omega.rbf differ diff --git a/Arcade/Galaxian Hardware/Omega_MiST/clean.bat b/Arcade/Galaxian Hardware/Omega_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/Omega.sv b/Arcade/Galaxian Hardware/Omega_MiST/rtl/Omega.sv new file mode 100644 index 00000000..e321dfc0 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/Omega.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Omega +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Omega +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Omega;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian omega +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..f7d8d13f --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,285 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1H is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1H is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"02",x"01",x"07",x"3C",x"60",x"42", -- 0x0180 + x"C1",x"8F",x"B8",x"E2",x"C1",x"63",x"26",x"38", -- 0x0188 + x"19",x"3B",x"7E",x"FC",x"F8",x"FE",x"F1",x"F0", -- 0x0190 + x"F0",x"F1",x"FE",x"F8",x"FC",x"7E",x"3B",x"19", -- 0x0198 + x"38",x"26",x"63",x"C1",x"E2",x"B8",x"8F",x"C1", -- 0x01A0 + x"42",x"60",x"3C",x"07",x"01",x"02",x"00",x"00", -- 0x01A8 + x"30",x"76",x"7D",x"F8",x"F8",x"FE",x"B1",x"F0", -- 0x01B0 + x"F0",x"B1",x"FE",x"F8",x"F8",x"7D",x"76",x"30", -- 0x01B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x01C8 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 + x"40",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x01E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"00", -- 0x01E8 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"40",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"80",x"A0",x"80", -- 0x0208 + x"07",x"00",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"60",x"C0",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"03", -- 0x0220 + x"00",x"00",x"00",x"00",x"40",x"20",x"20",x"E0", -- 0x0228 + x"01",x"02",x"05",x"01",x"00",x"00",x"00",x"00", -- 0x0230 + x"18",x"E0",x"D0",x"08",x"80",x"00",x"00",x"00", -- 0x0238 + x"00",x"00",x"00",x"00",x"08",x"08",x"08",x"06", -- 0x0240 + x"00",x"00",x"00",x"00",x"10",x"10",x"10",x"60", -- 0x0248 + x"13",x"0C",x"03",x"07",x"09",x"10",x"00",x"00", -- 0x0250 + x"C8",x"30",x"C0",x"E0",x"90",x"08",x"00",x"00", -- 0x0258 + x"30",x"18",x"08",x"0C",x"06",x"03",x"01",x"02", -- 0x0260 + x"18",x"29",x"66",x"40",x"60",x"91",x"CE",x"60", -- 0x0268 + x"60",x"CE",x"91",x"60",x"40",x"66",x"29",x"18", -- 0x0270 + x"02",x"01",x"03",x"06",x"0C",x"08",x"18",x"30", -- 0x0278 + x"55",x"55",x"55",x"95",x"25",x"25",x"29",x"C9", -- 0x0280 + x"13",x"12",x"E6",x"0C",x"38",x"E0",x"00",x"00", -- 0x0288 + x"D5",x"75",x"3D",x"2D",x"95",x"75",x"F5",x"9D", -- 0x0290 + x"9D",x"F5",x"75",x"95",x"2D",x"3D",x"75",x"D5", -- 0x0298 + x"00",x"00",x"38",x"07",x"39",x"03",x"87",x"7F", -- 0x02A0 + x"20",x"60",x"42",x"4F",x"7C",x"72",x"7D",x"7F", -- 0x02A8 + x"87",x"03",x"39",x"07",x"38",x"00",x"00",x"00", -- 0x02B0 + x"71",x"46",x"7C",x"4F",x"42",x"60",x"20",x"00", -- 0x02B8 + x"38",x"04",x"3A",x"01",x"01",x"03",x"87",x"7F", -- 0x02C0 + x"24",x"36",x"24",x"48",x"7C",x"72",x"7D",x"7F", -- 0x02C8 + x"87",x"03",x"01",x"01",x"3A",x"04",x"38",x"00", -- 0x02D0 + x"71",x"46",x"7C",x"48",x"24",x"36",x"24",x"00", -- 0x02D8 + x"FF",x"81",x"81",x"81",x"81",x"81",x"81",x"FF", -- 0x02E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"5E",x"AE",x"7E",x"EE",x"7E",x"AE",x"5E", -- 0x02F0 + x"00",x"05",x"0A",x"07",x"0E",x"07",x"0A",x"05", -- 0x02F8 + x"00",x"38",x"06",x"39",x"01",x"03",x"87",x"7F", -- 0x0300 + x"22",x"33",x"24",x"48",x"7C",x"72",x"7D",x"7F", -- 0x0308 + x"87",x"03",x"01",x"39",x"06",x"38",x"00",x"00", -- 0x0310 + x"71",x"46",x"7C",x"48",x"24",x"33",x"22",x"00", -- 0x0318 + x"80",x"E2",x"B3",x"22",x"02",x"8B",x"CE",x"88", -- 0x0320 + x"80",x"E2",x"B3",x"22",x"02",x"0B",x"0E",x"08", -- 0x0328 + x"00",x"22",x"33",x"22",x"02",x"0B",x"0E",x"08", -- 0x0330 + x"00",x"22",x"33",x"22",x"02",x"0B",x"0E",x"08", -- 0x0338 + x"00",x"02",x"03",x"02",x"02",x"0B",x"0E",x"08", -- 0x0340 + x"00",x"02",x"03",x"02",x"02",x"03",x"02",x"00", -- 0x0348 + x"00",x"02",x"03",x"02",x"02",x"03",x"02",x"00", -- 0x0350 + x"00",x"02",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0358 + x"00",x"22",x"33",x"22",x"02",x"8B",x"CE",x"88", -- 0x0360 + x"00",x"02",x"03",x"02",x"02",x"0B",x"0E",x"08", -- 0x0368 + x"00",x"02",x"03",x"02",x"02",x"0B",x"0E",x"08", -- 0x0370 + x"00",x"00",x"00",x"00",x"02",x"03",x"02",x"00", -- 0x0378 + x"00",x"00",x"01",x"00",x"0E",x"11",x"11",x"00", -- 0x0380 + x"00",x"00",x"08",x"88",x"50",x"50",x"F0",x"F8", -- 0x0388 + x"00",x"11",x"11",x"0E",x"00",x"01",x"00",x"00", -- 0x0390 + x"F8",x"F0",x"50",x"50",x"88",x"08",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x03A8 + x"01",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 + x"E0",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x03C8 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"03", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"C0", -- 0x03E8 + x"03",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 + x"C0",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"00",x"00",x"00",x"00",x"07",x"0F",x"0B",x"03", -- 0x0400 + x"00",x"00",x"10",x"10",x"27",x"A8",x"D8",x"5C", -- 0x0408 + x"03",x"0B",x"0D",x"07",x"00",x"00",x"00",x"00", -- 0x0410 + x"5C",x"D8",x"A8",x"27",x"10",x"10",x"00",x"00", -- 0x0418 + x"00",x"00",x"00",x"00",x"07",x"0F",x"0B",x"03", -- 0x0420 + x"00",x"00",x"41",x"22",x"24",x"A8",x"D8",x"5C", -- 0x0428 + x"03",x"0B",x"0D",x"07",x"00",x"00",x"00",x"00", -- 0x0430 + x"5C",x"D8",x"A8",x"24",x"22",x"41",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"00",x"07",x"0F",x"0B",x"03", -- 0x0440 + x"00",x"00",x"84",x"44",x"28",x"A8",x"D8",x"5C", -- 0x0448 + x"03",x"0B",x"0D",x"07",x"00",x"00",x"00",x"00", -- 0x0450 + x"5C",x"D8",x"A8",x"28",x"44",x"84",x"00",x"00", -- 0x0458 + x"00",x"00",x"00",x"00",x"07",x"0F",x"0B",x"03", -- 0x0460 + x"00",x"00",x"90",x"48",x"28",x"A8",x"D8",x"5C", -- 0x0468 + x"03",x"0B",x"0D",x"07",x"00",x"00",x"00",x"00", -- 0x0470 + x"5C",x"D8",x"A8",x"28",x"48",x"90",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"07",x"0F",x"0B",x"03", -- 0x0480 + x"00",x"00",x"88",x"88",x"50",x"50",x"B0",x"B8", -- 0x0488 + x"03",x"0B",x"0D",x"07",x"00",x"00",x"00",x"00", -- 0x0490 + x"B8",x"B0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"07",x"0F",x"03",x"03",x"16", -- 0x04A0 + x"00",x"00",x"00",x"20",x"A4",x"A4",x"A8",x"B8", -- 0x04A8 + x"20",x"13",x"0E",x"00",x"03",x"02",x"00",x"00", -- 0x04B0 + x"B0",x"B8",x"70",x"A0",x"20",x"20",x"20",x"00", -- 0x04B8 + x"00",x"00",x"03",x"04",x"07",x"1F",x"3F",x"20", -- 0x04C0 + x"00",x"00",x"00",x"80",x"50",x"50",x"90",x"E6", -- 0x04C8 + x"13",x"0D",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x04D0 + x"28",x"70",x"F0",x"70",x"80",x"00",x"00",x"00", -- 0x04D8 + x"00",x"00",x"00",x"01",x"0B",x"1F",x"10",x"10", -- 0x04E0 + x"00",x"00",x"80",x"40",x"20",x"20",x"60",x"4C", -- 0x04E8 + x"0F",x"00",x"1E",x"01",x"00",x"0C",x"00",x"00", -- 0x04F0 + x"F0",x"66",x"F8",x"E0",x"40",x"00",x"00",x"00", -- 0x04F8 + x"00",x"00",x"00",x"06",x"0C",x"0B",x"08",x"06", -- 0x0500 + x"00",x"00",x"00",x"60",x"30",x"10",x"10",x"60", -- 0x0508 + x"33",x"0C",x"03",x"07",x"31",x"00",x"00",x"00", -- 0x0510 + x"CC",x"30",x"C0",x"F0",x"8C",x"00",x"00",x"00", -- 0x0518 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0520 + x"00",x"00",x"10",x"10",x"27",x"A8",x"D8",x"5C", -- 0x0528 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0530 + x"5C",x"D8",x"A8",x"27",x"10",x"10",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"07",x"08",x"08", -- 0x0540 + x"00",x"00",x"41",x"22",x"24",x"A8",x"D8",x"5C", -- 0x0548 + x"08",x"08",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"5C",x"D8",x"A8",x"24",x"22",x"41",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0560 + x"00",x"00",x"84",x"44",x"28",x"A8",x"D8",x"5C", -- 0x0568 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0570 + x"5C",x"D8",x"A8",x"28",x"44",x"84",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"07",x"08",x"08", -- 0x0580 + x"00",x"00",x"90",x"48",x"28",x"A8",x"D8",x"5C", -- 0x0588 + x"08",x"08",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0590 + x"5C",x"D8",x"A8",x"28",x"48",x"90",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"0E",x"11",x"11", -- 0x05A0 + x"00",x"00",x"88",x"88",x"50",x"50",x"B0",x"B8", -- 0x05A8 + x"11",x"11",x"0E",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 + x"B8",x"B0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"07",x"08",x"00",x"00",x"10", -- 0x05C0 + x"00",x"00",x"00",x"20",x"A4",x"A4",x"A8",x"B8", -- 0x05C8 + x"20",x"13",x"0E",x"00",x"03",x"02",x"00",x"00", -- 0x05D0 + x"B0",x"B8",x"70",x"A0",x"20",x"20",x"20",x"00", -- 0x05D8 + x"00",x"00",x"03",x"04",x"00",x"10",x"20",x"20", -- 0x05E0 + x"00",x"00",x"00",x"80",x"50",x"50",x"90",x"E6", -- 0x05E8 + x"13",x"0D",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x05F0 + x"28",x"70",x"F0",x"70",x"80",x"00",x"00",x"00", -- 0x05F8 + x"00",x"00",x"00",x"01",x"08",x"10",x"10",x"10", -- 0x0600 + x"00",x"00",x"80",x"40",x"20",x"20",x"60",x"4C", -- 0x0608 + x"0F",x"00",x"1E",x"01",x"00",x"0C",x"00",x"00", -- 0x0610 + x"F0",x"66",x"F8",x"E0",x"40",x"00",x"00",x"00", -- 0x0618 + x"00",x"00",x"00",x"06",x"08",x"08",x"08",x"06", -- 0x0620 + x"00",x"00",x"00",x"60",x"10",x"10",x"10",x"60", -- 0x0628 + x"33",x"0C",x"03",x"0F",x"31",x"00",x"00",x"00", -- 0x0630 + x"CC",x"30",x"C0",x"F0",x"8C",x"00",x"00",x"00", -- 0x0638 + x"00",x"66",x"77",x"77",x"77",x"55",x"DD",x"66", -- 0x0640 + x"00",x"60",x"70",x"70",x"70",x"50",x"D0",x"60", -- 0x0648 + x"00",x"06",x"07",x"07",x"07",x"05",x"0D",x"06", -- 0x0650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658 + x"35",x"16",x"B7",x"76",x"B5",x"16",x"35",x"00", -- 0x0660 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0668 + x"F8",x"F8",x"F8",x"F8",x"B8",x"58",x"F8",x"00", -- 0x0670 + x"12",x"6A",x"94",x"D4",x"94",x"6A",x"12",x"00", -- 0x0678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"6C", -- 0x0688 + x"00",x"01",x"00",x"01",x"03",x"00",x"04",x"02", -- 0x0690 + x"83",x"38",x"86",x"39",x"01",x"33",x"87",x"7E", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"3B",x"00", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"40", -- 0x06A8 + x"22",x"B3",x"24",x"48",x"7C",x"7E",x"7F",x"7F", -- 0x06B0 + x"00",x"20",x"40",x"80",x"80",x"40",x"20",x"20", -- 0x06B8 + x"04",x"00",x"03",x"01",x"00",x"01",x"00",x"00", -- 0x06C0 + x"87",x"33",x"01",x"39",x"86",x"38",x"83",x"6C", -- 0x06C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"7F",x"7E",x"7C",x"48",x"24",x"B3",x"22",x"00", -- 0x06E0 + x"20",x"40",x"80",x"80",x"40",x"20",x"00",x"40", -- 0x06E8 + x"3B",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 + x"00",x"00",x"00",x"00",x"00",x"00",x"02",x"01", -- 0x0710 + x"60",x"08",x"04",x"69",x"03",x"00",x"0A",x"B5", -- 0x0718 + x"00",x"00",x"00",x"00",x"00",x"00",x"11",x"19", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"08", -- 0x0728 + x"00",x"20",x"44",x"00",x"6C",x"2E",x"06",x"30", -- 0x0730 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0738 + x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 + x"0A",x"00",x"03",x"69",x"04",x"08",x"60",x"00", -- 0x0748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"06",x"2E",x"6C",x"00",x"44",x"22",x"00",x"19", -- 0x0760 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0768 + x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"04",x"00",x"00",x"40",x"00",x"00",x"00",x"00", -- 0x0780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 + x"08",x"00",x"13",x"0C",x"00",x"23",x"31",x"4F", -- 0x0798 + x"00",x"00",x"00",x"00",x"00",x"10",x"00",x"00", -- 0x07A0 + x"01",x"00",x"00",x"00",x"00",x"04",x"00",x"00", -- 0x07A8 + x"00",x"08",x"C0",x"E8",x"80",x"40",x"A2",x"F0", -- 0x07B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 + x"27",x"31",x"01",x"00",x"91",x"10",x"09",x"04", -- 0x07C8 + x"00",x"00",x"00",x"00",x"10",x"00",x"00",x"00", -- 0x07D0 + x"00",x"00",x"20",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 + x"CE",x"A4",x"45",x"88",x"00",x"C2",x"00",x"00", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"10", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..cb6701eb --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,285 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1K is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1K is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0188 + x"00",x"00",x"60",x"F0",x"F8",x"FE",x"D1",x"F0", -- 0x0190 + x"F0",x"D1",x"FE",x"F8",x"F0",x"60",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 + x"00",x"00",x"60",x"F0",x"F8",x"FE",x"F5",x"FF", -- 0x01B0 + x"FF",x"F5",x"FE",x"F8",x"F0",x"60",x"00",x"00", -- 0x01B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x01C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"80", -- 0x01E8 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"00",x"20",x"C0", -- 0x0208 + x"01",x"01",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"A0",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0E", -- 0x0228 + x"01",x"03",x"04",x"01",x"00",x"00",x"00",x"00", -- 0x0230 + x"F8",x"00",x"10",x"08",x"80",x"00",x"00",x"00", -- 0x0238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0248 + x"13",x"0F",x"00",x"04",x"08",x"10",x"00",x"00", -- 0x0250 + x"C8",x"F0",x"00",x"20",x"10",x"08",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0278 + x"08",x"22",x"00",x"08",x"42",x"50",x"40",x"24", -- 0x0280 + x"40",x"40",x"08",x"40",x"40",x"00",x"00",x"00", -- 0x0288 + x"00",x"02",x"20",x"20",x"90",x"12",x"80",x"E0", -- 0x0290 + x"E0",x"80",x"12",x"90",x"20",x"20",x"02",x"00", -- 0x0298 + x"00",x"00",x"00",x"00",x"01",x"03",x"86",x"7D", -- 0x02A0 + x"00",x"00",x"00",x"00",x"FC",x"FE",x"FF",x"FF", -- 0x02A8 + x"86",x"03",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 + x"FF",x"FE",x"FC",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 + x"00",x"00",x"00",x"00",x"01",x"03",x"86",x"7D", -- 0x02C0 + x"00",x"00",x"00",x"00",x"FC",x"FE",x"FF",x"FF", -- 0x02C8 + x"86",x"03",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"FF",x"FE",x"FC",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 + x"FF",x"81",x"81",x"81",x"81",x"81",x"81",x"FF", -- 0x02E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"0E",x"1E",x"2E",x"0E",x"2E",x"1E",x"0E", -- 0x02F0 + x"00",x"00",x"01",x"02",x"00",x"02",x"01",x"00", -- 0x02F8 + x"00",x"00",x"00",x"00",x"01",x"03",x"86",x"7D", -- 0x0300 + x"00",x"00",x"00",x"00",x"FC",x"FE",x"FF",x"FF", -- 0x0308 + x"86",x"03",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"FF",x"FE",x"FC",x"00",x"00",x"00",x"00",x"00", -- 0x0318 + x"88",x"CE",x"8B",x"02",x"20",x"38",x"2C",x"08", -- 0x0320 + x"88",x"CE",x"8B",x"02",x"20",x"38",x"2C",x"08", -- 0x0328 + x"08",x"0E",x"0B",x"02",x"20",x"38",x"2C",x"08", -- 0x0330 + x"08",x"0E",x"0B",x"02",x"00",x"08",x"0C",x"08", -- 0x0338 + x"08",x"0E",x"0B",x"02",x"00",x"08",x"0C",x"08", -- 0x0340 + x"08",x"0E",x"0B",x"02",x"00",x"00",x"00",x"00", -- 0x0348 + x"00",x"02",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0350 + x"00",x"02",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0358 + x"08",x"0E",x"0B",x"02",x"20",x"38",x"2C",x"08", -- 0x0360 + x"08",x"0E",x"0B",x"02",x"20",x"38",x"2C",x"08", -- 0x0368 + x"00",x"02",x"03",x"02",x"00",x"08",x"0C",x"08", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"02",x"0C",x"10",x"20",x"40",x"80",x"80",x"40", -- 0x0380 + x"34",x"42",x"01",x"01",x"02",x"02",x"00",x"61", -- 0x0388 + x"40",x"80",x"80",x"40",x"20",x"10",x"0C",x"02", -- 0x0390 + x"61",x"00",x"02",x"02",x"01",x"01",x"42",x"34", -- 0x0398 + x"00",x"00",x"00",x"02",x"05",x"08",x"0C",x"18", -- 0x03A0 + x"00",x"00",x"00",x"40",x"D0",x"28",x"04",x"06", -- 0x03A8 + x"18",x"0C",x"08",x"05",x"02",x"00",x"00",x"00", -- 0x03B0 + x"06",x"04",x"28",x"D0",x"40",x"00",x"00",x"00", -- 0x03B8 + x"0B",x"36",x"22",x"20",x"40",x"20",x"62",x"80", -- 0x03C0 + x"50",x"B8",x"88",x"12",x"02",x"05",x"41",x"82", -- 0x03C8 + x"80",x"62",x"20",x"40",x"20",x"22",x"36",x"0B", -- 0x03D0 + x"82",x"41",x"05",x"02",x"12",x"88",x"B8",x"50", -- 0x03D8 + x"01",x"40",x"0A",x"00",x"12",x"00",x"24",x"81", -- 0x03E0 + x"00",x"02",x"A0",x"00",x"48",x"00",x"24",x"81", -- 0x03E8 + x"11",x"44",x"10",x"05",x"10",x"02",x"40",x"00", -- 0x03F0 + x"18",x"22",x"08",x"20",x"08",x"40",x"02",x"80", -- 0x03F8 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0400 + x"00",x"00",x"10",x"10",x"27",x"28",x"60",x"60", -- 0x0408 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0410 + x"60",x"60",x"28",x"27",x"10",x"10",x"00",x"00", -- 0x0418 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0420 + x"00",x"00",x"41",x"22",x"24",x"28",x"60",x"60", -- 0x0428 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0430 + x"60",x"60",x"28",x"24",x"22",x"41",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0440 + x"00",x"00",x"84",x"44",x"28",x"28",x"60",x"60", -- 0x0448 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0450 + x"60",x"60",x"28",x"28",x"44",x"84",x"00",x"00", -- 0x0458 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0460 + x"00",x"00",x"90",x"48",x"28",x"28",x"60",x"60", -- 0x0468 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0470 + x"60",x"60",x"28",x"28",x"48",x"90",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"00",x"07",x"0E",x"0E", -- 0x0480 + x"00",x"00",x"88",x"88",x"50",x"50",x"C0",x"C0", -- 0x0488 + x"0E",x"0E",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0490 + x"C0",x"C0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"00",x"07",x"07",x"0F",x"0E", -- 0x04A0 + x"00",x"00",x"00",x"20",x"24",x"24",x"28",x"C8", -- 0x04A8 + x"1E",x"0D",x"00",x"00",x"03",x"02",x"00",x"00", -- 0x04B0 + x"C0",x"C0",x"80",x"A0",x"20",x"20",x"20",x"00", -- 0x04B8 + x"00",x"00",x"00",x"03",x"01",x"03",x"17",x"1F", -- 0x04C0 + x"00",x"00",x"00",x"00",x"90",x"90",x"10",x"E6", -- 0x04C8 + x"0D",x"01",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x04D0 + x"C8",x"80",x"00",x"00",x"80",x"00",x"00",x"00", -- 0x04D8 + x"00",x"00",x"00",x"00",x"03",x"09",x"0F",x"0E", -- 0x04E0 + x"00",x"00",x"00",x"80",x"C0",x"C0",x"80",x"4C", -- 0x04E8 + x"01",x"01",x"1F",x"00",x"03",x"0C",x"00",x"00", -- 0x04F0 + x"B0",x"86",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"00", -- 0x0500 + x"00",x"00",x"00",x"00",x"E0",x"E0",x"E0",x"00", -- 0x0508 + x"33",x"0F",x"00",x"0C",x"30",x"00",x"00",x"00", -- 0x0510 + x"CC",x"F0",x"00",x"30",x"0C",x"00",x"00",x"00", -- 0x0518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"00",x"00",x"10",x"10",x"27",x"28",x"60",x"60", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"60",x"60",x"28",x"27",x"10",x"10",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 + x"00",x"00",x"41",x"22",x"24",x"28",x"60",x"60", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"60",x"60",x"28",x"24",x"22",x"41",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 + x"00",x"00",x"84",x"44",x"28",x"28",x"60",x"60", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"60",x"60",x"28",x"28",x"44",x"84",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"90",x"48",x"28",x"28",x"60",x"60", -- 0x0588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 + x"60",x"60",x"28",x"28",x"48",x"90",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 + x"00",x"00",x"88",x"88",x"50",x"50",x"C0",x"C0", -- 0x05A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 + x"C0",x"C0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 + x"00",x"00",x"00",x"20",x"24",x"24",x"28",x"C8", -- 0x05C8 + x"00",x"01",x"00",x"00",x"03",x"02",x"00",x"00", -- 0x05D0 + x"C0",x"C0",x"80",x"A0",x"20",x"20",x"20",x"00", -- 0x05D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 + x"00",x"00",x"00",x"00",x"10",x"10",x"10",x"E6", -- 0x05E8 + x"01",x"01",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x05F0 + x"C8",x"80",x"00",x"00",x"80",x"00",x"00",x"00", -- 0x05F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"4C", -- 0x0608 + x"01",x"01",x"1F",x"00",x"03",x"0C",x"00",x"00", -- 0x0610 + x"B0",x"86",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 + x"33",x"0F",x"00",x"0C",x"30",x"00",x"00",x"00", -- 0x0630 + x"CC",x"F0",x"00",x"30",x"0C",x"00",x"00",x"00", -- 0x0638 + x"00",x"66",x"FF",x"FF",x"FF",x"FF",x"FF",x"66", -- 0x0640 + x"00",x"60",x"F0",x"F0",x"F0",x"F0",x"F0",x"60", -- 0x0648 + x"00",x"06",x"0F",x"0F",x"0F",x"0F",x"0F",x"06", -- 0x0650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658 + x"00",x"1E",x"BF",x"6F",x"BF",x"1E",x"00",x"00", -- 0x0660 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0668 + x"50",x"50",x"50",x"50",x"F0",x"F0",x"F7",x"00", -- 0x0670 + x"12",x"0A",x"08",x"C8",x"08",x"0A",x"12",x"00", -- 0x0678 + x"00",x"00",x"00",x"00",x"00",x"01",x"02",x"04", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"B6",x"00",x"6C", -- 0x0688 + x"04",x"01",x"04",x"09",x"13",x"10",x"24",x"12", -- 0x0690 + x"83",x"00",x"80",x"00",x"01",x"33",x"86",x"7D", -- 0x0698 + x"00",x"00",x"00",x"33",x"4C",x"80",x"3B",x"00", -- 0x06A0 + x"00",x"00",x"00",x"80",x"60",x"10",x"88",x"48", -- 0x06A8 + x"00",x"80",x"00",x"00",x"FC",x"FE",x"FF",x"FF", -- 0x06B0 + x"04",x"24",x"48",x"90",x"90",x"48",x"24",x"24", -- 0x06B8 + x"24",x"10",x"13",x"09",x"04",x"01",x"04",x"04", -- 0x06C0 + x"86",x"33",x"01",x"00",x"80",x"00",x"83",x"6C", -- 0x06C8 + x"02",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 + x"00",x"B6",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"FF",x"FE",x"FC",x"00",x"00",x"80",x"00",x"00", -- 0x06E0 + x"24",x"48",x"90",x"90",x"48",x"24",x"04",x"48", -- 0x06E8 + x"3B",x"80",x"4C",x"33",x"00",x"00",x"00",x"00", -- 0x06F0 + x"88",x"10",x"60",x"80",x"00",x"00",x"00",x"00", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"02",x"04",x"01", -- 0x0700 + x"00",x"00",x"00",x"03",x"68",x"06",x"D1",x"0C", -- 0x0708 + x"02",x"09",x"11",x"22",x"28",x"48",x"02",x"51", -- 0x0710 + x"02",x"01",x"00",x"01",x"03",x"40",x"08",x"B1", -- 0x0718 + x"00",x"00",x"06",x"30",x"4D",x"00",x"40",x"40", -- 0x0720 + x"00",x"00",x"00",x"00",x"80",x"40",x"28",x"28", -- 0x0728 + x"80",x"00",x"00",x"00",x"6C",x"2E",x"86",x"B0", -- 0x0730 + x"04",x"14",x"90",x"C8",x"68",x"24",x"88",x"80", -- 0x0738 + x"02",x"48",x"28",x"22",x"11",x"09",x"02",x"01", -- 0x0740 + x"08",x"40",x"03",x"01",x"00",x"01",x"02",x"0C", -- 0x0748 + x"04",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"D1",x"06",x"68",x"03",x"00",x"00",x"00",x"00", -- 0x0758 + x"86",x"2E",x"6C",x"00",x"00",x"00",x"80",x"40", -- 0x0760 + x"88",x"24",x"68",x"C8",x"90",x"14",x"04",x"28", -- 0x0768 + x"40",x"00",x"4D",x"30",x"06",x"00",x"00",x"00", -- 0x0770 + x"28",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"03", -- 0x0780 + x"00",x"31",x"43",x"88",x"00",x"60",x"C0",x"01", -- 0x0788 + x"02",x"30",x"10",x"20",x"23",x"42",x"40",x"00", -- 0x0790 + x"01",x"06",x"30",x"60",x"C2",x"AD",x"18",x"1D", -- 0x0798 + x"00",x"00",x"80",x"40",x"02",x"03",x"00",x"00", -- 0x07A0 + x"00",x"00",x"00",x"00",x"00",x"80",x"80",x"40", -- 0x07A8 + x"C0",x"68",x"50",x"82",x"F1",x"10",x"28",x"B0", -- 0x07B0 + x"40",x"08",x"04",x"02",x"82",x"C2",x"84",x"00", -- 0x07B8 + x"01",x"19",x"10",x"10",x"88",x"88",x"C4",x"40", -- 0x07C0 + x"05",x"98",x"86",x"47",x"05",x"00",x"40",x"64", -- 0x07C8 + x"60",x"20",x"00",x"04",x"03",x"00",x"80",x"00", -- 0x07D0 + x"3C",x"08",x"00",x"00",x"86",x"C1",x"00",x"00", -- 0x07D8 + x"88",x"10",x"70",x"E0",x"00",x"08",x"18",x"80", -- 0x07E0 + x"00",x"11",x"21",x"C3",x"01",x"11",x"32",x"60", -- 0x07E8 + x"00",x"00",x"04",x"08",x"70",x"C0",x"00",x"00", -- 0x07F0 + x"20",x"40",x"08",x"30",x"40",x"00",x"00",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..e989225e --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,33 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_6L is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(4 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_6L is + + + type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"7A",x"36",x"07",x"00",x"F0",x"38",x"1F", -- 0x0000 + x"00",x"C7",x"F0",x"3F",x"00",x"DB",x"C6",x"38", -- 0x0008 + x"00",x"36",x"07",x"F0",x"00",x"33",x"3F",x"DB", -- 0x0010 + x"00",x"3F",x"57",x"C6",x"00",x"C6",x"3F",x"FF" -- 0x0018 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + 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+1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", + X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", + X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", + 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X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80", + X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D", + X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78", + X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83", + X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78", + X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75", + X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D", + X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80", + X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78", + X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D", + X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D", + X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D", + X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78", + X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D", + X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D", + X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D", + X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D", + X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", + X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", + X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", + X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..33721787 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,2077 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ROM_PGM_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM_0 is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"AF",x"32",x"01",x"70",x"C3",x"69",x"00",x"FF", -- 0x0000 + x"77",x"3C",x"23",x"77",x"3C",x"19",x"C9",x"FF", -- 0x0008 + x"77",x"23",x"10",x"FC",x"C9",x"FF",x"FF",x"FF", -- 0x0010 + x"77",x"23",x"10",x"FC",x"0D",x"20",x"F9",x"C9", -- 0x0018 + x"85",x"6F",x"3E",x"00",x"8C",x"67",x"7E",x"C9", -- 0x0020 + x"87",x"E1",x"5F",x"16",x"00",x"19",x"5E",x"23", -- 0x0028 + x"56",x"EB",x"E9",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0030 + x"E5",x"26",x"40",x"3A",x"A0",x"40",x"6F",x"CB", -- 0x0038 + x"7E",x"28",x"0E",x"72",x"2C",x"73",x"2C",x"7D", -- 0x0040 + x"FE",x"C0",x"30",x"02",x"3E",x"C0",x"32",x"A0", -- 0x0048 + x"40",x"E1",x"C9",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0050 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0058 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"C3",x"94", -- 0x0060 + x"08",x"21",x"00",x"40",x"11",x"01",x"40",x"01", -- 0x0068 + x"00",x"04",x"36",x"00",x"ED",x"B0",x"31",x"00", -- 0x0070 + x"44",x"21",x"C0",x"40",x"06",x"40",x"3E",x"FF", -- 0x0078 + x"D7",x"32",x"00",x"78",x"3A",x"00",x"78",x"AF", -- 0x0080 + x"32",x"01",x"70",x"32",x"00",x"68",x"32",x"01", -- 0x0088 + x"68",x"32",x"02",x"68",x"32",x"04",x"60",x"32", -- 0x0090 + x"05",x"60",x"32",x"06",x"60",x"32",x"07",x"60", -- 0x0098 + x"3E",x"01",x"32",x"06",x"70",x"32",x"07",x"70", -- 0x00A0 + x"21",x"C0",x"C0",x"22",x"A0",x"40",x"32",x"04", -- 0x00A8 + x"70",x"21",x"00",x"50",x"22",x"0B",x"40",x"3E", -- 0x00B0 + x"20",x"32",x"08",x"40",x"3A",x"00",x"70",x"47", -- 0x00B8 + x"E6",x"01",x"3E",x"10",x"28",x"02",x"3E",x"20", -- 0x00C0 + x"32",x"17",x"40",x"78",x"0F",x"0F",x"E6",x"01", -- 0x00C8 + x"3E",x"05",x"20",x"02",x"3E",x"03",x"32",x"07", -- 0x00D0 + x"40",x"78",x"0F",x"0F",x"0F",x"E6",x"01",x"32", -- 0x00D8 + x"0F",x"40",x"3A",x"00",x"68",x"07",x"07",x"E6", -- 0x00E0 + x"03",x"32",x"00",x"40",x"21",x"00",x"00",x"2B", -- 0x00E8 + x"3A",x"00",x"78",x"7D",x"B4",x"21",x"00",x"58", -- 0x00F0 + x"01",x"00",x"01",x"16",x"00",x"72",x"23",x"0B", -- 0x00F8 + x"78",x"B1",x"20",x"F9",x"16",x"5D",x"21",x"00", -- 0x0100 + x"50",x"01",x"00",x"04",x"72",x"3A",x"00",x"78", -- 0x0108 + x"23",x"0B",x"78",x"B1",x"20",x"F6",x"3E",x"01", -- 0x0110 + x"32",x"01",x"70",x"26",x"40",x"3A",x"A1",x"40", -- 0x0118 + x"6F",x"7E",x"87",x"30",x"05",x"CD",x"5E",x"01", -- 0x0120 + x"18",x"F1",x"E6",x"0F",x"4F",x"06",x"00",x"36", -- 0x0128 + x"FF",x"23",x"5E",x"36",x"FF",x"2C",x"7D",x"FE", -- 0x0130 + x"C0",x"30",x"02",x"3E",x"C0",x"32",x"A1",x"40", -- 0x0138 + x"7B",x"21",x"4E",x"01",x"09",x"5E",x"23",x"56", -- 0x0140 + x"21",x"1B",x"01",x"E5",x"EB",x"E9",x"F0",x"02", -- 0x0148 + x"24",x"03",x"35",x"03",x"AD",x"03",x"4E",x"04", -- 0x0150 + x"6A",x"04",x"B1",x"04",x"BC",x"07",x"3A",x"5F", -- 0x0158 + x"42",x"47",x"E6",x"0F",x"CA",x"82",x"01",x"21", -- 0x0160 + x"81",x"42",x"CB",x"46",x"C0",x"E6",x"03",x"CA", -- 0x0168 + x"A6",x"02",x"FE",x"01",x"28",x"53",x"FE",x"02", -- 0x0170 + x"28",x"76",x"3A",x"00",x"41",x"A7",x"C8",x"C3", -- 0x0178 + x"F0",x"02",x"11",x"E0",x"FF",x"21",x"E0",x"50", -- 0x0180 + x"3A",x"0E",x"40",x"A7",x"28",x"22",x"36",x"02", -- 0x0188 + x"CD",x"BA",x"01",x"21",x"40",x"53",x"CD",x"B8", -- 0x0190 + x"01",x"3A",x"0D",x"40",x"A7",x"21",x"40",x"53", -- 0x0198 + x"28",x"03",x"21",x"E0",x"50",x"CB",x"60",x"C8", -- 0x01A0 + x"3A",x"06",x"40",x"0F",x"D0",x"C3",x"C1",x"01", -- 0x01A8 + x"21",x"E0",x"50",x"CD",x"C1",x"01",x"18",x"DB", -- 0x01B0 + x"36",x"01",x"19",x"36",x"25",x"19",x"36",x"20", -- 0x01B8 + x"C9",x"3E",x"10",x"77",x"19",x"77",x"19",x"77", -- 0x01C0 + x"C9",x"21",x"7D",x"53",x"11",x"4F",x"41",x"06", -- 0x01C8 + x"02",x"CD",x"3E",x"02",x"01",x"E2",x"FF",x"09", -- 0x01D0 + x"7B",x"FE",x"3F",x"28",x"09",x"FE",x"2F",x"28", -- 0x01D8 + x"0A",x"FE",x"1F",x"20",x"EA",x"C9",x"21",x"3D", -- 0x01E0 + x"52",x"18",x"E4",x"21",x"FD",x"50",x"18",x"DF", -- 0x01E8 + x"21",x"68",x"50",x"11",x"50",x"41",x"06",x"03", -- 0x01F0 + x"CD",x"17",x"02",x"01",x"1D",x"00",x"09",x"7B", -- 0x01F8 + x"FE",x"80",x"28",x"09",x"FE",x"B0",x"28",x"0A", -- 0x0200 + x"FE",x"E0",x"C8",x"18",x"E9",x"21",x"88",x"51", -- 0x0208 + x"18",x"E4",x"21",x"A8",x"52",x"18",x"DF",x"1A", -- 0x0210 + x"F5",x"13",x"1A",x"4F",x"F1",x"CB",x"4F",x"28", -- 0x0218 + x"10",x"79",x"CB",x"4F",x"28",x"07",x"36",x"C8", -- 0x0220 + x"23",x"13",x"10",x"EB",x"C9",x"36",x"C9",x"18", -- 0x0228 + x"F7",x"79",x"CB",x"4F",x"28",x"04",x"36",x"CA", -- 0x0230 + x"18",x"EE",x"36",x"10",x"18",x"EA",x"E5",x"D5", -- 0x0238 + x"1A",x"CB",x"4F",x"28",x"25",x"CB",x"57",x"20", -- 0x0240 + x"28",x"CB",x"5F",x"20",x"2B",x"1D",x"1A",x"CB", -- 0x0248 + x"4F",x"28",x"30",x"CB",x"57",x"20",x"30",x"CB", -- 0x0250 + x"5F",x"20",x"36",x"36",x"C8",x"2D",x"1D",x"10", -- 0x0258 + x"DF",x"D1",x"E1",x"2D",x"2D",x"7B",x"D6",x"04", -- 0x0260 + x"5F",x"C9",x"36",x"10",x"2D",x"36",x"10",x"18", -- 0x0268 + x"F0",x"CD",x"9E",x"02",x"36",x"5E",x"18",x"F4", -- 0x0270 + x"D6",x"10",x"12",x"E6",x"70",x"20",x"F5",x"1A", -- 0x0278 + x"CB",x"9F",x"12",x"36",x"CA",x"18",x"E5",x"CD", -- 0x0280 + x"9E",x"02",x"36",x"C8",x"2D",x"36",x"5F",x"18", -- 0x0288 + x"D0",x"D6",x"10",x"12",x"E6",x"70",x"20",x"F2", -- 0x0290 + x"1A",x"CB",x"9F",x"12",x"18",x"CE",x"CB",x"97", -- 0x0298 + x"CB",x"DF",x"F6",x"70",x"12",x"C9",x"3A",x"BA", -- 0x02A0 + x"40",x"0F",x"D0",x"78",x"E6",x"08",x"21",x"D8", -- 0x02A8 + x"02",x"28",x"03",x"21",x"E4",x"02",x"06",x"06", -- 0x02B0 + x"11",x"20",x"00",x"DD",x"21",x"AC",x"51",x"7E", -- 0x02B8 + x"DD",x"77",x"00",x"23",x"DD",x"19",x"10",x"F7", -- 0x02C0 + x"06",x"06",x"DD",x"21",x"AD",x"51",x"7E",x"DD", -- 0x02C8 + x"77",x"00",x"23",x"DD",x"19",x"10",x"F7",x"C9", -- 0x02D0 + x"10",x"10",x"10",x"10",x"10",x"10",x"30",x"31", -- 0x02D8 + x"32",x"33",x"34",x"35",x"10",x"10",x"10",x"10", -- 0x02E0 + x"10",x"10",x"4F",x"4E",x"36",x"37",x"4D",x"4C", -- 0x02E8 + x"21",x"A5",x"51",x"11",x"1F",x"00",x"06",x"06", -- 0x02F0 + x"DD",x"21",x"04",x"41",x"3A",x"5F",x"42",x"E6", -- 0x02F8 + x"10",x"28",x"15",x"FD",x"21",x"0A",x"41",x"DD", -- 0x0300 + x"7E",x"00",x"77",x"23",x"FD",x"7E",x"00",x"77", -- 0x0308 + x"19",x"DD",x"23",x"FD",x"23",x"10",x"F0",x"C9", -- 0x0310 + x"FD",x"21",x"1E",x"03",x"18",x"E9",x"4F",x"4E", -- 0x0318 + x"32",x"33",x"4D",x"4C",x"21",x"A5",x"51",x"11", -- 0x0320 + x"1F",x"00",x"06",x"06",x"3E",x"10",x"77",x"23", -- 0x0328 + x"77",x"19",x"10",x"FA",x"C9",x"FE",x"06",x"30", -- 0x0330 + x"4A",x"A7",x"28",x"39",x"3D",x"28",x"22",x"3D", -- 0x0338 + x"87",x"87",x"87",x"87",x"2F",x"E6",x"30",x"C6", -- 0x0340 + x"C0",x"21",x"D8",x"51",x"CD",x"9A",x"03",x"21", -- 0x0348 + x"DA",x"51",x"CD",x"9A",x"03",x"21",x"18",x"52", -- 0x0350 + x"CD",x"9A",x"03",x"21",x"1A",x"52",x"C3",x"9A", -- 0x0358 + x"03",x"21",x"D8",x"51",x"11",x"1C",x"00",x"0E", -- 0x0360 + x"04",x"06",x"04",x"36",x"10",x"23",x"10",x"FB", -- 0x0368 + x"19",x"0D",x"20",x"F5",x"C9",x"CD",x"61",x"03", -- 0x0370 + x"3E",x"58",x"32",x"0D",x"42",x"21",x"F9",x"51", -- 0x0378 + x"C3",x"9A",x"03",x"FE",x"06",x"47",x"3E",x"58", -- 0x0380 + x"28",x"09",x"78",x"FE",x"07",x"3E",x"60",x"28", -- 0x0388 + x"02",x"3E",x"54",x"21",x"F9",x"51",x"18",x"02", -- 0x0390 + x"3E",x"10",x"D5",x"11",x"1F",x"00",x"CF",x"CF", -- 0x0398 + x"D1",x"C9",x"3E",x"10",x"D5",x"11",x"DF",x"FF", -- 0x03A0 + x"CF",x"C6",x"FC",x"18",x"F2",x"A7",x"28",x"48", -- 0x03A8 + x"4F",x"CD",x"03",x"04",x"87",x"81",x"4F",x"06", -- 0x03B0 + x"00",x"21",x"12",x"04",x"09",x"A7",x"06",x"03", -- 0x03B8 + x"1A",x"8E",x"27",x"12",x"13",x"23",x"10",x"F8", -- 0x03C0 + x"D5",x"3A",x"0D",x"40",x"0F",x"30",x"02",x"3E", -- 0x03C8 + x"01",x"CD",x"6A",x"04",x"D1",x"1B",x"21",x"AA", -- 0x03D0 + x"40",x"06",x"03",x"1A",x"BE",x"D8",x"20",x"05", -- 0x03D8 + x"1B",x"2B",x"10",x"F7",x"C9",x"CD",x"03",x"04", -- 0x03E0 + x"21",x"A8",x"40",x"06",x"03",x"1A",x"77",x"13", -- 0x03E8 + x"23",x"10",x"FA",x"3E",x"02",x"C3",x"6A",x"04", -- 0x03F0 + x"CD",x"03",x"04",x"21",x"AB",x"40",x"A7",x"06", -- 0x03F8 + x"03",x"18",x"BD",x"F5",x"3A",x"0D",x"40",x"11", -- 0x0400 + x"A2",x"40",x"0F",x"30",x"03",x"11",x"A5",x"40", -- 0x0408 + x"F1",x"C9",x"00",x"00",x"00",x"20",x"00",x"00", -- 0x0410 + x"40",x"00",x"00",x"60",x"00",x"00",x"80",x"00", -- 0x0418 + x"00",x"00",x"01",x"00",x"20",x"01",x"00",x"40", -- 0x0420 + x"01",x"00",x"60",x"01",x"00",x"00",x"02",x"00", -- 0x0428 + x"00",x"02",x"00",x"00",x"02",x"00",x"00",x"02", -- 0x0430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 + x"00",x"04",x"00",x"00",x"04",x"00",x"F5",x"21", -- 0x0448 + x"A2",x"40",x"A7",x"28",x"09",x"21",x"A5",x"40", -- 0x0450 + x"3D",x"28",x"03",x"21",x"A8",x"40",x"36",x"00", -- 0x0458 + x"23",x"36",x"00",x"23",x"36",x"00",x"F1",x"C3", -- 0x0460 + x"6A",x"04",x"21",x"A4",x"40",x"DD",x"21",x"81", -- 0x0468 + x"53",x"A7",x"28",x"11",x"21",x"A7",x"40",x"DD", -- 0x0470 + x"21",x"21",x"51",x"3D",x"28",x"07",x"21",x"AA", -- 0x0478 + x"40",x"DD",x"21",x"41",x"52",x"11",x"E0",x"FF", -- 0x0480 + x"06",x"03",x"0E",x"04",x"7E",x"0F",x"0F",x"0F", -- 0x0488 + x"0F",x"CD",x"9C",x"04",x"7E",x"CD",x"9C",x"04", -- 0x0490 + x"2B",x"10",x"F1",x"C9",x"E6",x"0F",x"28",x"08", -- 0x0498 + x"0E",x"00",x"DD",x"77",x"00",x"DD",x"19",x"C9", -- 0x04A0 + x"79",x"A7",x"28",x"F6",x"3E",x"10",x"0D",x"18", -- 0x04A8 + x"F1",x"87",x"F5",x"21",x"1E",x"05",x"E6",x"7F", -- 0x04B0 + x"5F",x"16",x"00",x"19",x"5E",x"23",x"56",x"EB", -- 0x04B8 + x"5E",x"23",x"56",x"23",x"EB",x"01",x"E0",x"FF", -- 0x04C0 + x"F1",x"38",x"0E",x"FA",x"E3",x"04",x"1A",x"FE", -- 0x04C8 + x"3F",x"C8",x"D6",x"30",x"77",x"13",x"09",x"18", -- 0x04D0 + x"F5",x"1A",x"FE",x"3F",x"C8",x"36",x"10",x"13", -- 0x04D8 + x"09",x"18",x"F6",x"22",x"B5",x"40",x"ED",x"53", -- 0x04E0 + x"B3",x"40",x"EB",x"7B",x"E6",x"1F",x"47",x"87", -- 0x04E8 + x"C6",x"20",x"6F",x"26",x"40",x"22",x"B1",x"40", -- 0x04F0 + x"CB",x"3B",x"CB",x"3B",x"7A",x"E6",x"03",x"0F", -- 0x04F8 + x"0F",x"B3",x"E6",x"F8",x"4F",x"21",x"00",x"50", -- 0x0500 + x"78",x"85",x"6F",x"11",x"20",x"00",x"43",x"36", -- 0x0508 + x"10",x"19",x"10",x"FB",x"2A",x"B1",x"40",x"71", -- 0x0510 + x"3E",x"01",x"32",x"B0",x"40",x"C9",x"6E",x"05", -- 0x0518 + x"7B",x"05",x"8F",x"05",x"9C",x"05",x"A9",x"05", -- 0x0520 + x"B6",x"05",x"D4",x"05",x"E4",x"05",x"ED",x"05", -- 0x0528 + x"FB",x"05",x"07",x"06",x"0F",x"06",x"16",x"06", -- 0x0530 + x"24",x"06",x"3E",x"06",x"4E",x"06",x"5E",x"06", -- 0x0538 + x"6E",x"06",x"7F",x"06",x"82",x"06",x"85",x"06", -- 0x0540 + x"88",x"06",x"8B",x"06",x"9C",x"06",x"A6",x"06", -- 0x0548 + x"B8",x"06",x"CD",x"06",x"E7",x"06",x"FA",x"06", -- 0x0550 + x"0D",x"07",x"20",x"07",x"33",x"07",x"46",x"07", -- 0x0558 + x"54",x"07",x"62",x"07",x"70",x"07",x"7E",x"07", -- 0x0560 + x"8C",x"07",x"9B",x"07",x"B5",x"07",x"96",x"52", -- 0x0568 + x"47",x"41",x"4D",x"45",x"40",x"40",x"4F",x"56", -- 0x0570 + x"45",x"52",x"3F",x"F1",x"52",x"50",x"55",x"53", -- 0x0578 + x"48",x"40",x"53",x"54",x"41",x"52",x"54",x"40", -- 0x0580 + x"42",x"55",x"54",x"54",x"4F",x"4E",x"3F",x"94", -- 0x0588 + x"52",x"50",x"4C",x"41",x"59",x"45",x"52",x"40", -- 0x0590 + x"4F",x"4E",x"45",x"3F",x"94",x"52",x"50",x"4C", -- 0x0598 + x"41",x"59",x"45",x"52",x"40",x"54",x"57",x"4F", -- 0x05A0 + x"3F",x"80",x"52",x"48",x"49",x"47",x"48",x"40", -- 0x05A8 + x"53",x"43",x"4F",x"52",x"45",x"3F",x"9F",x"53", -- 0x05B0 + x"40",x"43",x"52",x"45",x"44",x"49",x"54",x"40", -- 0x05B8 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x05C0 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x05C8 + x"40",x"40",x"40",x"3F",x"D1",x"52",x"49",x"4E", -- 0x05D0 + x"53",x"45",x"52",x"54",x"40",x"40",x"43",x"4F", -- 0x05D8 + x"49",x"4E",x"53",x"3F",x"1E",x"51",x"40",x"40", -- 0x05E0 + x"40",x"40",x"40",x"40",x"3F",x"5F",x"52",x"43", -- 0x05E8 + x"48",x"41",x"4E",x"43",x"45",x"40",x"54",x"49", -- 0x05F0 + x"4D",x"45",x"3F",x"94",x"52",x"46",x"49",x"52", -- 0x05F8 + x"45",x"40",x"40",x"55",x"46",x"4F",x"3F",x"4D", -- 0x0600 + x"52",x"40",x"40",x"40",x"40",x"40",x"3F",x"26", -- 0x0608 + x"52",x"50",x"4C",x"41",x"59",x"3F",x"89",x"52", -- 0x0610 + x"5B",x"40",x"40",x"4F",x"4D",x"45",x"47",x"41", -- 0x0618 + x"40",x"40",x"5B",x"3F",x"4F",x"53",x"5B",x"40", -- 0x0620 + x"53",x"43",x"4F",x"52",x"45",x"40",x"41",x"44", -- 0x0628 + x"56",x"41",x"4E",x"43",x"45",x"40",x"54",x"41", -- 0x0630 + x"42",x"4C",x"45",x"40",x"5B",x"3F",x"92",x"52", -- 0x0638 + x"34",x"30",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0640 + x"40",x"40",x"40",x"38",x"30",x"3F",x"95",x"52", -- 0x0648 + x"38",x"30",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0650 + x"40",x"40",x"31",x"36",x"30",x"3F",x"98",x"52", -- 0x0658 + x"32",x"30",x"30",x"40",x"40",x"40",x"40",x"40", -- 0x0660 + x"40",x"40",x"34",x"30",x"30",x"3F",x"BC",x"52", -- 0x0668 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0670 + x"40",x"40",x"40",x"40",x"40",x"40",x"3F",x"D5", -- 0x0678 + x"52",x"3F",x"D5",x"52",x"3F",x"D5",x"52",x"3F", -- 0x0680 + x"D5",x"52",x"3F",x"78",x"53",x"42",x"4F",x"4E", -- 0x0688 + x"55",x"53",x"40",x"42",x"45",x"45",x"54",x"4C", -- 0x0690 + x"45",x"40",x"40",x"3F",x"58",x"51",x"30",x"30", -- 0x0698 + x"30",x"40",x"50",x"54",x"53",x"3F",x"D4",x"52", -- 0x06A0 + x"4F",x"4E",x"45",x"40",x"50",x"4C",x"41",x"59", -- 0x06A8 + x"45",x"52",x"40",x"4F",x"4E",x"4C",x"59",x"3F", -- 0x06B0 + x"F4",x"52",x"4F",x"4E",x"45",x"40",x"4F",x"52", -- 0x06B8 + x"40",x"54",x"57",x"4F",x"40",x"50",x"4C",x"41", -- 0x06C0 + x"59",x"45",x"52",x"53",x"3F",x"4D",x"53",x"5B", -- 0x06C8 + x"40",x"53",x"43",x"4F",x"52",x"45",x"40",x"52", -- 0x06D0 + x"41",x"4E",x"4B",x"49",x"4E",x"47",x"40",x"54", -- 0x06D8 + x"41",x"42",x"4C",x"45",x"40",x"5B",x"3F",x"F0", -- 0x06E0 + x"52",x"31",x"53",x"54",x"40",x"40",x"40",x"40", -- 0x06E8 + x"40",x"40",x"40",x"40",x"40",x"40",x"50",x"54", -- 0x06F0 + x"53",x"3F",x"F2",x"52",x"32",x"4E",x"44",x"40", -- 0x06F8 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0700 + x"40",x"50",x"54",x"53",x"3F",x"F4",x"52",x"33", -- 0x0708 + x"52",x"44",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0710 + x"40",x"40",x"40",x"40",x"50",x"54",x"53",x"3F", -- 0x0718 + x"F6",x"52",x"34",x"54",x"48",x"40",x"40",x"40", -- 0x0720 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"50", -- 0x0728 + x"54",x"53",x"3F",x"F8",x"52",x"35",x"54",x"48", -- 0x0730 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0738 + x"40",x"40",x"50",x"54",x"53",x"3F",x"8F",x"52", -- 0x0740 + x"31",x"53",x"54",x"40",x"40",x"41",x"54",x"54", -- 0x0748 + x"41",x"43",x"4B",x"3F",x"8F",x"52",x"32",x"4E", -- 0x0750 + x"44",x"40",x"40",x"41",x"54",x"54",x"41",x"43", -- 0x0758 + x"4B",x"3F",x"8F",x"52",x"33",x"52",x"44",x"40", -- 0x0760 + x"40",x"41",x"54",x"54",x"41",x"43",x"4B",x"3F", -- 0x0768 + x"8F",x"52",x"34",x"54",x"48",x"40",x"40",x"41", -- 0x0770 + x"54",x"54",x"41",x"43",x"4B",x"3F",x"8F",x"52", -- 0x0778 + x"4E",x"45",x"58",x"54",x"40",x"41",x"54",x"54", -- 0x0780 + x"41",x"43",x"4B",x"3F",x"AF",x"52",x"4C",x"41", -- 0x0788 + x"53",x"54",x"40",x"41",x"54",x"54",x"41",x"43", -- 0x0790 + x"4B",x"40",x"3F",x"4F",x"53",x"43",x"48",x"41", -- 0x0798 + x"4C",x"4C",x"45",x"4E",x"47",x"45",x"40",x"4E", -- 0x07A0 + x"45",x"58",x"54",x"40",x"50",x"41",x"54",x"54", -- 0x07A8 + x"45",x"52",x"4E",x"40",x"3F",x"2D",x"52",x"47", -- 0x07B0 + x"4F",x"4F",x"44",x"3F",x"A7",x"CA",x"CB",x"07", -- 0x07B8 + x"3D",x"CA",x"EE",x"07",x"3D",x"CA",x"49",x"08", -- 0x07C0 + x"C3",x"2C",x"08",x"21",x"9F",x"53",x"11",x"E0", -- 0x07C8 + x"FF",x"3A",x"10",x"41",x"FE",x"15",x"38",x"02", -- 0x07D0 + x"3E",x"14",x"47",x"A7",x"28",x"06",x"36",x"CE", -- 0x07D8 + x"19",x"3D",x"20",x"F7",x"3E",x"15",x"90",x"47", -- 0x07E0 + x"36",x"10",x"19",x"10",x"FB",x"C9",x"3E",x"05", -- 0x07E8 + x"CD",x"B1",x"04",x"3A",x"02",x"40",x"FE",x"63", -- 0x07F0 + x"38",x"02",x"3E",x"63",x"CD",x"12",x"08",x"47", -- 0x07F8 + x"E6",x"F0",x"28",x"07",x"0F",x"0F",x"0F",x"0F", -- 0x0800 + x"32",x"9F",x"52",x"78",x"E6",x"0F",x"32",x"7F", -- 0x0808 + x"52",x"C9",x"47",x"E6",x"0F",x"C6",x"00",x"27", -- 0x0810 + x"4F",x"78",x"E6",x"F0",x"28",x"0B",x"0F",x"0F", -- 0x0818 + x"0F",x"0F",x"47",x"AF",x"C6",x"16",x"27",x"10", -- 0x0820 + x"FB",x"81",x"27",x"C9",x"3A",x"1D",x"41",x"47", -- 0x0828 + x"4F",x"21",x"7F",x"50",x"11",x"20",x"00",x"A7", -- 0x0830 + x"28",x"05",x"36",x"CC",x"19",x"10",x"FB",x"3E", -- 0x0838 + x"06",x"91",x"47",x"36",x"10",x"19",x"10",x"FB", -- 0x0840 + x"C9",x"DD",x"21",x"CE",x"43",x"FD",x"21",x"38", -- 0x0848 + x"52",x"0E",x"05",x"06",x"03",x"11",x"E0",x"FF", -- 0x0850 + x"26",x"04",x"DD",x"7E",x"00",x"0F",x"0F",x"0F", -- 0x0858 + x"0F",x"CD",x"77",x"08",x"DD",x"7E",x"00",x"CD", -- 0x0860 + x"77",x"08",x"DD",x"2B",x"10",x"EC",x"11",x"BE", -- 0x0868 + x"00",x"FD",x"19",x"0D",x"20",x"DD",x"C9",x"E6", -- 0x0870 + x"0F",x"6F",x"7C",x"A7",x"20",x"06",x"FD",x"75", -- 0x0878 + x"00",x"FD",x"19",x"C9",x"7D",x"A7",x"20",x"04", -- 0x0880 + x"25",x"FD",x"19",x"C9",x"26",x"00",x"FD",x"75", -- 0x0888 + x"00",x"FD",x"19",x"C9",x"F5",x"C5",x"D5",x"E5", -- 0x0890 + x"DD",x"E5",x"FD",x"E5",x"AF",x"32",x"01",x"70", -- 0x0898 + x"21",x"20",x"40",x"11",x"00",x"58",x"01",x"80", -- 0x08A0 + x"00",x"ED",x"B0",x"3A",x"00",x"78",x"3A",x"15", -- 0x08A8 + x"40",x"32",x"16",x"40",x"3A",x"13",x"40",x"32", -- 0x08B0 + x"15",x"40",x"2A",x"10",x"40",x"22",x"13",x"40", -- 0x08B8 + x"21",x"12",x"40",x"3A",x"00",x"70",x"77",x"2B", -- 0x08C0 + x"3A",x"00",x"68",x"77",x"2B",x"3A",x"00",x"60", -- 0x08C8 + x"77",x"21",x"5F",x"42",x"35",x"CD",x"1A",x"09", -- 0x08D0 + x"CD",x"3D",x"09",x"CD",x"86",x"09",x"CD",x"B8", -- 0x08D8 + x"09",x"3A",x"06",x"40",x"0F",x"38",x"10",x"AF", -- 0x08E0 + x"32",x"C0",x"58",x"32",x"A0",x"58",x"32",x"B0", -- 0x08E8 + x"58",x"32",x"D0",x"58",x"32",x"E0",x"58",x"CD", -- 0x08F0 + x"CC",x"2A",x"21",x"0C",x"09",x"E5",x"3A",x"05", -- 0x08F8 + x"40",x"EF",x"FF",x"09",x"C1",x"0A",x"05",x"0F", -- 0x0900 + x"80",x"11",x"A7",x"11",x"FD",x"E1",x"DD",x"E1", -- 0x0908 + x"E1",x"D1",x"C1",x"3E",x"01",x"32",x"01",x"70", -- 0x0910 + x"F1",x"C9",x"21",x"10",x"40",x"7E",x"23",x"23", -- 0x0918 + x"23",x"B6",x"23",x"23",x"2F",x"A6",x"23",x"A6", -- 0x0920 + x"E6",x"03",x"C8",x"CB",x"47",x"C4",x"38",x"09", -- 0x0928 + x"CB",x"4F",x"C8",x"21",x"81",x"58",x"34",x"C9", -- 0x0930 + x"21",x"85",x"58",x"34",x"C9",x"21",x"84",x"58", -- 0x0938 + x"7E",x"A7",x"20",x"3A",x"23",x"B6",x"C8",x"35", -- 0x0940 + x"2B",x"36",x"0F",x"3A",x"00",x"40",x"CB",x"47", -- 0x0948 + x"28",x"1C",x"21",x"02",x"40",x"7E",x"FE",x"63", -- 0x0950 + x"C8",x"30",x"10",x"34",x"21",x"90",x"58",x"CB", -- 0x0958 + x"CE",x"3A",x"06",x"40",x"0F",x"D8",x"11",x"01", -- 0x0960 + x"07",x"FF",x"C9",x"36",x"63",x"C9",x"21",x"01", -- 0x0968 + x"40",x"CB",x"46",x"28",x"06",x"36",x"00",x"23", -- 0x0970 + x"C3",x"55",x"09",x"36",x"01",x"C9",x"0F",x"0F", -- 0x0978 + x"0F",x"32",x"03",x"60",x"35",x"C9",x"21",x"80", -- 0x0980 + x"58",x"7E",x"A7",x"20",x"6A",x"23",x"B6",x"C8", -- 0x0988 + x"35",x"2B",x"36",x"0F",x"21",x"02",x"40",x"34", -- 0x0990 + x"34",x"34",x"3A",x"00",x"40",x"CB",x"4F",x"20", -- 0x0998 + x"02",x"34",x"34",x"7E",x"FE",x"63",x"C8",x"30", -- 0x09A0 + x"4B",x"21",x"90",x"58",x"CB",x"CE",x"3A",x"06", -- 0x09A8 + x"40",x"0F",x"D8",x"11",x"01",x"07",x"FF",x"C9", -- 0x09B0 + x"21",x"03",x"40",x"5E",x"16",x"06",x"1A",x"1C", -- 0x09B8 + x"73",x"23",x"86",x"3D",x"77",x"3A",x"B0",x"40", -- 0x09C0 + x"0F",x"D0",x"2A",x"B1",x"40",x"7E",x"E6",x"07", -- 0x09C8 + x"20",x"1B",x"EB",x"2A",x"B3",x"40",x"7E",x"FE", -- 0x09D0 + x"3F",x"28",x"11",x"23",x"22",x"B3",x"40",x"D6", -- 0x09D8 + x"30",x"2A",x"B5",x"40",x"77",x"01",x"E0",x"FF", -- 0x09E0 + x"09",x"22",x"B5",x"40",x"EB",x"35",x"C0",x"AF", -- 0x09E8 + x"32",x"B0",x"40",x"C9",x"36",x"63",x"C9",x"0F", -- 0x09F0 + x"0F",x"0F",x"32",x"04",x"68",x"35",x"C9",x"2A", -- 0x09F8 + x"0B",x"40",x"06",x"20",x"3E",x"10",x"D7",x"22", -- 0x0A00 + x"0B",x"40",x"21",x"08",x"40",x"35",x"C0",x"2D", -- 0x0A08 + x"2D",x"36",x"00",x"2D",x"36",x"01",x"AF",x"32", -- 0x0A10 + x"0A",x"40",x"21",x"41",x"0A",x"CD",x"30",x"0A", -- 0x0A18 + x"11",x"04",x"06",x"FF",x"11",x"00",x"05",x"FF", -- 0x0A20 + x"1E",x"02",x"FF",x"AF",x"32",x"80",x"42",x"C9", -- 0x0A28 + x"11",x"21",x"40",x"06",x"20",x"7E",x"12",x"23", -- 0x0A30 + x"1C",x"EB",x"36",x"00",x"EB",x"1C",x"10",x"F5", -- 0x0A38 + x"C9",x"00",x"05",x"00",x"00",x"00",x"01",x"06", -- 0x0A40 + x"00",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0A48 + x"00",x"00",x"00",x"00",x"05",x"05",x"05",x"05", -- 0x0A50 + x"05",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x0A58 + x"06",x"00",x"05",x"00",x"00",x"01",x"01",x"06", -- 0x0A60 + x"03",x"03",x"04",x"04",x"04",x"04",x"00",x"00", -- 0x0A68 + x"00",x"06",x"06",x"06",x"00",x"00",x"00",x"05", -- 0x0A70 + x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x0A78 + x"06",x"00",x"05",x"02",x"02",x"02",x"02",x"06", -- 0x0A80 + x"02",x"00",x"00",x"02",x"01",x"01",x"01",x"01", -- 0x0A88 + x"05",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x0A90 + x"06",x"06",x"06",x"06",x"06",x"00",x"06",x"06", -- 0x0A98 + x"06",x"00",x"05",x"00",x"00",x"00",x"00",x"06", -- 0x0AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 + x"00",x"05",x"05",x"02",x"02",x"06",x"06",x"07", -- 0x0AB0 + x"07",x"04",x"04",x"00",x"00",x"00",x"06",x"06", -- 0x0AB8 + x"06",x"21",x"E9",x"0E",x"E5",x"3A",x"80",x"42", -- 0x0AC0 + x"EF",x"E9",x"0A",x"34",x"0B",x"6F",x"0B",x"90", -- 0x0AC8 + x"0B",x"C2",x"0B",x"D6",x"0B",x"F3",x"0B",x"34", -- 0x0AD0 + x"0C",x"5D",x"0C",x"5E",x"0C",x"5F",x"0C",x"79", -- 0x0AD8 + x"0C",x"F9",x"0C",x"49",x"0D",x"64",x"0D",x"65", -- 0x0AE0 + x"0D",x"AF",x"32",x"C0",x"58",x"32",x"A0",x"58", -- 0x0AE8 + x"32",x"B0",x"58",x"32",x"D0",x"58",x"32",x"E0", -- 0x0AF0 + x"58",x"21",x"20",x"40",x"11",x"21",x"40",x"01", -- 0x0AF8 + x"7F",x"00",x"36",x"00",x"ED",x"B0",x"21",x"00", -- 0x0B00 + x"41",x"11",x"01",x"41",x"01",x"FF",x"01",x"36", -- 0x0B08 + x"00",x"ED",x"B0",x"21",x"A0",x"42",x"11",x"A1", -- 0x0B10 + x"42",x"01",x"FF",x"00",x"36",x"00",x"ED",x"B0", -- 0x0B18 + x"21",x"02",x"50",x"22",x"0B",x"40",x"21",x"09", -- 0x0B20 + x"40",x"36",x"20",x"21",x"80",x"42",x"34",x"AF", -- 0x0B28 + x"32",x"06",x"40",x"C9",x"2A",x"0B",x"40",x"06", -- 0x0B30 + x"1E",x"3E",x"10",x"D7",x"11",x"02",x"00",x"19", -- 0x0B38 + x"22",x"0B",x"40",x"21",x"09",x"40",x"35",x"C0", -- 0x0B40 + x"21",x"81",x"0A",x"CD",x"30",x"0A",x"3E",x"01", -- 0x0B48 + x"32",x"06",x"70",x"32",x"07",x"70",x"21",x"80", -- 0x0B50 + x"42",x"34",x"2C",x"36",x"01",x"2C",x"36",x"0B", -- 0x0B58 + x"2C",x"36",x"1E",x"11",x"01",x"07",x"FF",x"11", -- 0x0B60 + x"11",x"06",x"FF",x"1E",x"07",x"FF",x"C9",x"21", -- 0x0B68 + x"83",x"42",x"35",x"C0",x"36",x"1E",x"2D",x"5E", -- 0x0B70 + x"34",x"16",x"06",x"FF",x"7B",x"FE",x"0E",x"C0", -- 0x0B78 + x"2D",x"2D",x"34",x"21",x"1C",x"0C",x"22",x"84", -- 0x0B80 + x"42",x"21",x"60",x"40",x"22",x"86",x"42",x"C9", -- 0x0B88 + x"21",x"83",x"42",x"35",x"C0",x"36",x"1E",x"2D", -- 0x0B90 + x"5E",x"34",x"16",x"06",x"FF",x"2A",x"84",x"42", -- 0x0B98 + x"ED",x"5B",x"86",x"42",x"01",x"08",x"00",x"ED", -- 0x0BA0 + x"B0",x"22",x"84",x"42",x"ED",x"53",x"86",x"42", -- 0x0BA8 + x"3A",x"82",x"42",x"FE",x"12",x"C0",x"21",x"80", -- 0x0BB0 + x"42",x"34",x"2C",x"2C",x"36",x"0C",x"2C",x"36", -- 0x0BB8 + x"1E",x"C9",x"21",x"83",x"42",x"35",x"C0",x"36", -- 0x0BC0 + x"0F",x"11",x"0E",x"06",x"FF",x"1C",x"FF",x"1C", -- 0x0BC8 + x"FF",x"2D",x"2D",x"2D",x"34",x"C9",x"21",x"83", -- 0x0BD0 + x"42",x"35",x"C0",x"36",x"0F",x"11",x"8E",x"06", -- 0x0BD8 + x"FF",x"1C",x"FF",x"1C",x"FF",x"2D",x"35",x"28", -- 0x0BE0 + x"04",x"2D",x"2D",x"35",x"C9",x"36",x"14",x"2D", -- 0x0BE8 + x"2D",x"34",x"C9",x"21",x"82",x"42",x"35",x"C0", -- 0x0BF0 + x"36",x"96",x"11",x"8D",x"06",x"FF",x"21",x"60", -- 0x0BF8 + x"40",x"11",x"61",x"40",x"01",x"1F",x"00",x"36", -- 0x0C00 + x"00",x"ED",x"B0",x"3A",x"00",x"40",x"C6",x"12", -- 0x0C08 + x"5F",x"16",x"06",x"FF",x"1E",x"06",x"FF",x"21", -- 0x0C10 + x"80",x"42",x"34",x"C9",x"34",x"EB",x"07",x"8B", -- 0x0C18 + x"8B",x"22",x"07",x"8B",x"34",x"EB",x"03",x"A3", -- 0x0C20 + x"8B",x"22",x"03",x"A3",x"34",x"EB",x"01",x"BB", -- 0x0C28 + x"8B",x"22",x"01",x"BB",x"21",x"82",x"42",x"35", -- 0x0C30 + x"C0",x"21",x"A1",x"0A",x"CD",x"30",x"0A",x"11", -- 0x0C38 + x"92",x"06",x"FF",x"1E",x"86",x"FF",x"1E",x"1A", -- 0x0C40 + x"06",x"06",x"FF",x"1C",x"10",x"FC",x"11",x"02", -- 0x0C48 + x"07",x"FF",x"21",x"80",x"42",x"34",x"34",x"34", -- 0x0C50 + x"2C",x"2C",x"36",x"DC",x"C9",x"C9",x"C9",x"3A", -- 0x0C58 + x"5F",x"42",x"0F",x"D8",x"21",x"82",x"42",x"35", -- 0x0C60 + x"C0",x"3E",x"20",x"32",x"09",x"40",x"21",x"02", -- 0x0C68 + x"50",x"22",x"0B",x"40",x"21",x"80",x"42",x"34", -- 0x0C70 + x"C9",x"2A",x"0B",x"40",x"06",x"1D",x"3E",x"10", -- 0x0C78 + x"D7",x"11",x"03",x"00",x"19",x"22",x"0B",x"40", -- 0x0C80 + x"21",x"09",x"40",x"35",x"C0",x"21",x"41",x"0A", -- 0x0C88 + x"CD",x"30",x"0A",x"21",x"E8",x"0C",x"22",x"07", -- 0x0C90 + x"42",x"AF",x"32",x"5F",x"42",x"3E",x"01",x"32", -- 0x0C98 + x"06",x"70",x"32",x"07",x"70",x"AF",x"32",x"0D", -- 0x0CA0 + x"40",x"21",x"92",x"10",x"11",x"00",x"41",x"01", -- 0x0CA8 + x"E0",x"00",x"ED",x"B0",x"21",x"66",x"0D",x"11", -- 0x0CB0 + x"50",x"41",x"01",x"90",x"00",x"ED",x"B0",x"3E", -- 0x0CB8 + x"01",x"32",x"00",x"41",x"3E",x"0B",x"32",x"1A", -- 0x0CC0 + x"41",x"21",x"01",x"00",x"22",x"00",x"42",x"3E", -- 0x0CC8 + x"18",x"32",x"02",x"42",x"3E",x"67",x"32",x"52", -- 0x0CD0 + x"40",x"32",x"54",x"40",x"11",x"00",x"02",x"FF", -- 0x0CD8 + x"21",x"80",x"42",x"34",x"2C",x"36",x"00",x"C9", -- 0x0CE0 + x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x0CE8 + x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x0CF0 + x"FF",x"CD",x"1C",x"15",x"CD",x"85",x"1C",x"CD", -- 0x0CF8 + x"AB",x"1C",x"CD",x"7B",x"18",x"CD",x"8E",x"18", -- 0x0D00 + x"3A",x"16",x"41",x"A7",x"CC",x"E0",x"1C",x"CD", -- 0x0D08 + x"1F",x"18",x"CD",x"13",x"19",x"CD",x"6D",x"0E", -- 0x0D10 + x"CD",x"65",x"1A",x"3A",x"8B",x"42",x"A7",x"CC", -- 0x0D18 + x"E0",x"1B",x"CD",x"41",x"1B",x"3A",x"1A",x"41", -- 0x0D20 + x"A7",x"28",x"07",x"3A",x"11",x"41",x"A7",x"28", -- 0x0D28 + x"01",x"C9",x"21",x"80",x"42",x"34",x"2C",x"2C", -- 0x0D30 + x"36",x"B4",x"AF",x"32",x"90",x"42",x"CD",x"00", -- 0x0D38 + x"12",x"11",x"00",x"06",x"FF",x"1E",x"02",x"FF", -- 0x0D40 + x"C9",x"CD",x"AB",x"1C",x"CD",x"7B",x"18",x"CD", -- 0x0D48 + x"8E",x"18",x"CD",x"C1",x"15",x"3A",x"5F",x"42", -- 0x0D50 + x"0F",x"D8",x"21",x"82",x"42",x"35",x"C0",x"2D", -- 0x0D58 + x"2D",x"36",x"00",x"C9",x"C9",x"C9",x"03",x"03", -- 0x0D60 + x"03",x"03",x"01",x"01",x"03",x"03",x"03",x"03", -- 0x0D68 + x"01",x"01",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x0D70 + x"00",x"00",x"00",x"03",x"01",x"00",x"00",x"00", -- 0x0D78 + x"03",x"03",x"00",x"00",x"00",x"03",x"03",x"00", -- 0x0D80 + x"00",x"00",x"03",x"03",x"03",x"03",x"01",x"01", -- 0x0D88 + x"03",x"03",x"03",x"03",x"01",x"01",x"03",x"03", -- 0x0D90 + x"00",x"00",x"03",x"03",x"03",x"03",x"00",x"00", -- 0x0D98 + x"03",x"03",x"03",x"03",x"00",x"00",x"03",x"03", -- 0x0DA0 + x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0DA8 + x"03",x"03",x"03",x"03",x"03",x"03",x"00",x"00", -- 0x0DB0 + x"03",x"03",x"03",x"03",x"00",x"00",x"03",x"03", -- 0x0DB8 + x"03",x"03",x"00",x"00",x"03",x"03",x"03",x"00", -- 0x0DC0 + x"00",x"00",x"00",x"00",x"03",x"00",x"03",x"03", -- 0x0DC8 + x"00",x"00",x"03",x"00",x"03",x"03",x"00",x"00", -- 0x0DD0 + x"03",x"00",x"03",x"03",x"00",x"00",x"03",x"00", -- 0x0DD8 + x"03",x"03",x"00",x"00",x"03",x"00",x"03",x"03", -- 0x0DE0 + x"00",x"00",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0DE8 + x"03",x"03",x"03",x"03",x"03",x"03",x"3A",x"16", -- 0x0DF0 + x"41",x"A7",x"C8",x"3A",x"88",x"42",x"EF",x"05", -- 0x0DF8 + x"0E",x"1B",x"0E",x"3E",x"0E",x"ED",x"5F",x"0F", -- 0x0E00 + x"3E",x"68",x"38",x"02",x"3E",x"B8",x"21",x"88", -- 0x0E08 + x"42",x"34",x"2C",x"77",x"2C",x"36",x"28",x"2C", -- 0x0E10 + x"36",x"01",x"C9",x"21",x"02",x"42",x"3A",x"89", -- 0x0E18 + x"42",x"BE",x"28",x"11",x"38",x"03",x"34",x"18", -- 0x0E20 + x"01",x"35",x"7E",x"2F",x"C6",x"80",x"32",x"58", -- 0x0E28 + x"40",x"32",x"5A",x"40",x"C9",x"21",x"88",x"42", -- 0x0E30 + x"34",x"AF",x"32",x"8B",x"42",x"C9",x"21",x"64", -- 0x0E38 + x"42",x"CB",x"46",x"C8",x"2C",x"3A",x"02",x"42", -- 0x0E40 + x"C6",x"08",x"96",x"D8",x"FE",x"10",x"D0",x"2C", -- 0x0E48 + x"2C",x"7E",x"FE",x"B8",x"D8",x"21",x"02",x"42", -- 0x0E50 + x"35",x"7E",x"2F",x"C6",x"80",x"32",x"58",x"40", -- 0x0E58 + x"32",x"5A",x"40",x"21",x"8A",x"42",x"35",x"C0", -- 0x0E60 + x"2D",x"2D",x"36",x"00",x"C9",x"3A",x"7C",x"42", -- 0x0E68 + x"0F",x"D8",x"DD",x"21",x"A0",x"42",x"11",x"20", -- 0x0E70 + x"00",x"06",x"08",x"D9",x"CD",x"85",x"0E",x"D9", -- 0x0E78 + x"DD",x"19",x"10",x"F7",x"C9",x"DD",x"CB",x"00", -- 0x0E80 + x"46",x"C8",x"DD",x"CB",x"08",x"46",x"C8",x"DD", -- 0x0E88 + x"CB",x"09",x"46",x"C0",x"DD",x"7E",x"0B",x"FE", -- 0x0E90 + x"80",x"D0",x"DD",x"7E",x"03",x"FE",x"60",x"D8", -- 0x0E98 + x"FE",x"C0",x"D0",x"DD",x"4E",x"06",x"DD",x"46", -- 0x0EA0 + x"08",x"3A",x"02",x"42",x"05",x"28",x"09",x"B9", -- 0x0EA8 + x"D8",x"4F",x"DD",x"7E",x"04",x"91",x"18",x"05", -- 0x0EB0 + x"B9",x"D0",x"DD",x"96",x"04",x"D8",x"47",x"3E", -- 0x0EB8 + x"E0",x"DD",x"96",x"03",x"DD",x"CB",x"19",x"46", -- 0x0EC0 + x"20",x"13",x"DD",x"4E",x"16",x"0D",x"28",x"0D", -- 0x0EC8 + x"0F",x"0F",x"0F",x"E6",x"1F",x"B8",x"C0",x"3E", -- 0x0ED0 + x"01",x"32",x"7C",x"42",x"C9",x"0F",x"0F",x"E6", -- 0x0ED8 + x"3F",x"B8",x"C0",x"3E",x"01",x"32",x"7C",x"42", -- 0x0EE0 + x"C9",x"3A",x"02",x"40",x"A7",x"C8",x"21",x"05", -- 0x0EE8 + x"40",x"34",x"AF",x"32",x"0A",x"40",x"32",x"81", -- 0x0EF0 + x"42",x"21",x"96",x"10",x"11",x"04",x"41",x"01", -- 0x0EF8 + x"0C",x"00",x"ED",x"B0",x"C9",x"21",x"E8",x"0F", -- 0x0F00 + x"E5",x"3A",x"0A",x"40",x"EF",x"13",x"0F",x"49", -- 0x0F08 + x"0F",x"DA",x"0F",x"AF",x"32",x"00",x"41",x"11", -- 0x0F10 + x"00",x"01",x"FF",x"21",x"61",x"0A",x"CD",x"30", -- 0x0F18 + x"0A",x"21",x"60",x"40",x"06",x"40",x"AF",x"D7", -- 0x0F20 + x"21",x"60",x"42",x"D7",x"06",x"40",x"D7",x"21", -- 0x0F28 + x"20",x"41",x"06",x"C0",x"D7",x"32",x"B0",x"40", -- 0x0F30 + x"32",x"06",x"40",x"21",x"02",x"50",x"22",x"0B", -- 0x0F38 + x"40",x"21",x"09",x"40",x"36",x"10",x"2C",x"34", -- 0x0F40 + x"C9",x"2A",x"0B",x"40",x"06",x"1D",x"3E",x"10", -- 0x0F48 + x"D7",x"11",x"03",x"00",x"19",x"06",x"1D",x"D7", -- 0x0F50 + x"19",x"22",x"0B",x"40",x"21",x"09",x"40",x"35", -- 0x0F58 + x"C0",x"2C",x"34",x"3E",x"01",x"32",x"06",x"70", -- 0x0F60 + x"32",x"07",x"70",x"AF",x"32",x"0D",x"40",x"11", -- 0x0F68 + x"01",x"07",x"FF",x"11",x"01",x"06",x"FF",x"1E", -- 0x0F70 + x"16",x"FF",x"1C",x"FF",x"3A",x"17",x"40",x"47", -- 0x0F78 + x"E6",x"0F",x"32",x"78",x"51",x"78",x"E6",x"F0", -- 0x0F80 + x"C8",x"0F",x"0F",x"0F",x"0F",x"32",x"98",x"51", -- 0x0F88 + x"C9",x"3A",x"00",x"42",x"0F",x"D0",x"DD",x"21", -- 0x0F90 + x"A0",x"42",x"11",x"20",x"00",x"06",x"08",x"D9", -- 0x0F98 + x"CD",x"A9",x"0F",x"D9",x"DD",x"19",x"10",x"F7", -- 0x0FA0 + x"C9",x"DD",x"CB",x"00",x"46",x"C8",x"DD",x"7E", -- 0x0FA8 + x"03",x"C6",x"39",x"D6",x"05",x"38",x"10",x"D6", -- 0x0FB0 + x"0C",x"D0",x"3A",x"02",x"42",x"DD",x"96",x"04", -- 0x0FB8 + x"C6",x"0A",x"FE",x"15",x"D0",x"18",x"0B",x"3A", -- 0x0FC0 + x"02",x"42",x"DD",x"96",x"04",x"C6",x"07",x"FE", -- 0x0FC8 + x"0F",x"D0",x"3E",x"01",x"32",x"04",x"42",x"C3", -- 0x0FD0 + x"9C",x"1A",x"3A",x"02",x"40",x"A7",x"C8",x"3D", -- 0x0FD8 + x"11",x"18",x"06",x"28",x"01",x"1C",x"FF",x"C9", -- 0x0FE0 + x"3A",x"11",x"40",x"CB",x"47",x"C2",x"7C",x"10", -- 0x0FE8 + x"CB",x"4F",x"C8",x"3A",x"02",x"40",x"FE",x"02", -- 0x0FF0 + x"D8",x"D6",x"02",x"32",x"02",x"40",x"21",x"00", -- 0x0FF8 + x"01",x"22",x"0D",x"40",x"AF",x"32",x"0A",x"40", -- 0x1000 + x"3E",x"03",x"32",x"05",x"40",x"3E",x"01",x"32", -- 0x1008 + x"06",x"40",x"11",x"04",x"06",x"FF",x"21",x"92", -- 0x1010 + x"10",x"11",x"00",x"41",x"01",x"E0",x"00",x"ED", -- 0x1018 + x"B0",x"21",x"92",x"10",x"11",x"E0",x"41",x"01", -- 0x1020 + x"20",x"00",x"ED",x"B0",x"DD",x"21",x"20",x"41", -- 0x1028 + x"21",x"10",x"42",x"0E",x"30",x"06",x"04",x"CB", -- 0x1030 + x"26",x"CB",x"26",x"DD",x"CB",x"00",x"46",x"28", -- 0x1038 + x"02",x"CB",x"C6",x"DD",x"CB",x"00",x"4E",x"28", -- 0x1040 + x"02",x"CB",x"CE",x"DD",x"23",x"10",x"E8",x"23", -- 0x1048 + x"0D",x"20",x"E2",x"3E",x"01",x"32",x"00",x"41", -- 0x1050 + x"32",x"E0",x"41",x"3A",x"07",x"40",x"32",x"1D", -- 0x1058 + x"41",x"32",x"FD",x"41",x"AF",x"32",x"52",x"40", -- 0x1060 + x"32",x"54",x"40",x"21",x"A0",x"58",x"CB",x"C6", -- 0x1068 + x"11",x"00",x"04",x"FF",x"3A",x"0E",x"40",x"0F", -- 0x1070 + x"D0",x"1C",x"FF",x"C9",x"3A",x"02",x"40",x"A7", -- 0x1078 + x"28",x"0A",x"3D",x"32",x"02",x"40",x"21",x"00", -- 0x1080 + x"00",x"C3",x"01",x"10",x"3E",x"01",x"32",x"05", -- 0x1088 + x"40",x"C9",x"00",x"80",x"00",x"06",x"6C",x"64", -- 0x1090 + x"64",x"64",x"64",x"65",x"30",x"31",x"32",x"33", -- 0x1098 + x"34",x"35",x"00",x"2E",x"00",x"00",x"00",x"00", -- 0x10A0 + x"00",x"1C",x"20",x"24",x"60",x"30",x"00",x"03", -- 0x10A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10D8 + x"00",x"00",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x10E0 + x"01",x"01",x"01",x"01",x"01",x"01",x"00",x"00", -- 0x10E8 + x"00",x"00",x"01",x"01",x"00",x"00",x"00",x"01", -- 0x10F0 + x"01",x"00",x"00",x"00",x"01",x"01",x"00",x"00", -- 0x10F8 + x"00",x"01",x"01",x"00",x"00",x"00",x"01",x"01", -- 0x1100 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x1108 + x"01",x"01",x"01",x"01",x"00",x"00",x"01",x"01", -- 0x1110 + x"01",x"01",x"00",x"00",x"01",x"01",x"01",x"01", -- 0x1118 + x"00",x"00",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x1120 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x1128 + x"01",x"01",x"00",x"00",x"01",x"01",x"01",x"01", -- 0x1130 + x"00",x"00",x"01",x"01",x"01",x"01",x"00",x"00", -- 0x1138 + x"01",x"01",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x1140 + x"01",x"00",x"01",x"01",x"00",x"00",x"01",x"00", -- 0x1148 + x"01",x"01",x"00",x"00",x"01",x"00",x"01",x"01", -- 0x1150 + x"00",x"00",x"01",x"00",x"01",x"01",x"00",x"00", -- 0x1158 + x"01",x"00",x"01",x"01",x"00",x"00",x"01",x"01", -- 0x1160 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x1168 + x"01",x"01",x"21",x"09",x"40",x"35",x"C0",x"36", -- 0x1170 + x"00",x"11",x"60",x"06",x"FF",x"2C",x"34",x"C9", -- 0x1178 + x"CD",x"85",x"1C",x"CD",x"AB",x"1C",x"CD",x"7B", -- 0x1180 + x"18",x"CD",x"8E",x"18",x"CD",x"1C",x"15",x"3A", -- 0x1188 + x"0A",x"40",x"EF",x"CE",x"11",x"0F",x"12",x"28", -- 0x1190 + x"12",x"A6",x"12",x"B7",x"12",x"F1",x"12",x"A0", -- 0x1198 + x"13",x"D1",x"13",x"6C",x"15",x"AB",x"15",x"CD", -- 0x11A0 + x"85",x"1C",x"CD",x"AB",x"1C",x"CD",x"7B",x"18", -- 0x11A8 + x"CD",x"8E",x"18",x"CD",x"1C",x"15",x"3A",x"0A", -- 0x11B0 + x"40",x"EF",x"CE",x"11",x"0F",x"12",x"69",x"12", -- 0x11B8 + x"A6",x"12",x"B7",x"12",x"F1",x"12",x"13",x"14", -- 0x11C0 + x"35",x"14",x"6C",x"15",x"AB",x"15",x"AF",x"32", -- 0x11C8 + x"B0",x"58",x"32",x"D0",x"58",x"32",x"E0",x"58", -- 0x11D0 + x"AF",x"32",x"81",x"42",x"21",x"00",x"42",x"06", -- 0x11D8 + x"10",x"D7",x"21",x"60",x"42",x"D7",x"06",x"40", -- 0x11E0 + x"D7",x"CD",x"00",x"12",x"21",x"89",x"1B",x"22", -- 0x11E8 + x"07",x"42",x"21",x"0A",x"40",x"34",x"2D",x"36", -- 0x11F0 + x"20",x"21",x"00",x"50",x"22",x"0B",x"40",x"C9", -- 0x11F8 + x"21",x"60",x"40",x"06",x"40",x"AF",x"D7",x"AF", -- 0x1200 + x"32",x"52",x"40",x"32",x"54",x"40",x"C9",x"2A", -- 0x1208 + x"0B",x"40",x"06",x"20",x"3E",x"10",x"D7",x"22", -- 0x1210 + x"0B",x"40",x"21",x"09",x"40",x"35",x"C0",x"2C", -- 0x1218 + x"34",x"21",x"41",x"0A",x"CD",x"30",x"0A",x"C9", -- 0x1220 + x"AF",x"32",x"5F",x"42",x"3E",x"01",x"32",x"06", -- 0x1228 + x"70",x"32",x"07",x"70",x"AF",x"32",x"0D",x"40", -- 0x1230 + x"21",x"0A",x"40",x"34",x"2D",x"36",x"00",x"3A", -- 0x1238 + x"0E",x"40",x"0F",x"38",x"1E",x"11",x"00",x"05", -- 0x1240 + x"FF",x"1E",x"02",x"FF",x"14",x"FF",x"1E",x"04", -- 0x1248 + x"FF",x"3A",x"14",x"41",x"A7",x"C2",x"5B",x"12", -- 0x1250 + x"1E",x"60",x"FF",x"11",x"03",x"07",x"FF",x"1E", -- 0x1258 + x"00",x"FF",x"C9",x"11",x"01",x"05",x"FF",x"18", -- 0x1260 + x"DC",x"AF",x"32",x"5F",x"42",x"3A",x"0F",x"40", -- 0x1268 + x"0F",x"30",x"07",x"AF",x"32",x"06",x"70",x"32", -- 0x1270 + x"07",x"70",x"3E",x"01",x"32",x"0D",x"40",x"21", -- 0x1278 + x"0A",x"40",x"34",x"2D",x"36",x"00",x"11",x"00", -- 0x1280 + x"05",x"FF",x"1C",x"FF",x"1C",x"FF",x"11",x"03", -- 0x1288 + x"06",x"FF",x"1C",x"FF",x"3A",x"14",x"41",x"A7", -- 0x1290 + x"C2",x"9E",x"12",x"1E",x"60",x"FF",x"11",x"03", -- 0x1298 + x"07",x"FF",x"1E",x"00",x"FF",x"C9",x"21",x"09", -- 0x12A0 + x"40",x"35",x"C0",x"36",x"14",x"2C",x"34",x"11", -- 0x12A8 + x"82",x"06",x"FF",x"1E",x"A0",x"FF",x"C9",x"21", -- 0x12B0 + x"09",x"40",x"35",x"C0",x"36",x"0A",x"2C",x"34", -- 0x12B8 + x"21",x"60",x"42",x"06",x"20",x"AF",x"D7",x"21", -- 0x12C0 + x"01",x"00",x"22",x"00",x"42",x"3E",x"18",x"32", -- 0x12C8 + x"02",x"42",x"AF",x"32",x"52",x"40",x"32",x"54", -- 0x12D0 + x"40",x"3A",x"07",x"40",x"A7",x"20",x"05",x"3E", -- 0x12D8 + x"02",x"32",x"1D",x"41",x"21",x"1D",x"41",x"35", -- 0x12E0 + x"11",x"03",x"07",x"FF",x"11",x"00",x"02",x"FF", -- 0x12E8 + x"C9",x"CD",x"4D",x"13",x"CD",x"76",x"17",x"CD", -- 0x12F0 + x"54",x"15",x"CD",x"AF",x"17",x"CD",x"C5",x"17", -- 0x12F8 + x"CD",x"1F",x"18",x"CD",x"13",x"19",x"CD",x"91", -- 0x1300 + x"0F",x"CD",x"DC",x"18",x"CD",x"65",x"1A",x"CD", -- 0x1308 + x"0A",x"1B",x"CD",x"A2",x"1B",x"CD",x"E0",x"1B", -- 0x1310 + x"CD",x"5E",x"1C",x"CD",x"41",x"1B",x"3A",x"1A", -- 0x1318 + x"41",x"A7",x"28",x"43",x"3A",x"11",x"41",x"A7", -- 0x1320 + x"28",x"4E",x"21",x"00",x"42",x"CB",x"46",x"C0", -- 0x1328 + x"23",x"CB",x"46",x"C0",x"3A",x"7C",x"42",x"0F", -- 0x1330 + x"D8",x"3A",x"60",x"42",x"47",x"3A",x"64",x"42", -- 0x1338 + x"4F",x"3A",x"68",x"42",x"B0",x"B1",x"0F",x"D8", -- 0x1340 + x"21",x"0A",x"40",x"34",x"C9",x"21",x"A0",x"42", -- 0x1348 + x"11",x"20",x"00",x"06",x"08",x"AF",x"B6",x"19", -- 0x1350 + x"10",x"FC",x"0F",x"21",x"C0",x"58",x"CB",x"D6", -- 0x1358 + x"D8",x"21",x"C0",x"58",x"CB",x"96",x"C9",x"3A", -- 0x1360 + x"01",x"42",x"0F",x"D8",x"AF",x"32",x"1D",x"41", -- 0x1368 + x"32",x"00",x"42",x"21",x"0A",x"40",x"34",x"C9", -- 0x1370 + x"21",x"00",x"42",x"CB",x"46",x"20",x"06",x"2C", -- 0x1378 + x"CB",x"46",x"C0",x"18",x"AF",x"AF",x"21",x"60", -- 0x1380 + x"42",x"06",x"20",x"D7",x"21",x"80",x"40",x"06", -- 0x1388 + x"20",x"D7",x"21",x"B7",x"40",x"36",x"00",x"23", -- 0x1390 + x"36",x"32",x"3E",x"08",x"32",x"0A",x"40",x"C9", -- 0x1398 + x"3A",x"1D",x"41",x"A7",x"20",x"14",x"11",x"00", -- 0x13A0 + x"06",x"FF",x"1E",x"02",x"FF",x"21",x"0A",x"40", -- 0x13A8 + x"36",x"09",x"2B",x"36",x"B4",x"AF",x"32",x"90", -- 0x13B0 + x"42",x"C9",x"3A",x"0E",x"40",x"0F",x"38",x"09", -- 0x13B8 + x"21",x"0A",x"40",x"36",x"04",x"2B",x"36",x"64", -- 0x13C0 + x"C9",x"21",x"0A",x"40",x"34",x"2D",x"36",x"64", -- 0x13C8 + x"C9",x"21",x"09",x"40",x"35",x"C0",x"3A",x"1D", -- 0x13D0 + x"41",x"A7",x"20",x"0C",x"3A",x"0E",x"40",x"0F", -- 0x13D8 + x"38",x"15",x"3E",x"01",x"32",x"05",x"40",x"C9", -- 0x13E0 + x"3A",x"FD",x"41",x"A7",x"20",x"15",x"21",x"0A", -- 0x13E8 + x"40",x"36",x"04",x"2B",x"36",x"01",x"C9",x"3A", -- 0x13F0 + x"FD",x"41",x"A7",x"20",x"06",x"3E",x"01",x"32", -- 0x13F8 + x"05",x"40",x"C9",x"CD",x"6B",x"14",x"CD",x"AC", -- 0x1400 + x"14",x"AF",x"32",x"0A",x"40",x"3E",x"04",x"32", -- 0x1408 + x"05",x"40",x"C9",x"3A",x"1D",x"41",x"A7",x"20", -- 0x1410 + x"14",x"11",x"00",x"06",x"FF",x"1E",x"03",x"FF", -- 0x1418 + x"21",x"0A",x"40",x"36",x"09",x"2B",x"36",x"B4", -- 0x1420 + x"AF",x"32",x"90",x"42",x"C9",x"21",x"0A",x"40", -- 0x1428 + x"34",x"2D",x"36",x"64",x"C9",x"21",x"09",x"40", -- 0x1430 + x"35",x"C0",x"3A",x"1D",x"41",x"A7",x"20",x"0C", -- 0x1438 + x"3A",x"FD",x"41",x"A7",x"20",x"15",x"3E",x"01", -- 0x1440 + x"32",x"05",x"40",x"C9",x"3A",x"FD",x"41",x"A7", -- 0x1448 + x"20",x"09",x"21",x"0A",x"40",x"36",x"04",x"2B", -- 0x1450 + x"36",x"01",x"C9",x"CD",x"6B",x"14",x"CD",x"AC", -- 0x1458 + x"14",x"AF",x"32",x"0A",x"40",x"3E",x"03",x"32", -- 0x1460 + x"05",x"40",x"C9",x"AF",x"21",x"A0",x"42",x"11", -- 0x1468 + x"20",x"00",x"06",x"08",x"CB",x"46",x"28",x"01", -- 0x1470 + x"3C",x"19",x"10",x"F8",x"47",x"21",x"12",x"41", -- 0x1478 + x"7E",x"90",x"77",x"21",x"96",x"10",x"11",x"04", -- 0x1480 + x"41",x"01",x"0C",x"00",x"ED",x"B0",x"3A",x"12", -- 0x1488 + x"41",x"A7",x"C8",x"47",x"16",x"00",x"DD",x"21", -- 0x1490 + x"2A",x"20",x"21",x"04",x"41",x"DD",x"5E",x"00", -- 0x1498 + x"19",x"DD",x"7E",x"01",x"77",x"1E",x"05",x"DD", -- 0x14A0 + x"19",x"10",x"EF",x"C9",x"21",x"00",x"41",x"DD", -- 0x14A8 + x"21",x"E0",x"41",x"06",x"20",x"DD",x"7E",x"00", -- 0x14B0 + x"4E",x"DD",x"71",x"00",x"77",x"DD",x"23",x"23", -- 0x14B8 + x"10",x"F3",x"DD",x"21",x"20",x"41",x"FD",x"21", -- 0x14C0 + x"10",x"42",x"06",x"30",x"FD",x"4E",x"00",x"3E", -- 0x14C8 + x"03",x"A1",x"6F",x"CB",x"09",x"CB",x"09",x"3E", -- 0x14D0 + x"03",x"A1",x"67",x"CB",x"09",x"CB",x"09",x"3E", -- 0x14D8 + x"03",x"A1",x"5F",x"CB",x"09",x"CB",x"09",x"3E", -- 0x14E0 + x"03",x"A1",x"57",x"FD",x"23",x"0E",x"04",x"CB", -- 0x14E8 + x"27",x"CB",x"27",x"DD",x"CB",x"00",x"4E",x"28", -- 0x14F0 + x"02",x"CB",x"CF",x"DD",x"CB",x"00",x"46",x"28", -- 0x14F8 + x"02",x"CB",x"C7",x"DD",x"23",x"0D",x"20",x"E7", -- 0x1500 + x"DD",x"72",x"FC",x"DD",x"73",x"FD",x"DD",x"74", -- 0x1508 + x"FE",x"DD",x"75",x"FF",x"FD",x"77",x"FF",x"05", -- 0x1510 + x"C2",x"CC",x"14",x"C9",x"3A",x"00",x"42",x"0F", -- 0x1518 + x"D0",x"3A",x"5F",x"42",x"E6",x"0F",x"C0",x"3A", -- 0x1520 + x"0D",x"42",x"16",x"02",x"FE",x"58",x"28",x"09", -- 0x1528 + x"FE",x"60",x"28",x"0E",x"FE",x"54",x"28",x"13", -- 0x1530 + x"C9",x"3E",x"60",x"32",x"0D",x"42",x"1E",x"07", -- 0x1538 + x"FF",x"C9",x"3E",x"54",x"32",x"0D",x"42",x"1E", -- 0x1540 + x"08",x"FF",x"C9",x"3E",x"58",x"32",x"0D",x"42", -- 0x1548 + x"1E",x"06",x"FF",x"C9",x"3A",x"1C",x"41",x"0F", -- 0x1550 + x"D0",x"3E",x"01",x"32",x"13",x"41",x"3A",x"5F", -- 0x1558 + x"42",x"E6",x"10",x"11",x"08",x"06",x"28",x"02", -- 0x1560 + x"1E",x"88",x"FF",x"C9",x"3A",x"16",x"41",x"A7", -- 0x1568 + x"CC",x"E0",x"1C",x"3A",x"B7",x"40",x"EF",x"68", -- 0x1570 + x"26",x"BC",x"26",x"F8",x"26",x"03",x"27",x"0F", -- 0x1578 + x"27",x"2B",x"27",x"78",x"27",x"79",x"27",x"AF", -- 0x1580 + x"27",x"E0",x"27",x"0D",x"28",x"84",x"28",x"A9", -- 0x1588 + x"28",x"B7",x"28",x"D2",x"28",x"DF",x"28",x"01", -- 0x1590 + x"29",x"10",x"29",x"79",x"29",x"93",x"29",x"B6", -- 0x1598 + x"29",x"C5",x"29",x"DF",x"29",x"F1",x"29",x"0A", -- 0x15A0 + x"2A",x"53",x"2A",x"CD",x"C1",x"15",x"3A",x"5F", -- 0x15A8 + x"42",x"0F",x"D8",x"21",x"09",x"40",x"35",x"C0", -- 0x15B0 + x"36",x"0A",x"2C",x"36",x"07",x"CD",x"23",x"17", -- 0x15B8 + x"C9",x"CD",x"D2",x"15",x"3A",x"90",x"42",x"EF", -- 0x15C0 + x"0B",x"16",x"32",x"16",x"8A",x"16",x"D9",x"16", -- 0x15C8 + x"F6",x"16",x"3A",x"5F",x"42",x"E6",x"07",x"C0", -- 0x15D0 + x"21",x"9B",x"42",x"7E",x"3C",x"FE",x"06",x"20", -- 0x15D8 + x"01",x"AF",x"77",x"21",x"1D",x"17",x"4F",x"06", -- 0x15E0 + x"00",x"09",x"7E",x"32",x"31",x"40",x"32",x"33", -- 0x15E8 + x"40",x"32",x"35",x"40",x"C9",x"21",x"4C",x"50", -- 0x15F0 + x"22",x"92",x"42",x"22",x"96",x"42",x"21",x"5E", -- 0x15F8 + x"50",x"22",x"94",x"42",x"21",x"AC",x"53",x"22", -- 0x1600 + x"98",x"42",x"C9",x"CD",x"00",x"12",x"CD",x"F5", -- 0x1608 + x"15",x"21",x"90",x"42",x"34",x"2C",x"36",x"32", -- 0x1610 + x"21",x"9A",x"42",x"36",x"07",x"2C",x"36",x"00", -- 0x1618 + x"2C",x"36",x"00",x"21",x"A0",x"58",x"CB",x"CE", -- 0x1620 + x"21",x"C0",x"58",x"CB",x"96",x"AF",x"32",x"B0", -- 0x1628 + x"58",x"C9",x"21",x"91",x"42",x"35",x"C0",x"36", -- 0x1630 + x"01",x"2D",x"34",x"21",x"39",x"40",x"D9",x"06", -- 0x1638 + x"00",x"3A",x"9C",x"42",x"4F",x"21",x"85",x"16", -- 0x1640 + x"09",x"7E",x"D9",x"06",x"13",x"77",x"2C",x"2C", -- 0x1648 + x"10",x"FB",x"3E",x"01",x"32",x"81",x"42",x"AF", -- 0x1650 + x"06",x"18",x"21",x"30",x"40",x"77",x"2C",x"2C", -- 0x1658 + x"10",x"FB",x"21",x"4C",x"50",x"0E",x"1C",x"06", -- 0x1660 + x"13",x"36",x"10",x"23",x"10",x"FB",x"11",x"0D", -- 0x1668 + x"00",x"19",x"0D",x"20",x"F2",x"11",x"00",x"06", -- 0x1670 + x"FF",x"3A",x"0D",x"40",x"1E",x"02",x"0F",x"D2", -- 0x1678 + x"38",x"00",x"1C",x"FF",x"C9",x"06",x"02",x"03", -- 0x1680 + x"07",x"00",x"21",x"91",x"42",x"35",x"C0",x"36", -- 0x1688 + x"03",x"06",x"13",x"3E",x"C8",x"2A",x"96",x"42", -- 0x1690 + x"ED",x"5B",x"98",x"42",x"77",x"12",x"13",x"23", -- 0x1698 + x"10",x"FA",x"06",x"28",x"2A",x"92",x"42",x"11", -- 0x16A0 + x"20",x"00",x"77",x"19",x"10",x"FC",x"2A",x"94", -- 0x16A8 + x"42",x"06",x"1C",x"77",x"19",x"10",x"FC",x"21", -- 0x16B0 + x"92",x"42",x"34",x"2C",x"2C",x"35",x"2A",x"96", -- 0x16B8 + x"42",x"19",x"22",x"96",x"42",x"2A",x"98",x"42", -- 0x16C0 + x"11",x"E0",x"FF",x"19",x"22",x"98",x"42",x"21", -- 0x16C8 + x"9A",x"42",x"35",x"C0",x"21",x"90",x"42",x"34", -- 0x16D0 + x"C9",x"CD",x"F5",x"15",x"21",x"90",x"42",x"36", -- 0x16D8 + x"01",x"2C",x"36",x"0A",x"21",x"9A",x"42",x"36", -- 0x16E0 + x"07",x"2C",x"2C",x"34",x"7E",x"FE",x"05",x"C0", -- 0x16E8 + x"3E",x"04",x"32",x"90",x"42",x"C9",x"3A",x"5F", -- 0x16F0 + x"42",x"E6",x"07",x"C0",x"3A",x"9B",x"42",x"2E", -- 0x16F8 + x"13",x"11",x"39",x"40",x"06",x"00",x"D6",x"01", -- 0x1700 + x"30",x"02",x"3E",x"05",x"4F",x"E5",x"F5",x"21", -- 0x1708 + x"1D",x"17",x"09",x"7E",x"12",x"1C",x"1C",x"F1", -- 0x1710 + x"E1",x"2D",x"20",x"EA",x"C9",x"00",x"03",x"02", -- 0x1718 + x"06",x"07",x"04",x"11",x"FD",x"FF",x"DD",x"21", -- 0x1720 + x"A4",x"40",x"3A",x"0D",x"40",x"0F",x"30",x"04", -- 0x1728 + x"DD",x"21",x"A7",x"40",x"FD",x"21",x"CE",x"43", -- 0x1730 + x"06",x"05",x"FD",x"7E",x"00",x"DD",x"BE",x"00", -- 0x1738 + x"20",x"0F",x"FD",x"7E",x"FF",x"DD",x"BE",x"FF", -- 0x1740 + x"20",x"07",x"FD",x"7E",x"FE",x"DD",x"BE",x"FE", -- 0x1748 + x"C8",x"30",x"04",x"FD",x"19",x"10",x"E3",x"3E", -- 0x1750 + x"05",x"90",x"C8",x"21",x"CE",x"43",x"11",x"D1", -- 0x1758 + x"43",x"47",x"87",x"80",x"06",x"00",x"4F",x"ED", -- 0x1760 + x"B8",x"2C",x"EB",x"DD",x"E5",x"E1",x"2D",x"2D", -- 0x1768 + x"01",x"03",x"00",x"ED",x"B0",x"C9",x"3A",x"1E", -- 0x1770 + x"41",x"0F",x"D8",x"21",x"A4",x"40",x"3A",x"0D", -- 0x1778 + x"40",x"0F",x"30",x"03",x"21",x"A7",x"40",x"3A", -- 0x1780 + x"17",x"40",x"47",x"7E",x"E6",x"0F",x"07",x"07", -- 0x1788 + x"07",x"07",x"4F",x"2D",x"7E",x"E6",x"F0",x"0F", -- 0x1790 + x"0F",x"0F",x"0F",x"B1",x"B8",x"D8",x"21",x"90", -- 0x1798 + x"58",x"CB",x"C6",x"21",x"1D",x"41",x"34",x"11", -- 0x17A0 + x"03",x"07",x"FF",x"2C",x"36",x"01",x"C9",x"3A", -- 0x17A8 + x"16",x"41",x"A7",x"C0",x"21",x"1C",x"41",x"7E", -- 0x17B0 + x"0F",x"D2",x"E0",x"1C",x"11",x"88",x"06",x"FF", -- 0x17B8 + x"36",x"00",x"C3",x"E0",x"1C",x"21",x"00",x"42", -- 0x17C0 + x"CB",x"46",x"28",x"3A",x"2C",x"2C",x"3A",x"0F", -- 0x17C8 + x"40",x"0F",x"30",x"06",x"3A",x"0D",x"40",x"0F", -- 0x17D0 + x"38",x"3F",x"3A",x"10",x"40",x"47",x"CB",x"5F", -- 0x17D8 + x"28",x"07",x"7E",x"FE",x"17",x"38",x"02",x"35", -- 0x17E0 + x"35",x"CB",x"50",x"28",x"07",x"7E",x"FE",x"E9", -- 0x17E8 + x"30",x"02",x"34",x"34",x"7E",x"2F",x"C6",x"80", -- 0x17F0 + x"0E",x"06",x"21",x"50",x"40",x"06",x"04",x"77", -- 0x17F8 + x"2C",x"71",x"2C",x"10",x"FA",x"C9",x"2C",x"CB", -- 0x1800 + x"46",x"20",x"05",x"2C",x"36",x"00",x"18",x"E4", -- 0x1808 + x"2C",x"7E",x"2F",x"C6",x"80",x"0E",x"07",x"18", -- 0x1810 + x"E1",x"3A",x"11",x"40",x"47",x"18",x"BE",x"21", -- 0x1818 + x"7C",x"42",x"CB",x"46",x"23",x"23",x"23",x"28", -- 0x1820 + x"0C",x"7E",x"D6",x"05",x"77",x"FE",x"34",x"30", -- 0x1828 + x"16",x"AF",x"32",x"7C",x"42",x"36",x"C7",x"2D", -- 0x1830 + x"2D",x"3A",x"00",x"42",x"0F",x"30",x"06",x"3A", -- 0x1838 + x"02",x"42",x"77",x"18",x"02",x"36",x"00",x"DD", -- 0x1840 + x"21",x"9D",x"40",x"FD",x"21",x"7D",x"42",x"3A", -- 0x1848 + x"0F",x"40",x"0F",x"30",x"17",x"3A",x"0D",x"40", -- 0x1850 + x"0F",x"30",x"11",x"FD",x"7E",x"02",x"2F",x"C6", -- 0x1858 + x"FC",x"DD",x"77",x"02",x"FD",x"7E",x"00",x"2F", -- 0x1860 + x"DD",x"77",x"00",x"C9",x"FD",x"7E",x"02",x"3D", -- 0x1868 + x"DD",x"77",x"02",x"FD",x"7E",x"00",x"2F",x"DD", -- 0x1870 + x"77",x"00",x"C9",x"DD",x"21",x"A0",x"42",x"11", -- 0x1878 + x"20",x"00",x"06",x"08",x"D9",x"CD",x"1D",x"1D", -- 0x1880 + x"D9",x"DD",x"19",x"10",x"F7",x"C9",x"DD",x"21", -- 0x1888 + x"A0",x"42",x"FD",x"21",x"60",x"40",x"01",x"08", -- 0x1890 + x"08",x"DD",x"CB",x"00",x"46",x"28",x"27",x"DD", -- 0x1898 + x"7E",x"16",x"FD",x"77",x"02",x"DD",x"7E",x"03", -- 0x18A0 + x"91",x"FD",x"77",x"03",x"DD",x"7E",x"04",x"2F", -- 0x18A8 + x"91",x"FD",x"77",x"00",x"DD",x"7E",x"12",x"FD", -- 0x18B0 + x"77",x"01",x"11",x"20",x"00",x"DD",x"19",x"1E", -- 0x18B8 + x"04",x"FD",x"19",x"10",x"D4",x"C9",x"DD",x"CB", -- 0x18C0 + x"01",x"46",x"28",x"06",x"FD",x"36",x"02",x"07", -- 0x18C8 + x"18",x"CD",x"FD",x"36",x"03",x"F8",x"FD",x"36", -- 0x18D0 + x"00",x"F8",x"18",x"DE",x"3A",x"00",x"42",x"0F", -- 0x18D8 + x"D0",x"3A",x"7C",x"42",x"0F",x"D8",x"3A",x"0F", -- 0x18E0 + x"40",x"0F",x"30",x"06",x"3A",x"0D",x"40",x"0F", -- 0x18E8 + x"38",x"17",x"3A",x"13",x"40",x"2F",x"47",x"3A", -- 0x18F0 + x"10",x"40",x"A0",x"E6",x"10",x"C8",x"3E",x"01", -- 0x18F8 + x"32",x"7C",x"42",x"21",x"C0",x"58",x"CB",x"C6", -- 0x1900 + x"C9",x"3A",x"14",x"40",x"2F",x"47",x"3A",x"11", -- 0x1908 + x"40",x"18",x"E7",x"CD",x"89",x"19",x"CD",x"DC", -- 0x1910 + x"19",x"CD",x"FB",x"19",x"CD",x"3E",x"1A",x"C3", -- 0x1918 + x"22",x"19",x"06",x"08",x"21",x"60",x"42",x"CB", -- 0x1920 + x"46",x"20",x"07",x"2C",x"2C",x"2C",x"2C",x"10", -- 0x1928 + x"F6",x"C9",x"2C",x"2C",x"2C",x"7E",x"C6",x"20", -- 0x1930 + x"D6",x"10",x"30",x"F2",x"2D",x"2D",x"7E",x"C6", -- 0x1938 + x"E0",x"D6",x"20",x"30",x"05",x"11",x"20",x"41", -- 0x1940 + x"18",x"14",x"D6",x"30",x"D6",x"20",x"30",x"05", -- 0x1948 + x"11",x"30",x"41",x"18",x"09",x"D6",x"30",x"D6", -- 0x1950 + x"20",x"30",x"D1",x"11",x"40",x"41",x"C6",x"20", -- 0x1958 + x"E6",x"F8",x"1F",x"83",x"5F",x"2C",x"2C",x"7E", -- 0x1960 + x"D6",x"E0",x"E6",x"0C",x"1F",x"1F",x"83",x"5F", -- 0x1968 + x"1A",x"CB",x"4F",x"28",x"B9",x"4F",x"7D",x"FE", -- 0x1970 + x"7C",x"79",x"30",x"03",x"CB",x"D7",x"12",x"0E", -- 0x1978 + x"04",x"AF",x"77",x"2D",x"0D",x"20",x"FB",x"18", -- 0x1980 + x"A2",x"DD",x"21",x"60",x"42",x"11",x"04",x"00", -- 0x1988 + x"06",x"04",x"CD",x"9A",x"19",x"DD",x"19",x"10", -- 0x1990 + x"F9",x"C9",x"DD",x"CB",x"00",x"46",x"28",x"2B", -- 0x1998 + x"DD",x"CB",x"02",x"4E",x"28",x"18",x"DD",x"34", -- 0x19A0 + x"01",x"DD",x"CB",x"02",x"46",x"28",x"0F",x"DD", -- 0x19A8 + x"35",x"01",x"DD",x"35",x"01",x"DD",x"7E",x"01", -- 0x19B0 + x"C6",x"10",x"D6",x"21",x"38",x"0D",x"DD",x"7E", -- 0x19B8 + x"03",x"C6",x"02",x"DD",x"77",x"03",x"FE",x"DF", -- 0x19C0 + x"30",x"01",x"C9",x"DD",x"36",x"00",x"00",x"DD", -- 0x19C8 + x"36",x"01",x"00",x"DD",x"36",x"02",x"00",x"DD", -- 0x19D0 + x"36",x"03",x"00",x"C9",x"DD",x"21",x"68",x"42", -- 0x19D8 + x"DD",x"CB",x"00",x"46",x"28",x"E5",x"3A",x"10", -- 0x19E0 + x"41",x"FE",x"05",x"30",x"03",x"AF",x"18",x"02", -- 0x19E8 + x"3E",x"02",x"DD",x"86",x"03",x"DD",x"77",x"03", -- 0x19F0 + x"C3",x"C6",x"19",x"DD",x"21",x"60",x"42",x"11", -- 0x19F8 + x"04",x"00",x"06",x"03",x"CD",x"0C",x"1A",x"DD", -- 0x1A00 + x"19",x"10",x"F9",x"C9",x"DD",x"CB",x"00",x"46", -- 0x1A08 + x"C8",x"DD",x"7E",x"03",x"C6",x"37",x"D6",x"05", -- 0x1A10 + x"38",x"17",x"D6",x"09",x"D0",x"3A",x"02",x"42", -- 0x1A18 + x"DD",x"96",x"01",x"C6",x"06",x"D6",x"0D",x"D0", -- 0x1A20 + x"CD",x"CB",x"19",x"3E",x"01",x"32",x"04",x"42", -- 0x1A28 + x"C9",x"3A",x"02",x"42",x"DD",x"96",x"01",x"C6", -- 0x1A30 + x"02",x"D6",x"05",x"D0",x"18",x"EA",x"21",x"81", -- 0x1A38 + x"40",x"11",x"61",x"42",x"06",x"03",x"1A",x"2F", -- 0x1A40 + x"77",x"2C",x"2C",x"1C",x"1C",x"1A",x"77",x"3A", -- 0x1A48 + x"0F",x"40",x"0F",x"30",x"09",x"3A",x"0D",x"40", -- 0x1A50 + x"0F",x"30",x"03",x"7E",x"2F",x"77",x"2C",x"2C", -- 0x1A58 + x"1C",x"1C",x"10",x"E2",x"C9",x"3A",x"7C",x"42", -- 0x1A60 + x"0F",x"D0",x"DD",x"21",x"A0",x"42",x"11",x"20", -- 0x1A68 + x"00",x"06",x"08",x"D9",x"CD",x"7D",x"1A",x"D9", -- 0x1A70 + x"DD",x"19",x"10",x"F7",x"C9",x"DD",x"CB",x"00", -- 0x1A78 + x"46",x"C8",x"3A",x"7F",x"42",x"6F",x"3A",x"7D", -- 0x1A80 + x"42",x"67",x"DD",x"7E",x"03",x"95",x"C6",x"02", -- 0x1A88 + x"FE",x"06",x"D0",x"DD",x"7E",x"04",x"94",x"C6", -- 0x1A90 + x"05",x"FE",x"0C",x"D0",x"DD",x"36",x"00",x"00", -- 0x1A98 + x"DD",x"36",x"01",x"01",x"DD",x"36",x"02",x"00", -- 0x1AA0 + x"3A",x"06",x"40",x"0F",x"30",x"34",x"DD",x"CB", -- 0x1AA8 + x"19",x"46",x"28",x"07",x"21",x"B0",x"58",x"CB", -- 0x1AB0 + x"D6",x"18",x"05",x"21",x"B0",x"58",x"CB",x"DE", -- 0x1AB8 + x"16",x"03",x"DD",x"7E",x"16",x"FE",x"07",x"28", -- 0x1AC0 + x"06",x"FE",x"03",x"28",x"06",x"18",x"08",x"1E", -- 0x1AC8 + x"02",x"18",x"06",x"1E",x"04",x"18",x"02",x"1E", -- 0x1AD0 + x"09",x"DD",x"7E",x"19",x"0F",x"30",x"02",x"CB", -- 0x1AD8 + x"23",x"FF",x"AF",x"32",x"7C",x"42",x"21",x"11", -- 0x1AE0 + x"41",x"35",x"DD",x"7E",x"18",x"DD",x"36",x"18", -- 0x1AE8 + x"00",x"3D",x"28",x"04",x"3D",x"28",x"0C",x"C9", -- 0x1AF0 + x"DD",x"7E",x"17",x"C6",x"20",x"6F",x"26",x"41", -- 0x1AF8 + x"CB",x"BE",x"C9",x"DD",x"7E",x"17",x"C6",x"50", -- 0x1B00 + x"18",x"F3",x"21",x"04",x"42",x"CB",x"46",x"28", -- 0x1B08 + x"18",x"36",x"00",x"21",x"00",x"01",x"22",x"00", -- 0x1B10 + x"42",x"21",x"0A",x"04",x"22",x"05",x"42",x"11", -- 0x1B18 + x"03",x"02",x"FF",x"21",x"C0",x"58",x"CB",x"CE", -- 0x1B20 + x"C9",x"3A",x"01",x"42",x"0F",x"D0",x"21",x"05", -- 0x1B28 + x"42",x"35",x"C0",x"36",x"0A",x"23",x"16",x"02", -- 0x1B30 + x"5E",x"FF",x"35",x"C0",x"AF",x"32",x"01",x"42", -- 0x1B38 + x"C9",x"3A",x"12",x"41",x"FE",x"2E",x"C8",x"3A", -- 0x1B40 + x"00",x"42",x"0F",x"D0",x"3A",x"16",x"41",x"A7", -- 0x1B48 + x"C8",x"3A",x"5F",x"42",x"E6",x"07",x"C0",x"3A", -- 0x1B50 + x"5F",x"42",x"A7",x"20",x"0E",x"2A",x"07",x"42", -- 0x1B58 + x"23",x"7E",x"3C",x"20",x"03",x"21",x"89",x"1B", -- 0x1B60 + x"22",x"07",x"42",x"2A",x"07",x"42",x"46",x"21", -- 0x1B68 + x"A0",x"42",x"11",x"1F",x"00",x"7E",x"23",x"B6", -- 0x1B70 + x"0F",x"30",x"04",x"19",x"10",x"F7",x"C9",x"23", -- 0x1B78 + x"36",x"00",x"2B",x"36",x"00",x"2B",x"36",x"01", -- 0x1B80 + x"C9",x"08",x"08",x"04",x"04",x"04",x"05",x"05", -- 0x1B88 + x"05",x"06",x"06",x"06",x"07",x"07",x"07",x"08", -- 0x1B90 + x"08",x"08",x"08",x"08",x"08",x"04",x"04",x"04", -- 0x1B98 + x"04",x"FF",x"3A",x"10",x"41",x"FE",x"04",x"D8", -- 0x1BA0 + x"3A",x"11",x"41",x"FE",x"0F",x"D8",x"3A",x"00", -- 0x1BA8 + x"42",x"0F",x"D0",x"21",x"B8",x"42",x"11",x"20", -- 0x1BB0 + x"00",x"06",x"08",x"CB",x"46",x"20",x"04",x"19", -- 0x1BB8 + x"10",x"F9",x"C9",x"7D",x"D6",x"15",x"6F",x"3A", -- 0x1BC0 + x"60",x"42",x"0F",x"D8",x"7E",x"2C",x"46",x"FE", -- 0x1BC8 + x"B0",x"D0",x"FE",x"60",x"D8",x"21",x"60",x"42", -- 0x1BD0 + x"36",x"01",x"2C",x"70",x"2C",x"2C",x"77",x"C9", -- 0x1BD8 + x"3A",x"00",x"42",x"0F",x"D0",x"3A",x"10",x"41", -- 0x1BE0 + x"A7",x"C8",x"3A",x"11",x"41",x"FE",x"0F",x"D8", -- 0x1BE8 + x"3A",x"02",x"42",x"4F",x"26",x"FF",x"2E",x"00", -- 0x1BF0 + x"DD",x"21",x"A0",x"42",x"11",x"20",x"00",x"06", -- 0x1BF8 + x"08",x"DD",x"CB",x"00",x"46",x"28",x"12",x"DD", -- 0x1C00 + x"7E",x"04",x"B9",x"30",x"06",x"79",x"DD",x"96", -- 0x1C08 + x"04",x"18",x"01",x"91",x"BC",x"30",x"02",x"67", -- 0x1C10 + x"68",x"DD",x"19",x"10",x"E4",x"7D",x"A7",x"C8", -- 0x1C18 + x"3E",x"08",x"95",x"21",x"A0",x"42",x"A7",x"28", -- 0x1C20 + x"04",x"3D",x"19",x"18",x"F9",x"2C",x"2C",x"2C", -- 0x1C28 + x"DD",x"21",x"64",x"42",x"DD",x"CB",x"00",x"46", -- 0x1C30 + x"C0",x"7E",x"FE",x"60",x"D8",x"47",x"3A",x"10", -- 0x1C38 + x"41",x"0E",x"A8",x"A7",x"28",x"07",x"0E",x"B0", -- 0x1C40 + x"3D",x"28",x"02",x"0E",x"B8",x"78",x"B9",x"D0", -- 0x1C48 + x"DD",x"36",x"00",x"01",x"7E",x"DD",x"77",x"03", -- 0x1C50 + x"2C",x"7E",x"DD",x"77",x"01",x"C9",x"3A",x"00", -- 0x1C58 + x"42",x"0F",x"D0",x"3A",x"11",x"41",x"FE",x"0F", -- 0x1C60 + x"D8",x"3A",x"00",x"41",x"0F",x"D0",x"3A",x"10", -- 0x1C68 + x"41",x"FE",x"02",x"D8",x"21",x"68",x"42",x"CB", -- 0x1C70 + x"46",x"C0",x"34",x"2C",x"3A",x"01",x"41",x"77", -- 0x1C78 + x"2C",x"2C",x"36",x"38",x"C9",x"21",x"DF",x"41", -- 0x1C80 + x"1E",x"06",x"0E",x"06",x"06",x"18",x"CB",x"4E", -- 0x1C88 + x"20",x"0C",x"7D",x"93",x"6F",x"10",x"F7",x"7D", -- 0x1C90 + x"C6",x"8F",x"6F",x"0D",x"20",x"EE",x"3E",x"40", -- 0x1C98 + x"41",x"0E",x"04",x"04",x"81",x"10",x"FD",x"32", -- 0x1CA0 + x"1B",x"41",x"C9",x"3A",x"00",x"41",x"A7",x"C8", -- 0x1CA8 + x"3A",x"5F",x"42",x"E6",x"01",x"C8",x"21",x"02", -- 0x1CB0 + x"41",x"7E",x"2D",x"0F",x"38",x"12",x"7E",x"FE", -- 0x1CB8 + x"27",x"38",x"15",x"3D",x"77",x"2F",x"C6",x"80", -- 0x1CC0 + x"21",x"2A",x"40",x"77",x"2C",x"2C",x"77",x"C9", -- 0x1CC8 + x"7E",x"FE",x"D9",x"30",x"07",x"3C",x"18",x"EC", -- 0x1CD0 + x"2C",x"36",x"01",x"C9",x"2C",x"36",x"00",x"C9", -- 0x1CD8 + x"3A",x"58",x"40",x"A7",x"20",x"0E",x"3E",x"30", -- 0x1CE0 + x"32",x"58",x"40",x"32",x"5A",x"40",x"21",x"20", -- 0x1CE8 + x"41",x"C3",x"14",x"1D",x"21",x"58",x"40",x"34", -- 0x1CF0 + x"23",x"23",x"34",x"7E",x"FE",x"80",x"21",x"30", -- 0x1CF8 + x"41",x"CA",x"14",x"1D",x"FE",x"D0",x"21",x"40", -- 0x1D00 + x"41",x"CA",x"14",x"1D",x"A7",x"C0",x"21",x"16", -- 0x1D08 + x"41",x"36",x"30",x"C9",x"06",x"10",x"3E",x"02", -- 0x1D10 + x"77",x"23",x"10",x"FC",x"C9",x"DD",x"CB",x"01", -- 0x1D18 + x"46",x"C2",x"61",x"1D",x"DD",x"CB",x"00",x"46", -- 0x1D20 + x"C8",x"DD",x"7E",x"02",x"EF",x"BD",x"1F",x"76", -- 0x1D28 + x"21",x"A5",x"21",x"B7",x"21",x"C1",x"21",x"EE", -- 0x1D30 + x"21",x"12",x"22",x"1C",x"22",x"2B",x"22",x"A9", -- 0x1D38 + x"23",x"B3",x"23",x"C1",x"23",x"CB",x"23",x"FA", -- 0x1D40 + x"23",x"04",x"24",x"0E",x"24",x"18",x"24",x"25", -- 0x1D48 + x"24",x"28",x"24",x"32",x"24",x"41",x"24",x"F2", -- 0x1D50 + x"25",x"FC",x"25",x"0A",x"26",x"14",x"26",x"43", -- 0x1D58 + x"26",x"DD",x"7E",x"02",x"EF",x"69",x"1D",x"79", -- 0x1D60 + x"1D",x"DD",x"36",x"10",x"04",x"DD",x"36",x"11", -- 0x1D68 + x"04",x"DD",x"36",x"12",x"1C",x"DD",x"34",x"02", -- 0x1D70 + x"C9",x"DD",x"35",x"10",x"C0",x"DD",x"36",x"10", -- 0x1D78 + x"04",x"DD",x"34",x"12",x"DD",x"35",x"11",x"C0", -- 0x1D80 + x"DD",x"36",x"01",x"00",x"C9",x"DD",x"7E",x"16", -- 0x1D88 + x"FE",x"01",x"F5",x"CC",x"AC",x"1D",x"F1",x"28", -- 0x1D90 + x"13",x"DD",x"CB",x"19",x"46",x"20",x"0D",x"DD", -- 0x1D98 + x"7E",x"16",x"FE",x"03",x"28",x"06",x"3A",x"5F", -- 0x1DA0 + x"42",x"0F",x"3F",x"D0",x"DD",x"7E",x"04",x"DD", -- 0x1DA8 + x"BE",x"06",x"28",x"4A",x"DD",x"7E",x"03",x"DD", -- 0x1DB0 + x"BE",x"05",x"28",x"58",x"DD",x"CB",x"09",x"46", -- 0x1DB8 + x"28",x"1E",x"DD",x"7E",x"07",x"DD",x"86",x"03", -- 0x1DC0 + x"DD",x"77",x"03",x"DD",x"7E",x"0B",x"DD",x"86", -- 0x1DC8 + x"0A",x"DD",x"77",x"0A",x"D0",x"DD",x"7E",x"08", -- 0x1DD0 + x"DD",x"86",x"04",x"DD",x"77",x"04",x"A7",x"C9", -- 0x1DD8 + x"DD",x"7E",x"08",x"DD",x"86",x"04",x"DD",x"77", -- 0x1DE0 + x"04",x"DD",x"7E",x"0B",x"DD",x"86",x"0A",x"DD", -- 0x1DE8 + x"77",x"0A",x"D0",x"DD",x"7E",x"07",x"DD",x"86", -- 0x1DF0 + x"03",x"DD",x"77",x"03",x"A7",x"C9",x"DD",x"7E", -- 0x1DF8 + x"03",x"DD",x"BE",x"05",x"28",x"0C",x"30",x"05", -- 0x1E00 + x"DD",x"34",x"03",x"A7",x"C9",x"DD",x"35",x"03", -- 0x1E08 + x"A7",x"C9",x"37",x"C9",x"DD",x"7E",x"04",x"DD", -- 0x1E10 + x"BE",x"06",x"30",x"05",x"DD",x"34",x"04",x"A7", -- 0x1E18 + x"C9",x"DD",x"35",x"04",x"A7",x"C9",x"DD",x"35", -- 0x1E20 + x"0E",x"C0",x"DD",x"6E",x"0C",x"DD",x"66",x"0D", -- 0x1E28 + x"7E",x"FE",x"FF",x"20",x"06",x"23",x"5E",x"23", -- 0x1E30 + x"56",x"EB",x"7E",x"DD",x"77",x"12",x"23",x"7E", -- 0x1E38 + x"DD",x"77",x"0E",x"23",x"DD",x"75",x"0C",x"DD", -- 0x1E40 + x"74",x"0D",x"C9",x"8E",x"0A",x"8F",x"0A",x"90", -- 0x1E48 + x"0A",x"91",x"0A",x"92",x"0A",x"F1",x"05",x"F0", -- 0x1E50 + x"05",x"EF",x"05",x"EE",x"05",x"ED",x"05",x"FF", -- 0x1E58 + x"79",x"1E",x"0E",x"0A",x"0F",x"0A",x"10",x"0A", -- 0x1E60 + x"11",x"0A",x"12",x"0A",x"71",x"05",x"70",x"05", -- 0x1E68 + x"6F",x"05",x"6E",x"05",x"6D",x"05",x"FF",x"79", -- 0x1E70 + x"1E",x"E9",x"05",x"EA",x"05",x"EB",x"05",x"EC", -- 0x1E78 + x"05",x"FF",x"79",x"1E",x"6E",x"05",x"6F",x"05", -- 0x1E80 + x"6E",x"05",x"6D",x"05",x"E9",x"05",x"EA",x"05", -- 0x1E88 + x"EB",x"05",x"EC",x"05",x"ED",x"05",x"EE",x"05", -- 0x1E90 + x"EF",x"05",x"EE",x"05",x"ED",x"05",x"FF",x"79", -- 0x1E98 + x"1E",x"E4",x"03",x"E5",x"03",x"E6",x"03",x"E7", -- 0x1EA0 + x"03",x"E8",x"03",x"A7",x"03",x"A6",x"03",x"A5", -- 0x1EA8 + x"03",x"A4",x"03",x"FF",x"B6",x"1E",x"20",x"05", -- 0x1EB0 + x"21",x"05",x"22",x"05",x"23",x"05",x"FF",x"B6", -- 0x1EB8 + x"1E",x"25",x"05",x"26",x"05",x"25",x"05",x"24", -- 0x1EC0 + x"05",x"20",x"05",x"21",x"05",x"22",x"05",x"23", -- 0x1EC8 + x"05",x"A4",x"05",x"A5",x"05",x"A6",x"05",x"A5", -- 0x1ED0 + x"05",x"A4",x"05",x"FF",x"B6",x"1E",x"2D",x"03", -- 0x1ED8 + x"2E",x"03",x"2F",x"03",x"30",x"03",x"31",x"03", -- 0x1EE0 + x"70",x"03",x"6F",x"03",x"6E",x"03",x"6D",x"03", -- 0x1EE8 + x"FF",x"79",x"1E",x"DD",x"E5",x"E1",x"3E",x"07", -- 0x1EF0 + x"85",x"6F",x"DD",x"36",x"0A",x"00",x"DD",x"7E", -- 0x1EF8 + x"05",x"DD",x"BE",x"03",x"28",x"04",x"38",x"1E", -- 0x1F00 + x"18",x"56",x"DD",x"7E",x"06",x"DD",x"BE",x"04", -- 0x1F08 + x"28",x"0E",x"38",x"06",x"36",x"00",x"2C",x"36", -- 0x1F10 + x"01",x"C9",x"36",x"00",x"2C",x"36",x"FF",x"C9", -- 0x1F18 + x"36",x"00",x"2C",x"36",x"00",x"C9",x"DD",x"7E", -- 0x1F20 + x"06",x"DD",x"BE",x"04",x"28",x"2C",x"38",x"15", -- 0x1F28 + x"36",x"FF",x"2C",x"36",x"01",x"DD",x"7E",x"03", -- 0x1F30 + x"DD",x"96",x"05",x"47",x"DD",x"7E",x"06",x"DD", -- 0x1F38 + x"96",x"04",x"4F",x"18",x"55",x"36",x"FF",x"2C", -- 0x1F40 + x"36",x"FF",x"DD",x"7E",x"03",x"DD",x"96",x"05", -- 0x1F48 + x"47",x"DD",x"7E",x"04",x"DD",x"96",x"06",x"4F", -- 0x1F50 + x"18",x"40",x"36",x"FF",x"2C",x"36",x"00",x"C9", -- 0x1F58 + x"DD",x"7E",x"06",x"DD",x"BE",x"04",x"28",x"2C", -- 0x1F60 + x"38",x"15",x"36",x"01",x"2C",x"36",x"01",x"DD", -- 0x1F68 + x"7E",x"05",x"DD",x"96",x"03",x"47",x"DD",x"7E", -- 0x1F70 + x"06",x"DD",x"96",x"04",x"4F",x"18",x"1B",x"36", -- 0x1F78 + x"01",x"2C",x"36",x"FF",x"DD",x"7E",x"05",x"DD", -- 0x1F80 + x"96",x"03",x"47",x"DD",x"7E",x"04",x"DD",x"96", -- 0x1F88 + x"06",x"4F",x"18",x"06",x"36",x"01",x"2C",x"36", -- 0x1F90 + x"00",x"C9",x"79",x"B8",x"28",x"16",x"38",x"0B", -- 0x1F98 + x"DD",x"36",x"09",x"00",x"CD",x"4F",x"26",x"DD", -- 0x1FA0 + x"77",x"0B",x"C9",x"DD",x"36",x"09",x"01",x"78", -- 0x1FA8 + x"41",x"4F",x"18",x"F0",x"DD",x"36",x"09",x"01", -- 0x1FB0 + x"DD",x"36",x"0B",x"FF",x"C9",x"DD",x"36",x"18", -- 0x1FB8 + x"00",x"DD",x"36",x"19",x"00",x"21",x"0E",x"21", -- 0x1FC0 + x"DD",x"75",x"13",x"DD",x"74",x"14",x"DD",x"36", -- 0x1FC8 + x"10",x"30",x"DD",x"36",x"0E",x"01",x"21",x"12", -- 0x1FD0 + x"41",x"7E",x"34",x"47",x"87",x"87",x"80",x"5F", -- 0x1FD8 + x"16",x"00",x"21",x"28",x"20",x"19",x"3E",x"30", -- 0x1FE0 + x"86",x"DD",x"77",x"03",x"23",x"3A",x"01",x"41", -- 0x1FE8 + x"86",x"DD",x"77",x"04",x"23",x"5E",x"23",x"46", -- 0x1FF0 + x"23",x"7E",x"DD",x"77",x"16",x"21",x"04",x"41", -- 0x1FF8 + x"19",x"70",x"DD",x"36",x"12",x"0B",x"3A",x"01", -- 0x2000 + x"41",x"FE",x"80",x"30",x"11",x"DD",x"36",x"15", -- 0x2008 + x"00",x"21",x"4B",x"1E",x"DD",x"75",x"0C",x"DD", -- 0x2010 + x"74",x"0D",x"DD",x"34",x"02",x"C9",x"DD",x"36", -- 0x2018 + x"15",x"01",x"21",x"62",x"1E",x"C3",x"14",x"20", -- 0x2020 + x"F1",x"EF",x"00",x"66",x"07",x"F1",x"12",x"05", -- 0x2028 + x"66",x"07",x"F3",x"EB",x"00",x"6D",x"07",x"F3", -- 0x2030 + x"16",x"05",x"67",x"07",x"F3",x"EE",x"00",x"68", -- 0x2038 + x"07",x"F3",x"13",x"05",x"68",x"07",x"F5",x"EA", -- 0x2040 + x"00",x"6E",x"07",x"F5",x"17",x"05",x"69",x"07", -- 0x2048 + x"F5",x"EF",x"00",x"6A",x"07",x"F5",x"12",x"05", -- 0x2050 + x"6A",x"07",x"F7",x"EB",x"00",x"6F",x"07",x"F7", -- 0x2058 + x"16",x"05",x"6B",x"03",x"F7",x"EE",x"00",x"10", -- 0x2060 + x"03",x"F7",x"13",x"05",x"10",x"03",x"F1",x"F2", -- 0x2068 + x"01",x"6C",x"03",x"F1",x"0F",x"04",x"65",x"03", -- 0x2070 + x"F1",x"F7",x"01",x"66",x"03",x"F1",x"0A",x"04", -- 0x2078 + x"66",x"03",x"F3",x"F3",x"01",x"6D",x"03",x"F3", -- 0x2080 + x"0E",x"04",x"67",x"03",x"F3",x"F6",x"01",x"68", -- 0x2088 + x"03",x"F3",x"0B",x"04",x"68",x"03",x"F5",x"F2", -- 0x2090 + x"01",x"6E",x"03",x"F5",x"0F",x"04",x"69",x"03", -- 0x2098 + x"F5",x"F7",x"01",x"6A",x"03",x"F5",x"0A",x"04", -- 0x20A0 + x"6A",x"03",x"F7",x"F3",x"01",x"6F",x"03",x"F7", -- 0x20A8 + x"0E",x"04",x"6B",x"03",x"F7",x"F6",x"01",x"10", -- 0x20B0 + x"03",x"F7",x"0B",x"04",x"10",x"03",x"F1",x"FA", -- 0x20B8 + x"02",x"6C",x"03",x"F1",x"07",x"03",x"65",x"03", -- 0x20C0 + x"F1",x"FF",x"02",x"66",x"03",x"F1",x"02",x"03", -- 0x20C8 + x"66",x"03",x"F3",x"FB",x"02",x"6D",x"03",x"F3", -- 0x20D0 + x"06",x"03",x"67",x"03",x"F3",x"FE",x"02",x"68", -- 0x20D8 + x"03",x"F3",x"03",x"03",x"68",x"01",x"F5",x"FA", -- 0x20E0 + x"02",x"6E",x"01",x"F5",x"07",x"03",x"69",x"01", -- 0x20E8 + x"F5",x"FF",x"02",x"6A",x"01",x"F5",x"02",x"03", -- 0x20F0 + x"6A",x"01",x"F7",x"FB",x"02",x"6F",x"01",x"F7", -- 0x20F8 + x"06",x"03",x"6B",x"01",x"F7",x"FE",x"02",x"10", -- 0x2100 + x"01",x"F7",x"03",x"03",x"10",x"01",x"FF",x"00", -- 0x2108 + x"FF",x"00",x"FF",x"00",x"FF",x"01",x"FF",x"00", -- 0x2110 + x"FF",x"00",x"FF",x"01",x"FF",x"00",x"FF",x"01", -- 0x2118 + x"FF",x"00",x"00",x"01",x"FF",x"00",x"FF",x"01", -- 0x2120 + x"00",x"01",x"FF",x"00",x"00",x"01",x"FF",x"01", -- 0x2128 + x"00",x"01",x"FF",x"01",x"00",x"01",x"00",x"01", -- 0x2130 + x"FF",x"01",x"00",x"01",x"00",x"01",x"00",x"01", -- 0x2138 + x"00",x"01",x"00",x"01",x"00",x"01",x"01",x"01", -- 0x2140 + x"00",x"01",x"00",x"01",x"01",x"01",x"00",x"01", -- 0x2148 + x"01",x"01",x"00",x"01",x"01",x"00",x"00",x"01", -- 0x2150 + x"01",x"01",x"01",x"00",x"00",x"01",x"01",x"00", -- 0x2158 + x"01",x"01",x"01",x"00",x"01",x"01",x"01",x"00", -- 0x2160 + x"01",x"00",x"01",x"01",x"01",x"00",x"01",x"00", -- 0x2168 + x"01",x"00",x"01",x"00",x"01",x"00",x"DD",x"35", -- 0x2170 + x"10",x"28",x"27",x"DD",x"6E",x"13",x"DD",x"66", -- 0x2178 + x"14",x"DD",x"7E",x"03",x"86",x"DD",x"77",x"03", -- 0x2180 + x"23",x"7E",x"23",x"DD",x"75",x"13",x"DD",x"74", -- 0x2188 + x"14",x"DD",x"CB",x"15",x"46",x"28",x"02",x"ED", -- 0x2190 + x"44",x"DD",x"86",x"04",x"DD",x"77",x"04",x"C3", -- 0x2198 + x"26",x"1E",x"DD",x"34",x"02",x"3A",x"1B",x"41", -- 0x21A0 + x"DD",x"77",x"05",x"DD",x"7E",x"04",x"DD",x"77", -- 0x21A8 + x"06",x"CD",x"F3",x"1E",x"DD",x"34",x"02",x"CD", -- 0x21B0 + x"26",x"1E",x"CD",x"8D",x"1D",x"D0",x"DD",x"34", -- 0x21B8 + x"02",x"3A",x"1C",x"41",x"0F",x"3E",x"01",x"30", -- 0x21C0 + x"1F",x"3E",x"03",x"18",x"1B",x"3A",x"04",x"40", -- 0x21C8 + x"47",x"3A",x"10",x"41",x"A7",x"28",x"07",x"3D", -- 0x21D0 + x"28",x"0A",x"3E",x"01",x"18",x"0A",x"3E",x"03", -- 0x21D8 + x"A0",x"3C",x"18",x"04",x"3E",x"01",x"A0",x"3C", -- 0x21E0 + x"DD",x"77",x"10",x"DD",x"34",x"02",x"3A",x"04", -- 0x21E8 + x"40",x"47",x"E6",x"70",x"FE",x"60",x"38",x"02", -- 0x21F0 + x"D6",x"20",x"C6",x"58",x"DD",x"77",x"05",x"78", -- 0x21F8 + x"FE",x"D0",x"38",x"02",x"D6",x"80",x"C6",x"18", -- 0x2200 + x"DD",x"77",x"06",x"CD",x"F3",x"1E",x"DD",x"34", -- 0x2208 + x"02",x"C9",x"CD",x"26",x"1E",x"CD",x"8D",x"1D", -- 0x2210 + x"D0",x"DD",x"34",x"02",x"DD",x"35",x"10",x"28", -- 0x2218 + x"07",x"DD",x"35",x"02",x"DD",x"35",x"02",x"C9", -- 0x2220 + x"DD",x"34",x"02",x"DD",x"36",x"02",x"04",x"3A", -- 0x2228 + x"00",x"42",x"0F",x"D0",x"3A",x"16",x"41",x"A7", -- 0x2230 + x"C8",x"ED",x"5F",x"E6",x"03",x"28",x"13",x"3D", -- 0x2238 + x"28",x"44",x"3D",x"28",x"72",x"3A",x"02",x"42", -- 0x2240 + x"FE",x"58",x"38",x"6B",x"FE",x"A8",x"38",x"02", -- 0x2248 + x"18",x"34",x"21",x"20",x"41",x"CD",x"11",x"23", -- 0x2250 + x"DA",x"E8",x"22",x"21",x"2C",x"41",x"CD",x"2D", -- 0x2258 + x"23",x"DA",x"E8",x"22",x"21",x"30",x"41",x"CD", -- 0x2260 + x"11",x"23",x"DA",x"E8",x"22",x"21",x"3C",x"41", -- 0x2268 + x"CD",x"2D",x"23",x"38",x"73",x"21",x"40",x"41", -- 0x2270 + x"CD",x"11",x"23",x"38",x"6B",x"21",x"4C",x"41", -- 0x2278 + x"CD",x"2D",x"23",x"38",x"63",x"C9",x"21",x"3C", -- 0x2280 + x"41",x"CD",x"2D",x"23",x"38",x"5A",x"21",x"30", -- 0x2288 + x"41",x"CD",x"11",x"23",x"38",x"52",x"21",x"4C", -- 0x2290 + x"41",x"CD",x"2D",x"23",x"38",x"4A",x"21",x"40", -- 0x2298 + x"41",x"CD",x"11",x"23",x"38",x"42",x"21",x"20", -- 0x22A0 + x"41",x"CD",x"11",x"23",x"38",x"3A",x"21",x"2C", -- 0x22A8 + x"41",x"CD",x"2D",x"23",x"38",x"32",x"C9",x"21", -- 0x22B0 + x"40",x"41",x"CD",x"11",x"23",x"38",x"29",x"21", -- 0x22B8 + x"4C",x"41",x"CD",x"2D",x"23",x"38",x"21",x"21", -- 0x22C0 + x"20",x"41",x"CD",x"11",x"23",x"38",x"19",x"21", -- 0x22C8 + x"2C",x"41",x"CD",x"2D",x"23",x"38",x"11",x"21", -- 0x22D0 + x"30",x"41",x"CD",x"11",x"23",x"38",x"09",x"21", -- 0x22D8 + x"3C",x"41",x"CD",x"2D",x"23",x"38",x"01",x"C9", -- 0x22E0 + x"CB",x"FE",x"7D",x"D6",x"20",x"DD",x"77",x"17", -- 0x22E8 + x"DD",x"36",x"18",x"01",x"87",x"5F",x"16",x"00", -- 0x22F0 + x"21",x"49",x"23",x"19",x"7E",x"D6",x"10",x"DD", -- 0x22F8 + x"77",x"05",x"23",x"7E",x"DD",x"77",x"06",x"CD", -- 0x2300 + x"F3",x"1E",x"DD",x"36",x"02",x"09",x"C3",x"A9", -- 0x2308 + x"23",x"11",x"0F",x"04",x"4A",x"42",x"CB",x"4E", -- 0x2310 + x"20",x"0D",x"7D",x"82",x"6F",x"10",x"F7",x"7D", -- 0x2318 + x"93",x"6F",x"0D",x"20",x"F0",x"A7",x"C9",x"A7", -- 0x2320 + x"CB",x"7E",x"C0",x"37",x"C9",x"11",x"11",x"04", -- 0x2328 + x"4A",x"42",x"CB",x"4E",x"20",x"0D",x"7D",x"92", -- 0x2330 + x"6F",x"10",x"F7",x"7D",x"83",x"6F",x"0D",x"20", -- 0x2338 + x"F0",x"A7",x"C9",x"A7",x"CB",x"7E",x"C0",x"37", -- 0x2340 + x"C9",x"E0",x"24",x"E4",x"24",x"E8",x"24",x"EC", -- 0x2348 + x"24",x"E0",x"2C",x"E4",x"2C",x"E8",x"2C",x"EC", -- 0x2350 + x"2C",x"E0",x"34",x"E4",x"34",x"E8",x"34",x"EC", -- 0x2358 + x"34",x"E0",x"3C",x"E4",x"3C",x"E8",x"3C",x"EC", -- 0x2360 + x"3C",x"E0",x"74",x"E4",x"74",x"E8",x"74",x"EC", -- 0x2368 + x"74",x"E0",x"7C",x"E4",x"7C",x"E8",x"7C",x"EC", -- 0x2370 + x"7C",x"E0",x"84",x"E4",x"84",x"E8",x"84",x"EC", -- 0x2378 + x"84",x"E0",x"8C",x"E4",x"8C",x"E8",x"8C",x"EC", -- 0x2380 + x"8C",x"E0",x"C4",x"E4",x"C4",x"E8",x"C4",x"EC", -- 0x2388 + x"C4",x"E0",x"CC",x"E4",x"CC",x"E8",x"CC",x"EC", -- 0x2390 + x"CC",x"E0",x"D4",x"E4",x"D4",x"E8",x"D4",x"EC", -- 0x2398 + x"D4",x"E0",x"DC",x"E4",x"DC",x"E8",x"DC",x"EC", -- 0x23A0 + x"DC",x"CD",x"26",x"1E",x"CD",x"8D",x"1D",x"D0", -- 0x23A8 + x"DD",x"34",x"02",x"DD",x"7E",x"05",x"C6",x"10", -- 0x23B0 + x"DD",x"77",x"05",x"CD",x"F3",x"1E",x"DD",x"34", -- 0x23B8 + x"02",x"CD",x"26",x"1E",x"CD",x"8D",x"1D",x"D0", -- 0x23C0 + x"DD",x"34",x"02",x"21",x"B0",x"58",x"CB",x"CE", -- 0x23C8 + x"21",x"A1",x"1E",x"DD",x"75",x"0C",x"DD",x"74", -- 0x23D0 + x"0D",x"DD",x"36",x"0E",x"01",x"DD",x"36",x"10", -- 0x23D8 + x"0F",x"DD",x"36",x"18",x"00",x"DD",x"36",x"19", -- 0x23E0 + x"01",x"DD",x"7E",x"17",x"C6",x"20",x"6F",x"26", -- 0x23E8 + x"41",x"36",x"00",x"21",x"16",x"41",x"35",x"DD", -- 0x23F0 + x"34",x"02",x"CD",x"26",x"1E",x"DD",x"35",x"10", -- 0x23F8 + x"C0",x"DD",x"34",x"02",x"DD",x"36",x"05",x"B8", -- 0x2400 + x"CD",x"F3",x"1E",x"DD",x"34",x"02",x"CD",x"26", -- 0x2408 + x"1E",x"CD",x"8D",x"1D",x"D0",x"DD",x"34",x"02", -- 0x2410 + x"3A",x"04",x"40",x"E6",x"03",x"3E",x"01",x"DD", -- 0x2418 + x"77",x"10",x"DD",x"34",x"02",x"CD",x"EE",x"21", -- 0x2420 + x"CD",x"26",x"1E",x"CD",x"8D",x"1D",x"D0",x"DD", -- 0x2428 + x"34",x"02",x"DD",x"35",x"10",x"28",x"07",x"DD", -- 0x2430 + x"35",x"02",x"DD",x"35",x"02",x"C9",x"DD",x"34", -- 0x2438 + x"02",x"3A",x"04",x"40",x"E6",x"03",x"21",x"50", -- 0x2440 + x"41",x"3D",x"28",x"09",x"21",x"80",x"41",x"3D", -- 0x2448 + x"28",x"03",x"21",x"B0",x"41",x"CD",x"7D",x"24", -- 0x2450 + x"DD",x"36",x"02",x"10",x"D0",x"DD",x"6E",x"17", -- 0x2458 + x"26",x"00",x"29",x"EB",x"21",x"D2",x"24",x"19", -- 0x2460 + x"7E",x"C6",x"10",x"DD",x"77",x"05",x"23",x"7E", -- 0x2468 + x"DD",x"77",x"06",x"CD",x"F3",x"1E",x"DD",x"36", -- 0x2470 + x"02",x"15",x"C3",x"F2",x"25",x"08",x"3E",x"01", -- 0x2478 + x"08",x"16",x"06",x"ED",x"5F",x"E6",x"07",x"4F", -- 0x2480 + x"87",x"47",x"87",x"80",x"85",x"6F",x"1E",x"08", -- 0x2488 + x"7B",x"91",x"47",x"7E",x"CB",x"46",x"20",x"24", -- 0x2490 + x"7D",x"C6",x"06",x"6F",x"1D",x"10",x"F4",x"7B", -- 0x2498 + x"A7",x"28",x"0A",x"7D",x"D6",x"30",x"6F",x"43", -- 0x24A0 + x"08",x"AF",x"08",x"18",x"E6",x"08",x"A7",x"28", -- 0x24A8 + x"04",x"7D",x"D6",x"30",x"6F",x"08",x"2C",x"15", -- 0x24B0 + x"20",x"D4",x"A7",x"C9",x"CB",x"4E",x"20",x"D8", -- 0x24B8 + x"A7",x"CB",x"7E",x"C0",x"CB",x"FE",x"7D",x"D6", -- 0x24C0 + x"50",x"DD",x"77",x"17",x"DD",x"36",x"18",x"02", -- 0x24C8 + x"37",x"C9",x"44",x"1C",x"48",x"1C",x"4C",x"1C", -- 0x24D0 + x"50",x"1C",x"54",x"1C",x"58",x"1C",x"44",x"24", -- 0x24D8 + x"48",x"24",x"4C",x"24",x"50",x"24",x"54",x"24", -- 0x24E0 + x"58",x"24",x"44",x"2C",x"48",x"2C",x"4C",x"2C", -- 0x24E8 + x"50",x"2C",x"54",x"2C",x"58",x"2C",x"44",x"34", -- 0x24F0 + x"48",x"34",x"4C",x"34",x"50",x"34",x"54",x"34", -- 0x24F8 + x"58",x"34",x"44",x"3C",x"48",x"3C",x"4C",x"3C", -- 0x2500 + x"50",x"3C",x"54",x"3C",x"58",x"3C",x"44",x"44", -- 0x2508 + x"48",x"44",x"4C",x"44",x"50",x"44",x"54",x"44", -- 0x2510 + x"58",x"44",x"44",x"4C",x"48",x"4C",x"4C",x"4C", -- 0x2518 + x"50",x"4C",x"54",x"4C",x"58",x"4C",x"44",x"54", -- 0x2520 + x"48",x"54",x"4C",x"54",x"50",x"54",x"54",x"54", -- 0x2528 + x"58",x"54",x"44",x"64",x"48",x"64",x"4C",x"64", -- 0x2530 + x"50",x"64",x"54",x"64",x"58",x"64",x"44",x"6C", -- 0x2538 + x"48",x"6C",x"4C",x"6C",x"50",x"6C",x"54",x"6C", -- 0x2540 + x"58",x"6C",x"44",x"74",x"48",x"74",x"4C",x"74", -- 0x2548 + x"50",x"74",x"54",x"74",x"58",x"74",x"44",x"7C", -- 0x2550 + x"48",x"7C",x"4C",x"7C",x"50",x"7C",x"54",x"7C", -- 0x2558 + x"58",x"7C",x"44",x"84",x"48",x"84",x"4C",x"84", -- 0x2560 + x"50",x"84",x"54",x"84",x"58",x"84",x"44",x"8C", -- 0x2568 + x"48",x"8C",x"4C",x"8C",x"50",x"8C",x"54",x"8C", -- 0x2570 + x"58",x"8C",x"44",x"94",x"48",x"94",x"4C",x"94", -- 0x2578 + x"50",x"94",x"54",x"94",x"58",x"94",x"44",x"9C", -- 0x2580 + x"48",x"9C",x"4C",x"9C",x"50",x"9C",x"54",x"9C", -- 0x2588 + x"58",x"9C",x"44",x"AC",x"48",x"AC",x"4C",x"AC", -- 0x2590 + x"50",x"AC",x"54",x"AC",x"58",x"AC",x"44",x"B4", -- 0x2598 + x"48",x"B4",x"4C",x"B4",x"50",x"B4",x"54",x"B4", -- 0x25A0 + x"58",x"B4",x"44",x"BC",x"48",x"BC",x"4C",x"BC", -- 0x25A8 + x"50",x"BC",x"54",x"BC",x"58",x"BC",x"44",x"C4", -- 0x25B0 + x"48",x"C4",x"4C",x"C4",x"50",x"C4",x"54",x"C4", -- 0x25B8 + x"58",x"C4",x"44",x"CC",x"48",x"CC",x"4C",x"CC", -- 0x25C0 + x"50",x"CC",x"54",x"CC",x"58",x"CC",x"44",x"D4", -- 0x25C8 + x"48",x"D4",x"4C",x"D4",x"50",x"D4",x"54",x"D4", -- 0x25D0 + x"58",x"D4",x"44",x"DC",x"48",x"DC",x"4C",x"DC", -- 0x25D8 + x"50",x"DC",x"54",x"DC",x"58",x"DC",x"44",x"E4", -- 0x25E0 + x"48",x"E4",x"4C",x"E4",x"50",x"E4",x"54",x"E4", -- 0x25E8 + x"58",x"E4",x"CD",x"26",x"1E",x"CD",x"8D",x"1D", -- 0x25F0 + x"D0",x"DD",x"34",x"02",x"DD",x"7E",x"05",x"D6", -- 0x25F8 + x"10",x"DD",x"77",x"05",x"CD",x"F3",x"1E",x"DD", -- 0x2600 + x"34",x"02",x"CD",x"26",x"1E",x"CD",x"8D",x"1D", -- 0x2608 + x"D0",x"DD",x"34",x"02",x"21",x"B0",x"58",x"CB", -- 0x2610 + x"C6",x"21",x"DE",x"1E",x"DD",x"75",x"0C",x"DD", -- 0x2618 + x"74",x"0D",x"DD",x"36",x"0E",x"01",x"DD",x"7E", -- 0x2620 + x"17",x"C6",x"50",x"6F",x"26",x"41",x"36",x"03", -- 0x2628 + x"DD",x"36",x"18",x"00",x"DD",x"36",x"19",x"00", -- 0x2630 + x"21",x"1A",x"41",x"35",x"DD",x"36",x"10",x"0F", -- 0x2638 + x"DD",x"34",x"02",x"CD",x"26",x"1E",x"DD",x"35", -- 0x2640 + x"10",x"C0",x"DD",x"36",x"02",x"02",x"C9",x"AF", -- 0x2648 + x"67",x"68",x"57",x"59",x"06",x"08",x"CB",x"FF", -- 0x2650 + x"07",x"29",x"A7",x"ED",x"52",x"38",x"03",x"10", -- 0x2658 + x"F5",x"C9",x"19",x"CB",x"87",x"10",x"EF",x"C9", -- 0x2660 + x"AF",x"32",x"B0",x"58",x"32",x"D0",x"58",x"32", -- 0x2668 + x"E0",x"58",x"21",x"B8",x"40",x"35",x"C0",x"2D", -- 0x2670 + x"3A",x"1C",x"41",x"47",x"0F",x"38",x"13",x"3A", -- 0x2678 + x"1A",x"41",x"FE",x"2C",x"30",x"34",x"78",x"A7", -- 0x2680 + x"20",x"30",x"3E",x"01",x"32",x"1C",x"41",x"36", -- 0x2688 + x"02",x"C9",x"AF",x"32",x"1C",x"41",x"11",x"88", -- 0x2690 + x"06",x"FF",x"36",x"07",x"26",x"40",x"2E",x"AE", -- 0x2698 + x"36",x"20",x"2E",x"BF",x"36",x"12",x"3A",x"09", -- 0x26A0 + x"42",x"3C",x"32",x"09",x"42",x"FE",x"7F",x"C0", -- 0x26A8 + x"AF",x"32",x"09",x"42",x"26",x"40",x"2E",x"A1", -- 0x26B0 + x"34",x"C9",x"34",x"C9",x"21",x"10",x"41",x"34", -- 0x26B8 + x"21",x"14",x"41",x"34",x"11",x"00",x"07",x"FF", -- 0x26C0 + x"21",x"96",x"10",x"11",x"04",x"41",x"01",x"0C", -- 0x26C8 + x"00",x"ED",x"B0",x"21",x"11",x"41",x"36",x"2E", -- 0x26D0 + x"23",x"36",x"00",x"21",x"89",x"1B",x"22",x"07", -- 0x26D8 + x"42",x"21",x"B7",x"40",x"36",x"15",x"3A",x"15", -- 0x26E0 + x"41",x"0F",x"D8",x"36",x"13",x"3A",x"13",x"41", -- 0x26E8 + x"0F",x"D0",x"3E",x"01",x"32",x"15",x"41",x"C9", -- 0x26F0 + x"21",x"B7",x"40",x"34",x"2C",x"36",x"01",x"23", -- 0x26F8 + x"36",x"01",x"C9",x"21",x"B9",x"40",x"35",x"C0", -- 0x2700 + x"36",x"01",x"21",x"B7",x"40",x"34",x"C9",x"21", -- 0x2708 + x"B9",x"40",x"35",x"C0",x"36",x"10",x"21",x"20", -- 0x2710 + x"41",x"3A",x"15",x"41",x"0F",x"3E",x"00",x"38", -- 0x2718 + x"02",x"3E",x"02",x"06",x"30",x"D7",x"21",x"B7", -- 0x2720 + x"40",x"34",x"C9",x"21",x"B9",x"40",x"35",x"C0", -- 0x2728 + x"2D",x"36",x"00",x"3E",x"30",x"32",x"16",x"41", -- 0x2730 + x"21",x"10",x"41",x"34",x"21",x"14",x"41",x"34", -- 0x2738 + x"11",x"00",x"07",x"FF",x"11",x"08",x"06",x"3A", -- 0x2740 + x"15",x"41",x"0F",x"D4",x"38",x"00",x"21",x"72", -- 0x2748 + x"27",x"11",x"04",x"41",x"01",x"06",x"00",x"ED", -- 0x2750 + x"B0",x"21",x"11",x"41",x"36",x"18",x"2C",x"36", -- 0x2758 + x"16",x"21",x"B7",x"40",x"36",x"15",x"3A",x"15", -- 0x2760 + x"41",x"0F",x"D8",x"36",x"13",x"C9",x"2D",x"36", -- 0x2768 + x"03",x"C9",x"10",x"68",x"64",x"64",x"68",x"10", -- 0x2770 + x"C9",x"21",x"00",x"41",x"36",x"00",x"2C",x"34", -- 0x2778 + x"7E",x"47",x"2F",x"C6",x"80",x"32",x"2A",x"40", -- 0x2780 + x"32",x"2C",x"40",x"78",x"FE",x"FF",x"C0",x"36", -- 0x2788 + x"80",x"21",x"B7",x"40",x"34",x"16",x"01",x"FF", -- 0x2790 + x"23",x"36",x"19",x"3A",x"09",x"42",x"3C",x"32", -- 0x2798 + x"09",x"42",x"FE",x"7F",x"C0",x"AF",x"32",x"09", -- 0x27A0 + x"42",x"3E",x"01",x"32",x"0A",x"40",x"C9",x"21", -- 0x27A8 + x"B8",x"40",x"35",x"C0",x"3E",x"F7",x"32",x"BB", -- 0x27B0 + x"40",x"2F",x"32",x"38",x"40",x"32",x"3A",x"40", -- 0x27B8 + x"21",x"B7",x"40",x"34",x"21",x"A0",x"58",x"CB", -- 0x27C0 + x"D6",x"11",x"09",x"06",x"FF",x"3A",x"09",x"42", -- 0x27C8 + x"3C",x"32",x"09",x"42",x"FE",x"7F",x"C0",x"AF", -- 0x27D0 + x"32",x"09",x"42",x"21",x"1A",x"41",x"34",x"C9", -- 0x27D8 + x"21",x"BA",x"40",x"36",x"01",x"2C",x"35",x"7E", -- 0x27E0 + x"47",x"2F",x"C6",x"80",x"32",x"38",x"40",x"32", -- 0x27E8 + x"3A",x"40",x"78",x"FE",x"80",x"C0",x"11",x"89", -- 0x27F0 + x"06",x"FF",x"E5",x"21",x"A0",x"58",x"CB",x"96", -- 0x27F8 + x"E1",x"16",x"40",x"23",x"1E",x"BF",x"36",x"00", -- 0x2800 + x"21",x"B7",x"40",x"34",x"C9",x"CD",x"C5",x"17", -- 0x2808 + x"CD",x"1F",x"18",x"CD",x"DC",x"18",x"21",x"BC", -- 0x2810 + x"40",x"7E",x"2D",x"0F",x"38",x"08",x"35",x"7E", -- 0x2818 + x"FE",x"27",x"38",x"13",x"18",x"06",x"34",x"7E", -- 0x2820 + x"FE",x"D9",x"30",x"0B",x"2F",x"C6",x"80",x"32", -- 0x2828 + x"38",x"40",x"32",x"3A",x"40",x"18",x"02",x"2C", -- 0x2830 + x"34",x"CD",x"6A",x"28",x"38",x"13",x"3A",x"BC", -- 0x2838 + x"40",x"FE",x"0A",x"C0",x"AF",x"32",x"9D",x"40", -- 0x2840 + x"11",x"89",x"06",x"FF",x"21",x"B7",x"40",x"34", -- 0x2848 + x"C9",x"21",x"E0",x"58",x"CB",x"C6",x"AF",x"32", -- 0x2850 + x"9D",x"40",x"11",x"89",x"06",x"FF",x"21",x"B7", -- 0x2858 + x"40",x"36",x"0D",x"2C",x"36",x"0A",x"2C",x"36", -- 0x2860 + x"06",x"C9",x"21",x"7C",x"42",x"7E",x"0F",x"D0", -- 0x2868 + x"23",x"3A",x"BB",x"40",x"C6",x"02",x"96",x"FE", -- 0x2870 + x"05",x"D0",x"2C",x"2C",x"7E",x"FE",x"6E",x"D0", -- 0x2878 + x"FE",x"69",x"3F",x"C9",x"AF",x"32",x"BA",x"40", -- 0x2880 + x"32",x"7C",x"42",x"21",x"BB",x"40",x"35",x"7E", -- 0x2888 + x"47",x"2F",x"C6",x"80",x"32",x"38",x"40",x"32", -- 0x2890 + x"3A",x"40",x"78",x"FE",x"08",x"C0",x"CD",x"62", -- 0x2898 + x"2A",x"21",x"B7",x"40",x"34",x"2C",x"36",x"64", -- 0x28A0 + x"C9",x"21",x"B8",x"40",x"35",x"C0",x"3E",x"01", -- 0x28A8 + x"32",x"00",x"41",x"32",x"B7",x"40",x"C9",x"21", -- 0x28B0 + x"B8",x"40",x"35",x"C0",x"E5",x"21",x"E0",x"58", -- 0x28B8 + x"CB",x"C6",x"E1",x"AF",x"32",x"BA",x"40",x"32", -- 0x28C0 + x"7C",x"42",x"36",x"0A",x"CD",x"62",x"2A",x"2D", -- 0x28C8 + x"34",x"C9",x"21",x"B8",x"40",x"35",x"C0",x"36", -- 0x28D0 + x"0A",x"CD",x"75",x"2A",x"2D",x"34",x"C9",x"21", -- 0x28D8 + x"B9",x"40",x"35",x"20",x"17",x"CD",x"62",x"2A", -- 0x28E0 + x"11",x"AB",x"40",x"AF",x"12",x"1C",x"12",x"1C", -- 0x28E8 + x"12",x"E5",x"CD",x"31",x"29",x"E1",x"36",x"64", -- 0x28F0 + x"2D",x"2D",x"34",x"C9",x"2D",x"2D",x"36",x"0D", -- 0x28F8 + x"C9",x"21",x"B9",x"40",x"35",x"C0",x"11",x"8A", -- 0x2900 + x"06",x"FF",x"36",x"0A",x"2D",x"2D",x"34",x"C9", -- 0x2908 + x"21",x"B9",x"40",x"35",x"C0",x"36",x"0A",x"CD", -- 0x2910 + x"9B",x"2A",x"38",x"0C",x"CD",x"31",x"29",x"CD", -- 0x2918 + x"AD",x"2A",x"21",x"E0",x"58",x"CB",x"CE",x"C9", -- 0x2920 + x"21",x"B7",x"40",x"34",x"2C",x"2C",x"36",x"46", -- 0x2928 + x"C9",x"3A",x"BC",x"40",x"47",x"3E",x"0A",x"90", -- 0x2930 + x"07",x"07",x"07",x"07",x"E6",x"F0",x"00",x"00", -- 0x2938 + x"21",x"AB",x"40",x"86",x"27",x"77",x"23",x"3E", -- 0x2940 + x"00",x"8E",x"27",x"77",x"2D",x"7E",x"E6",x"0F", -- 0x2948 + x"32",x"CD",x"51",x"7E",x"0F",x"0F",x"0F",x"0F", -- 0x2950 + x"E6",x"0F",x"32",x"ED",x"51",x"2C",x"7E",x"E6", -- 0x2958 + x"F0",x"28",x"0E",x"0F",x"0F",x"0F",x"0F",x"32", -- 0x2960 + x"2D",x"52",x"7E",x"E6",x"0F",x"32",x"0D",x"52", -- 0x2968 + x"C9",x"7E",x"E6",x"0F",x"C8",x"32",x"0D",x"52", -- 0x2970 + x"C9",x"21",x"B9",x"40",x"35",x"C0",x"11",x"8A", -- 0x2978 + x"06",x"FF",x"11",x"00",x"03",x"FF",x"2D",x"2D", -- 0x2980 + x"3E",x"01",x"77",x"32",x"00",x"41",x"AF",x"32", -- 0x2988 + x"16",x"41",x"C9",x"11",x"65",x"06",x"3A",x"13", -- 0x2990 + x"41",x"0F",x"38",x"11",x"3A",x"14",x"41",x"FE", -- 0x2998 + x"05",x"20",x"05",x"3E",x"04",x"32",x"14",x"41", -- 0x29A0 + x"C6",x"20",x"F6",x"40",x"5F",x"FF",x"21",x"B8", -- 0x29A8 + x"40",x"36",x"00",x"2D",x"34",x"C9",x"21",x"B8", -- 0x29B0 + x"40",x"35",x"C0",x"11",x"A5",x"06",x"FF",x"3E", -- 0x29B8 + x"05",x"32",x"0A",x"40",x"C9",x"21",x"B9",x"40", -- 0x29C0 + x"36",x"08",x"2D",x"36",x"32",x"2D",x"34",x"E5", -- 0x29C8 + x"21",x"A0",x"58",x"CB",x"DE",x"E1",x"11",x"26", -- 0x29D0 + x"06",x"FF",x"AF",x"32",x"3A",x"40",x"C9",x"21", -- 0x29D8 + x"B8",x"40",x"35",x"C0",x"36",x"0F",x"11",x"27", -- 0x29E0 + x"06",x"FF",x"11",x"26",x"06",x"FF",x"2D",x"34", -- 0x29E8 + x"C9",x"21",x"B8",x"40",x"35",x"C0",x"36",x"0F", -- 0x29F0 + x"E5",x"21",x"A0",x"58",x"CB",x"9E",x"E1",x"11", -- 0x29F8 + x"A7",x"06",x"FF",x"11",x"A6",x"06",x"FF",x"2D", -- 0x2A00 + x"34",x"C9",x"21",x"B9",x"40",x"35",x"28",x"05", -- 0x2A08 + x"2D",x"2D",x"36",x"16",x"C9",x"21",x"96",x"10", -- 0x2A10 + x"11",x"04",x"41",x"01",x"0C",x"00",x"ED",x"B0", -- 0x2A18 + x"21",x"B2",x"10",x"11",x"20",x"41",x"01",x"C0", -- 0x2A20 + x"00",x"ED",x"B0",x"11",x"60",x"06",x"FF",x"AF", -- 0x2A28 + x"21",x"13",x"41",x"77",x"2C",x"77",x"2C",x"77", -- 0x2A30 + x"32",x"12",x"41",x"32",x"1C",x"41",x"32",x"16", -- 0x2A38 + x"41",x"3E",x"2E",x"32",x"11",x"41",x"3E",x"60", -- 0x2A40 + x"32",x"1A",x"41",x"21",x"B7",x"40",x"34",x"2C", -- 0x2A48 + x"36",x"00",x"C9",x"21",x"B8",x"40",x"35",x"C0", -- 0x2A50 + x"11",x"A0",x"06",x"FF",x"3E",x"05",x"32",x"0A", -- 0x2A58 + x"40",x"C9",x"E5",x"06",x"06",x"21",x"AC",x"51", -- 0x2A60 + x"11",x"1F",x"00",x"36",x"10",x"23",x"36",x"10", -- 0x2A68 + x"19",x"10",x"F8",x"E1",x"C9",x"E5",x"06",x"06", -- 0x2A70 + x"21",x"AC",x"51",x"11",x"20",x"00",x"DD",x"21", -- 0x2A78 + x"D8",x"02",x"DD",x"7E",x"00",x"77",x"19",x"DD", -- 0x2A80 + x"23",x"10",x"F7",x"06",x"06",x"21",x"AD",x"51", -- 0x2A88 + x"DD",x"7E",x"00",x"77",x"19",x"DD",x"23",x"10", -- 0x2A90 + x"F7",x"E1",x"C9",x"06",x"30",x"21",x"20",x"41", -- 0x2A98 + x"CB",x"4E",x"20",x"05",x"23",x"10",x"F9",x"37", -- 0x2AA0 + x"C9",x"CB",x"8E",x"A7",x"C9",x"21",x"55",x"41", -- 0x2AA8 + x"11",x"06",x"00",x"4B",x"06",x"18",x"CB",x"4E", -- 0x2AB0 + x"20",x"0B",x"19",x"10",x"F9",x"7D",x"D6",x"91", -- 0x2AB8 + x"6F",x"0D",x"20",x"F0",x"C9",x"36",x"01",x"21", -- 0x2AC0 + x"1A",x"41",x"34",x"C9",x"3E",x"03",x"32",x"06", -- 0x2AC8 + x"68",x"0F",x"32",x"07",x"68",x"3A",x"F3",x"58", -- 0x2AD0 + x"32",x"05",x"68",x"0F",x"32",x"03",x"68",x"0F", -- 0x2AD8 + x"32",x"00",x"68",x"32",x"01",x"68",x"32",x"02", -- 0x2AE0 + x"68",x"21",x"A0",x"42",x"11",x"20",x"00",x"06", -- 0x2AE8 + x"08",x"AF",x"B6",x"19",x"10",x"FC",x"0F",x"38", -- 0x2AF0 + x"05",x"21",x"C0",x"58",x"CB",x"96",x"21",x"B1", -- 0x2AF8 + x"2D",x"DD",x"21",x"C0",x"58",x"FD",x"21",x"F3", -- 0x2B00 + x"58",x"CD",x"36",x"2D",x"21",x"E1",x"2D",x"DD", -- 0x2B08 + x"21",x"90",x"58",x"FD",x"21",x"F1",x"58",x"CD", -- 0x2B10 + x"1A",x"2C",x"21",x"F1",x"2D",x"DD",x"21",x"B0", -- 0x2B18 + x"58",x"FD",x"21",x"F0",x"58",x"CD",x"1A",x"2C", -- 0x2B20 + x"21",x"11",x"2E",x"DD",x"21",x"E0",x"58",x"FD", -- 0x2B28 + x"21",x"F5",x"58",x"CD",x"1A",x"2C",x"21",x"B2", -- 0x2B30 + x"2D",x"DD",x"21",x"A0",x"58",x"FD",x"21",x"F2", -- 0x2B38 + x"58",x"CD",x"92",x"2B",x"06",x"00",x"21",x"F5", -- 0x2B40 + x"58",x"CD",x"6D",x"2B",x"21",x"F6",x"58",x"CD", -- 0x2B48 + x"6D",x"2B",x"21",x"F0",x"58",x"CD",x"6D",x"2B", -- 0x2B50 + x"21",x"F2",x"58",x"CD",x"6D",x"2B",x"21",x"F1", -- 0x2B58 + x"58",x"CD",x"6D",x"2B",x"CB",x"40",x"C0",x"3E", -- 0x2B60 + x"FF",x"32",x"00",x"78",x"C9",x"7E",x"A7",x"C8", -- 0x2B68 + x"CB",x"C0",x"32",x"00",x"78",x"C9",x"85",x"6F", -- 0x2B70 + x"3E",x"00",x"8C",x"67",x"7E",x"C9",x"78",x"87", -- 0x2B78 + x"CD",x"76",x"2B",x"5F",x"23",x"56",x"EB",x"C9", -- 0x2B80 + x"E1",x"87",x"CD",x"76",x"2B",x"5F",x"23",x"56", -- 0x2B88 + x"EB",x"E9",x"DD",x"7E",x"00",x"A7",x"CA",x"20", -- 0x2B90 + x"2C",x"4F",x"06",x"08",x"1E",x"80",x"7B",x"A1", -- 0x2B98 + x"20",x"05",x"CB",x"3B",x"10",x"F8",x"C9",x"DD", -- 0x2BA0 + x"7E",x"02",x"A3",x"20",x"09",x"DD",x"73",x"02", -- 0x2BA8 + x"05",x"CD",x"7E",x"2B",x"18",x"0C",x"DD",x"35", -- 0x2BB0 + x"0C",x"C2",x"13",x"2C",x"DD",x"6E",x"06",x"DD", -- 0x2BB8 + x"66",x"07",x"7E",x"23",x"DD",x"75",x"06",x"DD", -- 0x2BC0 + x"74",x"07",x"FE",x"F0",x"38",x"2A",x"21",x"BC", -- 0x2BC8 + x"2B",x"E5",x"E6",x"0F",x"CD",x"88",x"2B",x"14", -- 0x2BD0 + x"2D",x"24",x"2D",x"F7",x"2B",x"F7",x"2B",x"F7", -- 0x2BD8 + x"2B",x"F7",x"2B",x"F7",x"2B",x"F7",x"2B",x"F7", -- 0x2BE0 + x"2B",x"F7",x"2B",x"F7",x"2B",x"F7",x"2B",x"F7", -- 0x2BE8 + x"2B",x"F7",x"2B",x"F7",x"2B",x"A0",x"2D",x"C9", -- 0x2BF0 + x"47",x"07",x"07",x"07",x"E6",x"07",x"21",x"BA", -- 0x2BF8 + x"2D",x"CD",x"76",x"2B",x"DD",x"77",x"0C",x"78", -- 0x2C00 + x"E6",x"1F",x"21",x"C2",x"2D",x"CD",x"76",x"2B", -- 0x2C08 + x"DD",x"77",x"0E",x"DD",x"7E",x"0E",x"FD",x"77", -- 0x2C10 + x"00",x"C9",x"DD",x"7E",x"00",x"A7",x"20",x"23", -- 0x2C18 + x"DD",x"7E",x"02",x"A7",x"3E",x"00",x"FD",x"77", -- 0x2C20 + x"00",x"C8",x"DD",x"36",x"00",x"00",x"DD",x"36", -- 0x2C28 + x"02",x"00",x"DD",x"36",x"0D",x"00",x"DD",x"36", -- 0x2C30 + x"0E",x"00",x"DD",x"36",x"0F",x"00",x"FD",x"36", -- 0x2C38 + x"00",x"00",x"C9",x"4F",x"06",x"08",x"1E",x"80", -- 0x2C40 + x"7B",x"A1",x"20",x"05",x"CB",x"3B",x"10",x"F8", -- 0x2C48 + x"C9",x"DD",x"7E",x"02",x"A3",x"20",x"3F",x"DD", -- 0x2C50 + x"73",x"02",x"05",x"78",x"07",x"07",x"07",x"4F", -- 0x2C58 + x"06",x"00",x"E5",x"09",x"DD",x"E5",x"D1",x"13", -- 0x2C60 + x"13",x"13",x"01",x"08",x"00",x"ED",x"B0",x"E1", -- 0x2C68 + x"DD",x"7E",x"06",x"E6",x"7F",x"DD",x"77",x"0C", -- 0x2C70 + x"DD",x"7E",x"04",x"DD",x"77",x"0E",x"DD",x"7E", -- 0x2C78 + x"09",x"47",x"0F",x"0F",x"0F",x"0F",x"E6",x"0F", -- 0x2C80 + x"DD",x"77",x"0B",x"E6",x"08",x"20",x"07",x"DD", -- 0x2C88 + x"70",x"0F",x"DD",x"36",x"0D",x"00",x"DD",x"35", -- 0x2C90 + x"0C",x"20",x"5A",x"DD",x"7E",x"08",x"A7",x"28", -- 0x2C98 + x"10",x"DD",x"35",x"08",x"20",x"0B",x"7B",x"2F", -- 0x2CA0 + x"DD",x"A6",x"00",x"DD",x"77",x"00",x"C3",x"1A", -- 0x2CA8 + x"2C",x"DD",x"7E",x"06",x"E6",x"7F",x"DD",x"77", -- 0x2CB0 + x"0C",x"DD",x"CB",x"06",x"7E",x"28",x"16",x"DD", -- 0x2CB8 + x"7E",x"05",x"ED",x"44",x"DD",x"77",x"05",x"DD", -- 0x2CC0 + x"CB",x"0D",x"46",x"DD",x"CB",x"0D",x"C6",x"28", -- 0x2CC8 + x"24",x"DD",x"CB",x"0D",x"86",x"DD",x"7E",x"04", -- 0x2CD0 + x"DD",x"86",x"07",x"DD",x"77",x"04",x"DD",x"77", -- 0x2CD8 + x"0E",x"DD",x"7E",x"09",x"DD",x"86",x"0A",x"DD", -- 0x2CE0 + x"77",x"09",x"47",x"DD",x"7E",x"0B",x"E6",x"08", -- 0x2CE8 + x"20",x"03",x"DD",x"70",x"0F",x"DD",x"7E",x"0E", -- 0x2CF0 + x"DD",x"86",x"05",x"DD",x"77",x"0E",x"6F",x"26", -- 0x2CF8 + x"00",x"DD",x"7E",x"03",x"E6",x"70",x"28",x"08", -- 0x2D00 + x"0F",x"0F",x"0F",x"0F",x"47",x"29",x"10",x"FD", -- 0x2D08 + x"FD",x"75",x"00",x"C9",x"DD",x"6E",x"06",x"DD", -- 0x2D10 + x"66",x"07",x"7E",x"DD",x"77",x"06",x"23",x"7E", -- 0x2D18 + x"DD",x"77",x"07",x"C9",x"DD",x"6E",x"06",x"DD", -- 0x2D20 + x"66",x"07",x"7E",x"23",x"DD",x"75",x"06",x"DD", -- 0x2D28 + x"74",x"07",x"32",x"F4",x"58",x"C9",x"CD",x"40", -- 0x2D30 + x"2D",x"CD",x"64",x"2D",x"CD",x"88",x"2D",x"C9", -- 0x2D38 + x"DD",x"7E",x"00",x"CB",x"47",x"28",x"0A",x"DD", -- 0x2D40 + x"CB",x"00",x"86",x"3E",x"08",x"DD",x"77",x"01", -- 0x2D48 + x"C9",x"DD",x"7E",x"01",x"A7",x"28",x"08",x"DD", -- 0x2D50 + x"35",x"01",x"FD",x"CB",x"00",x"C6",x"C9",x"FD", -- 0x2D58 + x"CB",x"00",x"86",x"C9",x"DD",x"7E",x"00",x"CB", -- 0x2D60 + x"4F",x"28",x"0A",x"DD",x"CB",x"00",x"8E",x"3E", -- 0x2D68 + x"1D",x"DD",x"77",x"02",x"C9",x"DD",x"7E",x"02", -- 0x2D70 + x"A7",x"28",x"08",x"DD",x"35",x"02",x"FD",x"CB", -- 0x2D78 + x"00",x"CE",x"C9",x"FD",x"CB",x"00",x"8E",x"C9", -- 0x2D80 + x"DD",x"7E",x"00",x"CB",x"57",x"28",x"0C",x"3A", -- 0x2D88 + x"A0",x"58",x"CB",x"47",x"20",x"05",x"FD",x"CB", -- 0x2D90 + x"00",x"D6",x"C9",x"FD",x"CB",x"00",x"96",x"C9", -- 0x2D98 + x"DD",x"7E",x"02",x"2F",x"DD",x"A6",x"00",x"AF", -- 0x2DA0 + x"FD",x"77",x"00",x"DD",x"77",x"00",x"C3",x"20", -- 0x2DA8 + x"2C",x"00",x"21",x"2E",x"40",x"2E",x"6F",x"2E", -- 0x2DB0 + x"85",x"2E",x"01",x"02",x"04",x"08",x"10",x"20", -- 0x2DB8 + x"40",x"00",x"FF",x"00",x"40",x"55",x"5F",x"68", -- 0x2DC0 + x"70",x"80",x"8E",x"9A",x"A0",x"AA",x"B4",x"B8", -- 0x2DC8 + x"C0",x"C7",x"CD",x"D0",x"D5",x"DA",x"DC",x"E0", -- 0x2DD0 + x"1C",x"35",x"87",x"A5",x"C4",x"D3",x"CA",x"E3", -- 0x2DD8 + x"E6",x"20",x"40",x"10",x"87",x"00",x"0A",x"FF", -- 0x2DE0 + x"FF",x"40",x"20",x"FF",x"90",x"00",x"01",x"FF", -- 0x2DE8 + x"FF",x"40",x"20",x"FB",x"87",x"00",x"01",x"FF", -- 0x2DF0 + x"FF",x"40",x"20",x"FB",x"87",x"00",x"01",x"FF", -- 0x2DF8 + x"FF",x"20",x"70",x"FB",x"87",x"00",x"02",x"FF", -- 0x2E00 + x"FF",x"20",x"70",x"FB",x"87",x"00",x"02",x"FF", -- 0x2E08 + x"FF",x"80",x"20",x"F4",x"87",x"FE",x"10",x"FF", -- 0x2E10 + x"FF",x"80",x"20",x"F4",x"87",x"04",x"01",x"FF", -- 0x2E18 + x"FF",x"68",x"00",x"68",x"6A",x"6C",x"8B",x"88", -- 0x2E20 + x"00",x"68",x"00",x"68",x"67",x"6A",x"88",x"88", -- 0x2E28 + x"00",x"68",x"00",x"68",x"6A",x"6C",x"8B",x"8F", -- 0x2E30 + x"6E",x"00",x"6E",x"6C",x"6A",x"8F",x"8F",x"FF", -- 0x2E38 + x"80",x"6C",x"6B",x"8C",x"6B",x"6A",x"8B",x"6A", -- 0x2E40 + x"69",x"8A",x"69",x"68",x"89",x"65",x"67",x"88", -- 0x2E48 + x"4A",x"00",x"4A",x"00",x"4A",x"88",x"6C",x"6B", -- 0x2E50 + x"8C",x"6B",x"6A",x"8B",x"6A",x"69",x"8A",x"69", -- 0x2E58 + x"68",x"89",x"65",x"67",x"88",x"4A",x"00",x"4A", -- 0x2E60 + x"00",x"4A",x"88",x"A0",x"A0",x"10",x"FF",x"80", -- 0x2E68 + x"60",x"69",x"00",x"69",x"00",x"69",x"87",x"87", -- 0x2E70 + x"87",x"68",x"00",x"68",x"00",x"68",x"86",x"86", -- 0x2E78 + x"86",x"A0",x"A0",x"10",x"FF",x"65",x"67",x"67", -- 0x2E80 + x"65",x"68",x"87",x"00",x"87",x"60",x"65",x"68", -- 0x2E88 + x"00",x"68",x"65",x"69",x"88",x"00",x"88",x"60", -- 0x2E90 + x"A0",x"A0",x"A0",x"A0",x"A0",x"10",x"FF",x"FF", -- 0x2E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3818 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3820 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3828 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3830 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3838 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/Omega_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/Omega_MiST/rtl/build_id.v new file mode 100644 index 00000000..af3dbbfc --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180108" +`define BUILD_TIME "213858" diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..5f8a3a74 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + +-- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(3), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(2), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/Omega_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/Omega_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..5a4d0094 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..550e610e --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..e924e09e --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 0) = "11111010") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 0) = "11111010") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..dbe0d0d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/Omega_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/Omega_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/Omega_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/Omega_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/Omega_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/Omega_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.qpf b/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.qpf new file mode 100644 index 00000000..258424fc --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "Orbitron" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.qsf b/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.qsf new file mode 100644 index 00000000..ce29d38c --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Orbitron_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Orbitron.sv +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Orbitron +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.srf b/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/Orbitron.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/README.txt b/Arcade/Galaxian Hardware/Orbitron_MiST/README.txt new file mode 100644 index 00000000..3a2cf965 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Orbitron port to MiST by Gehstock +-- 18 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + +--Rotate and Fix Video \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/Release/Orbitron.rbf b/Arcade/Galaxian Hardware/Orbitron_MiST/Release/Orbitron.rbf new file mode 100644 index 00000000..1b93f88e Binary files /dev/null and b/Arcade/Galaxian Hardware/Orbitron_MiST/Release/Orbitron.rbf differ diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/clean.bat b/Arcade/Galaxian Hardware/Orbitron_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/Orbitron.sv b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/Orbitron.sv new file mode 100644 index 00000000..dd535dc3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/Orbitron.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Orbitron +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Orbitron +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Orbitron;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian orbitron +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,2'b00,m_right,m_left}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,2'b00,m_up ,m_down}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..dacb0a04 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1H is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1H is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00", + X"00",X"62",X"92",X"8A",X"86",X"86",X"42",X"00",X"00",X"8C",X"D2",X"B2",X"92",X"82",X"84",X"00", + X"00",X"08",X"FE",X"48",X"28",X"18",X"08",X"00",X"00",X"1C",X"A2",X"A2",X"A2",X"A6",X"E4",X"00", + X"00",X"8C",X"92",X"92",X"92",X"52",X"3C",X"00",X"00",X"C0",X"A0",X"90",X"8E",X"80",X"80",X"00", + X"00",X"6C",X"92",X"92",X"92",X"92",X"6C",X"00",X"00",X"7C",X"92",X"92",X"92",X"92",X"60",X"00", + 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X"04",X"00",X"02",X"00",X"08",X"11",X"21",X"00",X"5C",X"40",X"48",X"60",X"08",X"04",X"00",X"00", + X"08",X"08",X"08",X"04",X"14",X"23",X"11",X"12",X"00",X"80",X"84",X"98",X"A0",X"A0",X"00",X"44", + X"04",X"06",X"06",X"01",X"04",X"10",X"20",X"00",X"62",X"4C",X"70",X"88",X"40",X"44",X"40",X"40"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..fd77d08e --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_1K is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_1K is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00", + X"00",X"62",X"92",X"8A",X"86",X"86",X"42",X"00",X"00",X"8C",X"D2",X"B2",X"92",X"82",X"84",X"00", + X"00",X"08",X"FE",X"48",X"28",X"18",X"08",X"00",X"00",X"1C",X"A2",X"A2",X"A2",X"A6",X"E4",X"00", + X"00",X"8C",X"92",X"92",X"92",X"52",X"3C",X"00",X"00",X"C0",X"A0",X"90",X"8E",X"80",X"80",X"00", + X"00",X"6C",X"92",X"92",X"92",X"92",X"6C",X"00",X"00",X"7C",X"92",X"92",X"92",X"92",X"60",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0E",X"0E",X"0C",X"08",X"0C",X"0E",X"0E",X"0F",X"0F",X"0F",X"0F", + X"00",X"00",X"00",X"18",X"18",X"00",X"00",X"00",X"18",X"42",X"24",X"81",X"81",X"24",X"42",X"18", + X"40",X"20",X"10",X"08",X"04",X"02",X"00",X"00",X"00",X"00",X"00",X"30",X"30",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00", + 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X"80",X"81",X"82",X"C0",X"48",X"20",X"10",X"0F",X"09",X"81",X"01",X"03",X"02",X"04",X"08",X"F0", + X"00",X"00",X"20",X"19",X"08",X"00",X"20",X"03",X"00",X"00",X"00",X"60",X"00",X"10",X"00",X"20", + X"07",X"23",X"15",X"55",X"02",X"00",X"00",X"00",X"80",X"00",X"10",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"08",X"0B",X"07",X"03",X"27",X"00",X"00",X"00",X"20",X"40",X"00",X"80",X"C0", + X"17",X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"D0",X"90",X"90",X"80",X"80",X"00",X"00",X"00", + X"00",X"00",X"10",X"08",X"04",X"25",X"17",X"15",X"00",X"10",X"20",X"40",X"60",X"E0",X"C8",X"C2", + X"07",X"03",X"01",X"00",X"08",X"11",X"21",X"00",X"DC",X"C0",X"C8",X"E0",X"C8",X"44",X"00",X"00", + X"08",X"08",X"08",X"04",X"14",X"03",X"01",X"03",X"00",X"80",X"84",X"98",X"A0",X"A0",X"80",X"C4", + X"07",X"07",X"07",X"01",X"04",X"10",X"20",X"00",X"E2",X"CC",X"F0",X"88",X"40",X"44",X"40",X"40"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..9cf7380a --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GALAXIAN_6L is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GALAXIAN_6L is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7A",X"36",X"07",X"00",X"F0",X"38",X"1F",X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38", + X"00",X"36",X"07",X"F0",X"00",X"33",X"3F",X"DB",X"00",X"3F",X"57",X"C6",X"00",X"C6",X"3F",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd new file mode 100644 index 00000000..7d2fd29c --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..401c50ae --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,662 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 10239) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"00",X"44",X"C3",X"41",X"02",X"00",X"FF",X"FF",X"FF",X"FF",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"24",X"52",X"22",X"75",X"0D",X"01",X"69",X"02",X"21",X"B0",X"0D",X"36",X"00",X"11", + X"B1",X"0D",X"ED",X"B0",X"21",X"00",X"00",X"22",X"69",X"0D",X"22",X"6B",X"0D",X"22",X"61",X"0D", + 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X"00",X"92",X"04",X"24",X"04",X"21",X"04",X"90",X"92",X"42",X"49",X"09",X"04",X"01",X"00",X"22", + X"40",X"88",X"80",X"00",X"84",X"00",X"88",X"10",X"88",X"24",X"22",X"11",X"09",X"22",X"12",X"12", + X"04",X"00",X"24",X"92",X"49",X"24",X"82",X"49",X"21",X"20",X"40",X"01",X"09",X"11",X"12",X"21", + X"00",X"82",X"44",X"80",X"80",X"24",X"02",X"02",X"42",X"08",X"10",X"12",X"08",X"42",X"12",X"24", + X"81",X"04",X"92",X"22",X"49",X"04",X"80",X"90",X"24",X"10",X"84",X"01",X"02",X"04",X"00",X"00", + X"00",X"00",X"00",X"08",X"84",X"20",X"10",X"02",X"00",X"00",X"20",X"24",X"80",X"80",X"00",X"92", + X"04",X"00",X"21",X"11",X"04",X"92",X"02",X"44",X"80",X"81",X"10",X"82",X"12",X"10",X"91",X"24", + X"84",X"92",X"24",X"80",X"49",X"24",X"49",X"24",X"92",X"24",X"22",X"12",X"41",X"24",X"24",X"92", + X"49",X"20",X"08",X"11",X"04",X"20",X"10",X"10",X"81",X"08",X"40",X"08",X"49",X"20",X"91",X"00", + X"AA",X"AA",X"AA",X"AA",X"AA",X"49",X"24",X"20",X"01",X"00",X"01",X"02",X"40",X"84",X"11",X"01", + X"22",X"48",X"02",X"09",X"00",X"40",X"12",X"12",X"01",X"00",X"84",X"20",X"40",X"40",X"42",X"48", + X"10",X"00",X"08",X"41",X"11",X"01",X"04",X"42",X"49",X"12",X"41",X"04",X"00",X"09",X"24",X"20", + X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"40",X"02",X"10",X"10",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0B",X"01",X"0E",X"00",X"BE",X"C2",X"16",X"08",X"21",X"2F",X"0C",X"C3",X"61",X"0A",X"23",X"0D", + X"C2",X"0C",X"08",X"0E",X"0C",X"BE",X"CA",X"05",X"0A",X"23",X"0D",X"C2",X"1D",X"08",X"FE",X"C3", + X"CA",X"B6",X"08",X"FE",X"CD",X"CA",X"AD",X"08",X"0E",X"04",X"BE",X"CA",X"C3",X"09",X"23",X"0D", + X"C2",X"32",X"08",X"E6",X"C0",X"FE",X"40",X"CA",X"6D",X"09",X"FE",X"80",X"CA",X"52",X"09",X"7A", + X"E6",X"C7",X"D6",X"04",X"CA",X"49",X"09",X"3D",X"CA",X"43",X"09",X"3D",X"CA",X"3A",X"09",X"7A", + X"E6",X"C0",X"CA",X"DB",X"08",X"7A",X"E6",X"07",X"CA",X"CF",X"08",X"D6",X"02",X"CA",X"B6",X"08", + X"D6",X"02",X"CA",X"AD",X"08",X"D6",X"03",X"CA",X"95",X"08",X"7A",X"E6",X"0A",X"C2",X"9F",X"0A", + X"7A",X"E6",X"07",X"4F",X"3D",X"21",X"E5",X"0C",X"09",X"CD",X"33",X"07",X"CD",X"55",X"07",X"FE"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/build_id.v new file mode 100644 index 00000000..55315735 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "164536" diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..b881e738 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/galaxian.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..014e6f7a --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,88 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..596db956 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '1'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_2P_LE & I_2P_RI & I_2P_RI & I_1P_SH & I_1P_LE & I_1P_RI & I_COIN2 & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else I_2P_LE & "1" & "0" & I_1P_SH & I_1P_LE & I_1P_RI & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "0000" & W_TABLE & "000"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..dbe0d0d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1K VID-Rom + k_rom : entity work.GALAXIAN_1K + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + -- 1H VID-Rom + h_rom : entity work.GALAXIAN_1H + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..2a921604 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/scandoubler.v @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/Orbitron_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.qpf b/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.qpf new file mode 100644 index 00000000..02128464 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 21:51:58 January 08, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "21:51:58 January 08, 2018" + +# Revisions + +PROJECT_REVISION = "Pisces" +PROJECT_REVISION = "Catacomb" diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.qsf b/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.qsf new file mode 100644 index 00000000..60e75623 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaxian_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Pisces +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pisces.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.srf b/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.srf new file mode 100644 index 00000000..14cddd5e --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/Pisces.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/README.txt b/Arcade/Galaxian Hardware/Pisces_MiST/README.txt new file mode 100644 index 00000000..2a40daff --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Pisces port to MiST by Gehstock +-- 19 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/Release/Pisces.rbf b/Arcade/Galaxian Hardware/Pisces_MiST/Release/Pisces.rbf new file mode 100644 index 00000000..6e71f3a8 Binary files /dev/null and b/Arcade/Galaxian Hardware/Pisces_MiST/Release/Pisces.rbf differ diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/clean.bat b/Arcade/Galaxian Hardware/Pisces_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/Pisces.sv b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/Pisces.sv new file mode 100644 index 00000000..64a3f2ec --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/Pisces.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: Catacomb +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Pisces +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Pisces;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian catacomb +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..787ca26f --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,541 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1H is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(11 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1H is + + + type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"1C",x"02",x"3C",x"3D",x"14",x"10",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"00",x"60",x"C0",x"00", -- 0x0058 + x"38",x"48",x"1E",x"3E",x"3E",x"1E",x"3C",x"30", -- 0x0060 + x"00",x"00",x"00",x"30",x"10",x"08",x"00",x"00", -- 0x0068 + x"02",x"06",x"04",x"00",x"00",x"00",x"00",x"00", -- 0x0070 + x"00",x"00",x"38",x"1C",x"70",x"30",x"34",x"18", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"04",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"40",x"00",x"00", -- 0x0168 + x"00",x"01",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x0170 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"04",x"00",x"09", -- 0x0180 + x"00",x"00",x"00",x"00",x"00",x"40",x"00",x"00", -- 0x0188 + x"00",x"00",x"04",x"00",x"01",x"00",x"00",x"00", -- 0x0190 + x"10",x"80",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"01",x"08",x"00",x"00",x"00", -- 0x01A0 + x"00",x"00",x"00",x"40",x"00",x"00",x"00",x"00", -- 0x01A8 + x"11",x"04",x"00",x"00",x"08",x"00",x"00",x"00", -- 0x01B0 + x"20",x"00",x"00",x"00",x"00",x"20",x"00",x"00", -- 0x01B8 + x"00",x"00",x"00",x"02",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"20",x"00",x"00",x"00",x"00", -- 0x01C8 + x"08",x"00",x"01",x"00",x"00",x"04",x"00",x"00", -- 0x01D0 + x"88",x"00",x"00",x"10",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"03",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x01E0 + x"00",x"00",x"00",x"80",x"00",x"C0",x"00",x"60", -- 0x01E8 + x"00",x"00",x"00",x"00",x"00",x"01",x"00",x"03", -- 0x01F0 + x"00",x"60",x"00",x"C0",x"00",x"80",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"60",x"00",x"60", -- 0x0208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"00",x"60",x"00",x"60",x"00",x"00",x"00",x"00", -- 0x0218 + x"10",x"02",x"00",x"20",x"00",x"00",x"40",x"00", -- 0x0220 + x"00",x"10",x"02",x"40",x"00",x"00",x"04",x"00", -- 0x0228 + x"00",x"40",x"10",x"04",x"00",x"80",x"02",x"20", -- 0x0230 + x"00",x"08",x"80",x"00",x"01",x"00",x"20",x"00", -- 0x0238 + x"00",x"20",x"58",x"48",x"24",x"19",x"01",x"00", -- 0x0240 + x"00",x"04",x"08",x"10",x"12",x"0C",x"A0",x"38", -- 0x0248 + x"00",x"01",x"19",x"24",x"48",x"58",x"20",x"00", -- 0x0250 + x"38",x"A0",x"0C",x"12",x"10",x"08",x"04",x"00", -- 0x0258 + x"00",x"02",x"20",x"10",x"00",x"02",x"46",x"00", -- 0x0260 + x"00",x"40",x"04",x"08",x"00",x"60",x"62",x"80", -- 0x0268 + x"00",x"46",x"02",x"00",x"10",x"20",x"02",x"00", -- 0x0270 + x"80",x"62",x"60",x"00",x"08",x"04",x"40",x"00", -- 0x0278 + x"00",x"18",x"34",x"34",x"14",x"08",x"09",x"00", -- 0x0280 + x"00",x"00",x"00",x"0E",x"10",x"08",x"26",x"30", -- 0x0288 + x"00",x"09",x"08",x"14",x"34",x"34",x"18",x"00", -- 0x0290 + x"30",x"26",x"08",x"10",x"0E",x"00",x"00",x"00", -- 0x0298 + x"00",x"08",x"1C",x"1E",x"1E",x"0E",x"06",x"00", -- 0x02A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 + x"00",x"06",x"0E",x"1E",x"1E",x"1C",x"08",x"00", -- 0x02B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 + x"00",x"08",x"1C",x"1E",x"1E",x"0E",x"06",x"00", -- 0x02C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 + x"00",x"06",x"0E",x"1E",x"1E",x"1C",x"08",x"00", -- 0x02D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 + x"00",x"08",x"1C",x"1E",x"1E",x"0E",x"06",x"00", -- 0x02E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"06",x"0E",x"1E",x"1E",x"1C",x"08",x"00", -- 0x02F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 + x"00",x"00",x"00",x"01",x"03",x"1C",x"23",x"C0", -- 0x0300 + x"00",x"7E",x"FC",x"08",x"F1",x"13",x"FF",x"0F", -- 0x0308 + x"23",x"1C",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0310 + x"FF",x"13",x"F1",x"08",x"FC",x"7E",x"00",x"00", -- 0x0318 + x"1C",x"38",x"C2",x"06",x"C2",x"38",x"1C",x"00", -- 0x0320 + x"C3",x"C3",x"C3",x"C3",x"C3",x"C3",x"C3",x"C3", -- 0x0328 + x"C3",x"C3",x"C3",x"C3",x"C3",x"C3",x"FF",x"FF", -- 0x0330 + x"C3",x"C3",x"C3",x"C3",x"FF",x"FF",x"FF",x"FF", -- 0x0338 + x"C3",x"C3",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0340 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0348 + x"1F",x"C6",x"F2",x"1D",x"03",x"00",x"00",x"00", -- 0x0350 + x"CC",x"E0",x"80",x"40",x"98",x"F0",x"00",x"00", -- 0x0358 + x"03",x"06",x"0D",x"1E",x"F9",x"06",x"1C",x"FF", -- 0x0360 + x"60",x"FE",x"1F",x"61",x"70",x"F8",x"0C",x"E6", -- 0x0368 + x"06",x"D3",x"FC",x"3B",x"1D",x"0C",x"04",x"00", -- 0x0370 + x"0F",x"78",x"A0",x"18",x"C7",x"3E",x"0C",x"00", -- 0x0378 + x"00",x"01",x"03",x"07",x"03",x"07",x"0F",x"3F", -- 0x0380 + x"80",x"80",x"D8",x"F8",x"F8",x"F0",x"F0",x"F0", -- 0x0388 + x"1F",x"1F",x"1F",x"0F",x"03",x"07",x"07",x"01", -- 0x0390 + x"F8",x"F8",x"F0",x"E0",x"F8",x"FC",x"78",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"04",x"01",x"03", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"90", -- 0x03A8 + x"07",x"02",x"02",x"08",x"00",x"00",x"00",x"00", -- 0x03B0 + x"C0",x"80",x"A0",x"10",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"04",x"24",x"04",x"4E",x"27", -- 0x03C0 + x"00",x"00",x"20",x"40",x"11",x"80",x"A4",x"C8", -- 0x03C8 + x"07",x"03",x"25",x"00",x"08",x"00",x"00",x"00", -- 0x03D0 + x"C0",x"20",x"90",x"A0",x"20",x"50",x"00",x"00", -- 0x03D8 + x"00",x"00",x"42",x"20",x"04",x"0F",x"E7",x"3F", -- 0x03E0 + x"00",x"20",x"44",x"C8",x"80",x"80",x"D0",x"EC", -- 0x03E8 + x"07",x"07",x"0D",x"1D",x"29",x"42",x"01",x"00", -- 0x03F0 + x"C0",x"A0",x"B0",x"88",x"44",x"20",x"10",x"08", -- 0x03F8 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0400 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0408 + x"07",x"00",x"06",x"09",x"09",x"09",x"06",x"00", -- 0x0410 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"C0",x"00", -- 0x0418 + x"00",x"07",x"08",x"08",x"07",x"00",x"07",x"08", -- 0x0420 + x"00",x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20", -- 0x0428 + x"08",x"07",x"00",x"00",x"0F",x"04",x"00",x"00", -- 0x0430 + x"20",x"C0",x"00",x"20",x"E0",x"20",x"00",x"00", -- 0x0438 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0440 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0448 + x"07",x"00",x"06",x"09",x"08",x"08",x"04",x"00", -- 0x0450 + x"C0",x"00",x"20",x"20",x"A0",x"60",x"20",x"00", -- 0x0458 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0460 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0468 + x"07",x"00",x"08",x"0D",x"0B",x"09",x"08",x"00", -- 0x0470 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"20",x"00", -- 0x0478 + x"2F",x"2B",x"7D",x"7B",x"7E",x"FF",x"BF",x"4F", -- 0x0480 + x"E3",x"E3",x"E3",x"E3",x"E3",x"73",x"FB",x"FF", -- 0x0488 + x"7F",x"FF",x"FF",x"FF",x"7F",x"9F",x"5F",x"6F", -- 0x0490 + x"FF",x"FF",x"FF",x"FF",x"7F",x"3F",x"7B",x"77", -- 0x0498 + x"27",x"37",x"37",x"3B",x"3B",x"3D",x"7D",x"7F", -- 0x04A0 + x"FE",x"FC",x"DE",x"FF",x"FF",x"8F",x"EF",x"F7", -- 0x04A8 + x"7F",x"FF",x"FF",x"BE",x"BE",x"5F",x"5F",x"4F", -- 0x04B0 + x"EF",x"7F",x"7F",x"3F",x"37",x"77",x"7F",x"FE", -- 0x04B8 + x"FF",x"DF",x"DF",x"7F",x"7F",x"17",x"1B",x"1B", -- 0x04C0 + x"5F",x"8F",x"CF",x"E7",x"F7",x"FF",x"FF",x"DF", -- 0x04C8 + x"7E",x"3E",x"7E",x"37",x"37",x"3F",x"7F",x"FF", -- 0x04D0 + x"FF",x"FF",x"FD",x"FD",x"FB",x"FF",x"BF",x"DF", -- 0x04D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 + x"FF",x"FF",x"E7",x"07",x"07",x"06",x"FE",x"FE", -- 0x04E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 + x"66",x"06",x"06",x"64",x"3C",x"1C",x"08",x"00", -- 0x04F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 + x"00",x"08",x"1C",x"3C",x"64",x"06",x"06",x"66", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 + x"FE",x"FE",x"E7",x"07",x"07",x"07",x"FF",x"FF", -- 0x0518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"FF",x"E7",x"07",x"07",x"07",x"FE",x"66",x"06", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"06",x"64",x"3C",x"1C",x"08",x"00",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 + x"00",x"00",x"00",x"08",x"1C",x"3C",x"64",x"06", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"06",x"66",x"FE",x"E7",x"07",x"07",x"07",x"FF", -- 0x0558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 + x"07",x"07",x"FF",x"FF",x"FF",x"66",x"06",x"06", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"64",x"3C",x"1C",x"08",x"00",x"00",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"00",x"00",x"08",x"1C",x"3C",x"64", -- 0x0588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 + x"06",x"06",x"66",x"FF",x"FF",x"FF",x"E7",x"07", -- 0x0598 + x"FF",x"F9",x"F1",x"61",x"61",x"63",x"37",x"3F", -- 0x05A0 + x"F9",x"F8",x"F8",x"FE",x"FF",x"FF",x"F8",x"F0", -- 0x05A8 + x"3F",x"0F",x"0E",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 + x"F0",x"7B",x"3F",x"3E",x"00",x"00",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"01",x"0F",x"0F",x"3F", -- 0x05C0 + x"00",x"00",x"00",x"00",x"FE",x"FF",x"FF",x"FE", -- 0x05C8 + x"3F",x"37",x"63",x"61",x"61",x"F1",x"F9",x"FF", -- 0x05D0 + x"FC",x"C6",x"87",x"CF",x"FE",x"FC",x"FE",x"FF", -- 0x05D8 + x"00",x"00",x"03",x"0F",x"F2",x"CE",x"3E",x"FF", -- 0x05E0 + x"00",x"03",x"F8",x"C0",x"80",x"C0",x"30",x"08", -- 0x05E8 + x"1F",x"C6",x"F2",x"1D",x"03",x"00",x"00",x"00", -- 0x05F0 + x"CC",x"E0",x"80",x"40",x"98",x"F0",x"00",x"00", -- 0x05F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 + x"3F",x"3F",x"7F",x"0B",x"0B",x"07",x"03",x"02", -- 0x0610 + x"CE",x"FE",x"FE",x"EC",x"74",x"FC",x"FC",x"4C", -- 0x0618 + x"04",x"07",x"1F",x"1F",x"3D",x"7D",x"1F",x"2F", -- 0x0620 + x"04",x"04",x"F8",x"FC",x"F4",x"FC",x"FC",x"FE", -- 0x0628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 + x"2E",x"1F",x"1F",x"1F",x"27",x"42",x"04",x"00", -- 0x0640 + x"7E",x"FE",x"FE",x"BE",x"BD",x"50",x"00",x"00", -- 0x0648 + x"F7",x"EB",x"DD",x"3D",x"FD",x"7F",x"F7",x"2D", -- 0x0650 + x"F7",x"EF",x"DB",x"B7",x"AF",x"BE",x"FE",x"EA", -- 0x0658 + x"7F",x"7F",x"FF",x"7E",x"BD",x"DB",x"FB",x"F7", -- 0x0660 + x"FF",x"FE",x"6F",x"AF",x"D7",x"DD",x"ED",x"F7", -- 0x0668 + x"00",x"00",x"87",x"5F",x"3B",x"7B",x"7F",x"FF", -- 0x0670 + x"00",x"02",x"FC",x"FC",x"D4",x"BE",x"4E",x"CD", -- 0x0678 + x"60",x"74",x"D8",x"CE",x"64",x"68",x"FF",x"10", -- 0x0680 + x"0B",x"37",x"7B",x"BB",x"32",x"F0",x"24",x"02", -- 0x0688 + x"FF",x"BF",x"1F",x"3F",x"2F",x"14",x"00",x"03", -- 0x0690 + x"6F",x"EF",x"F7",x"F7",x"36",x"2E",x"5E",x"85", -- 0x0698 + x"3C",x"23",x"8E",x"CF",x"4F",x"7B",x"3D",x"FE", -- 0x06A0 + x"9E",x"12",x"3B",x"7D",x"9D",x"ED",x"FB",x"F7", -- 0x06A8 + x"00",x"00",x"20",x"6C",x"F8",x"58",x"26",x"16", -- 0x06B0 + x"80",x"80",x"80",x"98",x"8C",x"16",x"1C",x"1E", -- 0x06B8 + x"1C",x"0C",x"00",x"21",x"41",x"08",x"08",x"00", -- 0x06C0 + x"40",x"20",x"60",x"C0",x"80",x"84",x"82",x"00", -- 0x06C8 + x"38",x"3C",x"18",x"00",x"01",x"03",x"08",x"1C", -- 0x06D0 + x"00",x"08",x"0C",x"0E",x"C6",x"C4",x"86",x"42", -- 0x06D8 + x"4E",x"06",x"01",x"01",x"03",x"03",x"01",x"00", -- 0x06E0 + x"20",x"00",x"06",x"0F",x"07",x"03",x"01",x"00", -- 0x06E8 + x"00",x"00",x"10",x"10",x"00",x"00",x"04",x"8E", -- 0x06F0 + x"00",x"00",x"00",x"02",x"24",x"A0",x"60",x"30", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 + x"00",x"01",x"21",x"13",x"0F",x"0F",x"07",x"1F", -- 0x0708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 + x"3F",x"5F",x"17",x"0F",x"07",x"09",x"08",x"00", -- 0x0718 + x"00",x"00",x"04",x"88",x"B0",x"F0",x"F8",x"FE", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 + x"C8",x"F0",x"B8",x"D8",x"E4",x"C0",x"00",x"00", -- 0x0730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 + x"02",x"01",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x0740 + x"00",x"07",x"8F",x"FF",x"3F",x"7C",x"7B",x"73", -- 0x0748 + x"3F",x"0E",x"00",x"00",x"01",x"02",x"00",x"00", -- 0x0750 + x"F7",x"77",x"7B",x"FD",x"1E",x"0F",x"07",x"05", -- 0x0758 + x"00",x"30",x"F8",x"FF",x"FF",x"EF",x"EF",x"F7", -- 0x0760 + x"00",x"00",x"40",x"80",x"00",x"80",x"C0",x"C0", -- 0x0768 + x"F3",x"F7",x"EF",x"FF",x"9C",x"F8",x"E4",x"80", -- 0x0770 + x"B8",x"84",x"00",x"00",x"C0",x"20",x"00",x"00", -- 0x0778 + x"10",x"08",x"00",x"00",x"11",x"1F",x"0F",x"1F", -- 0x0780 + x"0E",x"1E",x"3E",x"BF",x"DF",x"EE",x"FF",x"FF", -- 0x0788 + x"1F",x"07",x"03",x"31",x"00",x"01",x"03",x"00", -- 0x0790 + x"FF",x"CF",x"BF",x"7F",x"FE",x"BF",x"1F",x"07", -- 0x0798 + x"00",x"F8",x"FF",x"FF",x"FF",x"FF",x"F8",x"E7", -- 0x07A0 + x"00",x"10",x"30",x"F0",x"F8",x"FC",x"0C",x"FC", -- 0x07A8 + x"EF",x"FF",x"FF",x"FF",x"EF",x"1C",x"F8",x"80", -- 0x07B0 + x"FC",x"FC",x"F8",x"F0",x"80",x"46",x"22",x"00", -- 0x07B8 + x"00",x"00",x"39",x"31",x"69",x"00",x"00",x"00", -- 0x07C0 + x"00",x"00",x"8F",x"DF",x"C6",x"07",x"01",x"00", -- 0x07C8 + x"0C",x"38",x"00",x"0C",x"1E",x"0C",x"00",x"00", -- 0x07D0 + x"01",x"39",x"38",x"18",x"00",x"00",x"00",x"00", -- 0x07D8 + x"00",x"18",x"1A",x"1A",x"03",x"02",x"44",x"C0", -- 0x07E0 + x"00",x"00",x"00",x"00",x"70",x"60",x"00",x"00", -- 0x07E8 + x"C1",x"01",x"00",x"70",x"70",x"60",x"00",x"00", -- 0x07F0 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0800 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0808 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0810 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0818 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0820 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0828 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0830 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0838 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0840 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0888 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0890 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0898 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x08A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x08A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x08B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x08B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x08C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x08C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x08D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x08D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x08E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x08E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x08F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x08F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0900 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0908 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0910 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0918 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0920 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0928 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0930 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0938 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0940 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0948 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0950 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 + x"00",x"00",x"00",x"01",x"01",x"01",x"1D",x"0F", -- 0x0A20 + x"00",x"40",x"C0",x"C0",x"C0",x"C0",x"C0",x"40", -- 0x0A28 + x"0F",x"1F",x"01",x"01",x"01",x"00",x"00",x"00", -- 0x0A30 + x"40",x"C0",x"C0",x"C0",x"C0",x"C0",x"40",x"00", -- 0x0A38 + x"1D",x"74",x"1F",x"33",x"23",x"03",x"01",x"01", -- 0x0A40 + x"80",x"C0",x"80",x"E0",x"80",x"80",x"C0",x"C0", -- 0x0A48 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 + x"C0",x"C0",x"C0",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 + x"FB",x"4B",x"FD",x"47",x"47",x"67",x"03",x"03", -- 0x0A60 + x"80",x"00",x"80",x"C0",x"00",x"00",x"00",x"00", -- 0x0A68 + x"03",x"03",x"03",x"01",x"01",x"00",x"00",x"00", -- 0x0A70 + x"00",x"00",x"80",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0A78 + x"10",x"AC",x"D6",x"98",x"6F",x"23",x"7B",x"03", -- 0x0A80 + x"C0",x"C0",x"C0",x"C0",x"C0",x"80",x"00",x"00", -- 0x0A88 + x"03",x"03",x"67",x"47",x"47",x"7D",x"CB",x"7B", -- 0x0A90 + x"00",x"00",x"00",x"00",x"C0",x"80",x"D0",x"80", -- 0x0A98 + x"EB",x"BD",x"8F",x"CF",x"1E",x"0E",x"0C",x"0C", -- 0x0AA0 + x"10",x"C0",x"20",x"80",x"40",x"00",x"00",x"00", -- 0x0AA8 + x"1C",x"1C",x"1C",x"1E",x"0E",x"0C",x"0C",x"04", -- 0x0AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 + x"00",x"0C",x"0C",x"1C",x"38",x"78",x"70",x"D0", -- 0x0AC8 + x"00",x"39",x"A3",x"B3",x"5F",x"5C",x"FD",x"5B", -- 0x0AD0 + x"C0",x"C0",x"C0",x"80",x"E0",x"D0",x"E0",x"90", -- 0x0AD8 + x"00",x"00",x"00",x"00",x"01",x"01",x"13",x"1F", -- 0x0AE0 + x"00",x"00",x"00",x"00",x"40",x"40",x"E4",x"FC", -- 0x0AE8 + x"03",x"01",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 + x"E0",x"C0",x"C0",x"80",x"00",x"00",x"00",x"00", -- 0x0AF8 + x"00",x"00",x"00",x"01",x"03",x"1C",x"23",x"C0", -- 0x0B00 + x"00",x"7E",x"FC",x"08",x"F1",x"13",x"FF",x"0F", -- 0x0B08 + x"23",x"1C",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0B10 + x"FF",x"13",x"F1",x"08",x"FC",x"7E",x"00",x"00", -- 0x0B18 + x"1C",x"38",x"C2",x"06",x"C2",x"38",x"1C",x"00", -- 0x0B20 + x"00",x"00",x"00",x"18",x"08",x"1C",x"FE",x"F8", -- 0x0B28 + x"0C",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 + x"FE",x"1C",x"08",x"18",x"00",x"00",x"00",x"00", -- 0x0B38 + x"02",x"07",x"07",x"0F",x"0F",x"0F",x"1F",x"18", -- 0x0B40 + x"00",x"00",x"00",x"80",x"80",x"80",x"C0",x"C0", -- 0x0B48 + x"17",x"37",x"38",x"3F",x"70",x"7F",x"7F",x"00", -- 0x0B50 + x"40",x"60",x"E0",x"E0",x"70",x"F0",x"F0",x"00", -- 0x0B58 + x"02",x"02",x"07",x"07",x"0F",x"0F",x"1F",x"00", -- 0x0B60 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"00", -- 0x0B68 + x"7F",x"00",x"00",x"0F",x"7F",x"48",x"7F",x"00", -- 0x0B70 + x"00",x"03",x"03",x"00",x"00",x"7F",x"41",x"41", -- 0x0B78 + x"00",x"01",x"03",x"07",x"03",x"07",x"0F",x"3F", -- 0x0B80 + x"80",x"80",x"D8",x"F8",x"F8",x"F0",x"F0",x"F0", -- 0x0B88 + x"1F",x"1F",x"1F",x"0F",x"03",x"07",x"07",x"01", -- 0x0B90 + x"F8",x"F8",x"F0",x"E0",x"F8",x"FC",x"78",x"00", -- 0x0B98 + x"00",x"00",x"00",x"00",x"00",x"04",x"01",x"03", -- 0x0BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"90", -- 0x0BA8 + x"07",x"02",x"02",x"08",x"00",x"00",x"00",x"00", -- 0x0BB0 + x"C0",x"80",x"A0",x"10",x"00",x"00",x"00",x"00", -- 0x0BB8 + x"00",x"00",x"00",x"04",x"24",x"04",x"4E",x"27", -- 0x0BC0 + x"00",x"00",x"20",x"40",x"11",x"80",x"A4",x"C8", -- 0x0BC8 + x"07",x"03",x"25",x"00",x"08",x"00",x"00",x"00", -- 0x0BD0 + x"C0",x"20",x"90",x"A0",x"20",x"50",x"00",x"00", -- 0x0BD8 + x"00",x"00",x"42",x"20",x"04",x"0F",x"E7",x"3F", -- 0x0BE0 + x"00",x"20",x"44",x"C8",x"80",x"80",x"D0",x"EC", -- 0x0BE8 + x"07",x"07",x"0D",x"1D",x"29",x"42",x"01",x"00", -- 0x0BF0 + x"C0",x"A0",x"B0",x"88",x"44",x"20",x"10",x"08", -- 0x0BF8 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0C00 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0C08 + x"07",x"00",x"06",x"09",x"09",x"09",x"06",x"00", -- 0x0C10 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"C0",x"00", -- 0x0C18 + x"00",x"07",x"08",x"08",x"07",x"00",x"07",x"08", -- 0x0C20 + x"00",x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20", -- 0x0C28 + x"08",x"07",x"00",x"00",x"0F",x"04",x"00",x"00", -- 0x0C30 + x"20",x"C0",x"00",x"20",x"E0",x"20",x"00",x"00", -- 0x0C38 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0C40 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0C48 + x"07",x"00",x"06",x"09",x"08",x"08",x"04",x"00", -- 0x0C50 + x"C0",x"00",x"20",x"20",x"A0",x"60",x"20",x"00", -- 0x0C58 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0C60 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0C68 + x"07",x"00",x"08",x"0D",x"0B",x"09",x"08",x"00", -- 0x0C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"23", -- 0x0DA0 + x"00",x"00",x"20",x"10",x"18",x"38",x"FC",x"78", -- 0x0DA8 + x"33",x"1F",x"1F",x"0F",x"01",x"00",x"00",x"00", -- 0x0DB0 + x"78",x"D8",x"48",x"20",x"B0",x"10",x"00",x"00", -- 0x0DB8 + x"00",x"00",x"00",x"00",x"00",x"20",x"31",x"1F", -- 0x0DC0 + x"00",x"00",x"00",x"08",x"08",x"1C",x"7C",x"7C", -- 0x0DC8 + x"1F",x"1F",x"06",x"02",x"00",x"00",x"00",x"00", -- 0x0DD0 + x"F8",x"B8",x"90",x"C0",x"40",x"40",x"00",x"00", -- 0x0DD8 + x"00",x"00",x"00",x"00",x"10",x"10",x"19",x"1F", -- 0x0DE0 + x"00",x"00",x"00",x"00",x"04",x"04",x"4C",x"7C", -- 0x0DE8 + x"1F",x"0E",x"06",x"02",x"00",x"00",x"00",x"00", -- 0x0DF0 + x"FC",x"B8",x"B0",x"A0",x"80",x"80",x"00",x"00", -- 0x0DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 + x"3F",x"3F",x"7F",x"0B",x"0B",x"07",x"03",x"02", -- 0x0E10 + x"CE",x"FE",x"FE",x"EC",x"74",x"FC",x"FC",x"4C", -- 0x0E18 + x"04",x"07",x"1F",x"1F",x"3D",x"7D",x"1F",x"2F", -- 0x0E20 + x"04",x"04",x"F8",x"FC",x"F4",x"FC",x"FC",x"FE", -- 0x0E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 + x"2E",x"1F",x"1F",x"1F",x"27",x"42",x"04",x"00", -- 0x0E40 + x"7E",x"FE",x"FE",x"BE",x"BD",x"50",x"00",x"00", -- 0x0E48 + x"F7",x"EB",x"DD",x"3D",x"FD",x"7F",x"F7",x"2D", -- 0x0E50 + x"F7",x"EF",x"DB",x"B7",x"AF",x"BE",x"FE",x"EA", -- 0x0E58 + x"7F",x"7F",x"FF",x"7E",x"BD",x"DB",x"FB",x"F7", -- 0x0E60 + x"FF",x"FE",x"6F",x"AF",x"D7",x"DD",x"ED",x"F7", -- 0x0E68 + x"00",x"00",x"87",x"5F",x"3B",x"7B",x"7F",x"FF", -- 0x0E70 + x"00",x"02",x"FC",x"FC",x"D4",x"BE",x"4E",x"CD", -- 0x0E78 + x"60",x"74",x"D8",x"CE",x"64",x"68",x"FF",x"10", -- 0x0E80 + x"0B",x"37",x"7B",x"BB",x"32",x"F0",x"24",x"02", -- 0x0E88 + x"FF",x"BF",x"1F",x"3F",x"2F",x"14",x"00",x"03", -- 0x0E90 + x"6F",x"EF",x"F7",x"F7",x"36",x"2E",x"5E",x"85", -- 0x0E98 + x"3C",x"23",x"8E",x"CF",x"4F",x"7B",x"3D",x"FE", -- 0x0EA0 + x"9E",x"12",x"3B",x"7D",x"9D",x"ED",x"FB",x"F7", -- 0x0EA8 + x"00",x"00",x"20",x"6C",x"F8",x"58",x"26",x"16", -- 0x0EB0 + x"80",x"80",x"80",x"98",x"8C",x"16",x"1C",x"1E", -- 0x0EB8 + x"1C",x"0C",x"00",x"21",x"41",x"08",x"08",x"00", -- 0x0EC0 + x"40",x"20",x"60",x"C0",x"80",x"84",x"82",x"00", -- 0x0EC8 + x"38",x"3C",x"18",x"00",x"01",x"03",x"08",x"1C", -- 0x0ED0 + x"00",x"08",x"0C",x"0E",x"C6",x"C4",x"86",x"42", -- 0x0ED8 + x"4E",x"06",x"01",x"01",x"03",x"03",x"01",x"00", -- 0x0EE0 + x"20",x"00",x"06",x"0F",x"07",x"03",x"01",x"00", -- 0x0EE8 + x"00",x"00",x"10",x"10",x"00",x"00",x"04",x"8E", -- 0x0EF0 + x"00",x"00",x"00",x"02",x"24",x"A0",x"60",x"30", -- 0x0EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 + x"00",x"01",x"21",x"13",x"0F",x"0F",x"07",x"1F", -- 0x0F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 + x"3F",x"5F",x"17",x"0F",x"07",x"09",x"08",x"00", -- 0x0F18 + x"00",x"00",x"04",x"88",x"B0",x"F0",x"F8",x"FE", -- 0x0F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 + x"C8",x"F0",x"B8",x"D8",x"E4",x"C0",x"00",x"00", -- 0x0F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 + x"02",x"01",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x0F40 + x"00",x"07",x"8F",x"FF",x"3F",x"7C",x"7B",x"73", -- 0x0F48 + x"3F",x"0E",x"00",x"00",x"01",x"02",x"00",x"00", -- 0x0F50 + x"F7",x"77",x"7B",x"FD",x"1E",x"0F",x"07",x"05", -- 0x0F58 + x"00",x"30",x"F8",x"FF",x"FF",x"EF",x"EF",x"F7", -- 0x0F60 + x"00",x"00",x"40",x"80",x"00",x"80",x"C0",x"C0", -- 0x0F68 + x"F3",x"F7",x"EF",x"FF",x"9C",x"F8",x"E4",x"80", -- 0x0F70 + x"B8",x"84",x"00",x"00",x"C0",x"20",x"00",x"00", -- 0x0F78 + x"10",x"08",x"00",x"00",x"11",x"1F",x"0F",x"1F", -- 0x0F80 + x"0E",x"1E",x"3E",x"BF",x"DF",x"EE",x"FF",x"FF", -- 0x0F88 + x"1F",x"07",x"03",x"31",x"00",x"01",x"03",x"00", -- 0x0F90 + x"FF",x"CF",x"BF",x"7F",x"FE",x"BF",x"1F",x"07", -- 0x0F98 + x"00",x"F8",x"FF",x"FF",x"FF",x"FF",x"F8",x"E7", -- 0x0FA0 + x"00",x"10",x"30",x"F0",x"F8",x"FC",x"0C",x"FC", -- 0x0FA8 + x"EF",x"FF",x"FF",x"FF",x"EF",x"1C",x"F8",x"80", -- 0x0FB0 + x"FC",x"FC",x"F8",x"F0",x"80",x"46",x"22",x"00", -- 0x0FB8 + x"00",x"00",x"39",x"31",x"69",x"00",x"00",x"00", -- 0x0FC0 + x"00",x"00",x"8F",x"DF",x"C6",x"07",x"01",x"00", -- 0x0FC8 + x"0C",x"38",x"00",x"0C",x"1E",x"0C",x"00",x"00", -- 0x0FD0 + x"01",x"39",x"38",x"18",x"00",x"00",x"00",x"00", -- 0x0FD8 + x"00",x"18",x"1A",x"1A",x"03",x"02",x"44",x"C0", -- 0x0FE0 + x"00",x"00",x"00",x"00",x"70",x"60",x"00",x"00", -- 0x0FE8 + x"C1",x"01",x"00",x"70",x"70",x"60",x"00",x"00", -- 0x0FF0 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..693ba290 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,541 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1K is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(11 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1K is + + + type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"02",x"3E",x"0F",x"1E",x"0E",x"0C",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"60",x"E0",x"60",x"40", -- 0x0058 + x"0A",x"3F",x"EF",x"C6",x"D2",x"7B",x"7B",x"76", -- 0x0060 + x"00",x"00",x"10",x"28",x"28",x"10",x"00",x"00", -- 0x0068 + x"00",x"03",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0070 + x"00",x"00",x"40",x"E8",x"BC",x"6C",x"68",x"20", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"01",x"00",x"08", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"20", -- 0x0168 + x"02",x"00",x"04",x"01",x"00",x"00",x"00",x"00", -- 0x0170 + x"80",x"00",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"04",x"00",x"00", -- 0x0180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0188 + x"00",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0190 + x"10",x"80",x"00",x"40",x"00",x"00",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"00",x"08",x"20",x"02",x"00", -- 0x01A0 + x"00",x"00",x"00",x"00",x"00",x"40",x"08",x"00", -- 0x01A8 + x"01",x"00",x"10",x"00",x"01",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"A0",x"00",x"00",x"20",x"00",x"00", -- 0x01B8 + x"00",x"00",x"00",x"00",x"10",x"04",x"00",x"11", -- 0x01C0 + x"00",x"00",x"00",x"00",x"80",x"10",x"40",x"00", -- 0x01C8 + x"00",x"02",x"10",x"04",x"00",x"04",x"00",x"00", -- 0x01D0 + x"88",x"20",x"00",x"50",x"00",x"40",x"00",x"00", -- 0x01D8 + x"00",x"03",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x01E0 + x"00",x"00",x"00",x"80",x"00",x"C0",x"00",x"60", -- 0x01E8 + x"00",x"00",x"00",x"00",x"00",x"01",x"00",x"03", -- 0x01F0 + x"00",x"60",x"00",x"C0",x"00",x"80",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"60",x"00",x"60", -- 0x0208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"00",x"60",x"00",x"60",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"02",x"00",x"00",x"08",x"00",x"42",x"00", -- 0x0220 + x"00",x"00",x"00",x"40",x"10",x"01",x"40",x"00", -- 0x0228 + x"00",x"05",x"10",x"00",x"20",x"04",x"00",x"00", -- 0x0230 + x"01",x"00",x"22",x"00",x"08",x"40",x"22",x"00", -- 0x0238 + x"00",x"00",x"20",x"32",x"33",x"07",x"07",x"0F", -- 0x0240 + x"00",x"00",x"00",x"00",x"00",x"90",x"D0",x"C0", -- 0x0248 + x"0F",x"07",x"07",x"33",x"32",x"20",x"00",x"00", -- 0x0250 + x"C0",x"D0",x"90",x"00",x"00",x"00",x"00",x"00", -- 0x0258 + x"00",x"40",x"24",x"12",x"0A",x"25",x"1B",x"07", -- 0x0260 + x"00",x"02",x"24",x"48",x"50",x"A4",x"D8",x"E0", -- 0x0268 + x"07",x"1B",x"25",x"0A",x"12",x"24",x"40",x"00", -- 0x0270 + x"E0",x"D8",x"A4",x"50",x"48",x"24",x"02",x"00", -- 0x0278 + x"00",x"00",x"18",x"0A",x"0B",x"07",x"07",x"0F", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"90",x"D0",x"F0", -- 0x0288 + x"0F",x"07",x"07",x"0B",x"0A",x"18",x"00",x"00", -- 0x0290 + x"F0",x"D0",x"90",x"00",x"00",x"00",x"00",x"00", -- 0x0298 + x"00",x"00",x"00",x"00",x"00",x"06",x"06",x"00", -- 0x02A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 + x"00",x"00",x"00",x"06",x"06",x"00",x"00",x"00", -- 0x02B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 + x"00",x"00",x"00",x"00",x"06",x"06",x"00",x"00", -- 0x02C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 + x"00",x"00",x"06",x"06",x"00",x"00",x"00",x"00", -- 0x02D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 + x"00",x"00",x"00",x"06",x"06",x"00",x"00",x"00", -- 0x02E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"06",x"06",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 + x"00",x"00",x"00",x"00",x"00",x"03",x"1C",x"3F", -- 0x0300 + x"00",x"00",x"78",x"F0",x"E1",x"E1",x"05",x"F5", -- 0x0308 + x"1C",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"05",x"E1",x"E1",x"F0",x"78",x"00",x"00",x"00", -- 0x0318 + x"00",x"18",x"3A",x"FE",x"3A",x"18",x"00",x"00", -- 0x0320 + x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C", -- 0x0328 + x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C", -- 0x0330 + x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C", -- 0x0338 + x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C", -- 0x0340 + x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C",x"3C", -- 0x0348 + x"FF",x"3F",x"0F",x"03",x"00",x"00",x"00",x"00", -- 0x0350 + x"F0",x"00",x"00",x"80",x"60",x"00",x"00",x"00", -- 0x0358 + x"00",x"00",x"00",x"01",x"06",x"FF",x"FF",x"FF", -- 0x0360 + x"00",x"00",x"E0",x"80",x"80",x"00",x"F0",x"F8", -- 0x0368 + x"FF",x"1F",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x0370 + x"F0",x"80",x"C0",x"E0",x"38",x"00",x"00",x"00", -- 0x0378 + x"00",x"00",x"00",x"02",x"05",x"00",x"03",x"0C", -- 0x0380 + x"00",x"00",x"00",x"10",x"50",x"68",x"88",x"C8", -- 0x0388 + x"03",x"0A",x"03",x"01",x"04",x"03",x"00",x"00", -- 0x0390 + x"F4",x"A0",x"C0",x"70",x"40",x"20",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"02",x"0A",x"04",x"00", -- 0x03A0 + x"00",x"00",x"00",x"00",x"50",x"A0",x"00",x"20", -- 0x03A8 + x"00",x"09",x"01",x"02",x"00",x"00",x"00",x"00", -- 0x03B0 + x"38",x"10",x"00",x"40",x"20",x"00",x"00",x"00", -- 0x03B8 + x"00",x"02",x"01",x"01",x"01",x"40",x"13",x"01", -- 0x03C0 + x"00",x"00",x"00",x"04",x"0C",x"18",x"80",x"90", -- 0x03C8 + x"00",x"08",x"00",x"00",x"02",x"04",x"00",x"00", -- 0x03D0 + x"82",x"CC",x"00",x"10",x"98",x"84",x"00",x"00", -- 0x03D8 + x"08",x"04",x"00",x"02",x"8C",x"0E",x"07",x"0F", -- 0x03E0 + x"01",x"12",x"00",x"04",x"00",x"C0",x"C8",x"E0", -- 0x03E8 + x"07",x"03",x"21",x"00",x"80",x"21",x"48",x"81", -- 0x03F0 + x"C2",x"80",x"01",x"00",x"22",x"00",x"02",x"01", -- 0x03F8 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0400 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0408 + x"07",x"00",x"06",x"09",x"09",x"09",x"06",x"00", -- 0x0410 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"C0",x"00", -- 0x0418 + x"00",x"07",x"08",x"08",x"07",x"00",x"07",x"08", -- 0x0420 + x"00",x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20", -- 0x0428 + x"08",x"07",x"00",x"00",x"0F",x"04",x"00",x"00", -- 0x0430 + x"20",x"C0",x"00",x"20",x"E0",x"20",x"00",x"00", -- 0x0438 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0440 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0448 + x"07",x"00",x"06",x"09",x"08",x"08",x"04",x"00", -- 0x0450 + x"C0",x"00",x"20",x"20",x"A0",x"60",x"20",x"00", -- 0x0458 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0460 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0468 + x"07",x"00",x"08",x"0D",x"0B",x"09",x"08",x"00", -- 0x0470 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"20",x"00", -- 0x0478 + x"30",x"34",x"62",x"43",x"81",x"80",x"C0",x"70", -- 0x0480 + x"1E",x"1E",x"9E",x"1E",x"9E",x"8C",x"04",x"00", -- 0x0488 + x"40",x"80",x"00",x"00",x"80",x"E0",x"60",x"70", -- 0x0490 + x"00",x"00",x"00",x"00",x"80",x"C0",x"C4",x"8C", -- 0x0498 + x"38",x"38",x"38",x"34",x"24",x"22",x"42",x"40", -- 0x04A0 + x"03",x"03",x"23",x"01",x"01",x"70",x"18",x"0C", -- 0x04A8 + x"40",x"80",x"00",x"C1",x"C1",x"60",x"60",x"70", -- 0x04B0 + x"10",x"80",x"80",x"C0",x"C8",x"C8",x"C0",x"81", -- 0x04B8 + x"80",x"20",x"E0",x"40",x"60",x"30",x"38",x"28", -- 0x04C0 + x"A0",x"70",x"38",x"18",x"08",x"00",x"00",x"20", -- 0x04C8 + x"41",x"21",x"41",x"38",x"38",x"24",x"64",x"80", -- 0x04D0 + x"00",x"00",x"02",x"02",x"04",x"00",x"40",x"20", -- 0x04D8 + x"F8",x"F8",x"FF",x"FF",x"F8",x"F8",x"F8",x"F8", -- 0x04E0 + x"00",x"00",x"18",x"F8",x"F8",x"18",x"00",x"00", -- 0x04E8 + x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 + x"18",x"F8",x"F8",x"18",x"00",x"00",x"00",x"00", -- 0x04F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"1F", -- 0x0500 + x"00",x"00",x"00",x"00",x"18",x"F8",x"F8",x"18", -- 0x0508 + x"F8",x"F8",x"F8",x"F8",x"FF",x"FF",x"F8",x"F8", -- 0x0510 + x"00",x"00",x"18",x"F8",x"F8",x"18",x"00",x"00", -- 0x0518 + x"F8",x"F8",x"FF",x"FF",x"F8",x"F8",x"1F",x"07", -- 0x0520 + x"00",x"18",x"F8",x"F8",x"18",x"00",x"18",x"F8", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"F8",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"F8", -- 0x0548 + x"07",x"1F",x"F8",x"F8",x"FF",x"FF",x"F8",x"F8", -- 0x0550 + x"F8",x"18",x"00",x"18",x"F8",x"F8",x"18",x"00", -- 0x0558 + x"FF",x"F8",x"F8",x"F8",x"F8",x"1F",x"07",x"00", -- 0x0560 + x"F8",x"18",x"00",x"00",x"00",x"18",x"F8",x"F8", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"18",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"18", -- 0x0588 + x"00",x"07",x"1F",x"F8",x"F8",x"F8",x"F8",x"FF", -- 0x0590 + x"F8",x"F8",x"18",x"00",x"00",x"00",x"18",x"F8", -- 0x0598 + x"F0",x"E0",x"C0",x"40",x"40",x"40",x"01",x"23", -- 0x05A0 + x"1F",x"1E",x"9C",x"FE",x"FF",x"FF",x"FE",x"FC", -- 0x05A8 + x"3F",x"0F",x"0F",x"01",x"00",x"00",x"00",x"00", -- 0x05B0 + x"FE",x"FF",x"FF",x"FE",x"00",x"00",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"01",x"0F",x"0F",x"3F", -- 0x05C0 + x"00",x"00",x"00",x"00",x"FE",x"FF",x"FF",x"FE", -- 0x05C8 + x"23",x"01",x"40",x"40",x"40",x"C0",x"E0",x"F0", -- 0x05D0 + x"FC",x"FE",x"FF",x"FF",x"FE",x"9C",x"1E",x"1F", -- 0x05D8 + x"00",x"00",x"00",x"03",x"0F",x"3F",x"FF",x"FF", -- 0x05E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"F0", -- 0x05E8 + x"FF",x"3F",x"0F",x"03",x"00",x"00",x"00",x"00", -- 0x05F0 + x"F0",x"00",x"00",x"80",x"60",x"00",x"00",x"00", -- 0x05F8 + x"21",x"01",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x0600 + x"12",x"10",x"10",x"00",x"00",x"00",x"00",x"00", -- 0x0608 + x"38",x"04",x"38",x"0B",x"07",x"06",x"09",x"11", -- 0x0610 + x"36",x"26",x"56",x"90",x"F8",x"AC",x"B4",x"20", -- 0x0618 + x"00",x"05",x"0D",x"17",x"3A",x"16",x"28",x"34", -- 0x0620 + x"40",x"88",x"D0",x"DE",x"5A",x"B0",x"24",x"0E", -- 0x0628 + x"00",x"00",x"00",x"00",x"00",x"00",x"10",x"08", -- 0x0630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"22", -- 0x0638 + x"1D",x"2E",x"46",x"8D",x"05",x"00",x"08",x"18", -- 0x0640 + x"AD",x"76",x"FA",x"E8",x"DA",x"33",x"01",x"00", -- 0x0648 + x"78",x"7C",x"BE",x"DE",x"DF",x"A3",x"7B",x"3B", -- 0x0650 + x"0E",x"1D",x"3D",x"7B",x"F7",x"CE",x"DC",x"DC", -- 0x0658 + x"3B",x"57",x"6F",x"57",x"DA",x"BC",x"3C",x"78", -- 0x0660 + x"DD",x"ED",x"F7",x"77",x"39",x"3E",x"1E",x"0E", -- 0x0668 + x"00",x"00",x"06",x"1D",x"0F",x"5F",x"2F",x"74", -- 0x0670 + x"00",x"00",x"7A",x"B4",x"EC",x"CE",x"B6",x"3F", -- 0x0678 + x"20",x"5C",x"EF",x"F2",x"5C",x"17",x"78",x"10", -- 0x0680 + x"0F",x"BB",x"34",x"77",x"76",x"6C",x"18",x"04", -- 0x0688 + x"FF",x"F7",x"6D",x"5D",x"4D",x"64",x"2D",x"02", -- 0x0690 + x"B7",x"F7",x"FB",x"FB",x"FB",x"77",x"8F",x"07", -- 0x0698 + x"3C",x"E0",x"E2",x"CF",x"4F",x"1F",x"3E",x"FF", -- 0x06A0 + x"1A",x"0E",x"37",x"7B",x"FB",x"FB",x"FF",x"7F", -- 0x06A8 + x"00",x"20",x"30",x"71",x"61",x"25",x"19",x"2E", -- 0x06B0 + x"00",x"40",x"42",x"4C",x"54",x"DA",x"3E",x"1D", -- 0x06B8 + x"1C",x"0E",x"00",x"00",x"01",x"00",x"00",x"00", -- 0x06C0 + x"00",x"20",x"60",x"C0",x"80",x"80",x"80",x"00", -- 0x06C8 + x"18",x"3C",x"18",x"01",x"22",x"41",x"08",x"1C", -- 0x06D0 + x"20",x"18",x"98",x"0E",x"C6",x"C4",x"86",x"22", -- 0x06D8 + x"0E",x"04",x"00",x"01",x"03",x"03",x"01",x"00", -- 0x06E0 + x"00",x"04",x"0E",x"0F",x"87",x"81",x"01",x"00", -- 0x06E8 + x"00",x"00",x"00",x"00",x"00",x"10",x"0C",x"0E", -- 0x06F0 + x"00",x"00",x"00",x"00",x"20",x"20",x"60",x"10", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 + x"00",x"00",x"00",x"02",x"06",x"6F",x"1E",x"1C", -- 0x0708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 + x"04",x"1E",x"1E",x"1D",x"03",x"01",x"00",x"00", -- 0x0718 + x"00",x"00",x"20",x"C0",x"E0",x"D0",x"78",x"30", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 + x"38",x"7C",x"E8",x"70",x"60",x"80",x"00",x"00", -- 0x0730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 + x"00",x"00",x"10",x"10",x"10",x"0E",x"01",x"00", -- 0x0740 + x"00",x"06",x"0E",x"3F",x"17",x"7B",x"FC",x"FC", -- 0x0748 + x"00",x"01",x"06",x"08",x"10",x"00",x"00",x"00", -- 0x0750 + x"68",x"48",x"1C",x"3E",x"17",x"0B",x"03",x"01", -- 0x0758 + x"00",x"38",x"FF",x"7F",x"7E",x"19",x"13",x"0F", -- 0x0760 + x"00",x"00",x"00",x"04",x"08",x"98",x"C0",x"C0", -- 0x0768 + x"0F",x"0B",x"1D",x"0E",x"6C",x"B0",x"E0",x"80", -- 0x0770 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"1F", -- 0x0778 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"1F", -- 0x0780 + x"0F",x"1F",x"BF",x"FC",x"F8",x"FB",x"7F",x"FE", -- 0x0788 + x"1F",x"01",x"03",x"05",x"08",x"10",x"00",x"00", -- 0x0790 + x"FE",x"FB",x"CD",x"9E",x"3F",x"3B",x"17",x"07", -- 0x0798 + x"00",x"F8",x"FF",x"7F",x"7C",x"8F",x"CF",x"7F", -- 0x07A0 + x"00",x"00",x"00",x"90",x"78",x"FC",x"FC",x"FC", -- 0x07A8 + x"7F",x"FE",x"F5",x"26",x"1F",x"FC",x"F8",x"80", -- 0x07B0 + x"FC",x"3C",x"18",x"E0",x"40",x"00",x"00",x"00", -- 0x07B8 + x"00",x"00",x"38",x"30",x"78",x"38",x"00",x"00", -- 0x07C0 + x"00",x"00",x"00",x"CF",x"C6",x"07",x"00",x"00", -- 0x07C8 + x"00",x"00",x"00",x"0C",x"1E",x"1E",x"0C",x"00", -- 0x07D0 + x"00",x"38",x"78",x"38",x"10",x"00",x"00",x"00", -- 0x07D8 + x"00",x"18",x"18",x"18",x"00",x"00",x"00",x"80", -- 0x07E0 + x"00",x"00",x"00",x"00",x"78",x"70",x"20",x"00", -- 0x07E8 + x"C1",x"01",x"71",x"78",x"70",x"60",x"00",x"00", -- 0x07F0 + x"80",x"C0",x"80",x"00",x"30",x"20",x"10",x"00", -- 0x07F8 + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0800 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0808 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0810 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0818 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0820 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0828 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0830 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0838 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0840 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0848 + x"07",x"07",x"0E",x"1E",x"3C",x"F8",x"F0",x"E0", -- 0x0850 + x"06",x"07",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0858 + x"C0",x"E0",x"F0",x"F8",x"FC",x"3C",x"1E",x"0E", -- 0x0860 + x"07",x"C7",x"FF",x"FF",x"FE",x"7C",x"00",x"80", -- 0x0868 + x"FE",x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07", -- 0x0870 + x"FE",x"FE",x"FE",x"1F",x"00",x"00",x"04",x"06", -- 0x0878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0888 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0890 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0898 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x08A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x08A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x08B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x08B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x08C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x08C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x08D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x08D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x08E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x08E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x08F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x08F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0900 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0908 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0910 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0918 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0920 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0928 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0930 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0938 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0940 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0948 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0950 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0958 + x"3C",x"0E",x"06",x"06",x"07",x"03",x"03",x"06", -- 0x0960 + x"F0",x"00",x"00",x"00",x"C0",x"E0",x"F0",x"F8", -- 0x0968 + x"03",x"03",x"03",x"03",x"07",x"FF",x"FE",x"FC", -- 0x0970 + x"07",x"03",x"33",x"38",x"1C",x"0C",x"06",x"03", -- 0x0978 + x"00",x"03",x"C3",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0980 + x"07",x"07",x"07",x"FE",x"FE",x"FC",x"F8",x"F0", -- 0x0988 + x"20",x"30",x"38",x"1C",x"0C",x"06",x"06",x"07", -- 0x0990 + x"03",x"FF",x"FF",x"FE",x"FC",x"F8",x"00",x"00", -- 0x0998 + x"30",x"38",x"0C",x"06",x"07",x"03",x"03",x"03", -- 0x09A0 + x"83",x"FF",x"FF",x"FF",x"7E",x"00",x"00",x"00", -- 0x09A8 + x"FF",x"1F",x"07",x"03",x"01",x"00",x"02",x"03", -- 0x09B0 + x"00",x"00",x"00",x"01",x"83",x"FF",x"FF",x"FF", -- 0x09B8 + x"03",x"07",x"FF",x"FF",x"FE",x"FC",x"F8",x"00", -- 0x09C0 + x"F8",x"FC",x"7E",x"0E",x"07",x"07",x"03",x"03", -- 0x09C8 + x"00",x"00",x"00",x"00",x"00",x"80",x"C0",x"F0", -- 0x09D0 + x"7C",x"7C",x"7C",x"7C",x"7F",x"3F",x"1F",x"0F", -- 0x09D8 + x"80",x"00",x"00",x"00",x"00",x"3C",x"3C",x"7C", -- 0x09E0 + x"7F",x"FF",x"FF",x"FF",x"FF",x"F0",x"E0",x"C0", -- 0x09E8 + x"F8",x"FF",x"FF",x"FF",x"77",x"40",x"00",x"0E", -- 0x09F0 + x"FF",x"FF",x"FF",x"61",x"40",x"00",x"00",x"00", -- 0x09F8 + x"FF",x"1F",x"01",x"00",x"00",x"80",x"F8",x"FF", -- 0x0A00 + x"80",x"80",x"80",x"80",x"C0",x"E0",x"FC",x"FF", -- 0x0A08 + x"01",x"00",x"3C",x"7F",x"FF",x"FF",x"FF",x"80", -- 0x0A10 + x"9C",x"9C",x"FC",x"FC",x"FF",x"3F",x"1F",x"07", -- 0x0A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"1E",x"08", -- 0x0A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0A28 + x"08",x"11",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 + x"02",x"6B",x"00",x"30",x"20",x"00",x"00",x"00", -- 0x0A40 + x"00",x"40",x"00",x"60",x"80",x"80",x"40",x"40", -- 0x0A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 + x"C4",x"34",x"C2",x"40",x"40",x"60",x"00",x"00", -- 0x0A60 + x"00",x"DE",x"00",x"C0",x"00",x"00",x"00",x"00", -- 0x0A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 + x"00",x"10",x"18",x"7E",x"1E",x"1C",x"00",x"00", -- 0x0A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 + x"00",x"00",x"60",x"40",x"40",x"42",x"B4",x"44", -- 0x0A90 + x"00",x"00",x"00",x"00",x"C0",x"00",x"E0",x"00", -- 0x0A98 + x"94",x"82",x"80",x"C0",x"00",x"00",x"00",x"00", -- 0x0AA0 + x"80",x"40",x"20",x"80",x"40",x"00",x"00",x"00", -- 0x0AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 + x"00",x"38",x"A0",x"A0",x"60",x"13",x"C2",x"24", -- 0x0AD0 + x"00",x"00",x"00",x"00",x"60",x"50",x"20",x"10", -- 0x0AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"40", -- 0x0AE8 + x"00",x"0E",x"1C",x"18",x"00",x"00",x"00",x"00", -- 0x0AF0 + x"00",x"38",x"1C",x"0C",x"00",x"00",x"00",x"00", -- 0x0AF8 + x"00",x"00",x"00",x"00",x"00",x"03",x"1C",x"3F", -- 0x0B00 + x"00",x"00",x"78",x"F0",x"E1",x"E1",x"05",x"F5", -- 0x0B08 + x"1C",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 + x"05",x"E1",x"E1",x"F0",x"78",x"00",x"00",x"00", -- 0x0B18 + x"00",x"18",x"3A",x"FE",x"3A",x"18",x"00",x"00", -- 0x0B20 + x"00",x"00",x"7E",x"3C",x"08",x"1C",x"FE",x"00", -- 0x0B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 + x"FE",x"1C",x"08",x"3C",x"7E",x"00",x"00",x"00", -- 0x0B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"07", -- 0x0B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 + x"08",x"08",x"07",x"00",x"0F",x"00",x"00",x"7F", -- 0x0B50 + x"80",x"80",x"00",x"00",x"80",x"00",x"00",x"FF", -- 0x0B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"1F", -- 0x0B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B68 + x"7F",x"00",x"00",x"0F",x"7F",x"48",x"7F",x"00", -- 0x0B70 + x"00",x"03",x"03",x"00",x"00",x"7F",x"41",x"41", -- 0x0B78 + x"00",x"00",x"00",x"02",x"05",x"00",x"03",x"0C", -- 0x0B80 + x"00",x"00",x"00",x"10",x"50",x"68",x"88",x"C8", -- 0x0B88 + x"03",x"0A",x"03",x"01",x"04",x"03",x"00",x"00", -- 0x0B90 + x"F4",x"A0",x"C0",x"70",x"40",x"20",x"00",x"00", -- 0x0B98 + x"00",x"00",x"00",x"00",x"02",x"0A",x"04",x"00", -- 0x0BA0 + x"00",x"00",x"00",x"00",x"50",x"A0",x"00",x"20", -- 0x0BA8 + x"00",x"09",x"01",x"02",x"00",x"00",x"00",x"00", -- 0x0BB0 + x"38",x"10",x"00",x"40",x"20",x"00",x"00",x"00", -- 0x0BB8 + x"00",x"02",x"01",x"01",x"01",x"40",x"13",x"01", -- 0x0BC0 + x"00",x"00",x"00",x"04",x"0C",x"18",x"80",x"90", -- 0x0BC8 + x"00",x"08",x"00",x"00",x"02",x"04",x"00",x"00", -- 0x0BD0 + x"82",x"CC",x"00",x"10",x"98",x"84",x"00",x"00", -- 0x0BD8 + x"08",x"04",x"00",x"02",x"8C",x"0E",x"07",x"0F", -- 0x0BE0 + x"01",x"12",x"00",x"04",x"00",x"C0",x"C8",x"E0", -- 0x0BE8 + x"07",x"03",x"21",x"00",x"80",x"21",x"48",x"81", -- 0x0BF0 + x"C2",x"80",x"01",x"00",x"22",x"00",x"02",x"01", -- 0x0BF8 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0C00 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0C08 + x"07",x"00",x"06",x"09",x"09",x"09",x"06",x"00", -- 0x0C10 + x"C0",x"00",x"C0",x"20",x"20",x"20",x"C0",x"00", -- 0x0C18 + x"00",x"07",x"08",x"08",x"07",x"00",x"07",x"08", -- 0x0C20 + x"00",x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20", -- 0x0C28 + x"08",x"07",x"00",x"00",x"0F",x"04",x"00",x"00", -- 0x0C30 + x"20",x"C0",x"00",x"20",x"E0",x"20",x"00",x"00", -- 0x0C38 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0C40 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0C48 + x"07",x"00",x"06",x"09",x"08",x"08",x"04",x"00", -- 0x0C50 + x"C0",x"00",x"20",x"20",x"A0",x"60",x"20",x"00", -- 0x0C58 + x"07",x"08",x"08",x"07",x"00",x"07",x"08",x"08", -- 0x0C60 + x"C0",x"20",x"20",x"C0",x"00",x"C0",x"20",x"20", -- 0x0C68 + x"07",x"00",x"08",x"0D",x"0B",x"09",x"08",x"00", -- 0x0C70 + x"1C",x"7C",x"FC",x"FC",x"FC",x"DC",x"9C",x"9C", -- 0x0C78 + x"C0",x"FC",x"FF",x"FF",x"3F",x"03",x"00",x"00", -- 0x0C80 + x"FC",x"FC",x"7F",x"3F",x"1F",x"0F",x"03",x"00", -- 0x0C88 + x"FC",x"FC",x"FC",x"FC",x"9C",x"9C",x"9C",x"9C", -- 0x0C90 + x"F8",x"7F",x"3F",x"1F",x"07",x"01",x"3C",x"7C", -- 0x0C98 + x"F0",x"F0",x"F0",x"80",x"80",x"80",x"80",x"C0", -- 0x0CA0 + x"FF",x"FF",x"FF",x"87",x"00",x"00",x"00",x"E0", -- 0x0CA8 + x"C3",x"40",x"00",x"80",x"80",x"80",x"C0",x"F8", -- 0x0CB0 + x"80",x"C0",x"E0",x"F8",x"FF",x"FF",x"FF",x"FF", -- 0x0CB8 + x"E0",x"F8",x"FF",x"7F",x"3F",x"0F",x"03",x"00", -- 0x0CC0 + x"FF",x"FF",x"C0",x"80",x"80",x"80",x"80",x"C0", -- 0x0CC8 + x"00",x"00",x"00",x"00",x"00",x"3F",x"7F",x"FF", -- 0x0CD0 + x"E0",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 + x"0F",x"1F",x"3E",x"FE",x"FC",x"F8",x"F8",x"F0", -- 0x0CE0 + x"00",x"00",x"00",x"01",x"01",x"03",x"03",x"07", -- 0x0CE8 + x"01",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CF0 + x"41",x"40",x"00",x"00",x"00",x"01",x"01",x"01", -- 0x0CF8 + x"01",x"01",x"01",x"C1",x"F9",x"FF",x"FF",x"FF", -- 0x0D00 + x"00",x"00",x"00",x"00",x"00",x"01",x"01",x"01", -- 0x0D08 + x"01",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 + x"00",x"00",x"00",x"01",x"01",x"01",x"01",x"01", -- 0x0D18 + x"FF",x"FF",x"FF",x"C3",x"C0",x"00",x"00",x"00", -- 0x0D20 + x"01",x"00",x"00",x"00",x"00",x"00",x"C0",x"FC", -- 0x0D28 + x"00",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0D30 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"00", -- 0x0D38 + x"07",x"03",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 + x"00",x"00",x"00",x"01",x"01",x"61",x"7F",x"1F", -- 0x0D48 + x"01",x"00",x"00",x"03",x"01",x"01",x"00",x"00", -- 0x0D50 + x"39",x"38",x"18",x"18",x"0C",x"0C",x"06",x"03", -- 0x0D58 + x"01",x"01",x"01",x"01",x"01",x"19",x"39",x"39", -- 0x0D60 + x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 + x"E0",x"E0",x"E0",x"F0",x"7F",x"7F",x"3F",x"3F", -- 0x0D70 + x"7F",x"7E",x"7C",x"F8",x"F0",x"E0",x"E0",x"E0", -- 0x0D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"3F", -- 0x0D80 + x"00",x"00",x"03",x"03",x"01",x"01",x"01",x"00", -- 0x0D88 + x"03",x"03",x"01",x"01",x"00",x"00",x"00",x"00", -- 0x0D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"03", -- 0x0D98 + x"00",x"00",x"00",x"00",x"03",x"03",x"07",x"07", -- 0x0DA0 + x"00",x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0", -- 0x0DA8 + x"07",x"0F",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 + x"F0",x"D0",x"40",x"20",x"30",x"10",x"00",x"00", -- 0x0DB8 + x"00",x"00",x"00",x"01",x"03",x"03",x"07",x"0F", -- 0x0DC0 + x"00",x"00",x"00",x"00",x"C0",x"F0",x"F8",x"F0", -- 0x0DC8 + x"0F",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 + x"F0",x"B0",x"90",x"C0",x"40",x"40",x"00",x"00", -- 0x0DD8 + x"00",x"00",x"00",x"00",x"01",x"03",x"0F",x"0F", -- 0x0DE0 + x"00",x"00",x"00",x"80",x"C0",x"E0",x"F8",x"F8", -- 0x0DE8 + x"07",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 + x"F0",x"A0",x"80",x"80",x"80",x"80",x"00",x"00", -- 0x0DF8 + x"21",x"01",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 + x"12",x"10",x"10",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 + x"38",x"04",x"38",x"0B",x"07",x"06",x"09",x"11", -- 0x0E10 + x"36",x"26",x"56",x"90",x"F8",x"AC",x"B4",x"20", -- 0x0E18 + x"00",x"05",x"0D",x"17",x"3A",x"16",x"28",x"34", -- 0x0E20 + x"40",x"88",x"D0",x"DE",x"5A",x"B0",x"24",x"0E", -- 0x0E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"10",x"08", -- 0x0E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"22", -- 0x0E38 + x"1D",x"2E",x"46",x"8D",x"05",x"00",x"08",x"18", -- 0x0E40 + x"AD",x"76",x"FA",x"E8",x"DA",x"33",x"01",x"00", -- 0x0E48 + x"78",x"7C",x"BE",x"DE",x"DF",x"A3",x"7B",x"3B", -- 0x0E50 + x"0E",x"1D",x"3D",x"7B",x"F7",x"CE",x"DC",x"DC", -- 0x0E58 + x"3B",x"57",x"6F",x"57",x"DA",x"BC",x"3C",x"78", -- 0x0E60 + x"DD",x"ED",x"F7",x"77",x"39",x"3E",x"1E",x"0E", -- 0x0E68 + x"00",x"00",x"06",x"1D",x"0F",x"5F",x"2F",x"74", -- 0x0E70 + x"00",x"00",x"7A",x"B4",x"EC",x"CE",x"B6",x"3F", -- 0x0E78 + x"20",x"5C",x"EF",x"F2",x"5C",x"17",x"78",x"10", -- 0x0E80 + x"0F",x"BB",x"34",x"77",x"76",x"6C",x"18",x"04", -- 0x0E88 + x"FF",x"F7",x"6D",x"5D",x"4D",x"64",x"2D",x"02", -- 0x0E90 + x"B7",x"F7",x"FB",x"FB",x"FB",x"77",x"8F",x"07", -- 0x0E98 + x"3C",x"E0",x"E2",x"CF",x"4F",x"1F",x"3E",x"FF", -- 0x0EA0 + x"1A",x"0E",x"37",x"7B",x"FB",x"FB",x"FF",x"7F", -- 0x0EA8 + x"00",x"20",x"30",x"71",x"61",x"25",x"19",x"2E", -- 0x0EB0 + x"00",x"40",x"42",x"4C",x"54",x"DA",x"3E",x"1D", -- 0x0EB8 + x"1C",x"0E",x"00",x"00",x"01",x"00",x"00",x"00", -- 0x0EC0 + x"00",x"20",x"60",x"C0",x"80",x"80",x"80",x"00", -- 0x0EC8 + x"18",x"3C",x"18",x"01",x"22",x"41",x"08",x"1C", -- 0x0ED0 + x"20",x"18",x"98",x"0E",x"C6",x"C4",x"86",x"22", -- 0x0ED8 + x"0E",x"04",x"00",x"01",x"03",x"03",x"01",x"00", -- 0x0EE0 + x"00",x"04",x"0E",x"0F",x"87",x"81",x"01",x"00", -- 0x0EE8 + x"00",x"00",x"00",x"00",x"00",x"10",x"0C",x"0E", -- 0x0EF0 + x"00",x"00",x"00",x"00",x"20",x"20",x"60",x"10", -- 0x0EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 + x"00",x"00",x"00",x"02",x"06",x"6F",x"1E",x"1C", -- 0x0F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 + x"04",x"1E",x"1E",x"1D",x"03",x"01",x"00",x"00", -- 0x0F18 + x"00",x"00",x"20",x"C0",x"E0",x"D0",x"78",x"30", -- 0x0F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 + x"38",x"7C",x"E8",x"70",x"60",x"80",x"00",x"00", -- 0x0F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 + x"00",x"00",x"10",x"10",x"10",x"0E",x"01",x"00", -- 0x0F40 + x"00",x"06",x"0E",x"3F",x"17",x"7B",x"FC",x"FC", -- 0x0F48 + x"00",x"01",x"06",x"08",x"10",x"00",x"00",x"00", -- 0x0F50 + x"68",x"48",x"1C",x"3E",x"17",x"0B",x"03",x"01", -- 0x0F58 + x"00",x"38",x"FF",x"7F",x"7E",x"19",x"13",x"0F", -- 0x0F60 + x"00",x"00",x"00",x"04",x"08",x"98",x"C0",x"C0", -- 0x0F68 + x"0F",x"0B",x"1D",x"0E",x"6C",x"B0",x"E0",x"80", -- 0x0F70 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"1F", -- 0x0F78 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"1F", -- 0x0F80 + x"0F",x"1F",x"BF",x"FC",x"F8",x"FB",x"7F",x"FE", -- 0x0F88 + x"1F",x"01",x"03",x"05",x"08",x"10",x"00",x"00", -- 0x0F90 + x"FE",x"FB",x"CD",x"9E",x"3F",x"3B",x"17",x"07", -- 0x0F98 + x"00",x"F8",x"FF",x"7F",x"7C",x"8F",x"CF",x"7F", -- 0x0FA0 + x"00",x"00",x"00",x"90",x"78",x"FC",x"FC",x"FC", -- 0x0FA8 + x"7F",x"FE",x"F5",x"26",x"1F",x"FC",x"F8",x"80", -- 0x0FB0 + x"FC",x"3C",x"18",x"E0",x"40",x"00",x"00",x"00", -- 0x0FB8 + x"00",x"00",x"38",x"30",x"78",x"38",x"00",x"00", -- 0x0FC0 + x"00",x"00",x"00",x"CF",x"C6",x"07",x"00",x"00", -- 0x0FC8 + x"00",x"00",x"00",x"0C",x"1E",x"1E",x"0C",x"00", -- 0x0FD0 + x"00",x"38",x"78",x"38",x"10",x"00",x"00",x"00", -- 0x0FD8 + x"00",x"18",x"18",x"18",x"00",x"00",x"00",x"80", -- 0x0FE0 + x"00",x"00",x"00",x"00",x"78",x"70",x"20",x"00", -- 0x0FE8 + x"C1",x"01",x"71",x"78",x"70",x"60",x"00",x"00", -- 0x0FF0 + x"80",x"C0",x"80",x"00",x"30",x"20",x"10",x"00" -- 0x0FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd new file mode 100644 index 00000000..222709ac --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd @@ -0,0 +1,33 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_6L is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(4 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_6L is + + + type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"33",x"C3",x"F6",x"00",x"17",x"C0",x"3F", -- 0x0000 + x"00",x"D8",x"07",x"3F",x"00",x"C0",x"C4",x"07", -- 0x0008 + x"00",x"C0",x"B0",x"1F",x"00",x"1E",x"71",x"07", -- 0x0010 + x"00",x"F6",x"07",x"F0",x"00",x"76",x"07",x"C6" -- 0x0018 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", + X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", + X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", + X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", + X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", + X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", + X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", + X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", + X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", + X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", + X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", + X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", + X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", + X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", + X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", + X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", + X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", + X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", + X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", + X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", + X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", + X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", + X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", + X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", + X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", + X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", + X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", + X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44", + X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1", + X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37", + X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0", + 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+port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A", + X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88", + X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88", + X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC", + 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X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D", + X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78", + X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80", + X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78", + X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..f49d198b --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,2077 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ROM_PGM_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM_0 is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"AF",x"32",x"01",x"70",x"31",x"FF",x"43",x"C3", -- 0x0000 + x"72",x"02",x"F5",x"DD",x"E5",x"FD",x"E5",x"C5", -- 0x0008 + x"D5",x"E5",x"AF",x"32",x"01",x"70",x"3A",x"00", -- 0x0010 + x"78",x"21",x"6A",x"41",x"11",x"00",x"58",x"01", -- 0x0018 + x"80",x"00",x"ED",x"B0",x"2A",x"14",x"41",x"2B", -- 0x0020 + x"22",x"14",x"41",x"2A",x"32",x"41",x"2B",x"C2", -- 0x0028 + x"9B",x"00",x"3A",x"31",x"41",x"2F",x"21",x"FF", -- 0x0030 + x"FF",x"0F",x"CB",x"1C",x"0F",x"CB",x"1C",x"22", -- 0x0038 + x"32",x"41",x"CD",x"03",x"01",x"CD",x"58",x"01", -- 0x0040 + x"CD",x"C1",x"01",x"3A",x"00",x"40",x"FE",x"06", -- 0x0048 + x"D2",x"DB",x"00",x"3A",x"08",x"40",x"A7",x"CA", -- 0x0050 + x"DB",x"00",x"CD",x"00",x"00",x"CD",x"00",x"00", -- 0x0058 + x"AF",x"32",x"06",x"70",x"32",x"07",x"F5",x"DD", -- 0x0060 + x"E5",x"FD",x"E5",x"C5",x"D5",x"E5",x"AF",x"32", -- 0x0068 + x"01",x"70",x"3A",x"00",x"78",x"21",x"6A",x"41", -- 0x0070 + x"11",x"00",x"58",x"01",x"80",x"00",x"ED",x"B0", -- 0x0078 + x"2A",x"14",x"41",x"2B",x"22",x"14",x"41",x"2A", -- 0x0080 + x"32",x"41",x"2B",x"C2",x"9B",x"00",x"3A",x"31", -- 0x0088 + x"41",x"2F",x"21",x"FF",x"FF",x"0F",x"CB",x"1C", -- 0x0090 + x"0F",x"CB",x"1C",x"22",x"32",x"41",x"CD",x"03", -- 0x0098 + x"01",x"CD",x"58",x"01",x"CD",x"C1",x"01",x"3A", -- 0x00A0 + x"00",x"40",x"FE",x"06",x"D2",x"DB",x"00",x"3A", -- 0x00A8 + x"08",x"40",x"A7",x"CA",x"DB",x"00",x"CD",x"FC", -- 0x00B0 + x"26",x"CD",x"B1",x"26",x"AF",x"32",x"06",x"70", -- 0x00B8 + x"32",x"07",x"70",x"21",x"EF",x"52",x"11",x"5F", -- 0x00C0 + x"02",x"CD",x"E7",x"26",x"3E",x"04",x"32",x"A9", -- 0x00C8 + x"41",x"3E",x"01",x"32",x"8E",x"40",x"3E",x"06", -- 0x00D0 + x"32",x"00",x"40",x"21",x"F5",x"00",x"E5",x"21", -- 0x00D8 + x"85",x"28",x"ED",x"4B",x"06",x"41",x"09",x"5E", -- 0x00E0 + x"23",x"56",x"EB",x"ED",x"4B",x"00",x"40",x"09", -- 0x00E8 + x"5E",x"23",x"56",x"EB",x"E9",x"E1",x"D1",x"C1", -- 0x00F0 + x"FD",x"E1",x"DD",x"E1",x"3E",x"01",x"32",x"01", -- 0x00F8 + x"70",x"F1",x"C9",x"3A",x"00",x"68",x"4F",x"32", -- 0x0100 + x"04",x"40",x"3A",x"00",x"60",x"47",x"32",x"06", -- 0x0108 + x"40",x"3A",x"00",x"40",x"FE",x"04",x"C2",x"43", -- 0x0110 + x"01",x"3A",x"05",x"40",x"47",x"21",x"9B",x"40", -- 0x0118 + x"35",x"C2",x"39",x"01",x"CD",x"09",x"28",x"E6", -- 0x0120 + x"1F",x"3C",x"32",x"9B",x"40",x"CD",x"09",x"28", -- 0x0128 + x"E6",x"01",x"06",x"04",x"CA",x"39",x"01",x"06", -- 0x0130 + x"08",x"CD",x"09",x"28",x"E6",x"10",x"B0",x"32", -- 0x0138 + x"05",x"40",x"C9",x"3A",x"00",x"68",x"CB",x"7F", -- 0x0140 + x"CA",x"53",x"01",x"3A",x"00",x"40",x"FE",x"18", -- 0x0148 + x"79",x"28",x"01",x"78",x"32",x"05",x"40",x"C9", -- 0x0150 + x"21",x"07",x"40",x"D9",x"11",x"09",x"40",x"21", -- 0x0158 + x"06",x"40",x"CB",x"4E",x"EB",x"CA",x"6C",x"01", -- 0x0160 + x"34",x"C3",x"7D",x"01",x"7E",x"36",x"00",x"FE", -- 0x0168 + x"02",x"DA",x"7D",x"01",x"D9",x"3E",x"01",x"86", -- 0x0170 + x"77",x"D9",x"CD",x"B6",x"01",x"23",x"EB",x"CB", -- 0x0178 + x"46",x"EB",x"CA",x"89",x"01",x"34",x"C3",x"99", -- 0x0180 + x"01",x"7E",x"36",x"00",x"FE",x"02",x"DA",x"99", -- 0x0188 + x"01",x"D9",x"3E",x"06",x"86",x"77",x"CD",x"B6", -- 0x0190 + x"01",x"11",x"08",x"40",x"1A",x"FE",x"99",x"C8", -- 0x0198 + x"21",x"07",x"40",x"3A",x"0B",x"40",x"BE",x"D0", -- 0x01A0 + x"2F",x"86",x"77",x"EB",x"3E",x"01",x"86",x"27", -- 0x01A8 + x"D8",x"77",x"EB",x"C3",x"A3",x"01",x"D5",x"E5", -- 0x01B0 + x"11",x"03",x"2A",x"CD",x"1F",x"27",x"E1",x"D1", -- 0x01B8 + x"C9",x"21",x"02",x"40",x"35",x"C0",x"2A",x"0C", -- 0x01C0 + x"40",x"7C",x"B5",x"C8",x"3A",x"00",x"40",x"FE", -- 0x01C8 + x"04",x"CA",x"07",x"02",x"7E",x"E6",x"3F",x"3C", -- 0x01D0 + x"32",x"02",x"40",x"7E",x"07",x"32",x"06",x"68", -- 0x01D8 + x"07",x"32",x"07",x"68",x"23",x"7E",x"FE",x"FE", -- 0x01E0 + x"CA",x"07",x"02",x"FE",x"FD",x"CA",x"17",x"02", -- 0x01E8 + x"FE",x"FC",x"CA",x"26",x"02",x"FE",x"FB",x"CA", -- 0x01F0 + x"3B",x"02",x"FE",x"FA",x"CA",x"4A",x"02",x"32", -- 0x01F8 + x"00",x"78",x"23",x"22",x"0C",x"40",x"C9",x"CD", -- 0x0200 + x"12",x"27",x"2A",x"0E",x"40",x"22",x"0C",x"40", -- 0x0208 + x"21",x"00",x"00",x"22",x"0E",x"40",x"C9",x"23", -- 0x0210 + x"7E",x"32",x"1B",x"40",x"23",x"7E",x"32",x"1C", -- 0x0218 + x"40",x"23",x"22",x"0C",x"40",x"C9",x"23",x"3A", -- 0x0220 + x"1B",x"40",x"86",x"32",x"00",x"78",x"32",x"1B", -- 0x0228 + x"40",x"23",x"BE",x"C2",x"50",x"02",x"23",x"22", -- 0x0230 + x"0C",x"40",x"C9",x"23",x"7E",x"32",x"1C",x"40", -- 0x0238 + x"23",x"7E",x"32",x"1B",x"40",x"23",x"22",x"0C", -- 0x0240 + x"40",x"C9",x"3A",x"1B",x"40",x"32",x"00",x"78", -- 0x0248 + x"3A",x"1B",x"40",x"47",x"3A",x"1C",x"40",x"32", -- 0x0250 + x"1B",x"40",x"78",x"32",x"1C",x"40",x"C9",x"50", -- 0x0258 + x"55",x"53",x"48",x"20",x"53",x"54",x"41",x"52", -- 0x0260 + x"54",x"20",x"42",x"55",x"54",x"54",x"4F",x"4E", -- 0x0268 + x"FF",x"25",x"21",x"00",x"40",x"55",x"72",x"23", -- 0x0270 + x"7C",x"FE",x"44",x"20",x"F9",x"21",x"00",x"50", -- 0x0278 + x"06",x"04",x"0E",x"10",x"71",x"2C",x"20",x"FC", -- 0x0280 + x"24",x"3A",x"00",x"78",x"10",x"F6",x"CD",x"B1", -- 0x0288 + x"26",x"21",x"00",x"60",x"06",x"04",x"AF",x"77", -- 0x0290 + x"23",x"10",x"FC",x"3C",x"06",x"04",x"77",x"23", -- 0x0298 + x"10",x"FC",x"3E",x"03",x"32",x"6D",x"41",x"3D", -- 0x02A0 + x"32",x"A9",x"41",x"32",x"79",x"41",x"32",x"9D", -- 0x02A8 + x"41",x"07",x"32",x"9B",x"41",x"3E",x"07",x"32", -- 0x02B0 + x"A3",x"41",x"32",x"A5",x"41",x"32",x"6B",x"41", -- 0x02B8 + x"3E",x"04",x"32",x"A7",x"41",x"32",x"A9",x"41", -- 0x02C0 + x"AF",x"06",x"08",x"21",x"00",x"68",x"77",x"23", -- 0x02C8 + x"10",x"FC",x"32",x"06",x"70",x"32",x"07",x"70", -- 0x02D0 + x"3D",x"32",x"00",x"78",x"3A",x"00",x"68",x"CB", -- 0x02D8 + x"77",x"3E",x"03",x"CA",x"E8",x"02",x"3E",x"04", -- 0x02E0 + x"32",x"69",x"40",x"3A",x"00",x"68",x"CB",x"7F", -- 0x02E8 + x"3E",x"01",x"C2",x"F6",x"02",x"AF",x"32",x"8F", -- 0x02F0 + x"40",x"3A",x"00",x"70",x"CB",x"47",x"3E",x"10", -- 0x02F8 + x"CA",x"05",x"03",x"3E",x"20",x"32",x"68",x"40", -- 0x0300 + x"3A",x"00",x"70",x"CB",x"4F",x"3E",x"00",x"CA", -- 0x0308 + x"14",x"03",x"3E",x"01",x"32",x"0B",x"40",x"3A", -- 0x0310 + x"00",x"78",x"11",x"EB",x"03",x"21",x"40",x"53", -- 0x0318 + x"CD",x"E7",x"26",x"11",x"F5",x"03",x"21",x"80", -- 0x0320 + x"52",x"CD",x"E7",x"26",x"11",x"F0",x"03",x"21", -- 0x0328 + x"00",x"51",x"CD",x"E7",x"26",x"AF",x"32",x"01", -- 0x0330 + x"53",x"32",x"41",x"50",x"32",x"61",x"50",x"32", -- 0x0338 + x"A1",x"51",x"32",x"C1",x"51",x"3E",x"01",x"32", -- 0x0340 + x"04",x"70",x"32",x"01",x"70",x"DD",x"21",x"A1", -- 0x0348 + x"53",x"21",x"02",x"41",x"01",x"E0",x"FF",x"CD", -- 0x0350 + x"BA",x"03",x"DD",x"21",x"E1",x"50",x"21",x"05", -- 0x0358 + x"41",x"CD",x"BA",x"03",x"DD",x"21",x"41",x"52", -- 0x0360 + x"21",x"23",x"40",x"CD",x"BA",x"03",x"21",x"5F", -- 0x0368 + x"51",x"3A",x"8E",x"40",x"A7",x"C2",x"8B",x"03", -- 0x0370 + x"11",x"E0",x"FF",x"06",x"09",x"7E",x"FE",x"2C", -- 0x0378 + x"D2",x"85",x"03",x"36",x"10",x"19",x"10",x"F5", -- 0x0380 + x"C3",x"AB",x"03",x"11",x"00",x"04",x"CD",x"E7", -- 0x0388 + x"26",x"21",x"08",x"40",x"7E",x"0F",x"0F",x"0F", -- 0x0390 + x"0F",x"E6",x"0F",x"C2",x"A0",x"03",x"3E",x"10", -- 0x0398 + x"11",x"7F",x"50",x"12",x"7E",x"E6",x"0F",x"11", -- 0x03A0 + x"5F",x"50",x"12",x"21",x"67",x"40",x"ED",x"5F", -- 0x03A8 + x"E6",x"0F",x"86",x"77",x"CD",x"09",x"28",x"C3", -- 0x03B0 + x"4D",x"03",x"11",x"10",x"00",x"7E",x"CD",x"DE", -- 0x03B8 + x"03",x"2B",x"7E",x"0F",x"0F",x"0F",x"0F",x"CD", -- 0x03C0 + x"DE",x"03",x"7E",x"CD",x"DE",x"03",x"2B",x"7E", -- 0x03C8 + x"0F",x"0F",x"0F",x"0F",x"CD",x"DE",x"03",x"7E", -- 0x03D0 + x"E6",x"0F",x"DD",x"77",x"00",x"C9",x"E6",x"0F", -- 0x03D8 + x"CA",x"E4",x"03",x"5A",x"B3",x"DD",x"77",x"00", -- 0x03E0 + x"DD",x"09",x"C9",x"31",x"20",x"55",x"50",x"FF", -- 0x03E8 + x"32",x"20",x"55",x"50",x"FF",x"48",x"49",x"47", -- 0x03F0 + x"48",x"40",x"53",x"43",x"4F",x"52",x"45",x"FF", -- 0x03F8 + x"43",x"52",x"45",x"44",x"49",x"54",x"40",x"FF", -- 0x0400 + x"3A",x"08",x"41",x"FE",x"08",x"CA",x"1F",x"05", -- 0x0408 + x"FE",x"0C",x"CA",x"A8",x"04",x"FE",x"0A",x"CA", -- 0x0410 + x"CC",x"04",x"FE",x"10",x"CA",x"0F",x"05",x"FE", -- 0x0418 + x"06",x"CA",x"25",x"04",x"C9",x"3A",x"05",x"40", -- 0x0420 + x"E6",x"0C",x"CA",x"50",x"04",x"FE",x"0C",x"CA", -- 0x0428 + x"50",x"04",x"CB",x"57",x"21",x"A2",x"41",x"7E", -- 0x0430 + x"C2",x"47",x"04",x"FE",x"68",x"CA",x"50",x"04", -- 0x0438 + x"34",x"23",x"23",x"34",x"C3",x"50",x"04",x"FE", -- 0x0440 + x"96",x"CA",x"50",x"04",x"35",x"23",x"23",x"35", -- 0x0448 + x"3A",x"65",x"40",x"3C",x"E6",x"03",x"32",x"65", -- 0x0450 + x"40",x"CA",x"25",x"04",x"DD",x"21",x"EA",x"41", -- 0x0458 + x"FD",x"21",x"AA",x"41",x"3A",x"29",x"41",x"47", -- 0x0460 + x"DD",x"7E",x"00",x"FE",x"0E",x"D2",x"7D",x"04", -- 0x0468 + x"11",x"24",x"00",x"DD",x"19",x"11",x"04",x"00", -- 0x0470 + x"FD",x"19",x"10",x"EC",x"C9",x"FD",x"7E",x"03", -- 0x0478 + x"D6",x"D9",x"FE",x"13",x"D2",x"70",x"04",x"3A", -- 0x0480 + x"A2",x"41",x"4F",x"FD",x"7E",x"00",x"DD",x"86", -- 0x0488 + x"1A",x"C6",x"7F",x"91",x"D2",x"99",x"04",x"ED", -- 0x0490 + x"44",x"DD",x"BE",x"1D",x"D2",x"70",x"04",x"CD", -- 0x0498 + x"40",x"07",x"3E",x"0C",x"32",x"08",x"41",x"C9", -- 0x04A0 + x"3E",x"07",x"32",x"A7",x"41",x"32",x"A9",x"41", -- 0x04A8 + x"3A",x"00",x"40",x"FE",x"04",x"CA",x"BD",x"04", -- 0x04B0 + x"3E",x"01",x"32",x"03",x"68",x"21",x"3C",x"52", -- 0x04B8 + x"36",x"B8",x"3E",x"0A",x"32",x"08",x"41",x"21", -- 0x04C0 + x"03",x"40",x"36",x"01",x"21",x"03",x"40",x"35", -- 0x04C8 + x"C0",x"36",x"0A",x"21",x"3C",x"52",x"7E",x"C6", -- 0x04D0 + x"08",x"FE",x"E0",x"CA",x"EC",x"04",x"FE",x"D0", -- 0x04D8 + x"C2",x"E8",x"04",x"21",x"03",x"68",x"36",x"00", -- 0x04E0 + x"CD",x"FD",x"06",x"C9",x"3E",x"04",x"32",x"A7", -- 0x04E8 + x"41",x"32",x"A9",x"41",x"21",x"3C",x"52",x"11", -- 0x04F0 + x"DF",x"FF",x"3E",x"10",x"06",x"04",x"77",x"23", -- 0x04F8 + x"77",x"19",x"10",x"FA",x"3E",x"80",x"32",x"0A", -- 0x0500 + x"41",x"3E",x"10",x"32",x"08",x"41",x"C9",x"21", -- 0x0508 + x"0A",x"41",x"35",x"C0",x"3E",x"80",x"32",x"0A", -- 0x0510 + x"41",x"3E",x"0E",x"32",x"08",x"41",x"C9",x"21", -- 0x0518 + x"0A",x"41",x"35",x"C0",x"36",x"80",x"3E",x"FF", -- 0x0520 + x"32",x"A2",x"41",x"32",x"A4",x"41",x"3E",x"07", -- 0x0528 + x"32",x"A3",x"41",x"32",x"A5",x"41",x"3E",x"60", -- 0x0530 + x"32",x"FC",x"51",x"3C",x"32",x"FD",x"51",x"3C", -- 0x0538 + x"32",x"1C",x"52",x"3C",x"32",x"1D",x"52",x"3E", -- 0x0540 + x"06",x"32",x"08",x"41",x"C9",x"3A",x"0D",x"41", -- 0x0548 + x"21",x"13",x"41",x"BE",x"D2",x"DC",x"05",x"3A", -- 0x0550 + x"08",x"41",x"FE",x"06",x"C2",x"DC",x"05",x"3A", -- 0x0558 + x"05",x"40",x"CB",x"67",x"C2",x"6E",x"05",x"AF", -- 0x0560 + x"32",x"7B",x"40",x"C3",x"DC",x"05",x"3A",x"7B", -- 0x0568 + x"40",x"A7",x"C2",x"DC",x"05",x"3A",x"00",x"40", -- 0x0570 + x"FE",x"04",x"3E",x"01",x"CA",x"82",x"05",x"32", -- 0x0578 + x"05",x"68",x"32",x"7B",x"40",x"21",x"0D",x"41", -- 0x0580 + x"34",x"21",x"C7",x"41",x"11",x"04",x"00",x"3A", -- 0x0588 + x"A2",x"41",x"C6",x"7F",x"06",x"07",x"0E",x"07", -- 0x0590 + x"19",x"BE",x"C2",x"9F",x"05",x"CB",x"89",x"3C", -- 0x0598 + x"BE",x"C2",x"A6",x"05",x"CB",x"81",x"3C",x"BE", -- 0x05A0 + x"C2",x"AD",x"05",x"CB",x"91",x"D6",x"02",x"10", -- 0x05A8 + x"E7",x"3C",x"CB",x"41",x"C2",x"C5",x"05",x"3D", -- 0x05B0 + x"CB",x"49",x"C2",x"C5",x"05",x"C6",x"02",x"CB", -- 0x05B8 + x"51",x"C2",x"C5",x"05",x"3D",x"47",x"21",x"EA", -- 0x05C0 + x"41",x"11",x"FC",x"FF",x"AF",x"19",x"BE",x"C2", -- 0x05C8 + x"CD",x"05",x"36",x"FF",x"23",x"70",x"23",x"23", -- 0x05D0 + x"3A",x"20",x"41",x"77",x"DD",x"21",x"E6",x"41", -- 0x05D8 + x"3E",x"03",x"08",x"DD",x"22",x"6C",x"40",x"DD", -- 0x05E0 + x"CB",x"00",x"7E",x"CA",x"EE",x"06",x"DD",x"7E", -- 0x05E8 + x"03",x"21",x"1B",x"41",x"AE",x"C6",x"06",x"AE", -- 0x05F0 + x"DD",x"77",x"03",x"AE",x"FE",x"08",x"DA",x"C3", -- 0x05F8 + x"06",x"DD",x"35",x"00",x"DD",x"7E",x"00",x"FE", -- 0x0600 + x"FC",x"C2",x"11",x"06",x"21",x"05",x"68",x"36", -- 0x0608 + x"00",x"FE",x"DD",x"CA",x"C3",x"06",x"DD",x"56", -- 0x0610 + x"01",x"3A",x"1B",x"41",x"DD",x"AE",x"03",x"5F", -- 0x0618 + x"DD",x"21",x"EA",x"41",x"FD",x"21",x"AA",x"41", -- 0x0620 + x"3A",x"29",x"41",x"47",x"DD",x"7E",x"00",x"FE", -- 0x0628 + x"0E",x"DA",x"DE",x"06",x"7B",x"FD",x"86",x"03", -- 0x0630 + x"C6",x"14",x"FE",x"0F",x"D2",x"DE",x"06",x"FD", -- 0x0638 + x"7E",x"00",x"DD",x"86",x"1A",x"92",x"D2",x"4B", -- 0x0640 + x"06",x"ED",x"44",x"DD",x"BE",x"1B",x"D2",x"DE", -- 0x0648 + x"06",x"DD",x"BE",x"1C",x"DA",x"C0",x"06",x"3E", -- 0x0650 + x"02",x"CD",x"2B",x"28",x"4A",x"11",x"0D",x"2A", -- 0x0658 + x"CD",x"1F",x"27",x"CD",x"4A",x"28",x"DD",x"7E", -- 0x0660 + x"00",x"FE",x"18",x"CA",x"C3",x"06",x"CD",x"09", -- 0x0668 + x"28",x"E6",x"0F",x"C6",x"08",x"DD",x"77",x"21", -- 0x0670 + x"FD",x"7E",x"00",x"DD",x"86",x"1A",x"91",x"DA", -- 0x0678 + x"A0",x"06",x"DD",x"36",x"1F",x"80",x"FD",x"36", -- 0x0680 + x"01",x"94",x"DD",x"6E",x"18",x"DD",x"66",x"19", -- 0x0688 + x"23",x"3E",x"14",x"BE",x"CA",x"C3",x"06",x"36", -- 0x0690 + x"93",x"DD",x"36",x"00",x"1C",x"C3",x"C3",x"06", -- 0x0698 + x"DD",x"36",x"20",x"80",x"3E",x"94",x"FD",x"BE", -- 0x06A0 + x"01",x"CA",x"B0",x"06",x"FD",x"36",x"01",x"13", -- 0x06A8 + x"DD",x"6E",x"18",x"DD",x"66",x"19",x"23",x"36", -- 0x06B0 + x"14",x"DD",x"36",x"00",x"1C",x"C3",x"C3",x"06", -- 0x06B8 + x"CD",x"0E",x"07",x"AF",x"32",x"05",x"68",x"DD", -- 0x06C0 + x"2A",x"6C",x"40",x"DD",x"36",x"00",x"00",x"DD", -- 0x06C8 + x"36",x"01",x"00",x"DD",x"36",x"03",x"00",x"21", -- 0x06D0 + x"0D",x"41",x"35",x"C3",x"EE",x"06",x"D5",x"11", -- 0x06D8 + x"24",x"00",x"DD",x"19",x"11",x"04",x"00",x"FD", -- 0x06E0 + x"19",x"D1",x"05",x"C2",x"2C",x"06",x"DD",x"2A", -- 0x06E8 + x"6C",x"40",x"11",x"FC",x"FF",x"DD",x"19",x"08", -- 0x06F0 + x"3D",x"C2",x"E2",x"05",x"C9",x"11",x"DF",x"FF", -- 0x06F8 + x"21",x"3C",x"52",x"06",x"04",x"77",x"23",x"3C", -- 0x0700 + x"77",x"3C",x"19",x"10",x"F8",x"C9",x"DD",x"7E", -- 0x0708 + x"00",x"FE",x"14",x"C2",x"40",x"07",x"DD",x"36", -- 0x0710 + x"00",x"20",x"FD",x"36",x"02",x"05",x"DD",x"7E", -- 0x0718 + x"0D",x"CD",x"2B",x"28",x"3A",x"0B",x"41",x"FE", -- 0x0720 + x"03",x"3E",x"80",x"DA",x"3A",x"07",x"3A",x"67", -- 0x0728 + x"40",x"E6",x"30",x"C2",x"38",x"07",x"3E",x"10", -- 0x0730 + x"F6",x"80",x"DD",x"77",x"0D",x"C3",x"68",x"07", -- 0x0738 + x"FD",x"36",x"01",x"1C",x"DD",x"36",x"0A",x"07", -- 0x0740 + x"FD",x"36",x"02",x"07",x"DD",x"7E",x"00",x"DD", -- 0x0748 + x"36",x"00",x"0C",x"FE",x"12",x"DA",x"6B",x"07", -- 0x0750 + x"FE",x"16",x"DA",x"68",x"07",x"CA",x"6B",x"07", -- 0x0758 + x"FE",x"1E",x"DC",x"C2",x"0B",x"C3",x"6B",x"07", -- 0x0760 + x"CD",x"24",x"0D",x"11",x"EF",x"29",x"CD",x"1F", -- 0x0768 + x"27",x"CD",x"4A",x"28",x"C9",x"B1",x"07",x"B1", -- 0x0770 + x"07",x"B1",x"07",x"B9",x"07",x"44",x"09",x"C6", -- 0x0778 + x"07",x"FA",x"08",x"B1",x"07",x"B1",x"07",x"B4", -- 0x0780 + x"09",x"B4",x"09",x"9C",x"09",x"9C",x"09",x"9C", -- 0x0788 + x"09",x"43",x"08",x"DC",x"08",x"8C",x"09",x"DD", -- 0x0790 + x"21",x"EA",x"41",x"FD",x"21",x"AA",x"41",x"3A", -- 0x0798 + x"29",x"41",x"47",x"21",x"75",x"07",x"DD",x"5E", -- 0x07A0 + x"00",x"16",x"00",x"19",x"5E",x"23",x"56",x"EB", -- 0x07A8 + x"E9",x"DD",x"22",x"72",x"40",x"FD",x"22",x"74", -- 0x07B0 + x"40",x"11",x"24",x"00",x"DD",x"19",x"11",x"04", -- 0x07B8 + x"00",x"FD",x"19",x"10",x"DE",x"C9",x"DD",x"35", -- 0x07C0 + x"11",x"C2",x"B9",x"07",x"FD",x"7E",x"02",x"FE", -- 0x07C8 + x"07",x"3E",x"12",x"CA",x"D8",x"07",x"3E",x"14", -- 0x07D0 + x"DD",x"77",x"00",x"FD",x"36",x"01",x"12",x"FD", -- 0x07D8 + x"36",x"00",x"00",x"DD",x"6E",x"0F",x"DD",x"66", -- 0x07E0 + x"10",x"11",x"06",x"00",x"19",x"7E",x"FD",x"77", -- 0x07E8 + x"03",x"23",x"7E",x"DD",x"77",x"0C",x"DD",x"36", -- 0x07F0 + x"12",x"01",x"21",x"99",x"29",x"22",x"0C",x"40", -- 0x07F8 + x"21",x"00",x"00",x"22",x"0E",x"40",x"3E",x"01", -- 0x0800 + x"32",x"02",x"40",x"DD",x"7E",x"0E",x"E6",x"03", -- 0x0808 + x"C2",x"EB",x"0B",x"C5",x"DD",x"7E",x"0F",x"21", -- 0x0810 + x"D5",x"41",x"11",x"A9",x"41",x"01",x"24",x"00", -- 0x0818 + x"09",x"EB",x"01",x"04",x"00",x"09",x"EB",x"BE", -- 0x0820 + x"C2",x"1D",x"08",x"1A",x"FD",x"77",x"03",x"01", -- 0x0828 + x"F2",x"FF",x"09",x"DD",x"E5",x"D1",x"13",x"06", -- 0x0830 + x"0B",x"7E",x"12",x"23",x"13",x"10",x"FA",x"C1", -- 0x0838 + x"C3",x"B9",x"07",x"DD",x"7E",x"1F",x"A7",x"CA", -- 0x0840 + x"70",x"08",x"DD",x"35",x"1F",x"C2",x"69",x"08", -- 0x0848 + x"DD",x"36",x"21",x"00",x"21",x"30",x"41",x"3A", -- 0x0850 + x"0B",x"41",x"BE",x"DA",x"B6",x"08",x"FD",x"36", -- 0x0858 + x"01",x"13",x"DD",x"7E",x"20",x"A7",x"CA",x"94", -- 0x0860 + x"08",x"DD",x"7E",x"20",x"A7",x"CA",x"9F",x"08", -- 0x0868 + x"DD",x"35",x"20",x"C2",x"9F",x"08",x"DD",x"36", -- 0x0870 + x"21",x"00",x"21",x"30",x"41",x"3A",x"0B",x"41", -- 0x0878 + x"BE",x"DA",x"B6",x"08",x"DD",x"6E",x"18",x"DD", -- 0x0880 + x"66",x"19",x"23",x"36",x"93",x"DD",x"7E",x"1F", -- 0x0888 + x"A7",x"C2",x"9F",x"08",x"DD",x"36",x"00",x"1A", -- 0x0890 + x"DD",x"36",x"21",x"00",x"C3",x"B9",x"07",x"3A", -- 0x0898 + x"0B",x"41",x"21",x"30",x"41",x"BE",x"D2",x"D0", -- 0x08A0 + x"08",x"DD",x"7E",x"21",x"A7",x"CA",x"B6",x"08", -- 0x08A8 + x"DD",x"35",x"21",x"C2",x"D0",x"08",x"FD",x"7E", -- 0x08B0 + x"03",x"C6",x"06",x"FE",x"08",x"DA",x"91",x"0B", -- 0x08B8 + x"FD",x"77",x"03",x"DD",x"6E",x"18",x"DD",x"66", -- 0x08C0 + x"19",x"23",x"23",x"23",x"77",x"C3",x"B9",x"07", -- 0x08C8 + x"ED",x"5F",x"E6",x"02",x"3D",x"DD",x"36",x"12", -- 0x08D0 + x"01",x"C3",x"12",x"0A",x"DD",x"35",x"0A",x"C2", -- 0x08D8 + x"B9",x"07",x"DD",x"36",x"0A",x"06",x"FD",x"7E", -- 0x08E0 + x"02",x"EE",x"01",x"FD",x"77",x"02",x"DD",x"35", -- 0x08E8 + x"0C",x"C2",x"B9",x"07",x"CD",x"40",x"07",x"C3", -- 0x08F0 + x"B9",x"07",x"DD",x"35",x"0A",x"C2",x"B9",x"07", -- 0x08F8 + x"DD",x"36",x"0A",x"07",x"FD",x"34",x"01",x"FD", -- 0x0900 + x"7E",x"01",x"FE",x"20",x"C2",x"B9",x"07",x"DD", -- 0x0908 + x"7E",x"0D",x"E6",x"7F",x"C2",x"19",x"09",x"F6", -- 0x0910 + x"80",x"CD",x"2B",x"28",x"CD",x"4A",x"28",x"DD", -- 0x0918 + x"CB",x"0D",x"7E",x"CA",x"4A",x"09",x"DD",x"7E", -- 0x0920 + x"0D",x"0F",x"0F",x"0F",x"0F",x"E6",x"03",x"0E", -- 0x0928 + x"20",x"81",x"FD",x"77",x"01",x"FD",x"36",x"02", -- 0x0930 + x"05",x"DD",x"36",x"0A",x"20",x"DD",x"36",x"00", -- 0x0938 + x"08",x"C3",x"B9",x"07",x"DD",x"35",x"0A",x"C2", -- 0x0940 + x"B9",x"07",x"FD",x"36",x"01",x"00",x"FD",x"36", -- 0x0948 + x"00",x"00",x"FD",x"36",x"03",x"00",x"DD",x"36", -- 0x0950 + x"00",x"00",x"21",x"0C",x"41",x"35",x"2B",x"35", -- 0x0958 + x"20",x"0D",x"3A",x"00",x"40",x"FE",x"04",x"C2", -- 0x0960 + x"B9",x"07",x"36",x"08",x"C3",x"B9",x"07",x"7E", -- 0x0968 + x"21",x"30",x"41",x"BE",x"D2",x"B9",x"07",x"3A", -- 0x0970 + x"06",x"41",x"FE",x"04",x"C2",x"B9",x"07",x"CD", -- 0x0978 + x"09",x"28",x"E6",x"0F",x"C6",x"08",x"DD",x"77", -- 0x0980 + x"21",x"C3",x"B9",x"07",x"FD",x"7E",x"03",x"C6", -- 0x0988 + x"06",x"FD",x"77",x"03",x"FE",x"08",x"DA",x"80", -- 0x0990 + x"0B",x"C3",x"B9",x"07",x"FD",x"7E",x"00",x"CB", -- 0x0998 + x"7F",x"CA",x"A5",x"09",x"2F",x"07",x"07",x"07", -- 0x09A0 + x"E6",x"03",x"C2",x"AE",x"09",x"3C",x"DD",x"77", -- 0x09A8 + x"12",x"C3",x"C6",x"09",x"DD",x"35",x"23",x"C2", -- 0x09B0 + x"C6",x"09",x"DD",x"36",x"23",x"07",x"FD",x"7E", -- 0x09B8 + x"01",x"EE",x"06",x"FD",x"77",x"01",x"AF",x"57", -- 0x09C0 + x"5F",x"DD",x"BE",x"05",x"CA",x"D3",x"09",x"DD", -- 0x09C8 + x"35",x"05",x"1D",x"DD",x"BE",x"06",x"CA",x"DD", -- 0x09D0 + x"09",x"DD",x"35",x"06",x"15",x"B2",x"B3",x"C2", -- 0x09D8 + x"F1",x"09",x"DD",x"7E",x"03",x"DD",x"77",x"05", -- 0x09E0 + x"DD",x"7E",x"04",x"DD",x"77",x"06",x"C3",x"C6", -- 0x09E8 + x"09",x"DD",x"7E",x"09",x"07",x"E6",x"02",x"3D", -- 0x09F0 + x"A3",x"FD",x"86",x"00",x"DD",x"BE",x"14",x"CA", -- 0x09F8 + x"62",x"0B",x"DD",x"BE",x"15",x"CA",x"62",x"0B", -- 0x0A00 + x"FD",x"77",x"00",x"DD",x"7E",x"09",x"E6",x"02", -- 0x0A08 + x"3D",x"A2",x"FD",x"86",x"03",x"CA",x"91",x"0B", -- 0x0A10 + x"FE",x"10",x"D2",x"30",x"0A",x"DD",x"7E",x"0C", -- 0x0A18 + x"EE",x"AA",x"DD",x"77",x"0C",x"DD",x"7E",x"09", -- 0x0A20 + x"EE",x"AA",x"DD",x"77",x"09",x"C3",x"6B",x"0A", -- 0x0A28 + x"FD",x"77",x"03",x"FE",x"E0",x"C2",x"6B",x"0A", -- 0x0A30 + x"DD",x"7E",x"00",x"FE",x"14",x"C2",x"6B",x"0A", -- 0x0A38 + x"FD",x"7E",x"00",x"FE",x"40",x"DA",x"6B",x"0A", -- 0x0A40 + x"FE",x"C0",x"D2",x"6B",x"0A",x"21",x"66",x"40", -- 0x0A48 + x"BE",x"CA",x"6B",x"0A",x"77",x"ED",x"5F",x"E6", -- 0x0A50 + x"FE",x"3C",x"DD",x"77",x"0C",x"DD",x"36",x"0A", -- 0x0A58 + x"06",x"DD",x"36",x"00",x"1E",x"CD",x"24",x"0D", -- 0x0A60 + x"C3",x"B9",x"07",x"DD",x"7E",x"00",x"FE",x"18", -- 0x0A68 + x"DA",x"86",x"0A",x"DD",x"6E",x"18",x"DD",x"66", -- 0x0A70 + x"19",x"FD",x"7E",x"00",x"C6",x"0F",x"77",x"23", -- 0x0A78 + x"23",x"23",x"FD",x"7E",x"03",x"77",x"DD",x"35", -- 0x0A80 + x"12",x"C2",x"C6",x"09",x"21",x"30",x"41",x"3A", -- 0x0A88 + x"0B",x"41",x"BE",x"3E",x"01",x"D2",x"99",x"0A", -- 0x0A90 + x"3C",x"DD",x"77",x"12",x"DD",x"35",x"0B",x"C2", -- 0x0A98 + x"8C",x"0C",x"DD",x"7E",x"00",x"FE",x"16",x"DA", -- 0x0AA0 + x"B3",x"0A",x"ED",x"5F",x"E6",x"1F",x"C6",x"08", -- 0x0AA8 + x"C3",x"BB",x"0A",x"DD",x"6E",x"0F",x"DD",x"66", -- 0x0AB0 + x"10",x"23",x"7E",x"DD",x"77",x"0B",x"DD",x"6E", -- 0x0AB8 + x"01",x"DD",x"66",x"02",x"23",x"DD",x"75",x"01", -- 0x0AC0 + x"DD",x"74",x"02",x"7E",x"A7",x"CA",x"DA",x"0B", -- 0x0AC8 + x"0F",x"0F",x"0F",x"0F",x"E6",x"0F",x"DD",x"77", -- 0x0AD0 + x"03",x"DD",x"77",x"05",x"7E",x"E6",x"0F",x"DD", -- 0x0AD8 + x"77",x"04",x"DD",x"77",x"06",x"DD",x"CB",x"09", -- 0x0AE0 + x"0E",x"DD",x"CB",x"09",x"0E",x"DD",x"35",x"0A", -- 0x0AE8 + x"C2",x"0B",x"0B",x"DD",x"36",x"0A",x"04",x"DD", -- 0x0AF0 + x"6E",x"07",x"DD",x"66",x"08",x"23",x"DD",x"75", -- 0x0AF8 + x"07",x"DD",x"74",x"08",x"7E",x"DD",x"AE",x"0C", -- 0x0B00 + x"DD",x"77",x"09",x"CD",x"11",x"0B",x"C3",x"B9", -- 0x0B08 + x"07",x"DD",x"7E",x"00",x"FE",x"1A",x"C0",x"DD", -- 0x0B10 + x"7E",x"03",x"A7",x"CA",x"54",x"0B",x"DD",x"96", -- 0x0B18 + x"04",x"D2",x"26",x"0B",x"ED",x"44",x"DD",x"BE", -- 0x0B20 + x"03",x"CA",x"54",x"0B",x"FE",x"03",x"DA",x"54", -- 0x0B28 + x"0B",x"DD",x"CB",x"09",x"46",x"C2",x"46",x"0B", -- 0x0B30 + x"FD",x"36",x"01",x"96",x"DD",x"6E",x"18",x"DD", -- 0x0B38 + x"66",x"19",x"23",x"36",x"95",x"C9",x"FD",x"36", -- 0x0B40 + x"01",x"15",x"DD",x"6E",x"18",x"DD",x"66",x"19", -- 0x0B48 + x"23",x"36",x"16",x"C9",x"FD",x"36",x"01",x"13", -- 0x0B50 + x"DD",x"6E",x"18",x"DD",x"66",x"19",x"23",x"36", -- 0x0B58 + x"93",x"C9",x"DD",x"7E",x"00",x"FE",x"16",x"DA", -- 0x0B60 + x"91",x"0B",x"3E",x"55",x"DD",x"AE",x"0C",x"DD", -- 0x0B68 + x"77",x"0C",x"3E",x"55",x"DD",x"AE",x"09",x"DD", -- 0x0B70 + x"77",x"09",x"CD",x"11",x"0B",x"C3",x"6B",x"0A", -- 0x0B78 + x"21",x"0B",x"41",x"35",x"C2",x"91",x"0B",x"3A", -- 0x0B80 + x"00",x"40",x"FE",x"04",x"C2",x"91",x"0B",x"36", -- 0x0B88 + x"10",x"FD",x"36",x"01",x"00",x"FD",x"36",x"00", -- 0x0B90 + x"00",x"FD",x"36",x"03",x"00",x"FD",x"36",x"02", -- 0x0B98 + x"00",x"DD",x"7E",x"00",x"FE",x"16",x"DA",x"B4", -- 0x0BA0 + x"0B",x"CA",x"B7",x"0B",x"FE",x"1E",x"DC",x"C2", -- 0x0BA8 + x"0B",x"C3",x"B7",x"0B",x"CD",x"24",x"0D",x"DD", -- 0x0BB0 + x"36",x"00",x"00",x"21",x"0C",x"41",x"35",x"C3", -- 0x0BB8 + x"B9",x"07",x"DD",x"6E",x"16",x"DD",x"66",x"17", -- 0x0BC0 + x"36",x"00",x"DD",x"6E",x"18",x"DD",x"66",x"19", -- 0x0BC8 + x"0E",x"04",x"36",x"00",x"23",x"0D",x"C2",x"D2", -- 0x0BD0 + x"0B",x"C9",x"DD",x"7E",x"00",x"FE",x"16",x"DA", -- 0x0BD8 + x"EB",x"0B",x"CD",x"7D",x"27",x"CD",x"11",x"0B", -- 0x0BE0 + x"C3",x"B9",x"07",x"DD",x"5E",x"0F",x"DD",x"56", -- 0x0BE8 + x"10",x"13",x"DD",x"CB",x"0E",x"46",x"C2",x"32", -- 0x0BF0 + x"0C",x"EB",x"7E",x"DD",x"77",x"0B",x"23",x"5E", -- 0x0BF8 + x"DD",x"73",x"07",x"23",x"56",x"DD",x"72",x"08", -- 0x0C00 + x"1A",x"DD",x"AE",x"0C",x"DD",x"77",x"09",x"23", -- 0x0C08 + x"5E",x"DD",x"73",x"01",x"23",x"56",x"DD",x"72", -- 0x0C10 + x"02",x"1A",x"0F",x"0F",x"0F",x"0F",x"E6",x"0F", -- 0x0C18 + x"DD",x"77",x"03",x"DD",x"77",x"05",x"1A",x"E6", -- 0x0C20 + x"0F",x"DD",x"77",x"04",x"DD",x"77",x"06",x"C3", -- 0x0C28 + x"B9",x"07",x"C5",x"ED",x"5F",x"E6",x"0F",x"C6", -- 0x0C30 + x"08",x"DD",x"77",x"0B",x"12",x"13",x"ED",x"5F", -- 0x0C38 + x"E6",x"0C",x"4F",x"06",x"00",x"21",x"68",x"2B", -- 0x0C40 + x"09",x"7E",x"23",x"12",x"13",x"4F",x"DD",x"77", -- 0x0C48 + x"07",x"7E",x"23",x"47",x"12",x"13",x"DD",x"77", -- 0x0C50 + x"08",x"0A",x"DD",x"AE",x"0C",x"DD",x"77",x"09", -- 0x0C58 + x"DD",x"36",x"0A",x"04",x"7E",x"23",x"4F",x"12", -- 0x0C60 + x"13",x"DD",x"77",x"01",x"7E",x"47",x"12",x"DD", -- 0x0C68 + x"77",x"02",x"0A",x"0F",x"0F",x"0F",x"0F",x"E6", -- 0x0C70 + x"0F",x"DD",x"77",x"03",x"DD",x"77",x"05",x"0A", -- 0x0C78 + x"E6",x"0F",x"DD",x"77",x"04",x"DD",x"77",x"06", -- 0x0C80 + x"C1",x"C3",x"B9",x"07",x"DD",x"35",x"13",x"C2", -- 0x0C88 + x"B9",x"07",x"DD",x"36",x"13",x"50",x"DD",x"7E", -- 0x0C90 + x"00",x"FE",x"18",x"CA",x"02",x"0D",x"FE",x"16", -- 0x0C98 + x"C2",x"B9",x"07",x"2A",x"72",x"40",x"7C",x"B5", -- 0x0CA0 + x"CA",x"B9",x"07",x"11",x"00",x"00",x"ED",x"53", -- 0x0CA8 + x"72",x"40",x"ED",x"5B",x"74",x"40",x"36",x"06", -- 0x0CB0 + x"DD",x"75",x"16",x"DD",x"74",x"17",x"DD",x"73", -- 0x0CB8 + x"18",x"DD",x"72",x"19",x"DD",x"36",x"14",x"08", -- 0x0CC0 + x"DD",x"36",x"15",x"F0",x"FD",x"7E",x"00",x"D6", -- 0x0CC8 + x"08",x"FD",x"77",x"00",x"C6",x"0F",x"12",x"13", -- 0x0CD0 + x"FD",x"34",x"01",x"FD",x"7E",x"01",x"F6",x"80", -- 0x0CD8 + x"12",x"13",x"FD",x"7E",x"02",x"12",x"13",x"FD", -- 0x0CE0 + x"7E",x"03",x"12",x"DD",x"36",x"1A",x"0F",x"DD", -- 0x0CE8 + x"36",x"1B",x"0B",x"DD",x"36",x"1C",x"05",x"DD", -- 0x0CF0 + x"36",x"1D",x"11",x"DD",x"36",x"00",x"18",x"C3", -- 0x0CF8 + x"B9",x"07",x"FD",x"34",x"01",x"DD",x"6E",x"18", -- 0x0D00 + x"DD",x"66",x"19",x"23",x"34",x"DD",x"36",x"1A", -- 0x0D08 + x"0F",x"DD",x"36",x"1B",x"10",x"DD",x"36",x"1C", -- 0x0D10 + x"05",x"DD",x"36",x"1D",x"16",x"DD",x"36",x"00", -- 0x0D18 + x"1A",x"C3",x"B9",x"07",x"DD",x"6E",x"0F",x"DD", -- 0x0D20 + x"66",x"10",x"DD",x"36",x"0F",x"00",x"35",x"C8", -- 0x0D28 + x"DD",x"CB",x"0E",x"46",x"C8",x"7D",x"11",x"24", -- 0x0D30 + x"00",x"21",x"D5",x"41",x"19",x"BE",x"C2",x"3C", -- 0x0D38 + x"0D",x"2B",x"CB",x"C6",x"C9",x"DD",x"21",x"AA", -- 0x0D40 + x"41",x"3A",x"05",x"40",x"E6",x"0C",x"CA",x"7C", -- 0x0D48 + x"0D",x"FE",x"0C",x"CA",x"7C",x"0D",x"CB",x"57", -- 0x0D50 + x"21",x"A2",x"41",x"DD",x"7E",x"00",x"C2",x"70", -- 0x0D58 + x"0D",x"FE",x"E1",x"CA",x"7C",x"0D",x"DD",x"34", -- 0x0D60 + x"00",x"34",x"DD",x"34",x"04",x"C3",x"7C",x"0D", -- 0x0D68 + x"FE",x"0F",x"CA",x"7C",x"0D",x"DD",x"35",x"00", -- 0x0D70 + x"35",x"DD",x"35",x"04",x"3A",x"65",x"40",x"3C", -- 0x0D78 + x"E6",x"03",x"32",x"65",x"40",x"CA",x"49",x"0D", -- 0x0D80 + x"21",x"76",x"40",x"35",x"C2",x"A5",x"0D",x"3A", -- 0x0D88 + x"78",x"40",x"77",x"DD",x"35",x"03",x"DD",x"35", -- 0x0D90 + x"07",x"EB",x"21",x"20",x"41",x"3A",x"1B",x"41", -- 0x0D98 + x"37",x"17",x"86",x"77",x"EB",x"23",x"35",x"C2", -- 0x0DA0 + x"B5",x"0D",x"36",x"0F",x"23",x"35",x"7E",x"FE", -- 0x0DA8 + x"02",x"D2",x"B5",x"0D",x"34",x"21",x"6E",x"40", -- 0x0DB0 + x"35",x"C2",x"C6",x"0D",x"36",x"03",x"DD",x"7E", -- 0x0DB8 + x"05",x"EE",x"34",x"DD",x"77",x"05",x"3A",x"10", -- 0x0DC0 + x"40",x"DD",x"46",x"03",x"FE",x"00",x"CA",x"E0", -- 0x0DC8 + x"0D",x"FE",x"01",x"CA",x"E6",x"0D",x"FE",x"02", -- 0x0DD0 + x"C0",x"78",x"FE",x"E0",x"C0",x"C3",x"E6",x"0D", -- 0x0DD8 + x"78",x"A7",x"CA",x"E6",x"0D",x"C9",x"21",x"10", -- 0x0DE0 + x"40",x"34",x"C9",x"21",x"1D",x"40",x"35",x"C0", -- 0x0DE8 + x"36",x"08",x"3A",x"08",x"41",x"FE",x"06",x"C0", -- 0x0DF0 + x"3A",x"1E",x"40",x"21",x"27",x"41",x"BE",x"C8", -- 0x0DF8 + x"3A",x"0C",x"41",x"A7",x"C8",x"47",x"DD",x"21", -- 0x0E00 + x"C6",x"41",x"FD",x"21",x"A6",x"41",x"11",x"24", -- 0x0E08 + x"00",x"DD",x"19",x"11",x"04",x"00",x"FD",x"19", -- 0x0E10 + x"DD",x"7E",x"00",x"1E",x"00",x"FE",x"12",x"CA", -- 0x0E18 + x"2D",x"0E",x"1D",x"FE",x"1A",x"CA",x"2D",x"0E", -- 0x0E20 + x"FE",x"1C",x"C2",x"93",x"0E",x"FD",x"7E",x"00", -- 0x0E28 + x"FE",x"0A",x"DA",x"93",x"0E",x"FE",x"E7",x"D2", -- 0x0E30 + x"93",x"0E",x"FD",x"7E",x"03",x"FE",x"A0",x"D2", -- 0x0E38 + x"93",x"0E",x"3A",x"A2",x"41",x"FD",x"96",x"00", -- 0x0E40 + x"C6",x"89",x"FE",x"21",x"D2",x"93",x"0E",x"FD", -- 0x0E48 + x"7E",x"00",x"DD",x"86",x"1E",x"4F",x"ED",x"5F", -- 0x0E50 + x"E6",x"07",x"D6",x"04",x"A3",x"81",x"21",x"C7", -- 0x0E58 + x"41",x"11",x"04",x"00",x"0E",x"07",x"19",x"BE", -- 0x0E60 + x"CA",x"93",x"0E",x"0D",x"C2",x"66",x"0E",x"DD", -- 0x0E68 + x"21",x"C6",x"41",x"47",x"DD",x"19",x"DD",x"7E", -- 0x0E70 + x"01",x"DD",x"B6",x"03",x"C2",x"74",x"0E",x"DD", -- 0x0E78 + x"70",x"01",x"3E",x"F5",x"FD",x"96",x"03",x"21", -- 0x0E80 + x"1B",x"41",x"AE",x"DD",x"77",x"03",x"21",x"1E", -- 0x0E88 + x"40",x"34",x"C9",x"DD",x"7E",x"00",x"FE",x"08", -- 0x0E90 + x"DA",x"0E",x"0E",x"05",x"C2",x"0E",x"0E",x"C9", -- 0x0E98 + x"3A",x"1E",x"40",x"A7",x"C8",x"47",x"DD",x"21", -- 0x0EA0 + x"C6",x"41",x"11",x"04",x"00",x"DD",x"19",x"DD", -- 0x0EA8 + x"7E",x"03",x"A7",x"CA",x"AD",x"0E",x"21",x"1B", -- 0x0EB0 + x"41",x"AE",x"D6",x"03",x"AE",x"DD",x"77",x"03", -- 0x0EB8 + x"AE",x"FE",x"1B",x"D2",x"05",x"0F",x"3A",x"08", -- 0x0EC0 + x"41",x"FE",x"06",x"C2",x"ED",x"0E",x"3A",x"A2", -- 0x0EC8 + x"41",x"C6",x"87",x"DD",x"96",x"01",x"FE",x"0D", -- 0x0ED0 + x"D2",x"ED",x"0E",x"DD",x"36",x"01",x"00",x"DD", -- 0x0ED8 + x"36",x"03",x"00",x"21",x"1E",x"40",x"35",x"3E", -- 0x0EE0 + x"0C",x"32",x"08",x"41",x"C9",x"DD",x"7E",x"03", -- 0x0EE8 + x"21",x"1B",x"41",x"AE",x"FE",x"0F",x"D2",x"05", -- 0x0EF0 + x"0F",x"DD",x"36",x"03",x"00",x"DD",x"36",x"01", -- 0x0EF8 + x"00",x"21",x"1E",x"40",x"35",x"10",x"A6",x"C9", -- 0x0F00 + x"3A",x"08",x"41",x"FE",x"06",x"C0",x"3A",x"0C", -- 0x0F08 + x"41",x"21",x"29",x"41",x"BE",x"C8",x"47",x"3A", -- 0x0F10 + x"0B",x"41",x"90",x"C8",x"4F",x"CD",x"09",x"28", -- 0x0F18 + x"47",x"3A",x"0B",x"41",x"21",x"34",x"41",x"BE", -- 0x0F20 + x"78",x"D2",x"32",x"0F",x"E6",x"01",x"3C",x"C3", -- 0x0F28 + x"35",x"0F",x"E6",x"03",x"86",x"47",x"79",x"90", -- 0x0F30 + x"D8",x"3A",x"0C",x"41",x"80",x"21",x"29",x"41", -- 0x0F38 + x"3D",x"BE",x"D0",x"3C",x"32",x"0C",x"41",x"21", -- 0x0F40 + x"1C",x"40",x"11",x"08",x"00",x"AF",x"19",x"BE", -- 0x0F48 + x"C2",x"4E",x"0F",x"70",x"CD",x"09",x"28",x"4F", -- 0x0F50 + x"CB",x"3F",x"A1",x"2F",x"F6",x"01",x"E6",x"03", -- 0x0F58 + x"4F",x"DD",x"21",x"C6",x"41",x"FD",x"21",x"A6", -- 0x0F60 + x"41",x"11",x"24",x"00",x"DD",x"19",x"11",x"04", -- 0x0F68 + x"00",x"FD",x"19",x"DD",x"7E",x"00",x"FE",x"00", -- 0x0F70 + x"C2",x"69",x"0F",x"ED",x"5F",x"E6",x"03",x"80", -- 0x0F78 + x"DD",x"36",x"0D",x"08",x"16",x"07",x"FE",x"03", -- 0x0F80 + x"D2",x"91",x"0F",x"16",x"04",x"DD",x"36",x"0D", -- 0x0F88 + x"05",x"FD",x"72",x"02",x"DD",x"71",x"0E",x"DD", -- 0x0F90 + x"71",x"11",x"DD",x"75",x"0F",x"DD",x"74",x"10", -- 0x0F98 + x"DD",x"36",x"0A",x"04",x"DD",x"36",x"00",x"0A", -- 0x0FA0 + x"DD",x"36",x"14",x"00",x"DD",x"36",x"15",x"00", -- 0x0FA8 + x"DD",x"36",x"1A",x"07",x"DD",x"36",x"1B",x"08", -- 0x0FB0 + x"DD",x"36",x"1C",x"08",x"DD",x"36",x"1D",x"0E", -- 0x0FB8 + x"DD",x"36",x"1E",x"08",x"DD",x"36",x"22",x"FF", -- 0x0FC0 + x"DD",x"36",x"23",x"07",x"3E",x"28",x"81",x"E6", -- 0x0FC8 + x"FE",x"4F",x"10",x"95",x"11",x"06",x"00",x"19", -- 0x0FD0 + x"ED",x"5F",x"E6",x"7F",x"4F",x"ED",x"5F",x"E6", -- 0x0FD8 + x"3F",x"81",x"C6",x"1C",x"77",x"FE",x"60",x"DA", -- 0x0FE0 + x"EC",x"0F",x"CB",x"C8",x"ED",x"5F",x"E6",x"01", -- 0x0FE8 + x"B0",x"47",x"07",x"07",x"B0",x"47",x"07",x"07", -- 0x0FF0 + x"07",x"07",x"B0",x"23",x"77",x"C9",x"3A",x"08", -- 0x0FF8 + x"41",x"FE",x"06",x"C0",x"21",x"0C",x"41",x"3A", -- 0x1000 + x"29",x"41",x"BE",x"C8",x"3A",x"0B",x"41",x"BE", -- 0x1008 + x"C8",x"34",x"21",x"00",x"00",x"22",x"72",x"40", -- 0x1010 + x"DD",x"21",x"C6",x"41",x"FD",x"21",x"A6",x"41", -- 0x1018 + x"01",x"24",x"00",x"11",x"04",x"00",x"DD",x"09", -- 0x1020 + x"FD",x"19",x"DD",x"7E",x"00",x"FE",x"00",x"C2", -- 0x1028 + x"26",x"10",x"FD",x"36",x"01",x"11",x"ED",x"5F", -- 0x1030 + x"E6",x"3F",x"C6",x"10",x"FD",x"77",x"03",x"ED", -- 0x1038 + x"5F",x"E6",x"7F",x"C6",x"40",x"FD",x"77",x"00", -- 0x1040 + x"DD",x"36",x"0D",x"10",x"21",x"30",x"41",x"3A", -- 0x1048 + x"0B",x"41",x"BE",x"3E",x"07",x"D2",x"69",x"10", -- 0x1050 + x"DD",x"36",x"0D",x"15",x"FE",x"01",x"3E",x"04", -- 0x1058 + x"C2",x"69",x"10",x"3E",x"02",x"DD",x"36",x"0D", -- 0x1060 + x"20",x"FD",x"77",x"02",x"DD",x"CB",x"0E",x"C6", -- 0x1068 + x"DD",x"36",x"1E",x"10",x"DD",x"36",x"13",x"50", -- 0x1070 + x"DD",x"36",x"14",x"12",x"DD",x"36",x"15",x"E8", -- 0x1078 + x"DD",x"36",x"1A",x"07",x"DD",x"36",x"1B",x"08", -- 0x1080 + x"DD",x"36",x"1C",x"08",x"DD",x"36",x"1D",x"0E", -- 0x1088 + x"CD",x"09",x"28",x"E6",x"01",x"5F",x"3A",x"31", -- 0x1090 + x"41",x"3C",x"07",x"2F",x"E6",x"07",x"C2",x"A2", -- 0x1098 + x"10",x"3C",x"83",x"DD",x"77",x"11",x"DD",x"36", -- 0x10A0 + x"22",x"FF",x"CD",x"7D",x"27",x"DD",x"36",x"00", -- 0x10A8 + x"16",x"C9",x"CD",x"FC",x"26",x"CD",x"B1",x"26", -- 0x10B0 + x"AF",x"32",x"06",x"70",x"32",x"07",x"70",x"3E", -- 0x10B8 + x"01",x"32",x"02",x"60",x"21",x"47",x"52",x"11", -- 0x10C0 + x"C2",x"18",x"CD",x"E7",x"26",x"21",x"39",x"53", -- 0x10C8 + x"11",x"FB",x"18",x"CD",x"E7",x"26",x"21",x"38", -- 0x10D0 + x"53",x"11",x"11",x"19",x"CD",x"E7",x"26",x"21", -- 0x10D8 + x"37",x"53",x"11",x"27",x"19",x"CD",x"E7",x"26", -- 0x10E0 + x"21",x"36",x"53",x"11",x"3C",x"19",x"CD",x"E7", -- 0x10E8 + x"26",x"3E",x"02",x"32",x"00",x"40",x"C9",x"21", -- 0x10F0 + x"1F",x"40",x"35",x"C0",x"3E",x"04",x"32",x"00", -- 0x10F8 + x"40",x"CD",x"FC",x"26",x"3E",x"00",x"32",x"02", -- 0x1100 + x"60",x"CD",x"41",x"27",x"CD",x"BF",x"12",x"CD", -- 0x1108 + x"09",x"28",x"E6",x"1F",x"3C",x"32",x"9B",x"40", -- 0x1110 + x"3A",x"9C",x"40",x"EE",x"04",x"32",x"9C",x"40", -- 0x1118 + x"EE",x"04",x"32",x"06",x"41",x"A7",x"CA",x"2D", -- 0x1120 + x"11",x"CD",x"6F",x"15",x"C9",x"CD",x"2D",x"18", -- 0x1128 + x"C9",x"3A",x"04",x"40",x"CB",x"4F",x"C2",x"4D", -- 0x1130 + x"11",x"CB",x"47",x"C8",x"3A",x"08",x"40",x"C6", -- 0x1138 + x"99",x"27",x"32",x"08",x"40",x"CD",x"FC",x"26", -- 0x1140 + x"3E",x"08",x"C3",x"65",x"11",x"3A",x"08",x"40", -- 0x1148 + x"C6",x"98",x"27",x"D0",x"32",x"08",x"40",x"CD", -- 0x1150 + x"FC",x"26",x"21",x"8F",x"52",x"11",x"C9",x"18", -- 0x1158 + x"CD",x"E7",x"26",x"3E",x"0A",x"32",x"00",x"40", -- 0x1160 + x"AF",x"32",x"8E",x"40",x"3E",x"80",x"32",x"11", -- 0x1168 + x"41",x"C9",x"CD",x"08",x"04",x"CD",x"84",x"28", -- 0x1170 + x"3A",x"08",x"41",x"FE",x"0E",x"CA",x"AD",x"11", -- 0x1178 + x"CD",x"4D",x"05",x"CD",x"08",x"0F",x"CD",x"97", -- 0x1180 + x"07",x"CD",x"EB",x"0D",x"CD",x"A0",x"0E",x"3A", -- 0x1188 + x"0B",x"41",x"A7",x"C0",x"3A",x"1E",x"40",x"A7", -- 0x1190 + x"C0",x"3A",x"08",x"41",x"FE",x"06",x"C0",x"3A", -- 0x1198 + x"00",x"40",x"C6",x"FA",x"32",x"00",x"40",x"21", -- 0x11A0 + x"06",x"41",x"34",x"34",x"C9",x"3A",x"00",x"40", -- 0x11A8 + x"FE",x"04",x"CA",x"9A",x"14",x"21",x"97",x"29", -- 0x11B0 + x"22",x"0C",x"40",x"21",x"00",x"00",x"22",x"0E", -- 0x11B8 + x"40",x"21",x"60",x"50",x"FE",x"18",x"CA",x"CC", -- 0x11C0 + x"11",x"21",x"A0",x"53",x"35",x"CD",x"B1",x"26", -- 0x11C8 + x"21",x"10",x"41",x"35",x"C2",x"04",x"12",x"CD", -- 0x11D0 + x"FC",x"26",x"21",x"8D",x"52",x"11",x"DF",x"18", -- 0x11D8 + x"CD",x"E7",x"26",x"3A",x"00",x"40",x"FE",x"14", -- 0x11E0 + x"CA",x"FF",x"11",x"21",x"8F",x"52",x"11",x"C9", -- 0x11E8 + x"18",x"FE",x"16",x"CA",x"F9",x"11",x"11",x"D4", -- 0x11F0 + x"18",x"CD",x"E7",x"26",x"3A",x"00",x"40",x"C6", -- 0x11F8 + x"12",x"C3",x"42",x"12",x"3A",x"00",x"40",x"FE", -- 0x1200 + x"14",x"CA",x"3D",x"12",x"CD",x"FC",x"26",x"21", -- 0x1208 + x"8F",x"52",x"11",x"D4",x"18",x"3A",x"00",x"40", -- 0x1210 + x"FE",x"16",x"3A",x"8F",x"40",x"CA",x"24",x"12", -- 0x1218 + x"AF",x"11",x"C9",x"18",x"32",x"06",x"70",x"32", -- 0x1220 + x"07",x"70",x"CD",x"E7",x"26",x"3A",x"20",x"40", -- 0x1228 + x"A7",x"C2",x"3D",x"12",x"21",x"8D",x"52",x"11", -- 0x1230 + x"DF",x"18",x"CD",x"E7",x"26",x"3A",x"00",x"40", -- 0x1238 + x"C6",x"06",x"32",x"00",x"40",x"3E",x"80",x"32", -- 0x1240 + x"11",x"41",x"C9",x"21",x"11",x"41",x"35",x"C0", -- 0x1248 + x"3A",x"00",x"40",x"FE",x"08",x"CA",x"63",x"12", -- 0x1250 + x"3A",x"69",x"40",x"32",x"60",x"50",x"3E",x"64", -- 0x1258 + x"32",x"40",x"50",x"3A",x"69",x"40",x"32",x"A0", -- 0x1260 + x"53",x"3E",x"64",x"32",x"80",x"53",x"11",x"6B", -- 0x1268 + x"29",x"CD",x"1F",x"27",x"CD",x"FC",x"26",x"3E", -- 0x1270 + x"00",x"32",x"02",x"60",x"CD",x"2D",x"18",x"3A", -- 0x1278 + x"00",x"40",x"C6",x"0C",x"32",x"00",x"40",x"CD", -- 0x1280 + x"41",x"27",x"3A",x"8F",x"40",x"3D",x"2F",x"32", -- 0x1288 + x"1B",x"41",x"21",x"03",x"41",x"22",x"0E",x"41", -- 0x1290 + x"3E",x"18",x"32",x"12",x"41",x"3A",x"69",x"40", -- 0x1298 + x"32",x"10",x"41",x"CD",x"BF",x"12",x"CD",x"5F", -- 0x12A0 + x"27",x"AF",x"32",x"1B",x"41",x"21",x"00",x"41", -- 0x12A8 + x"22",x"0E",x"41",x"3A",x"00",x"40",x"32",x"12", -- 0x12B0 + x"41",x"3A",x"69",x"40",x"32",x"10",x"41",x"3E", -- 0x12B8 + x"10",x"32",x"0B",x"41",x"3E",x"03",x"32",x"30", -- 0x12C0 + x"41",x"3E",x"03",x"32",x"34",x"41",x"3E",x"05", -- 0x12C8 + x"32",x"29",x"41",x"3E",x"18",x"21",x"1B",x"41", -- 0x12D0 + x"AE",x"32",x"20",x"41",x"3E",x"03",x"32",x"13", -- 0x12D8 + x"41",x"3E",x"02",x"32",x"27",x"41",x"3E",x"22", -- 0x12E0 + x"32",x"18",x"41",x"3E",x"04",x"32",x"19",x"41", -- 0x12E8 + x"3E",x"03",x"32",x"1A",x"41",x"3E",x"08",x"32", -- 0x12F0 + x"1E",x"41",x"3E",x"0F",x"32",x"1F",x"41",x"3E", -- 0x12F8 + x"05",x"32",x"35",x"41",x"3E",x"25",x"32",x"36", -- 0x1300 + x"41",x"3E",x"05",x"32",x"37",x"41",x"3E",x"08", -- 0x1308 + x"32",x"24",x"41",x"3E",x"20",x"32",x"28",x"41", -- 0x1310 + x"3E",x"50",x"32",x"2B",x"41",x"3E",x"C0",x"32", -- 0x1318 + x"2F",x"41",x"3E",x"1F",x"32",x"2A",x"41",x"3E", -- 0x1320 + x"40",x"32",x"2D",x"41",x"3E",x"02",x"32",x"2E", -- 0x1328 + x"41",x"3E",x"08",x"32",x"08",x"41",x"3E",x"80", -- 0x1330 + x"32",x"0A",x"41",x"3E",x"01",x"32",x"21",x"41", -- 0x1338 + x"3A",x"00",x"70",x"CB",x"57",x"3E",x"01",x"C2", -- 0x1340 + x"4B",x"13",x"AF",x"32",x"31",x"41",x"C9",x"21", -- 0x1348 + x"31",x"41",x"34",x"3E",x"10",x"32",x"0B",x"41", -- 0x1350 + x"3E",x"08",x"32",x"29",x"41",x"3E",x"00",x"32", -- 0x1358 + x"02",x"60",x"3E",x"03",x"32",x"13",x"41",x"CD", -- 0x1360 + x"93",x"18",x"21",x"31",x"41",x"3E",x"03",x"96", -- 0x1368 + x"FE",x"01",x"D2",x"77",x"13",x"3E",x"01",x"32", -- 0x1370 + x"34",x"41",x"3A",x"00",x"40",x"C6",x"06",x"32", -- 0x1378 + x"00",x"40",x"C9",x"21",x"11",x"41",x"35",x"C0", -- 0x1380 + x"3A",x"00",x"40",x"FE",x"1A",x"3E",x"20",x"CA", -- 0x1388 + x"AB",x"13",x"CD",x"FC",x"26",x"3A",x"20",x"40", -- 0x1390 + x"A7",x"CA",x"AF",x"13",x"CD",x"5F",x"27",x"3A", -- 0x1398 + x"00",x"40",x"FE",x"1C",x"3E",x"24",x"CA",x"AB", -- 0x13A0 + x"13",x"3E",x"22",x"32",x"00",x"40",x"C9",x"CD", -- 0x13A8 + x"5F",x"27",x"21",x"8F",x"52",x"11",x"C9",x"18", -- 0x13B0 + x"3A",x"00",x"40",x"FE",x"1C",x"3E",x"1E",x"CA", -- 0x13B8 + x"C7",x"13",x"3E",x"1C",x"11",x"D4",x"18",x"32", -- 0x13C0 + x"00",x"40",x"3A",x"4D",x"41",x"E6",x"01",x"C3", -- 0x13C8 + x"33",x"14",x"C9",x"CD",x"2D",x"18",x"3E",x"00", -- 0x13D0 + x"32",x"02",x"60",x"C3",x"F4",x"13",x"3E",x"01", -- 0x13D8 + x"32",x"00",x"68",x"32",x"01",x"68",x"32",x"02", -- 0x13E0 + x"68",x"3E",x"01",x"32",x"02",x"60",x"21",x"00", -- 0x13E8 + x"00",x"22",x"14",x"41",x"3E",x"08",x"32",x"08", -- 0x13F0 + x"41",x"3A",x"00",x"40",x"C6",x"F4",x"32",x"00", -- 0x13F8 + x"40",x"C9",x"21",x"11",x"41",x"35",x"C0",x"CD", -- 0x1400 + x"FC",x"26",x"3A",x"00",x"40",x"FE",x"26",x"CA", -- 0x1408 + x"42",x"14",x"3A",x"20",x"40",x"A7",x"CA",x"42", -- 0x1410 + x"14",x"3A",x"00",x"40",x"C6",x"F4",x"32",x"00", -- 0x1418 + x"40",x"21",x"8F",x"52",x"11",x"D4",x"18",x"FE", -- 0x1420 + x"1C",x"3A",x"8F",x"40",x"CA",x"33",x"14",x"AF", -- 0x1428 + x"11",x"C9",x"18",x"32",x"06",x"70",x"32",x"07", -- 0x1430 + x"70",x"CD",x"E7",x"26",x"3E",x"80",x"32",x"11", -- 0x1438 + x"41",x"C9",x"A7",x"2A",x"22",x"40",x"ED",x"5B", -- 0x1440 + x"01",x"41",x"ED",x"52",x"DA",x"5D",x"14",x"C2", -- 0x1448 + x"68",x"14",x"3A",x"00",x"41",x"47",x"3A",x"21", -- 0x1450 + x"40",x"90",x"D2",x"68",x"14",x"ED",x"53",x"22", -- 0x1458 + x"40",x"3A",x"00",x"41",x"32",x"21",x"40",x"3F", -- 0x1460 + x"2A",x"22",x"40",x"ED",x"5B",x"04",x"41",x"ED", -- 0x1468 + x"52",x"DA",x"82",x"14",x"C2",x"8C",x"14",x"3A", -- 0x1470 + x"03",x"41",x"47",x"3A",x"21",x"40",x"90",x"D2", -- 0x1478 + x"8C",x"14",x"ED",x"53",x"22",x"40",x"3A",x"03", -- 0x1480 + x"41",x"32",x"21",x"40",x"3E",x"10",x"32",x"A0", -- 0x1488 + x"53",x"32",x"80",x"53",x"32",x"60",x"50",x"32", -- 0x1490 + x"40",x"50",x"AF",x"32",x"A6",x"41",x"32",x"A8", -- 0x1498 + x"41",x"32",x"74",x"41",x"32",x"76",x"41",x"32", -- 0x14A0 + x"78",x"41",x"32",x"7A",x"41",x"3E",x"00",x"32", -- 0x14A8 + x"00",x"40",x"C9",x"DD",x"21",x"AA",x"41",x"3A", -- 0x14B0 + x"1B",x"41",x"E6",x"FE",x"C6",x"79",x"47",x"3A", -- 0x14B8 + x"A2",x"41",x"80",x"47",x"DD",x"77",x"00",x"DD", -- 0x14C0 + x"36",x"03",x"E0",x"DD",x"36",x"01",x"18",x"DD", -- 0x14C8 + x"36",x"02",x"07",x"3E",x"10",x"32",x"FC",x"51", -- 0x14D0 + x"32",x"FD",x"51",x"32",x"1C",x"52",x"32",x"1D", -- 0x14D8 + x"52",x"DD",x"70",x"04",x"DD",x"36",x"07",x"EE", -- 0x14E0 + x"DD",x"36",x"05",x"1B",x"DD",x"36",x"06",x"07", -- 0x14E8 + x"3E",x"0A",x"32",x"78",x"40",x"C6",x"60",x"32", -- 0x14F0 + x"76",x"40",x"3E",x"10",x"32",x"77",x"40",x"3E", -- 0x14F8 + x"03",x"32",x"6E",x"40",x"3E",x"01",x"32",x"03", -- 0x1500 + x"68",x"21",x"37",x"2A",x"22",x"0C",x"40",x"21", -- 0x1508 + x"00",x"00",x"22",x"0E",x"40",x"3E",x"01",x"32", -- 0x1510 + x"02",x"40",x"3E",x"00",x"32",x"10",x"40",x"3A", -- 0x1518 + x"00",x"40",x"C6",x"06",x"32",x"00",x"40",x"CD", -- 0x1520 + x"45",x"0D",x"CD",x"4D",x"05",x"3A",x"10",x"40", -- 0x1528 + x"FE",x"01",x"C2",x"39",x"15",x"CD",x"FC",x"26", -- 0x1530 + x"C9",x"FE",x"03",x"C0",x"AF",x"32",x"03",x"68", -- 0x1538 + x"06",x"08",x"21",x"AA",x"41",x"36",x"00",x"23", -- 0x1540 + x"10",x"FB",x"3A",x"A2",x"41",x"32",x"A4",x"41", -- 0x1548 + x"3E",x"60",x"32",x"FC",x"51",x"3C",x"32",x"FD", -- 0x1550 + x"51",x"3C",x"32",x"1C",x"52",x"3C",x"32",x"1D", -- 0x1558 + x"52",x"21",x"06",x"41",x"34",x"34",x"3A",x"00", -- 0x1560 + x"40",x"C6",x"FA",x"32",x"00",x"40",x"C9",x"3E", -- 0x1568 + x"08",x"32",x"0B",x"41",x"32",x"29",x"41",x"21", -- 0x1570 + x"00",x"00",x"22",x"72",x"40",x"3E",x"01",x"32", -- 0x1578 + x"02",x"60",x"3E",x"01",x"32",x"13",x"41",x"CD", -- 0x1580 + x"93",x"18",x"3A",x"00",x"40",x"FE",x"04",x"C8", -- 0x1588 + x"3E",x"01",x"32",x"00",x"68",x"32",x"01",x"68", -- 0x1590 + x"32",x"02",x"68",x"3A",x"00",x"40",x"C6",x"06", -- 0x1598 + x"32",x"00",x"40",x"C9",x"3E",x"10",x"32",x"0B", -- 0x15A0 + x"41",x"3A",x"31",x"41",x"CB",x"27",x"C6",x"03", -- 0x15A8 + x"FE",x"07",x"DA",x"B7",x"15",x"3E",x"06",x"32", -- 0x15B0 + x"29",x"41",x"3E",x"20",x"32",x"28",x"41",x"3E", -- 0x15B8 + x"01",x"32",x"92",x"40",x"3E",x"60",x"32",x"93", -- 0x15C0 + x"40",x"CD",x"93",x"18",x"3A",x"31",x"41",x"3C", -- 0x15C8 + x"3C",x"FE",x"06",x"DA",x"D8",x"15",x"3E",x"05", -- 0x15D0 + x"32",x"27",x"41",x"3A",x"31",x"41",x"A7",x"CA", -- 0x15D8 + x"E6",x"15",x"AF",x"32",x"2F",x"41",x"3E",x"00", -- 0x15E0 + x"32",x"9D",x"40",x"3E",x"01",x"32",x"00",x"68", -- 0x15E8 + x"32",x"01",x"68",x"32",x"02",x"68",x"3A",x"00", -- 0x15F0 + x"40",x"C6",x"06",x"32",x"00",x"40",x"C9",x"3E", -- 0x15F8 + x"08",x"32",x"08",x"41",x"3E",x"01",x"32",x"92", -- 0x1600 + x"40",x"3E",x"60",x"32",x"93",x"40",x"CD",x"2D", -- 0x1608 + x"18",x"3E",x"00",x"32",x"9D",x"40",x"3E",x"01", -- 0x1610 + x"32",x"00",x"68",x"32",x"01",x"68",x"32",x"02", -- 0x1618 + x"68",x"3E",x"00",x"32",x"02",x"60",x"3A",x"00", -- 0x1620 + x"40",x"C6",x"F4",x"32",x"00",x"40",x"C9",x"CD", -- 0x1628 + x"08",x"04",x"CD",x"84",x"28",x"CD",x"4D",x"05", -- 0x1630 + x"CD",x"91",x"20",x"CD",x"28",x"22",x"CD",x"A0", -- 0x1638 + x"0E",x"CD",x"99",x"22",x"CD",x"48",x"23",x"CD", -- 0x1640 + x"FA",x"24",x"3A",x"08",x"41",x"FE",x"0E",x"CA", -- 0x1648 + x"AD",x"11",x"3A",x"0B",x"41",x"A7",x"C0",x"3A", -- 0x1650 + x"1E",x"40",x"A7",x"C0",x"3A",x"9D",x"40",x"FE", -- 0x1658 + x"04",x"C0",x"CD",x"B1",x"26",x"3A",x"00",x"40", -- 0x1660 + x"C6",x"FA",x"32",x"00",x"40",x"3E",x"00",x"32", -- 0x1668 + x"06",x"41",x"C9",x"3A",x"00",x"40",x"C6",x"FA", -- 0x1670 + x"32",x"00",x"40",x"3E",x"00",x"32",x"06",x"41", -- 0x1678 + x"C9",x"DD",x"21",x"AA",x"41",x"3A",x"1B",x"41", -- 0x1680 + x"E6",x"FE",x"C6",x"79",x"47",x"3A",x"A2",x"41", -- 0x1688 + x"80",x"DD",x"77",x"00",x"DD",x"36",x"03",x"E0", -- 0x1690 + x"DD",x"36",x"02",x"07",x"DD",x"36",x"01",x"18", -- 0x1698 + x"3E",x"10",x"32",x"FC",x"51",x"32",x"FD",x"51", -- 0x16A0 + x"32",x"1C",x"52",x"32",x"1D",x"52",x"3E",x"11", -- 0x16A8 + x"32",x"78",x"40",x"32",x"76",x"40",x"3E",x"10", -- 0x16B0 + x"32",x"77",x"40",x"AF",x"32",x"7E",x"40",x"32", -- 0x16B8 + x"7B",x"40",x"32",x"80",x"40",x"3E",x"0A",x"32", -- 0x16C0 + x"7C",x"40",x"32",x"7D",x"40",x"3E",x"10",x"32", -- 0x16C8 + x"7F",x"40",x"3E",x"00",x"32",x"02",x"60",x"3E", -- 0x16D0 + x"02",x"32",x"08",x"41",x"3E",x"00",x"32",x"91", -- 0x16D8 + x"40",x"3E",x"00",x"32",x"17",x"41",x"AF",x"32", -- 0x16E0 + x"A6",x"41",x"32",x"A8",x"41",x"3E",x"00",x"32", -- 0x16E8 + x"1C",x"41",x"CD",x"79",x"18",x"21",x"31",x"41", -- 0x16F0 + x"3E",x"22",x"96",x"FE",x"1E",x"D2",x"02",x"17", -- 0x16F8 + x"3E",x"1E",x"32",x"18",x"41",x"21",x"19",x"41", -- 0x1700 + x"3A",x"31",x"41",x"C6",x"02",x"E6",x"03",x"CA", -- 0x1708 + x"13",x"17",x"34",x"21",x"1A",x"41",x"3A",x"31", -- 0x1710 + x"41",x"C6",x"02",x"E6",x"04",x"CA",x"2C",x"17", -- 0x1718 + x"7E",x"3D",x"FE",x"01",x"DA",x"2C",x"17",x"35", -- 0x1720 + x"21",x"19",x"41",x"35",x"3A",x"31",x"41",x"CB", -- 0x1728 + x"27",x"47",x"3E",x"08",x"90",x"DA",x"42",x"17", -- 0x1730 + x"FE",x"04",x"D2",x"3F",x"17",x"3E",x"04",x"32", -- 0x1738 + x"1E",x"41",x"3A",x"00",x"40",x"C6",x"06",x"32", -- 0x1740 + x"00",x"40",x"C9",x"3E",x"08",x"32",x"08",x"41", -- 0x1748 + x"CD",x"2D",x"18",x"3E",x"01",x"32",x"91",x"40", -- 0x1750 + x"3E",x"20",x"32",x"90",x"40",x"3E",x"02",x"32", -- 0x1758 + x"17",x"41",x"3E",x"00",x"32",x"02",x"60",x"CD", -- 0x1760 + x"79",x"18",x"3A",x"00",x"40",x"C6",x"F4",x"32", -- 0x1768 + x"00",x"40",x"C9",x"CD",x"08",x"04",x"CD",x"84", -- 0x1770 + x"28",x"CD",x"4D",x"05",x"3A",x"08",x"41",x"FE", -- 0x1778 + x"0E",x"CA",x"AD",x"11",x"CD",x"FE",x"0F",x"CD", -- 0x1780 + x"97",x"07",x"CD",x"EB",x"0D",x"CD",x"A0",x"0E", -- 0x1788 + x"3A",x"08",x"41",x"FE",x"06",x"C0",x"3A",x"0B", -- 0x1790 + x"41",x"A7",x"C0",x"3A",x"1E",x"40",x"A7",x"C0", -- 0x1798 + x"3E",x"01",x"32",x"7B",x"40",x"3A",x"0D",x"41", -- 0x17A0 + x"A7",x"C0",x"AF",x"32",x"00",x"68",x"32",x"01", -- 0x17A8 + x"68",x"32",x"02",x"68",x"3E",x"06",x"32",x"06", -- 0x17B0 + x"41",x"3A",x"00",x"40",x"C6",x"FA",x"32",x"00", -- 0x17B8 + x"40",x"C9",x"CD",x"26",x"1C",x"CD",x"49",x"19", -- 0x17C0 + x"CD",x"99",x"1F",x"CD",x"8C",x"1D",x"CD",x"62", -- 0x17C8 + x"1E",x"CD",x"AF",x"1D",x"3A",x"08",x"41",x"FE", -- 0x17D0 + x"0E",x"C2",x"E8",x"17",x"CD",x"FC",x"26",x"CD", -- 0x17D8 + x"2D",x"18",x"CD",x"54",x"18",x"C3",x"AD",x"11", -- 0x17E0 + x"FE",x"12",x"C0",x"CD",x"FC",x"26",x"CD",x"2D", -- 0x17E8 + x"18",x"3A",x"1B",x"41",x"E6",x"FE",x"C6",x"79", -- 0x17F0 + x"47",x"3A",x"AA",x"41",x"90",x"32",x"A2",x"41", -- 0x17F8 + x"32",x"A4",x"41",x"CD",x"B1",x"26",x"3E",x"60", -- 0x1800 + x"32",x"FC",x"51",x"3C",x"32",x"FD",x"51",x"3C", -- 0x1808 + x"32",x"1C",x"52",x"3C",x"32",x"1D",x"52",x"3E", -- 0x1810 + x"06",x"32",x"08",x"41",x"CD",x"54",x"18",x"3A", -- 0x1818 + x"00",x"40",x"C6",x"FA",x"32",x"00",x"40",x"3E", -- 0x1820 + x"08",x"32",x"06",x"41",x"C9",x"3E",x"04",x"32", -- 0x1828 + x"A7",x"41",x"32",x"A9",x"41",x"3E",x"02",x"32", -- 0x1830 + x"79",x"41",x"21",x"FE",x"53",x"11",x"DF",x"FF", -- 0x1838 + x"06",x"20",x"3E",x"90",x"77",x"23",x"3C",x"77", -- 0x1840 + x"3C",x"FE",x"9A",x"C2",x"50",x"18",x"3E",x"90", -- 0x1848 + x"19",x"10",x"F1",x"C9",x"AF",x"21",x"6E",x"41", -- 0x1850 + x"06",x"34",x"77",x"23",x"10",x"FC",x"3E",x"02", -- 0x1858 + x"32",x"79",x"41",x"32",x"9D",x"41",x"07",x"32", -- 0x1860 + x"9B",x"41",x"3E",x"05",x"32",x"A1",x"41",x"21", -- 0x1868 + x"80",x"52",x"11",x"F5",x"03",x"CD",x"E7",x"26", -- 0x1870 + x"C9",x"21",x"80",x"52",x"11",x"F0",x"18",x"CD", -- 0x1878 + x"E7",x"26",x"21",x"60",x"51",x"22",x"97",x"40", -- 0x1880 + x"3E",x"05",x"32",x"95",x"40",x"3E",x"35",x"32", -- 0x1888 + x"96",x"40",x"C9",x"3A",x"31",x"41",x"C6",x"03", -- 0x1890 + x"FE",x"06",x"DA",x"9F",x"18",x"3E",x"05",x"32", -- 0x1898 + x"27",x"41",x"3A",x"31",x"41",x"3C",x"CB",x"27", -- 0x18A0 + x"32",x"30",x"41",x"3A",x"31",x"41",x"2F",x"21", -- 0x18A8 + x"FF",x"FF",x"0F",x"CB",x"1C",x"0F",x"CB",x"1C", -- 0x18B0 + x"22",x"32",x"41",x"C9",x"C9",x"C9",x"C9",x"C9", -- 0x18B8 + x"C9",x"C9",x"50",x"49",x"53",x"43",x"45",x"53", -- 0x18C0 + x"FF",x"50",x"4C",x"41",x"59",x"45",x"52",x"20", -- 0x18C8 + x"4F",x"4E",x"45",x"FF",x"50",x"4C",x"41",x"59", -- 0x18D0 + x"45",x"52",x"20",x"54",x"57",x"4F",x"FF",x"47", -- 0x18D8 + x"41",x"4D",x"45",x"20",x"20",x"4F",x"56",x"45", -- 0x18E0 + x"52",x"FF",x"20",x"20",x"20",x"20",x"30",x"FF", -- 0x18E8 + x"46",x"55",x"45",x"4C",x"40",x"99",x"99",x"99", -- 0x18F0 + x"99",x"99",x"FF",x"3A",x"3B",x"3C",x"3D",x"3E", -- 0x18F8 + x"3F",x"5C",x"5D",x"5E",x"5F",x"60",x"61",x"62", -- 0x1900 + x"63",x"64",x"65",x"66",x"67",x"68",x"69",x"6A", -- 0x1908 + x"FF",x"6B",x"6C",x"6D",x"6E",x"6F",x"70",x"71", -- 0x1910 + x"72",x"73",x"BF",x"C0",x"C1",x"C2",x"C3",x"C4", -- 0x1918 + x"C5",x"C6",x"C7",x"C8",x"C9",x"CA",x"FF",x"CB", -- 0x1920 + x"CC",x"CD",x"CE",x"20",x"CF",x"D0",x"D1",x"D2", -- 0x1928 + x"D3",x"D4",x"D5",x"D6",x"20",x"D7",x"D8",x"D9", -- 0x1930 + x"DA",x"DB",x"DC",x"FF",x"DD",x"DE",x"DF",x"E0", -- 0x1938 + x"20",x"20",x"E1",x"20",x"20",x"20",x"E2",x"E3", -- 0x1940 + x"FF",x"DD",x"21",x"AA",x"41",x"3A",x"08",x"41", -- 0x1948 + x"FE",x"00",x"CA",x"47",x"1A",x"FE",x"02",x"CA", -- 0x1950 + x"1B",x"1A",x"FE",x"04",x"CA",x"1B",x"1B",x"FE", -- 0x1958 + x"08",x"CA",x"74",x"19",x"FE",x"0C",x"CA",x"9C", -- 0x1960 + x"19",x"FE",x"0A",x"CA",x"D8",x"19",x"FE",x"10", -- 0x1968 + x"CA",x"0E",x"1A",x"C9",x"21",x"0A",x"41",x"35", -- 0x1970 + x"C0",x"DD",x"36",x"00",x"80",x"DD",x"36",x"03", -- 0x1978 + x"10",x"DD",x"36",x"01",x"18",x"DD",x"36",x"02", -- 0x1980 + x"07",x"3E",x"11",x"32",x"76",x"40",x"32",x"78", -- 0x1988 + x"40",x"3E",x"10",x"32",x"77",x"40",x"3E",x"00", -- 0x1990 + x"32",x"08",x"41",x"C9",x"AF",x"32",x"03",x"68", -- 0x1998 + x"11",x"1D",x"2A",x"CD",x"1F",x"27",x"CD",x"86", -- 0x19A0 + x"20",x"DD",x"7E",x"00",x"DD",x"77",x"04",x"DD", -- 0x19A8 + x"7E",x"03",x"C6",x"08",x"DD",x"77",x"07",x"D6", -- 0x19B0 + x"10",x"DD",x"77",x"03",x"3E",x"38",x"DD",x"77", -- 0x19B8 + x"01",x"3C",x"DD",x"77",x"05",x"DD",x"36",x"02", -- 0x19C0 + x"07",x"DD",x"36",x"06",x"07",x"3E",x"0A",x"32", -- 0x19C8 + x"79",x"40",x"3E",x"0A",x"32",x"08",x"41",x"C9", -- 0x19D0 + x"21",x"79",x"40",x"35",x"C0",x"36",x"0A",x"DD", -- 0x19D8 + x"7E",x"01",x"C6",x"02",x"FE",x"40",x"CA",x"F1", -- 0x19E0 + x"19",x"DD",x"77",x"01",x"3C",x"DD",x"77",x"05", -- 0x19E8 + x"C9",x"21",x"AA",x"41",x"06",x"08",x"AF",x"77", -- 0x19F0 + x"23",x"10",x"FC",x"3E",x"04",x"32",x"A7",x"41", -- 0x19F8 + x"32",x"A9",x"41",x"3E",x"80",x"32",x"0A",x"41", -- 0x1A00 + x"3E",x"10",x"32",x"08",x"41",x"C9",x"21",x"0A", -- 0x1A08 + x"41",x"35",x"C0",x"36",x"80",x"3E",x"0E",x"32", -- 0x1A10 + x"08",x"41",x"C9",x"DD",x"7E",x"03",x"A7",x"C2", -- 0x1A18 + x"29",x"1B",x"CD",x"2D",x"18",x"3E",x"01",x"32", -- 0x1A20 + x"91",x"40",x"3E",x"20",x"32",x"90",x"40",x"3E", -- 0x1A28 + x"02",x"32",x"1C",x"41",x"3A",x"1E",x"41",x"32", -- 0x1A30 + x"1D",x"41",x"3E",x"02",x"32",x"17",x"41",x"3E", -- 0x1A38 + x"00",x"32",x"08",x"41",x"C3",x"29",x"1B",x"DD", -- 0x1A40 + x"7E",x"03",x"FE",x"E0",x"C2",x"29",x"1B",x"DD", -- 0x1A48 + x"46",x"10",x"DD",x"7E",x"11",x"FE",x"27",x"CA", -- 0x1A50 + x"6D",x"1A",x"FE",x"29",x"CA",x"7B",x"1A",x"DD", -- 0x1A58 + x"7E",x"00",x"90",x"D6",x"05",x"FE",x"0C",x"DA", -- 0x1A60 + x"94",x"1A",x"C3",x"86",x"1A",x"DD",x"7E",x"00", -- 0x1A68 + x"90",x"D6",x"02",x"FE",x"0F",x"DA",x"94",x"1A", -- 0x1A70 + x"C3",x"86",x"1A",x"DD",x"7E",x"00",x"90",x"D6", -- 0x1A78 + x"04",x"FE",x"0D",x"DA",x"94",x"1A",x"3E",x"0C", -- 0x1A80 + x"32",x"08",x"41",x"3E",x"07",x"32",x"A7",x"41", -- 0x1A88 + x"32",x"A9",x"41",x"C9",x"3E",x"00",x"32",x"81", -- 0x1A90 + x"40",x"3E",x"04",x"32",x"08",x"41",x"3E",x"00", -- 0x1A98 + x"32",x"1C",x"41",x"21",x"9A",x"40",x"0E",x"00", -- 0x1AA0 + x"71",x"2B",x"71",x"ED",x"5B",x"97",x"40",x"1A", -- 0x1AA8 + x"D6",x"64",x"DA",x"C7",x"1A",x"E6",x"07",x"5F", -- 0x1AB0 + x"3A",x"95",x"40",x"CB",x"27",x"CB",x"27",x"83", -- 0x1AB8 + x"3C",x"11",x"35",x"41",x"CD",x"F2",x"1A",x"DD", -- 0x1AC0 + x"7E",x"15",x"D6",x"26",x"11",x"36",x"41",x"CD", -- 0x1AC8 + x"F2",x"1A",x"3A",x"1E",x"41",x"2F",x"0F",x"0F", -- 0x1AD0 + x"E6",x"07",x"C6",x"04",x"11",x"37",x"41",x"CD", -- 0x1AD8 + x"F2",x"1A",x"CD",x"4A",x"28",x"3E",x"03",x"32", -- 0x1AE0 + x"91",x"40",x"3E",x"04",x"32",x"90",x"40",x"C3", -- 0x1AE8 + x"E9",x"1F",x"01",x"00",x"00",x"08",x"08",x"3D", -- 0x1AF0 + x"CA",x"08",x"1B",x"08",x"1A",x"81",x"27",x"4F", -- 0x1AF8 + x"78",x"CE",x"00",x"27",x"47",x"C3",x"F6",x"1A", -- 0x1B00 + x"79",x"CD",x"2B",x"28",x"78",x"CD",x"18",x"28", -- 0x1B08 + x"79",x"86",x"27",x"77",x"23",x"78",x"8E",x"27", -- 0x1B10 + x"77",x"2B",x"C9",x"21",x"81",x"40",x"35",x"C0", -- 0x1B18 + x"CD",x"86",x"20",x"3E",x"12",x"32",x"08",x"41", -- 0x1B20 + x"C9",x"3A",x"05",x"40",x"E6",x"0C",x"CA",x"85", -- 0x1B28 + x"1B",x"FE",x"0C",x"CA",x"85",x"1B",x"CB",x"57", -- 0x1B30 + x"21",x"7B",x"40",x"C2",x"53",x"1B",x"34",x"7E", -- 0x1B38 + x"FE",x"08",x"DA",x"89",x"1B",x"36",x"00",x"23", -- 0x1B40 + x"3A",x"7E",x"40",x"FE",x"01",x"CA",x"67",x"1B", -- 0x1B48 + x"C3",x"7A",x"1B",x"35",x"7E",x"ED",x"44",x"FE", -- 0x1B50 + x"08",x"DA",x"89",x"1B",x"36",x"00",x"23",x"3A", -- 0x1B58 + x"7E",x"40",x"FE",x"01",x"CA",x"7A",x"1B",x"34", -- 0x1B60 + x"7E",x"FE",x"0B",x"DA",x"89",x"1B",x"35",x"3A", -- 0x1B68 + x"7E",x"40",x"EE",x"01",x"32",x"7E",x"40",x"C3", -- 0x1B70 + x"89",x"1B",x"35",x"7E",x"FE",x"01",x"D2",x"89", -- 0x1B78 + x"1B",x"34",x"C3",x"89",x"1B",x"AF",x"32",x"7B", -- 0x1B80 + x"40",x"21",x"7D",x"40",x"35",x"C2",x"C4",x"1B", -- 0x1B88 + x"3A",x"7E",x"40",x"FE",x"01",x"DD",x"7E",x"00", -- 0x1B90 + x"CA",x"A6",x"1B",x"FE",x"E1",x"CA",x"AB",x"1B", -- 0x1B98 + x"DD",x"34",x"00",x"C3",x"BE",x"1B",x"FE",x"0F", -- 0x1BA0 + x"C2",x"BB",x"1B",x"3E",x"0A",x"32",x"7C",x"40", -- 0x1BA8 + x"3A",x"7E",x"40",x"EE",x"01",x"32",x"7E",x"40", -- 0x1BB0 + x"C3",x"BE",x"1B",x"DD",x"35",x"00",x"3A",x"7C", -- 0x1BB8 + x"40",x"32",x"7D",x"40",x"21",x"7F",x"40",x"35", -- 0x1BC0 + x"C2",x"D9",x"1B",x"36",x"10",x"3A",x"7C",x"40", -- 0x1BC8 + x"FE",x"0A",x"CA",x"D9",x"1B",x"3C",x"32",x"7C", -- 0x1BD0 + x"40",x"21",x"76",x"40",x"35",x"C2",x"FD",x"1B", -- 0x1BD8 + x"3A",x"78",x"40",x"77",x"3A",x"80",x"40",x"FE", -- 0x1BE0 + x"01",x"CA",x"FA",x"1B",x"DD",x"7E",x"03",x"FE", -- 0x1BE8 + x"10",x"CA",x"FD",x"1B",x"DD",x"35",x"03",x"C3", -- 0x1BF0 + x"FD",x"1B",x"DD",x"34",x"03",x"23",x"35",x"C0", -- 0x1BF8 + x"36",x"0F",x"3A",x"80",x"40",x"FE",x"01",x"CA", -- 0x1C00 + x"1C",x"1C",x"23",x"34",x"34",x"7E",x"FE",x"12", -- 0x1C08 + x"D8",x"35",x"35",x"3A",x"80",x"40",x"EE",x"01", -- 0x1C10 + x"32",x"80",x"40",x"C9",x"23",x"35",x"35",x"7E", -- 0x1C18 + x"FE",x"02",x"D0",x"34",x"34",x"C9",x"3A",x"08", -- 0x1C20 + x"41",x"FE",x"03",x"D0",x"DD",x"21",x"AA",x"41", -- 0x1C28 + x"DD",x"7E",x"03",x"CB",x"3F",x"CB",x"3F",x"E6", -- 0x1C30 + x"3E",x"5F",x"CB",x"3F",x"16",x"00",x"FD",x"21", -- 0x1C38 + x"6A",x"41",x"FD",x"19",x"5F",x"16",x"50",x"ED", -- 0x1C40 + x"53",x"85",x"40",x"DD",x"7E",x"03",x"E6",x"07", -- 0x1C48 + x"3C",x"32",x"82",x"40",x"3E",x"03",x"32",x"87", -- 0x1C50 + x"40",x"DD",x"7E",x"00",x"C6",x"02",x"FD",x"96", -- 0x1C58 + x"00",x"06",x"00",x"CB",x"27",x"CB",x"10",x"CB", -- 0x1C60 + x"27",x"CB",x"10",x"E6",x"E0",x"4F",x"21",x"E0", -- 0x1C68 + x"03",x"ED",x"42",x"7C",x"FE",x"04",x"DA",x"7E", -- 0x1C70 + x"1C",x"01",x"0E",x"03",x"ED",x"42",x"ED",x"5B", -- 0x1C78 + x"85",x"40",x"19",x"22",x"89",x"40",x"DD",x"7E", -- 0x1C80 + x"00",x"FD",x"96",x"00",x"ED",x"44",x"C6",x"05", -- 0x1C88 + x"E6",x"07",x"CB",x"27",x"4F",x"06",x"00",x"21", -- 0x1C90 + x"DA",x"2B",x"09",x"22",x"83",x"40",x"3E",x"03", -- 0x1C98 + x"32",x"88",x"40",x"2A",x"89",x"40",x"7E",x"D6", -- 0x1CA0 + x"0A",x"FE",x"06",x"D2",x"42",x"1D",x"CB",x"27", -- 0x1CA8 + x"4F",x"06",x"00",x"21",x"18",x"2C",x"09",x"5E", -- 0x1CB0 + x"23",x"56",x"2A",x"83",x"40",x"3E",x"08",x"47", -- 0x1CB8 + x"32",x"8B",x"40",x"3A",x"87",x"40",x"FE",x"03", -- 0x1CC0 + x"CA",x"FC",x"1C",x"FE",x"02",x"CA",x"1B",x"1D", -- 0x1CC8 + x"23",x"3A",x"82",x"40",x"4F",x"7E",x"06",x"00", -- 0x1CD0 + x"0D",x"CA",x"E3",x"1C",x"CB",x"3F",x"CB",x"18", -- 0x1CD8 + x"C3",x"D8",x"1C",x"EB",x"78",x"AE",x"A0",x"B8", -- 0x1CE0 + x"C2",x"81",x"1D",x"EB",x"23",x"23",x"13",x"3A", -- 0x1CE8 + x"8B",x"40",x"3D",x"32",x"8B",x"40",x"C2",x"D1", -- 0x1CF0 + x"1C",x"C3",x"42",x"1D",x"3A",x"82",x"40",x"4F", -- 0x1CF8 + x"7E",x"0D",x"CA",x"0A",x"1D",x"CB",x"3F",x"C3", -- 0x1D00 + x"01",x"1D",x"EB",x"4F",x"AE",x"A1",x"B9",x"C2", -- 0x1D08 + x"81",x"1D",x"EB",x"23",x"23",x"13",x"10",x"E4", -- 0x1D10 + x"C3",x"42",x"1D",x"3A",x"82",x"40",x"4F",x"7E", -- 0x1D18 + x"23",x"46",x"0D",x"CA",x"2D",x"1D",x"CB",x"3F", -- 0x1D20 + x"CB",x"18",x"C3",x"22",x"1D",x"EB",x"78",x"AE", -- 0x1D28 + x"A0",x"B8",x"C2",x"81",x"1D",x"EB",x"23",x"13", -- 0x1D30 + x"3A",x"8B",x"40",x"3D",x"32",x"8B",x"40",x"C2", -- 0x1D38 + x"1B",x"1D",x"21",x"88",x"40",x"35",x"CA",x"71", -- 0x1D40 + x"1D",x"2A",x"83",x"40",x"01",x"10",x"00",x"09", -- 0x1D48 + x"22",x"83",x"40",x"2A",x"89",x"40",x"7D",x"E6", -- 0x1D50 + x"E0",x"6F",x"7C",x"E6",x"0F",x"B5",x"2A",x"89", -- 0x1D58 + x"40",x"01",x"E0",x"FF",x"C2",x"6A",x"1D",x"01", -- 0x1D60 + x"E0",x"03",x"09",x"22",x"89",x"40",x"C3",x"A6", -- 0x1D68 + x"1C",x"21",x"87",x"40",x"35",x"C8",x"21",x"85", -- 0x1D70 + x"40",x"34",x"FD",x"23",x"FD",x"23",x"C3",x"59", -- 0x1D78 + x"1C",x"2A",x"89",x"40",x"36",x"10",x"3E",x"0C", -- 0x1D80 + x"32",x"08",x"41",x"C9",x"3A",x"1C",x"41",x"FE", -- 0x1D88 + x"02",x"C0",x"21",x"1D",x"41",x"35",x"C0",x"3A", -- 0x1D90 + x"1E",x"41",x"77",x"21",x"A6",x"41",x"34",x"23", -- 0x1D98 + x"23",x"34",x"3A",x"91",x"40",x"FE",x"02",x"C0", -- 0x1DA0 + x"DD",x"34",x"10",x"DD",x"34",x"14",x"C9",x"DD", -- 0x1DA8 + x"21",x"AA",x"41",x"3A",x"91",x"40",x"FE",x"01", -- 0x1DB0 + x"CA",x"21",x"1E",x"FE",x"02",x"CA",x"15",x"1E", -- 0x1DB8 + x"FE",x"03",x"CA",x"FA",x"1D",x"FE",x"04",x"C0", -- 0x1DC0 + x"21",x"90",x"40",x"35",x"C0",x"36",x"04",x"21", -- 0x1DC8 + x"20",x"52",x"11",x"9A",x"40",x"01",x"E0",x"FF", -- 0x1DD0 + x"1A",x"E6",x"0F",x"CA",x"DF",x"1D",x"77",x"09", -- 0x1DD8 + x"1B",x"1A",x"0F",x"0F",x"0F",x"0F",x"E6",x"0F", -- 0x1DE0 + x"00",x"00",x"00",x"77",x"09",x"1A",x"E6",x"0F", -- 0x1DE8 + x"77",x"09",x"36",x"00",x"3E",x"03",x"32",x"91", -- 0x1DF0 + x"40",x"C9",x"21",x"90",x"40",x"35",x"C0",x"36", -- 0x1DF8 + x"04",x"21",x"80",x"52",x"11",x"E0",x"FF",x"06", -- 0x1E00 + x"0A",x"3E",x"10",x"77",x"19",x"10",x"FC",x"3E", -- 0x1E08 + x"04",x"32",x"91",x"40",x"C9",x"DD",x"7E",x"10", -- 0x1E10 + x"FE",x"FF",x"C0",x"3E",x"01",x"32",x"91",x"40", -- 0x1E18 + x"C9",x"21",x"90",x"40",x"35",x"C0",x"CD",x"09", -- 0x1E20 + x"28",x"47",x"3A",x"1F",x"41",x"A0",x"3C",x"77", -- 0x1E28 + x"AF",x"DD",x"77",x"10",x"3E",x"10",x"DD",x"77", -- 0x1E30 + x"14",x"DD",x"36",x"12",x"06",x"DD",x"36",x"16", -- 0x1E38 + x"06",x"DD",x"36",x"13",x"F0",x"DD",x"36",x"17", -- 0x1E40 + x"F0",x"CD",x"09",x"28",x"E6",x"06",x"C2",x"53", -- 0x1E48 + x"1E",x"3C",x"3C",x"C6",x"25",x"DD",x"77",x"11", -- 0x1E50 + x"3C",x"DD",x"77",x"15",x"3E",x"02",x"32",x"91", -- 0x1E58 + x"40",x"C9",x"3A",x"17",x"41",x"FE",x"02",x"CA", -- 0x1E60 + x"70",x"1E",x"FE",x"04",x"CA",x"0E",x"1F",x"C9", -- 0x1E68 + x"DD",x"21",x"EA",x"41",x"FD",x"21",x"A0",x"41", -- 0x1E70 + x"D9",x"11",x"1B",x"50",x"D9",x"06",x"1A",x"3A", -- 0x1E78 + x"1A",x"41",x"4F",x"CD",x"09",x"28",x"E6",x"01", -- 0x1E80 + x"DD",x"77",x"00",x"3A",x"18",x"41",x"90",x"CB", -- 0x1E88 + x"3F",x"DD",x"77",x"02",x"DD",x"77",x"03",x"CD", -- 0x1E90 + x"09",x"28",x"E6",x"07",x"3C",x"3C",x"DD",x"77", -- 0x1E98 + x"05",x"DD",x"36",x"01",x"00",x"DD",x"36",x"04", -- 0x1EA0 + x"00",x"0D",x"C2",x"EE",x"1E",x"CD",x"09",x"28", -- 0x1EA8 + x"E6",x"01",x"4F",x"3A",x"19",x"41",x"81",x"DD", -- 0x1EB0 + x"77",x"04",x"3A",x"1A",x"41",x"4F",x"78",x"FE", -- 0x1EB8 + x"05",x"DA",x"EE",x"1E",x"D9",x"DD",x"46",x"04", -- 0x1EC0 + x"DD",x"70",x"01",x"26",x"00",x"CD",x"09",x"28", -- 0x1EC8 + x"CB",x"27",x"CB",x"14",x"CB",x"27",x"CB",x"14", -- 0x1ED0 + x"E6",x"E0",x"6F",x"19",x"CD",x"09",x"28",x"E6", -- 0x1ED8 + x"07",x"C6",x"0A",x"FE",x"10",x"DA",x"EA",x"1E", -- 0x1EE0 + x"D6",x"02",x"77",x"10",x"DE",x"D9",x"CD",x"09", -- 0x1EE8 + x"28",x"FD",x"77",x"00",x"FD",x"36",x"01",x"06", -- 0x1EF0 + x"FD",x"2B",x"FD",x"2B",x"11",x"06",x"00",x"DD", -- 0x1EF8 + x"19",x"D9",x"1B",x"D9",x"05",x"C2",x"83",x"1E", -- 0x1F00 + x"3E",x"04",x"32",x"17",x"41",x"C9",x"DD",x"21", -- 0x1F08 + x"EA",x"41",x"FD",x"21",x"A0",x"41",x"11",x"1B", -- 0x1F10 + x"50",x"62",x"6B",x"DD",x"35",x"03",x"C2",x"88", -- 0x1F18 + x"1F",x"DD",x"7E",x"02",x"DD",x"77",x"03",x"FD", -- 0x1F20 + x"34",x"00",x"DD",x"CB",x"00",x"46",x"CA",x"37", -- 0x1F28 + x"1F",x"FD",x"35",x"00",x"FD",x"35",x"00",x"FD", -- 0x1F30 + x"7E",x"00",x"E6",x"07",x"C2",x"88",x"1F",x"06", -- 0x1F38 + x"00",x"FD",x"7E",x"00",x"CB",x"27",x"CB",x"10", -- 0x1F40 + x"CB",x"27",x"CB",x"10",x"E6",x"E0",x"4F",x"09", -- 0x1F48 + x"7E",x"36",x"10",x"FE",x"10",x"CA",x"5B",x"1F", -- 0x1F50 + x"DD",x"35",x"01",x"DD",x"7E",x"01",x"DD",x"BE", -- 0x1F58 + x"04",x"D2",x"88",x"1F",x"DD",x"35",x"05",x"C2", -- 0x1F60 + x"88",x"1F",x"CD",x"09",x"28",x"E6",x"07",x"3C", -- 0x1F68 + x"DD",x"77",x"05",x"CD",x"09",x"28",x"0F",x"0F", -- 0x1F70 + x"0F",x"E6",x"07",x"C6",x"0A",x"FE",x"10",x"DA", -- 0x1F78 + x"84",x"1F",x"D6",x"02",x"77",x"DD",x"34",x"01", -- 0x1F80 + x"FD",x"2B",x"FD",x"2B",x"01",x"06",x"00",x"DD", -- 0x1F88 + x"09",x"1B",x"7B",x"FE",x"01",x"C2",x"19",x"1F", -- 0x1F90 + x"C9",x"3A",x"08",x"41",x"FE",x"00",x"C0",x"DD", -- 0x1F98 + x"21",x"AA",x"41",x"DD",x"7E",x"03",x"FE",x"10", -- 0x1FA0 + x"D8",x"DD",x"7E",x"05",x"A7",x"C2",x"E1",x"1F", -- 0x1FA8 + x"3A",x"95",x"40",x"A7",x"C8",x"3A",x"05",x"40", -- 0x1FB0 + x"CB",x"67",x"C8",x"3E",x"05",x"32",x"7A",x"40", -- 0x1FB8 + x"DD",x"36",x"05",x"1B",x"DD",x"36",x"06",x"07", -- 0x1FC0 + x"3E",x"03",x"32",x"6E",x"40",x"DD",x"7E",x"00", -- 0x1FC8 + x"DD",x"77",x"04",x"DD",x"7E",x"03",x"C6",x"0E", -- 0x1FD0 + x"DD",x"77",x"07",x"3E",x"01",x"32",x"03",x"68", -- 0x1FD8 + x"C9",x"3A",x"05",x"40",x"CB",x"67",x"C2",x"F7", -- 0x1FE0 + x"1F",x"21",x"AE",x"41",x"06",x"04",x"AF",x"77", -- 0x1FE8 + x"23",x"10",x"FC",x"32",x"03",x"68",x"C9",x"21", -- 0x1FF0 + x"96",x"40",x"35",x"C2",x"36",x"20",x"36",x"35", -- 0x1FF8 + x"2A",x"97",x"40",x"7E",x"3D",x"FE",x"64",x"C2", -- 0x2000 + x"35",x"20",x"21",x"95",x"40",x"35",x"C2",x"1D", -- 0x2008 + x"20",x"21",x"97",x"29",x"22",x"0C",x"40",x"22", -- 0x2010 + x"0E",x"40",x"C3",x"E9",x"1F",x"7E",x"FE",x"02", -- 0x2018 + x"C2",x"29",x"20",x"11",x"31",x"2A",x"CD",x"1F", -- 0x2020 + x"27",x"2A",x"97",x"40",x"01",x"20",x"00",x"09", -- 0x2028 + x"22",x"97",x"40",x"3E",x"68",x"77",x"DD",x"7E", -- 0x2030 + x"00",x"DD",x"77",x"04",x"DD",x"7E",x"03",x"C6", -- 0x2038 + x"0E",x"DD",x"77",x"07",x"21",x"6E",x"40",x"35", -- 0x2040 + x"C2",x"55",x"20",x"36",x"03",x"DD",x"7E",x"05", -- 0x2048 + x"EE",x"34",x"DD",x"77",x"05",x"21",x"7A",x"40", -- 0x2050 + x"35",x"C0",x"36",x"05",x"3A",x"80",x"40",x"FE", -- 0x2058 + x"01",x"CA",x"6F",x"20",x"3A",x"78",x"40",x"3D", -- 0x2060 + x"3D",x"FE",x"02",x"D8",x"C3",x"82",x"20",x"3A", -- 0x2068 + x"78",x"40",x"3C",x"3C",x"FE",x"12",x"DA",x"82", -- 0x2070 + x"20",x"3A",x"80",x"40",x"EE",x"01",x"32",x"80", -- 0x2078 + x"40",x"C9",x"32",x"78",x"40",x"C9",x"21",x"BA", -- 0x2080 + x"41",x"AF",x"06",x"08",x"77",x"23",x"10",x"FC", -- 0x2088 + x"C9",x"3A",x"92",x"40",x"FE",x"01",x"CA",x"B2", -- 0x2090 + x"21",x"FE",x"03",x"CA",x"B2",x"20",x"FE",x"02", -- 0x2098 + x"C0",x"3A",x"08",x"41",x"FE",x"10",x"C2",x"B2", -- 0x20A0 + x"20",x"AF",x"32",x"94",x"40",x"3E",x"03",x"32", -- 0x20A8 + x"92",x"40",x"DD",x"21",x"C2",x"42",x"FD",x"21", -- 0x20B0 + x"94",x"40",x"21",x"65",x"52",x"06",x"20",x"DD", -- 0x20B8 + x"7E",x"00",x"A7",x"CA",x"EA",x"20",x"DD",x"35", -- 0x20C0 + x"00",x"C2",x"EA",x"20",x"CD",x"09",x"28",x"E6", -- 0x20C8 + x"0E",x"3C",x"DD",x"77",x"00",x"CD",x"09",x"28", -- 0x20D0 + x"DD",x"A6",x"01",x"DD",x"86",x"02",x"FD",x"A6", -- 0x20D8 + x"00",x"C2",x"E9",x"20",x"DD",x"77",x"00",x"3E", -- 0x20E0 + x"10",x"77",x"23",x"78",x"E6",x"03",x"FE",x"01", -- 0x20E8 + x"C2",x"F7",x"20",x"11",x"DC",x"FF",x"19",x"11", -- 0x20F0 + x"03",x"00",x"DD",x"19",x"10",x"C1",x"DD",x"21", -- 0x20F8 + x"AA",x"41",x"21",x"22",x"41",x"35",x"C2",x"22", -- 0x2100 + x"21",x"CD",x"09",x"28",x"E6",x"0F",x"3C",x"77", -- 0x2108 + x"CD",x"09",x"28",x"E6",x"03",x"3C",x"32",x"75", -- 0x2110 + x"41",x"32",x"77",x"41",x"32",x"79",x"41",x"32", -- 0x2118 + x"7B",x"41",x"21",x"23",x"41",x"35",x"C2",x"5C", -- 0x2120 + x"21",x"3A",x"24",x"41",x"77",x"3A",x"9D",x"40", -- 0x2128 + x"FE",x"00",x"C2",x"5C",x"21",x"3A",x"25",x"41", -- 0x2130 + x"A7",x"3A",x"74",x"41",x"CA",x"49",x"21",x"3C", -- 0x2138 + x"DD",x"34",x"18",x"DD",x"34",x"1C",x"C3",x"50", -- 0x2140 + x"21",x"3D",x"DD",x"35",x"18",x"DD",x"35",x"1C", -- 0x2148 + x"32",x"74",x"41",x"32",x"76",x"41",x"32",x"78", -- 0x2150 + x"41",x"32",x"7A",x"41",x"21",x"26",x"41",x"35", -- 0x2158 + x"C2",x"7C",x"21",x"3E",x"30",x"32",x"26",x"41", -- 0x2160 + x"3A",x"A2",x"41",x"D6",x"84",x"47",x"DD",x"7E", -- 0x2168 + x"18",x"90",x"06",x"00",x"D2",x"78",x"21",x"04", -- 0x2170 + x"78",x"32",x"25",x"41",x"3A",x"A2",x"41",x"D6", -- 0x2178 + x"84",x"47",x"DD",x"7E",x"18",x"90",x"06",x"03", -- 0x2180 + x"D2",x"8F",x"21",x"06",x"01",x"ED",x"44",x"FE", -- 0x2188 + x"23",x"D2",x"96",x"21",x"06",x"00",x"3E",x"16", -- 0x2190 + x"A8",x"DD",x"77",x"19",x"3A",x"9D",x"40",x"FE", -- 0x2198 + x"00",x"C0",x"3A",x"08",x"41",x"FE",x"06",x"3E", -- 0x21A0 + x"10",x"CA",x"AE",x"21",x"3E",x"0F",x"DD",x"77", -- 0x21A8 + x"1D",x"C9",x"21",x"93",x"40",x"35",x"C0",x"3E", -- 0x21B0 + x"02",x"32",x"75",x"41",x"32",x"77",x"41",x"32", -- 0x21B8 + x"79",x"41",x"32",x"7B",x"41",x"AF",x"32",x"74", -- 0x21C0 + x"41",x"32",x"76",x"41",x"32",x"78",x"41",x"32", -- 0x21C8 + x"7A",x"41",x"21",x"C2",x"42",x"11",x"54",x"2C", -- 0x21D0 + x"06",x"60",x"1A",x"77",x"23",x"13",x"10",x"FA", -- 0x21D8 + x"DD",x"21",x"AA",x"41",x"DD",x"36",x"18",x"7A", -- 0x21E0 + x"DD",x"36",x"19",x"16",x"DD",x"36",x"1A",x"07", -- 0x21E8 + x"DD",x"36",x"1B",x"30",x"DD",x"36",x"1C",x"7A", -- 0x21F0 + x"DD",x"36",x"1D",x"10",x"DD",x"36",x"1E",x"07", -- 0x21F8 + x"DD",x"36",x"1F",x"34",x"3E",x"10",x"32",x"22", -- 0x2200 + x"41",x"3A",x"24",x"41",x"32",x"23",x"41",x"CD", -- 0x2208 + x"09",x"28",x"E6",x"01",x"32",x"25",x"41",x"3A", -- 0x2210 + x"30",x"00",x"32",x"26",x"41",x"3E",x"FF",x"32", -- 0x2218 + x"94",x"40",x"3E",x"02",x"32",x"92",x"40",x"C9", -- 0x2220 + x"3A",x"08",x"41",x"FE",x"06",x"C0",x"3A",x"92", -- 0x2228 + x"40",x"FE",x"02",x"C0",x"21",x"1D",x"40",x"35", -- 0x2230 + x"C0",x"3A",x"74",x"41",x"47",x"3A",x"A2",x"41", -- 0x2238 + x"90",x"D2",x"46",x"22",x"ED",x"44",x"CB",x"3F", -- 0x2240 + x"CB",x"3F",x"CB",x"3F",x"47",x"CD",x"09",x"28", -- 0x2248 + x"E6",x"0F",x"80",x"3C",x"77",x"3A",x"1E",x"40", -- 0x2250 + x"21",x"27",x"41",x"BE",x"C8",x"3A",x"74",x"41", -- 0x2258 + x"C6",x"6B",x"47",x"CD",x"09",x"28",x"E6",x"2F", -- 0x2260 + x"80",x"21",x"C7",x"41",x"11",x"04",x"00",x"06", -- 0x2268 + x"06",x"19",x"BE",x"CA",x"5D",x"22",x"10",x"F9", -- 0x2270 + x"DD",x"21",x"C6",x"41",x"47",x"DD",x"19",x"DD", -- 0x2278 + x"7E",x"01",x"DD",x"B6",x"03",x"C2",x"7D",x"22", -- 0x2280 + x"DD",x"70",x"01",x"3E",x"B9",x"21",x"1B",x"41", -- 0x2288 + x"AE",x"DD",x"77",x"03",x"21",x"1E",x"40",x"34", -- 0x2290 + x"C9",x"21",x"2C",x"41",x"35",x"C0",x"3A",x"2D", -- 0x2298 + x"41",x"77",x"3A",x"08",x"41",x"FE",x"06",x"C0", -- 0x22A0 + x"3A",x"92",x"40",x"FE",x"02",x"C0",x"21",x"0B", -- 0x22A8 + x"41",x"3A",x"0C",x"41",x"BE",x"D0",x"21",x"29", -- 0x22B0 + x"41",x"BE",x"C8",x"DD",x"21",x"C6",x"41",x"FD", -- 0x22B8 + x"21",x"A6",x"41",x"01",x"24",x"00",x"11",x"04", -- 0x22C0 + x"00",x"DD",x"09",x"FD",x"19",x"DD",x"7E",x"00", -- 0x22C8 + x"FE",x"00",x"C2",x"C9",x"22",x"DD",x"36",x"00", -- 0x22D0 + x"02",x"CD",x"09",x"28",x"E6",x"01",x"DD",x"77", -- 0x22D8 + x"05",x"3A",x"28",x"41",x"DD",x"77",x"06",x"3A", -- 0x22E0 + x"2B",x"41",x"DD",x"77",x"04",x"3A",x"2F",x"41", -- 0x22E8 + x"DD",x"77",x"08",x"CD",x"09",x"28",x"21",x"2A", -- 0x22F0 + x"41",x"A6",x"3C",x"DD",x"77",x"03",x"DD",x"36", -- 0x22F8 + x"01",x"02",x"DD",x"36",x"02",x"01",x"3A",x"2E", -- 0x2300 + x"41",x"DD",x"77",x"07",x"DD",x"36",x"1A",x"07", -- 0x2308 + x"DD",x"36",x"1B",x"08",x"DD",x"36",x"1C",x"08", -- 0x2310 + x"DD",x"36",x"1D",x"0E",x"3A",x"74",x"41",x"C6", -- 0x2318 + x"7A",x"FD",x"77",x"00",x"FD",x"36",x"03",x"38", -- 0x2320 + x"FD",x"36",x"01",x"0B",x"3A",x"75",x"41",x"FD", -- 0x2328 + x"77",x"02",x"21",x"0C",x"41",x"34",x"21",x"CF", -- 0x2330 + x"29",x"22",x"0C",x"40",x"3E",x"01",x"32",x"02", -- 0x2338 + x"40",x"21",x"00",x"00",x"22",x"0E",x"40",x"C9", -- 0x2340 + x"3A",x"0C",x"41",x"A7",x"C8",x"47",x"DD",x"21", -- 0x2348 + x"C6",x"41",x"FD",x"21",x"A6",x"41",x"11",x"24", -- 0x2350 + x"00",x"DD",x"19",x"11",x"04",x"00",x"FD",x"19", -- 0x2358 + x"DD",x"7E",x"00",x"FE",x"00",x"CA",x"56",x"23", -- 0x2360 + x"FE",x"0C",x"C2",x"B5",x"23",x"DD",x"35",x"0A", -- 0x2368 + x"C2",x"F5",x"24",x"DD",x"36",x"0A",x"07",x"FD", -- 0x2370 + x"34",x"01",x"FD",x"7E",x"01",x"FE",x"20",x"C2", -- 0x2378 + x"F5",x"24",x"DD",x"36",x"00",x"00",x"FD",x"36", -- 0x2380 + x"01",x"00",x"FD",x"36",x"00",x"00",x"FD",x"36", -- 0x2388 + x"03",x"00",x"DD",x"7E",x"0D",x"0F",x"0F",x"0F", -- 0x2390 + x"0F",x"E6",x"70",x"CD",x"2B",x"28",x"CD",x"4A", -- 0x2398 + x"28",x"21",x"0C",x"41",x"35",x"2B",x"35",x"7E", -- 0x23A0 + x"FE",x"01",x"C2",x"F5",x"24",x"3E",x"08",x"32", -- 0x23A8 + x"28",x"41",x"C3",x"F5",x"24",x"DD",x"35",x"07", -- 0x23B0 + x"CA",x"C8",x"23",x"21",x"30",x"41",x"3A",x"0B", -- 0x23B8 + x"41",x"BE",x"DA",x"9D",x"24",x"C3",x"F5",x"24", -- 0x23C0 + x"3A",x"2E",x"41",x"DD",x"77",x"07",x"DD",x"7E", -- 0x23C8 + x"00",x"FE",x"05",x"D2",x"FE",x"23",x"DD",x"35", -- 0x23D0 + x"01",x"C2",x"FE",x"23",x"DD",x"36",x"01",x"02", -- 0x23D8 + x"FD",x"7E",x"01",x"DD",x"86",x"02",x"FE",x"0F", -- 0x23E0 + x"D2",x"F0",x"23",x"FE",x"0B",x"D2",x"FB",x"23", -- 0x23E8 + x"DD",x"7E",x"02",x"ED",x"44",x"DD",x"77",x"02", -- 0x23F0 + x"C3",x"E0",x"23",x"FD",x"77",x"01",x"DD",x"35", -- 0x23F8 + x"03",x"C2",x"1F",x"24",x"CD",x"09",x"28",x"21", -- 0x2400 + x"2A",x"41",x"A6",x"3C",x"DD",x"77",x"03",x"FD", -- 0x2408 + x"7E",x"02",x"3C",x"E6",x"03",x"C2",x"19",x"24", -- 0x2410 + x"3C",x"FD",x"77",x"02",x"DD",x"77",x"0D",x"DD", -- 0x2418 + x"7E",x"00",x"FE",x"02",x"C2",x"39",x"24",x"FD", -- 0x2420 + x"35",x"03",x"FD",x"7E",x"03",x"FE",x"10",x"C2", -- 0x2428 + x"9D",x"24",x"DD",x"36",x"00",x"04",x"C3",x"9D", -- 0x2430 + x"24",x"FD",x"34",x"03",x"FD",x"7E",x"03",x"DD", -- 0x2438 + x"BE",x"08",x"DA",x"49",x"24",x"FD",x"34",x"03", -- 0x2440 + x"3C",x"3D",x"FE",x"FE",x"DA",x"5E",x"24",x"3A", -- 0x2448 + x"74",x"41",x"C6",x"7A",x"FD",x"77",x"00",x"DD", -- 0x2450 + x"36",x"00",x"0E",x"C3",x"F5",x"24",x"DD",x"7E", -- 0x2458 + x"00",x"FE",x"04",x"C2",x"7A",x"24",x"FD",x"7E", -- 0x2460 + x"03",x"DD",x"BE",x"04",x"C2",x"7A",x"24",x"FD", -- 0x2468 + x"36",x"01",x"13",x"DD",x"36",x"00",x"10",x"C3", -- 0x2470 + x"9D",x"24",x"DD",x"7E",x"00",x"FE",x"0E",x"C2", -- 0x2478 + x"9D",x"24",x"FD",x"7E",x"03",x"FE",x"38",x"C2", -- 0x2480 + x"F5",x"24",x"DD",x"36",x"00",x"00",x"FD",x"36", -- 0x2488 + x"00",x"00",x"FD",x"36",x"03",x"00",x"21",x"0C", -- 0x2490 + x"41",x"35",x"C3",x"F5",x"24",x"DD",x"7E",x"00", -- 0x2498 + x"FE",x"0E",x"CA",x"F5",x"24",x"3A",x"A2",x"41", -- 0x24A0 + x"C6",x"89",x"4F",x"FD",x"7E",x"00",x"91",x"D2", -- 0x24A8 + x"B4",x"24",x"ED",x"44",x"0F",x"0F",x"0F",x"0F", -- 0x24B0 + x"2F",x"E6",x"03",x"3C",x"DD",x"CB",x"05",x"46", -- 0x24B8 + x"C2",x"C5",x"24",x"ED",x"44",x"FD",x"86",x"00", -- 0x24C0 + x"5F",x"C6",x"1C",x"FE",x"20",x"CB",x"17",x"57", -- 0x24C8 + x"DD",x"AE",x"05",x"DD",x"77",x"05",x"CB",x"42", -- 0x24D0 + x"C2",x"AB",x"24",x"FD",x"73",x"00",x"DD",x"35", -- 0x24D8 + x"06",x"C2",x"F5",x"24",x"3A",x"28",x"41",x"DD", -- 0x24E0 + x"77",x"06",x"FD",x"7E",x"00",x"91",x"CB",x"17", -- 0x24E8 + x"E6",x"01",x"DD",x"77",x"05",x"05",x"C2",x"56", -- 0x24F0 + x"23",x"C9",x"DD",x"21",x"AA",x"41",x"FD",x"21", -- 0x24F8 + x"E6",x"41",x"3A",x"9D",x"40",x"FE",x"01",x"CA", -- 0x2500 + x"16",x"26",x"FE",x"03",x"CA",x"5F",x"26",x"FE", -- 0x2508 + x"02",x"CA",x"36",x"25",x"FE",x"00",x"C0",x"3A", -- 0x2510 + x"0B",x"41",x"A7",x"C0",x"3A",x"08",x"41",x"FE", -- 0x2518 + x"06",x"C0",x"3E",x"20",x"32",x"9E",x"40",x"3E", -- 0x2520 + x"01",x"32",x"9D",x"40",x"AF",x"32",x"94",x"40", -- 0x2528 + x"3E",x"03",x"32",x"92",x"40",x"C9",x"DD",x"7E", -- 0x2530 + x"03",x"FE",x"D8",x"DA",x"53",x"25",x"3A",x"A2", -- 0x2538 + x"41",x"C6",x"83",x"DD",x"96",x"00",x"FE",x"23", -- 0x2540 + x"D2",x"53",x"25",x"3E",x"0C",x"32",x"08",x"41", -- 0x2548 + x"C3",x"7B",x"25",x"DD",x"7E",x"00",x"C6",x"19", -- 0x2550 + x"FD",x"96",x"01",x"FE",x"17",x"D2",x"86",x"25", -- 0x2558 + x"21",x"1B",x"41",x"FD",x"7E",x"03",x"AE",x"DD", -- 0x2560 + x"86",x"03",x"C6",x"10",x"FE",x"08",x"D2",x"86", -- 0x2568 + x"25",x"AF",x"32",x"0D",x"41",x"FD",x"77",x"01", -- 0x2570 + x"FD",x"77",x"03",x"3E",x"20",x"CD",x"2B",x"28", -- 0x2578 + x"CD",x"4A",x"28",x"C3",x"8E",x"25",x"DD",x"7E", -- 0x2580 + x"03",x"FE",x"E0",x"C2",x"B2",x"25",x"3E",x"01", -- 0x2588 + x"32",x"87",x"40",x"32",x"88",x"40",x"3E",x"80", -- 0x2590 + x"32",x"9F",x"40",x"21",x"EF",x"29",x"22",x"0C", -- 0x2598 + x"40",x"21",x"00",x"00",x"22",x"0E",x"40",x"3E", -- 0x25A0 + x"01",x"32",x"02",x"40",x"3E",x"03",x"32",x"9D", -- 0x25A8 + x"40",x"C9",x"DD",x"34",x"03",x"DD",x"34",x"07", -- 0x25B0 + x"DD",x"34",x"1B",x"3A",x"A2",x"41",x"C6",x"70", -- 0x25B8 + x"4F",x"DD",x"7E",x"00",x"91",x"D2",x"CA",x"25", -- 0x25C0 + x"ED",x"44",x"0F",x"0F",x"0F",x"0F",x"E6",x"03", -- 0x25C8 + x"3C",x"3C",x"21",x"72",x"40",x"CB",x"46",x"C2", -- 0x25D0 + x"DC",x"25",x"ED",x"44",x"DD",x"86",x"00",x"5F", -- 0x25D8 + x"C6",x"40",x"FE",x"40",x"CB",x"17",x"47",x"AE", -- 0x25E0 + x"77",x"CB",x"40",x"C2",x"C1",x"25",x"DD",x"73", -- 0x25E8 + x"00",x"3E",x"0F",x"83",x"DD",x"77",x"04",x"3E", -- 0x25F0 + x"07",x"83",x"DD",x"77",x"18",x"21",x"73",x"40", -- 0x25F8 + x"35",x"C0",x"CD",x"09",x"28",x"E6",x"1F",x"C6", -- 0x2600 + x"20",x"77",x"DD",x"7E",x"00",x"91",x"CB",x"17", -- 0x2608 + x"E6",x"01",x"32",x"72",x"40",x"C9",x"21",x"9E", -- 0x2610 + x"40",x"35",x"C0",x"DD",x"7E",x"18",x"D6",x"0F", -- 0x2618 + x"DD",x"77",x"00",x"C6",x"07",x"DD",x"77",x"04", -- 0x2620 + x"DD",x"36",x"03",x"30",x"DD",x"36",x"07",x"30", -- 0x2628 + x"DD",x"36",x"01",x"2D",x"DD",x"36",x"05",x"2E", -- 0x2630 + x"DD",x"36",x"02",x"07",x"DD",x"36",x"06",x"07", -- 0x2638 + x"DD",x"36",x"1C",x"00",x"DD",x"36",x"1F",x"00", -- 0x2640 + x"21",x"A9",x"2A",x"22",x"0C",x"40",x"21",x"00", -- 0x2648 + x"00",x"22",x"0E",x"40",x"3E",x"01",x"32",x"02", -- 0x2650 + x"40",x"3E",x"02",x"32",x"9D",x"40",x"C9",x"21", -- 0x2658 + x"9F",x"40",x"35",x"CA",x"93",x"26",x"21",x"87", -- 0x2660 + x"40",x"35",x"C2",x"7E",x"26",x"CD",x"09",x"28", -- 0x2668 + x"E6",x"0F",x"3C",x"77",x"CD",x"09",x"28",x"E6", -- 0x2670 + x"03",x"C6",x"0B",x"DD",x"77",x"01",x"23",x"35", -- 0x2678 + x"C0",x"CD",x"09",x"28",x"E6",x"0F",x"3C",x"77", -- 0x2680 + x"CD",x"09",x"28",x"E6",x"03",x"C6",x"0B",x"DD", -- 0x2688 + x"77",x"05",x"C9",x"DD",x"36",x"00",x"00",x"DD", -- 0x2690 + x"36",x"04",x"00",x"DD",x"36",x"03",x"00",x"DD", -- 0x2698 + x"36",x"07",x"00",x"DD",x"36",x"18",x"00",x"DD", -- 0x26A0 + x"36",x"1B",x"00",x"3E",x"04",x"32",x"9D",x"40", -- 0x26A8 + x"C9",x"21",x"AA",x"41",x"AF",x"06",x"40",x"77", -- 0x26B0 + x"23",x"10",x"FC",x"32",x"0C",x"41",x"32",x"0D", -- 0x26B8 + x"41",x"32",x"1E",x"40",x"32",x"00",x"68",x"32", -- 0x26C0 + x"01",x"68",x"32",x"02",x"68",x"21",x"EA",x"41", -- 0x26C8 + x"01",x"20",x"01",x"36",x"00",x"23",x"0B",x"78", -- 0x26D0 + x"B1",x"C2",x"D3",x"26",x"21",x"24",x"40",x"06", -- 0x26D8 + x"40",x"36",x"00",x"23",x"10",x"FB",x"C9",x"01", -- 0x26E0 + x"20",x"00",x"1A",x"FE",x"FF",x"C8",x"FE",x"20", -- 0x26E8 + x"CA",x"F6",x"26",x"D6",x"30",x"77",x"ED",x"42", -- 0x26F0 + x"13",x"C3",x"EA",x"26",x"21",x"02",x"50",x"06", -- 0x26F8 + x"20",x"36",x"10",x"23",x"7D",x"E6",x"1F",x"C2", -- 0x2700 + x"01",x"27",x"23",x"23",x"3A",x"00",x"78",x"10", -- 0x2708 + x"F0",x"C9",x"3E",x"FF",x"32",x"00",x"78",x"AF", -- 0x2710 + x"32",x"06",x"68",x"32",x"07",x"68",x"C9",x"C5", -- 0x2718 + x"2A",x"0C",x"40",x"01",x"EF",x"29",x"ED",x"42", -- 0x2720 + x"C1",x"DA",x"31",x"27",x"ED",x"53",x"0C",x"40", -- 0x2728 + x"C9",x"2A",x"0C",x"40",x"22",x"0E",x"40",x"ED", -- 0x2730 + x"53",x"0C",x"40",x"3E",x"01",x"32",x"02",x"40", -- 0x2738 + x"C9",x"21",x"00",x"41",x"01",x"6A",x"00",x"3A", -- 0x2740 + x"00",x"40",x"FE",x"04",x"C2",x"55",x"27",x"21", -- 0x2748 + x"06",x"41",x"01",x"64",x"00",x"36",x"00",x"23", -- 0x2750 + x"0B",x"78",x"B1",x"C2",x"55",x"27",x"C9",x"3A", -- 0x2758 + x"10",x"41",x"32",x"20",x"40",x"21",x"06",x"41", -- 0x2760 + x"11",x"38",x"41",x"01",x"32",x"00",x"7E",x"08", -- 0x2768 + x"1A",x"77",x"08",x"12",x"23",x"13",x"0B",x"78", -- 0x2770 + x"B1",x"C2",x"6E",x"27",x"C9",x"FD",x"7E",x"00", -- 0x2778 + x"FE",x"80",x"1E",x"55",x"D2",x"89",x"27",x"1E", -- 0x2780 + x"00",x"ED",x"5F",x"E6",x"01",x"7B",x"CA",x"93", -- 0x2788 + x"27",x"F6",x"AA",x"DD",x"A6",x"22",x"DD",x"77", -- 0x2790 + x"0C",x"21",x"BA",x"2B",x"DD",x"7E",x"22",x"FE", -- 0x2798 + x"FF",x"C2",x"AA",x"27",x"DD",x"35",x"11",x"C2", -- 0x27A0 + x"C3",x"27",x"21",x"CA",x"2B",x"DD",x"7E",x"0C", -- 0x27A8 + x"E6",x"55",x"DD",x"77",x"0C",x"DD",x"36",x"22", -- 0x27B0 + x"55",x"DD",x"7E",x"11",x"0F",x"DA",x"C3",x"27", -- 0x27B8 + x"DD",x"77",x"11",x"ED",x"5F",x"E6",x"0C",x"5F", -- 0x27C0 + x"16",x"00",x"19",x"5E",x"23",x"56",x"23",x"1A", -- 0x27C8 + x"DD",x"AE",x"0C",x"DD",x"73",x"07",x"DD",x"72", -- 0x27D0 + x"08",x"DD",x"77",x"09",x"5E",x"23",x"56",x"DD", -- 0x27D8 + x"73",x"01",x"DD",x"72",x"02",x"1A",x"0F",x"0F", -- 0x27E0 + x"0F",x"0F",x"E6",x"0F",x"DD",x"77",x"03",x"DD", -- 0x27E8 + x"77",x"05",x"1A",x"E6",x"0F",x"DD",x"77",x"04", -- 0x27F0 + x"DD",x"77",x"06",x"DD",x"36",x"0A",x"04",x"ED", -- 0x27F8 + x"5F",x"E6",x"1F",x"C6",x"08",x"DD",x"77",x"0B", -- 0x2800 + x"C9",x"E5",x"2A",x"8C",x"40",x"23",x"7C",x"E6", -- 0x2808 + x"1F",x"67",x"22",x"8C",x"40",x"7E",x"E1",x"C9", -- 0x2810 + x"D9",x"4F",x"3A",x"00",x"40",x"FE",x"04",x"CA", -- 0x2818 + x"48",x"28",x"79",x"2A",x"0E",x"41",x"23",x"86", -- 0x2820 + x"C3",x"40",x"28",x"D9",x"4F",x"3A",x"00",x"40", -- 0x2828 + x"FE",x"04",x"79",x"CA",x"48",x"28",x"2A",x"0E", -- 0x2830 + x"41",x"86",x"27",x"77",x"23",x"7E",x"CE",x"00", -- 0x2838 + x"27",x"77",x"23",x"7E",x"CE",x"00",x"27",x"77", -- 0x2840 + x"D9",x"C9",x"3A",x"21",x"41",x"A7",x"C8",x"3A", -- 0x2848 + x"00",x"40",x"FE",x"04",x"C8",x"2A",x"0E",x"41", -- 0x2850 + x"23",x"23",x"7E",x"A7",x"C2",x"66",x"28",x"2B", -- 0x2858 + x"7E",x"21",x"68",x"40",x"BE",x"D8",x"3A",x"00", -- 0x2860 + x"40",x"FE",x"18",x"21",x"60",x"50",x"CA",x"74", -- 0x2868 + x"28",x"21",x"A0",x"53",x"34",x"21",x"10",x"41", -- 0x2870 + x"34",x"AF",x"32",x"21",x"41",x"11",x"CB",x"2A", -- 0x2878 + x"CD",x"1F",x"27",x"C9",x"C9",x"8F",x"28",x"BB", -- 0x2880 + x"28",x"E7",x"28",x"13",x"29",x"3F",x"29",x"B2", -- 0x2888 + x"10",x"F7",x"10",x"72",x"11",x"31",x"11",x"4B", -- 0x2890 + x"12",x"4B",x"12",x"4B",x"12",x"4F",x"13",x"4F", -- 0x2898 + x"13",x"4F",x"13",x"72",x"11",x"72",x"11",x"72", -- 0x28A0 + x"11",x"83",x"13",x"83",x"13",x"83",x"13",x"D3", -- 0x28A8 + x"13",x"D3",x"13",x"D3",x"13",x"02",x"14",x"02", -- 0x28B0 + x"14",x"02",x"14",x"00",x"00",x"00",x"00",x"00", -- 0x28B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C0 + x"00",x"B3",x"14",x"B3",x"14",x"B3",x"14",x"27", -- 0x28C8 + x"15",x"27",x"15",x"27",x"15",x"83",x"13",x"83", -- 0x28D0 + x"13",x"83",x"13",x"00",x"00",x"00",x"00",x"00", -- 0x28D8 + x"00",x"02",x"14",x"02",x"14",x"02",x"14",x"B2", -- 0x28E0 + x"10",x"F7",x"10",x"73",x"17",x"31",x"11",x"4B", -- 0x28E8 + x"12",x"4B",x"12",x"4B",x"12",x"6F",x"15",x"6F", -- 0x28F0 + x"15",x"6F",x"15",x"73",x"17",x"73",x"17",x"73", -- 0x28F8 + x"17",x"83",x"13",x"83",x"13",x"83",x"13",x"DE", -- 0x2900 + x"13",x"DE",x"13",x"DE",x"13",x"02",x"14",x"02", -- 0x2908 + x"14",x"02",x"14",x"B2",x"10",x"F7",x"10",x"72", -- 0x2910 + x"11",x"31",x"11",x"4B",x"12",x"4B",x"12",x"4B", -- 0x2918 + x"12",x"81",x"16",x"81",x"16",x"81",x"16",x"C2", -- 0x2920 + x"17",x"C2",x"17",x"C2",x"17",x"83",x"13",x"83", -- 0x2928 + x"13",x"83",x"13",x"4B",x"17",x"4B",x"17",x"4B", -- 0x2930 + x"17",x"02",x"14",x"02",x"14",x"02",x"14",x"B2", -- 0x2938 + x"10",x"F7",x"10",x"72",x"11",x"31",x"11",x"4B", -- 0x2940 + x"12",x"4B",x"12",x"4B",x"12",x"A4",x"15",x"A4", -- 0x2948 + x"15",x"A4",x"15",x"2F",x"16",x"2F",x"16",x"2F", -- 0x2950 + x"16",x"83",x"13",x"83",x"13",x"83",x"13",x"FF", -- 0x2958 + x"15",x"FF",x"15",x"FF",x"15",x"02",x"14",x"02", -- 0x2960 + x"14",x"02",x"14",x"5E",x"4D",x"7C",x"88",x"5E", -- 0x2968 + x"88",x"4A",x"7A",x"4A",x"72",x"4A",x"60",x"7C", -- 0x2970 + x"A6",x"5E",x"88",x"4A",x"7A",x"4A",x"72",x"4A", -- 0x2978 + x"60",x"7C",x"A6",x"5E",x"88",x"4A",x"7A",x"4A", -- 0x2980 + x"72",x"4A",x"7A",x"7C",x"60",x"4F",x"11",x"47", -- 0x2988 + x"FF",x"47",x"11",x"7C",x"4D",x"7C",x"4D",x"00", -- 0x2990 + x"FE",x"41",x"8F",x"41",x"A1",x"41",x"8F",x"41", -- 0x2998 + x"A1",x"41",x"8F",x"41",x"A1",x"05",x"FF",x"41", -- 0x29A0 + x"8F",x"41",x"A1",x"41",x"8F",x"41",x"A1",x"41", -- 0x29A8 + x"8F",x"41",x"A1",x"05",x"FF",x"41",x"8F",x"41", -- 0x29B0 + x"A1",x"41",x"8F",x"41",x"A1",x"41",x"8F",x"41", -- 0x29B8 + x"A1",x"41",x"FD",x"8F",x"A1",x"41",x"FC",x"01", -- 0x29C0 + x"A6",x"41",x"FC",x"FF",x"00",x"00",x"FE",x"C4", -- 0x29C8 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C2",x"FF",x"C4", -- 0x29D0 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C2",x"FF",x"C4", -- 0x29D8 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C1",x"FD",x"E5", -- 0x29E0 + x"D8",x"C1",x"FC",x"FF",x"30",x"00",x"FE",x"C2", -- 0x29E8 + x"1E",x"C2",x"57",x"C2",x"81",x"C2",x"2B",x"C2", -- 0x29F0 + x"60",x"C2",x"88",x"C2",x"37",x"C2",x"69",x"C2", -- 0x29F8 + x"8F",x"00",x"FE",x"C4",x"DC",x"C3",x"D6",x"C2", -- 0x2A00 + x"E5",x"C1",x"E1",x"00",x"FE",x"C2",x"A6",x"C4", -- 0x2A08 + x"B9",x"C2",x"A6",x"C4",x"1E",x"C2",x"A6",x"C4", -- 0x2A10 + x"B9",x"C2",x"A6",x"00",x"FE",x"43",x"11",x"42", -- 0x2A18 + x"1E",x"42",x"11",x"C3",x"4D",x"41",x"37",x"42", -- 0x2A20 + x"81",x"42",x"11",x"C2",x"60",x"43",x"1E",x"00", -- 0x2A28 + x"FE",x"44",x"FB",x"1E",x"11",x"44",x"FA",x"42", -- 0x2A30 + x"4D",x"42",x"7A",x"6C",x"95",x"56",x"95",x"42", -- 0x2A38 + x"69",x"42",x"7A",x"56",x"95",x"42",x"60",x"42", -- 0x2A40 + x"7A",x"56",x"9B",x"42",x"60",x"42",x"7A",x"6C", -- 0x2A48 + x"9B",x"42",x"4D",x"42",x"7A",x"56",x"95",x"42", -- 0x2A50 + x"60",x"42",x"7A",x"61",x"9B",x"42",x"7A",x"4B", -- 0x2A58 + x"95",x"42",x"72",x"56",x"88",x"42",x"60",x"56", -- 0x2A60 + x"7A",x"42",x"4D",x"6C",x"72",x"56",x"72",x"42", -- 0x2A68 + x"72",x"56",x"88",x"42",x"7A",x"42",x"95",x"6C", -- 0x2A70 + x"A6",x"42",x"4D",x"42",x"72",x"6C",x"9B",x"42", -- 0x2A78 + x"7A",x"4B",x"95",x"4B",x"7A",x"42",x"72",x"4B", -- 0x2A80 + x"9B",x"4B",x"88",x"42",x"7A",x"42",x"95",x"56", -- 0x2A88 + x"A6",x"42",x"60",x"42",x"7A",x"56",x"9B",x"42", -- 0x2A90 + x"4D",x"42",x"7A",x"6C",x"95",x"42",x"4D",x"42", -- 0x2A98 + x"72",x"6C",x"88",x"6C",x"7A",x"6C",x"7A",x"00", -- 0x2AA0 + x"FE",x"41",x"FD",x"69",x"72",x"41",x"FC",x"FF", -- 0x2AA8 + x"57",x"41",x"FD",x"42",x"57",x"41",x"FC",x"01", -- 0x2AB0 + x"88",x"41",x"FD",x"95",x"88",x"41",x"FC",x"FF", -- 0x2AB8 + x"1E",x"41",x"FD",x"1E",x"11",x"41",x"FC",x"01", -- 0x2AC0 + x"E5",x"00",x"FE",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x2AC8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x2AD0 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x2AD8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x2AE0 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x2AE8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"00",x"FE",x"F0", -- 0x2AF0 + x"41",x"41",x"53",x"53",x"FF",x"53",x"31",x"F0", -- 0x2AF8 + x"43",x"35",x"0F",x"12",x"12",x"12",x"54",x"52", -- 0x2B00 + x"51",x"F0",x"41",x"35",x"0F",x"15",x"35",x"FF", -- 0x2B08 + x"53",x"53",x"52",x"F0",x"52",x"53",x"41",x"00", -- 0x2B10 + x"FF",x"FF",x"57",x"00",x"80",x"FA",x"FF",x"57", -- 0x2B18 + x"32",x"32",x"32",x"32",x"32",x"32",x"F0",x"21", -- 0x2B20 + x"FF",x"12",x"0F",x"12",x"FF",x"21",x"F0",x"21", -- 0x2B28 + x"FF",x"12",x"0F",x"12",x"FF",x"21",x"F0",x"32", -- 0x2B30 + x"32",x"32",x"32",x"32",x"32",x"00",x"FF",x"7F", -- 0x2B38 + x"15",x"80",x"EA",x"7F",x"55",x"01",x"FF",x"FF", -- 0x2B40 + x"FF",x"21",x"21",x"F0",x"F0",x"21",x"0F",x"21", -- 0x2B48 + x"0F",x"FF",x"FF",x"00",x"FF",x"FF",x"EB",x"03", -- 0x2B50 + x"53",x"73",x"F0",x"52",x"FF",x"27",x"0F",x"0F", -- 0x2B58 + x"0F",x"0F",x"37",x"45",x"00",x"5F",x"D5",x"FF", -- 0x2B60 + x"18",x"2B",x"F7",x"2A",x"54",x"2B",x"46",x"2B", -- 0x2B68 + x"3E",x"2B",x"20",x"2B",x"65",x"2B",x"58",x"2B", -- 0x2B70 + x"52",x"31",x"51",x"61",x"F0",x"F0",x"61",x"51", -- 0x2B78 + x"31",x"52",x"00",x"FF",x"5F",x"05",x"53",x"21", -- 0x2B80 + x"52",x"F0",x"52",x"21",x"53",x"F0",x"52",x"21", -- 0x2B88 + x"53",x"00",x"FF",x"55",x"15",x"12",x"23",x"FF", -- 0x2B90 + x"21",x"41",x"F0",x"F0",x"41",x"21",x"FF",x"23", -- 0x2B98 + x"12",x"25",x"13",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x2BA0 + x"FF",x"FF",x"FF",x"0F",x"FF",x"FF",x"12",x"12", -- 0x2BA8 + x"FF",x"21",x"F0",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x2BB0 + x"FF",x"0F",x"83",x"2B",x"78",x"2B",x"92",x"2B", -- 0x2BB8 + x"86",x"2B",x"83",x"2B",x"78",x"2B",x"92",x"2B", -- 0x2BC0 + x"86",x"2B",x"A7",x"2B",x"95",x"2B",x"B7",x"2B", -- 0x2BC8 + x"AC",x"2B",x"A7",x"2B",x"95",x"2B",x"B7",x"2B", -- 0x2BD0 + x"AC",x"2B",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE0 + x"00",x"7E",x"00",x"FC",x"01",x"F8",x"03",x"F1", -- 0x2BE8 + x"1F",x"F3",x"3F",x"FF",x"FF",x"FF",x"3F",x"FF", -- 0x2BF0 + x"1F",x"F3",x"03",x"F1",x"01",x"F8",x"00",x"FC", -- 0x2BF8 + x"00",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C10 + x"2C",x"2C",x"3C",x"2C",x"24",x"2C",x"44",x"2C", -- 0x2C18 + x"4C",x"2C",x"34",x"2C",x"76",x"7F",x"7F",x"FE", -- 0x2C20 + x"FE",x"FF",x"7F",x"3A",x"00",x"00",x"1C",x"1E", -- 0x2C28 + x"3F",x"3F",x"3E",x"1E",x"38",x"7C",x"7C",x"FC", -- 0x2C30 + x"FC",x"78",x"00",x"00",x"40",x"E0",x"E0",x"60", -- 0x2C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"38", -- 0x2C40 + x"38",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C48 + x"02",x"07",x"07",x"02",x"00",x"00",x"00",x"2E", -- 0x2C50 + x"0C",x"2E",x"40",x"0C",x"2F",x"00",x"00",x"00", -- 0x2C58 + x"18",x"0C",x"2E",x"26",x"03",x"44",x"10",x"03", -- 0x2C60 + x"44",x"2A",x"0C",x"2F",x"22",x"03",x"44",x"10", -- 0x2C68 + x"03",x"44",x"2E",x"03",x"44",x"14",x"03",x"44", -- 0x2C70 + x"0C",x"03",x"44",x"02",x"03",x"44",x"04",x"03", -- 0x2C78 + x"44",x"0E",x"03",x"44",x"18",x"03",x"44",x"06", -- 0x2C80 + x"03",x"44",x"08",x"03",x"44",x"12",x"03",x"44", -- 0x2C88 + x"30",x"03",x"44",x"16",x"03",x"44",x"24",x"03", -- 0x2C90 + x"44",x"26",x"03",x"44",x"2C",x"0C",x"2C",x"0E", -- 0x2C98 + x"03",x"44",x"2C",x"03",x"44",x"40",x"0C",x"2D", -- 0x2CA0 + x"00",x"00",x"00",x"32",x"0C",x"2C",x"30",x"0C", -- 0x2CA8 + x"2D",x"00",x"00",x"00",x"38",x"7C",x"7C",x"FC", -- 0x2CB0 + x"FC",x"78",x"00",x"00",x"40",x"E0",x"E0",x"60", -- 0x2CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"38", -- 0x2CC0 + x"38",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC8 + x"02",x"07",x"07",x"02",x"00",x"00",x"00",x"2E", -- 0x2CD0 + x"0C",x"2E",x"40",x"0C",x"2F",x"00",x"00",x"00", -- 0x2CD8 + x"18",x"0C",x"2E",x"26",x"03",x"44",x"10",x"03", -- 0x2CE0 + x"44",x"2A",x"0C",x"2F",x"22",x"03",x"44",x"10", -- 0x2CE8 + x"03",x"44",x"2E",x"03",x"44",x"14",x"03",x"44", -- 0x2CF0 + x"0C",x"03",x"44",x"02",x"03",x"44",x"04",x"03", -- 0x2CF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF8 + x"5F",x"E6",x"1F",x"C6",x"08",x"DD",x"77",x"0B", -- 0x3000 + x"C9",x"E5",x"2A",x"8C",x"40",x"23",x"7C",x"E6", -- 0x3008 + x"1F",x"67",x"22",x"8C",x"40",x"7E",x"E1",x"C9", -- 0x3010 + x"D9",x"4F",x"3A",x"00",x"40",x"FE",x"04",x"CA", -- 0x3018 + x"48",x"28",x"79",x"2A",x"0E",x"41",x"23",x"86", -- 0x3020 + x"C3",x"40",x"28",x"D9",x"4F",x"3A",x"00",x"40", -- 0x3028 + x"FE",x"04",x"79",x"CA",x"48",x"28",x"2A",x"0E", -- 0x3030 + x"41",x"86",x"27",x"77",x"23",x"7E",x"CE",x"00", -- 0x3038 + x"27",x"77",x"23",x"7E",x"CE",x"00",x"27",x"77", -- 0x3040 + x"D9",x"C9",x"3A",x"21",x"41",x"A7",x"C8",x"3A", -- 0x3048 + x"00",x"40",x"FE",x"04",x"C8",x"2A",x"0E",x"41", -- 0x3050 + x"23",x"23",x"7E",x"A7",x"C2",x"66",x"28",x"2B", -- 0x3058 + x"7E",x"21",x"68",x"40",x"BE",x"D8",x"3A",x"00", -- 0x3060 + x"40",x"FE",x"18",x"21",x"60",x"50",x"CA",x"74", -- 0x3068 + x"28",x"21",x"A0",x"53",x"34",x"21",x"10",x"41", -- 0x3070 + x"34",x"AF",x"32",x"21",x"41",x"11",x"CB",x"2A", -- 0x3078 + x"CD",x"1F",x"27",x"C9",x"C9",x"8F",x"28",x"BB", -- 0x3080 + x"28",x"E7",x"28",x"13",x"29",x"3F",x"29",x"B2", -- 0x3088 + x"10",x"F7",x"10",x"72",x"11",x"31",x"11",x"4B", -- 0x3090 + x"12",x"4B",x"12",x"4B",x"12",x"4F",x"13",x"4F", -- 0x3098 + x"13",x"4F",x"13",x"72",x"11",x"72",x"11",x"72", -- 0x30A0 + x"11",x"83",x"13",x"83",x"13",x"83",x"13",x"D3", -- 0x30A8 + x"13",x"D3",x"13",x"D3",x"13",x"02",x"14",x"02", -- 0x30B0 + x"14",x"02",x"14",x"00",x"00",x"00",x"00",x"00", -- 0x30B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C0 + x"00",x"B3",x"14",x"B3",x"14",x"B3",x"14",x"27", -- 0x30C8 + x"15",x"27",x"15",x"27",x"15",x"83",x"13",x"83", -- 0x30D0 + x"13",x"83",x"13",x"00",x"00",x"00",x"00",x"00", -- 0x30D8 + x"00",x"02",x"14",x"02",x"14",x"02",x"14",x"B2", -- 0x30E0 + x"10",x"F7",x"10",x"73",x"17",x"31",x"11",x"4B", -- 0x30E8 + x"12",x"4B",x"12",x"4B",x"12",x"6F",x"15",x"6F", -- 0x30F0 + x"15",x"6F",x"15",x"73",x"17",x"73",x"17",x"73", -- 0x30F8 + x"17",x"83",x"13",x"83",x"13",x"83",x"13",x"DE", -- 0x3100 + x"13",x"DE",x"13",x"DE",x"13",x"02",x"14",x"02", -- 0x3108 + x"14",x"02",x"14",x"B2",x"10",x"F7",x"10",x"72", -- 0x3110 + x"11",x"31",x"11",x"4B",x"12",x"4B",x"12",x"4B", -- 0x3118 + x"12",x"81",x"16",x"81",x"16",x"81",x"16",x"C2", -- 0x3120 + x"17",x"C2",x"17",x"C2",x"17",x"83",x"13",x"83", -- 0x3128 + x"13",x"83",x"13",x"4B",x"17",x"4B",x"17",x"4B", -- 0x3130 + x"17",x"02",x"14",x"02",x"14",x"02",x"14",x"B2", -- 0x3138 + x"10",x"F7",x"10",x"72",x"11",x"31",x"11",x"4B", -- 0x3140 + x"12",x"4B",x"12",x"4B",x"12",x"A4",x"15",x"A4", -- 0x3148 + x"15",x"A4",x"15",x"2F",x"16",x"2F",x"16",x"2F", -- 0x3150 + x"16",x"83",x"13",x"83",x"13",x"83",x"13",x"FF", -- 0x3158 + x"15",x"FF",x"15",x"FF",x"15",x"02",x"14",x"02", -- 0x3160 + x"14",x"02",x"14",x"5E",x"4D",x"7C",x"88",x"5E", -- 0x3168 + x"88",x"4A",x"7A",x"4A",x"72",x"4A",x"60",x"7C", -- 0x3170 + x"A6",x"5E",x"88",x"4A",x"7A",x"4A",x"72",x"4A", -- 0x3178 + x"60",x"7C",x"A6",x"5E",x"88",x"4A",x"7A",x"4A", -- 0x3180 + x"72",x"4A",x"7A",x"7C",x"60",x"4F",x"11",x"47", -- 0x3188 + x"FF",x"47",x"11",x"7C",x"4D",x"7C",x"4D",x"00", -- 0x3190 + x"FE",x"41",x"8F",x"41",x"A1",x"41",x"8F",x"41", -- 0x3198 + x"A1",x"41",x"8F",x"41",x"A1",x"05",x"FF",x"41", -- 0x31A0 + x"8F",x"41",x"A1",x"41",x"8F",x"41",x"A1",x"41", -- 0x31A8 + x"8F",x"41",x"A1",x"05",x"FF",x"41",x"8F",x"41", -- 0x31B0 + x"A1",x"41",x"8F",x"41",x"A1",x"41",x"8F",x"41", -- 0x31B8 + x"A1",x"41",x"FD",x"8F",x"A1",x"41",x"FC",x"01", -- 0x31C0 + x"A6",x"41",x"FC",x"FF",x"00",x"00",x"FE",x"C4", -- 0x31C8 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C2",x"FF",x"C4", -- 0x31D0 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C2",x"FF",x"C4", -- 0x31D8 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C1",x"FD",x"E5", -- 0x31E0 + x"D8",x"C1",x"FC",x"FF",x"30",x"00",x"FE",x"C2", -- 0x31E8 + x"1E",x"C2",x"57",x"C2",x"81",x"C2",x"2B",x"C2", -- 0x31F0 + x"60",x"C2",x"88",x"C2",x"37",x"C2",x"69",x"C2", -- 0x31F8 + x"8F",x"00",x"FE",x"C4",x"DC",x"C3",x"D6",x"C2", -- 0x3200 + x"E5",x"C1",x"E1",x"00",x"FE",x"C2",x"A6",x"C4", -- 0x3208 + x"B9",x"C2",x"A6",x"C4",x"1E",x"C2",x"A6",x"C4", -- 0x3210 + x"B9",x"C2",x"A6",x"00",x"FE",x"43",x"11",x"42", -- 0x3218 + x"1E",x"42",x"11",x"C3",x"4D",x"41",x"37",x"42", -- 0x3220 + x"81",x"42",x"11",x"C2",x"60",x"43",x"1E",x"00", -- 0x3228 + x"FE",x"44",x"FB",x"1E",x"11",x"44",x"FA",x"42", -- 0x3230 + x"4D",x"42",x"7A",x"6C",x"95",x"56",x"95",x"42", -- 0x3238 + x"69",x"42",x"7A",x"56",x"95",x"42",x"60",x"42", -- 0x3240 + x"7A",x"56",x"9B",x"42",x"60",x"42",x"7A",x"6C", -- 0x3248 + x"9B",x"42",x"4D",x"42",x"7A",x"56",x"95",x"42", -- 0x3250 + x"60",x"42",x"7A",x"61",x"9B",x"42",x"7A",x"4B", -- 0x3258 + x"95",x"42",x"72",x"56",x"88",x"42",x"60",x"56", -- 0x3260 + x"7A",x"42",x"4D",x"6C",x"72",x"56",x"72",x"42", -- 0x3268 + x"72",x"56",x"88",x"42",x"7A",x"42",x"95",x"6C", -- 0x3270 + x"A6",x"42",x"4D",x"42",x"72",x"6C",x"9B",x"42", -- 0x3278 + x"7A",x"4B",x"95",x"4B",x"7A",x"42",x"72",x"4B", -- 0x3280 + x"9B",x"4B",x"88",x"42",x"7A",x"42",x"95",x"56", -- 0x3288 + x"A6",x"42",x"60",x"42",x"7A",x"56",x"9B",x"42", -- 0x3290 + x"4D",x"42",x"7A",x"6C",x"95",x"42",x"4D",x"42", -- 0x3298 + x"72",x"6C",x"88",x"6C",x"7A",x"6C",x"7A",x"00", -- 0x32A0 + x"FE",x"41",x"FD",x"69",x"72",x"41",x"FC",x"FF", -- 0x32A8 + x"57",x"41",x"FD",x"42",x"57",x"41",x"FC",x"01", -- 0x32B0 + x"88",x"41",x"FD",x"95",x"88",x"41",x"FC",x"FF", -- 0x32B8 + x"1E",x"41",x"FD",x"1E",x"11",x"41",x"FC",x"01", -- 0x32C0 + x"E5",x"00",x"FE",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x32C8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x32D0 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x32D8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x32E0 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x32E8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"00",x"FE",x"F0", -- 0x32F0 + x"41",x"41",x"53",x"53",x"FF",x"53",x"31",x"F0", -- 0x32F8 + x"43",x"35",x"0F",x"12",x"12",x"12",x"54",x"52", -- 0x3300 + x"51",x"F0",x"41",x"35",x"0F",x"15",x"35",x"FF", -- 0x3308 + x"53",x"53",x"52",x"F0",x"52",x"53",x"41",x"00", -- 0x3310 + x"FF",x"FF",x"57",x"00",x"80",x"FA",x"FF",x"57", -- 0x3318 + x"32",x"32",x"32",x"32",x"32",x"32",x"F0",x"21", -- 0x3320 + x"FF",x"12",x"0F",x"12",x"FF",x"21",x"F0",x"21", -- 0x3328 + x"FF",x"12",x"0F",x"12",x"FF",x"21",x"F0",x"32", -- 0x3330 + x"32",x"32",x"32",x"32",x"32",x"00",x"FF",x"7F", -- 0x3338 + x"15",x"80",x"EA",x"7F",x"55",x"01",x"FF",x"FF", -- 0x3340 + x"FF",x"21",x"21",x"F0",x"F0",x"21",x"0F",x"21", -- 0x3348 + x"0F",x"FF",x"FF",x"00",x"FF",x"FF",x"EB",x"03", -- 0x3350 + x"53",x"73",x"F0",x"52",x"FF",x"27",x"0F",x"0F", -- 0x3358 + x"0F",x"0F",x"37",x"45",x"00",x"5F",x"D5",x"FF", -- 0x3360 + x"18",x"2B",x"F7",x"2A",x"54",x"2B",x"46",x"2B", -- 0x3368 + x"3E",x"2B",x"20",x"2B",x"65",x"2B",x"58",x"2B", -- 0x3370 + x"52",x"31",x"51",x"61",x"F0",x"F0",x"61",x"51", -- 0x3378 + x"31",x"52",x"00",x"FF",x"5F",x"05",x"53",x"21", -- 0x3380 + x"52",x"F0",x"52",x"21",x"53",x"F0",x"52",x"21", -- 0x3388 + x"53",x"00",x"FF",x"55",x"15",x"12",x"23",x"FF", -- 0x3390 + x"21",x"41",x"F0",x"F0",x"41",x"21",x"FF",x"23", -- 0x3398 + x"12",x"25",x"13",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x33A0 + x"FF",x"FF",x"FF",x"0F",x"FF",x"FF",x"12",x"12", -- 0x33A8 + x"FF",x"21",x"F0",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x33B0 + x"FF",x"0F",x"83",x"2B",x"78",x"2B",x"92",x"2B", -- 0x33B8 + x"86",x"2B",x"83",x"2B",x"78",x"2B",x"92",x"2B", -- 0x33C0 + x"86",x"2B",x"A7",x"2B",x"95",x"2B",x"B7",x"2B", -- 0x33C8 + x"AC",x"2B",x"A7",x"2B",x"95",x"2B",x"B7",x"2B", -- 0x33D0 + x"AC",x"2B",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E0 + x"00",x"7E",x"00",x"FC",x"01",x"F8",x"03",x"F1", -- 0x33E8 + x"1F",x"F3",x"3F",x"FF",x"FF",x"FF",x"3F",x"FF", -- 0x33F0 + x"1F",x"F3",x"03",x"F1",x"01",x"F8",x"00",x"FC", -- 0x33F8 + x"00",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3410 + x"2C",x"2C",x"3C",x"2C",x"24",x"2C",x"44",x"2C", -- 0x3418 + x"4C",x"2C",x"34",x"2C",x"76",x"7F",x"7F",x"FE", -- 0x3420 + x"FE",x"FF",x"7F",x"3A",x"00",x"00",x"1C",x"1E", -- 0x3428 + x"3F",x"3F",x"3E",x"1E",x"38",x"7C",x"7C",x"FC", -- 0x3430 + x"FC",x"78",x"00",x"00",x"40",x"E0",x"E0",x"60", -- 0x3438 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"38", -- 0x3440 + x"38",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3448 + x"02",x"07",x"07",x"02",x"00",x"00",x"00",x"2E", -- 0x3450 + x"0C",x"2E",x"40",x"0C",x"2F",x"00",x"00",x"00", -- 0x3458 + x"18",x"0C",x"2E",x"26",x"03",x"44",x"10",x"03", -- 0x3460 + x"44",x"2A",x"0C",x"2F",x"22",x"03",x"44",x"10", -- 0x3468 + x"03",x"44",x"2E",x"03",x"44",x"14",x"03",x"44", -- 0x3470 + x"0C",x"03",x"44",x"02",x"03",x"44",x"04",x"03", -- 0x3478 + x"44",x"0E",x"03",x"44",x"18",x"03",x"44",x"06", -- 0x3480 + x"03",x"44",x"08",x"03",x"44",x"12",x"03",x"44", -- 0x3488 + x"30",x"03",x"44",x"16",x"03",x"44",x"24",x"03", -- 0x3490 + x"44",x"26",x"03",x"44",x"2C",x"0C",x"2C",x"0E", -- 0x3498 + x"03",x"44",x"2C",x"03",x"44",x"40",x"0C",x"2D", -- 0x34A0 + x"00",x"00",x"00",x"32",x"0C",x"2C",x"30",x"0C", -- 0x34A8 + x"2D",x"00",x"00",x"00",x"38",x"7C",x"7C",x"FC", -- 0x34B0 + x"FC",x"78",x"00",x"00",x"40",x"E0",x"E0",x"60", -- 0x34B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"38", -- 0x34C0 + x"38",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C8 + x"02",x"07",x"07",x"02",x"00",x"00",x"00",x"2E", -- 0x34D0 + x"0C",x"2E",x"40",x"0C",x"2F",x"00",x"00",x"00", -- 0x34D8 + x"18",x"0C",x"2E",x"26",x"03",x"44",x"10",x"03", -- 0x34E0 + x"44",x"2A",x"0C",x"2F",x"22",x"03",x"44",x"10", -- 0x34E8 + x"03",x"44",x"2E",x"03",x"44",x"14",x"03",x"44", -- 0x34F0 + x"0C",x"03",x"44",x"02",x"03",x"44",x"04",x"03", -- 0x34F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3500 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3508 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3510 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3518 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3520 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3528 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3530 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3538 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3540 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3548 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3550 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3558 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3560 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3568 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3570 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3578 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3580 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3588 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3590 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3598 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x35F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3600 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3608 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3610 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3618 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3620 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3628 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3630 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3638 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3640 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3648 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3658 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3660 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3668 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3670 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3678 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3680 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3688 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3690 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3698 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x36F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3700 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3708 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3710 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3718 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3720 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3728 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3730 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3738 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3740 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3748 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3750 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3758 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3760 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3768 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3770 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3778 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3780 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3788 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3790 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3798 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x37F8 + x"5F",x"E6",x"1F",x"C6",x"08",x"DD",x"77",x"0B", -- 0x3800 + x"C9",x"E5",x"2A",x"8C",x"40",x"23",x"7C",x"E6", -- 0x3808 + x"1F",x"67",x"22",x"8C",x"40",x"7E",x"E1",x"C9", -- 0x3810 + x"D9",x"4F",x"3A",x"00",x"40",x"FE",x"04",x"CA", -- 0x3818 + x"48",x"28",x"79",x"2A",x"0E",x"41",x"23",x"86", -- 0x3820 + x"C3",x"40",x"28",x"D9",x"4F",x"3A",x"00",x"40", -- 0x3828 + x"FE",x"04",x"79",x"CA",x"48",x"28",x"2A",x"0E", -- 0x3830 + x"41",x"86",x"27",x"77",x"23",x"7E",x"CE",x"00", -- 0x3838 + x"27",x"77",x"23",x"7E",x"CE",x"00",x"27",x"77", -- 0x3840 + x"D9",x"C9",x"3A",x"21",x"41",x"A7",x"C8",x"3A", -- 0x3848 + x"00",x"40",x"FE",x"04",x"C8",x"2A",x"0E",x"41", -- 0x3850 + x"23",x"23",x"7E",x"A7",x"C2",x"66",x"28",x"2B", -- 0x3858 + x"7E",x"21",x"68",x"40",x"BE",x"D8",x"3A",x"00", -- 0x3860 + x"40",x"FE",x"18",x"21",x"60",x"50",x"CA",x"74", -- 0x3868 + x"28",x"21",x"A0",x"53",x"34",x"21",x"10",x"41", -- 0x3870 + x"34",x"AF",x"32",x"21",x"41",x"11",x"CB",x"2A", -- 0x3878 + x"CD",x"1F",x"27",x"C9",x"C9",x"8F",x"28",x"BB", -- 0x3880 + x"28",x"E7",x"28",x"13",x"29",x"3F",x"29",x"B2", -- 0x3888 + x"10",x"F7",x"10",x"72",x"11",x"31",x"11",x"4B", -- 0x3890 + x"12",x"4B",x"12",x"4B",x"12",x"4F",x"13",x"4F", -- 0x3898 + x"13",x"4F",x"13",x"72",x"11",x"72",x"11",x"72", -- 0x38A0 + x"11",x"83",x"13",x"83",x"13",x"83",x"13",x"D3", -- 0x38A8 + x"13",x"D3",x"13",x"D3",x"13",x"02",x"14",x"02", -- 0x38B0 + x"14",x"02",x"14",x"00",x"00",x"00",x"00",x"00", -- 0x38B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C0 + x"00",x"B3",x"14",x"B3",x"14",x"B3",x"14",x"27", -- 0x38C8 + x"15",x"27",x"15",x"27",x"15",x"83",x"13",x"83", -- 0x38D0 + x"13",x"83",x"13",x"00",x"00",x"00",x"00",x"00", -- 0x38D8 + x"00",x"02",x"14",x"02",x"14",x"02",x"14",x"B2", -- 0x38E0 + x"10",x"F7",x"10",x"73",x"17",x"31",x"11",x"4B", -- 0x38E8 + x"12",x"4B",x"12",x"4B",x"12",x"6F",x"15",x"6F", -- 0x38F0 + x"15",x"6F",x"15",x"73",x"17",x"73",x"17",x"73", -- 0x38F8 + x"17",x"83",x"13",x"83",x"13",x"83",x"13",x"DE", -- 0x3900 + x"13",x"DE",x"13",x"DE",x"13",x"02",x"14",x"02", -- 0x3908 + x"14",x"02",x"14",x"B2",x"10",x"F7",x"10",x"72", -- 0x3910 + x"11",x"31",x"11",x"4B",x"12",x"4B",x"12",x"4B", -- 0x3918 + x"12",x"81",x"16",x"81",x"16",x"81",x"16",x"C2", -- 0x3920 + x"17",x"C2",x"17",x"C2",x"17",x"83",x"13",x"83", -- 0x3928 + x"13",x"83",x"13",x"4B",x"17",x"4B",x"17",x"4B", -- 0x3930 + x"17",x"02",x"14",x"02",x"14",x"02",x"14",x"B2", -- 0x3938 + x"10",x"F7",x"10",x"72",x"11",x"31",x"11",x"4B", -- 0x3940 + x"12",x"4B",x"12",x"4B",x"12",x"A4",x"15",x"A4", -- 0x3948 + x"15",x"A4",x"15",x"2F",x"16",x"2F",x"16",x"2F", -- 0x3950 + x"16",x"83",x"13",x"83",x"13",x"83",x"13",x"FF", -- 0x3958 + x"15",x"FF",x"15",x"FF",x"15",x"02",x"14",x"02", -- 0x3960 + x"14",x"02",x"14",x"5E",x"4D",x"7C",x"88",x"5E", -- 0x3968 + x"88",x"4A",x"7A",x"4A",x"72",x"4A",x"60",x"7C", -- 0x3970 + x"A6",x"5E",x"88",x"4A",x"7A",x"4A",x"72",x"4A", -- 0x3978 + x"60",x"7C",x"A6",x"5E",x"88",x"4A",x"7A",x"4A", -- 0x3980 + x"72",x"4A",x"7A",x"7C",x"60",x"4F",x"11",x"47", -- 0x3988 + x"FF",x"47",x"11",x"7C",x"4D",x"7C",x"4D",x"00", -- 0x3990 + x"FE",x"41",x"8F",x"41",x"A1",x"41",x"8F",x"41", -- 0x3998 + x"A1",x"41",x"8F",x"41",x"A1",x"05",x"FF",x"41", -- 0x39A0 + x"8F",x"41",x"A1",x"41",x"8F",x"41",x"A1",x"41", -- 0x39A8 + x"8F",x"41",x"A1",x"05",x"FF",x"41",x"8F",x"41", -- 0x39B0 + x"A1",x"41",x"8F",x"41",x"A1",x"41",x"8F",x"41", -- 0x39B8 + x"A1",x"41",x"FD",x"8F",x"A1",x"41",x"FC",x"01", -- 0x39C0 + x"A6",x"41",x"FC",x"FF",x"00",x"00",x"FE",x"C4", -- 0x39C8 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C2",x"FF",x"C4", -- 0x39D0 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C2",x"FF",x"C4", -- 0x39D8 + x"E5",x"C2",x"FF",x"C4",x"E5",x"C1",x"FD",x"E5", -- 0x39E0 + x"D8",x"C1",x"FC",x"FF",x"30",x"00",x"FE",x"C2", -- 0x39E8 + x"1E",x"C2",x"57",x"C2",x"81",x"C2",x"2B",x"C2", -- 0x39F0 + x"60",x"C2",x"88",x"C2",x"37",x"C2",x"69",x"C2", -- 0x39F8 + x"8F",x"00",x"FE",x"C4",x"DC",x"C3",x"D6",x"C2", -- 0x3A00 + x"E5",x"C1",x"E1",x"00",x"FE",x"C2",x"A6",x"C4", -- 0x3A08 + x"B9",x"C2",x"A6",x"C4",x"1E",x"C2",x"A6",x"C4", -- 0x3A10 + x"B9",x"C2",x"A6",x"00",x"FE",x"43",x"11",x"42", -- 0x3A18 + x"1E",x"42",x"11",x"C3",x"4D",x"41",x"37",x"42", -- 0x3A20 + x"81",x"42",x"11",x"C2",x"60",x"43",x"1E",x"00", -- 0x3A28 + x"FE",x"44",x"FB",x"1E",x"11",x"44",x"FA",x"42", -- 0x3A30 + x"4D",x"42",x"7A",x"6C",x"95",x"56",x"95",x"42", -- 0x3A38 + x"69",x"42",x"7A",x"56",x"95",x"42",x"60",x"42", -- 0x3A40 + x"7A",x"56",x"9B",x"42",x"60",x"42",x"7A",x"6C", -- 0x3A48 + x"9B",x"42",x"4D",x"42",x"7A",x"56",x"95",x"42", -- 0x3A50 + x"60",x"42",x"7A",x"61",x"9B",x"42",x"7A",x"4B", -- 0x3A58 + x"95",x"42",x"72",x"56",x"88",x"42",x"60",x"56", -- 0x3A60 + x"7A",x"42",x"4D",x"6C",x"72",x"56",x"72",x"42", -- 0x3A68 + x"72",x"56",x"88",x"42",x"7A",x"42",x"95",x"6C", -- 0x3A70 + x"A6",x"42",x"4D",x"42",x"72",x"6C",x"9B",x"42", -- 0x3A78 + x"7A",x"4B",x"95",x"4B",x"7A",x"42",x"72",x"4B", -- 0x3A80 + x"9B",x"4B",x"88",x"42",x"7A",x"42",x"95",x"56", -- 0x3A88 + x"A6",x"42",x"60",x"42",x"7A",x"56",x"9B",x"42", -- 0x3A90 + x"4D",x"42",x"7A",x"6C",x"95",x"42",x"4D",x"42", -- 0x3A98 + x"72",x"6C",x"88",x"6C",x"7A",x"6C",x"7A",x"00", -- 0x3AA0 + x"FE",x"41",x"FD",x"69",x"72",x"41",x"FC",x"FF", -- 0x3AA8 + x"57",x"41",x"FD",x"42",x"57",x"41",x"FC",x"01", -- 0x3AB0 + x"88",x"41",x"FD",x"95",x"88",x"41",x"FC",x"FF", -- 0x3AB8 + x"1E",x"41",x"FD",x"1E",x"11",x"41",x"FC",x"01", -- 0x3AC0 + x"E5",x"00",x"FE",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x3AC8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x3AD0 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x3AD8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x3AE0 + x"1E",x"C2",x"FF",x"C4",x"1E",x"C2",x"FF",x"C4", -- 0x3AE8 + x"1E",x"C2",x"FF",x"C4",x"1E",x"00",x"FE",x"F0", -- 0x3AF0 + x"41",x"41",x"53",x"53",x"FF",x"53",x"31",x"F0", -- 0x3AF8 + x"43",x"35",x"0F",x"12",x"12",x"12",x"54",x"52", -- 0x3B00 + x"51",x"F0",x"41",x"35",x"0F",x"15",x"35",x"FF", -- 0x3B08 + x"53",x"53",x"52",x"F0",x"52",x"53",x"41",x"00", -- 0x3B10 + x"FF",x"FF",x"57",x"00",x"80",x"FA",x"FF",x"57", -- 0x3B18 + x"32",x"32",x"32",x"32",x"32",x"32",x"F0",x"21", -- 0x3B20 + x"FF",x"12",x"0F",x"12",x"FF",x"21",x"F0",x"21", -- 0x3B28 + x"FF",x"12",x"0F",x"12",x"FF",x"21",x"F0",x"32", -- 0x3B30 + x"32",x"32",x"32",x"32",x"32",x"00",x"FF",x"7F", -- 0x3B38 + x"15",x"80",x"EA",x"7F",x"55",x"01",x"FF",x"FF", -- 0x3B40 + x"FF",x"21",x"21",x"F0",x"F0",x"21",x"0F",x"21", -- 0x3B48 + x"0F",x"FF",x"FF",x"00",x"FF",x"FF",x"EB",x"03", -- 0x3B50 + x"53",x"73",x"F0",x"52",x"FF",x"27",x"0F",x"0F", -- 0x3B58 + x"0F",x"0F",x"37",x"45",x"00",x"5F",x"D5",x"FF", -- 0x3B60 + x"18",x"2B",x"F7",x"2A",x"54",x"2B",x"46",x"2B", -- 0x3B68 + x"3E",x"2B",x"20",x"2B",x"65",x"2B",x"58",x"2B", -- 0x3B70 + x"52",x"31",x"51",x"61",x"F0",x"F0",x"61",x"51", -- 0x3B78 + x"31",x"52",x"00",x"FF",x"5F",x"05",x"53",x"21", -- 0x3B80 + x"52",x"F0",x"52",x"21",x"53",x"F0",x"52",x"21", -- 0x3B88 + x"53",x"00",x"FF",x"55",x"15",x"12",x"23",x"FF", -- 0x3B90 + x"21",x"41",x"F0",x"F0",x"41",x"21",x"FF",x"23", -- 0x3B98 + x"12",x"25",x"13",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x3BA0 + x"FF",x"FF",x"FF",x"0F",x"FF",x"FF",x"12",x"12", -- 0x3BA8 + x"FF",x"21",x"F0",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x3BB0 + x"FF",x"0F",x"83",x"2B",x"78",x"2B",x"92",x"2B", -- 0x3BB8 + x"86",x"2B",x"83",x"2B",x"78",x"2B",x"92",x"2B", -- 0x3BC0 + x"86",x"2B",x"A7",x"2B",x"95",x"2B",x"B7",x"2B", -- 0x3BC8 + x"AC",x"2B",x"A7",x"2B",x"95",x"2B",x"B7",x"2B", -- 0x3BD0 + x"AC",x"2B",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE0 + x"00",x"7E",x"00",x"FC",x"01",x"F8",x"03",x"F1", -- 0x3BE8 + x"1F",x"F3",x"3F",x"FF",x"FF",x"FF",x"3F",x"FF", -- 0x3BF0 + x"1F",x"F3",x"03",x"F1",x"01",x"F8",x"00",x"FC", -- 0x3BF8 + x"00",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C10 + x"2C",x"2C",x"3C",x"2C",x"24",x"2C",x"44",x"2C", -- 0x3C18 + x"4C",x"2C",x"34",x"2C",x"76",x"7F",x"7F",x"FE", -- 0x3C20 + x"FE",x"FF",x"7F",x"3A",x"00",x"00",x"1C",x"1E", -- 0x3C28 + x"3F",x"3F",x"3E",x"1E",x"38",x"7C",x"7C",x"FC", -- 0x3C30 + x"FC",x"78",x"00",x"00",x"40",x"E0",x"E0",x"60", -- 0x3C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"38", -- 0x3C40 + x"38",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C48 + x"02",x"07",x"07",x"02",x"00",x"00",x"00",x"2E", -- 0x3C50 + x"0C",x"2E",x"40",x"0C",x"2F",x"00",x"00",x"00", -- 0x3C58 + x"18",x"0C",x"2E",x"26",x"03",x"44",x"10",x"03", -- 0x3C60 + x"44",x"2A",x"0C",x"2F",x"22",x"03",x"44",x"10", -- 0x3C68 + x"03",x"44",x"2E",x"03",x"44",x"14",x"03",x"44", -- 0x3C70 + x"0C",x"03",x"44",x"02",x"03",x"44",x"04",x"03", -- 0x3C78 + x"44",x"0E",x"03",x"44",x"18",x"03",x"44",x"06", -- 0x3C80 + x"03",x"44",x"08",x"03",x"44",x"12",x"03",x"44", -- 0x3C88 + x"30",x"03",x"44",x"16",x"03",x"44",x"24",x"03", -- 0x3C90 + x"44",x"26",x"03",x"44",x"2C",x"0C",x"2C",x"0E", -- 0x3C98 + x"03",x"44",x"2C",x"03",x"44",x"40",x"0C",x"2D", -- 0x3CA0 + x"00",x"00",x"00",x"32",x"0C",x"2C",x"30",x"0C", -- 0x3CA8 + x"2D",x"00",x"00",x"00",x"38",x"7C",x"7C",x"FC", -- 0x3CB0 + x"FC",x"78",x"00",x"00",x"40",x"E0",x"E0",x"60", -- 0x3CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"18",x"38", -- 0x3CC0 + x"38",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC8 + x"02",x"07",x"07",x"02",x"00",x"00",x"00",x"2E", -- 0x3CD0 + x"0C",x"2E",x"40",x"0C",x"2F",x"00",x"00",x"00", -- 0x3CD8 + x"18",x"0C",x"2E",x"26",x"03",x"44",x"10",x"03", -- 0x3CE0 + x"44",x"2A",x"0C",x"2F",x"22",x"03",x"44",x"10", -- 0x3CE8 + x"03",x"44",x"2E",x"03",x"44",x"14",x"03",x"44", -- 0x3CF0 + x"0C",x"03",x"44",x"02",x"03",x"44",x"04",x"03", -- 0x3CF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3D98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3DF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x3FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/build_id.v new file mode 100644 index 00000000..0841f27d --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180108" +`define BUILD_TIME "220955" diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..138d85cb --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/galaxian.vhd @@ -0,0 +1,448 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + signal gfx_bank : std_logic; + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + I_BANK => gfx_bank, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + +-- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); + when "010" => gfx_bank <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..5a4d0094 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..01cee00a --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_inport.vhd @@ -0,0 +1,74 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN1 & I_COIN2; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..ec46308a --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mc_video.vhd @@ -0,0 +1,433 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + I_BANK : in std_logic; + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1H VID-Rom + k_rom : entity work.GALAXIAN_1H + port map ( + CLK => I_CLK_12M, + ADDR => I_BANK & W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + + -- 1K VID-Rom + h_rom : entity work.GALAXIAN_1K + port map( + CLK => I_CLK_12M, + ADDR => I_BANK & W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + ----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/Pisces_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/Pisces_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/README.txt b/Arcade/Galaxian Hardware/WarOfBugs_MiST/README.txt new file mode 100644 index 00000000..870c99c7 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: War of the Bugs port to MiST by Gehstock +-- 3 Januar 2018 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Galaxian hardware +-- Copyright(c) 2004 Katsumi Degawa +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- F2 : Coin + Start 2 players +-- F1 : Coin + Start 1 player +-- SPACE : Fire +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/Release/WarOfTheBugs.rbf b/Arcade/Galaxian Hardware/WarOfBugs_MiST/Release/WarOfTheBugs.rbf new file mode 100644 index 00000000..e38389f4 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/Release/WarOfTheBugs.rbf differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qpf b/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qpf new file mode 100644 index 00000000..323e0052 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:59:16 November 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "14:59:16 November 16, 2017" + +# Revisions + +PROJECT_REVISION = "WarOfTheBugs" \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qsf b/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qsf new file mode 100644 index 00000000..9213f729 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.qsf @@ -0,0 +1,190 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:12:35 November 17, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Galaxian_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sine_package.vhd +set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd +set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd +set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd +set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd +set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd +set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd +set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd +set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd +set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd +set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd +set_global_assignment -name VHDL_FILE rtl/galaxian.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY WarOfTheBugs +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(Galaxian) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Galaxian) +# -------------------- +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VHDL_FILE rtl/mc_video.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/WarOfTheBugs.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.srf b/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.srf new file mode 100644 index 00000000..14cddd5e --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/WarOfTheBugs.srf @@ -0,0 +1,54 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/clean.bat b/Arcade/Galaxian Hardware/WarOfBugs_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd new file mode 100644 index 00000000..a6558456 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd @@ -0,0 +1,285 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1H is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1H is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0158 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0160 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0168 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0170 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0178 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0180 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0188 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0190 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0198 + x"00",x"00",x"00",x"03",x"0F",x"1F",x"41",x"00", -- 0x01A0 + x"08",x"3C",x"FE",x"E7",x"8F",x"FE",x"FC",x"00", -- 0x01A8 + x"00",x"41",x"1F",x"0F",x"03",x"00",x"00",x"00", -- 0x01B0 + x"00",x"FC",x"FE",x"8F",x"E7",x"FE",x"3C",x"08", -- 0x01B8 + x"06",x"08",x"03",x"24",x"40",x"10",x"20",x"40", -- 0x01C0 + x"60",x"10",x"00",x"30",x"0A",x"21",x"10",x"00", -- 0x01C8 + x"88",x"A8",x"24",x"08",x"40",x"26",x"10",x"03", -- 0x01D0 + x"15",x"15",x"24",x"80",x"12",x"60",x"04",x"90", -- 0x01D8 + x"00",x"00",x"00",x"00",x"04",x"00",x"08",x"09", -- 0x01E0 + x"00",x"00",x"00",x"00",x"80",x"20",x"80",x"50", -- 0x01E8 + x"00",x"02",x"08",x"04",x"00",x"00",x"00",x"00", -- 0x01F0 + x"90",x"00",x"20",x"40",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"08",x"08",x"E5",x"15",x"15",x"3A", -- 0x0200 + x"00",x"00",x"80",x"90",x"20",x"4E",x"5F",x"BB", -- 0x0208 + x"3A",x"15",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0210 + x"A3",x"5B",x"4E",x"20",x"90",x"80",x"00",x"00", -- 0x0218 + x"00",x"00",x"01",x"22",x"14",x"15",x"15",x"3A", -- 0x0220 + x"00",x"00",x"20",x"48",x"90",x"2E",x"5F",x"BB", -- 0x0228 + x"3A",x"15",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0230 + x"A3",x"5B",x"2E",x"90",x"48",x"20",x"00",x"00", -- 0x0238 + x"10",x"48",x"2C",x"1C",x"06",x"02",x"00",x"00", -- 0x0240 + x"00",x"02",x"04",x"05",x"8E",x"2C",x"98",x"20", -- 0x0248 + x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0250 + x"00",x"40",x"33",x"8C",x"60",x"1E",x"C0",x"38", -- 0x0258 + x"11",x"0A",x"0E",x"04",x"06",x"02",x"00",x"00", -- 0x0260 + x"10",x"14",x"14",x"1C",x"8C",x"28",x"98",x"20", -- 0x0268 + x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0270 + x"01",x"42",x"3C",x"81",x"7E",x"00",x"84",x"78", -- 0x0278 + x"00",x"00",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x0280 + x"50",x"90",x"24",x"44",x"18",x"00",x"80",x"40", -- 0x0288 + x"00",x"06",x"06",x"00",x"01",x"01",x"00",x"00", -- 0x0290 + x"40",x"80",x"00",x"18",x"44",x"24",x"90",x"50", -- 0x0298 + x"00",x"06",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x02A0 + x"00",x"00",x"3C",x"40",x"1F",x"00",x"80",x"C0", -- 0x02A8 + x"00",x"06",x"06",x"00",x"01",x"01",x"06",x"00", -- 0x02B0 + x"C0",x"80",x"00",x"1F",x"40",x"38",x"00",x"00", -- 0x02B8 + x"00",x"FF",x"00",x"9F",x"CF",x"9F",x"00",x"FF", -- 0x02C0 + x"FF",x"FF",x"FF",x"C1",x"BE",x"BE",x"80",x"FF", -- 0x02C8 + x"88",x"77",x"00",x"FF",x"80",x"77",x"80",x"FF", -- 0x02D0 + x"BF",x"80",x"BF",x"FF",x"FE",x"FE",x"80",x"FF", -- 0x02D8 + x"FF",x"80",x"77",x"80",x"FF",x"7E",x"00",x"7E", -- 0x02E0 + x"FE",x"80",x"DE",x"FF",x"C9",x"B6",x"B6",x"C9", -- 0x02E8 + x"FF",x"00",x"CF",x"9F",x"00",x"FF",x"7E",x"76", -- 0x02F0 + x"FF",x"C1",x"B6",x"B6",x"CF",x"FE",x"80",x"DE", -- 0x02F8 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3C",x"1C",x"08", -- 0x0310 + x"00",x"00",x"00",x"00",x"00",x"80",x"80",x"80", -- 0x0318 + x"7C",x"FE",x"FE",x"C8",x"C0",x"FE",x"7E",x"3C", -- 0x0320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 + x"7E",x"FF",x"9F",x"DD",x"65",x"35",x"1C",x"08", -- 0x0330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 + x"7C",x"FE",x"FE",x"E2",x"C0",x"EE",x"7E",x"3C", -- 0x0340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 + x"7E",x"FF",x"EF",x"ED",x"79",x"38",x"38",x"10", -- 0x0350 + x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0358 + x"7C",x"FE",x"FC",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 + x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1C",x"08", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 + x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 + x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 + x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 + x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 + x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x0420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 + x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x0430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x0440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 + x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x0450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 + x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x0460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 + x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 + x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 + x"7E",x"FF",x"EF",x"E5",x"7D",x"3D",x"1C",x"08", -- 0x0490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 + x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x04A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 + x"7E",x"FF",x"9F",x"DD",x"65",x"34",x"1C",x"08", -- 0x04B0 + x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x04B8 + x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x04C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 + x"7E",x"FF",x"EF",x"E5",x"7C",x"3C",x"1C",x"08", -- 0x04D0 + x"00",x"00",x"00",x"00",x"80",x"40",x"40",x"00", -- 0x04D8 + x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x04E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 + x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1D",x"08", -- 0x04F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 + x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 + x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x05B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 + x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x05D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 + x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x05F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 + x"7F",x"3F",x"3F",x"1E",x"1C",x"0F",x"0F",x"07", -- 0x0610 + x"C0",x"00",x"E0",x"F0",x"E0",x"C0",x"80",x"00", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 + x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x0630 + x"7C",x"F0",x"FE",x"EF",x"CE",x"FC",x"F8",x"70", -- 0x0638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 + x"1C",x"18",x"18",x"1B",x"1F",x"0F",x"03",x"00", -- 0x0650 + x"18",x"7D",x"FD",x"CD",x"DE",x"DC",x"F8",x"70", -- 0x0658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 + x"08",x"1C",x"3D",x"7D",x"E7",x"EF",x"FF",x"7E", -- 0x0668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0678 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 + x"3C",x"3E",x"1E",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0690 + x"E0",x"70",x"78",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 + x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x06B0 + x"18",x"CC",x"CE",x"DE",x"FE",x"FC",x"F8",x"70", -- 0x06B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"1C",x"3E", -- 0x06C8 + x"00",x"00",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x06D0 + x"7F",x"FF",x"FF",x"FF",x"FE",x"FC",x"38",x"80", -- 0x06D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 + x"00",x"1C",x"3F",x"7F",x"EF",x"E7",x"F3",x"78", -- 0x06E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x06F8 + x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0700 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0708 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0710 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0718 + x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0720 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0728 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0730 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0738 + x"46",x"2F",x"1F",x"CF",x"3F",x"0F",x"3F",x"C6", -- 0x0740 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0748 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0760 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0768 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0770 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"09",x"17",x"3C",x"1B",x"3F",x"EF",x"DF",x"BF", -- 0x0780 + x"80",x"E0",x"F8",x"CC",x"F4",x"DE",x"EF",x"FF", -- 0x0788 + x"77",x"57",x"DB",x"77",x"3F",x"19",x"0F",x"04", -- 0x0790 + x"EA",x"EA",x"DB",x"7E",x"EC",x"9C",x"F8",x"40", -- 0x0798 + x"03",x"07",x"1F",x"1F",x"3B",x"3F",x"37",x"36", -- 0x07A0 + x"C0",x"E0",x"F0",x"F8",x"7C",x"DC",x"7C",x"AC", -- 0x07A8 + x"3F",x"3D",x"37",x"1B",x"1F",x"1F",x"0F",x"07", -- 0x07B0 + x"6C",x"FC",x"DC",x"BC",x"F8",x"F8",x"F0",x"E0", -- 0x07B8 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C0 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C8 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D0 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D8 + x"1E",x"3F",x"7E",x"00",x"00",x"7E",x"3F",x"1E", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd new file mode 100644 index 00000000..25f4acf1 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd @@ -0,0 +1,285 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_1K is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_1K is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0158 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0160 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0168 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0170 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0178 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0180 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0188 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0190 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0198 + x"00",x"00",x"00",x"00",x"01",x"00",x"5E",x"FF", -- 0x01A0 + x"00",x"00",x"18",x"7C",x"F4",x"78",x"00",x"F8", -- 0x01A8 + x"FF",x"5E",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x01B0 + x"F8",x"00",x"78",x"F4",x"7C",x"18",x"00",x"00", -- 0x01B8 + x"00",x"00",x"03",x"04",x"01",x"12",x"22",x"00", -- 0x01C0 + x"00",x"00",x"00",x"30",x"08",x"00",x"00",x"C0", -- 0x01C8 + x"02",x"21",x"20",x"10",x"00",x"06",x"00",x"00", -- 0x01D0 + x"44",x"04",x"04",x"00",x"10",x"60",x"00",x"00", -- 0x01D8 + x"02",x"00",x"00",x"10",x"10",x"20",x"00",x"01", -- 0x01E0 + x"C0",x"00",x"10",x"08",x"00",x"00",x"84",x"40", -- 0x01E8 + x"20",x"22",x"00",x"00",x"10",x"00",x"00",x"06", -- 0x01F0 + x"80",x"04",x"04",x"00",x"00",x"10",x"00",x"40", -- 0x01F8 + x"00",x"00",x"08",x"08",x"E5",x"15",x"42",x"2F", -- 0x0200 + x"00",x"00",x"80",x"90",x"20",x"40",x"84",x"DE", -- 0x0208 + x"05",x"42",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0210 + x"5E",x"84",x"40",x"20",x"90",x"80",x"00",x"00", -- 0x0218 + x"00",x"00",x"01",x"22",x"14",x"15",x"42",x"2F", -- 0x0220 + x"00",x"00",x"20",x"48",x"90",x"20",x"84",x"DE", -- 0x0228 + x"05",x"42",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0230 + x"5E",x"84",x"20",x"90",x"48",x"20",x"00",x"00", -- 0x0238 + x"10",x"48",x"2C",x"1C",x"06",x"03",x"01",x"03", -- 0x0240 + x"00",x"02",x"04",x"05",x"4E",x"CC",x"78",x"E0", -- 0x0248 + x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0250 + x"E0",x"E0",x"F3",x"CC",x"E0",x"9E",x"C0",x"38", -- 0x0258 + x"11",x"0A",x"0E",x"04",x"06",x"03",x"01",x"03", -- 0x0260 + x"10",x"14",x"14",x"1C",x"4C",x"C8",x"78",x"E0", -- 0x0268 + x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0270 + x"E1",x"E2",x"FC",x"C1",x"FE",x"80",x"84",x"78", -- 0x0278 + x"00",x"00",x"01",x"01",x"03",x"01",x"0B",x"0F", -- 0x0280 + x"50",x"90",x"24",x"C4",x"D8",x"E0",x"60",x"B0", -- 0x0288 + x"0F",x"0B",x"01",x"03",x"01",x"01",x"00",x"00", -- 0x0290 + x"B0",x"60",x"E0",x"D8",x"C4",x"24",x"90",x"50", -- 0x0298 + x"00",x"06",x"01",x"01",x"03",x"07",x"0D",x"0F", -- 0x02A0 + x"00",x"00",x"3C",x"C0",x"DF",x"E0",x"60",x"30", -- 0x02A8 + x"0F",x"0D",x"07",x"03",x"01",x"01",x"06",x"00", -- 0x02B0 + x"30",x"60",x"E0",x"DF",x"C0",x"38",x"00",x"00", -- 0x02B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02F8 + x"70",x"F8",x"FC",x"BE",x"9F",x"CC",x"78",x"30", -- 0x0300 + x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0308 + x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1D",x"09", -- 0x0310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 + x"70",x"F8",x"FC",x"BF",x"BF",x"CC",x"78",x"30", -- 0x0320 + x"00",x"00",x"00",x"00",x"C0",x"00",x"00",x"00", -- 0x0328 + x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"08", -- 0x0330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0338 + x"70",x"F8",x"CC",x"9C",x"BF",x"DC",x"78",x"30", -- 0x0340 + x"00",x"00",x"40",x"80",x"00",x"00",x"00",x"00", -- 0x0348 + x"78",x"FC",x"9E",x"DE",x"6A",x"39",x"39",x"12", -- 0x0350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 + x"70",x"F9",x"CE",x"8E",x"9C",x"FC",x"78",x"30", -- 0x0360 + x"C0",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 + x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"09", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0380 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0388 + x"70",x"F8",x"FC",x"BE",x"9E",x"CD",x"78",x"30", -- 0x0390 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0398 + x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x03A0 + x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x03A8 + x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x03B0 + x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x03B8 + x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x03C0 + x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x03C8 + x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x03D0 + x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x03D8 + x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x03E0 + x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 + x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x03F0 + x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 + x"78",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 + x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 + x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 + x"78",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 + x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 + x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 + x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 + x"78",x"FC",x"9E",x"DE",x"66",x"36",x"1E",x"0A", -- 0x0490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 + x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x04A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 + x"78",x"FC",x"EE",x"E6",x"7E",x"3D",x"1C",x"08", -- 0x04B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x04B8 + x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x04C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 + x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1C",x"09", -- 0x04D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x04D8 + x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x04E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 + x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1E",x"09", -- 0x04F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 + x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 + x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x05B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 + x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x05D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 + x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x05F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"70", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 + x"78",x"37",x"3F",x"1F",x"1F",x"0C",x"0D",x"07", -- 0x0610 + x"00",x"00",x"E0",x"30",x"60",x"C0",x"80",x"00", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 + x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0630 + x"00",x"30",x"7E",x"F3",x"F6",x"CC",x"D8",x"70", -- 0x0638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 + x"19",x"1F",x"1E",x"1D",x"1F",x"0F",x"07",x"06", -- 0x0650 + x"18",x"7C",x"FC",x"FC",x"B8",x"B0",x"D0",x"60", -- 0x0658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 + x"08",x"1C",x"34",x"64",x"DE",x"9E",x"FC",x"78", -- 0x0668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0678 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"32", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 + x"3F",x"3D",x"1D",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0690 + x"00",x"C0",x"E0",x"30",x"F8",x"F0",x"E0",x"C0", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 + x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x06B0 + x"60",x"30",x"7E",x"EE",x"CE",x"FC",x"F8",x"70", -- 0x06B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x06C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"9C",x"3E", -- 0x06C8 + x"01",x"03",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x06D0 + x"FE",x"FE",x"FE",x"FC",x"F8",x"F0",x"E0",x"FC", -- 0x06D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 + x"00",x"1C",x"3C",x"7E",x"FE",x"DE",x"CC",x"7F", -- 0x06E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"71",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x06F8 + x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0700 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0708 + x"1F",x"36",x"6F",x"FF",x"CF",x"C6",x"40",x"40", -- 0x0710 + x"80",x"C0",x"60",x"F0",x"30",x"30",x"20",x"20", -- 0x0718 + x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0720 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0728 + x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"20",x"20", -- 0x0730 + x"80",x"C0",x"60",x"F0",x"30",x"60",x"40",x"40", -- 0x0738 + x"44",x"2C",x"1C",x"CC",x"3C",x"0C",x"3C",x"C4", -- 0x0740 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0748 + x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"30",x"10", -- 0x0750 + x"80",x"C0",x"60",x"F0",x"30",x"60",x"C0",x"80", -- 0x0758 + x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0760 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0768 + x"1F",x"36",x"6F",x"FF",x"FF",x"76",x"19",x"06", -- 0x0770 + x"80",x"C0",x"60",x"F0",x"F0",x"E0",x"80",x"00", -- 0x0778 + x"0F",x"1F",x"3C",x"3B",x"7E",x"ED",x"DD",x"FF", -- 0x0780 + x"E0",x"F0",x"F8",x"CC",x"F6",x"FF",x"FF",x"3F", -- 0x0788 + x"FD",x"DE",x"DF",x"6F",x"7F",x"39",x"1F",x"07", -- 0x0790 + x"BB",x"FB",x"FB",x"FE",x"EE",x"9C",x"F8",x"C0", -- 0x0798 + x"01",x"07",x"1F",x"0F",x"2F",x"1F",x"3F",x"3E", -- 0x07A0 + x"00",x"E0",x"E0",x"F0",x"FC",x"FC",x"78",x"BC", -- 0x07A8 + x"1F",x"1D",x"3F",x"1F",x"0F",x"1F",x"0F",x"01", -- 0x07B0 + x"7C",x"F8",x"F8",x"FC",x"F8",x"E8",x"F0",x"A0", -- 0x07B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 + x"24",x"14",x"0C",x"3F",x"3F",x"0C",x"14",x"24", -- 0x07C8 + x"20",x"90",x"40",x"F0",x"F0",x"40",x"90",x"20", -- 0x07D0 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D8 + x"00",x"0C",x"14",x"FE",x"FE",x"14",x"0C",x"00", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd new file mode 100644 index 00000000..5aff2022 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_FIR is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_FIR is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62", + X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3", + X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91", + X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B", + X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29", + X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB", + X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1", + X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22", + X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44", + X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26", + X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3", + X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86", + X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90", + X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33", + X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9", + X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6", + X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA", + X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28", + X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA", + X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F", + X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67", + X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A", + X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89", + X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A", + X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74", + X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30", + X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F", + X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61", + X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20", + X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D", + X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35", + X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C", + X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd new file mode 100644 index 00000000..7d2fd29c --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GAL_HIT is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GAL_HIT is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6", + X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68", + X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B", + 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if; +end process; +end architecture; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat new file mode 100644 index 00000000..8d35a90e --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat @@ -0,0 +1,20 @@ +@echo off + + +copy /b/y warofbug.1j + warofbug.1k gfx1.bin > NUL +copy /b/y warofbug.u + warofbug.v + warofbug.w + warofbug.y + warofbug.z main.bin > NUL + + + +romgen warofbug.cla GALAXIAN_6L 5 a r e > GALAXIAN_6L.vhd + + +romgen gfx1.bin GFX1 12 a r e > GFX1.vhd +romgen main.bin ROM_PGM_0 14 a r e > ROM_PGM_0.vhd + +romgen warofbug.1j GALAXIAN_1H 11 a r e > GALAXIAN_1H.vhd +romgen warofbug.1k GALAXIAN_1K 11 a r e > GALAXIAN_1K.vhd + + +echo done +pause diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin new file mode 100644 index 00000000..3593689f Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin new file mode 100644 index 00000000..c5f46697 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe new file mode 100644 index 00000000..ab2427f2 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j new file mode 100644 index 00000000..d8c1edde Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k new file mode 100644 index 00000000..92d611b2 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla new file mode 100644 index 00000000..298d9068 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u new file mode 100644 index 00000000..8f554dec Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v new file mode 100644 index 00000000..ce7f3ea7 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w new file mode 100644 index 00000000..cfe60857 Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y new file mode 100644 index 00000000..03c2e3bf Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z new file mode 100644 index 00000000..d1ed656c Binary files /dev/null and b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z differ diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..c5c2e037 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1290 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ROM_PGM_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM_0 is + + + type ROM_ARRAY is array(0 to 10087) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"31",x"00",x"44",x"AF",x"C3",x"00",x"03",x"C3", -- 0x0000 + x"46",x"0B",x"55",x"50",x"4F",x"00",x"84",x"54", -- 0x0008 + x"77",x"23",x"10",x"FC",x"C9",x"06",x"C2",x"4C", -- 0x0010 + x"41",x"43",x"4B",x"4F",x"49",x"00",x"85",x"43", -- 0x0018 + x"C3",x"B4",x"04",x"45",x"00",x"10",x"00",x"05", -- 0x0020 + x"C3",x"0B",x"05",x"56",x"45",x"00",x"10",x"00", -- 0x0028 + x"85",x"42",x"49",x"4E",x"49",x"54",x"61",x"00", -- 0x0030 + x"C3",x"00",x"00",x"05",x"49",x"54",x"5E",x"00", -- 0x0038 + x"C3",x"00",x"10",x"41",x"4C",x"4F",x"C3",x"6A", -- 0x0040 + x"14",x"C3",x"7A",x"06",x"C3",x"EF",x"05",x"C3", -- 0x0048 + x"5C",x"03",x"C3",x"70",x"0C",x"C9",x"7B",x"15", -- 0x0050 + x"C3",x"BE",x"15",x"C3",x"46",x"0B",x"C3",x"F8", -- 0x0058 + x"0A",x"C3",x"6E",x"07",x"45",x"70",x"F5",x"AF", -- 0x0060 + x"32",x"01",x"70",x"08",x"3A",x"00",x"78",x"08", -- 0x0068 + x"C5",x"D5",x"E5",x"DD",x"E5",x"FD",x"E5",x"21", -- 0x0070 + x"00",x"43",x"11",x"00",x"58",x"01",x"80",x"00", -- 0x0078 + x"ED",x"B0",x"CD",x"FC",x"00",x"CD",x"CB",x"0C", -- 0x0080 + x"21",x"02",x"40",x"34",x"23",x"CD",x"77",x"05", -- 0x0088 + x"CD",x"D5",x"05",x"CD",x"46",x"00",x"CD",x"DD", -- 0x0090 + x"0A",x"CD",x"40",x"00",x"CD",x"85",x"06",x"3A", -- 0x0098 + x"10",x"40",x"F5",x"CB",x"47",x"28",x"05",x"CD", -- 0x00A0 + x"7D",x"05",x"18",x"0C",x"21",x"40",x"50",x"22", -- 0x00A8 + x"18",x"40",x"CD",x"92",x"07",x"CD",x"70",x"0B", -- 0x00B0 + x"F1",x"FD",x"E1",x"DD",x"E1",x"E1",x"D1",x"C1", -- 0x00B8 + x"3E",x"01",x"32",x"01",x"70",x"F1",x"C9",x"01", -- 0x00C0 + x"70",x"F1",x"C9",x"C1",x"3E",x"01",x"32",x"01", -- 0x00C8 + x"70",x"F1",x"C9",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 + x"C3",x"3E",x"03",x"00",x"00",x"C3",x"FD",x"14", -- 0x00D8 + x"C3",x"C1",x"0B",x"C3",x"12",x"01",x"C3",x"53", -- 0x00E0 + x"01",x"C3",x"8E",x"01",x"C3",x"B1",x"01",x"00", -- 0x00E8 + x"C3",x"00",x"0D",x"C9",x"00",x"1A",x"C3",x"08", -- 0x00F0 + x"0A",x"C3",x"59",x"21",x"C3",x"E1",x"21",x"00", -- 0x00F8 + x"02",x"10",x"06",x"52",x"45",x"41",x"44",x"59", -- 0x0100 + x"40",x"50",x"4C",x"41",x"59",x"45",x"52",x"40", -- 0x0108 + x"31",x"FF",x"11",x"00",x"00",x"3A",x"14",x"40", -- 0x0110 + x"CB",x"5F",x"28",x"06",x"DD",x"21",x"00",x"41", -- 0x0118 + x"18",x"04",x"DD",x"21",x"00",x"42",x"DD",x"7E", -- 0x0120 + x"08",x"B7",x"28",x"18",x"21",x"4B",x"01",x"5F", -- 0x0128 + x"19",x"7E",x"07",x"07",x"07",x"4F",x"21",x"05", -- 0x0130 + x"43",x"71",x"23",x"23",x"7D",x"FE",x"3F",x"38", -- 0x0138 + x"F8",x"DD",x"7E",x"08",x"3C",x"E6",x"07",x"DD", -- 0x0140 + x"77",x"08",x"C9",x"00",x"20",x"40",x"60",x"80", -- 0x0148 + x"A0",x"C0",x"E0",x"3A",x"14",x"40",x"01",x"00", -- 0x0150 + x"00",x"11",x"40",x"50",x"CB",x"5F",x"28",x"05", -- 0x0158 + x"21",x"10",x"41",x"18",x"03",x"21",x"10",x"42", -- 0x0160 + x"7D",x"FE",x"FD",x"30",x"1E",x"7A",x"FE",x"54", -- 0x0168 + x"28",x"19",x"78",x"FE",x"FF",x"0E",x"10",x"28", -- 0x0170 + x"08",x"1A",x"4F",x"E6",x"FC",x"FE",x"30",x"20", -- 0x0178 + x"06",x"70",x"23",x"71",x"23",x"06",x"00",x"13", -- 0x0180 + x"04",x"18",x"DD",x"36",x"00",x"C9",x"3A",x"14", -- 0x0188 + x"40",x"11",x"40",x"50",x"CB",x"5F",x"28",x"05", -- 0x0190 + x"21",x"10",x"41",x"18",x"03",x"21",x"10",x"42", -- 0x0198 + x"7A",x"FE",x"54",x"C8",x"7E",x"47",x"B7",x"C8", -- 0x01A0 + x"13",x"10",x"FD",x"23",x"7E",x"12",x"23",x"18", -- 0x01A8 + x"EF",x"0E",x"00",x"21",x"01",x"43",x"CD",x"36", -- 0x01B0 + x"01",x"3A",x"01",x"40",x"E6",x"F0",x"32",x"01", -- 0x01B8 + x"40",x"AF",x"21",x"00",x"60",x"06",x"00",x"D7", -- 0x01C0 + x"21",x"00",x"68",x"D7",x"3E",x"FF",x"32",x"00", -- 0x01C8 + x"78",x"3A",x"14",x"40",x"CB",x"5F",x"28",x"0A", -- 0x01D0 + x"DD",x"21",x"00",x"41",x"FD",x"21",x"00",x"42", -- 0x01D8 + x"18",x"08",x"DD",x"21",x"00",x"42",x"FD",x"21", -- 0x01E0 + x"00",x"41",x"CB",x"7F",x"20",x"73",x"DD",x"7E", -- 0x01E8 + x"09",x"3D",x"B7",x"28",x"2E",x"DD",x"77",x"09", -- 0x01F0 + x"DD",x"7E",x"0A",x"FE",x"0F",x"28",x"01",x"3C", -- 0x01F8 + x"DD",x"77",x"0A",x"F5",x"DD",x"7E",x"05",x"FE", -- 0x0200 + x"1A",x"30",x"08",x"DD",x"34",x"05",x"21",x"00", -- 0x0208 + x"23",x"7E",x"47",x"F1",x"B8",x"DA",x"CC",x"02", -- 0x0210 + x"DD",x"7E",x"06",x"CB",x"A7",x"DD",x"77",x"06", -- 0x0218 + x"C3",x"CC",x"02",x"AF",x"32",x"10",x"40",x"CD", -- 0x0220 + x"49",x"00",x"3E",x"C0",x"CD",x"4C",x"00",x"11", -- 0x0228 + x"D0",x"02",x"E7",x"3E",x"80",x"CD",x"4C",x"00", -- 0x0230 + x"31",x"00",x"44",x"21",x"03",x"41",x"06",x"F8", -- 0x0238 + x"AF",x"D7",x"21",x"03",x"42",x"06",x"F8",x"D7", -- 0x0240 + x"21",x"00",x"43",x"06",x"80",x"D7",x"21",x"1C", -- 0x0248 + x"1F",x"22",x"05",x"41",x"22",x"05",x"42",x"CD", -- 0x0250 + x"49",x"00",x"AF",x"32",x"2F",x"40",x"C3",x"D8", -- 0x0258 + x"00",x"DD",x"7E",x"09",x"3D",x"B7",x"28",x"3B", -- 0x0260 + x"DD",x"77",x"09",x"DD",x"7E",x"0A",x"3C",x"DD", -- 0x0268 + x"77",x"0A",x"3A",x"14",x"40",x"EE",x"18",x"32", -- 0x0270 + x"14",x"40",x"CD",x"49",x"00",x"CD",x"00",x"25", -- 0x0278 + x"3E",x"E0",x"CD",x"4C",x"00",x"11",x"DD",x"02", -- 0x0280 + x"E7",x"3A",x"14",x"40",x"CB",x"5F",x"28",x"0E", -- 0x0288 + x"11",x"E6",x"02",x"E7",x"3E",x"C0",x"CD",x"4C", -- 0x0290 + x"00",x"CD",x"49",x"00",x"18",x"2E",x"11",x"F3", -- 0x0298 + x"02",x"18",x"F0",x"11",x"D0",x"02",x"E7",x"3E", -- 0x02A0 + x"C0",x"CD",x"4C",x"00",x"3A",x"14",x"40",x"CB", -- 0x02A8 + x"5F",x"28",x"06",x"11",x"E6",x"02",x"E7",x"18", -- 0x02B0 + x"03",x"11",x"F3",x"02",x"E7",x"3E",x"C0",x"CD", -- 0x02B8 + x"4C",x"00",x"CD",x"49",x"00",x"3A",x"14",x"40", -- 0x02C0 + x"CB",x"BF",x"18",x"A9",x"CD",x"12",x"01",x"C9", -- 0x02C8 + x"04",x"0C",x"08",x"47",x"41",x"4D",x"45",x"40", -- 0x02D0 + x"4F",x"56",x"45",x"52",x"FF",x"05",x"0C",x"0C", -- 0x02D8 + x"52",x"45",x"41",x"44",x"59",x"FF",x"05",x"0E", -- 0x02E0 + x"0A",x"50",x"4C",x"41",x"59",x"45",x"52",x"40", -- 0x02E8 + x"40",x"31",x"FF",x"05",x"0E",x"0A",x"50",x"4C", -- 0x02F0 + x"41",x"59",x"45",x"52",x"40",x"40",x"32",x"FF", -- 0x02F8 + x"08",x"3A",x"00",x"78",x"08",x"AF",x"32",x"01", -- 0x0300 + x"70",x"21",x"00",x"50",x"3E",x"10",x"06",x"00", -- 0x0308 + x"D7",x"D7",x"D7",x"D7",x"08",x"3A",x"00",x"78", -- 0x0310 + x"08",x"21",x"00",x"58",x"AF",x"D7",x"08",x"3A", -- 0x0318 + x"00",x"78",x"08",x"21",x"00",x"68",x"D7",x"21", -- 0x0320 + x"00",x"60",x"D7",x"08",x"3A",x"00",x"78",x"08", -- 0x0328 + x"21",x"00",x"70",x"D7",x"21",x"00",x"40",x"AF", -- 0x0330 + x"D7",x"D7",x"D7",x"06",x"F8",x"D7",x"3E",x"FF", -- 0x0338 + x"32",x"00",x"78",x"08",x"3A",x"00",x"78",x"08", -- 0x0340 + x"21",x"FF",x"FF",x"22",x"C0",x"40",x"3E",x"01", -- 0x0348 + x"32",x"01",x"70",x"11",x"00",x"04",x"E7",x"CD", -- 0x0350 + x"84",x"07",x"18",x"23",x"21",x"00",x"50",x"22", -- 0x0358 + x"18",x"40",x"21",x"50",x"40",x"06",x"30",x"D7", -- 0x0360 + x"3E",x"08",x"32",x"11",x"40",x"CD",x"6E",x"07", -- 0x0368 + x"3E",x"01",x"32",x"01",x"70",x"3E",x"E0",x"CD", -- 0x0370 + x"EF",x"05",x"C9",x"AF",x"32",x"0C",x"40",x"3A", -- 0x0378 + x"10",x"40",x"CB",x"D7",x"CB",x"C7",x"32",x"10", -- 0x0380 + x"40",x"CD",x"C1",x"0B",x"C3",x"00",x"1E",x"00", -- 0x0388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"06",x"00",x"00",x"53",x"43",x"4F",x"52",x"45", -- 0x0400 + x"31",x"40",x"40",x"40",x"40",x"48",x"49",x"40", -- 0x0408 + x"53",x"43",x"4F",x"52",x"45",x"40",x"40",x"40", -- 0x0410 + x"40",x"53",x"43",x"4F",x"52",x"45",x"32",x"FF", -- 0x0418 + x"05",x"01",x"00",x"00",x"41",x"06",x"05",x"01", -- 0x0420 + x"0B",x"34",x"40",x"06",x"05",x"01",x"16",x"00", -- 0x0428 + x"42",x"06",x"03",x"14",x"0D",x"06",x"40",x"02", -- 0x0430 + x"06",x"10",x"0B",x"43",x"52",x"45",x"44",x"49", -- 0x0438 + x"54",x"FF",x"05",x"08",x"04",x"50",x"52",x"45", -- 0x0440 + x"53",x"53",x"40",x"31",x"40",x"50",x"4C",x"41", -- 0x0448 + x"59",x"45",x"52",x"40",x"42",x"55",x"54",x"54", -- 0x0450 + x"4F",x"4E",x"FF",x"05",x"08",x"02",x"50",x"55", -- 0x0458 + x"53",x"48",x"40",x"31",x"40",x"4F",x"52",x"40", -- 0x0460 + x"32",x"40",x"50",x"4C",x"41",x"59",x"45",x"52", -- 0x0468 + x"40",x"42",x"55",x"54",x"54",x"4F",x"4E",x"FF", -- 0x0470 + x"05",x"0C",x"04",x"49",x"4E",x"53",x"45",x"52", -- 0x0478 + x"54",x"40",x"41",x"4E",x"4F",x"54",x"48",x"45", -- 0x0480 + x"52",x"40",x"43",x"4F",x"49",x"4E",x"FF",x"03", -- 0x0488 + x"14",x"0A",x"46",x"52",x"45",x"45",x"40",x"50", -- 0x0490 + x"4C",x"41",x"59",x"FF",x"02",x"1E",x"04",x"40", -- 0x0498 + x"40",x"41",x"52",x"4D",x"40",x"40",x"40",x"40", -- 0x04A0 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"31", -- 0x04A8 + x"39",x"38",x"31",x"FF",x"F5",x"C5",x"D5",x"E5", -- 0x04B0 + x"D5",x"DD",x"E1",x"DD",x"7E",x"01",x"87",x"06", -- 0x04B8 + x"00",x"4F",x"FD",x"21",x"00",x"43",x"FD",x"09", -- 0x04C0 + x"FD",x"36",x"00",x"00",x"DD",x"7E",x"00",x"FD", -- 0x04C8 + x"77",x"01",x"DD",x"46",x"02",x"3E",x"1B",x"90", -- 0x04D0 + x"B7",x"CA",x"E7",x"04",x"21",x"40",x"50",x"01", -- 0x04D8 + x"20",x"00",x"09",x"3D",x"C2",x"E2",x"04",x"DD", -- 0x04E0 + x"4E",x"01",x"06",x"00",x"09",x"01",x"E0",x"FF", -- 0x04E8 + x"DD",x"23",x"DD",x"23",x"DD",x"23",x"DD",x"7E", -- 0x04F0 + x"00",x"FE",x"FF",x"28",x"09",x"D6",x"30",x"77", -- 0x04F8 + x"09",x"DD",x"23",x"C3",x"F6",x"04",x"E1",x"D1", -- 0x0500 + x"C1",x"F1",x"C9",x"F5",x"C5",x"D5",x"E5",x"D5", -- 0x0508 + x"DD",x"E1",x"DD",x"7E",x"01",x"87",x"06",x"00", -- 0x0510 + x"4F",x"FD",x"21",x"00",x"43",x"FD",x"09",x"FD", -- 0x0518 + x"36",x"00",x"00",x"DD",x"7E",x"00",x"FD",x"77", -- 0x0520 + x"01",x"DD",x"46",x"02",x"3E",x"1B",x"90",x"B7", -- 0x0528 + x"CA",x"40",x"05",x"FD",x"21",x"40",x"50",x"01", -- 0x0530 + x"20",x"00",x"FD",x"09",x"3D",x"C2",x"3A",x"05", -- 0x0538 + x"DD",x"4E",x"01",x"06",x"00",x"FD",x"09",x"01", -- 0x0540 + x"E0",x"FF",x"DD",x"56",x"05",x"DD",x"66",x"04", -- 0x0548 + x"DD",x"6E",x"03",x"CB",x"42",x"CA",x"62",x"05", -- 0x0550 + x"7E",x"E6",x"0F",x"FD",x"77",x"00",x"23",x"C3", -- 0x0558 + x"6C",x"05",x"7E",x"0F",x"0F",x"0F",x"0F",x"E6", -- 0x0560 + x"0F",x"FD",x"77",x"00",x"FD",x"09",x"15",x"C2", -- 0x0568 + x"53",x"05",x"E1",x"D1",x"C1",x"F1",x"C9",x"7E", -- 0x0570 + x"B7",x"C8",x"3C",x"77",x"C9",x"CD",x"70",x"0C", -- 0x0578 + x"3E",x"1C",x"32",x"0B",x"40",x"2A",x"18",x"40", -- 0x0580 + x"3A",x"05",x"40",x"47",x"CB",x"43",x"20",x"20", -- 0x0588 + x"E6",x"1F",x"11",x"00",x"00",x"5F",x"19",x"3A", -- 0x0590 + x"0B",x"40",x"47",x"7D",x"E6",x"1F",x"FE",x"03", -- 0x0598 + x"38",x"29",x"B8",x"30",x"26",x"7C",x"FE",x"53", -- 0x05A0 + x"30",x"13",x"36",x"32",x"22",x"18",x"40",x"C9", -- 0x05A8 + x"DD",x"A6",x"06",x"F5",x"DD",x"7E",x"05",x"32", -- 0x05B0 + x"0B",x"40",x"F1",x"18",x"D5",x"7D",x"FE",x"BF", -- 0x05B8 + x"38",x"E8",x"3A",x"10",x"40",x"CB",x"87",x"32", -- 0x05C0 + x"10",x"40",x"C9",x"11",x"16",x"00",x"7D",x"E6", -- 0x05C8 + x"F0",x"6F",x"19",x"18",x"D0",x"3A",x"00",x"40", -- 0x05D0 + x"5F",x"3A",x"01",x"40",x"57",x"0F",x"AB",x"5F", -- 0x05D8 + x"ED",x"57",x"83",x"AA",x"07",x"07",x"07",x"AA", -- 0x05E0 + x"83",x"32",x"05",x"40",x"C9",x"3E",x"80",x"32", -- 0x05E8 + x"03",x"40",x"3A",x"03",x"40",x"B7",x"C8",x"18", -- 0x05F0 + x"F9",x"21",x"02",x"50",x"3E",x"10",x"06",x"1E", -- 0x05F8 + x"D7",x"11",x"02",x"00",x"19",x"7C",x"FE",x"54", -- 0x0600 + x"20",x"F2",x"AF",x"21",x"02",x"43",x"06",x"7D", -- 0x0608 + x"D7",x"C9",x"AF",x"21",x"40",x"40",x"06",x"A0", -- 0x0610 + x"D7",x"21",x"02",x"43",x"06",x"7C",x"D7",x"08", -- 0x0618 + x"3A",x"00",x"78",x"08",x"21",x"02",x"58",x"06", -- 0x0620 + x"7C",x"D7",x"21",x"00",x"60",x"06",x"07",x"D7", -- 0x0628 + x"21",x"00",x"68",x"06",x"07",x"D7",x"3E",x"FF", -- 0x0630 + x"32",x"00",x"78",x"C9",x"3A",x"00",x"60",x"CB", -- 0x0638 + x"47",x"28",x"06",x"3E",x"01",x"32",x"08",x"40", -- 0x0640 + x"C9",x"3A",x"08",x"40",x"B7",x"C8",x"3A",x"07", -- 0x0648 + x"40",x"3C",x"32",x"07",x"40",x"AF",x"32",x"08", -- 0x0650 + x"40",x"3A",x"10",x"40",x"E6",x"18",x"B7",x"C0", -- 0x0658 + x"CD",x"7A",x"06",x"3A",x"10",x"40",x"CB",x"57", -- 0x0660 + x"C0",x"AF",x"32",x"0C",x"40",x"3E",x"04",x"32", -- 0x0668 + x"10",x"40",x"AF",x"32",x"03",x"40",x"CD",x"EC", -- 0x0670 + x"0B",x"C9",x"CD",x"F9",x"05",x"CD",x"12",x"06", -- 0x0678 + x"11",x"66",x"0C",x"E7",x"C9",x"CD",x"3C",x"06", -- 0x0680 + x"3A",x"10",x"40",x"47",x"E6",x"18",x"5F",x"3A", -- 0x0688 + x"06",x"40",x"4F",x"3A",x"07",x"40",x"81",x"B7", -- 0x0690 + x"C8",x"3A",x"0F",x"00",x"B7",x"20",x"08",x"3A", -- 0x0698 + x"06",x"40",x"B7",x"20",x"02",x"18",x"0C",x"3A", -- 0x06A0 + x"00",x"68",x"E6",x"C0",x"FE",x"C0",x"28",x"7C", -- 0x06A8 + x"B7",x"28",x"70",x"7B",x"B7",x"3A",x"07",x"40", -- 0x06B0 + x"20",x"05",x"FE",x"01",x"CC",x"33",x"07",x"FE", -- 0x06B8 + x"02",x"20",x"0A",x"79",x"3C",x"27",x"32",x"06", -- 0x06C0 + x"40",x"AF",x"32",x"07",x"40",x"3A",x"2F",x"40", -- 0x06C8 + x"B7",x"C0",x"3A",x"06",x"40",x"FE",x"01",x"28", -- 0x06D0 + x"68",x"FE",x"02",x"D4",x"59",x"07",x"21",x"40", -- 0x06D8 + x"40",x"AF",x"06",x"14",x"D7",x"11",x"38",x"04", -- 0x06E0 + x"E7",x"11",x"9C",x"04",x"E7",x"3E",x"2B",x"32", -- 0x06E8 + x"9E",x"53",x"11",x"32",x"04",x"EF",x"3A",x"00", -- 0x06F0 + x"40",x"CB",x"5F",x"28",x"18",x"21",x"0F",x"43", -- 0x06F8 + x"06",x"10",x"34",x"23",x"23",x"10",x"FB",x"CD", -- 0x0700 + x"EC",x"0B",x"CD",x"84",x"07",x"3A",x"00",x"60", -- 0x0708 + x"CB",x"67",x"C2",x"15",x"07",x"3E",x"01",x"31", -- 0x0710 + x"00",x"44",x"32",x"01",x"70",x"AF",x"32",x"04", -- 0x0718 + x"70",x"18",x"FE",x"3A",x"07",x"40",x"FE",x"01", -- 0x0720 + x"28",x"99",x"18",x"A1",x"3E",x"04",x"32",x"06", -- 0x0728 + x"40",x"18",x"9A",x"CB",x"48",x"C0",x"3A",x"2F", -- 0x0730 + x"40",x"B7",x"20",x"18",x"11",x"78",x"04",x"18", -- 0x0738 + x"12",x"11",x"42",x"04",x"3A",x"00",x"68",x"CB", -- 0x0740 + x"47",x"28",x"05",x"3E",x"40",x"32",x"13",x"40", -- 0x0748 + x"E7",x"18",x"8B",x"E7",x"AF",x"32",x"04",x"70", -- 0x0750 + x"C9",x"11",x"5B",x"04",x"3A",x"00",x"68",x"CB", -- 0x0758 + x"47",x"20",x"E8",x"CB",x"4F",x"28",x"EC",x"3E", -- 0x0760 + x"C0",x"32",x"13",x"40",x"18",x"E5",x"FD",x"21", -- 0x0768 + x"50",x"40",x"FD",x"36",x"00",x"10",x"FD",x"36", -- 0x0770 + x"01",x"E0",x"FD",x"36",x"05",x"0D",x"3E",x"26", -- 0x0778 + x"32",x"44",x"40",x"C9",x"3A",x"00",x"70",x"E6", -- 0x0780 + x"03",x"C6",x"01",x"32",x"09",x"41",x"32",x"09", -- 0x0788 + x"42",x"C9",x"CD",x"E2",x"07",x"3A",x"43",x"40", -- 0x0790 + x"32",x"7D",x"43",x"32",x"79",x"43",x"3A",x"44", -- 0x0798 + x"40",x"4F",x"3A",x"0F",x"40",x"B7",x"28",x"03", -- 0x07A0 + x"79",x"2F",x"4F",x"79",x"32",x"7F",x"43",x"D6", -- 0x07A8 + x"05",x"32",x"7B",x"43",x"CD",x"00",x"0D",x"C9", -- 0x07B0 + x"3A",x"10",x"40",x"E6",x"18",x"C8",x"CB",x"5F", -- 0x07B8 + x"28",x"05",x"21",x"09",x"41",x"18",x"03",x"21", -- 0x07C0 + x"09",x"42",x"7E",x"3D",x"B7",x"C8",x"47",x"21", -- 0x07C8 + x"DF",x"50",x"11",x"E0",x"FF",x"36",x"FC",x"19", -- 0x07D0 + x"10",x"FB",x"C9",x"21",x"00",x"00",x"22",x"43", -- 0x07D8 + x"40",x"C9",x"FD",x"21",x"43",x"40",x"CD",x"A6", -- 0x07E0 + x"08",x"3A",x"42",x"40",x"FE",x"FA",x"20",x"06", -- 0x07E8 + x"F5",x"AF",x"32",x"05",x"68",x"F1",x"B7",x"28", -- 0x07F0 + x"04",x"3C",x"32",x"42",x"40",x"3A",x"10",x"40", -- 0x07F8 + x"CB",x"4F",x"20",x"D7",x"CD",x"0D",x"09",x"3A", -- 0x0800 + x"50",x"40",x"B7",x"C8",x"3A",x"41",x"40",x"B7", -- 0x0808 + x"20",x"4E",x"3A",x"10",x"40",x"5F",x"3A",x"0F", -- 0x0810 + x"40",x"57",x"CB",x"53",x"C2",x"9F",x"08",x"3A", -- 0x0818 + x"42",x"40",x"B7",x"20",x"14",x"7A",x"B7",x"20", -- 0x0820 + x"05",x"3A",x"00",x"60",x"18",x"07",x"CB",x"63", -- 0x0828 + x"28",x"F7",x"3A",x"00",x"68",x"CB",x"67",x"20", -- 0x0830 + x"16",x"3A",x"50",x"40",x"C6",x"07",x"32",x"43", -- 0x0838 + x"40",x"3A",x"51",x"40",x"2F",x"D6",x"06",x"32", -- 0x0840 + x"44",x"40",x"AF",x"32",x"05",x"68",x"C9",x"3E", -- 0x0848 + x"01",x"32",x"41",x"40",x"32",x"05",x"68",x"CD", -- 0x0850 + x"75",x"08",x"3E",x"F8",x"32",x"42",x"40",x"C9", -- 0x0858 + x"3A",x"50",x"40",x"C6",x"07",x"32",x"43",x"40", -- 0x0860 + x"3A",x"44",x"40",x"FE",x"D8",x"30",x"2A",x"C6", -- 0x0868 + x"08",x"32",x"44",x"40",x"C9",x"3A",x"10",x"40", -- 0x0870 + x"CB",x"5F",x"28",x"06",x"FD",x"21",x"00",x"41", -- 0x0878 + x"18",x"04",x"FD",x"21",x"00",x"42",x"FD",x"34", -- 0x0880 + x"04",x"11",x"B7",x"0C",x"1A",x"FD",x"BE",x"04", -- 0x0888 + x"C0",x"FD",x"36",x"04",x"00",x"FD",x"34",x"0A", -- 0x0890 + x"C9",x"AF",x"32",x"41",x"40",x"18",x"9A",x"3E", -- 0x0898 + x"01",x"32",x"41",x"40",x"18",x"93",x"E5",x"D5", -- 0x08A0 + x"FD",x"7E",x"00",x"2F",x"CB",x"3F",x"CB",x"3F", -- 0x08A8 + x"CB",x"3F",x"FD",x"77",x"02",x"FD",x"7E",x"01", -- 0x08B0 + x"2F",x"CB",x"3F",x"CB",x"3F",x"CB",x"3F",x"FD", -- 0x08B8 + x"77",x"03",x"21",x"00",x"00",x"11",x"20",x"00", -- 0x08C0 + x"FD",x"7E",x"02",x"B7",x"28",x"04",x"19",x"3D", -- 0x08C8 + x"18",x"F9",x"11",x"00",x"50",x"FD",x"7E",x"03", -- 0x08D0 + x"5F",x"19",x"11",x"01",x"00",x"B7",x"ED",x"52", -- 0x08D8 + x"FD",x"75",x"04",x"FD",x"74",x"05",x"7E",x"FD", -- 0x08E0 + x"77",x"06",x"B7",x"D1",x"E1",x"C9",x"3A",x"00", -- 0x08E8 + x"40",x"4F",x"DD",x"7E",x"05",x"E6",x"3E",x"57", -- 0x08F0 + x"DD",x"36",x"05",x"0E",x"CD",x"11",x"0A",x"DD", -- 0x08F8 + x"36",x"04",x"00",x"C3",x"83",x"09",x"3E",x"01", -- 0x0900 + x"32",x"1D",x"40",x"18",x"35",x"CD",x"70",x"0B", -- 0x0908 + x"CD",x"91",x"0A",x"3A",x"41",x"40",x"B7",x"C8", -- 0x0910 + x"FD",x"21",x"43",x"40",x"CD",x"A6",x"08",x"DD", -- 0x0918 + x"21",x"56",x"40",x"06",x"07",x"C5",x"DD",x"66", -- 0x0920 + x"03",x"DD",x"6E",x"02",x"DD",x"7E",x"05",x"E6", -- 0x0928 + x"3E",x"FE",x"10",x"38",x"58",x"FE",x"16",x"38", -- 0x0930 + x"CD",x"DD",x"7E",x"04",x"E6",x"3F",x"FE",x"18", -- 0x0938 + x"38",x"4B",x"DD",x"7E",x"01",x"4F",x"3A",x"0F", -- 0x0940 + x"40",x"B7",x"FD",x"7E",x"01",x"20",x"01",x"2F", -- 0x0948 + x"C6",x"04",x"91",x"FE",x"18",x"30",x"36",x"DD", -- 0x0950 + x"4E",x"00",x"3A",x"50",x"40",x"D6",x"08",x"91", -- 0x0958 + x"C6",x"06",x"FE",x"0C",x"30",x"27",x"CD",x"99", -- 0x0960 + x"08",x"CD",x"A6",x"08",x"3A",x"1D",x"40",x"B7", -- 0x0968 + x"C2",x"EE",x"08",x"DD",x"7E",x"05",x"E6",x"80", -- 0x0970 + x"4F",x"CD",x"58",x"00",x"E5",x"16",x"50",x"CD", -- 0x0978 + x"11",x"0A",x"E1",x"3E",x"01",x"32",x"1C",x"40", -- 0x0980 + x"3E",x"F0",x"32",x"03",x"40",x"AF",x"32",x"1D", -- 0x0988 + x"40",x"C1",x"11",x"06",x"00",x"DD",x"19",x"10", -- 0x0990 + x"8C",x"2A",x"47",x"40",x"7E",x"FE",x"10",x"20", -- 0x0998 + x"05",x"2B",x"7E",x"FE",x"10",x"C8",x"57",x"D5", -- 0x09A0 + x"FE",x"30",x"28",x"3F",x"FE",x"2C",x"28",x"3B", -- 0x09A8 + x"FE",x"F8",x"28",x"37",x"3D",x"77",x"3E",x"01", -- 0x09B0 + x"32",x"1C",x"40",x"3E",x"FC",x"32",x"03",x"40", -- 0x09B8 + x"FD",x"7E",x"00",x"D6",x"08",x"67",x"3A",x"0F", -- 0x09C0 + x"40",x"B7",x"FD",x"7E",x"01",x"20",x"01",x"2F", -- 0x09C8 + x"D6",x"18",x"6F",x"0E",x"0E",x"CD",x"46",x"0B", -- 0x09D0 + x"CD",x"99",x"08",x"D1",x"7A",x"E6",x"FC",x"FE", -- 0x09D8 + x"F8",x"28",x"04",x"CD",x"15",x"0A",x"C9",x"CD", -- 0x09E0 + x"11",x"0A",x"C9",x"36",x"10",x"18",x"C7",x"DD", -- 0x09E8 + x"E5",x"DD",x"21",x"87",x"0C",x"DD",x"7E",x"00", -- 0x09F0 + x"BA",x"20",x"07",x"DD",x"7E",x"01",x"DD",x"E1", -- 0x09F8 + x"C9",x"C9",x"DD",x"23",x"DD",x"23",x"18",x"ED", -- 0x0A00 + x"3A",x"14",x"40",x"0E",x"00",x"FD",x"E5",x"18", -- 0x0A08 + x"0B",x"0E",x"01",x"18",x"02",x"0E",x"00",x"FD", -- 0x0A10 + x"E5",x"3A",x"10",x"40",x"E6",x"18",x"B7",x"28", -- 0x0A18 + x"4B",x"CB",x"5F",x"20",x"66",x"FD",x"21",x"00", -- 0x0A20 + x"42",x"CD",x"EF",x"09",x"CB",x"41",x"20",x"0D", -- 0x0A28 + x"32",x"A8",x"40",x"32",x"39",x"40",x"5F",x"AF", -- 0x0A30 + x"32",x"38",x"40",x"18",x"0D",x"32",x"38",x"40", -- 0x0A38 + x"32",x"A9",x"40",x"5F",x"AF",x"32",x"39",x"40", -- 0x0A40 + x"18",x"34",x"FD",x"7E",x"02",x"B7",x"83",x"27", -- 0x0A48 + x"FD",x"77",x"02",x"30",x"17",x"FD",x"7E",x"01", -- 0x0A50 + x"B7",x"3C",x"27",x"FD",x"77",x"01",x"30",x"0C", -- 0x0A58 + x"FD",x"7E",x"00",x"3C",x"B7",x"27",x"FD",x"77", -- 0x0A60 + x"00",x"FD",x"34",x"0A",x"FD",x"E1",x"3A",x"10", -- 0x0A68 + x"40",x"E6",x"18",x"B7",x"C8",x"11",x"BE",x"0C", -- 0x0A70 + x"E7",x"11",x"B8",x"0C",x"EF",x"C9",x"FD",x"7E", -- 0x0A78 + x"01",x"B7",x"83",x"27",x"FD",x"77",x"01",x"30", -- 0x0A80 + x"E3",x"18",x"D5",x"FD",x"21",x"00",x"41",x"18", -- 0x0A88 + x"98",x"E5",x"D5",x"C5",x"FD",x"7E",x"05",x"DD", -- 0x0A90 + x"77",x"01",x"FD",x"7E",x"00",x"DD",x"77",x"00", -- 0x0A98 + x"C6",x"10",x"2F",x"CB",x"3F",x"CB",x"3F",x"CB", -- 0x0AA0 + x"3F",x"4F",x"FD",x"7E",x"01",x"DD",x"77",x"03", -- 0x0AA8 + x"C6",x"08",x"CB",x"3F",x"CB",x"3F",x"CB",x"3F", -- 0x0AB0 + x"47",x"21",x"00",x"00",x"11",x"20",x"00",x"79", -- 0x0AB8 + x"B7",x"28",x"04",x"19",x"3D",x"18",x"F9",x"11", -- 0x0AC0 + x"00",x"50",x"78",x"5F",x"19",x"11",x"01",x"00", -- 0x0AC8 + x"B7",x"ED",x"52",x"FD",x"75",x"02",x"FD",x"74", -- 0x0AD0 + x"03",x"C1",x"D1",x"E1",x"C9",x"DD",x"21",x"40", -- 0x0AD8 + x"43",x"11",x"04",x"00",x"FD",x"21",x"50",x"40", -- 0x0AE0 + x"06",x"08",x"CD",x"91",x"0A",x"FD",x"19",x"DD", -- 0x0AE8 + x"19",x"FD",x"23",x"FD",x"23",x"10",x"F3",x"C9", -- 0x0AF0 + x"DD",x"E5",x"FD",x"E5",x"E5",x"C5",x"F5",x"21", -- 0x0AF8 + x"56",x"40",x"06",x"23",x"AF",x"D7",x"3A",x"05", -- 0x0B00 + x"40",x"FE",x"30",x"38",x"04",x"FE",x"D0",x"38", -- 0x0B08 + x"02",x"3E",x"80",x"67",x"2E",x"00",x"DD",x"21", -- 0x0B10 + x"40",x"0B",x"DD",x"4E",x"00",x"06",x"06",x"CD", -- 0x0B18 + x"46",x"0B",x"DD",x"7E",x"00",x"FD",x"77",x"04", -- 0x0B20 + x"FD",x"77",x"05",x"DD",x"23",x"7C",x"C6",x"10", -- 0x0B28 + x"67",x"10",x"EC",x"3A",x"10",x"40",x"CB",x"C7", -- 0x0B30 + x"F1",x"C1",x"E1",x"FD",x"E1",x"DD",x"E1",x"C9", -- 0x0B38 + x"18",x"1C",x"1C",x"1C",x"1C",x"20",x"C5",x"06", -- 0x0B40 + x"07",x"FD",x"21",x"56",x"40",x"11",x"06",x"00", -- 0x0B48 + x"FD",x"7E",x"00",x"B7",x"20",x"13",x"FD",x"7E", -- 0x0B50 + x"05",x"B7",x"20",x"0D",x"FD",x"74",x"00",x"FD", -- 0x0B58 + x"75",x"01",x"FD",x"71",x"05",x"C1",x"3E",x"01", -- 0x0B60 + x"C9",x"FD",x"19",x"10",x"E3",x"AF",x"C1",x"C9", -- 0x0B68 + x"FD",x"21",x"50",x"40",x"06",x"08",x"11",x"06", -- 0x0B70 + x"00",x"FD",x"7E",x"00",x"B7",x"28",x"30",x"FD", -- 0x0B78 + x"7E",x"05",x"E6",x"FE",x"FE",x"0E",x"20",x"27", -- 0x0B80 + x"FE",x"3C",x"28",x"28",x"3A",x"03",x"40",x"B7", -- 0x0B88 + x"20",x"0F",x"AF",x"FD",x"77",x"00",x"FD",x"77", -- 0x0B90 + x"01",x"FD",x"77",x"05",x"32",x"1C",x"40",x"18", -- 0x0B98 + x"0E",x"FE",x"FC",x"30",x"06",x"FD",x"36",x"05", -- 0x0BA0 + x"0E",x"18",x"04",x"FD",x"36",x"05",x"0F",x"FD", -- 0x0BA8 + x"19",x"10",x"C6",x"C9",x"3A",x"03",x"40",x"FE", -- 0x0BB0 + x"E8",x"20",x"F4",x"FD",x"36",x"05",x"3D",x"18", -- 0x0BB8 + x"EE",x"3A",x"00",x"40",x"4F",x"3A",x"14",x"40", -- 0x0BC0 + x"E6",x"1C",x"B7",x"C8",x"CB",x"57",x"20",x"1C", -- 0x0BC8 + x"CB",x"5F",x"20",x"25",x"21",x"02",x"42",x"79", -- 0x0BD0 + x"CB",x"61",x"20",x"10",x"11",x"5C",x"0C",x"E7", -- 0x0BD8 + x"11",x"66",x"0C",x"E7",x"CD",x"0F",x"0C",x"CD", -- 0x0BE0 + x"B8",x"07",x"C9",x"C9",x"11",x"20",x"04",x"EF", -- 0x0BE8 + x"11",x"26",x"04",x"EF",x"11",x"2C",x"04",x"EF", -- 0x0BF0 + x"C9",x"21",x"02",x"41",x"CB",x"61",x"20",x"EC", -- 0x0BF8 + x"11",x"52",x"0C",x"E7",x"11",x"66",x"0C",x"E7", -- 0x0C00 + x"CD",x"0F",x"0C",x"CD",x"B8",x"07",x"C9",x"3A", -- 0x0C08 + x"10",x"40",x"CB",x"5F",x"28",x"06",x"DD",x"21", -- 0x0C10 + x"00",x"41",x"18",x"04",x"DD",x"21",x"00",x"42", -- 0x0C18 + x"3A",x"34",x"40",x"06",x"03",x"DD",x"BE",x"00", -- 0x0C20 + x"38",x"16",x"05",x"3A",x"35",x"40",x"DD",x"BE", -- 0x0C28 + x"01",x"38",x"0D",x"05",x"3A",x"36",x"40",x"DD", -- 0x0C30 + x"BE",x"02",x"38",x"04",x"CD",x"F9",x"00",x"C9", -- 0x0C38 + x"DD",x"E5",x"E1",x"23",x"23",x"11",x"36",x"40", -- 0x0C40 + x"7E",x"12",x"2B",x"1B",x"10",x"FA",x"CD",x"F9", -- 0x0C48 + x"00",x"C9",x"05",x"01",x"00",x"40",x"40",x"40", -- 0x0C50 + x"40",x"40",x"40",x"FF",x"05",x"01",x"16",x"40", -- 0x0C58 + x"40",x"40",x"40",x"40",x"40",x"FF",x"07",x"1F", -- 0x0C60 + x"16",x"40",x"40",x"40",x"40",x"40",x"40",x"FF", -- 0x0C68 + x"AB",x"3A",x"14",x"40",x"E6",x"18",x"C8",x"1E", -- 0x0C70 + x"01",x"CB",x"5F",x"28",x"05",x"DD",x"21",x"00", -- 0x0C78 + x"41",x"C9",x"DD",x"21",x"00",x"42",x"C9",x"32", -- 0x0C80 + x"40",x"31",x"30",x"30",x"20",x"2F",x"40",x"2E", -- 0x0C88 + x"80",x"2D",x"60",x"2C",x"40",x"F8",x"09",x"F9", -- 0x0C90 + x"09",x"FA",x"09",x"FB",x"09",x"00",x"00",x"00", -- 0x0C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 + x"00",x"50",x"01",x"10",x"02",x"11",x"04",x"12", -- 0x0CA8 + x"06",x"13",x"06",x"14",x"50",x"15",x"50",x"60", -- 0x0CB0 + x"07",x"1F",x"0C",x"38",x"40",x"04",x"07",x"1F", -- 0x0CB8 + x"02",x"48",x"49",x"54",x"40",x"56",x"41",x"4C", -- 0x0CC0 + x"55",x"45",x"FF",x"2A",x"00",x"40",x"23",x"22", -- 0x0CC8 + x"00",x"40",x"3A",x"10",x"40",x"B7",x"CC",x"EC", -- 0x0CD0 + x"0B",x"C9",x"04",x"32",x"01",x"40",x"C9",x"CB", -- 0x0CD8 + x"BF",x"18",x"F8",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 + x"FD",x"21",x"50",x"40",x"0E",x"FF",x"3A",x"10", -- 0x0D00 + x"40",x"47",x"E6",x"1C",x"B7",x"C8",x"CB",x"50", -- 0x0D08 + x"C2",x"CE",x"0D",x"0E",x"00",x"CB",x"58",x"28", -- 0x0D10 + x"05",x"CD",x"80",x"0D",x"18",x"0E",x"3A",x"0F", -- 0x0D18 + x"40",x"B7",x"20",x"05",x"CD",x"80",x"0D",x"18", -- 0x0D20 + x"03",x"CD",x"A6",x"0D",x"79",x"CD",x"43",x"0D", -- 0x0D28 + x"CD",x"46",x"0E",x"CD",x"62",x"0D",x"3A",x"32", -- 0x0D30 + x"40",x"B7",x"20",x"03",x"CD",x"62",x"0D",x"FD", -- 0x0D38 + x"71",x"04",x"C9",x"FD",x"7E",x"00",x"FE",x"14", -- 0x0D40 + x"30",x"02",x"CB",x"A1",x"FE",x"E2",x"38",x"02", -- 0x0D48 + x"CB",x"99",x"FD",x"7E",x"01",x"FE",x"A0",x"30", -- 0x0D50 + x"02",x"CB",x"B1",x"FE",x"E6",x"38",x"02",x"CB", -- 0x0D58 + x"A9",x"C9",x"CB",x"59",x"28",x"05",x"FD",x"34", -- 0x0D60 + x"00",x"18",x"07",x"CB",x"61",x"28",x"03",x"FD", -- 0x0D68 + x"35",x"00",x"CB",x"69",x"28",x"03",x"FD",x"34", -- 0x0D70 + x"01",x"CB",x"71",x"C8",x"FD",x"35",x"01",x"C9", -- 0x0D78 + x"3A",x"00",x"60",x"CB",x"57",x"28",x"02",x"CB", -- 0x0D80 + x"E1",x"CB",x"5F",x"28",x"02",x"CB",x"D9",x"CB", -- 0x0D88 + x"77",x"28",x"02",x"CB",x"E9",x"CB",x"7F",x"28", -- 0x0D90 + x"02",x"CB",x"F1",x"79",x"B7",x"28",x"04",x"06", -- 0x0D98 + x"01",x"79",x"C9",x"06",x"00",x"C9",x"3A",x"00", -- 0x0DA0 + x"68",x"CB",x"57",x"28",x"02",x"CB",x"E1",x"CB", -- 0x0DA8 + x"5F",x"28",x"02",x"CB",x"D9",x"CB",x"6F",x"28", -- 0x0DB0 + x"02",x"CB",x"E9",x"3A",x"00",x"60",x"CB",x"4F", -- 0x0DB8 + x"28",x"02",x"CB",x"F1",x"79",x"B7",x"28",x"03", -- 0x0DC0 + x"06",x"01",x"C9",x"06",x"00",x"C9",x"FD",x"4E", -- 0x0DC8 + x"04",x"FD",x"7E",x"00",x"FE",x"0C",x"30",x"02", -- 0x0DD0 + x"CB",x"F1",x"FE",x"E0",x"38",x"02",x"CB",x"B1", -- 0x0DD8 + x"FD",x"7E",x"01",x"FE",x"80",x"30",x"02",x"CB", -- 0x0DE0 + x"E9",x"FE",x"E0",x"38",x"02",x"CB",x"A9",x"3A", -- 0x0DE8 + x"00",x"40",x"CB",x"77",x"28",x"12",x"CB",x"71", -- 0x0DF0 + x"28",x"08",x"FD",x"34",x"00",x"FD",x"34",x"00", -- 0x0DF8 + x"18",x"06",x"FD",x"35",x"00",x"FD",x"35",x"00", -- 0x0E00 + x"CB",x"69",x"28",x"05",x"FD",x"34",x"01",x"18", -- 0x0E08 + x"03",x"FD",x"35",x"01",x"FD",x"71",x"04",x"C9", -- 0x0E10 + x"C5",x"7D",x"E6",x"1F",x"47",x"AF",x"C6",x"08", -- 0x0E18 + x"10",x"FC",x"57",x"7D",x"E6",x"E0",x"CB",x"3F", -- 0x0E20 + x"CB",x"3F",x"CB",x"3F",x"CB",x"3F",x"CB",x"3F", -- 0x0E28 + x"4F",x"7C",x"E6",x"03",x"CB",x"27",x"CB",x"27", -- 0x0E30 + x"CB",x"27",x"B1",x"47",x"AF",x"D6",x"08",x"10", -- 0x0E38 + x"FC",x"D6",x"1C",x"5F",x"C1",x"C9",x"FD",x"66", -- 0x0E40 + x"03",x"FD",x"6E",x"02",x"E5",x"23",x"11",x"20", -- 0x0E48 + x"00",x"7E",x"FE",x"10",x"28",x"09",x"CD",x"DA", -- 0x0E50 + x"0E",x"C6",x"10",x"FE",x"08",x"38",x"11",x"23", -- 0x0E58 + x"7E",x"2B",x"FE",x"10",x"28",x"0C",x"23",x"CD", -- 0x0E60 + x"DA",x"0E",x"C6",x"10",x"FE",x"08",x"30",x"02", -- 0x0E68 + x"CB",x"99",x"11",x"40",x"00",x"19",x"7E",x"FE", -- 0x0E70 + x"10",x"28",x"07",x"CD",x"DA",x"0E",x"FE",x"E8", -- 0x0E78 + x"30",x"0F",x"23",x"7E",x"2B",x"FE",x"10",x"28", -- 0x0E80 + x"0A",x"23",x"CD",x"DA",x"0E",x"FE",x"E8",x"38", -- 0x0E88 + x"02",x"CB",x"A1",x"2B",x"7E",x"FE",x"10",x"28", -- 0x0E90 + x"09",x"CD",x"E2",x"0E",x"FE",x"FE",x"38",x"02", -- 0x0E98 + x"CB",x"B1",x"11",x"E0",x"FF",x"19",x"7E",x"FE", -- 0x0EA0 + x"10",x"28",x"09",x"CD",x"E2",x"0E",x"FE",x"FE", -- 0x0EA8 + x"38",x"02",x"CB",x"B1",x"E1",x"11",x"20",x"00", -- 0x0EB0 + x"19",x"23",x"23",x"7E",x"FE",x"10",x"28",x"09", -- 0x0EB8 + x"CD",x"E2",x"0E",x"FE",x"0C",x"30",x"02",x"CB", -- 0x0EC0 + x"A9",x"11",x"20",x"00",x"19",x"7E",x"FE",x"10", -- 0x0EC8 + x"C8",x"CD",x"E2",x"0E",x"FE",x"0C",x"D0",x"CB", -- 0x0ED0 + x"A9",x"C9",x"CD",x"18",x"0E",x"7B",x"FD",x"96", -- 0x0ED8 + x"00",x"C9",x"CD",x"18",x"0E",x"7A",x"FD",x"96", -- 0x0EE0 + x"01",x"ED",x"53",x"90",x"40",x"32",x"92",x"40", -- 0x0EE8 + x"C9",x"B1",x"E1",x"11",x"20",x"00",x"19",x"23", -- 0x0EF0 + x"23",x"7E",x"FE",x"10",x"28",x"09",x"CD",x"20", -- 0x0EF8 + x"0F",x"FE",x"0C",x"30",x"02",x"CB",x"A9",x"11", -- 0x0F00 + x"20",x"00",x"19",x"7E",x"FE",x"10",x"C8",x"CD", -- 0x0F08 + x"20",x"0F",x"FE",x"0C",x"D0",x"CB",x"A9",x"C9", -- 0x0F10 + x"CD",x"56",x"0E",x"7B",x"FD",x"96",x"00",x"C9", -- 0x0F18 + x"CD",x"56",x"0E",x"7A",x"FD",x"96",x"01",x"ED", -- 0x0F20 + x"53",x"90",x"40",x"32",x"92",x"40",x"C9",x"00", -- 0x0F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 + x"0F",x"FE",x"0C",x"30",x"02",x"CB",x"A9",x"11", -- 0x0F40 + x"20",x"00",x"19",x"7E",x"FE",x"10",x"C8",x"CD", -- 0x0F48 + x"20",x"0F",x"FE",x"0C",x"D0",x"CB",x"A9",x"C9", -- 0x0F50 + x"CD",x"56",x"0E",x"7B",x"FD",x"96",x"00",x"C9", -- 0x0F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF8 + x"CD",x"45",x"15",x"CD",x"98",x"13",x"AF",x"21", -- 0x1000 + x"A0",x"40",x"06",x"04",x"D7",x"32",x"0C",x"40", -- 0x1008 + x"3A",x"10",x"40",x"E6",x"1C",x"C8",x"FD",x"21", -- 0x1010 + x"56",x"40",x"06",x"07",x"FD",x"7E",x"05",x"4F", -- 0x1018 + x"E6",x"3E",x"FE",x"10",x"CA",x"00",x"26",x"FE", -- 0x1020 + x"14",x"CA",x"8E",x"26",x"FE",x"12",x"CA",x"0C", -- 0x1028 + x"27",x"79",x"E6",x"3F",x"FE",x"18",x"38",x"09", -- 0x1030 + x"FE",x"30",x"38",x"10",x"FE",x"38",x"DA",x"BF", -- 0x1038 + x"11",x"11",x"06",x"00",x"FD",x"19",x"10",x"D4", -- 0x1040 + x"CD",x"7F",x"15",x"C9",x"3A",x"0C",x"40",x"3C", -- 0x1048 + x"32",x"0C",x"40",x"FD",x"7E",x"04",x"E6",x"3F", -- 0x1050 + x"FE",x"18",x"CA",x"19",x"14",x"FE",x"24",x"CA", -- 0x1058 + x"19",x"14",x"FE",x"28",x"CA",x"19",x"14",x"FD", -- 0x1060 + x"7E",x"FF",x"E6",x"3F",x"FE",x"18",x"38",x"1E", -- 0x1068 + x"FE",x"30",x"30",x"1A",x"FD",x"7E",x"05",x"E6", -- 0x1070 + x"80",x"B7",x"FD",x"7E",x"FB",x"FD",x"77",x"01", -- 0x1078 + x"FD",x"7E",x"FA",x"20",x"04",x"C6",x"10",x"18", -- 0x1080 + x"02",x"D6",x"10",x"FD",x"77",x"00",x"FD",x"7E", -- 0x1088 + x"01",x"FE",x"A0",x"30",x"08",x"FD",x"7E",x"04", -- 0x1090 + x"CB",x"BF",x"FD",x"77",x"04",x"FD",x"7E",x"01", -- 0x1098 + x"FE",x"E8",x"38",x"0D",x"FD",x"7E",x"04",x"CB", -- 0x10A0 + x"FF",x"FD",x"77",x"04",x"3E",x"01",x"32",x"13", -- 0x10A8 + x"40",x"79",x"E6",x"80",x"B7",x"FD",x"7E",x"00", -- 0x10B0 + x"C2",x"6F",x"11",x"5F",x"FD",x"7E",x"04",x"E6", -- 0x10B8 + x"3F",x"FE",x"18",x"28",x"1E",x"FE",x"24",x"28", -- 0x10C0 + x"1A",x"FE",x"28",x"28",x"16",x"3A",x"16",x"40", -- 0x10C8 + x"B7",x"20",x"49",x"FD",x"7E",x"FB",x"FD",x"77", -- 0x10D0 + x"01",x"FD",x"7E",x"FA",x"C6",x"10",x"FD",x"77", -- 0x10D8 + x"00",x"18",x"21",x"3A",x"12",x"40",x"B7",x"C4", -- 0x10E0 + x"31",x"11",x"FD",x"7E",x"00",x"FE",x"18",x"DC", -- 0x10E8 + x"31",x"11",x"FD",x"66",x"03",x"FD",x"6E",x"02", -- 0x10F0 + x"11",x"40",x"00",x"19",x"7E",x"FE",x"10",x"C4", -- 0x10F8 + x"31",x"11",x"18",x"18",x"FD",x"7E",x"05",x"E6", -- 0x1100 + x"FC",x"4F",x"3A",x"00",x"40",x"E6",x"18",x"CB", -- 0x1108 + x"3F",x"CB",x"3F",x"CB",x"3F",x"B1",x"FD",x"77", -- 0x1110 + x"05",x"C3",x"36",x"13",x"FD",x"35",x"00",x"FD", -- 0x1118 + x"35",x"00",x"18",x"E0",x"3E",x"01",x"32",x"16", -- 0x1120 + x"40",x"18",x"1C",x"AF",x"32",x"16",x"40",x"18", -- 0x1128 + x"16",x"FD",x"7E",x"04",x"5F",x"E6",x"3C",x"FE", -- 0x1130 + x"18",x"28",x"E9",x"FE",x"28",x"28",x"E5",x"FE", -- 0x1138 + x"20",x"28",x"E8",x"FE",x"2C",x"28",x"E4",x"7B", -- 0x1140 + x"E6",x"80",x"57",x"FD",x"7E",x"05",x"E6",x"80", -- 0x1148 + x"4F",x"7B",x"E6",x"7F",x"CB",x"7A",x"20",x"08", -- 0x1150 + x"CD",x"1C",x"12",x"B1",x"FD",x"77",x"05",x"C9", -- 0x1158 + x"CD",x"16",x"12",x"F5",x"FD",x"7E",x"01",x"D6", -- 0x1160 + x"08",x"FD",x"77",x"01",x"F1",x"18",x"EC",x"5F", -- 0x1168 + x"FD",x"7E",x"04",x"E6",x"3F",x"FE",x"18",x"28", -- 0x1170 + x"1F",x"FE",x"24",x"28",x"1B",x"FE",x"28",x"28", -- 0x1178 + x"17",x"3A",x"16",x"40",x"B7",x"20",x"2C",x"FD", -- 0x1180 + x"7E",x"FB",x"FD",x"77",x"01",x"FD",x"7E",x"FA", -- 0x1188 + x"D6",x"10",x"FD",x"77",x"00",x"C3",x"04",x"11", -- 0x1190 + x"3A",x"12",x"40",x"B7",x"C4",x"31",x"11",x"FD", -- 0x1198 + x"7E",x"00",x"FE",x"D8",x"D4",x"31",x"11",x"FD", -- 0x11A0 + x"66",x"03",x"FD",x"6E",x"02",x"7E",x"FE",x"10", -- 0x11A8 + x"C4",x"31",x"11",x"FD",x"34",x"00",x"FD",x"34", -- 0x11B0 + x"00",x"FD",x"7E",x"00",x"C3",x"04",x"11",x"3A", -- 0x11B8 + x"0C",x"40",x"3C",x"32",x"0C",x"40",x"3A",x"00", -- 0x11C0 + x"40",x"E6",x"02",x"6F",x"FD",x"7E",x"04",x"E6", -- 0x11C8 + x"80",x"B7",x"20",x"21",x"FD",x"7E",x"05",x"4F", -- 0x11D0 + x"E6",x"80",x"5F",x"79",x"E6",x"3F",x"FE",x"33", -- 0x11D8 + x"CA",x"64",x"12",x"FE",x"37",x"D2",x"64",x"12", -- 0x11E0 + x"CB",x"4D",x"CA",x"41",x"10",x"3C",x"B3",x"FD", -- 0x11E8 + x"77",x"05",x"C3",x"41",x"10",x"FD",x"7E",x"05", -- 0x11F0 + x"4F",x"E6",x"C0",x"5F",x"79",x"E6",x"3F",x"FE", -- 0x11F8 + x"30",x"CA",x"64",x"12",x"FE",x"34",x"CA",x"64", -- 0x1200 + x"12",x"CB",x"4D",x"CA",x"41",x"10",x"3D",x"B3", -- 0x1208 + x"FD",x"77",x"05",x"C3",x"41",x"10",x"DD",x"21", -- 0x1210 + x"44",x"12",x"18",x"04",x"DD",x"21",x"36",x"12", -- 0x1218 + x"C5",x"06",x"07",x"E6",x"FC",x"DD",x"BE",x"00", -- 0x1220 + x"28",x"07",x"DD",x"23",x"DD",x"23",x"10",x"F5", -- 0x1228 + x"C9",x"DD",x"7E",x"01",x"C1",x"C9",x"18",x"30", -- 0x1230 + x"1C",x"34",x"20",x"34",x"24",x"30",x"28",x"30", -- 0x1238 + x"2C",x"30",x"00",x"00",x"18",x"73",x"1C",x"77", -- 0x1240 + x"20",x"77",x"24",x"73",x"28",x"77",x"2C",x"77", -- 0x1248 + x"00",x"00",x"FD",x"7E",x"04",x"CB",x"FF",x"FD", -- 0x1250 + x"77",x"04",x"C9",x"FD",x"7E",x"04",x"CB",x"BF", -- 0x1258 + x"FD",x"77",x"04",x"C9",x"FD",x"7E",x"05",x"E6", -- 0x1260 + x"3F",x"FE",x"18",x"CC",x"52",x"12",x"FE",x"24", -- 0x1268 + x"CC",x"52",x"12",x"FE",x"28",x"CC",x"52",x"12", -- 0x1270 + x"FE",x"37",x"CC",x"5B",x"12",x"FE",x"33",x"CC", -- 0x1278 + x"5B",x"12",x"FD",x"7E",x"0A",x"E6",x"3F",x"FE", -- 0x1280 + x"19",x"38",x"18",x"FE",x"24",x"28",x"14",x"FE", -- 0x1288 + x"28",x"28",x"10",x"FE",x"38",x"30",x"0C",x"FD", -- 0x1290 + x"7E",x"00",x"FD",x"77",x"06",x"FD",x"7E",x"01", -- 0x1298 + x"FD",x"77",x"07",x"FD",x"7E",x"04",x"5F",x"E6", -- 0x12A0 + x"80",x"57",x"FD",x"7E",x"05",x"E6",x"80",x"4F", -- 0x12A8 + x"FD",x"7E",x"04",x"E6",x"3F",x"FE",x"18",x"28", -- 0x12B0 + x"0A",x"FE",x"24",x"28",x"06",x"FE",x"28",x"28", -- 0x12B8 + x"02",x"18",x"0C",x"FD",x"7E",x"00",x"32",x"1E", -- 0x12C0 + x"40",x"FD",x"7E",x"01",x"32",x"1F",x"40",x"FD", -- 0x12C8 + x"7E",x"0A",x"E6",x"3F",x"FE",x"19",x"38",x"2D", -- 0x12D0 + x"FE",x"24",x"28",x"29",x"FE",x"28",x"28",x"25", -- 0x12D8 + x"FE",x"38",x"30",x"21",x"3A",x"1E",x"40",x"FD", -- 0x12E0 + x"77",x"06",x"3A",x"1F",x"40",x"FD",x"77",x"07", -- 0x12E8 + x"FD",x"7E",x"0A",x"E6",x"3F",x"CB",x"7A",x"28", -- 0x12F0 + x"05",x"CD",x"16",x"12",x"18",x"03",x"CD",x"1C", -- 0x12F8 + x"12",x"B1",x"FD",x"77",x"0B",x"3A",x"12",x"40", -- 0x1300 + x"B7",x"20",x"1A",x"FD",x"7E",x"04",x"E6",x"3F", -- 0x1308 + x"B1",x"EE",x"80",x"FD",x"77",x"05",x"3A",x"1F", -- 0x1310 + x"40",x"CB",x"7A",x"20",x"02",x"C6",x"08",x"FD", -- 0x1318 + x"77",x"01",x"C3",x"41",x"10",x"FD",x"7E",x"05", -- 0x1320 + x"E6",x"3F",x"CB",x"7A",x"20",x"05",x"CD",x"1C", -- 0x1328 + x"12",x"18",x"DD",x"CD",x"16",x"12",x"FD",x"7E", -- 0x1330 + x"05",x"E6",x"3F",x"FE",x"18",x"CA",x"4B",x"13", -- 0x1338 + x"FE",x"24",x"28",x"07",x"FE",x"28",x"28",x"03", -- 0x1340 + x"C3",x"41",x"10",x"D9",x"DD",x"21",x"50",x"40", -- 0x1348 + x"06",x"08",x"DD",x"7E",x"05",x"E6",x"3C",x"FE", -- 0x1350 + x"18",x"28",x"0A",x"FE",x"24",x"28",x"06",x"FE", -- 0x1358 + x"28",x"28",x"02",x"18",x"28",x"DD",x"E5",x"E1", -- 0x1360 + x"FD",x"E5",x"D1",x"B7",x"ED",x"52",x"28",x"1D", -- 0x1368 + x"FD",x"66",x"01",x"FD",x"6E",x"00",x"DD",x"56", -- 0x1370 + x"01",x"DD",x"5E",x"00",x"B7",x"ED",x"52",x"20", -- 0x1378 + x"0C",x"FD",x"7E",x"05",x"E6",x"80",x"4F",x"3E", -- 0x1380 + x"30",x"A9",x"FD",x"77",x"05",x"11",x"08",x"00", -- 0x1388 + x"DD",x"19",x"10",x"BE",x"D9",x"C3",x"41",x"10", -- 0x1390 + x"3A",x"10",x"40",x"E6",x"1C",x"C8",x"CB",x"4F", -- 0x1398 + x"C0",x"FD",x"21",x"50",x"40",x"FD",x"7E",x"00", -- 0x13A0 + x"FE",x"10",x"D8",x"DD",x"21",x"56",x"40",x"11", -- 0x13A8 + x"06",x"00",x"06",x"07",x"DD",x"7E",x"05",x"E6", -- 0x13B0 + x"3F",x"FE",x"10",x"38",x"27",x"FE",x"16",x"38", -- 0x13B8 + x"0D",x"DD",x"7E",x"04",x"E6",x"3F",x"FE",x"18", -- 0x13C0 + x"38",x"1A",x"FE",x"3C",x"30",x"16",x"DD",x"7E", -- 0x13C8 + x"00",x"B7",x"28",x"10",x"FD",x"7E",x"00",x"D6", -- 0x13D0 + x"04",x"4F",x"DD",x"7E",x"00",x"91",x"C6",x"08", -- 0x13D8 + x"FE",x"10",x"38",x"08",x"11",x"06",x"00",x"DD", -- 0x13E0 + x"19",x"10",x"C9",x"C9",x"DD",x"7E",x"01",x"4F", -- 0x13E8 + x"FD",x"7E",x"01",x"C6",x"04",x"91",x"C6",x"08", -- 0x13F0 + x"FE",x"10",x"30",x"E8",x"3A",x"10",x"40",x"32", -- 0x13F8 + x"14",x"40",x"3E",x"01",x"32",x"1C",x"40",x"3E", -- 0x1400 + x"02",x"32",x"10",x"40",x"3E",x"E0",x"32",x"03", -- 0x1408 + x"40",x"3E",x"3D",x"FD",x"77",x"05",x"C3",x"B5", -- 0x1410 + x"17",x"FD",x"E5",x"DD",x"E5",x"D9",x"FD",x"E5", -- 0x1418 + x"DD",x"E1",x"3E",x"01",x"32",x"09",x"40",x"11", -- 0x1420 + x"06",x"00",x"DD",x"19",x"DD",x"7E",x"05",x"E6", -- 0x1428 + x"3F",x"FE",x"18",x"38",x"15",x"FE",x"30",x"30", -- 0x1430 + x"11",x"FD",x"6E",x"02",x"FD",x"66",x"03",x"DD", -- 0x1438 + x"5E",x"02",x"DD",x"56",x"03",x"B7",x"ED",x"52", -- 0x1440 + x"28",x"12",x"DD",x"E5",x"D1",x"21",x"7F",x"40", -- 0x1448 + x"ED",x"52",x"30",x"D3",x"D9",x"DD",x"E1",x"FD", -- 0x1450 + x"E1",x"C3",x"8E",x"10",x"FD",x"7E",x"05",x"E6", -- 0x1458 + x"80",x"EE",x"80",x"C6",x"30",x"FD",x"77",x"05", -- 0x1460 + x"18",x"E0",x"3A",x"13",x"40",x"CB",x"77",x"C8", -- 0x1468 + x"CB",x"B7",x"32",x"13",x"40",x"AF",x"32",x"10", -- 0x1470 + x"40",x"3E",x"01",x"32",x"2F",x"40",x"32",x"01", -- 0x1478 + x"70",x"31",x"00",x"44",x"AF",x"21",x"00",x"60", -- 0x1480 + x"06",x"00",x"D7",x"21",x"00",x"68",x"D7",x"21", -- 0x1488 + x"00",x"00",x"22",x"06",x"70",x"21",x"16",x"1F", -- 0x1490 + x"22",x"05",x"41",x"22",x"05",x"42",x"3E",x"01", -- 0x1498 + x"32",x"08",x"41",x"CD",x"49",x"00",x"3A",x"13", -- 0x14A0 + x"40",x"CB",x"7F",x"3A",x"06",x"40",x"20",x"0C", -- 0x14A8 + x"3D",x"27",x"32",x"06",x"40",x"3E",x"08",x"32", -- 0x14B0 + x"14",x"40",x"18",x"0B",x"3D",x"3D",x"27",x"32", -- 0x14B8 + x"06",x"40",x"3E",x"88",x"32",x"14",x"40",x"3A", -- 0x14C0 + x"13",x"40",x"3E",x"C0",x"CD",x"4C",x"00",x"11", -- 0x14C8 + x"00",x"01",x"E7",x"3E",x"80",x"CD",x"4C",x"00", -- 0x14D0 + x"CD",x"49",x"00",x"21",x"50",x"40",x"06",x"30", -- 0x14D8 + x"AF",x"D7",x"21",x"00",x"41",x"CD",x"61",x"27", -- 0x14E0 + x"21",x"00",x"42",x"CD",x"61",x"27",x"AF",x"32", -- 0x14E8 + x"0A",x"41",x"32",x"0A",x"42",x"3A",x"10",x"40", -- 0x14F0 + x"CB",x"C7",x"32",x"10",x"40",x"3E",x"80",x"CD", -- 0x14F8 + x"4C",x"00",x"CD",x"4F",x"00",x"3A",x"14",x"40", -- 0x1500 + x"32",x"10",x"40",x"3E",x"01",x"32",x"04",x"70", -- 0x1508 + x"3A",x"10",x"40",x"CB",x"47",x"20",x"23",x"21", -- 0x1510 + x"40",x"50",x"11",x"00",x"00",x"7E",x"E6",x"FC", -- 0x1518 + x"FE",x"30",x"20",x"01",x"1C",x"23",x"7C",x"FE", -- 0x1520 + x"54",x"20",x"F2",x"7B",x"32",x"0A",x"40",x"B7", -- 0x1528 + x"20",x"08",x"3A",x"10",x"40",x"CB",x"C7",x"32", -- 0x1530 + x"10",x"40",x"CD",x"F3",x"00",x"CD",x"98",x"13", -- 0x1538 + x"CD",x"E0",x"00",x"18",x"CB",x"3A",x"0C",x"40", -- 0x1540 + x"B7",x"C0",x"3A",x"10",x"40",x"E6",x"1C",x"B7", -- 0x1548 + x"C8",x"21",x"A0",x"40",x"7E",x"4F",x"23",x"7E", -- 0x1550 + x"81",x"4F",x"23",x"7E",x"81",x"B7",x"C0",x"3E", -- 0x1558 + x"FF",x"32",x"00",x"78",x"CD",x"5E",x"00",x"CD", -- 0x1560 + x"57",x"18",x"3E",x"06",x"32",x"0C",x"40",x"FD", -- 0x1568 + x"21",x"7A",x"40",x"FD",x"7E",x"04",x"FE",x"18", -- 0x1570 + x"D8",x"FE",x"2F",x"D0",x"C3",x"26",x"17",x"FD", -- 0x1578 + x"21",x"56",x"40",x"21",x"00",x"00",x"06",x"07", -- 0x1580 + x"FD",x"7E",x"04",x"E6",x"3F",x"FE",x"1C",x"28", -- 0x1588 + x"25",x"FE",x"20",x"28",x"21",x"FE",x"2C",x"28", -- 0x1590 + x"1D",x"FE",x"18",x"28",x"1D",x"FE",x"28",x"28", -- 0x1598 + x"19",x"11",x"06",x"00",x"FD",x"19",x"10",x"E0", -- 0x15A0 + x"7C",x"B7",x"C8",x"7D",x"B7",x"C0",x"21",x"56", -- 0x15A8 + x"40",x"06",x"2C",x"AF",x"D7",x"C9",x"26",x"01", -- 0x15B0 + x"18",x"E7",x"2E",x"01",x"18",x"E3",x"36",x"2E", -- 0x15B8 + x"D9",x"DD",x"66",x"00",x"DD",x"6E",x"01",x"0E", -- 0x15C0 + x"0E",x"CD",x"5B",x"00",x"DD",x"7E",x"04",x"E6", -- 0x15C8 + x"3F",x"32",x"24",x"40",x"DD",x"7E",x"FE",x"E6", -- 0x15D0 + x"3F",x"32",x"25",x"40",x"DD",x"7E",x"0A",x"E6", -- 0x15D8 + x"3F",x"32",x"26",x"40",x"21",x"24",x"40",x"7E", -- 0x15E0 + x"FE",x"20",x"28",x"1C",x"FE",x"2C",x"28",x"0E", -- 0x15E8 + x"FE",x"24",x"28",x"14",x"23",x"36",x"FF",x"23", -- 0x15F0 + x"CD",x"10",x"16",x"77",x"18",x"2A",x"23",x"CD", -- 0x15F8 + x"10",x"16",x"77",x"23",x"36",x"FF",x"18",x"20", -- 0x1600 + x"23",x"36",x"FF",x"23",x"36",x"FF",x"18",x"18", -- 0x1608 + x"7E",x"06",x"06",x"FD",x"21",x"22",x"16",x"FD", -- 0x1610 + x"BE",x"00",x"C8",x"FD",x"23",x"10",x"F8",x"3E", -- 0x1618 + x"FF",x"C9",x"18",x"1C",x"20",x"24",x"28",x"2C", -- 0x1620 + x"DD",x"E5",x"FD",x"E5",x"DD",x"21",x"61",x"17", -- 0x1628 + x"FD",x"21",x"8B",x"17",x"06",x"00",x"3A",x"24", -- 0x1630 + x"40",x"DD",x"BE",x"00",x"C2",x"3F",x"17",x"3A", -- 0x1638 + x"25",x"40",x"DD",x"BE",x"01",x"C2",x"3F",x"17", -- 0x1640 + x"3A",x"26",x"40",x"DD",x"BE",x"02",x"C2",x"3F", -- 0x1648 + x"17",x"FD",x"7E",x"00",x"32",x"21",x"40",x"FD", -- 0x1650 + x"7E",x"01",x"32",x"22",x"40",x"FD",x"7E",x"02", -- 0x1658 + x"32",x"23",x"40",x"FD",x"E1",x"DD",x"E1",x"DD", -- 0x1660 + x"7E",x"04",x"E6",x"80",x"5F",x"3A",x"21",x"40", -- 0x1668 + x"B7",x"CA",x"FE",x"16",x"FE",x"FF",x"28",x"34", -- 0x1670 + x"B3",x"DD",x"77",x"04",x"DD",x"7E",x"05",x"E6", -- 0x1678 + x"80",x"5F",x"3A",x"21",x"40",x"B3",x"DD",x"77", -- 0x1680 + x"05",x"CD",x"8E",x"16",x"18",x"1E",x"DD",x"7E", -- 0x1688 + x"04",x"E6",x"3F",x"FE",x"18",x"28",x"09",x"FE", -- 0x1690 + x"24",x"28",x"05",x"FE",x"28",x"28",x"01",x"C9", -- 0x1698 + x"DD",x"E5",x"DD",x"E5",x"FD",x"E1",x"CD",x"31", -- 0x16A0 + x"11",x"DD",x"E1",x"C9",x"3A",x"22",x"40",x"B7", -- 0x16A8 + x"28",x"55",x"57",x"FE",x"FF",x"28",x"16",x"DD", -- 0x16B0 + x"7E",x"FE",x"E6",x"80",x"5F",x"7A",x"B3",x"DD", -- 0x16B8 + x"77",x"FE",x"DD",x"7E",x"FF",x"E6",x"80",x"5F", -- 0x16C0 + x"7A",x"B3",x"DD",x"77",x"FF",x"3A",x"23",x"40", -- 0x16C8 + x"B7",x"28",x"42",x"FE",x"FF",x"28",x"25",x"57", -- 0x16D0 + x"DD",x"7E",x"0A",x"E6",x"80",x"5F",x"7A",x"B3", -- 0x16D8 + x"DD",x"77",x"0A",x"DD",x"7E",x"0B",x"E6",x"80", -- 0x16E0 + x"5F",x"7A",x"B3",x"DD",x"77",x"0B",x"DD",x"E5", -- 0x16E8 + x"D5",x"11",x"06",x"00",x"DD",x"19",x"CD",x"8E", -- 0x16F0 + x"16",x"D1",x"DD",x"E1",x"D9",x"C9",x"DD",x"E5", -- 0x16F8 + x"FD",x"E1",x"CD",x"26",x"17",x"18",x"A5",x"DD", -- 0x1700 + x"E5",x"FD",x"E1",x"11",x"FA",x"FF",x"FD",x"19", -- 0x1708 + x"CD",x"26",x"17",x"18",x"B8",x"DD",x"E5",x"FD", -- 0x1710 + x"E1",x"11",x"06",x"00",x"FD",x"19",x"CD",x"26", -- 0x1718 + x"17",x"C3",x"FC",x"16",x"FD",x"E1",x"FD",x"36", -- 0x1720 + x"00",x"00",x"FD",x"36",x"01",x"00",x"FD",x"36", -- 0x1728 + x"02",x"00",x"FD",x"36",x"03",x"00",x"FD",x"36", -- 0x1730 + x"04",x"00",x"FD",x"36",x"05",x"00",x"C9",x"04", -- 0x1738 + x"78",x"FE",x"10",x"20",x"0D",x"AF",x"21",x"56", -- 0x1740 + x"40",x"06",x"2C",x"D7",x"FD",x"E1",x"DD",x"E1", -- 0x1748 + x"D9",x"C9",x"DD",x"23",x"DD",x"23",x"DD",x"23", -- 0x1750 + x"FD",x"23",x"FD",x"23",x"FD",x"23",x"C3",x"36", -- 0x1758 + x"16",x"18",x"FF",x"1C",x"18",x"FF",x"20",x"18", -- 0x1760 + x"FF",x"2C",x"1C",x"FF",x"1C",x"1C",x"FF",x"20", -- 0x1768 + x"1C",x"FF",x"2C",x"20",x"FF",x"FF",x"24",x"FF", -- 0x1770 + x"FF",x"28",x"FF",x"1C",x"28",x"FF",x"20",x"28", -- 0x1778 + x"FF",x"2C",x"2C",x"18",x"FF",x"2C",x"1C",x"FF", -- 0x1780 + x"2C",x"28",x"FF",x"28",x"FF",x"FF",x"28",x"FF", -- 0x1788 + x"FF",x"24",x"FF",x"00",x"20",x"FF",x"18",x"20", -- 0x1790 + x"FF",x"24",x"20",x"FF",x"24",x"2C",x"FF",x"FF", -- 0x1798 + x"00",x"FF",x"FF",x"00",x"FF",x"18",x"00",x"FF", -- 0x17A0 + x"24",x"00",x"FF",x"00",x"00",x"24",x"FF",x"00", -- 0x17A8 + x"20",x"FF",x"00",x"00",x"FF",x"3A",x"10",x"40", -- 0x17B0 + x"E6",x"E3",x"32",x"10",x"40",x"31",x"00",x"44", -- 0x17B8 + x"3A",x"14",x"40",x"4F",x"3E",x"01",x"32",x"01", -- 0x17C0 + x"70",x"CB",x"51",x"20",x"03",x"32",x"03",x"68", -- 0x17C8 + x"3A",x"03",x"40",x"FE",x"E8",x"20",x"F9",x"3E", -- 0x17D0 + x"3D",x"32",x"55",x"40",x"3A",x"03",x"40",x"FE", -- 0x17D8 + x"F0",x"20",x"F9",x"3E",x"0E",x"32",x"55",x"40", -- 0x17E0 + x"AF",x"32",x"03",x"68",x"3A",x"0A",x"40",x"FE", -- 0x17E8 + x"28",x"30",x"08",x"3A",x"10",x"40",x"CB",x"CF", -- 0x17F0 + x"32",x"10",x"40",x"3E",x"80",x"32",x"02",x"40", -- 0x17F8 + x"3A",x"02",x"40",x"B7",x"20",x"FA",x"CD",x"82", -- 0x1800 + x"18",x"AF",x"32",x"04",x"70",x"3E",x"C0",x"CD", -- 0x1808 + x"4C",x"00",x"21",x"50",x"40",x"AF",x"06",x"2F", -- 0x1810 + x"D7",x"CD",x"E6",x"00",x"CD",x"49",x"00",x"CD", -- 0x1818 + x"EC",x"00",x"3E",x"C0",x"CD",x"4C",x"00",x"CD", -- 0x1820 + x"E9",x"00",x"3E",x"C0",x"CD",x"4C",x"00",x"3A", -- 0x1828 + x"0A",x"40",x"FE",x"28",x"30",x"08",x"3A",x"14", -- 0x1830 + x"40",x"CB",x"C7",x"32",x"14",x"40",x"CD",x"61", -- 0x1838 + x"00",x"CD",x"57",x"18",x"3E",x"C0",x"CD",x"4C", -- 0x1840 + x"00",x"3E",x"01",x"32",x"04",x"70",x"3A",x"14", -- 0x1848 + x"40",x"32",x"10",x"40",x"C3",x"10",x"15",x"3A", -- 0x1850 + x"14",x"40",x"CB",x"5F",x"28",x"06",x"DD",x"21", -- 0x1858 + x"00",x"41",x"18",x"04",x"DD",x"21",x"00",x"42", -- 0x1860 + x"21",x"46",x"43",x"DD",x"7E",x"0C",x"3C",x"E6", -- 0x1868 + x"07",x"DD",x"77",x"0C",x"7D",x"FE",x"60",x"D0", -- 0x1870 + x"DD",x"7E",x"0C",x"77",x"23",x"23",x"23",x"23", -- 0x1878 + x"18",x"F2",x"21",x"C0",x"53",x"7C",x"FE",x"4F", -- 0x1880 + x"C8",x"7E",x"E6",x"3C",x"FE",x"2C",x"E5",x"CC", -- 0x1888 + x"96",x"18",x"E1",x"2B",x"18",x"EF",x"56",x"E5", -- 0x1890 + x"DD",x"E5",x"CD",x"F6",x"00",x"CD",x"E0",x"00", -- 0x1898 + x"DD",x"E1",x"E1",x"36",x"FA",x"3A",x"14",x"40", -- 0x18A0 + x"CB",x"57",x"20",x"05",x"3E",x"01",x"32",x"03", -- 0x18A8 + x"68",x"3E",x"FC",x"CD",x"4C",x"00",x"36",x"FB", -- 0x18B0 + x"AF",x"32",x"03",x"68",x"3E",x"FC",x"CD",x"4C", -- 0x18B8 + x"00",x"36",x"10",x"C9",x"10",x"C9",x"FE",x"E8", -- 0x18C0 + x"38",x"13",x"3A",x"0C",x"40",x"B7",x"20",x"0B", -- 0x18C8 + x"CD",x"F6",x"16",x"3E",x"FF",x"32",x"00",x"78", -- 0x18D0 + x"C3",x"3E",x"10",x"CB",x"D1",x"3A",x"00",x"40", -- 0x18D8 + x"CB",x"77",x"20",x"0E",x"CB",x"61",x"FD",x"7E", -- 0x18E0 + x"00",x"20",x"03",x"93",x"18",x"01",x"83",x"FD", -- 0x18E8 + x"77",x"00",x"CB",x"51",x"FD",x"7E",x"01",x"28", -- 0x18F0 + x"03",x"93",x"18",x"01",x"83",x"FD",x"77",x"01", -- 0x18F8 + x"CB",x"51",x"FD",x"7E",x"05",x"28",x"0B",x"CB", -- 0x1900 + x"B7",x"FD",x"77",x"05",x"FD",x"71",x"04",x"C3", -- 0x1908 + x"3E",x"10",x"CB",x"F7",x"18",x"F3",x"3A",x"A2", -- 0x1910 + x"40",x"3C",x"32",x"A2",x"40",x"FD",x"7E",x"05", -- 0x1918 + x"E6",x"3F",x"FE",x"15",x"28",x"64",x"FD",x"7E", -- 0x1920 + x"04",x"E6",x"03",x"B7",x"20",x"02",x"3E",x"03", -- 0x1928 + x"4F",x"FD",x"7E",x"01",x"5F",x"FD",x"BE",x"0F", -- 0x1930 + x"38",x"38",x"3A",x"05",x"40",x"E6",x"0F",x"FE", -- 0x1938 + x"03",x"20",x"2F",x"FD",x"66",x"03",x"FD",x"6E", -- 0x1940 + x"02",x"11",x"20",x"00",x"19",x"7D",x"E6",x"1F", -- 0x1948 + x"FE",x"1C",x"30",x"0C",x"36",x"32",x"3E",x"FC", -- 0x1950 + x"32",x"00",x"40",x"3E",x"15",x"FD",x"77",x"05", -- 0x1958 + x"3A",x"10",x"40",x"CB",x"57",x"CA",x"3E",x"10", -- 0x1960 + x"FD",x"7E",x"01",x"2F",x"32",x"00",x"78",x"C3", -- 0x1968 + x"3E",x"10",x"F5",x"3A",x"10",x"40",x"CB",x"57", -- 0x1970 + x"F1",x"28",x"04",x"2F",x"32",x"00",x"78",x"7B", -- 0x1978 + x"81",x"FE",x"F0",x"30",x"12",x"FD",x"77",x"01", -- 0x1980 + x"18",x"E5",x"3A",x"00",x"40",x"B7",x"20",x"DF", -- 0x1988 + x"3E",x"14",x"FD",x"77",x"05",x"18",x"D8",x"CD", -- 0x1990 + x"F6",x"16",x"3E",x"FF",x"32",x"00",x"78",x"18", -- 0x1998 + x"CE",x"3A",x"A1",x"40",x"3C",x"32",x"A1",x"40", -- 0x19A0 + x"3A",x"00",x"40",x"5F",x"FD",x"7E",x"04",x"4F", -- 0x19A8 + x"E6",x"03",x"B7",x"20",x"02",x"3E",x"03",x"57", -- 0x19B0 + x"FD",x"7E",x"00",x"CB",x"61",x"20",x"03",x"82", -- 0x19B8 + x"18",x"01",x"92",x"FD",x"77",x"00",x"FE",x"08", -- 0x19C0 + x"38",x"CD",x"FE",x"F8",x"30",x"C9",x"CB",x"53", -- 0x19C8 + x"20",x"04",x"3E",x"12",x"18",x"02",x"3E",x"13", -- 0x19D0 + x"CB",x"61",x"28",x"02",x"CB",x"FF",x"FD",x"77", -- 0x19D8 + x"05",x"FD",x"66",x"03",x"FD",x"6E",x"02",x"23", -- 0x19E0 + x"11",x"20",x"00",x"19",x"7E",x"FE",x"10",x"28", -- 0x19E8 + x"02",x"36",x"FA",x"C3",x"3E",x"10",x"00",x"00", -- 0x19F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x19F8 + x"FD",x"E5",x"DD",x"E5",x"CD",x"0C",x"1A",x"DD", -- 0x1A00 + x"E1",x"FD",x"E1",x"C9",x"FD",x"21",x"00",x"40", -- 0x1A08 + x"FD",x"7E",x"0C",x"B7",x"C8",x"FD",x"7E",x"00", -- 0x1A10 + x"4F",x"3A",x"10",x"40",x"FE",x"04",x"28",x"6C", -- 0x1A18 + x"FD",x"7E",x"10",x"CB",x"5F",x"28",x"06",x"DD", -- 0x1A20 + x"21",x"00",x"41",x"18",x"04",x"DD",x"21",x"00", -- 0x1A28 + x"42",x"DD",x"7E",x"04",x"FE",x"04",x"D8",x"DD", -- 0x1A30 + x"7E",x"0A",x"FE",x"10",x"38",x"05",x"3E",x"0E", -- 0x1A38 + x"DD",x"77",x"0A",x"47",x"DD",x"7E",x"01",x"5F", -- 0x1A40 + x"E6",x"0F",x"57",x"78",x"FE",x"0F",x"20",x"0C", -- 0x1A48 + x"CB",x"79",x"20",x"08",x"FD",x"34",x"01",x"CB", -- 0x1A50 + x"B9",x"FD",x"71",x"00",x"7A",x"B7",x"CA",x"52", -- 0x1A58 + x"1B",x"FE",x"02",x"28",x"17",x"FE",x"04",x"28", -- 0x1A60 + x"53",x"FE",x"08",x"28",x"0F",x"FE",x"A0",x"CA", -- 0x1A68 + x"7F",x"1B",x"FE",x"C0",x"CA",x"03",x"1B",x"FE", -- 0x1A70 + x"E0",x"28",x"41",x"C9",x"FD",x"34",x"01",x"CB", -- 0x1A78 + x"61",x"C8",x"3A",x"10",x"40",x"CB",x"57",x"20", -- 0x1A80 + x"0F",x"DD",x"7E",x"0A",x"21",x"00",x"21",x"CD", -- 0x1A88 + x"B6",x"1B",x"3A",x"A0",x"40",x"BA",x"C8",x"D0", -- 0x1A90 + x"3E",x"F0",x"C5",x"D5",x"67",x"2E",x"F0",x"0E", -- 0x1A98 + x"10",x"CD",x"5B",x"00",x"D1",x"C1",x"B7",x"C8", -- 0x1AA0 + x"7B",x"FE",x"01",x"28",x"05",x"CB",x"51",x"20", -- 0x1AA8 + x"01",x"1D",x"7B",x"C6",x"04",x"FD",x"77",x"04", -- 0x1AB0 + x"DD",x"34",x"04",x"C9",x"FD",x"34",x"01",x"CB", -- 0x1AB8 + x"41",x"C8",x"3A",x"05",x"40",x"FE",x"20",x"38", -- 0x1AC0 + x"04",x"FE",x"D0",x"38",x"02",x"C6",x"80",x"F5", -- 0x1AC8 + x"DD",x"7E",x"0A",x"21",x"1F",x"21",x"CD",x"B6", -- 0x1AD0 + x"1B",x"3A",x"A2",x"40",x"BA",x"28",x"22",x"30", -- 0x1AD8 + x"20",x"F1",x"C5",x"D5",x"67",x"2E",x"08",x"0E", -- 0x1AE0 + x"14",x"CD",x"5B",x"00",x"D1",x"E1",x"B7",x"C8", -- 0x1AE8 + x"7B",x"FE",x"01",x"28",x"05",x"CB",x"49",x"20", -- 0x1AF0 + x"01",x"1D",x"FD",x"73",x"04",x"DD",x"34",x"04", -- 0x1AF8 + x"C9",x"F1",x"C9",x"FD",x"34",x"01",x"CB",x"41", -- 0x1B00 + x"C8",x"FD",x"34",x"01",x"DD",x"7E",x"0A",x"21", -- 0x1B08 + x"3D",x"21",x"CD",x"B6",x"1B",x"3A",x"A1",x"40", -- 0x1B10 + x"BA",x"D0",x"3A",x"05",x"40",x"FE",x"20",x"38", -- 0x1B18 + x"04",x"FE",x"E0",x"38",x"02",x"C6",x"80",x"6F", -- 0x1B20 + x"C5",x"D5",x"CB",x"49",x"28",x"04",x"26",x"10", -- 0x1B28 + x"18",x"02",x"26",x"F0",x"0E",x"12",x"CD",x"5B", -- 0x1B30 + x"00",x"B7",x"D1",x"C1",x"C8",x"CB",x"49",x"20", -- 0x1B38 + x"07",x"FD",x"73",x"04",x"FD",x"34",x"04",x"C9", -- 0x1B40 + x"7B",x"C6",x"10",x"FD",x"73",x"04",x"FD",x"34", -- 0x1B48 + x"04",x"C9",x"FD",x"34",x"01",x"3A",x"A1",x"40", -- 0x1B50 + x"B7",x"C0",x"3A",x"51",x"40",x"FE",x"C0",x"D0", -- 0x1B58 + x"6F",x"3A",x"50",x"40",x"FE",x"80",x"30",x"06", -- 0x1B60 + x"26",x"10",x"0E",x"02",x"18",x"04",x"26",x"F0", -- 0x1B68 + x"0E",x"12",x"C5",x"0E",x"12",x"CD",x"5B",x"00", -- 0x1B70 + x"C1",x"B7",x"C8",x"FD",x"71",x"04",x"C9",x"FD", -- 0x1B78 + x"34",x"01",x"3A",x"0C",x"40",x"FE",x"02",x"D8", -- 0x1B80 + x"DD",x"7E",x"0A",x"FE",x"06",x"D8",x"3A",x"01", -- 0x1B88 + x"40",x"3C",x"32",x"01",x"40",x"3A",x"05",x"40", -- 0x1B90 + x"E6",x"7F",x"67",x"2E",x"08",x"0E",x"24",x"CD", -- 0x1B98 + x"5B",x"00",x"FD",x"36",x"04",x"24",x"DD",x"7E", -- 0x1BA0 + x"04",x"67",x"2E",x"08",x"0E",x"24",x"CD",x"5B", -- 0x1BA8 + x"00",x"FD",x"36",x"04",x"24",x"C9",x"47",x"7E", -- 0x1BB0 + x"B8",x"30",x"02",x"18",x"05",x"23",x"5E",x"23", -- 0x1BB8 + x"56",x"C9",x"23",x"23",x"23",x"18",x"F0",x"56", -- 0x1BC0 + x"C9",x"23",x"23",x"23",x"18",x"F0",x"C9",x"23", -- 0x1BC8 + x"23",x"23",x"18",x"F0",x"23",x"18",x"F0",x"18", -- 0x1BD0 + x"04",x"DD",x"21",x"00",x"41",x"DD",x"7E",x"0D", -- 0x1BD8 + x"B7",x"C0",x"3A",x"00",x"70",x"CB",x"5F",x"28", -- 0x1BE0 + x"05",x"3A",x"4E",x"1C",x"18",x"03",x"3A",x"4F", -- 0x1BE8 + x"1C",x"DD",x"BE",x"00",x"C0",x"DD",x"36",x"0D", -- 0x1BF0 + x"01",x"DD",x"36",x"0E",x"01",x"DD",x"34",x"09", -- 0x1BF8 + x"11",x"38",x"1C",x"E7",x"11",x"2A",x"1C",x"E7", -- 0x1C00 + x"3A",x"10",x"40",x"F5",x"AF",x"32",x"10",x"40", -- 0x1C08 + x"21",x"00",x"1D",x"22",x"C0",x"40",x"AF",x"32", -- 0x1C10 + x"00",x"40",x"3A",x"00",x"40",x"FE",x"80",x"20", -- 0x1C18 + x"F9",x"11",x"38",x"1C",x"E7",x"F1",x"32",x"10", -- 0x1C20 + x"40",x"C9",x"01",x"1F",x"04",x"42",x"4F",x"4E", -- 0x1C28 + x"55",x"53",x"40",x"42",x"41",x"53",x"45",x"FF", -- 0x1C30 + x"05",x"1F",x"00",x"40",x"40",x"40",x"40",x"40", -- 0x1C38 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x1C40 + x"40",x"40",x"40",x"40",x"40",x"FF",x"50",x"75", -- 0x1C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CF8 + x"00",x"20",x"20",x"30",x"30",x"40",x"40",x"50", -- 0x1D00 + x"50",x"80",x"80",x"70",x"70",x"50",x"50",x"FF", -- 0x1D08 + x"44",x"77",x"99",x"AA",x"D0",x"80",x"60",x"40", -- 0x1D10 + x"50",x"80",x"80",x"80",x"FF",x"00",x"00",x"00", -- 0x1D18 + x"AA",x"BB",x"CC",x"DD",x"AA",x"90",x"80",x"FF", -- 0x1D20 + x"40",x"FF",x"C0",x"B0",x"A0",x"90",x"80",x"FF", -- 0x1D28 + x"12",x"34",x"56",x"78",x"9A",x"BC",x"DE",x"F1", -- 0x1D30 + x"23",x"45",x"67",x"FF",x"AB",x"CD",x"FF",x"00", -- 0x1D38 + x"F0",x"DC",x"BA",x"98",x"76",x"54",x"32",x"12", -- 0x1D40 + x"34",x"FF",x"78",x"9A",x"FF",x"00",x"00",x"00", -- 0x1D48 + x"C3",x"10",x"43",x"3E",x"1A",x"01",x"22",x"45", -- 0x1D50 + x"C9",x"01",x"FF",x"10",x"22",x"83",x"FF",x"00", -- 0x1D58 + x"10",x"10",x"20",x"20",x"30",x"30",x"40",x"40", -- 0x1D60 + x"30",x"30",x"20",x"20",x"10",x"10",x"FF",x"00", -- 0x1D68 + x"50",x"60",x"70",x"80",x"90",x"A0",x"B0",x"A0", -- 0x1D70 + x"90",x"80",x"70",x"FF",x"50",x"FF",x"00",x"00", -- 0x1D78 + x"F0",x"E0",x"C0",x"D0",x"E0",x"F0",x"D0",x"C0", -- 0x1D80 + x"A0",x"D0",x"FF",x"E0",x"F0",x"FF",x"00",x"00", -- 0x1D88 + x"18",x"68",x"74",x"98",x"A0",x"98",x"74",x"68", -- 0x1D90 + x"36",x"38",x"FF",x"3C",x"3E",x"FF",x"00",x"00", -- 0x1D98 + x"10",x"80",x"20",x"A0",x"30",x"E0",x"40",x"80", -- 0x1DA0 + x"80",x"FF",x"70",x"68",x"60",x"20",x"20",x"FF", -- 0x1DA8 + x"22",x"33",x"45",x"67",x"65",x"55",x"F0",x"E0", -- 0x1DB0 + x"20",x"30",x"20",x"30",x"20",x"FF",x"00",x"00", -- 0x1DB8 + x"82",x"84",x"86",x"88",x"8A",x"8C",x"8E",x"90", -- 0x1DC0 + x"92",x"94",x"96",x"98",x"9A",x"9C",x"9E",x"FF", -- 0x1DC8 + x"F0",x"E8",x"E0",x"D8",x"D0",x"C8",x"C0",x"B8", -- 0x1DD0 + x"B0",x"A8",x"A0",x"E0",x"F0",x"F0",x"F0",x"FF", -- 0x1DD8 + x"30",x"50",x"70",x"80",x"70",x"60",x"50",x"40", -- 0x1DE0 + x"30",x"20",x"10",x"FF",x"00",x"00",x"00",x"00", -- 0x1DE8 + x"80",x"80",x"F0",x"D9",x"68",x"65",x"D6",x"D7", -- 0x1DF0 + x"D9",x"22",x"33",x"44",x"55",x"66",x"77",x"FF", -- 0x1DF8 + x"AF",x"32",x"10",x"40",x"3E",x"C0",x"CD",x"4C", -- 0x1E00 + x"00",x"21",x"00",x"70",x"AF",x"06",x"20",x"D7", -- 0x1E08 + x"3E",x"01",x"32",x"01",x"70",x"21",x"00",x"43", -- 0x1E10 + x"06",x"40",x"D7",x"3A",x"00",x"68",x"E6",x"C0", -- 0x1E18 + x"FE",x"C0",x"20",x"05",x"3E",x"02",x"32",x"06", -- 0x1E20 + x"40",x"11",x"7D",x"1F",x"E7",x"3E",x"C0",x"CD", -- 0x1E28 + x"4C",x"00",x"11",x"92",x"1F",x"E7",x"3E",x"C0", -- 0x1E30 + x"CD",x"4C",x"00",x"11",x"9E",x"1F",x"E7",x"3E", -- 0x1E38 + x"80",x"CD",x"4C",x"00",x"11",x"C2",x"1F",x"E7", -- 0x1E40 + x"3E",x"80",x"CD",x"4C",x"00",x"11",x"C8",x"1F", -- 0x1E48 + x"E7",x"11",x"B1",x"1F",x"E7",x"3E",x"80",x"CD", -- 0x1E50 + x"4C",x"00",x"11",x"E5",x"1F",x"E7",x"3E",x"2B", -- 0x1E58 + x"32",x"98",x"53",x"3E",x"80",x"CD",x"4C",x"00", -- 0x1E60 + x"11",x"F9",x"1F",x"E7",x"11",x"19",x"20",x"E7", -- 0x1E68 + x"11",x"35",x"20",x"E7",x"3E",x"C0",x"CD",x"4C", -- 0x1E70 + x"00",x"CD",x"49",x"00",x"3E",x"C0",x"CD",x"4C", -- 0x1E78 + x"00",x"11",x"43",x"20",x"E7",x"3E",x"C0",x"CD", -- 0x1E80 + x"4C",x"00",x"DD",x"21",x"5A",x"20",x"FD",x"21", -- 0x1E88 + x"50",x"40",x"06",x"04",x"DD",x"7E",x"00",x"FD", -- 0x1E90 + x"77",x"00",x"DD",x"7E",x"01",x"FD",x"77",x"01", -- 0x1E98 + x"DD",x"7E",x"02",x"FD",x"77",x"05",x"11",x"06", -- 0x1EA0 + x"00",x"FD",x"19",x"11",x"03",x"00",x"DD",x"19", -- 0x1EA8 + x"10",x"E2",x"FD",x"E5",x"11",x"66",x"20",x"E7", -- 0x1EB0 + x"FD",x"E1",x"FD",x"36",x"00",x"40",x"FD",x"36", -- 0x1EB8 + x"01",x"E0",x"FD",x"36",x"05",x"10",x"FD",x"E5", -- 0x1EC0 + x"11",x"72",x"20",x"E7",x"FD",x"E1",x"FD",x"36", -- 0x1EC8 + x"06",x"40",x"FD",x"36",x"07",x"C0",x"FD",x"36", -- 0x1ED0 + x"0B",x"12",x"FD",x"E5",x"11",x"79",x"20",x"E7", -- 0x1ED8 + x"FD",x"E1",x"FD",x"36",x"0C",x"40",x"FD",x"36", -- 0x1EE0 + x"0D",x"A0",x"FD",x"36",x"11",x"14",x"11",x"80", -- 0x1EE8 + x"20",x"E7",x"3E",x"32",x"32",x"E7",x"52",x"11", -- 0x1EF0 + x"87",x"20",x"E7",x"3E",x"F8",x"32",x"EB",x"52", -- 0x1EF8 + x"11",x"8F",x"20",x"E7",x"3E",x"10",x"CD",x"4C", -- 0x1F00 + x"00",x"CD",x"49",x"00",x"3E",x"C0",x"CD",x"4C", -- 0x1F08 + x"00",x"11",x"9A",x"20",x"E7",x"3E",x"C0",x"CD", -- 0x1F10 + x"4C",x"00",x"11",x"B0",x"20",x"E7",x"3E",x"C0", -- 0x1F18 + x"CD",x"4C",x"00",x"3A",x"0F",x"00",x"B7",x"CA", -- 0x1F20 + x"1C",x"25",x"3A",x"00",x"68",x"07",x"07",x"B7", -- 0x1F28 + x"28",x"06",x"11",x"D0",x"20",x"E7",x"18",x"04", -- 0x1F30 + x"11",x"C0",x"20",x"E7",x"3E",x"80",x"CD",x"4C", -- 0x1F38 + x"00",x"CD",x"49",x"00",x"3E",x"C0",x"CD",x"4C", -- 0x1F40 + x"00",x"CD",x"4F",x"00",x"3A",x"10",x"40",x"CB", -- 0x1F48 + x"C7",x"32",x"10",x"40",x"3A",x"10",x"40",x"CB", -- 0x1F50 + x"47",x"20",x"F9",x"3E",x"01",x"32",x"04",x"70", -- 0x1F58 + x"3E",x"04",x"32",x"10",x"40",x"32",x"14",x"40", -- 0x1F60 + x"3E",x"01",x"32",x"09",x"41",x"32",x"09",x"42", -- 0x1F68 + x"3E",x"08",x"32",x"0A",x"42",x"32",x"0A",x"41", -- 0x1F70 + x"CD",x"E0",x"00",x"18",x"FE",x"02",x"04",x"05", -- 0x1F78 + x"46",x"4F",x"4F",x"44",x"40",x"41",x"4E",x"44", -- 0x1F80 + x"40",x"46",x"55",x"4E",x"40",x"43",x"4F",x"52", -- 0x1F88 + x"50",x"FF",x"03",x"08",x"0A",x"50",x"52",x"45", -- 0x1F90 + x"53",x"45",x"4E",x"54",x"53",x"FF",x"04",x"0C", -- 0x1F98 + x"06",x"57",x"41",x"52",x"40",x"4F",x"46",x"40", -- 0x1FA0 + x"54",x"48",x"45",x"40",x"42",x"55",x"47",x"53", -- 0x1FA8 + x"FF",x"06",x"13",x"08",x"4D",x"55",x"53",x"48", -- 0x1FB0 + x"52",x"4F",x"4F",x"4D",x"40",x"4D",x"41",x"5A", -- 0x1FB8 + x"45",x"FF",x"05",x"0E",x"0C",x"4F",x"52",x"FF", -- 0x1FC0 + x"06",x"11",x"02",x"4D",x"4F",x"4E",x"53",x"54", -- 0x1FC8 + x"45",x"52",x"4F",x"55",x"53",x"40",x"4D",x"41", -- 0x1FD0 + x"4E",x"4F",x"55",x"56",x"45",x"52",x"53",x"40", -- 0x1FD8 + x"49",x"4E",x"40",x"41",x"FF",x"00",x"18",x"06", -- 0x1FE0 + x"41",x"52",x"4D",x"45",x"4E",x"49",x"41",x"40", -- 0x1FE8 + x"4C",x"54",x"44",x"40",x"31",x"39",x"38",x"31", -- 0x1FF0 + x"FF",x"07",x"1D",x"00",x"50",x"52",x"4F",x"47", -- 0x1FF8 + x"FF",x"41",x"4D",x"4D",x"49",x"4E",x"47",x"40", -- 0x2000 + x"54",x"4F",x"54",x"41",x"4C",x"4C",x"59",x"40", -- 0x2008 + x"4F",x"52",x"49",x"47",x"49",x"4E",x"41",x"4C", -- 0x2010 + x"FF",x"07",x"1E",x"02",x"55",x"4E",x"41",x"55", -- 0x2018 + x"54",x"48",x"4F",x"52",x"49",x"53",x"45",x"44", -- 0x2020 + x"40",x"44",x"55",x"50",x"4C",x"49",x"43",x"41", -- 0x2028 + x"54",x"49",x"4F",x"4E",x"FF",x"07",x"1F",x"09", -- 0x2030 + x"50",x"52",x"4F",x"48",x"49",x"42",x"49",x"54", -- 0x2038 + x"45",x"44",x"FF",x"07",x"03",x"04",x"53",x"43", -- 0x2040 + x"4F",x"52",x"45",x"40",x"41",x"44",x"56",x"41", -- 0x2048 + x"4E",x"43",x"45",x"40",x"54",x"41",x"42",x"4C", -- 0x2050 + x"45",x"FF",x"40",x"80",x"18",x"50",x"80",x"1C", -- 0x2058 + x"60",x"80",x"1C",x"70",x"80",x"20",x"00",x"07", -- 0x2060 + x"10",x"32",x"30",x"40",x"33",x"30",x"40",x"34", -- 0x2068 + x"30",x"FF",x"01",x"0B",x"15",x"39",x"30",x"30", -- 0x2070 + x"FF",x"00",x"10",x"15",x"31",x"30",x"30",x"FF", -- 0x2078 + x"00",x"14",x"15",x"36",x"30",x"30",x"FF",x"00", -- 0x2080 + x"19",x"15",x"35",x"30",x"30",x"30",x"FF",x"00", -- 0x2088 + x"1D",x"13",x"4D",x"59",x"53",x"54",x"45",x"52", -- 0x2090 + x"59",x"FF",x"03",x"06",x"04",x"4F",x"4E",x"45", -- 0x2098 + x"40",x"4F",x"52",x"40",x"54",x"57",x"4F",x"40", -- 0x20A0 + x"50",x"4C",x"41",x"59",x"45",x"52",x"53",x"FF", -- 0x20A8 + x"04",x"0A",x"07",x"49",x"4E",x"53",x"45",x"52", -- 0x20B0 + x"54",x"40",x"43",x"4F",x"49",x"4E",x"53",x"FF", -- 0x20B8 + x"05",x"18",x"07",x"4F",x"4E",x"45",x"40",x"50", -- 0x20C0 + x"4C",x"41",x"59",x"40",x"32",x"30",x"43",x"FF", -- 0x20C8 + x"05",x"18",x"07",x"4F",x"4E",x"45",x"40",x"50", -- 0x20D0 + x"4C",x"41",x"59",x"40",x"32",x"30",x"43",x"FF", -- 0x20D8 + x"3E",x"02",x"32",x"06",x"40",x"18",x"FE",x"00", -- 0x20E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20F8 + x"00",x"01",x"01",x"01",x"01",x"01",x"03",x"02", -- 0x2100 + x"01",x"06",x"03",x"01",x"08",x"03",x"01",x"0C", -- 0x2108 + x"03",x"02",x"00",x"00",x"00",x"00",x"10",x"03", -- 0x2110 + x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2118 + x"02",x"01",x"02",x"03",x"01",x"04",x"02",x"02", -- 0x2120 + x"08",x"03",x"03",x"0A",x"03",x"03",x"00",x"00", -- 0x2128 + x"00",x"00",x"00",x"00",x"10",x"03",x"04",x"00", -- 0x2130 + x"00",x"00",x"00",x"00",x"00",x"01",x"01",x"01", -- 0x2138 + x"04",x"00",x"02",x"01",x"0F",x"03",x"03",x"06", -- 0x2140 + x"01",x"03",x"10",x"01",x"03",x"00",x"00",x"00", -- 0x2148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2150 + x"00",x"3A",x"10",x"40",x"E6",x"18",x"B7",x"C8", -- 0x2158 + x"CB",x"5F",x"20",x"06",x"DD",x"21",x"00",x"42", -- 0x2160 + x"18",x"04",x"DD",x"21",x"00",x"41",x"DD",x"7E", -- 0x2168 + x"0D",x"B7",x"C0",x"3A",x"00",x"70",x"CB",x"5F", -- 0x2170 + x"28",x"05",x"3A",x"DF",x"21",x"18",x"03",x"3A", -- 0x2178 + x"E0",x"21",x"DD",x"BE",x"00",x"C0",x"DD",x"36", -- 0x2180 + x"0D",x"01",x"DD",x"36",x"0E",x"01",x"DD",x"34", -- 0x2188 + x"09",x"11",x"C9",x"21",x"E7",x"11",x"BB",x"21", -- 0x2190 + x"E7",x"3A",x"10",x"40",x"F5",x"AF",x"32",x"10", -- 0x2198 + x"40",x"21",x"00",x"1D",x"22",x"C0",x"40",x"AF", -- 0x21A0 + x"32",x"00",x"40",x"3A",x"00",x"40",x"FE",x"80", -- 0x21A8 + x"20",x"F9",x"11",x"C9",x"21",x"E7",x"F1",x"32", -- 0x21B0 + x"10",x"40",x"C9",x"01",x"1F",x"04",x"42",x"4F", -- 0x21B8 + x"4E",x"55",x"53",x"40",x"42",x"41",x"53",x"45", -- 0x21C0 + x"FF",x"05",x"1F",x"00",x"40",x"40",x"40",x"40", -- 0x21C8 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x21D0 + x"40",x"40",x"40",x"40",x"40",x"40",x"FF",x"50", -- 0x21D8 + x"75",x"CD",x"00",x"1A",x"2A",x"C0",x"40",x"7C", -- 0x21E0 + x"FE",x"18",x"30",x"07",x"3E",x"FF",x"32",x"00", -- 0x21E8 + x"78",x"18",x"29",x"3A",x"C2",x"40",x"3C",x"32", -- 0x21F0 + x"C2",x"40",x"2A",x"C0",x"40",x"7E",x"FE",x"01", -- 0x21F8 + x"C8",x"32",x"00",x"78",x"FE",x"FF",x"28",x"14", -- 0x2200 + x"3A",x"C2",x"40",x"CB",x"57",x"C8",x"CB",x"97", -- 0x2208 + x"32",x"C2",x"40",x"7E",x"32",x"00",x"78",x"23", -- 0x2210 + x"22",x"C0",x"40",x"C9",x"2A",x"D0",x"22",x"22", -- 0x2218 + x"C0",x"40",x"3A",x"10",x"40",x"E6",x"18",x"20", -- 0x2220 + x"08",x"21",x"00",x"68",x"AF",x"06",x"00",x"D7", -- 0x2228 + x"C9",x"3A",x"A0",x"40",x"B7",x"20",x"3C",x"CD", -- 0x2230 + x"4C",x"22",x"3A",x"0C",x"40",x"DD",x"21",x"D1", -- 0x2238 + x"22",x"DD",x"BE",x"00",x"28",x"1B",x"DD",x"23", -- 0x2240 + x"DD",x"23",x"18",x"F5",x"3A",x"A2",x"40",x"B7", -- 0x2248 + x"C8",x"3A",x"C8",x"40",x"2F",x"FE",x"20",x"28", -- 0x2250 + x"04",x"32",x"00",x"78",x"C9",x"3E",x"FF",x"18", -- 0x2258 + x"F8",x"DD",x"7E",x"00",x"DD",x"21",x"00",x"68", -- 0x2260 + x"06",x"07",x"DD",x"77",x"00",x"CB",x"3F",x"DD", -- 0x2268 + x"23",x"10",x"F7",x"3A",x"A1",x"40",x"B7",x"28", -- 0x2270 + x"0C",x"3A",x"00",x"40",x"07",x"07",x"07",x"07", -- 0x2278 + x"32",x"00",x"78",x"18",x"16",x"3A",x"A0",x"40", -- 0x2280 + x"B7",x"28",x"10",x"3A",x"00",x"40",x"CB",x"5F", -- 0x2288 + x"28",x"04",x"3E",x"20",x"18",x"02",x"3E",x"40", -- 0x2290 + x"32",x"00",x"78",x"3A",x"A9",x"40",x"B7",x"28", -- 0x2298 + x"1E",x"DD",x"21",x"DF",x"22",x"DD",x"BE",x"00", -- 0x22A0 + x"28",x"08",x"DD",x"23",x"DD",x"23",x"DD",x"23", -- 0x22A8 + x"18",x"F3",x"DD",x"66",x"02",x"DD",x"6E",x"01", -- 0x22B0 + x"22",x"C0",x"40",x"AF",x"32",x"A9",x"40",x"3A", -- 0x22B8 + x"A8",x"40",x"FE",x"50",x"C0",x"AF",x"32",x"A8", -- 0x22C0 + x"40",x"21",x"A0",x"1D",x"22",x"C0",x"40",x"C9", -- 0x22C8 + x"01",x"01",x"01",x"02",x"02",x"03",x"03",x"04", -- 0x22D0 + x"13",x"05",x"33",x"06",x"FF",x"00",x"00",x"01", -- 0x22D8 + x"20",x"1D",x"02",x"40",x"1D",x"03",x"40",x"1D", -- 0x22E0 + x"04",x"50",x"1D",x"05",x"60",x"1D",x"06",x"70", -- 0x22E8 + x"1D",x"07",x"80",x"1D",x"08",x"90",x"1D",x"09", -- 0x22F0 + x"A0",x"1D",x"09",x"B0",x"1D",x"50",x"C0",x"1D", -- 0x22F8 + x"0F",x"A0",x"40",x"3C",x"32",x"A0",x"40",x"FD", -- 0x2300 + x"7E",x"04",x"4F",x"E6",x"03",x"B7",x"20",x"02", -- 0x2308 + x"3E",x"01",x"00",x"00",x"5F",x"FD",x"7E",x"05", -- 0x2310 + x"E6",x"3E",x"57",x"3A",x"00",x"40",x"CB",x"3F", -- 0x2318 + x"CB",x"3F",x"E6",x"01",x"B2",x"FD",x"77",x"05", -- 0x2320 + x"FD",x"7E",x"00",x"FE",x"20",x"30",x"04",x"CB", -- 0x2328 + x"E1",x"18",x"06",x"FE",x"E8",x"38",x"02",x"CB", -- 0x2330 + x"A1",x"FD",x"7E",x"01",x"FE",x"80",x"30",x"04", -- 0x2338 + x"CB",x"91",x"18",x"17",x"FE",x"E8",x"38",x"13", -- 0x2340 + x"3A",x"0C",x"40",x"B7",x"20",x"0B",x"CD",x"0A", -- 0x2348 + x"17",x"3E",x"FF",x"32",x"00",x"78",x"C3",x"3E", -- 0x2350 + x"10",x"CB",x"D1",x"3A",x"00",x"40",x"CB",x"77", -- 0x2358 + x"20",x"0E",x"CB",x"61",x"FD",x"7E",x"00",x"20", -- 0x2360 + x"03",x"93",x"18",x"01",x"83",x"FD",x"77",x"00", -- 0x2368 + x"CB",x"51",x"FD",x"7E",x"01",x"28",x"03",x"93", -- 0x2370 + x"18",x"01",x"83",x"FD",x"77",x"01",x"CB",x"51", -- 0x2378 + x"FD",x"7E",x"05",x"28",x"0B",x"CB",x"B7",x"FD", -- 0x2380 + x"77",x"05",x"FD",x"71",x"04",x"C3",x"3E",x"10", -- 0x2388 + x"CB",x"F7",x"18",x"F3",x"3A",x"A2",x"40",x"3C", -- 0x2390 + x"32",x"A2",x"40",x"FD",x"7E",x"01",x"32",x"00", -- 0x2398 + x"78",x"FD",x"7E",x"05",x"E6",x"3F",x"FE",x"15", -- 0x23A0 + x"28",x"50",x"FD",x"7E",x"04",x"E6",x"03",x"B7", -- 0x23A8 + x"20",x"02",x"3E",x"03",x"4F",x"FD",x"7E",x"01", -- 0x23B0 + x"5F",x"3A",x"05",x"40",x"E6",x"1F",x"FE",x"05", -- 0x23B8 + x"20",x"28",x"FD",x"7E",x"01",x"FE",x"30",x"38", -- 0x23C0 + x"21",x"FD",x"66",x"03",x"FD",x"6E",x"02",x"11", -- 0x23C8 + x"20",x"00",x"19",x"7D",x"E6",x"1F",x"FE",x"1D", -- 0x23D0 + x"D2",x"3E",x"10",x"36",x"32",x"3E",x"FC",x"32", -- 0x23D8 + x"00",x"40",x"3E",x"15",x"FD",x"77",x"05",x"C3", -- 0x23E0 + x"3E",x"10",x"7B",x"81",x"FE",x"80",x"38",x"01", -- 0x23E8 + x"3C",x"FE",x"F8",x"30",x"12",x"FD",x"77",x"01", -- 0x23F0 + x"18",x"ED",x"3A",x"00",x"40",x"B7",x"20",x"E7", -- 0x23F8 + x"3E",x"14",x"FD",x"77",x"05",x"18",x"E0",x"CD", -- 0x2400 + x"0A",x"17",x"3E",x"FF",x"32",x"00",x"78",x"18", -- 0x2408 + x"D6",x"3A",x"A1",x"40",x"3C",x"32",x"A1",x"40", -- 0x2410 + x"3A",x"00",x"40",x"5F",x"FD",x"7E",x"04",x"4F", -- 0x2418 + x"E6",x"03",x"B7",x"20",x"02",x"3E",x"03",x"57", -- 0x2420 + x"FD",x"7E",x"00",x"CB",x"61",x"20",x"03",x"82", -- 0x2428 + x"18",x"01",x"92",x"FD",x"77",x"00",x"FE",x"08", -- 0x2430 + x"38",x"CD",x"FE",x"F8",x"30",x"C9",x"CB",x"53", -- 0x2438 + x"20",x"04",x"3E",x"12",x"18",x"02",x"3E",x"13", -- 0x2440 + x"CB",x"61",x"28",x"02",x"CB",x"FF",x"FD",x"77", -- 0x2448 + x"05",x"FD",x"66",x"03",x"FD",x"6E",x"02",x"23", -- 0x2450 + x"11",x"20",x"00",x"19",x"7E",x"FE",x"10",x"28", -- 0x2458 + x"02",x"36",x"FA",x"C3",x"3E",x"10",x"03",x"03", -- 0x2460 + x"00",x"56",x"40",x"20",x"02",x"02",x"00",x"0C", -- 0x2468 + x"40",x"04",x"6F",x"3A",x"14",x"40",x"CB",x"67", -- 0x2470 + x"C8",x"3E",x"01",x"32",x"06",x"70",x"32",x"07", -- 0x2478 + x"70",x"C9",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24F8 + x"3A",x"00",x"60",x"CB",x"6F",x"C8",x"3A",x"14", -- 0x2500 + x"40",x"CB",x"67",x"20",x"0B",x"AF",x"32",x"0F", -- 0x2508 + x"40",x"32",x"06",x"70",x"32",x"07",x"70",x"C9", -- 0x2510 + x"3E",x"01",x"18",x"F2",x"3E",x"C0",x"CD",x"4C", -- 0x2518 + x"00",x"11",x"36",x"25",x"E7",x"3E",x"C0",x"CD", -- 0x2520 + x"4C",x"00",x"11",x"4A",x"25",x"E7",x"3E",x"80", -- 0x2528 + x"CD",x"4C",x"00",x"C3",x"3C",x"1F",x"04",x"14", -- 0x2530 + x"04",x"46",x"49",x"52",x"53",x"54",x"40",x"43", -- 0x2538 + x"52",x"45",x"44",x"49",x"54",x"40",x"34",x"30", -- 0x2540 + x"43",x"FF",x"05",x"18",x"04",x"46",x"55",x"52", -- 0x2548 + x"54",x"48",x"45",x"52",x"40",x"43",x"52",x"45", -- 0x2550 + x"44",x"49",x"54",x"53",x"40",x"32",x"30",x"43", -- 0x2558 + x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25F8 + x"3A",x"A0",x"40",x"3C",x"32",x"A0",x"40",x"FD", -- 0x2600 + x"7E",x"04",x"4F",x"E6",x"03",x"B7",x"20",x"02", -- 0x2608 + x"3E",x"02",x"5F",x"FD",x"7E",x"05",x"E6",x"FE", -- 0x2610 + x"57",x"3A",x"00",x"40",x"CB",x"3F",x"CB",x"3F", -- 0x2618 + x"E6",x"01",x"B2",x"FD",x"77",x"05",x"FD",x"7E", -- 0x2620 + x"00",x"FE",x"20",x"30",x"02",x"CB",x"E1",x"FE", -- 0x2628 + x"E8",x"38",x"02",x"CB",x"A1",x"FD",x"7E",x"01", -- 0x2630 + x"FE",x"80",x"30",x"02",x"CB",x"91",x"FE",x"E8", -- 0x2638 + x"38",x"13",x"3A",x"0C",x"40",x"B7",x"20",x"0B", -- 0x2640 + x"CD",x"26",x"17",x"3E",x"FF",x"32",x"00",x"78", -- 0x2648 + x"C3",x"41",x"10",x"CB",x"D1",x"3A",x"00",x"40", -- 0x2650 + x"CB",x"77",x"20",x"0E",x"CB",x"61",x"FD",x"7E", -- 0x2658 + x"00",x"20",x"03",x"93",x"18",x"01",x"83",x"FD", -- 0x2660 + x"77",x"00",x"CB",x"51",x"FD",x"7E",x"01",x"28", -- 0x2668 + x"03",x"93",x"18",x"01",x"83",x"FD",x"77",x"01", -- 0x2670 + x"CB",x"51",x"FD",x"7E",x"05",x"28",x"0B",x"CB", -- 0x2678 + x"B7",x"FD",x"77",x"05",x"FD",x"71",x"04",x"C3", -- 0x2680 + x"41",x"10",x"CB",x"F7",x"18",x"F3",x"3A",x"A2", -- 0x2688 + x"40",x"3C",x"32",x"A2",x"40",x"FD",x"7E",x"01", -- 0x2690 + x"2F",x"32",x"00",x"78",x"FD",x"7E",x"05",x"E6", -- 0x2698 + x"3F",x"FE",x"15",x"28",x"50",x"FD",x"7E",x"04", -- 0x26A0 + x"E6",x"03",x"B7",x"20",x"02",x"3E",x"02",x"4F", -- 0x26A8 + x"FD",x"7E",x"01",x"FE",x"80",x"38",x"01",x"3C", -- 0x26B0 + x"5F",x"3A",x"05",x"40",x"E6",x"1F",x"FE",x"04", -- 0x26B8 + x"20",x"27",x"FD",x"66",x"03",x"FD",x"6E",x"02", -- 0x26C0 + x"11",x"20",x"00",x"19",x"7D",x"E6",x"1F",x"FE", -- 0x26C8 + x"1B",x"30",x"10",x"FE",x"04",x"38",x"0C",x"36", -- 0x26D0 + x"32",x"3E",x"FC",x"32",x"00",x"40",x"3E",x"15", -- 0x26D8 + x"FD",x"77",x"05",x"FD",x"7E",x"01",x"C3",x"41", -- 0x26E0 + x"10",x"2F",x"7B",x"81",x"FE",x"F0",x"30",x"12", -- 0x26E8 + x"FD",x"77",x"01",x"18",x"F1",x"3A",x"00",x"40", -- 0x26F0 + x"B7",x"20",x"EB",x"3E",x"14",x"FD",x"77",x"05", -- 0x26F8 + x"18",x"E4",x"CD",x"26",x"17",x"3E",x"FF",x"32", -- 0x2700 + x"00",x"78",x"18",x"DA",x"3A",x"A1",x"40",x"3C", -- 0x2708 + x"32",x"A1",x"40",x"3A",x"00",x"40",x"5F",x"FD", -- 0x2710 + x"7E",x"04",x"4F",x"E6",x"03",x"B7",x"20",x"02", -- 0x2718 + x"3E",x"03",x"57",x"FD",x"7E",x"00",x"CB",x"61", -- 0x2720 + x"20",x"03",x"82",x"18",x"01",x"92",x"FD",x"77", -- 0x2728 + x"00",x"FE",x"08",x"38",x"CD",x"FE",x"F8",x"30", -- 0x2730 + x"C9",x"CB",x"53",x"20",x"04",x"3E",x"12",x"18", -- 0x2738 + x"02",x"3E",x"13",x"CB",x"61",x"28",x"02",x"CB", -- 0x2740 + x"FF",x"FD",x"77",x"05",x"FD",x"66",x"03",x"FD", -- 0x2748 + x"6E",x"02",x"23",x"11",x"20",x"00",x"19",x"7E", -- 0x2750 + x"FE",x"10",x"28",x"02",x"36",x"FA",x"C3",x"41", -- 0x2758 + x"10",x"AF",x"06",x"04",x"D7",x"C9",x"00",x"00" + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd new file mode 100644 index 00000000..7eb01da4 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd @@ -0,0 +1,33 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GALAXIAN_6L is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(4 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GALAXIAN_6L is + + + type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"FF",x"07",x"C0",x"00",x"07",x"C0",x"3F", -- 0x0000 + x"00",x"38",x"07",x"C0",x"00",x"07",x"C0",x"38", -- 0x0008 + x"00",x"3F",x"38",x"07",x"00",x"C0",x"3F",x"07", -- 0x0010 + x"00",x"F8",x"07",x"38",x"00",x"C0",x"38",x"C7" -- 0x0018 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/gfx1.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/gfx1.vhd new file mode 100644 index 00000000..1b3ce2c4 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/ROM/gfx1.vhd @@ -0,0 +1,547 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + use UNISIM.Vcomponents.all; + +entity GFX1 is + port ( + CLK : in std_logic; + ENA : in std_logic; + ADDR : in std_logic_vector(11 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GFX1 is + + + type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0158 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0160 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0168 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0170 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0178 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0180 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0188 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0190 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0198 + x"00",x"00",x"00",x"03",x"0F",x"1F",x"41",x"00", -- 0x01A0 + x"08",x"3C",x"FE",x"E7",x"8F",x"FE",x"FC",x"00", -- 0x01A8 + x"00",x"41",x"1F",x"0F",x"03",x"00",x"00",x"00", -- 0x01B0 + x"00",x"FC",x"FE",x"8F",x"E7",x"FE",x"3C",x"08", -- 0x01B8 + x"06",x"08",x"03",x"24",x"40",x"10",x"20",x"40", -- 0x01C0 + x"60",x"10",x"00",x"30",x"0A",x"21",x"10",x"00", -- 0x01C8 + x"88",x"A8",x"24",x"08",x"40",x"26",x"10",x"03", -- 0x01D0 + x"15",x"15",x"24",x"80",x"12",x"60",x"04",x"90", -- 0x01D8 + x"00",x"00",x"00",x"00",x"04",x"00",x"08",x"09", -- 0x01E0 + x"00",x"00",x"00",x"00",x"80",x"20",x"80",x"50", -- 0x01E8 + x"00",x"02",x"08",x"04",x"00",x"00",x"00",x"00", -- 0x01F0 + x"90",x"00",x"20",x"40",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"08",x"08",x"E5",x"15",x"15",x"3A", -- 0x0200 + x"00",x"00",x"80",x"90",x"20",x"4E",x"5F",x"BB", -- 0x0208 + x"3A",x"15",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0210 + x"A3",x"5B",x"4E",x"20",x"90",x"80",x"00",x"00", -- 0x0218 + x"00",x"00",x"01",x"22",x"14",x"15",x"15",x"3A", -- 0x0220 + x"00",x"00",x"20",x"48",x"90",x"2E",x"5F",x"BB", -- 0x0228 + x"3A",x"15",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0230 + x"A3",x"5B",x"2E",x"90",x"48",x"20",x"00",x"00", -- 0x0238 + x"10",x"48",x"2C",x"1C",x"06",x"02",x"00",x"00", -- 0x0240 + x"00",x"02",x"04",x"05",x"8E",x"2C",x"98",x"20", -- 0x0248 + x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0250 + x"00",x"40",x"33",x"8C",x"60",x"1E",x"C0",x"38", -- 0x0258 + x"11",x"0A",x"0E",x"04",x"06",x"02",x"00",x"00", -- 0x0260 + x"10",x"14",x"14",x"1C",x"8C",x"28",x"98",x"20", -- 0x0268 + x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0270 + x"01",x"42",x"3C",x"81",x"7E",x"00",x"84",x"78", -- 0x0278 + x"00",x"00",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x0280 + x"50",x"90",x"24",x"44",x"18",x"00",x"80",x"40", -- 0x0288 + x"00",x"06",x"06",x"00",x"01",x"01",x"00",x"00", -- 0x0290 + x"40",x"80",x"00",x"18",x"44",x"24",x"90",x"50", -- 0x0298 + x"00",x"06",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x02A0 + x"00",x"00",x"3C",x"40",x"1F",x"00",x"80",x"C0", -- 0x02A8 + x"00",x"06",x"06",x"00",x"01",x"01",x"06",x"00", -- 0x02B0 + x"C0",x"80",x"00",x"1F",x"40",x"38",x"00",x"00", -- 0x02B8 + x"00",x"FF",x"00",x"9F",x"CF",x"9F",x"00",x"FF", -- 0x02C0 + x"FF",x"FF",x"FF",x"C1",x"BE",x"BE",x"80",x"FF", -- 0x02C8 + x"88",x"77",x"00",x"FF",x"80",x"77",x"80",x"FF", -- 0x02D0 + x"BF",x"80",x"BF",x"FF",x"FE",x"FE",x"80",x"FF", -- 0x02D8 + x"FF",x"80",x"77",x"80",x"FF",x"7E",x"00",x"7E", -- 0x02E0 + x"FE",x"80",x"DE",x"FF",x"C9",x"B6",x"B6",x"C9", -- 0x02E8 + x"FF",x"00",x"CF",x"9F",x"00",x"FF",x"7E",x"76", -- 0x02F0 + x"FF",x"C1",x"B6",x"B6",x"CF",x"FE",x"80",x"DE", -- 0x02F8 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3C",x"1C",x"08", -- 0x0310 + x"00",x"00",x"00",x"00",x"00",x"80",x"80",x"80", -- 0x0318 + x"7C",x"FE",x"FE",x"C8",x"C0",x"FE",x"7E",x"3C", -- 0x0320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 + x"7E",x"FF",x"9F",x"DD",x"65",x"35",x"1C",x"08", -- 0x0330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 + x"7C",x"FE",x"FE",x"E2",x"C0",x"EE",x"7E",x"3C", -- 0x0340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 + x"7E",x"FF",x"EF",x"ED",x"79",x"38",x"38",x"10", -- 0x0350 + x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0358 + x"7C",x"FE",x"FC",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 + x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1C",x"08", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 + x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 + x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 + x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 + x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 + x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x0420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 + x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x0430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x0440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 + x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x0450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 + x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x0460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 + x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 + x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 + x"7E",x"FF",x"EF",x"E5",x"7D",x"3D",x"1C",x"08", -- 0x0490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 + x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x04A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 + x"7E",x"FF",x"9F",x"DD",x"65",x"34",x"1C",x"08", -- 0x04B0 + x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x04B8 + x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x04C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 + x"7E",x"FF",x"EF",x"E5",x"7C",x"3C",x"1C",x"08", -- 0x04D0 + x"00",x"00",x"00",x"00",x"80",x"40",x"40",x"00", -- 0x04D8 + x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x04E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 + x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1D",x"08", -- 0x04F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 + x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 + x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 + x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x05B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 + x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x05D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 + x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x05F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 + x"7F",x"3F",x"3F",x"1E",x"1C",x"0F",x"0F",x"07", -- 0x0610 + x"C0",x"00",x"E0",x"F0",x"E0",x"C0",x"80",x"00", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 + x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x0630 + x"7C",x"F0",x"FE",x"EF",x"CE",x"FC",x"F8",x"70", -- 0x0638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 + x"1C",x"18",x"18",x"1B",x"1F",x"0F",x"03",x"00", -- 0x0650 + x"18",x"7D",x"FD",x"CD",x"DE",x"DC",x"F8",x"70", -- 0x0658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 + x"08",x"1C",x"3D",x"7D",x"E7",x"EF",x"FF",x"7E", -- 0x0668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0678 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 + x"3C",x"3E",x"1E",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0690 + x"E0",x"70",x"78",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 + x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x06B0 + x"18",x"CC",x"CE",x"DE",x"FE",x"FC",x"F8",x"70", -- 0x06B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"1C",x"3E", -- 0x06C8 + x"00",x"00",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x06D0 + x"7F",x"FF",x"FF",x"FF",x"FE",x"FC",x"38",x"80", -- 0x06D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 + x"00",x"1C",x"3F",x"7F",x"EF",x"E7",x"F3",x"78", -- 0x06E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x06F8 + x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0700 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0708 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0710 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0718 + x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0720 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0728 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0730 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0738 + x"46",x"2F",x"1F",x"CF",x"3F",x"0F",x"3F",x"C6", -- 0x0740 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0748 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0760 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0768 + x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0770 + x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"09",x"17",x"3C",x"1B",x"3F",x"EF",x"DF",x"BF", -- 0x0780 + x"80",x"E0",x"F8",x"CC",x"F4",x"DE",x"EF",x"FF", -- 0x0788 + x"77",x"57",x"DB",x"77",x"3F",x"19",x"0F",x"04", -- 0x0790 + x"EA",x"EA",x"DB",x"7E",x"EC",x"9C",x"F8",x"40", -- 0x0798 + x"03",x"07",x"1F",x"1F",x"3B",x"3F",x"37",x"36", -- 0x07A0 + x"C0",x"E0",x"F0",x"F8",x"7C",x"DC",x"7C",x"AC", -- 0x07A8 + x"3F",x"3D",x"37",x"1B",x"1F",x"1F",x"0F",x"07", -- 0x07B0 + x"6C",x"FC",x"DC",x"BC",x"F8",x"F8",x"F0",x"E0", -- 0x07B8 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C0 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C8 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D0 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D8 + x"1E",x"3F",x"7E",x"00",x"00",x"7E",x"3F",x"1E", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0800 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0808 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0810 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0818 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0820 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0828 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0830 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0838 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0840 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0848 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0850 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0858 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0860 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0868 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0870 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0888 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0890 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0898 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x08A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x08A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x08B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x08B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x08C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x08C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x08D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x08D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x08E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x08E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x08F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x08F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0900 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0908 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0910 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0918 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0920 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0928 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0930 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0938 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0940 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0948 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0950 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0958 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0960 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0968 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0970 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0978 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0980 + x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0988 + x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0990 + x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0998 + x"00",x"00",x"00",x"00",x"01",x"00",x"5E",x"FF", -- 0x09A0 + x"00",x"00",x"18",x"7C",x"F4",x"78",x"00",x"F8", -- 0x09A8 + x"FF",x"5E",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x09B0 + x"F8",x"00",x"78",x"F4",x"7C",x"18",x"00",x"00", -- 0x09B8 + x"00",x"00",x"03",x"04",x"01",x"12",x"22",x"00", -- 0x09C0 + x"00",x"00",x"00",x"30",x"08",x"00",x"00",x"C0", -- 0x09C8 + x"02",x"21",x"20",x"10",x"00",x"06",x"00",x"00", -- 0x09D0 + x"44",x"04",x"04",x"00",x"10",x"60",x"00",x"00", -- 0x09D8 + x"02",x"00",x"00",x"10",x"10",x"20",x"00",x"01", -- 0x09E0 + x"C0",x"00",x"10",x"08",x"00",x"00",x"84",x"40", -- 0x09E8 + x"20",x"22",x"00",x"00",x"10",x"00",x"00",x"06", -- 0x09F0 + x"80",x"04",x"04",x"00",x"00",x"10",x"00",x"40", -- 0x09F8 + x"00",x"00",x"08",x"08",x"E5",x"15",x"42",x"2F", -- 0x0A00 + x"00",x"00",x"80",x"90",x"20",x"40",x"84",x"DE", -- 0x0A08 + x"05",x"42",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0A10 + x"5E",x"84",x"40",x"20",x"90",x"80",x"00",x"00", -- 0x0A18 + x"00",x"00",x"01",x"22",x"14",x"15",x"42",x"2F", -- 0x0A20 + x"00",x"00",x"20",x"48",x"90",x"20",x"84",x"DE", -- 0x0A28 + x"05",x"42",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0A30 + x"5E",x"84",x"20",x"90",x"48",x"20",x"00",x"00", -- 0x0A38 + x"10",x"48",x"2C",x"1C",x"06",x"03",x"01",x"03", -- 0x0A40 + x"00",x"02",x"04",x"05",x"4E",x"CC",x"78",x"E0", -- 0x0A48 + x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0A50 + x"E0",x"E0",x"F3",x"CC",x"E0",x"9E",x"C0",x"38", -- 0x0A58 + x"11",x"0A",x"0E",x"04",x"06",x"03",x"01",x"03", -- 0x0A60 + x"10",x"14",x"14",x"1C",x"4C",x"C8",x"78",x"E0", -- 0x0A68 + x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0A70 + x"E1",x"E2",x"FC",x"C1",x"FE",x"80",x"84",x"78", -- 0x0A78 + x"00",x"00",x"01",x"01",x"03",x"01",x"0B",x"0F", -- 0x0A80 + x"50",x"90",x"24",x"C4",x"D8",x"E0",x"60",x"B0", -- 0x0A88 + x"0F",x"0B",x"01",x"03",x"01",x"01",x"00",x"00", -- 0x0A90 + x"B0",x"60",x"E0",x"D8",x"C4",x"24",x"90",x"50", -- 0x0A98 + x"00",x"06",x"01",x"01",x"03",x"07",x"0D",x"0F", -- 0x0AA0 + x"00",x"00",x"3C",x"C0",x"DF",x"E0",x"60",x"30", -- 0x0AA8 + x"0F",x"0D",x"07",x"03",x"01",x"01",x"06",x"00", -- 0x0AB0 + x"30",x"60",x"E0",x"DF",x"C0",x"38",x"00",x"00", -- 0x0AB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF8 + x"70",x"F8",x"FC",x"BE",x"9F",x"CC",x"78",x"30", -- 0x0B00 + x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0B08 + x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1D",x"09", -- 0x0B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 + x"70",x"F8",x"FC",x"BF",x"BF",x"CC",x"78",x"30", -- 0x0B20 + x"00",x"00",x"00",x"00",x"C0",x"00",x"00",x"00", -- 0x0B28 + x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"08", -- 0x0B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0B38 + x"70",x"F8",x"CC",x"9C",x"BF",x"DC",x"78",x"30", -- 0x0B40 + x"00",x"00",x"40",x"80",x"00",x"00",x"00",x"00", -- 0x0B48 + x"78",x"FC",x"9E",x"DE",x"6A",x"39",x"39",x"12", -- 0x0B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 + x"70",x"F9",x"CE",x"8E",x"9C",x"FC",x"78",x"30", -- 0x0B60 + x"C0",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 + x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"09", -- 0x0B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0B88 + x"70",x"F8",x"FC",x"BE",x"9E",x"CD",x"78",x"30", -- 0x0B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0B98 + x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0BA0 + x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x0BA8 + x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0BB0 + x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x0BB8 + x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0BC0 + x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x0BC8 + x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0BD0 + x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x0BD8 + x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0BE0 + x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 + x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0BF0 + x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 + x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 + x"78",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 + x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 + x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 + x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 + x"78",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 + x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 + x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 + x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 + x"78",x"FC",x"9E",x"DE",x"66",x"36",x"1E",x"0A", -- 0x0C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 + x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 + x"78",x"FC",x"EE",x"E6",x"7E",x"3D",x"1C",x"08", -- 0x0CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CB8 + x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 + x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1C",x"09", -- 0x0CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CD8 + x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 + x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1E",x"09", -- 0x0CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 + x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 + x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 + x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 + x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 + x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"70", -- 0x0E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 + x"78",x"37",x"3F",x"1F",x"1F",x"0C",x"0D",x"07", -- 0x0E10 + x"00",x"00",x"E0",x"30",x"60",x"C0",x"80",x"00", -- 0x0E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 + x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0E30 + x"00",x"30",x"7E",x"F3",x"F6",x"CC",x"D8",x"70", -- 0x0E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 + x"19",x"1F",x"1E",x"1D",x"1F",x"0F",x"07",x"06", -- 0x0E50 + x"18",x"7C",x"FC",x"FC",x"B8",x"B0",x"D0",x"60", -- 0x0E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 + x"08",x"1C",x"34",x"64",x"DE",x"9E",x"FC",x"78", -- 0x0E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0E78 + x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"32", -- 0x0E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 + x"3F",x"3D",x"1D",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0E90 + x"00",x"C0",x"E0",x"30",x"F8",x"F0",x"E0",x"C0", -- 0x0E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 + x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0EB0 + x"60",x"30",x"7E",x"EE",x"CE",x"FC",x"F8",x"70", -- 0x0EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"9C",x"3E", -- 0x0EC8 + x"01",x"03",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x0ED0 + x"FE",x"FE",x"FE",x"FC",x"F8",x"F0",x"E0",x"FC", -- 0x0ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 + x"00",x"1C",x"3C",x"7E",x"FE",x"DE",x"CC",x"7F", -- 0x0EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 + x"71",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0EF8 + x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F00 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F08 + x"1F",x"36",x"6F",x"FF",x"CF",x"C6",x"40",x"40", -- 0x0F10 + x"80",x"C0",x"60",x"F0",x"30",x"30",x"20",x"20", -- 0x0F18 + x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F20 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F28 + x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"20",x"20", -- 0x0F30 + x"80",x"C0",x"60",x"F0",x"30",x"60",x"40",x"40", -- 0x0F38 + x"44",x"2C",x"1C",x"CC",x"3C",x"0C",x"3C",x"C4", -- 0x0F40 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F48 + x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"30",x"10", -- 0x0F50 + x"80",x"C0",x"60",x"F0",x"30",x"60",x"C0",x"80", -- 0x0F58 + x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F60 + x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F68 + x"1F",x"36",x"6F",x"FF",x"FF",x"76",x"19",x"06", -- 0x0F70 + x"80",x"C0",x"60",x"F0",x"F0",x"E0",x"80",x"00", -- 0x0F78 + x"0F",x"1F",x"3C",x"3B",x"7E",x"ED",x"DD",x"FF", -- 0x0F80 + x"E0",x"F0",x"F8",x"CC",x"F6",x"FF",x"FF",x"3F", -- 0x0F88 + x"FD",x"DE",x"DF",x"6F",x"7F",x"39",x"1F",x"07", -- 0x0F90 + x"BB",x"FB",x"FB",x"FE",x"EE",x"9C",x"F8",x"C0", -- 0x0F98 + x"01",x"07",x"1F",x"0F",x"2F",x"1F",x"3F",x"3E", -- 0x0FA0 + x"00",x"E0",x"E0",x"F0",x"FC",x"FC",x"78",x"BC", -- 0x0FA8 + x"1F",x"1D",x"3F",x"1F",x"0F",x"1F",x"0F",x"01", -- 0x0FB0 + x"7C",x"F8",x"F8",x"FC",x"F8",x"E8",x"F0",x"A0", -- 0x0FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 + x"24",x"14",x"0C",x"3F",x"3F",x"0C",x"14",x"24", -- 0x0FC8 + x"20",x"90",x"40",x"F0",x"F0",x"40",x"90",x"20", -- 0x0FD0 + x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x0FD8 + x"00",x"0C",x"14",x"FE",x"FE",x"14",x"0C",x"00", -- 0x0FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + DATA <= ROM(to_integer(unsigned(ADDR))); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/WarOfTheBugs.sv b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/WarOfTheBugs.sv new file mode 100644 index 00000000..63673276 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/WarOfTheBugs.sv @@ -0,0 +1,176 @@ +//============================================================================ +// Arcade: WarOfTheBugs +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module WarOfTheBugs +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "WarOfTheBugs;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +assign LED = 1; + +wire clk_18, clk_12, clk_6, clk_4p5; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_18), + .c1(clk_12), + .c2(clk_6), + .c3(clk_4p5)//for now, needs a fix +); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +galaxian warofbugs +( + .W_CLK_18M(clk_18), + .W_CLK_12M(clk_12), + .W_CLK_6M(clk_6), + .I_RESET(status[0] | status[6] | buttons[1]), + .P1_CSJUDLR({m_coin,m_start1,m_fire,m_up,m_down,m_left,m_right}), + .P2_CSJUDLR({1'b0, m_start2,m_fire,m_up,m_down,m_left,m_right}), + .W_R(r), + .W_G(g), + .W_B(b), + .W_H_SYNC(hs), + .W_V_SYNC(vs), + .HBLANK(hblank), + .VBLANK(vblank), + .W_SDAT_A(audio_a), + .W_SDAT_B(audio_b) +); + +wire [7:0] audio_a, audio_b; +wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a}; + +dac dac ( + .clk_i(clk_18), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +wire hs, vs; +wire [2:0] r, g, b; +wire hblank, vblank; +wire blankn = ~(hblank | vblank); +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_18), + .ce_pix(clk_4p5), + .ce_pix_actual(clk_4p5), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn?r:"000"), + .G(blankn?g:"000"), + .B(blankn?b:"000"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_18 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_18), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.tcl b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.v b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.v new file mode 100644 index 00000000..a0609192 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "163543" diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c07d2629 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1093 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..6bd576cf --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..ee217402 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..679730ab --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80as.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80as.vhd new file mode 100644 index 00000000..fe477f50 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/cpu/T80as.vhd @@ -0,0 +1,283 @@ +------------------------------------------------------------------------------ +-- t80as.vhd : The non-tristate signal edition of t80a.vhd +-- +-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh +-- +-- 1.separate 'D' to 'DO' and 'DI'. +-- 2.added 'DOE' to 'DO' enable signal.(data direction) +-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. +-- +-- There is a mark of "--AS" in all the change points. +-- +------------------------------------------------------------------------------ + +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80as is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); +--AS-- D : inout std_logic_vector(7 downto 0) +--AS>> + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + DOE : out std_logic +--< 'Z'); +--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); +--AS>> + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DOE <= Write when BUSAK_n_i = '1' else '0'; +--< Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, +-- DInst => D, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then +--AS-- DI_Reg <= to_x01(D); +--AS>> + DI_Reg <= to_x01(DI); +--< 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/dac.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/dac.vhd new file mode 100644 index 00000000..b1ecdcb7 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/dpram.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..dafe8385 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/galaxian.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/galaxian.vhd new file mode 100644 index 00000000..a2c66505 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/galaxian.vhd @@ -0,0 +1,450 @@ +------------------------------------------------------------------------------ +-- FPGA GALAXIAN +-- +-- Version downto 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important not +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +-- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--use work.pkg_galaxian.all; + +entity galaxian is + port( + W_CLK_18M : in std_logic; + W_CLK_12M : in std_logic; + W_CLK_6M : in std_logic; + + P1_CSJUDLR : in std_logic_vector(6 downto 0); + P2_CSJUDLR : in std_logic_vector(6 downto 0); + I_RESET : in std_logic; + + W_R : out std_logic_vector(2 downto 0); + W_G : out std_logic_vector(2 downto 0); + W_B : out std_logic_vector(2 downto 0); + HBLANK : out std_logic; + VBLANK : out std_logic; + W_H_SYNC : out std_logic; + W_V_SYNC : out std_logic; + W_SDAT_A : out std_logic_vector( 7 downto 0); + W_SDAT_B : out std_logic_vector( 7 downto 0); + O_CMPBL : out std_logic + ); +end; + +architecture RTL of galaxian is + -- CPU ADDRESS BUS + signal W_A : std_logic_vector(15 downto 0) := (others => '0'); + -- CPU IF + signal W_CPU_CLK : std_logic := '0'; + signal W_CPU_MREQn : std_logic := '0'; + signal W_CPU_NMIn : std_logic := '0'; + signal W_CPU_RDn : std_logic := '0'; + signal W_CPU_RFSHn : std_logic := '0'; + signal W_CPU_WAITn : std_logic := '0'; + signal W_CPU_WRn : std_logic := '0'; + signal W_CPU_WR : std_logic := '0'; + signal W_RESETn : std_logic := '0'; + -------- H and V COUNTER ------------------------- + signal W_C_BLn : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_C_BLXn : std_logic := '0'; + signal W_H_BL : std_logic := '0'; + signal W_H_SYNC_int : std_logic := '0'; + signal W_V_BLn : std_logic := '0'; + signal W_V_BL2n : std_logic := '0'; + signal W_V_SYNC_int : std_logic := '0'; + signal W_H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal W_V_CNT : std_logic_vector(7 downto 0) := (others => '0'); + -------- CPU RAM ---------------------------- + signal W_CPU_RAM_DO : std_logic_vector(7 downto 0) := (others => '0'); + -------- ADDRESS DECDER ---------------------- + signal W_BD_G : std_logic := '0'; + signal W_CPU_RAM_CS : std_logic := '0'; + signal W_CPU_RAM_RD : std_logic := '0'; +-- signal W_CPU_RAM_WR : std_logic := '0'; + signal W_CPU_ROM_CS : std_logic := '0'; + signal W_DIP_OE : std_logic := '0'; + signal W_H_FLIP : std_logic := '0'; + signal W_DRIVER_WE : std_logic := '0'; + signal W_OBJ_RAM_RD : std_logic := '0'; + signal W_OBJ_RAM_RQ : std_logic := '0'; + signal W_OBJ_RAM_WR : std_logic := '0'; + signal W_PITCH : std_logic := '0'; + signal W_SOUND_WE : std_logic := '0'; + signal W_STARS_ON : std_logic := '0'; + signal W_STARS_OFFn : std_logic := '0'; + signal W_SW0_OE : std_logic := '0'; + signal W_SW1_OE : std_logic := '0'; + signal W_V_FLIP : std_logic := '0'; + signal W_VID_RAM_RD : std_logic := '0'; + signal W_VID_RAM_WR : std_logic := '0'; + signal W_WDR_OE : std_logic := '0'; + --------- INPORT ----------------------------- + signal W_SW_DO : std_logic_vector( 7 downto 0) := (others => '0'); + --------- VIDEO ----------------------------- + signal W_VID_DO : std_logic_vector( 7 downto 0) := (others => '0'); + ----- DATA I/F ------------------------------------- + signal W_CPU_ROM_DO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_ROM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDO : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_BDI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_CPU_RAM_CLK : std_logic := '0'; + signal W_VOL1 : std_logic := '0'; + signal W_VOL2 : std_logic := '0'; + signal W_FIRE : std_logic := '0'; + signal W_HIT : std_logic := '0'; + signal W_FS : std_logic_vector( 2 downto 0) := (others => '0'); + + signal blx_comb : std_logic := '0'; + signal W_1VF : std_logic := '0'; + signal W_256HnX : std_logic := '0'; + signal W_8HF : std_logic := '0'; + signal W_DAC_A : std_logic := '0'; + signal W_DAC_B : std_logic := '0'; + signal W_MISSILEn : std_logic := '0'; + signal W_SHELLn : std_logic := '0'; + signal W_MS_D : std_logic := '0'; + signal W_MS_R : std_logic := '0'; + signal W_MS_G : std_logic := '0'; + signal W_MS_B : std_logic := '0'; + + signal new_sw : std_logic_vector( 2 downto 0) := (others => '0'); + signal in_game : std_logic_vector( 1 downto 0) := (others => '0'); + signal ROM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal rst_count : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_STARS_B : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_G : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_STARS_R : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_VIDEO_B : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_G : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_VIDEO_R : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_WAV_A0 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A1 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_A2 : std_logic_vector(18 downto 0) := (others => '0'); + signal W_WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_WAV_D2 : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_DAC : std_logic_vector( 3 downto 0) := (others => '0'); + +begin + mc_vid : entity work.MC_VIDEO + port map( + I_CLK_18M => W_CLK_18M, + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT => W_H_CNT, + I_V_CNT => W_V_CNT, + I_H_FLIP => W_H_FLIP, + I_V_FLIP => W_V_FLIP, + I_V_BLn => W_V_BLn, + I_C_BLn => W_C_BLn, + I_A => W_A(9 downto 0), + I_OBJ_SUB_A => "000", + I_BD => W_BDI, + I_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + I_OBJ_RAM_RD => W_OBJ_RAM_RD, + I_OBJ_RAM_WR => W_OBJ_RAM_WR, + I_VID_RAM_RD => W_VID_RAM_RD, + I_VID_RAM_WR => W_VID_RAM_WR, + I_DRIVER_WR => W_DRIVER_WE, + O_C_BLnX => W_C_BLnX, + O_8HF => W_8HF, + O_256HnX => W_256HnX, + O_1VF => W_1VF, + O_MISSILEn => W_MISSILEn, + O_SHELLn => W_SHELLn, + O_BD => W_VID_DO, + O_VID => W_VID, + O_COL => W_COL + ); + + cpu : entity work.T80as + port map ( + RESET_n => W_RESETn, + CLK_n => W_CPU_CLK, + WAIT_n => W_CPU_WAITn, + INT_n => '1', + NMI_n => W_CPU_NMIn, + BUSRQ_n => '1', + MREQ_n => W_CPU_MREQn, + RD_n => W_CPU_RDn, + WR_n => W_CPU_WRn, + RFSH_n => W_CPU_RFSHn, + A => W_A, + DI => W_BDO, + DO => W_BDI, + M1_n => open, + IORQ_n => open, + HALT_n => open, + BUSAK_n => open, + DOE => open + ); + + mc_cpu_ram : entity work.MC_CPU_RAM + port map ( + I_CLK => W_CPU_RAM_CLK, + I_ADDR => W_A(9 downto 0), + I_D => W_BDI, + I_WE => W_CPU_WR, + I_OE => W_CPU_RAM_RD, + O_D => W_CPU_RAM_DO + ); + + mc_adec : entity work.MC_ADEC + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_CPU_CLK => W_CPU_CLK, + I_RSTn => W_RESETn, + + I_CPU_A => W_A, + I_CPU_D => W_BDI(0), + I_MREQn => W_CPU_MREQn, + I_RFSHn => W_CPU_RFSHn, + I_RDn => W_CPU_RDn, + I_WRn => W_CPU_WRn, + I_H_BL => W_H_BL, + I_V_BLn => W_V_BLn, + + O_WAITn => W_CPU_WAITn, + O_NMIn => W_CPU_NMIn, + O_CPU_ROM_CS => W_CPU_ROM_CS, + O_CPU_RAM_RD => W_CPU_RAM_RD, +-- O_CPU_RAM_WR => W_CPU_RAM_WR, + O_CPU_RAM_CS => W_CPU_RAM_CS, + O_OBJ_RAM_RD => W_OBJ_RAM_RD, + O_OBJ_RAM_WR => W_OBJ_RAM_WR, + O_OBJ_RAM_RQ => W_OBJ_RAM_RQ, + O_VID_RAM_RD => W_VID_RAM_RD, + O_VID_RAM_WR => W_VID_RAM_WR, + O_SW0_OE => W_SW0_OE, + O_SW1_OE => W_SW1_OE, + O_DIP_OE => W_DIP_OE, + O_WDR_OE => W_WDR_OE, + O_DRIVER_WE => W_DRIVER_WE, + O_SOUND_WE => W_SOUND_WE, + O_PITCH => W_PITCH, + O_H_FLIP => W_H_FLIP, + O_V_FLIP => W_V_FLIP, + O_BD_G => W_BD_G, + O_STARS_ON => W_STARS_ON + ); + + -- active high buttons + mc_inport : entity work.MC_INPORT + port map ( + I_COIN1 => P1_CSJUDLR(6), + I_COIN2 => P2_CSJUDLR(6), + I_1P_START => P1_CSJUDLR(5), + I_2P_START => P2_CSJUDLR(5), + I_1P_SH => P1_CSJUDLR(4), + I_2P_SH => P2_CSJUDLR(4), + I_1P_UP => P1_CSJUDLR(3), + I_2P_UP => P2_CSJUDLR(3), + I_1P_DW => P1_CSJUDLR(2), + I_2P_DW => P2_CSJUDLR(2), + I_1P_LE => P1_CSJUDLR(1), + I_2P_LE => P2_CSJUDLR(1), + I_1P_RI => P1_CSJUDLR(0), + I_2P_RI => P2_CSJUDLR(0), + I_SW0_OE => W_SW0_OE, + I_SW1_OE => W_SW1_OE, + I_DIP_OE => W_DIP_OE, + O_D => W_SW_DO + ); + + mc_hv : entity work.MC_HV_COUNT + port map( + I_CLK => W_CLK_6M, + I_RSTn => W_RESETn, + O_H_CNT => W_H_CNT, + O_H_SYNC => W_H_SYNC_int, + O_H_BL => W_H_BL, + O_V_CNT => W_V_CNT, + O_V_SYNC => W_V_SYNC_int, + O_V_BL2n => W_V_BL2n, + O_V_BLn => W_V_BLn, + O_C_BLn => W_C_BLn + ); + + mc_col_pal : entity work.MC_COL_PAL + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_VID => W_VID, + I_COL => W_COL, + I_C_BLnX => W_C_BLnX, + O_C_BLXn => W_C_BLXn, + O_STARS_OFFn => W_STARS_OFFn, + O_R => W_VIDEO_R, + O_G => W_VIDEO_G, + O_B => W_VIDEO_B + ); + + mc_stars : entity work.MC_STARS + port map ( + I_CLK_18M => W_CLK_18M, + I_CLK_6M => W_CLK_6M, + I_H_FLIP => W_H_FLIP, + I_V_SYNC => W_V_SYNC_int, + I_8HF => W_8HF, + I_256HnX => W_256HnX, + I_1VF => W_1VF, + I_2V => W_V_CNT(1), + I_STARS_ON => W_STARS_ON, + I_STARS_OFFn => W_STARS_OFFn, + O_R => W_STARS_R, + O_G => W_STARS_G, + O_B => W_STARS_B, + O_NOISE => open + ); + + mc_sound_a : entity work.MC_SOUND_A + port map( + I_CLK_12M => W_CLK_12M, + I_CLK_6M => W_CLK_6M, + I_H_CNT1 => W_H_CNT(1), + I_BD => W_BDI, + I_PITCH => W_PITCH, + I_VOL1 => W_VOL1, + I_VOL2 => W_VOL2, + O_SDAT => W_SDAT_A, + O_DO => open + ); + + vmc_sound_b : entity work.MC_SOUND_B + port map( + I_CLK1 => W_CLK_6M, + I_RSTn => rst_count(3), + I_SW => new_sw, + I_DAC => W_DAC, + I_FS => W_FS, + O_SDAT => W_SDAT_B + ); + +--------- ROM ------------------------------------------------------- + mc_roms : entity work.ROM_PGM_0 + port map ( + CLK => W_CLK_12M, + ADDR => W_A(13 downto 0), + DATA => W_CPU_ROM_DO + ); + +-------- VIDEO ----------------------------- + blx_comb <= not ( W_C_BLXn and W_V_BL2n ); + W_V_SYNC <= not W_V_SYNC_int; + W_H_SYNC <= not W_H_SYNC_int; + O_CMPBL <= W_C_BLnX; + + -- MISSILE => Yellow ; + -- SHELL => White ; + W_MS_D <= not (W_MISSILEn and W_SHELLn); + W_MS_R <= not blx_comb and W_MS_D; + W_MS_G <= not blx_comb and W_MS_D; + W_MS_B <= not blx_comb and W_MS_D and not W_SHELLn ; + + W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0"); + W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0"); + W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0"); + + process(W_CLK_6M) + begin + if rising_edge(W_CLK_6M) then + HBLANK <= not W_C_BLXn; + VBLANK <= not W_V_BL2n; + end if; + end process; + + +----- CPU I/F ------------------------------------- + + W_CPU_CLK <= W_H_CNT(0); + W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS; + + W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0'); + + W_RESETn <= not I_RESET; + W_BDO <= W_SW_DO or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ; + W_CPU_WR <= not W_CPU_WRn; + + new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE; + + process(W_CPU_CLK, I_RESET) + begin + if (I_RESET = '1') then + rst_count <= (others => '0'); + elsif rising_edge( W_CPU_CLK) then + if ( rst_count /= x"f") then + rst_count <= rst_count + 1; + end if; + end if; + end process; + +----- Parts 9L --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_FS <= (others=>'0'); + W_HIT <= '0'; + W_FIRE <= '0'; + W_VOL1 <= '0'; + W_VOL2 <= '0'; + elsif rising_edge(W_CLK_12M) then + if (W_SOUND_WE = '1') then + case(W_A(2 downto 0)) is + when "000" => W_FS(0) <= W_BDI(0); + when "001" => W_FS(1) <= W_BDI(0); + when "010" => W_FS(2) <= W_BDI(0); + when "011" => W_HIT <= W_BDI(0); +-- when "100" => UNUSED <= W_BDI(0); + when "101" => W_FIRE <= W_BDI(0); + when "110" => W_VOL1 <= W_BDI(0); + when "111" => W_VOL2 <= W_BDI(0); + when others => null; + end case; + end if; + end if; + end process; + +----- Parts 9M --------- + process(W_CLK_12M, I_RESET) + begin + if (I_RESET = '1') then + W_DAC <= (others=>'0'); + elsif rising_edge(W_CLK_12M) then + if (W_DRIVER_WE = '1') then + case(W_A(2 downto 0)) is + -- next 4 outputs go off board via ULN2075 buffer +-- when "000" => 1P START <= W_BDI(0); +-- when "001" => 2P START <= W_BDI(0); +-- when "010" => COIN LOCK <= W_BDI(0); +-- when "011" => COIN CTR <= W_BDI(0); + when "100" => W_DAC(0) <= W_BDI(0); -- 1M + when "101" => W_DAC(1) <= W_BDI(0); -- 470K + when "110" => W_DAC(2) <= W_BDI(0); -- 220K + when "111" => W_DAC(3) <= W_BDI(0); -- 100K + when others => null; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/hq2x.sv b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/keyboard.v b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_adec.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_adec.vhd new file mode 100644 index 00000000..7245ce8c --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_adec.vhd @@ -0,0 +1,251 @@ +--------------------------------------------------------------------- +-- FPGA GALAXIAN ADDRESS DECDER +-- +-- Version : 2.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 4-30 galaxian modify by K.DEGAWA +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. +--------------------------------------------------------------------- +-- +--GALAXIAN Address Map +-- +-- Address Item(R..read-mode W..wight-mode) Parts +--0000 - 1FFF CPU-ROM..R ( 7H or 7K ) +--2000 - 3FFF CPU-ROM..R ( 7L ) +--4000 - 47FF CPU-RAM..RW ( 7N & 7P ) +--5000 - 57FF VID-RAM..RW +--5800 - 5FFF OBJ-RAM..RW +--6000 - SW0..R LAMP......W +--6800 - SW1..R SOUND.....W +--7000 - DIP..R +--7001 NMI_ON....W +--7004 STARS_ON..W +--7006 H_FLIP....W +--7007 V-FLIP....W +--7800 WDR..R PITCH.....W +-- +--W MODE +--6000 1P START +--6001 2P START +--6002 COIN LOCKOUT +--6003 COIN COUNTER +--6004 - 6007 SOUND CONTROL(OSC) +-- +--6800 SOUND CONTROL(FS1) +--6801 SOUND CONTROL(FS2) +--6802 SOUND CONTROL(FS3) +--6803 SOUND CONTROL(HIT) +--6805 SOUND CONTROL(SHOT) +--6806 SOUND CONTROL(VOL1) +--6807 SOUND CONTROL(VOL2) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_ADEC is + port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_CPU_CLK : in std_logic; + I_RSTn : in std_logic; + + I_CPU_A : in std_logic_vector(15 downto 0); + I_CPU_D : in std_logic; + I_MREQn : in std_logic; + I_RFSHn : in std_logic; + I_RDn : in std_logic; + I_WRn : in std_logic; + I_H_BL : in std_logic; + I_V_BLn : in std_logic; + + O_WAITn : out std_logic; + O_NMIn : out std_logic; + O_CPU_ROM_CS : out std_logic; + O_CPU_RAM_RD : out std_logic; + O_CPU_RAM_WR : out std_logic; + O_CPU_RAM_CS : out std_logic; + O_OBJ_RAM_RD : out std_logic; + O_OBJ_RAM_WR : out std_logic; + O_OBJ_RAM_RQ : out std_logic; + O_VID_RAM_RD : out std_logic; + O_VID_RAM_WR : out std_logic; + O_SW0_OE : out std_logic; + O_SW1_OE : out std_logic; + O_DIP_OE : out std_logic; + O_WDR_OE : out std_logic; + O_DRIVER_WE : out std_logic; + O_SOUND_WE : out std_logic; + O_PITCH : out std_logic; + O_H_FLIP : out std_logic; + O_V_FLIP : out std_logic; + O_BD_G : out std_logic; + O_STARS_ON : out std_logic + ); +end; + +architecture RTL of MC_ADEC is + signal W_8E1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8E2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_8P_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_8M_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_9N_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_NMI_ONn : std_logic := '0'; + -------- CPU WAITn ---------------------------------------------- +-- signal W_6S1_Q : std_logic := '0'; + signal W_6S1_Qn : std_logic := '0'; +-- signal W_6S2_Qn : std_logic := '0'; + + signal W_V_BL : std_logic := '0'; + +begin + W_NMI_ONn <= W_9N_Q(1); -- galaxian + +-- O_WAITn <= '1' ; -- No Wait + O_WAITn <= W_6S1_Qn; + + process(I_CPU_CLK, I_V_BLn) + begin + if (I_V_BLn = '0') then +-- W_6S1_Q <= '0'; + W_6S1_Qn <= '1'; + elsif rising_edge(I_CPU_CLK) then +-- W_6S1_Q <= not (I_H_BL or W_8P_Q(2)); + W_6S1_Qn <= I_H_BL or W_8P_Q(2); + end if; + end process; + +-- process(I_CPU_CLK) +-- begin +-- if falling_edge(I_CPU_CLK) then +-- W_6S2_Qn <= not W_6S1_Q; +-- end if; +-- end process; + +-------- CPU NMIn ----------------------------------------------- + W_V_BL <= not I_V_BLn; + process(W_V_BL, W_NMI_ONn) + begin + if (W_NMI_ONn = '0') then + O_NMIn <= '1'; + elsif rising_edge(W_V_BL) then + O_NMIn <= '0'; + end if; + end process; + + ------------------------------------------------------------------- + u_8e1 : entity work.LOGIC_74XX139 + port map ( + I_G => I_MREQn, + I_Sel(1) => I_CPU_A(15), + I_Sel(0) => I_CPU_A(14), + O_Q => W_8E1_Q + ); + + ---------- CPU_ROM CS 0000 - 3FFF --------------------------- + u_8e2 : entity work.LOGIC_74XX139 + port map ( + I_G => I_RDn, + I_Sel(1) => W_8E1_Q(0), + I_Sel(0) => I_CPU_A(13), + O_Q => W_8E2_Q + ); + + O_CPU_ROM_CS <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ; -- 0000 - 3FFF + ------------------------------------------------------------------- + -- ADDRESS + -- W_8E1_Q[0] = 0000 - 3FFF ---- CPU_ROM_USE + -- W_8E1_Q[1] = 4000 - 7FFF ---- GALAXIAN USE *1 + -- W_8E1_Q[2] = 8000 - BFFF ---- MOONCREST USE + -- W_8E1_Q[3] = C000 - FFFF + + u_8p : entity work.LOGIC_74XX138 + port map ( + I_G1 => I_RFSHn, + I_G2a => W_8E1_Q(1), -- <= *1 + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8P_Q + ); + + u_8n : entity work.LOGIC_74XX138 + port map ( + I_G1 => '1', + I_G2a => I_RDn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8N_Q + ); + + u_8m : entity work.LOGIC_74XX138 + port map ( + -- I_G1 => W_6S2_Qn, + I_G1 => '1', -- No Wait + I_G2a => I_WRn, + I_G2b => W_8E1_Q(1), -- <= *1 + I_Sel => I_CPU_A(13 downto 11), + O_Q => W_8M_Q + ); + + O_BD_G <= not (W_8E1_Q(0) and W_8P_Q(0)); + O_OBJ_RAM_RQ <= not W_8P_Q(3); + + O_CPU_RAM_CS <= not (W_8N_Q(0) and W_8M_Q(0)); + + O_WDR_OE <= not W_8N_Q(7); + O_DIP_OE <= not W_8N_Q(6); + O_SW1_OE <= not W_8N_Q(5); + O_SW0_OE <= not W_8N_Q(4); + O_OBJ_RAM_RD <= not W_8N_Q(3); + O_VID_RAM_RD <= not W_8N_Q(2); +-- UNUSED <= not W_8N_Q(1); + O_CPU_RAM_RD <= not W_8N_Q(0); + + O_PITCH <= not W_8M_Q(7); +-- STARS_ON_ENA <= not W_8M_Q(6); + O_SOUND_WE <= not W_8M_Q(5); + O_DRIVER_WE <= not W_8M_Q(4); + O_OBJ_RAM_WR <= not W_8M_Q(3); + O_VID_RAM_WR <= not W_8M_Q(2); +-- UNUSED <= not W_8M_Q(1); + O_CPU_RAM_WR <= not W_8M_Q(0); + + ----- Parts 9N --------- + + process(I_CLK_12M, I_RSTn) + begin + if (I_RSTn = '0') then + W_9N_Q <= (others => '0'); + elsif rising_edge(I_CLK_12M) then + if (W_8M_Q(6) = '0') then + case I_CPU_A(2 downto 0) is + when "000" => W_9N_Q(0) <= I_CPU_D; + when "001" => W_9N_Q(1) <= I_CPU_D; + when "010" => W_9N_Q(2) <= I_CPU_D; + when "011" => W_9N_Q(3) <= I_CPU_D; + when "100" => W_9N_Q(4) <= I_CPU_D; + when "101" => W_9N_Q(5) <= I_CPU_D; + when "110" => W_9N_Q(6) <= I_CPU_D; + when "111" => W_9N_Q(7) <= I_CPU_D; + when others => null; + end case; + end if; + end if; + end process; + + O_STARS_ON <= W_9N_Q(4); + O_H_FLIP <= W_9N_Q(6); + O_V_FLIP <= W_9N_Q(7); + +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_bram.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_bram.vhd new file mode 100644 index 00000000..a6df1ce1 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_bram.vhd @@ -0,0 +1,182 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA & GALAXIAN +-- FPGA BLOCK RAM I/F (XILINX SPARTAN) +-- +-- Version : 2.50 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- mc_col_rom(6L) added by k.Degawa +-- +-- 2004- 5- 6 first release. +-- 2004- 8-23 Improvement with T80-IP. K.Degawa +-- 2004- 9-18 added Xilinx Device K.Degawa +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_top.v use +entity MC_CPU_RAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(9 downto 0); + I_D : in std_logic_vector(7 downto 0); + I_WE : in std_logic; + I_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) + ); +end; +architecture RTL of MC_CPU_RAM is + + signal W_D : std_logic_vector(7 downto 0) := (others => '0'); +begin + O_D <= W_D when I_OE ='1' else (others=>'0'); + + ram_inst : work.spram generic map(10,8) + port map + ( + address => I_ADDR, + clock => I_CLK, + data => I_D, + wren => I_WE, + q => W_D + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_OBJ_RAM is + port( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(7 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(7 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); + end; + +architecture RTL of MC_OBJ_RAM is +begin + + ram_inst : work.dpram generic map(8,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_VID_RAM is + port ( + I_CLKA : in std_logic := '0'; + I_WEA : in std_logic := '0'; + I_CEA : in std_logic := '0'; + I_ADDRA : in std_logic_vector(9 downto 0); + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + + I_CLKB : in std_logic := '0'; + I_WEB : in std_logic := '0'; + I_CEB : in std_logic := '0'; + I_ADDRB : in std_logic_vector(9 downto 0); + I_DB : in std_logic_vector(7 downto 0); + O_DB : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of MC_VID_RAM is +begin + ram_inst : work.dpram generic map(10,8) + port map + ( + clock_a => I_CLKA, + address_a => I_ADDRA, + data_a => I_DA, + q_a => O_DA, + enable_a => I_CEA, + wren_a => I_WEA, + + clock_b => I_CLKB, + address_b => I_ADDRB, + data_b => I_DB, + q_b => O_DB, + enable_b => I_CEB, + wren_b => I_WEB + ); +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +-- mc_video.v use +entity MC_LRAM is + port ( + I_CLK : in std_logic; + I_ADDR : in std_logic_vector(7 downto 0); + I_D : in std_logic_vector(4 downto 0); + I_WE : in std_logic; + O_Dn : out std_logic_vector(4 downto 0) + ); +end; + +architecture RTL of MC_LRAM is + signal W_D : std_logic_vector(4 downto 0) := (others => '0'); +begin + + O_Dn <= not W_D; + + ram_inst : work.dpram generic map(8,5) + port map + ( + clock_a => I_CLK, + address_a => I_ADDR, + data_a => I_D, + wren_a => not I_WE, + + clock_b => not I_CLK, + address_b => I_ADDR, + data_b => (others => '0'), + q_b => W_D, + enable_b => '1', + wren_b => '0' + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_clocks.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_clocks.vhd new file mode 100644 index 00000000..5a4d0094 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_clocks.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA CLOCK GEN +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +----------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity CLOCKGEN is +port ( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + -- + O_CLK_24M : out std_logic; + O_CLK_18M : out std_logic; + O_CLK_12M : out std_logic; + O_CLK_06M : out std_logic +); +end; + +architecture RTL of CLOCKGEN is + signal state : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr1 : std_logic_vector(1 downto 0) := (others => '0'); + signal ctr2 : std_logic_vector(2 downto 0) := (others => '0'); + signal CLKFB_IN : std_logic := '0'; + signal CLK0_BUF : std_logic := '0'; + signal CLKFX_BUF : std_logic := '0'; + signal CLK_72M : std_logic := '0'; + signal I_DCM_LOCKED : std_logic := '0'; + +begin + dcm_inst : DCM_SP + generic map ( + CLKFX_MULTIPLY => 9, + CLKFX_DIVIDE => 4, + CLKIN_PERIOD => 31.25 + ) + port map ( + CLKIN => CLKIN_IN, + CLKFB => CLKFB_IN, + RST => RST_IN, + CLK0 => CLK0_BUF, + CLKFX => CLKFX_BUF, + LOCKED => I_DCM_LOCKED + ); + + BUFG0 : BUFG port map (I=> CLK0_BUF, O => CLKFB_IN); + BUFG1 : BUFG port map (I=> CLKFX_BUF, O => CLK_72M); + O_CLK_06M <= ctr2(2); + O_CLK_12M <= ctr2(1); + O_CLK_24M <= ctr2(0); + O_CLK_18M <= ctr1(1); + + -- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz + process(CLK_72M) + begin + if rising_edge(CLK_72M) then + if (I_DCM_LOCKED = '0') then + state <= "00"; + ctr1 <= (others=>'0'); + ctr2 <= (others=>'0'); + else + ctr1 <= ctr1 + 1; + case state is + when "00" => state <= "01"; ctr2 <= ctr2 + 1; + when "01" => state <= "10"; ctr2 <= ctr2 + 1; + when "10" => state <= "00"; + when "11" => state <= "00"; + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_col_pal.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_col_pal.vhd new file mode 100644 index 00000000..c4dc06ad --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_col_pal.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA COLOR-PALETTE +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-18 added Xilinx Device. K.Degawa +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; +-- use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity MC_COL_PAL is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_VID : in std_logic_vector(1 downto 0); + I_COL : in std_logic_vector(2 downto 0); + I_C_BLnX : in std_logic; + + O_C_BLXn : out std_logic; + O_STARS_OFFn : out std_logic; + O_R : out std_logic_vector(2 downto 0); + O_G : out std_logic_vector(2 downto 0); + O_B : out std_logic_vector(2 downto 0) +); +end; + +architecture RTL of MC_COL_PAL is + --- Parts 6M -------------------------------------------------------- + signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6M_DI : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_DO : std_logic_vector(6 downto 0) := (others => '0'); + signal W_6M_CLR : std_logic := '0'; + +begin + W_6M_DI <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX; + W_6M_CLR <= W_6M_DI(0) or W_6M_DO(0); + O_C_BLXn <= W_6M_DI(0) or W_6M_DO(0); + O_STARS_OFFn <= W_6M_DO(1); + +--always@(posedge I_CLK_6M or negedge W_6M_CLR) + process(I_CLK_6M, W_6M_CLR) + begin + if (W_6M_CLR = '0') then + W_6M_DO <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + W_6M_DO <= W_6M_DI; + end if; + end process; + + --- COL ROM -------------------------------------------------------- +--wire W_COL_ROM_OEn = W_6M_DO[1]; + + galaxian_6l : entity work.GALAXIAN_6L + port map ( + CLK => I_CLK_12M, + ADDR => W_6M_DO(6 downto 2), + DATA => W_COL_ROM_DO + ); + + --- VID OUT -------------------------------------------------------- + O_R <= W_COL_ROM_DO(2 downto 0); + O_G <= W_COL_ROM_DO(5 downto 3); + O_B <= W_COL_ROM_DO(7 downto 6) & "0"; + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_hv_count.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_hv_count.vhd new file mode 100644 index 00000000..f310321b --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_hv_count.vhd @@ -0,0 +1,145 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA H & V COUNTER +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 +----------------------------------------------------------------------- +-- MoonCrest hv_count +-- H_CNT 0 - 255 , 384 - 511 Total 384 count +-- V_CNT 0 - 255 , 504 - 511 Total 264 count +------------------------------------------------------------------------------------------- +-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8], +-- 1 H 2 H 4 H 8 H 16 H 32 H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_HV_COUNT is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + O_H_CNT : out std_logic_vector(8 downto 0); + O_H_SYNC : out std_logic; + O_H_BL : out std_logic; + O_V_BL2n : out std_logic; + O_V_CNT : out std_logic_vector(7 downto 0); + O_V_SYNC : out std_logic; + O_V_BLn : out std_logic; + O_C_BLn : out std_logic + ); +end; + +architecture RTL of MC_HV_COUNT is + signal H_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal V_CNT : std_logic_vector(8 downto 0) := (others => '0'); + signal H_SYNC : std_logic := '0'; + signal H_CLK : std_logic := '0'; + signal H_BL : std_logic := '0'; + signal V_BLn : std_logic := '0'; + signal V_BL2n : std_logic := '0'; + +begin +--------- H_COUNT ---------------------------------------- + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if (H_CNT = 255) then + H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length)); + else + H_CNT <= H_CNT + 1 ; + end if; + end if; + end process; + + O_H_CNT <= H_CNT; + +--------- H_SYNC ---------------------------------------- + H_CLK <= H_CNT(4); + process(H_CLK, H_CNT(8)) + begin + if (H_CNT(8) = '0') then + H_SYNC <= '0'; + elsif rising_edge(H_CLK) then + H_SYNC <= (not H_CNT(6) ) and H_CNT(5); + end if; + end process; + + O_H_SYNC <= H_SYNC; + +--------- H_BL ------------------------------------------ + + process(I_CLK) + begin + if rising_edge(I_CLK) then + if H_CNT = 387 then + H_BL <= '1'; + elsif H_CNT = 503 then + H_BL <= '0'; + end if; + end if; + end process; + + O_H_BL <= H_BL; + +--------- V_COUNT ---------------------------------------- + process(H_SYNC, I_RSTn) + begin + if (I_RSTn = '0') then + V_CNT <= (others => '0'); + elsif rising_edge(H_SYNC) then + if (V_CNT = 255) then + V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length)); + else + V_CNT <= V_CNT + 1 ; + end if; + end if; + end process; + + O_V_CNT <= V_CNT(7 downto 0); + O_V_SYNC <= V_CNT(8); + +--------- V_BLn ------------------------------------------ + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BLn <= '0'; + elsif V_CNT(7 downto 0) = 15 then + V_BLn <= '1'; + end if; + end if; + end process; + + process(H_SYNC) + begin + if rising_edge(H_SYNC) then + if V_CNT(7 downto 0) = 239 then + V_BL2n <= '0'; + elsif V_CNT(7 downto 0) = 16 then + V_BL2n <= '1'; + end if; + end if; + end process; + + O_V_BLn <= V_BLn; + O_V_BL2n <= V_BL2n; +------- C_BLn ------------------------------------------ + O_C_BLn <= V_BLn and (not H_CNT(8)); + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_inport.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_inport.vhd new file mode 100644 index 00000000..25250c11 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_inport.vhd @@ -0,0 +1,85 @@ +----------------------------------------------------------------------- +-- FPGA MOONCRESTA INPORT +-- +-- Version : 1.01 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004-4-30 galaxian modify by K.DEGAWA +----------------------------------------------------------------------- + +-- DIP SW 0 1 2 3 4 5 +----------------------------------------------------------------- +-- COIN CHUTE +-- 1 COIN/1 PLAY 1'b0 1'b0 +-- 2 COIN/1 PLAY 1'b1 1'b0 +-- 1 COIN/2 PLAY 1'b0 1'b1 +-- FREE PLAY 1'b1 1'b1 +-- BOUNS +-- 1'b0 1'b0 +-- 1'b1 1'b0 +-- 1'b0 1'b1 +-- 1'b1 1'b1 +-- LIVES +-- 2 1'b0 +-- 3 1'b1 +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_INPORT is +port ( + I_COIN1 : in std_logic; -- active high + I_COIN2 : in std_logic; -- active high + I_1P_LE : in std_logic; -- active high + I_1P_RI : in std_logic; -- active high + I_1P_SH : in std_logic; -- active high + I_1P_UP : in std_logic; -- active high + I_1P_DW : in std_logic; -- active high + + I_2P_LE : in std_logic; + I_2P_RI : in std_logic; + I_2P_SH : in std_logic; + I_2P_UP : in std_logic; -- active high + I_2P_DW : in std_logic; -- active high + I_1P_START : in std_logic; -- active high + I_2P_START : in std_logic; -- active high + I_SW0_OE : in std_logic; + I_SW1_OE : in std_logic; + I_DIP_OE : in std_logic; + O_D : out std_logic_vector(7 downto 0) +); + +end; + +architecture RTL of MC_INPORT is + + constant W_TABLE : std_logic := '0'; -- UP = 0; + constant W_TEST : std_logic := '0'; + constant W_SERVICE : std_logic := '0'; + + signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0'); + signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1; + W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01" & I_2P_DW & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; + W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; + O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + +-- W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST & W_TABLE & I_1P_SH & I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1; +-- W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010" & I_2P_SH & I_2P_RI & I_2P_LE & I_2P_START & I_1P_START; +-- W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010"; +-- O_D <= W_SW0_DO or W_SW1_DO or W_DIP_DO ; + + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_ld_pls.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_ld_pls.vhd new file mode 100644 index 00000000..0945fe35 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_ld_pls.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_LD_PLS is + port ( + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_3D_DI : in std_logic; + + O_LDn : out std_logic; + O_CNTRLDn : out std_logic; + O_CNTRCLRn : out std_logic; + O_COLLn : out std_logic; + O_VPLn : out std_logic; + O_OBJDATALn : out std_logic; + O_MLDn : out std_logic; + O_SLDn : out std_logic + ); +end; + +architecture RTL of MC_LD_PLS is + signal W_4C1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4C1_Q3 : std_logic := '0'; + signal W_4C2_B : std_logic := '0'; + signal W_4D1_G : std_logic := '0'; + signal W_4D1_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_4D2_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_5C_Q : std_logic := '0'; + signal W_HCNT : std_logic := '0'; +begin + O_LDn <= W_4D1_G; + O_CNTRLDn <= W_4D1_Q(2); + O_CNTRCLRn <= W_4D1_Q(0); + O_COLLn <= W_4D2_Q(2); + O_VPLn <= W_4D2_Q(0); + O_OBJDATALn <= W_4C1_Q(2); + O_MLDn <= W_4C2_Q(0); + O_SLDn <= W_4C2_Q(1); + W_4D1_G <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2)); + W_HCNT <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3)); + -- Parts 4D + u_4d1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_G, + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q =>W_4D1_Q + ); + + u_4d2 : entity work.LOGIC_74XX139 + port map( + I_G => W_5C_Q, + I_Sel(1) => I_H_CNT(2), + I_Sel(0) => I_H_CNT(1), + O_Q => W_4D2_Q + ); + + -- Parts 4C + u_4c1 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D2_Q(1), + I_Sel(1) => I_H_CNT(8), + I_Sel(0) => I_H_CNT(3), + O_Q => W_4C1_Q + ); + + u_4c2 : entity work.LOGIC_74XX139 + port map( + I_G => W_4D1_Q(3), + I_Sel(1) => W_4C2_B, + I_Sel(0) => W_HCNT, + O_Q => W_4C2_Q + ); + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_5C_Q <= I_H_CNT(0); + end if; + end process; + + -- 2004-9-22 added + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + W_4C1_Q3 <= W_4C1_Q(3); + end if; + end process; + + process(W_4C1_Q3) + begin + if rising_edge(W_4C1_Q3) then + W_4C2_B <= I_3D_DI; + end if; + end process; + +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_logic.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_logic.vhd new file mode 100644 index 00000000..5dae8a87 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_logic.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- FPGA MOONCRESTA LOGIC IP MODULE +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx138 +-- 3-to-8 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX138 is + port ( + I_G1 : in std_logic; + I_G2a : in std_logic; + I_G2b : in std_logic; + I_Sel : in std_logic_vector(2 downto 0); + O_Q : out std_logic_vector(7 downto 0) + ); +end logic_74xx138; + +architecture RTL of LOGIC_74XX138 is + signal I_G : std_logic_vector(2 downto 0) := (others => '0'); + +begin + I_G <= I_G1 & I_G2a & I_G2b; + + xx138 : process(I_G, I_Sel) + begin + if(I_G = "100" ) then + case I_Sel is + when "000" => O_Q <= "11111110"; + when "001" => O_Q <= "11111101"; + when "010" => O_Q <= "11111011"; + when "011" => O_Q <= "11110111"; + when "100" => O_Q <= "11101111"; + when "101" => O_Q <= "11011111"; + when "110" => O_Q <= "10111111"; + when "111" => O_Q <= "01111111"; + when others => null; + end case; + else + O_Q <= (others => '1'); + end if; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +------------------------------------------------------------------------------- +-- 74xx139 +-- 2-to-4 line decoder +------------------------------------------------------------------------------- +entity LOGIC_74XX139 is + port ( + I_G : in std_logic; + I_Sel : in std_logic_vector(1 downto 0); + O_Q : out std_logic_vector(3 downto 0) + ); +end; + +architecture RTL of LOGIC_74XX139 is +begin + xx139 : process (I_G, I_Sel) + begin + if I_G = '0' then + case I_Sel is + when "00" => O_Q <= "1110"; + when "01" => O_Q <= "1101"; + when "10" => O_Q <= "1011"; + when "11" => O_Q <= "0111"; + when others => null; + end case; + else + O_Q <= "1111"; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_missile.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_missile.vhd new file mode 100644 index 00000000..c5aa6633 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_missile.vhd @@ -0,0 +1,107 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA VIDEO-MISSILE +---- +---- Version : 2.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 9-22 The problem which missile didn't sometimes come out from was improved. +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_MISSILE is + port( + I_CLK_6M : in std_logic; + I_CLK_18M : in std_logic; + I_C_BLn_X : in std_logic; + I_MLDn : in std_logic; + I_SLDn : in std_logic; + I_HPOS : in std_logic_vector (7 downto 0); + + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic + ); +end; + +architecture RTL of MC_MISSILE is + signal W_45R_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_45S_Q : std_logic_vector (7 downto 0) := (others => '0'); + signal W_5P1_Q : std_logic := '0'; + signal W_5P2_Q : std_logic := '0'; + signal W_5P1_CLK : std_logic := '0'; + signal W_5P2_CLK : std_logic := '0'; +begin + + O_MISSILEn <= W_5P1_CLK; + O_SHELLn <= W_5P2_CLK; + + -- missile counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if (I_MLDn = '0') then + W_45R_Q <= I_HPOS; + else + if (I_C_BLn_X = '1') then + W_45R_Q <= W_45R_Q + 1; + if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then + W_5P1_CLK <= '0'; + else + W_5P1_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- shell counter + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + if(I_SLDn = '0') then + W_45S_Q <= I_HPOS; + else + if(I_C_BLn_X = '1') then + W_45S_Q <= W_45S_Q + 1; + if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then + W_5P2_CLK <= '0'; + else + W_5P2_CLK <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK) + process(W_5P1_CLK, I_MLDn) + begin + if (I_MLDn = '0') then + W_5P1_Q <= '1'; + elsif rising_edge(W_5P1_CLK) then + W_5P1_Q <= '0'; + end if; + end process; + + -- Standard D-type flip-flop with D input tied low, async active + -- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK) + process(W_5P2_CLK, I_SLDn) + begin + if (I_SLDn = '0') then + W_5P2_Q <= '1'; + elsif rising_edge(W_5P2_CLK) then + W_5P2_Q <= '0'; + end if; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_a.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_a.vhd new file mode 100644 index 00000000..ee0c66be --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_a.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA SOUND I/F +-- +-- Version : 1.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + use IEEE.std_logic_arith.all; + +entity MC_SOUND_A is +port ( + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT1 : in std_logic; + I_BD : in std_logic_vector(7 downto 0); + I_PITCH : in std_logic; + I_VOL1 : in std_logic; + I_VOL2 : in std_logic; + + O_SDAT : out std_logic_vector(7 downto 0); + O_DO : out std_logic_vector(3 downto 0) +); +end; + +architecture RTL of MC_SOUND_A is + signal W_PITCH : std_logic := '0'; + signal W_89K_LDn : std_logic := '0'; + signal W_89K_Q : std_logic_vector(7 downto 0) := (others => '0'); + signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0'); + signal W_6T_Q : std_logic_vector(3 downto 0) := (others => '0'); + signal W_SDAT0 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT2 : std_logic_vector(7 downto 0) := (others => '0'); + signal W_SDAT3 : std_logic_vector(7 downto 0) := (others => '0'); + +begin + O_DO <= W_6T_Q; + + process (I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_PITCH <= I_PITCH; + if (W_89K_Q = x"ff") then + W_89K_LDn <= '0' ; + else + W_89K_LDn <= '1' ; + end if; + end if; + end process; + + -- Parts 9J + process (W_PITCH) + begin + if falling_edge(W_PITCH) then + W_89K_LDATA <= I_BD; + end if; + end process; + + process (I_H_CNT1) + begin + if rising_edge(I_H_CNT1) then + if (W_89K_LDn = '0') then + W_89K_Q <= W_89K_LDATA; + else + W_89K_Q <= W_89K_Q + 1; + end if; + end if; + end process; + + process (W_89K_LDn) + begin + if falling_edge(W_89K_LDn) then + W_6T_Q <= W_6T_Q + 1; + end if; + end process; + + process (I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2); + + if W_6T_Q(0)='1' then + W_SDAT0 <= x"2a"; + else + W_SDAT0 <= (others => '0'); + end if; + + if W_6T_Q(2)='1' then + if I_VOL1 = '1' then + W_SDAT2 <= x"69"; + else + W_SDAT2 <= x"39"; + end if; + else + W_SDAT2 <= (others => '0'); + end if; + + if (W_6T_Q(3)='1') and (I_VOL2 = '1') then + W_SDAT3 <= x"48" ; + else + W_SDAT3 <= (others => '0'); + end if; + + end if; + end process; + +end; \ No newline at end of file diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_b.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_b.vhd new file mode 100644 index 00000000..b74e4bb1 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_b.vhd @@ -0,0 +1,253 @@ +-------------------------------------------------------------------------------- +---- FPGA MOONCRESTA WAVE SOUND +---- +---- Version : 1.00 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does no guarantee this program. +---- You can use this at your own risk. +---- +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--pragma translate_off +-- use ieee.std_logic_textio.all; +-- use std.textio.all; +--pragma translate_on + +entity MC_SOUND_B is + port( + I_CLK1 : in std_logic; -- 6MHz + I_RSTn : in std_logic; + I_SW : in std_logic_vector( 2 downto 0); + I_DAC : in std_logic_vector( 3 downto 0); + I_FS : in std_logic_vector( 2 downto 0); + O_SDAT : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_B is +constant sample_time : integer := 557; -- sample time : 557 = 11025Hz, 557/2 = 22050Hz +constant fire_cnt : std_logic_vector(15 downto 0) := x"2000"; +constant hit_cnt : std_logic_vector(15 downto 0) := x"2000"; + +signal sample : std_logic_vector(10 downto 0) := (others => '0'); +signal sample_pls : std_logic := '0'; +signal s0_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s0_trg : std_logic := '0'; +signal s1_trg_ff : std_logic_vector( 1 downto 0) := (others => '0'); +signal s1_trg : std_logic := '0'; +signal fire_addr : std_logic_vector(15 downto 0) := (others => '0'); +signal hit_addr : std_logic_vector(15 downto 0) := (others => '0'); + +signal WAV_D0 : std_logic_vector( 7 downto 0) := (others => '0'); +signal WAV_D1 : std_logic_vector( 7 downto 0) := (others => '0'); + +signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0'); +signal VCO_CTR : std_logic_vector(24 downto 0) := (others => '0'); + +signal SDAT : std_logic_vector(10 downto 0) := (others => '0'); + +begin + -- ideally we should divide by 5 because this is the sum of 5 channels + -- but in practice we divide by 4 and just clip sounds that are too loud. + O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds + + process(I_CLK1) + begin + if rising_edge(I_CLK1) then + SDAT <= ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) ); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + sample <= (others => '0'); + sample_pls <= '0'; + elsif rising_edge(I_CLK1) then + if (sample = sample_time - 1) then + sample <= (others => '0'); + sample_pls <= '1'; + else + sample <= sample + 1; + sample_pls <= '0'; + end if; + end if; + end process; + +------------- FIRE SOUND ------------------------------------------ + mc_roms_fire : entity work.GAL_FIR + port map ( + CLK => I_CLK1, + ADDR => fire_addr(12 downto 0), + DATA => WAV_D0 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s0_trg_ff <= (others => '0'); + s0_trg <= '0'; + elsif rising_edge(I_CLK1) then + s0_trg_ff(0) <= I_SW(0); + s0_trg_ff(1) <= s0_trg_ff(0); + s0_trg <= not s0_trg_ff(1) and s0_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + fire_addr <= fire_cnt; + elsif rising_edge(I_CLK1) then + if (s0_trg = '1') then + fire_addr <= (others => '0'); + else + if(sample_pls = '1') then + if(fire_addr <= fire_cnt) then + fire_addr <= fire_addr + 1; + else + fire_addr <= fire_addr ; + end if; + end if; + end if; + end if; + end process; + +------------- HIT SOUND ------------------------------------------ + mc_roms_hit : entity work.GAL_HIT + port map ( + CLK => I_CLK1, + ADDR => hit_addr(12 downto 0), + DATA => WAV_D1 + ); + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + s1_trg_ff <= (others => '0'); + s1_trg <= '0'; + elsif rising_edge(I_CLK1) then + s1_trg_ff(0) <= I_SW(1); + s1_trg_ff(1) <= s1_trg_ff(0); + s1_trg <= not s1_trg_ff(1) and s1_trg_ff(0); + end if; + end process; + + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + hit_addr <= hit_cnt; + elsif rising_edge(I_CLK1) then + if (s1_trg = '1') then + hit_addr <= (others => '0'); + else + if (sample_pls = '1') then + if (hit_addr <= hit_cnt) then + hit_addr <= hit_addr + 1 ; + else + hit_addr <= hit_addr ; + end if; + end if; + end if; + end if; + end process; + +--------------- EFFECT SOUND --------------------------------------- + +-- 9R modulator voltage generator based on DAC value + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + VCO_CTR <= (others=>'0'); + elsif rising_edge(I_CLK1) then + VCO_CTR <= VCO_CTR + (not I_DAC); + end if; + end process; + + -- modulator frequency lookup tables for the three VCOs + process(I_CLK1, I_RSTn) + begin + if (I_RSTn = '0') then + elsif rising_edge(I_CLK1) then + case VCO_CTR(23 downto 19) is + when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54"; + when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; + when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52"; + when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50"; + when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F"; + when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E"; + when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D"; + when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C"; + when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A"; + when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49"; + when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48"; + when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47"; + when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46"; + when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44"; + when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43"; + when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42"; + when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41"; + when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; + when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F"; + when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D"; + when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C"; + when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B"; + when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A"; + when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39"; + when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37"; + when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36"; + when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35"; + when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34"; + when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33"; + when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32"; + when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30"; + when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F"; + when others => null; + end case; + end if; + end process; + +-- 8R VCO 240Hz - 140Hz (8) + mc_vco1 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(0), + I_STEP => W_VCO1_STEP, + O_WAV => W_VCO1_OUT + ); + +-- 8S VCO 330Hz - 190Hz (11) + mc_vco2 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(1), + I_STEP => W_VCO2_STEP, + O_WAV => W_VCO2_OUT + ); + +-- 8T VCO 480Hz - 270Hz (16) + mc_vco3 : entity work.MC_SOUND_VCO + port map ( + I_CLK => I_CLK1, + I_RSTn => I_RSTn, + I_FS => I_FS(2), + I_STEP => W_VCO3_STEP, + O_WAV => W_VCO3_OUT + ); +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_vco.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_vco.vhd new file mode 100644 index 00000000..e2a63e85 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_sound_vco.vhd @@ -0,0 +1,49 @@ +-------------------------------------------------------------------------------- +---- FPGA VCO +-------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +use work.sine_package.all; + +-- O_CLK = (I_CLK / 2^20) * I_STEP +entity MC_SOUND_VCO is + port( + I_CLK : in std_logic; + I_RSTn : in std_logic; + I_FS : in std_logic; + I_STEP : in std_logic_vector( 7 downto 0); + O_WAV : out std_logic_vector( 7 downto 0) + ); +end; + +architecture RTL of MC_SOUND_VCO is + signal VCO1_CTR : std_logic_vector(19 downto 0) := (others => '0'); + signal sine : std_logic_vector(14 downto 0) := (others => '0'); + +begin + O_WAV <= sine(14 downto 7); + process(I_CLK, I_RSTn) + begin + if (I_RSTn = '0') then + VCO1_CTR <= (others=>'0'); + elsif rising_edge(I_CLK) then + if I_FS = '1' then + VCO1_CTR <= VCO1_CTR + I_STEP; + case VCO1_CTR(19 downto 18) is + when "00" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "01" => + sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when "10" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( VCO1_CTR(17 downto 11)), 15)); + when "11" => + sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15)); + when others => null; + end case; + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_stars.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_stars.vhd new file mode 100644 index 00000000..b91197b3 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_stars.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------ +-- FPGA MOONCRESTA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK_18M : in std_logic; + I_CLK_6M : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0'); + + CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(CLK_1C, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(CLK_1C) then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end process; + + process(CLK_1AB, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(CLK_1AB) then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end process; +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_video.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_video.vhd new file mode 100644 index 00000000..9642043d --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mc_video.vhd @@ -0,0 +1,436 @@ +-------------------------------------------------------------------------------- +---- FPGA GALAXIAN VIDEO +---- +---- Version : 2.50 +---- +---- Copyright(c) 2004 Katsumi Degawa , All rights reserved +---- +---- Important ! +---- +---- This program is freeware for non-commercial use. +---- The author does not guarantee this program. +---- You can use this at your own risk. +---- +---- 2004- 4-30 galaxian modify by K.DEGAWA +---- 2004- 5- 6 first release. +---- 2004- 8-23 Improvement with T80-IP. +---- 2004- 9-22 The problem where missile sometimes didn't come out was fixed. +-------------------------------------------------------------------------------- + +------------------------------------------------------------------------------------------- +-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8), +-- 1 H 2 H 4 H 8 H 16 H 32H 64 H 128 H 256 H +------------------------------------------------------------------------------------------- +-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7) +-- 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V +------------------------------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity MC_VIDEO is + port( + I_CLK_18M : in std_logic; + I_CLK_12M : in std_logic; + I_CLK_6M : in std_logic; + I_H_CNT : in std_logic_vector(8 downto 0); + I_V_CNT : in std_logic_vector(7 downto 0); + I_H_FLIP : in std_logic; + I_V_FLIP : in std_logic; + I_V_BLn : in std_logic; + I_C_BLn : in std_logic; + + I_A : in std_logic_vector(9 downto 0); + I_BD : in std_logic_vector(7 downto 0); + I_OBJ_SUB_A : in std_logic_vector(2 downto 0); + I_OBJ_RAM_RQ : in std_logic; + I_OBJ_RAM_RD : in std_logic; + I_OBJ_RAM_WR : in std_logic; + I_VID_RAM_RD : in std_logic; + I_VID_RAM_WR : in std_logic; + I_DRIVER_WR : in std_logic; + + + O_C_BLnX : out std_logic; + O_8HF : out std_logic; + O_256HnX : out std_logic; + O_1VF : out std_logic; + O_MISSILEn : out std_logic; + O_SHELLn : out std_logic; + + O_BD : out std_logic_vector(7 downto 0); + O_VID : out std_logic_vector(1 downto 0); + O_COL : out std_logic_vector(2 downto 0) + ); +end; + +architecture RTL of MC_VIDEO is + + signal WB_LDn : std_logic := '0'; + signal WB_CNTRLDn : std_logic := '0'; + signal WB_CNTRCLRn : std_logic := '0'; + signal WB_COLLn : std_logic := '0'; + signal WB_VPLn : std_logic := '0'; + signal WB_OBJDATALn : std_logic := '0'; + signal WB_MLDn : std_logic := '0'; + signal WB_SLDn : std_logic := '0'; + signal W_3D : std_logic := '0'; + signal W_LDn : std_logic := '0'; + signal W_CNTRLDn : std_logic := '0'; + signal W_CNTRCLRn : std_logic := '0'; + signal W_COLLn : std_logic := '0'; + signal W_VPLn : std_logic := '0'; + signal W_OBJDATALn : std_logic := '0'; + signal W_MLDn : std_logic := '0'; + signal W_SLDn : std_logic := '0'; + signal W_VID : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_COL : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_H_POSI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_2M_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6K_Q : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_6P_Q : std_logic_vector( 6 downto 0) := (others => '0'); + signal W_45T_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2KL : std_logic_vector( 7 downto 0) := (others => '0'); + signal reg_2HJ : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_RV : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_RC : std_logic_vector( 2 downto 0) := (others => '0'); + + signal W_O_OBJ_ROM_A : std_logic_vector(10 downto 0) := (others => '0'); + signal W_VID_RAM_A : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AA : std_logic_vector(11 downto 0) := (others => '0'); + signal W_VID_RAM_AB : std_logic_vector(11 downto 0) := (others => '0'); + signal C_2HJ : std_logic_vector( 1 downto 0) := (others => '0'); + signal C_2KL : std_logic_vector( 1 downto 0) := (others => '0'); + signal W_CD : std_logic_vector( 2 downto 0) := (others => '0'); + signal W_1M : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_A : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_B : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_3L_Y : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_LRAM_DI : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_LRAM_DO : std_logic_vector( 4 downto 0) := (others => '0'); + signal W_1H_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_1K_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_LRAM_A : std_logic_vector( 7 downto 0) := (others => '0'); +-- signal W_OBJ_RAM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_A : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_OBJ_ROM_AB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_D : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DI : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOA : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_VID_RAM_DOB : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_HF_CNT : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_45N_Q : std_logic_vector( 7 downto 0) := (others => '0'); + signal W_6J_Q : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DA : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_6J_DB : std_logic_vector( 3 downto 0) := (others => '0'); + signal W_256HnX : std_logic := '0'; + signal W_2N : std_logic := '0'; + signal W_45T_CLR : std_logic := '0'; + signal W_C_BLnX : std_logic := '0'; + signal W_H_FLIP1 : std_logic := '0'; + signal W_H_FLIP2 : std_logic := '0'; + signal W_H_FLIP1X : std_logic := '0'; + signal W_H_FLIP2X : std_logic := '0'; + signal W_LRAM_AND : std_logic := '0'; + signal W_RAW0 : std_logic := '0'; + signal W_RAW1 : std_logic := '0'; + signal W_RAW_OR : std_logic := '0'; + signal W_SRCLK : std_logic := '0'; + signal W_SRLD : std_logic := '0'; + signal W_VID_RAM_CS : std_logic := '0'; + signal W_CLK_6Mn : std_logic := '0'; + +begin + + ld_pls : entity work.MC_LD_PLS + port map( + I_CLK_6M => I_CLK_6M, + I_H_CNT => I_H_CNT, + I_3D_DI => W_3D, + + O_LDn => WB_LDn, + O_CNTRLDn => WB_CNTRLDn, + O_CNTRCLRn => WB_CNTRCLRn, + O_COLLn => WB_COLLn, + O_VPLn => WB_VPLn, + O_OBJDATALn => WB_OBJDATALn, + O_MLDn => WB_MLDn, + O_SLDn => WB_SLDn + ); + + obj_ram : entity work.MC_OBJ_RAM + port map( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(7 downto 0), + I_WEA => I_OBJ_RAM_WR, + I_CEA => I_OBJ_RAM_RQ, + I_DA => I_BD, + O_DA => W_OBJ_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_OBJ_RAM_AB, + I_WEB => '0', + I_CEB => '1', + I_DB => x"00", + O_DB => W_OBJ_RAM_DOB + ); + + lram : entity work.MC_LRAM + port map( + I_CLK => I_CLK_18M, + I_ADDR => W_LRAM_A, + I_WE => W_CLK_6Mn, + I_D => W_LRAM_DI, + O_Dn => W_LRAM_DO + ); + + missile : entity work.MC_MISSILE + port map( + I_CLK_18M => I_CLK_18M, + I_CLK_6M => I_CLK_6M, + I_C_BLn_X => W_C_BLnX, + I_MLDn => W_MLDn, + I_SLDn => W_SLDn, + I_HPOS => W_H_POSI, + O_MISSILEn => O_MISSILEn, + O_SHELLn => O_SHELLn + ); + + vid_ram : entity work.MC_VID_RAM + port map ( + I_CLKA => I_CLK_12M, + I_ADDRA => I_A(9 downto 0), + I_DA => W_VID_RAM_DI, + I_WEA => I_VID_RAM_WR, + I_CEA => W_VID_RAM_CS, + O_DA => W_VID_RAM_DOA, + + I_CLKB => I_CLK_12M, + I_ADDRB => W_VID_RAM_A(9 downto 0), + I_DB => x"00", + I_WEB => '0', + I_CEB => '1', + O_DB => W_VID_RAM_DOB + ); + + -- 1H VID-Rom + k_rom : entity work.GALAXIAN_1H + port map ( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1H_D + ); + + -- 1K VID-Rom + h_rom : entity work.GALAXIAN_1K + port map( + CLK => I_CLK_12M, + ADDR => W_O_OBJ_ROM_A, + DATA => W_1K_D + ); + + +----------------------------------------------------------------------------------- + + process(I_CLK_12M) + begin + if falling_edge(I_CLK_12M) then + W_LDn <= WB_LDn; + W_CNTRLDn <= WB_CNTRLDn; + W_CNTRCLRn <= WB_CNTRCLRn; + W_COLLn <= WB_COLLn; + W_VPLn <= WB_VPLn; + W_OBJDATALn <= WB_OBJDATALn; + W_MLDn <= WB_MLDn; + W_SLDn <= WB_SLDn; + end if; + end process; + + W_CLK_6Mn <= not I_CLK_6M; + + W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2); + W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1); + W_6J_Q <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA; + + W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP; + + W_HF_CNT(7 downto 3) <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3); + W_VF_CNT <= not I_V_CNT when I_V_FLIP = '1' else I_V_CNT; + + O_8HF <= W_HF_CNT(3); + O_1VF <= W_VF_CNT(0); + W_H_FLIP2 <= W_6J_Q(3); + +-- Parts 4F,5F + W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0); +-- W_OBJ_RAM_A <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ; + + process(I_CLK_12M) + begin + if rising_edge(I_CLK_12M) then + W_H_POSI <= W_OBJ_RAM_DOB; + end if; + end process; + + W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0'); + +-- Parts 4L + process(W_OBJDATALn) + begin + if rising_edge(W_OBJDATALn) then + W_OBJ_D <= W_H_POSI; + end if; + end process; + +-- Parts 4,5N + W_45N_Q <= W_VF_CNT + W_H_POSI; + W_3D <= '0' when W_45N_Q = x"FF" else '1'; + + process(W_VPLn, I_V_BLn) + begin + if (I_V_BLn = '0') then + W_2M_Q <= (others => '0'); + elsif rising_edge(W_VPLn) then + W_2M_Q <= W_45N_Q; + end if; + end process; + + W_2N <= I_H_CNT(8) and W_OBJ_D(7); + W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N); + W_VID_RAM_CS <= I_VID_RAM_RD or I_VID_RAM_WR; + W_VID_RAM_DI <= I_BD when I_VID_RAM_WR = '1' else (others => '0'); + W_VID_RAM_AA <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0) + W_VID_RAM_AB <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3); + W_VID_RAM_A <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA; + W_VID_RAM_D <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0'); + +---- VIDEO DATA OUTPUT -------------- + + O_BD <= W_OBJ_RAM_D or W_VID_RAM_D; + W_SRLD <= not (W_LDn or W_VID_RAM_A(11)); + W_OBJ_ROM_AB <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3)); + W_OBJ_ROM_A <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB; + W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0); + +----------------------------------------------------------------------------------- + + W_3L_A <= reg_2HJ(7) & reg_2KL(7) & "1" & W_SRLD; + W_3L_B <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1"; + W_3L_Y <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A; -- (3)=RAW1,(2)=RAW0 + C_2HJ <= W_3L_Y(1 downto 0); + C_2KL <= W_3L_Y(1 downto 0); + W_RAW0 <= W_3L_Y(2); + W_RAW1 <= W_3L_Y(3); + W_SRCLK <= I_CLK_6M; + +-------- PARTS 2KL ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2KL) is + when "00" => reg_2KL <= reg_2KL; + when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0"; + when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1); + when "11" => reg_2KL <= W_1K_D; + when others => null; + end case; + end if; + end process; + +-------- PARTS 2HJ ---------------------------------------------- + + process(W_SRCLK) + begin + if rising_edge(W_SRCLK) then + case(C_2HJ) is + when "00" => reg_2HJ <= reg_2HJ; + when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0"; + when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1); + when "11" => reg_2HJ <= W_1H_D; + when others => null; + end case; + end if; + end process; + +------- SHT2 ----------------------------------------------------- + +-- Parts 6K + process(W_COLLn) + begin + if rising_edge(W_COLLn) then + W_6K_Q <= W_H_POSI(2 downto 0); + end if; + end process; + +-- Parts 6P + process(I_CLK_6M) + begin + if rising_edge(I_CLK_6M) then + if (W_LDn = '0') then + W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0); + else + W_6P_Q <= W_6P_Q; + end if; + end if; + end process; + + W_H_FLIP2X <= W_6P_Q(6); + W_H_FLIP1X <= W_6P_Q(5); + W_C_BLnX <= W_6P_Q(4); + W_256HnX <= W_6P_Q(3); + W_CD <= W_6P_Q(2 downto 0); + O_256HnX <= W_256HnX; + O_C_BLnX <= W_C_BLnX; + W_45T_CLR <= W_CNTRCLRn or W_256HnX ; + + process(I_CLK_6M, W_45T_CLR) + begin + if (W_45T_CLR = '0') then + W_45T_Q <= (others => '0'); + elsif rising_edge(I_CLK_6M) then + if (W_CNTRLDn = '0') then + W_45T_Q <= W_H_POSI; + else + W_45T_Q <= W_45T_Q + 1; + end if; + end if; + end process; + + W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q; + + process(I_CLK_6M) + begin + if falling_edge(I_CLK_6M) then + W_RV <= W_LRAM_DO(1 downto 0); + W_RC <= W_LRAM_DO(4 downto 2); + end if; + end process; + + W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX ); + W_RAW_OR <= W_RAW0 or W_RAW1 ; + + W_VID(0) <= not (not (W_RAW0 and W_RV(1)) and W_RV(0)); + W_VID(1) <= not (not (W_RAW1 and W_RV(0)) and W_RV(1)); + W_COL(0) <= not (not (W_RAW_OR and W_CD(0) and W_RC(1) and W_RC(2)) and W_RC(0)); + W_COL(1) <= not (not (W_RAW_OR and W_CD(1) and W_RC(2) and W_RC(0)) and W_RC(1)); + W_COL(2) <= not (not (W_RAW_OR and W_CD(2) and W_RC(0) and W_RC(1)) and W_RC(2)); + + O_VID <= W_VID; + O_COL <= W_COL; + + W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0); + W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); + W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0); + W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1); + W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2); + +end RTL; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mist_io.v b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/osd.v b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/pll.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/pll.vhd new file mode 100644 index 00000000..d76a5e1d --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/pll.vhd @@ -0,0 +1,451 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 3, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 9, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 2, + clk2_phase_shift => "0", + clk3_divide_by => 6, + clk3_duty_cycle => 50, + clk3_multiply_by => 1, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "6" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "18.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "4.500000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "18.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "4.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/scandoubler.v b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/sine_package.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/sine_package.vhd new file mode 100644 index 00000000..473caa04 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/sine_package.vhd @@ -0,0 +1,152 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sine_package is + + subtype table_value_type is integer range 0 to 16383; + subtype table_index_type is std_logic_vector( 6 downto 0 ); + + function get_table_value (table_index: table_index_type) return table_value_type; + +end; + +package body sine_package is + + function get_table_value (table_index: table_index_type) return table_value_type is + variable table_value: table_value_type; + begin + case table_index is + when "0000000" => table_value := 101; + when "0000001" => table_value := 302; + when "0000010" => table_value := 503; + when "0000011" => table_value := 703; + when "0000100" => table_value := 904; + when "0000101" => table_value := 1105; + when "0000110" => table_value := 1305; + when "0000111" => table_value := 1506; + when "0001000" => table_value := 1706; + when "0001001" => table_value := 1906; + when "0001010" => table_value := 2105; + when "0001011" => table_value := 2304; + when "0001100" => table_value := 2503; + when "0001101" => table_value := 2702; + when "0001110" => table_value := 2900; + when "0001111" => table_value := 3098; + when "0010000" => table_value := 3295; + when "0010001" => table_value := 3491; + when "0010010" => table_value := 3688; + when "0010011" => table_value := 3883; + when "0010100" => table_value := 4078; + when "0010101" => table_value := 4273; + when "0010110" => table_value := 4466; + when "0010111" => table_value := 4659; + when "0011000" => table_value := 4852; + when "0011001" => table_value := 5044; + when "0011010" => table_value := 5234; + when "0011011" => table_value := 5425; + when "0011100" => table_value := 5614; + when "0011101" => table_value := 5802; + when "0011110" => table_value := 5990; + when "0011111" => table_value := 6177; + when "0100000" => table_value := 6362; + when "0100001" => table_value := 6547; + when "0100010" => table_value := 6731; + when "0100011" => table_value := 6914; + when "0100100" => table_value := 7095; + when "0100101" => table_value := 7276; + when "0100110" => table_value := 7456; + when "0100111" => table_value := 7634; + when "0101000" => table_value := 7811; + when "0101001" => table_value := 7988; + when "0101010" => table_value := 8162; + when "0101011" => table_value := 8336; + when "0101100" => table_value := 8509; + when "0101101" => table_value := 8680; + when "0101110" => table_value := 8850; + when "0101111" => table_value := 9018; + when "0110000" => table_value := 9185; + when "0110001" => table_value := 9351; + when "0110010" => table_value := 9515; + when "0110011" => table_value := 9678; + when "0110100" => table_value := 9840; + when "0110101" => table_value := 10000; + when "0110110" => table_value := 10158; + when "0110111" => table_value := 10315; + when "0111000" => table_value := 10471; + when "0111001" => table_value := 10625; + when "0111010" => table_value := 10777; + when "0111011" => table_value := 10927; + when "0111100" => table_value := 11076; + when "0111101" => table_value := 11224; + when "0111110" => table_value := 11369; + when "0111111" => table_value := 11513; + when "1000000" => table_value := 11655; + when "1000001" => table_value := 11796; + when "1000010" => table_value := 11934; + when "1000011" => table_value := 12071; + when "1000100" => table_value := 12206; + when "1000101" => table_value := 12339; + when "1000110" => table_value := 12471; + when "1000111" => table_value := 12600; + when "1001000" => table_value := 12728; + when "1001001" => table_value := 12853; + when "1001010" => table_value := 12977; + when "1001011" => table_value := 13099; + when "1001100" => table_value := 13219; + when "1001101" => table_value := 13336; + when "1001110" => table_value := 13452; + when "1001111" => table_value := 13566; + when "1010000" => table_value := 13678; + when "1010001" => table_value := 13787; + when "1010010" => table_value := 13895; + when "1010011" => table_value := 14000; + when "1010100" => table_value := 14104; + when "1010101" => table_value := 14205; + when "1010110" => table_value := 14304; + when "1010111" => table_value := 14401; + when "1011000" => table_value := 14496; + when "1011001" => table_value := 14588; + when "1011010" => table_value := 14679; + when "1011011" => table_value := 14767; + when "1011100" => table_value := 14853; + when "1011101" => table_value := 14936; + when "1011110" => table_value := 15018; + when "1011111" => table_value := 15097; + when "1100000" => table_value := 15174; + when "1100001" => table_value := 15249; + when "1100010" => table_value := 15321; + when "1100011" => table_value := 15391; + when "1100100" => table_value := 15459; + when "1100101" => table_value := 15524; + when "1100110" => table_value := 15587; + when "1100111" => table_value := 15648; + when "1101000" => table_value := 15706; + when "1101001" => table_value := 15762; + when "1101010" => table_value := 15816; + when "1101011" => table_value := 15867; + when "1101100" => table_value := 15916; + when "1101101" => table_value := 15963; + when "1101110" => table_value := 16007; + when "1101111" => table_value := 16048; + when "1110000" => table_value := 16088; + when "1110001" => table_value := 16124; + when "1110010" => table_value := 16159; + when "1110011" => table_value := 16191; + when "1110100" => table_value := 16220; + when "1110101" => table_value := 16247; + when "1110110" => table_value := 16272; + when "1110111" => table_value := 16294; + when "1111000" => table_value := 16314; + when "1111001" => table_value := 16331; + when "1111010" => table_value := 16346; + when "1111011" => table_value := 16358; + when "1111100" => table_value := 16368; + when "1111101" => table_value := 16375; + when "1111110" => table_value := 16380; + when "1111111" => table_value := 16383; + when others => null; + end case; + return table_value; + end; + +end; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/spram.vhd b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/spram.vhd new file mode 100644 index 00000000..ad6b58b5 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/spram.vhd @@ -0,0 +1,55 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY spram IS + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "NORMAL", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone V", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + width_a => data_width_g, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + clocken0 => clken, + data_a => data, + wren_a => wren, + q_a => q + ); + + + +END SYN; diff --git a/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/video_mixer.sv b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..b9f7e424 --- /dev/null +++ b/Arcade/Galaxian Hardware/WarOfBugs_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; +reg [DWIDTH:0] Rd,Gd,Bd; +always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B}; +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(Rd), + .g_in(Gd), + .b_in(Bd), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/ReadMe.txt b/Arcade/IremM52 Hardware/MoonPatrol_MIST/ReadMe.txt new file mode 100644 index 00000000..ee68fd00 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/ReadMe.txt @@ -0,0 +1,27 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Moon Patrol port to MiST by Gehstock +-- 19 December 2017 +-- +--------------------------------------------------------------------------------- +-- Uses PACE framework by http://pacedev.net/ +--------------------------------------------------------------------------------- +-- Moon patrol sound board by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- cpu68 - Version 9th Jan 2004 0.8 +-- 6800/01 compatible CPU core +-- GNU public license - December 2002 : John E. Kent +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin + Start +-- SPACE : Fire +-- CTRL,UP : Jump +-- LEFT,RIGHT : Increase/Decrease the speed +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- \ No newline at end of file diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf b/Arcade/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf new file mode 100644 index 00000000..77989ab8 Binary files /dev/null and b/Arcade/IremM52 Hardware/MoonPatrol_MIST/Release/mpatrol.rbf differ diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/clean.bat b/Arcade/IremM52 Hardware/MoonPatrol_MIST/clean.bat new file mode 100644 index 00000000..c9a2cb06 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qpf b/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qpf new file mode 100644 index 00000000..0ead7d61 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Full Version +# Date created = 08:25:10 February 28, 2013 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "12.1" +DATE = "08:25:10 February 28, 2013" + +# Revisions + +PROJECT_REVISION = "mpatrol" diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf b/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf new file mode 100644 index 00000000..0c3d59fb --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf @@ -0,0 +1,241 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 13:17:08 December 19, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# mpatrol_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:52 FEBRUARY 01, 2013" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:src/build_id.tcl" +set_global_assignment -name VHDL_FILE src/t80/Z80.vhd +set_global_assignment -name VHDL_FILE src/t80/T80se.vhd +set_global_assignment -name VHDL_FILE src/t80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE src/t80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE src/t80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE src/t80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE src/t80/T80.vhd +set_global_assignment -name VHDL_FILE src/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE src/video_controller_pkg.vhd +set_global_assignment -name VHDL_FILE src/video_controller.vhd +set_global_assignment -name VHDL_FILE src/tilemapctl.vhd +set_global_assignment -name VHDL_FILE src/sprom.vhd +set_global_assignment -name VHDL_FILE src/spritereg.vhd +set_global_assignment -name VHDL_FILE src/spritectl.vhd +set_global_assignment -name VHDL_FILE src/sprite_pkg_body.vhd +set_global_assignment -name VHDL_FILE src/sprite_pkg.vhd +set_global_assignment -name VHDL_FILE src/spram.vhd +set_global_assignment -name VHDL_FILE src/platform_variant_pkg.vhd +set_global_assignment -name VHDL_FILE src/platform.vhd +set_global_assignment -name VHDL_FILE src/pace_pkg.vhd +set_global_assignment -name VHDL_FILE src/pace.vhd +set_global_assignment -name VHDL_FILE src/Inputs.VHD +set_global_assignment -name VHDL_FILE src/input_mapper.vhd +set_global_assignment -name VHDL_FILE src/Graphics.VHD +set_global_assignment -name VHDL_FILE src/dprom_2r.vhd +set_global_assignment -name VHDL_FILE src/dpram.vhd +set_global_assignment -name VHDL_FILE src/clk_div.vhd +set_global_assignment -name VHDL_FILE src/bitmap3_ctl.vhd +set_global_assignment -name VHDL_FILE src/bitmap2_ctl.vhd +set_global_assignment -name VHDL_FILE src/bitmap1_ctl.vhd +set_global_assignment -name VHDL_FILE src/i82c55.vhd +set_global_assignment -name VERILOG_FILE src/keyboard.v +set_global_assignment -name VHDL_FILE src/moon_patrol_sound_board.vhd +set_global_assignment -name VHDL_FILE src/cpu68.vhd +set_global_assignment -name VHDL_FILE src/moon_patrol_sound_prog.vhd +set_global_assignment -name VHDL_FILE src/dac.vhd +set_global_assignment -name VHDL_FILE src/video_controller_pkg_body.vhd +set_global_assignment -name VHDL_FILE src/video_mixer.vhd +set_global_assignment -name VHDL_FILE src/mpatrol.vhd +set_global_assignment -name SYSTEMVERILOG_FILE src/hq2x.sv +set_global_assignment -name VERILOG_FILE src/scandoubler.v +set_global_assignment -name SYSTEMVERILOG_FILE src/video_mist.sv +set_global_assignment -name VERILOG_FILE src/osd.v +set_global_assignment -name VERILOG_FILE src/mist_io.v +set_global_assignment -name VHDL_FILE src/sprite_array.vhd +set_global_assignment -name VHDL_FILE src/Clock.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_46 -to UART_TX +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name SEARCH_PATH device/cycloneiii/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/cpu/t80/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/ps2/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/sound/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/pace/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/pace/stubs/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/pace/video/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/platform/m52/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/platform/m52/mpatrol/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/platform/m52/mpatrol/roms/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/target/mist/ -tag from_archive +set_global_assignment -name TOP_LEVEL_ENTITY mpatrol +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(mpatrol) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(mpatrol) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.srf b/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.srf new file mode 100644 index 00000000..7be837d6 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/mpatrol.srf @@ -0,0 +1,4 @@ +{ "" "" "" "*" { } { } 0 10873 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Clock.qip b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Clock.qip new file mode 100644 index 00000000..3a7624fb --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Clock.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock.ppf"] diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd new file mode 100644 index 00000000..4b337d8f --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd @@ -0,0 +1,446 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: Clock.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY Clock IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END Clock; + + +ARCHITECTURE SYN OF clock IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 603, + clk0_duty_cycle => 50, + clk0_multiply_by => 80, + clk0_phase_shift => "0", + clk1_divide_by => 18, + clk1_duty_cycle => 50, + clk1_multiply_by => 5, + clk1_phase_shift => "0", + clk2_divide_by => 9, + clk2_duty_cycle => 50, + clk2_multiply_by => 10, + clk2_phase_shift => "0", + clk3_divide_by => 27, + clk3_duty_cycle => 50, + clk3_multiply_by => 40, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=Clock", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "603" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "18" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.582090" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "30.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "40.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "80" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "40" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "3.58000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "30.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "40.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "603" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "80" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "18" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD new file mode 100644 index 00000000..9c24ca4e --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Graphics.VHD @@ -0,0 +1,183 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; + +entity Graphics is + port + ( + bitmap_ctl_i : in to_BITMAP_CTL_a(1 to 3); + bitmap_ctl_o : out from_BITMAP_CTL_a(1 to 3); + tilemap_ctl_i : in to_TILEMAP_CTL_a(1 to 1); + tilemap_ctl_o : out from_TILEMAP_CTL_a(1 to 1); + sprite_reg_i : in to_SPRITE_REG_t; + sprite_ctl_i : in to_SPRITE_CTL_t; + sprite_ctl_o : out from_SPRITE_CTL_t; + spr0_hit : out std_logic; + graphics_i : in to_GRAPHICS_t; + graphics_o : out from_GRAPHICS_t; + video_i : in from_VIDEO_t; + video_o : out to_VIDEO_t + ); + +end Graphics; + +architecture SYN of Graphics is + + alias clk : std_logic is video_i.clk; + signal from_video_ctl : from_VIDEO_CTL_t; + signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to 3); + signal tilemap_ctl_o_s : from_TILEMAP_CTL_a(1 to 1); + signal sprite_ctl_o_s : from_SPRITE_CTL_t; + signal sprite_pri : std_logic; + signal rgb_data : RGB_t; + signal video_o_s : to_VIDEO_t; + +begin + + video_o.clk <= video_o_s.clk; + video_o.rgb.r <= video_o_s.rgb.r; + video_o.rgb.g <= video_o_s.rgb.g; + video_o.rgb.b <= video_o_s.rgb.b; + video_o.hsync <= video_o_s.hsync; + video_o.vsync <= video_o_s.vsync; + video_o.hblank <= video_o_s.hblank; + video_o.vblank <= video_o_s.vblank; + graphics_o.y <= from_video_ctl.y; + graphics_o.hblank <= video_o_s.hblank; + graphics_o.vblank <= video_o_s.vblank; + + pace_video_controller_inst : entity work.pace_video_controller + generic map + ( + CONFIG => PACE_VIDEO_VGA_800x600_60Hz, + DELAY => 7, + H_SIZE => 256, + V_SIZE => 256, + L_CROP => 0,--8 + R_CROP => 0,--8 + H_SCALE => 2,--2 + V_SCALE => 2,--2 + H_SYNC_POL => '1',--1 + V_SYNC_POL => '1',--1 + BORDER_RGB => RGB_BLACK + ) + port map + ( + video_i => video_i, + reg_i.h_scale => "000", + reg_i.v_scale => "000", + rgb_i => rgb_data, + video_ctl_o => from_video_ctl, + video_o => video_o_s + ); + + + pace_video_mixer_inst : entity work.pace_video_mixer + port map + ( + bitmap_ctl_o => bitmap_ctl_o_s, + tilemap_ctl_o => tilemap_ctl_o_s, + sprite_rgb => sprite_ctl_o_s.rgb, + sprite_set => sprite_ctl_o_s.set, + sprite_pri => sprite_pri, + + video_ctl_i => from_video_ctl, + graphics_i => graphics_i, + rgb_o => rgb_data + ); + + + forground_bitmapctl_inst1 : entity work.BITMAP_1 + generic map + ( + DELAY => 7 + ) + port map + ( + reset => video_i.reset, + video_ctl => from_video_ctl, + ctl_i => bitmap_ctl_i(1), + ctl_o => bitmap_ctl_o_s(1), + graphics_i => graphics_i + ); + + forground_bitmapctl_inst2 : entity work.BITMAP_2 + generic map + ( + DELAY => 7 + ) + port map + ( + reset => video_i.reset, + video_ctl => from_video_ctl, + ctl_i => bitmap_ctl_i(2), + ctl_o => bitmap_ctl_o_s(2), + graphics_i => graphics_i + ); + + + forground_bitmapctl_inst3 : entity work.BITMAP_3 + generic map + ( + DELAY => 7 + ) + port map + ( + reset => video_i.reset, + video_ctl => from_video_ctl, + ctl_i => bitmap_ctl_i(3), + ctl_o => bitmap_ctl_o_s(3), + graphics_i => graphics_i + ); + + + bitmap_ctl_o <= bitmap_ctl_o_s; + + + foreground_mapctl_inst : entity work.TILEMAP_1 + generic map + ( + DELAY => 7 + ) + port map + ( + reset => video_i.reset, + video_ctl => from_video_ctl, + ctl_i => tilemap_ctl_i(1), + ctl_o => tilemap_ctl_o_s(1), + graphics_i => graphics_i + ); + + tilemap_ctl_o <= tilemap_ctl_o_s; + + sprites_inst : sprite_array + generic map + ( + N_SPRITES => 64, + DELAY => 7 + ) + port map + ( + reset => video_i.reset, + reg_i => sprite_reg_i, + video_ctl => from_video_ctl, + graphics_i => graphics_i, + row_a => sprite_ctl_o_s.a, + row_d => sprite_ctl_i.d, + rgb => sprite_ctl_o_s.rgb, + set => sprite_ctl_o_s.set, + pri => sprite_pri, + spr0_set => spr0_hit + ); + + + sprite_ctl_o <= sprite_ctl_o_s; + + +end SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Inputs.VHD b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Inputs.VHD new file mode 100644 index 00000000..ef42f7bd --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/Inputs.VHD @@ -0,0 +1,85 @@ +Library IEEE; +Use IEEE.std_logic_1164.all; + +library work; +use work.pace_pkg.all; + + +entity inputs is + generic + ( + NUM_DIPS : integer := 8; + NUM_INPUTS : integer := 2; + CLK_1US_DIV : natural := 30 + ); + port + ( + clk : in std_logic; + reset : in std_logic; + ps2clk : in std_logic; + ps2data : in std_logic; + jamma : in from_JAMMA_t; + + dips : in std_logic_vector(NUM_DIPS-1 downto 0); + inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1) + ); +end entity inputs; + +architecture SYN of inputs is + + + + signal reset_n : std_logic; + signal tick_1us : std_logic; + signal ps2_reset : std_logic; + signal ps2_press : std_logic; + signal ps2_release : std_logic; + signal ps2_scancode : std_logic_vector(7 downto 0); + +begin + + reset_n <= not reset; + +-- ps2clk <= 'Z'; +-- ps2data <= 'Z'; + + + + inputmapper_inst : entity work.inputmapper + generic map + ( + NUM_DIPS => NUM_DIPS, + NUM_INPUTS => NUM_INPUTS + ) + port map + ( + clk => clk, + rst_n => reset_n, + + reset => ps2_reset, + key_down => ps2_press, + key_up => ps2_release, + data => ps2_scancode, + jamma => jamma, + + dips => dips, + inputs => inputs + ); + + process (clk, reset) + variable count : integer range 0 to CLK_1US_DIV := 0; + begin + if reset = '1' then + count := 0; + tick_1us <= '0'; + elsif rising_edge(clk) then + tick_1us <= '0'; + count := count + 1; + if count = CLK_1US_DIV then + count := 0; + tick_1us <= '1'; + end if; + end if; + end process; + +end architecture SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/YM2149_linmix_sep.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd new file mode 100644 index 00000000..d2ba927b --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap1_ctl.vhd @@ -0,0 +1,111 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; +use work.video_controller_pkg.all; + +entity BITMAP_1 is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity BITMAP_1; + +architecture bit1 of BITMAP_1 is + + alias clk : std_logic is video_ctl.clk; + alias clk_en : std_logic is video_ctl.clk_ena; + alias stb : std_logic is video_ctl.stb; + alias hblank : std_logic is video_ctl.hblank; + alias vblank : std_logic is video_ctl.vblank; + alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; + alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; + alias rgb : RGB_t is ctl_o.rgb; + alias m52_bg1xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(15 downto 8); + alias m52_bg1ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(7 downto 0); + alias m52_bgcontrol : std_logic_vector(7 downto 0) is graphics_i.bit16(2)(7 downto 0); + +begin + + process (clk, reset) + variable y_r : std_logic_vector(y'range); + variable bgy : unsigned(7 downto 0); + variable bgx : unsigned(7 downto 0); + variable bitmap_d_r : std_logic_vector(7 downto 0); + variable pel : std_logic_vector(1 downto 0); + variable pal_i : std_logic_vector(4 downto 0); + variable pal_rgb : pal_rgb_t; + begin + if reset = '1' then + y_r := (others => '0'); + elsif rising_edge (clk) then + -- default + ctl_o.set <= '0'; + -- same for a whole line + ctl_o.a(11 downto 6) <= std_logic_vector(bgy(5 downto 0)); + if clk_en = '1' then + -- handle line changes + if vblank = '1' then + bgy := (others => '1'); + elsif y /= y_r then + if y(7 downto 0) = m52_bg1ypos then + bgy := (others => '0'); + else + -- need to invert to scroll in the right direction + bgx := not unsigned(m52_bg1xpos); + if bgy < 63 then + bgy := bgy + 1; + end if; + end if; + end if; + -- bit 5 is background enable, bit 2 is layer enable + if m52_bgcontrol(5) = '0' and m52_bgcontrol(2) = '0' and graphics_i.bit8(0)(0) = '1' then + if bgy < 64 then + ctl_o.a(5 downto 0) <= std_logic_vector(bgx(7 downto 2)); + if hblank = '0' then + if bgx(1 downto 0) = "01" then + bitmap_d_r := ctl_i.d(7 downto 0); + else + bitmap_d_r := bitmap_d_r(6 downto 0) & '0'; + end if; + bgx := bgx + 1; + --/* the colors to pick is as follows: */ + --/* 1xxbb: city */ + pel := bitmap_d_r(3) & bitmap_d_r(7); + pal_i := "100" & pel; + pal_rgb := bg_pal(to_integer(unsigned(pal_i))); + ctl_o.rgb.r <= pal_rgb(0) & "00"; + ctl_o.rgb.g <= pal_rgb(1) & "00"; + ctl_o.rgb.b <= pal_rgb(2) & "00"; + if pel /= "00" then + ctl_o.set <= '1'; + end if; + end if; -- hblank='0' + end if; -- bgy<64 + end if; -- m52_bgcontrol + y_r := y; + end if; -- clk_en='1' + end if; -- rising_edge(clk) + end process; + + -- unused + ctl_o.a(ctl_o.a'left downto 12) <= (others => '0'); + +end architecture bit1; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd new file mode 100644 index 00000000..baf468eb --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap2_ctl.vhd @@ -0,0 +1,111 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; +use work.video_controller_pkg.all; + +entity BITMAP_2 is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity BITMAP_2; + +architecture bit2 of BITMAP_2 is + + alias clk : std_logic is video_ctl.clk; + alias clk_en : std_logic is video_ctl.clk_ena; + alias stb : std_logic is video_ctl.stb; + alias hblank : std_logic is video_ctl.hblank; + alias vblank : std_logic is video_ctl.vblank; + alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; + alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; + alias rgb : RGB_t is ctl_o.rgb; + alias m52_bg1xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(15 downto 8); + alias m52_bg1ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(0)(7 downto 0); + alias m52_bgcontrol : std_logic_vector(7 downto 0) is graphics_i.bit16(2)(7 downto 0); + +begin + + process (clk, reset) + variable y_r : std_logic_vector(y'range); + variable bgy : unsigned(7 downto 0); + variable bgx : unsigned(7 downto 0); + variable bitmap_d_r : std_logic_vector(7 downto 0); + variable pel : std_logic_vector(1 downto 0); + variable pal_i : std_logic_vector(4 downto 0); + variable pal_rgb : pal_rgb_t; + begin + if reset = '1' then + y_r := (others => '0'); + elsif rising_edge (clk) then + -- default + ctl_o.set <= '0'; + -- same for a whole line + ctl_o.a(11 downto 6) <= std_logic_vector(bgy(5 downto 0)); + if clk_en = '1' then + -- handle line changes + if vblank = '1' then + bgy := (others => '1'); + elsif y /= y_r then + if y(7 downto 0) = m52_bg1ypos then + bgy := (others => '0'); + else + -- need to invert to scroll in the right direction + bgx := not unsigned(m52_bg1xpos); + if bgy < 63 then + bgy := bgy + 1; + end if; + end if; + end if; + -- bit 5 is background enable, bit 1 is layer enable + if m52_bgcontrol(5) = '0' and m52_bgcontrol(1) = '0' and graphics_i.bit8(0)(1) = '1' then + if bgy < 64 then + ctl_o.a(5 downto 0) <= std_logic_vector(bgx(7 downto 2)); + if hblank = '0' then + if bgx(1 downto 0) = "01" then + bitmap_d_r := ctl_i.d(7 downto 0); + else + bitmap_d_r := bitmap_d_r(6 downto 0) & '0'; + end if; + bgx := bgx + 1; + --/* the colors to pick is as follows: */ + --/* 0xxbb: hills */ + pel := bitmap_d_r(3) & bitmap_d_r(7); + pal_i := "000" & pel; + pal_rgb := bg_pal(to_integer(unsigned(pal_i))); + ctl_o.rgb.r <= pal_rgb(0) & "00"; + ctl_o.rgb.g <= pal_rgb(1) & "00"; + ctl_o.rgb.b <= pal_rgb(2) & "00"; + if pel /= "00" then + ctl_o.set <= '1'; + end if; + end if; -- hblank='0' + end if; -- bgy<64 + end if; -- m52_bgcontrol + y_r := y; + end if; -- clk_en='1' + end if; -- rising_edge(clk) + end process; + + -- unused + ctl_o.a(ctl_o.a'left downto 12) <= (others => '0'); + +end architecture bit2; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd new file mode 100644 index 00000000..e27ec7b6 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmap3_ctl.vhd @@ -0,0 +1,111 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; +use work.video_controller_pkg.all; + +entity BITMAP_3 is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity BITMAP_3; + +architecture bit3 of BITMAP_3 is + + alias clk : std_logic is video_ctl.clk; + alias clk_en : std_logic is video_ctl.clk_ena; + alias stb : std_logic is video_ctl.stb; + alias hblank : std_logic is video_ctl.hblank; + alias vblank : std_logic is video_ctl.vblank; + alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; + alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; + alias rgb : RGB_t is ctl_o.rgb; + alias m52_bg2xpos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(15 downto 8); + alias m52_bg2ypos : std_logic_vector(7 downto 0) is graphics_i.bit16(1)(7 downto 0); + alias m52_bgcontrol : std_logic_vector(7 downto 0) is graphics_i.bit16(2)(7 downto 0); + +begin + + process (clk, reset) + variable y_r : std_logic_vector(y'range); + variable bgy : unsigned(7 downto 0); + variable bgx : unsigned(7 downto 0); + variable bitmap_d_r : std_logic_vector(7 downto 0); + variable pel : std_logic_vector(1 downto 0); + variable pal_i : std_logic_vector(4 downto 0); + variable pal_rgb : pal_rgb_t; + begin + if reset = '1' then + y_r := (others => '0'); + elsif rising_edge (clk) then + -- default + ctl_o.set <= '0'; + -- same for a whole line + ctl_o.a(11 downto 6) <= std_logic_vector(bgy(5 downto 0)); + if clk_en = '1' then + -- handle line changes + if vblank = '1' then + bgy := (others => '1'); + elsif y /= y_r then + if y(7 downto 0) = m52_bg2ypos then + bgy := (others => '0'); + else + -- need to invert to scroll in the right direction + bgx := not unsigned(m52_bg2xpos); + if bgy < 63 then + bgy := bgy + 1; + end if; + end if; + end if; + -- bit 5 is background enable, bit 4 is layer enable + if m52_bgcontrol(5) = '0' and m52_bgcontrol(4) = '0' and graphics_i.bit8(0)(2) = '1' then + if bgy < 64 then + ctl_o.a(5 downto 0) <= std_logic_vector(bgx(7 downto 2)); + if hblank = '0' then + if bgx(1 downto 0) = "01" then + bitmap_d_r := ctl_i.d(7 downto 0); + else + bitmap_d_r := bitmap_d_r(6 downto 0) & '0'; + end if; + bgx := bgx + 1; + --/* the colors to pick is as follows: */ + --/* xbb00: mountains */ + pel := bitmap_d_r(3) & bitmap_d_r(7); + pal_i := '0' & pel & "00"; + pal_rgb := bg_pal(to_integer(unsigned(pal_i))); + ctl_o.rgb.r <= pal_rgb(0) & "00"; + ctl_o.rgb.g <= pal_rgb(1) & "00"; + ctl_o.rgb.b <= pal_rgb(2) & "00"; + if pel /= "00" then + ctl_o.set <= '1'; + end if; + end if; -- hblank='0' + end if; -- bgy<64 + end if; -- m52_bgcontrol + y_r := y; + end if; -- clk_en='1' + end if; -- rising_edge(clk) + end process; + + -- unused + ctl_o.a(ctl_o.a'left downto 12) <= (others => '0'); + +end architecture bit3; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd new file mode 100644 index 00000000..1f6a995c --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/bitmapctl_e.vhd @@ -0,0 +1,29 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; + + +entity bitmapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity bitmapCtl; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl new file mode 100644 index 00000000..c8c7096c --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "src/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/build_id.v b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/build_id.v new file mode 100644 index 00000000..47feaad4 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171219" +`define BUILD_TIME "161924" diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/clk_div.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/clk_div.vhd new file mode 100644 index 00000000..020d6ae6 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/clk_div.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity clk_div is + generic + ( + DIVISOR : natural + ); + port + ( + clk : in std_logic; + reset : in std_logic; + + clk_en : out std_logic + ); +end clk_div; + +architecture SYN of clk_div is + +begin + + process (clk, reset) + variable count : integer range 0 to DIVISOR-1; + begin + if reset = '1' then + count := 0; + clk_en <= '0'; + elsif rising_edge(clk) then + clk_en <= '0'; + if count = DIVISOR-1 then + clk_en <= '1'; + count := 0; + else + count := count + 1; + end if; + end if; + end process; + +end SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/cpu68.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/cpu68.vhd new file mode 100644 index 00000000..016bd9a9 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/cpu68.vhd @@ -0,0 +1,3963 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E CPU68 C O R E +-- +-- www.OpenCores.Org - December 2002 +-- This core adheres to the GNU public license +-- +-- File name : cpu68.vhd +-- +-- Purpose : Implements a 6800 compatible CPU core with some +-- additional instructions found in the 6801 +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +-- 22 Sep 2002 0.1 John Kent +-- +-- 30 Oct 2002 0.2 John Kent +-- made NMI edge triggered +-- +-- 30 Oct 2002 0.3 John Kent +-- more corrections to NMI +-- added wai_wait_state to prevent stack overflow on wai. +-- +-- 1 Nov 2002 0.4 John Kent +-- removed WAI states and integrated WAI with the interrupt service routine +-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg. +-- Added Multiply instruction states. +-- run ALU and CC out of CPU module for timing measurements. +-- +-- 3 Nov 2002 0.5 John Kent +-- Memory Data Register was not loaded on Store instructions +-- SEV and CLV were not defined in the ALU +-- Overflow Flag on NEG was incorrect +-- +-- 16th Feb 2003 0.6 John Kent +-- Rearranged the execution cycle for dual operand instructions +-- so that occurs during the following fetch cycle. +-- This allows the reduction of one clock cycle from dual operand +-- instruction. Note that this also necessitated re-arranging the +-- program counter so that it is no longer incremented in the ALU. +-- The effective address has also been re-arranged to include a +-- separate added. The STD (store accd) now sets the condition codes. +-- +-- 28th Jun 2003 0.7 John Kent +-- Added Hold and Halt signals. Hold is used to steal cycles from the +-- CPU or add wait states. Halt puts the CPU in the inactive state +-- and is only honoured in the fetch cycle. Both signals are active high. +-- +-- 9th Jan 2004 0.8 John Kent +-- Clear instruction did an alu_ld8 rather than an alu_clr, so +-- the carry bit was not cleared correctly. +-- This error was picked up by Michael Hassenfratz. +-- + +library ieee; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity cpu68 is + port ( + clk: in std_logic; + rst: in std_logic; + rw: out std_logic; + vma: out std_logic; + address: out std_logic_vector(15 downto 0); + data_in: in std_logic_vector(7 downto 0); + data_out: out std_logic_vector(7 downto 0); + hold: in std_logic; + halt: in std_logic; + irq: in std_logic; + nmi: in std_logic; + test_alu: out std_logic_vector(15 downto 0); + test_cc: out std_logic_vector(7 downto 0) + ); +end; + +architecture CPU_ARCH of cpu68 is + + constant SBIT : integer := 7; + constant XBIT : integer := 6; + constant HBIT : integer := 5; + constant IBIT : integer := 4; + constant NBIT : integer := 3; + constant ZBIT : integer := 2; + constant VBIT : integer := 1; + constant CBIT : integer := 0; + + type state_type is (reset_state, fetch_state, decode_state, + extended_state, indexed_state, read8_state, read16_state, immediate16_state, + write8_state, write16_state, + execute_state, halt_state, error_state, + mul_state, mulea_state, muld_state, + mul0_state, mul1_state, mul2_state, mul3_state, + mul4_state, mul5_state, mul6_state, mul7_state, + jmp_state, jsr_state, jsr1_state, + branch_state, bsr_state, bsr1_state, + rts_hi_state, rts_lo_state, + int_pcl_state, int_pch_state, + int_ixl_state, int_ixh_state, + int_cc_state, int_acca_state, int_accb_state, + int_wai_state, int_mask_state, + rti_state, rti_cc_state, rti_acca_state, rti_accb_state, + rti_ixl_state, rti_ixh_state, + rti_pcl_state, rti_pch_state, + pula_state, psha_state, pulb_state, pshb_state, + pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state, + vect_lo_state, vect_hi_state ); + type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad ); + type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout ); + type op_type is (reset_op, fetch_op, latch_op ); + type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ); + type accb_type is (reset_accb, load_accb, pull_accb, latch_accb ); + type cc_type is (reset_cc, load_cc, pull_cc, latch_cc ); + type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ); + type sp_type is (reset_sp, latch_sp, load_sp ); + type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc ); + type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ); + type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea ); + type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv ); + type nmi_type is (reset_nmi, set_nmi, latch_nmi ); + type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left ); + type right_type is (md_right, zero_right, plus_one_right, accb_right ); + type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, + alu_and, alu_ora, alu_eor, + alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, + alu_inx, alu_dex, alu_cpx, + alu_lsr16, alu_lsl16, + alu_ror8, alu_rol8, + alu_asr8, alu_asl8, alu_lsr8, + alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap, + alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa ); + + signal op_code: std_logic_vector(7 downto 0); + signal acca: std_logic_vector(7 downto 0); + signal accb: std_logic_vector(7 downto 0); + signal cc: std_logic_vector(7 downto 0); + signal cc_out: std_logic_vector(7 downto 0); + signal xreg: std_logic_vector(15 downto 0); + signal sp: std_logic_vector(15 downto 0); + signal ea: std_logic_vector(15 downto 0); + signal pc: std_logic_vector(15 downto 0); + signal md: std_logic_vector(15 downto 0); + signal left: std_logic_vector(15 downto 0); + signal right: std_logic_vector(15 downto 0); + signal out_alu: std_logic_vector(15 downto 0); + signal iv: std_logic_vector(1 downto 0); + signal nmi_req: std_logic; + signal nmi_ack: std_logic; + + signal state: state_type; + signal next_state: state_type; + signal pc_ctrl: pc_type; + signal ea_ctrl: ea_type; + signal op_ctrl: op_type; + signal md_ctrl: md_type; + signal acca_ctrl: acca_type; + signal accb_ctrl: accb_type; + signal ix_ctrl: ix_type; + signal cc_ctrl: cc_type; + signal sp_ctrl: sp_type; + signal iv_ctrl: iv_type; + signal left_ctrl: left_type; + signal right_ctrl: right_type; + signal alu_ctrl: alu_type; + signal addr_ctrl: addr_type; + signal dout_ctrl: dout_type; + signal nmi_ctrl: nmi_type; + + +begin + +---------------------------------- +-- +-- Address bus multiplexer +-- +---------------------------------- + +addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv ) +begin + case addr_ctrl is + when idle_ad => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + when fetch_ad => + address <= pc; + vma <= '1'; + rw <= '1'; + when read_ad => + address <= ea; + vma <= '1'; + rw <= '1'; + when write_ad => + address <= ea; + vma <= '1'; + rw <= '0'; + when push_ad => + address <= sp; + vma <= '1'; + rw <= '0'; + when pull_ad => + address <= sp; + vma <= '1'; + rw <= '1'; + when int_hi_ad => + address <= "1111111111111" & iv & "0"; + vma <= '1'; + rw <= '1'; + when int_lo_ad => + address <= "1111111111111" & iv & "1"; + vma <= '1'; + rw <= '1'; + when others => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + end case; +end process; + +-------------------------------- +-- +-- Data Bus output +-- +-------------------------------- +dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc ) +begin + case dout_ctrl is + when md_hi_dout => -- alu output + data_out <= md(15 downto 8); + when md_lo_dout => + data_out <= md(7 downto 0); + when acca_dout => -- accumulator a + data_out <= acca; + when accb_dout => -- accumulator b + data_out <= accb; + when ix_lo_dout => -- index reg + data_out <= xreg(7 downto 0); + when ix_hi_dout => -- index reg + data_out <= xreg(15 downto 8); + when cc_dout => -- condition codes + data_out <= cc; + when pc_lo_dout => -- low order pc + data_out <= pc(7 downto 0); + when pc_hi_dout => -- high order pc + data_out <= pc(15 downto 8); + when others => + data_out <= "00000000"; + end case; +end process; + + +---------------------------------- +-- +-- Program Counter Control +-- +---------------------------------- + +pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold ) +variable tempof : std_logic_vector(15 downto 0); +variable temppc : std_logic_vector(15 downto 0); +begin + case pc_ctrl is + when add_ea_pc => + if ea(7) = '0' then + tempof := "00000000" & ea(7 downto 0); + else + tempof := "11111111" & ea(7 downto 0); + end if; + when inc_pc => + tempof := "0000000000000001"; + when others => + tempof := "0000000000000000"; + end case; + + case pc_ctrl is + when reset_pc => + temppc := "1111111111111110"; + when load_ea_pc => + temppc := ea; + when pull_lo_pc => + temppc(7 downto 0) := data_in; + temppc(15 downto 8) := pc(15 downto 8); + when pull_hi_pc => + temppc(7 downto 0) := pc(7 downto 0); + temppc(15 downto 8) := data_in; + when others => + temppc := pc; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + pc <= pc; + else + pc <= temppc + tempof; + end if; + end if; +end process; + +---------------------------------- +-- +-- Effective Address Control +-- +---------------------------------- + +ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold ) +variable tempind : std_logic_vector(15 downto 0); +variable tempea : std_logic_vector(15 downto 0); +begin + case ea_ctrl is + when add_ix_ea => + tempind := "00000000" & ea(7 downto 0); + when inc_ea => + tempind := "0000000000000001"; + when others => + tempind := "0000000000000000"; + end case; + + case ea_ctrl is + when reset_ea => + tempea := "0000000000000000"; + when load_accb_ea => + tempea := "00000000" & accb(7 downto 0); + when add_ix_ea => + tempea := xreg; + when fetch_first_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := "00000000"; + when fetch_next_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := ea(7 downto 0); + when others => + tempea := ea; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + ea <= ea; + else + ea <= tempea + tempind; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator A +-- +-------------------------------- +acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + acca <= acca; + else + case acca_ctrl is + when reset_acca => + acca <= "00000000"; + when load_acca => + acca <= out_alu(7 downto 0); + when load_hi_acca => + acca <= out_alu(15 downto 8); + when pull_acca => + acca <= data_in; + when others => +-- when latch_acca => + acca <= acca; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator B +-- +-------------------------------- +accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + accb <= accb; + else + case accb_ctrl is + when reset_accb => + accb <= "00000000"; + when load_accb => + accb <= out_alu(7 downto 0); + when pull_accb => + accb <= data_in; + when others => +-- when latch_accb => + accb <= accb; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- X Index register +-- +-------------------------------- +ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + xreg <= xreg; + else + case ix_ctrl is + when reset_ix => + xreg <= "0000000000000000"; + when load_ix => + xreg <= out_alu(15 downto 0); + when pull_hi_ix => + xreg(15 downto 8) <= data_in; + when pull_lo_ix => + xreg(7 downto 0) <= data_in; + when others => +-- when latch_ix => + xreg <= xreg; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- stack pointer +-- +-------------------------------- +sp_mux : process( clk, sp_ctrl, out_alu, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + sp <= sp; + else + case sp_ctrl is + when reset_sp => + sp <= "0000000000000000"; + when load_sp => + sp <= out_alu(15 downto 0); + when others => +-- when latch_sp => + sp <= sp; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Memory Data +-- +-------------------------------- +md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + md <= md; + else + case md_ctrl is + when reset_md => + md <= "0000000000000000"; + when load_md => + md <= out_alu(15 downto 0); + when fetch_first_md => + md(15 downto 8) <= "00000000"; + md(7 downto 0) <= data_in; + when fetch_next_md => + md(15 downto 8) <= md(7 downto 0); + md(7 downto 0) <= data_in; + when shiftl_md => + md(15 downto 1) <= md(14 downto 0); + md(0) <= '0'; + when others => +-- when latch_md => + md <= md; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- Condition Codes +-- +---------------------------------- + +cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + cc <= cc; + else + case cc_ctrl is + when reset_cc => + cc <= "11000000"; + when load_cc => + cc <= cc_out; + when pull_cc => + cc <= data_in; + when others => +-- when latch_cc => + cc <= cc; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- interrupt vector +-- +---------------------------------- + +iv_mux: process( clk, iv_ctrl, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + iv <= iv; + else + case iv_ctrl is + when reset_iv => + iv <= "11"; + when nmi_iv => + iv <= "10"; + when swi_iv => + iv <= "01"; + when irq_iv => + iv <= "00"; + when others => + iv <= iv; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- op code fetch +-- +---------------------------------- + +op_fetch: process( clk, data_in, op_ctrl, op_code, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + op_code <= op_code; + else + case op_ctrl is + when reset_op => + op_code <= "00000001"; -- nop + when fetch_op => + op_code <= data_in; + when others => +-- when latch_op => + op_code <= op_code; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Left Mux +-- +---------------------------------- + +left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md ) +begin + case left_ctrl is + when acca_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= acca; + when accb_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= accb; + when accd_left => + left(15 downto 8) <= acca; + left(7 downto 0) <= accb; + when ix_left => + left <= xreg; + when sp_left => + left <= sp; + when others => +-- when md_left => + left <= md; + end case; +end process; +---------------------------------- +-- +-- Right Mux +-- +---------------------------------- + +right_mux: process( right_ctrl, data_in, md, accb, ea ) +begin + case right_ctrl is + when zero_right => + right <= "0000000000000000"; + when plus_one_right => + right <= "0000000000000001"; + when accb_right => + right <= "00000000" & accb; + when others => +-- when md_right => + right <= md; + end case; +end process; + +---------------------------------- +-- +-- Arithmetic Logic Unit +-- +---------------------------------- + +mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out ) +variable valid_lo, valid_hi : boolean; +variable carry_in : std_logic; +variable daa_reg : std_logic_vector(7 downto 0); +begin + + case alu_ctrl is + when alu_adc | alu_sbc | + alu_rol8 | alu_ror8 => + carry_in := cc(CBIT); + when others => + carry_in := '0'; + end case; + + valid_lo := left(3 downto 0) <= 9; + valid_hi := left(7 downto 4) <= 9; + + if (cc(CBIT) = '0') then + if( cc(HBIT) = '1' ) then + if valid_hi then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + else + if valid_lo then + if valid_hi then + daa_reg := "00000000"; + else + daa_reg := "01100000"; + end if; + else + if( left(7 downto 4) <= 8 ) then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + else + if ( cc(HBIT) = '1' )then + daa_reg := "01100110"; + else + if valid_lo then + daa_reg := "01100000"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + + case alu_ctrl is + when alu_add8 | alu_inc | + alu_add16 | alu_inx | + alu_adc => + out_alu <= left + right + ("000000000000000" & carry_in); + when alu_sub8 | alu_dec | + alu_sub16 | alu_dex | + alu_sbc | alu_cpx => + out_alu <= left - right - ("000000000000000" & carry_in); + when alu_and => + out_alu <= left and right; -- and/bit + when alu_ora => + out_alu <= left or right; -- or + when alu_eor => + out_alu <= left xor right; -- eor/xor + when alu_lsl16 | alu_asl8 | alu_rol8 => + out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16 + when alu_lsr16 | alu_lsr8 => + out_alu <= carry_in & left(15 downto 1); -- lsr + when alu_ror8 => + out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror + when alu_asr8 => + out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr + when alu_neg => + out_alu <= right - left; -- neg (right=0) + when alu_com => + out_alu <= not left; + when alu_clr | alu_ld8 | alu_ld16 => + out_alu <= right; -- clr, ld + when alu_st8 | alu_st16 => + out_alu <= left; + when alu_daa => + out_alu <= left + ("00000000" & daa_reg); + when alu_tpa => + out_alu <= "00000000" & cc; + when others => + out_alu <= left; -- nop + end case; + + -- + -- carry bit + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(CBIT) <= (left(7) and right(7)) or + (left(7) and not out_alu(7)) or + (right(7) and not out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(CBIT) <= ((not left(7)) and right(7)) or + ((not left(7)) and out_alu(7)) or + (right(7) and out_alu(7)); + when alu_add16 => + cc_out(CBIT) <= (left(15) and right(15)) or + (left(15) and not out_alu(15)) or + (right(15) and not out_alu(15)); + when alu_sub16 => + cc_out(CBIT) <= ((not left(15)) and right(15)) or + ((not left(15)) and out_alu(15)) or + (right(15) and out_alu(15)); + when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 => + cc_out(CBIT) <= left(0); + when alu_rol8 | alu_asl8 => + cc_out(CBIT) <= left(7); + when alu_lsl16 => + cc_out(CBIT) <= left(15); + when alu_com => + cc_out(CBIT) <= '1'; + when alu_neg | alu_clr => + cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); + when alu_daa => + if ( daa_reg(7 downto 4) = "0110" ) then + cc_out(CBIT) <= '1'; + else + cc_out(CBIT) <= '0'; + end if; + when alu_sec => + cc_out(CBIT) <= '1'; + when alu_clc => + cc_out(CBIT) <= '0'; + when alu_tap => + cc_out(CBIT) <= left(CBIT); + when others => -- carry is not affected by cpx + cc_out(CBIT) <= cc(CBIT); + end case; + -- + -- Zero flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_inc | alu_dec | + alu_neg | alu_com | alu_clr | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_ld8 | alu_st8 => + cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_inx | alu_dex | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or + out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or + out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_tap => + cc_out(ZBIT) <= left(ZBIT); + when others => + cc_out(ZBIT) <= cc(ZBIT); + end case; + + -- + -- negative flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_inc | alu_dec | alu_neg | alu_com | alu_clr | + alu_ld8 | alu_st8 => + cc_out(NBIT) <= out_alu(7); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(NBIT) <= out_alu(15); + when alu_tap => + cc_out(NBIT) <= left(NBIT); + when others => + cc_out(NBIT) <= cc(NBIT); + end case; + + -- + -- Interrupt mask flag + -- + case alu_ctrl is + when alu_sei => + cc_out(IBIT) <= '1'; -- set interrupt mask + when alu_cli => + cc_out(IBIT) <= '0'; -- clear interrupt mask + when alu_tap => + cc_out(IBIT) <= left(IBIT); + when others => + cc_out(IBIT) <= cc(IBIT); -- interrupt mask + end case; + + -- + -- Half Carry flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(HBIT) <= (left(3) and right(3)) or + (right(3) and not out_alu(3)) or + (left(3) and not out_alu(3)); + when alu_tap => + cc_out(HBIT) <= left(HBIT); + when others => + cc_out(HBIT) <= cc(HBIT); + end case; + + -- + -- Overflow flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or + ((not left(7)) and (not right(7)) and out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or + ((not left(7)) and right(7) and out_alu(7)); + when alu_add16 => + cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or + ((not left(15)) and (not right(15)) and out_alu(15)); + when alu_sub16 | alu_cpx => + cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or + ((not left(15)) and right(15) and out_alu(15)); + when alu_inc => + cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and + left(3) and left(2) and left(1) and left(0)); + when alu_dec | alu_neg => + cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and + (not left(3)) and (not left(2)) and (not left(1)) and (not left(0))); + when alu_asr8 => + cc_out(VBIT) <= left(0) xor left(7); + when alu_lsr8 | alu_lsr16 => + cc_out(VBIT) <= left(0); + when alu_ror8 => + cc_out(VBIT) <= left(0) xor cc(CBIT); + when alu_lsl16 => + cc_out(VBIT) <= left(15) xor left(14); + when alu_rol8 | alu_asl8 => + cc_out(VBIT) <= left(7) xor left(6); + when alu_tap => + cc_out(VBIT) <= left(VBIT); + when alu_and | alu_ora | alu_eor | alu_com | + alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | + alu_clv => + cc_out(VBIT) <= '0'; + when alu_sev => + cc_out(VBIT) <= '1'; + when others => + cc_out(VBIT) <= cc(VBIT); + end case; + + case alu_ctrl is + when alu_tap => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= left(SBIT); + when others => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= cc(SBIT); + end case; + + test_alu <= out_alu; + test_cc <= cc_out; +end process; + +------------------------------------ +-- +-- Detect Edge of NMI interrupt +-- +------------------------------------ + +nmi_handler : process( clk, rst, nmi, nmi_ack ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_req <= nmi_req; + else + if rst='1' then + nmi_req <= '0'; + else + if (nmi='1') and (nmi_ack='0') then + nmi_req <= '1'; + else + if (nmi='0') and (nmi_ack='1') then + nmi_req <= '0'; + else + nmi_req <= nmi_req; + end if; + end if; + end if; + end if; + end if; +end process; + +------------------------------------ +-- +-- Nmi mux +-- +------------------------------------ + +nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_ack <= nmi_ack; + else + case nmi_ctrl is + when set_nmi => + nmi_ack <= '1'; + when reset_nmi => + nmi_ack <= '0'; + when others => +-- when latch_nmi => + nmi_ack <= nmi_ack; + end case; + end if; + end if; +end process; + +------------------------------------ +-- +-- state sequencer +-- +------------------------------------ +process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt ) + begin + case state is + when reset_state => -- released from reset + -- reset the registers + op_ctrl <= reset_op; + acca_ctrl <= reset_acca; + accb_ctrl <= reset_accb; + ix_ctrl <= reset_ix; + sp_ctrl <= reset_sp; + pc_ctrl <= reset_pc; + ea_ctrl <= reset_ea; + md_ctrl <= reset_md; + iv_ctrl <= reset_iv; + nmi_ctrl <= reset_nmi; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= reset_cc; + -- idle the bus + dout_ctrl <= md_lo_dout; + addr_ctrl <= idle_ad; + next_state <= vect_hi_state; + + -- + -- Jump via interrupt vector + -- iv holds interrupt type + -- fetch PC hi from vector location + -- + when vect_hi_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch pc low interrupt vector + pc_ctrl <= pull_hi_pc; + addr_ctrl <= int_hi_ad; + dout_ctrl <= pc_hi_dout; + next_state <= vect_lo_state; + -- + -- jump via interrupt vector + -- iv holds vector type + -- fetch PC lo from vector location + -- + when vect_lo_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch the vector low byte + pc_ctrl <= pull_lo_pc; + addr_ctrl <= int_lo_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- Here to fetch an instruction + -- PC points to opcode + -- Should service interrupt requests at this point + -- either from the timer + -- or from the external input. + -- + when fetch_state => + case op_code(7 downto 4) is + when "0000" | + "0001" | + "0010" | -- branch conditional + "0011" | + "0100" | -- acca single op + "0101" | -- accb single op + "0110" | -- indexed single op + "0111" => -- extended single op + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + + when "1000" | -- acca immediate + "1001" | -- acca direct + "1010" | -- acca indexed + "1011" => -- acca extended + case op_code(3 downto 0) is + when "0000" => -- suba + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- subd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- anda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bita + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldaa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eora + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- oraa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- adda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- cpx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_cpx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- bsr / jsr + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- lds + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when "1100" | -- accb immediate + "1101" | -- accb direct + "1110" | -- accb indexed + "1111" => -- accb extended + case op_code(3 downto 0) is + when "0000" => -- subb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- addd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- andb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bitb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eorb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- orab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- addb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- ldd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- ldx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + md_ctrl <= latch_md; + -- fetch the op code + op_ctrl <= fetch_op; + ea_ctrl <= reset_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + iv_ctrl <= latch_iv; + if halt = '1' then + pc_ctrl <= latch_pc; + nmi_ctrl <= latch_nmi; + next_state <= halt_state; + -- service non maskable interrupts + elsif (nmi_req = '1') and (nmi_ack = '0') then + pc_ctrl <= latch_pc; + nmi_ctrl <= set_nmi; + next_state <= int_pcl_state; + -- service maskable interrupts + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if(nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + pc_ctrl <= latch_pc; + next_state <= int_pcl_state; + else + -- Advance the PC to fetch next instruction byte + pc_ctrl <= inc_pc; + next_state <= decode_state; + end if; + end if; + -- + -- Here to decode instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode_state => + -- fetch first byte of address or immediate data + ea_ctrl <= fetch_first_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + iv_ctrl <= latch_iv; + case op_code(7 downto 4) is + when "0000" => + md_ctrl <= fetch_first_md; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0001" => -- nop + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0100" => -- lsrd + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0101" => -- lsld + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsl16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0110" => -- tap + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tap; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0111" => -- tpa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tpa; + cc_ctrl <= latch_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1000" => -- inx + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1001" => -- dex + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dex; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1010" => -- clv + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clv; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1011" => -- sev + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sev; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1100" => -- clc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1101" => -- sec + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sec; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1110" => -- cli + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1111" => -- sei + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + end case; + next_state <= fetch_state; + -- acca / accb inherent instructions + when "0001" => + md_ctrl <= fetch_first_md; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + left_ctrl <= acca_left; + right_ctrl <= accb_right; + case op_code(3 downto 0) is + when "0000" => -- sba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "0001" => -- cba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + when "0110" => -- tab + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + when "0111" => -- tba + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1001" => -- daa + alu_ctrl <= alu_daa; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1011" => -- aba + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when others => + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end case; + next_state <= fetch_state; + when "0010" => -- branch conditional + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0000" => -- bra + next_state <= branch_state; + when "0001" => -- brn + next_state <= fetch_state; + when "0010" => -- bhi + if (cc(CBIT) or cc(ZBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0011" => -- bls + if (cc(CBIT) or cc(ZBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0100" => -- bcc/bhs + if cc(CBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0101" => -- bcs/blo + if cc(CBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0110" => -- bne + if cc(ZBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0111" => -- beq + if cc(ZBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1000" => -- bvc + if cc(VBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1001" => -- bvs + if cc(VBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1010" => -- bpl + if cc(NBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1011" => -- bmi + if cc(NBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1100" => -- bge + if (cc(NBIT) xor cc(VBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1101" => -- blt + if (cc(NBIT) xor cc(VBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1110" => -- bgt + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1111" => -- ble + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when others => + next_state <= fetch_state; + end case; + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0000" => -- tsx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "0001" => -- ins + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0010" => -- pula + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pula_state; + when "0011" => -- pulb + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulb_state; + when "0100" => -- des + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0101" => -- txs + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0110" => -- psha + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= psha_state; + when "0111" => -- pshb + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshb_state; + when "1000" => -- pulx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulx_hi_state; + when "1001" => -- rts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rts_hi_state; + when "1010" => -- abx + left_ctrl <= ix_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "1011" => -- rti + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rti_cc_state; + when "1100" => -- pshx + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshx_lo_state; + when "1101" => -- mul + left_ctrl <= acca_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= mul_state; + when "1110" => -- wai + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when "1111" => -- swi + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when others => + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + end case; + -- + -- Accumulator A Single operand + -- source = Acc A dest = Acc A + -- Do not advance PC + -- + when "0100" => -- acca single op + md_ctrl <= fetch_first_md; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + acca_ctrl <= latch_acca; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- single operand acc b + -- Do not advance PC + -- + when "0101" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= accb_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + accb_ctrl <= latch_accb; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- Single operand indexed + -- Two byte instruction so advance PC + -- EA should hold index offset + -- + when "0110" => -- indexed single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + -- + -- Single operand extended addressing + -- three byte instruction so advance the PC + -- Low order EA holds high order address + -- + when "0111" => -- extended single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1000" => -- acca immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- subdd # + "1100" | -- cpx # + "1110" => -- lds # + next_state <= immediate16_state; + when "1101" => -- bsr + next_state <= bsr_state; + when others => + next_state <= fetch_state; + end case; + + when "1001" => -- acca direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- staa direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1111" => -- sts direct + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1101" => -- jsr direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= jsr_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1010" => -- acca indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1011" => -- acca extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1100" => -- accb immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- addd # + "1100" | -- ldd # + "1110" => -- ldx # + next_state <= immediate16_state; + when others => + next_state <= fetch_state; + end case; + + when "1101" => -- accb direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1110" => -- accb indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1111" => -- accb extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when others => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- idle the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= latch_pc; + next_state <= fetch_state; + end case; + + when immediate16_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + op_ctrl <= latch_op; + iv_ctrl <= latch_iv; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + -- fetch next immediate byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- ea holds 8 bit index offet + -- calculate the effective memory address + -- using the alu + -- + when indexed_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- calculate effective address from index reg + -- index offest is not sign extended + ea_ctrl <= add_ix_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + -- work out next state + case op_code(7 downto 4) is + when "0110" => -- single op indexed + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1010" => -- acca indexed + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1110" => -- accb indexed + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- ea holds the low byte of the absolute address + -- Move ea low byte into ea high byte + -- load new ea low byte to for absolute 16 bit address + -- advance the program counter + -- + when extended_state => -- fetch ea low byte + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment pc + pc_ctrl <= inc_pc; + -- fetch next effective address bytes + ea_ctrl <= fetch_next_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + -- work out the next state + case op_code(7 downto 4) is + when "0111" => -- single op extended + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1011" => -- acca extended + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1111" => -- accb extended + case op_code(3 downto 0) is + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- here if ea holds low byte (direct page) + -- can enter here from extended addressing + -- read memory location + -- note that reads may be 8 or 16 bits + -- + when read8_state => -- read data + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + case op_code(7 downto 4) is + when "0110" | "0111" => -- single operand + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + + when "1001" | "1010" | "1011" => -- acca + case op_code(3 downto 0) is + when "0011" | -- subd + "1110" | -- lds + "1100" => -- cpx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- staa +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- jsr +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_nop; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= latch_md; +-- ea_ctrl <= latch_ea; +-- next_state <= jsr_state; +-- when "1111" => -- sts +-- left_ctrl <= sp_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when "1101" | "1110" | "1111" => -- accb + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- stab +-- left_ctrl <= accb_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- std +-- left_ctrl <= accd_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; +-- when "1111" => -- stx +-- left_ctrl <= ix_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + end case; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when read16_state => -- read second data byte from ea + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle the effective address + ea_ctrl <= latch_ea; + -- read the low byte of the 16 bit data + md_ctrl <= fetch_next_md; + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- 16 bit Write state + -- write high byte of ALU output. + -- EA hold address of memory to write to + -- Advance the effective address in ALU + -- + when write16_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment the effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ea_ctrl <= inc_ea; + -- write the ALU hi byte to ea + addr_ctrl <= write_ad; + dout_ctrl <= md_hi_dout; + next_state <= write8_state; + -- + -- 8 bit write + -- Write low 8 bits of ALU output + -- + when write8_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- write ALU low byte output + addr_ctrl <= write_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jmp_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- load PC with effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= load_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jsr_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= jsr1_state; + + when jsr1_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= jmp_state; + + when branch_state => -- Bcc + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- calculate signed branch + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= add_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when bsr_state => -- BSR + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= bsr1_state; + + when bsr1_state => -- BSR + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= branch_state; + + when rts_hi_state => -- RTS + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment the sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rts_lo_state; + + when rts_lo_state => -- RTS1 + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + when mul_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- move acca to md + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mulea_state; + + when mulea_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + md_ctrl <= latch_md; + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- move accb to ea + ea_ctrl <= load_accb_ea; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= muld_state; + + when muld_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + md_ctrl <= latch_md; + -- clear accd + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= latch_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul0_state; + + when mul0_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 0 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(0) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul1_state; + + when mul1_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 1 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(1) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul2_state; + + when mul2_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 2 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(2) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul3_state; + + when mul3_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 3 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(3) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul4_state; + + when mul4_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 4 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(4) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul5_state; + + when mul5_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 5 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(5) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul6_state; + + when mul6_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 6 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(6) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul7_state; + + when mul7_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 7 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(7) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when execute_state => -- execute single operand instruction + -- default + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + case op_code(7 downto 4) is + when "0110" | -- indexed single op + "0111" => -- extended single op + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + left_ctrl <= md_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + end case; + + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + end case; + + when psha_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pula_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pshb_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pulb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pshx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= pshx_hi_state; + + when pshx_hi_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= fetch_state; + + when pulx_hi_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= pulx_lo_state; + + when pulx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= fetch_state; + + -- + -- return from interrupt + -- enter here from bogus interrupts + -- + when rti_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- idle address bus + cc_ctrl <= latch_cc; + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + next_state <= rti_cc_state; + + when rti_cc_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pull_ad; + dout_ctrl <= cc_dout; + next_state <= rti_accb_state; + + when rti_accb_state => + -- default registers + acca_ctrl <= latch_acca; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= rti_acca_state; + + when rti_acca_state => + -- default registers + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= rti_ixh_state; + + when rti_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= rti_ixl_state; + + when rti_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= rti_pch_state; + + when rti_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rti_pcl_state; + + when rti_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- pull pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- here on interrupt + -- iv register hold interrupt type + -- + when int_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= int_pch_state; + + when int_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= int_ixl_state; + + when int_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= int_ixh_state; + + when int_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= int_acca_state; + + when int_acca_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= int_accb_state; + + + when int_accb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= int_cc_state; + + when int_cc_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write cc + addr_ctrl <= push_ad; + dout_ctrl <= cc_dout; + nmi_ctrl <= latch_nmi; + -- + -- nmi is edge triggered + -- nmi_req is cleared when nmi goes low. + -- + if nmi_req = '1' then + iv_ctrl <= nmi_iv; + next_state <= vect_hi_state; + else + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + case op_code is + when "00111110" => -- WAI (wait for interrupt) + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + when "00111111" => -- SWI (Software interrupt) + iv_ctrl <= swi_iv; + next_state <= vect_hi_state; + when others => -- bogus interrupt (return) + iv_ctrl <= latch_iv; + next_state <= rti_state; + end case; + end if; + end if; + + when int_wai_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + ea_ctrl <= latch_ea; + -- enable interrupts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + if (nmi_req = '1') and (nmi_ack='0') then + iv_ctrl <= nmi_iv; + nmi_ctrl <= set_nmi; + next_state <= vect_hi_state; + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if (nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + end if; + end if; + + when int_mask_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- Mask IRQ + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= vect_hi_state; + + when halt_state => -- halt CPU. + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + if halt = '1' then + next_state <= halt_state; + else + next_state <= fetch_state; + end if; + + when others => -- error state halt on undefine states + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= error_state; + end case; +end process; + +-------------------------------- +-- +-- state machine +-- +-------------------------------- + +change_state: process( clk, rst, state, hold ) +begin + if clk'event and clk = '0' then + if rst = '1' then + state <= reset_state; + elsif hold = '1' then + state <= state; + else + state <= next_state; + end if; + end if; +end process; + -- output + +end CPU_ARCH; + diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dac.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dac.vhd new file mode 100644 index 00000000..9685a6cc --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 12 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dpram.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dpram.vhd new file mode 100644 index 00000000..672d33d3 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dpram.vhd @@ -0,0 +1,131 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + --numwords_a : natural; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_a, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dprom_2r.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dprom_2r.vhd new file mode 100644 index 00000000..a17e0e58 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/dprom_2r.vhd @@ -0,0 +1,135 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dprom_2r IS + GENERIC + ( + INIT_FILE : string := ""; + --NUMWORDS_A : natural; + WIDTHAD_A : natural; + WIDTH_A : natural := 8; + --NUMWORDS_B : natural; + WIDTHAD_B : natural; + WIDTH_B : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : in std_logic_vector (WIDTHAD_A-1 downto 0); + address_b : in std_logic_vector (WIDTHAD_B-1 downto 0); + clock : in std_logic ; + q_a : out std_logic_vector (WIDTH_A-1 downto 0); + q_b : out std_logic_vector (WIDTH_B-1 downto 0) + ); +END dprom_2r; + + +ARCHITECTURE SYN OF dprom_2r IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3_bv : BIT_VECTOR (WIDTH_A-1 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (WIDTH_B-1 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + init_file_layout : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + ram_block_type : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (WIDTHAD_A-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (WIDTHAD_B-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire2 <= '0'; + sub_wire3_bv(WIDTH_A-1 DOWNTO 0) <= (others => '0'); + sub_wire3 <= To_stdlogicvector(sub_wire3_bv); + sub_wire4_bv(WIDTH_B-1 DOWNTO 0) <= (others => '0'); + sub_wire4 <= To_stdlogicvector(sub_wire4_bv); + q_a <= sub_wire0(WIDTH_A-1 DOWNTO 0); + q_b <= sub_wire1(WIDTH_B-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK0", + init_file => INIT_FILE, + init_file_layout => "PORT_A", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 2**WIDTHAD_A, + numwords_b => 2**WIDTHAD_B, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + ram_block_type => "M9K", + widthad_a => WIDTHAD_A, + widthad_b => WIDTHAD_B, + width_a => WIDTH_A, + width_b => WIDTH_B, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK0" + ) + PORT MAP ( + wren_a => sub_wire2, + wren_b => sub_wire2, + clock0 => clock, + address_a => address_a, + address_b => address_b, + data_a => sub_wire3, + data_b => sub_wire4, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/gen_ram.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/hq2x.sv b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/i82c55.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/i82c55.vhd new file mode 100644 index 00000000..3cce30d1 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/i82c55.vhd @@ -0,0 +1,686 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity I82C55 is + port ( + + I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_CS_L : in std_logic; + I_RD_L : in std_logic; + I_WR_L : in std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_PC : in std_logic_vector(7 downto 0); + O_PC : out std_logic_vector(7 downto 0); + O_PC_OE_L : out std_logic_vector(7 downto 0); + + RESET : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + CLK : in std_logic + ); +end; + +architecture RTL of I82C55 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(I_DATA) + begin + bit_mask <= x"01"; + case I_DATA(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and I_DATA(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (I_CS_L = '0') and (I_WR_L = '0') then + case I_ADDR is + when "00" => r_porta <= I_DATA; + when "01" => r_portb <= I_DATA; + when "10" => r_portc <= I_DATA; + + when "11" => if (I_DATA(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= I_DATA; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + p_oe : process(I_CS_L, I_RD_L) + begin + O_DATA_OE_L <= '1'; + if (I_CS_L = '0') and (I_RD_L = '0') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read) + begin + O_DATA <= x"00"; -- default + --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required + case I_ADDR is + when "00" => O_DATA <= porta_read; + when "01" => O_DATA <= portb_read; + when "10" => O_DATA <= portc_read; + when "11" => O_DATA <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (I_CS_L = '0') and (I_ADDR = "00") then + porta_we <= not I_WR_L; + porta_re <= not I_RD_L; + end if; + + if (I_CS_L = '0') and (I_ADDR = "01") then + portb_we <= not I_WR_L; + portb_re <= not I_RD_L; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= I_DATA(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= I_DATA(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= I_DATA(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_porta, r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + O_PA <= x"FF"; -- if not driven, float high + O_PA_OE_L <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= I_PA; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_portb, r_control, groupb_mode, r_portb, I_PB, portb_ipreg) + begin + O_PB <= x"FF"; -- if not driven, float high + O_PB_OE_L <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= I_PB; + else -- strobed mode + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + O_PC <= x"FF"; -- if not driven, float high + O_PC_OE_L <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + O_PC (7 downto 4) <= r_portc(7 downto 4); + O_PC_OE_L(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + O_PC (5 downto 4) <= r_portc(5 downto 4); + O_PC_OE_L(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + O_PC (7 downto 6) <= r_portc(7 downto 6); + O_PC_OE_L(7 downto 6) <= "00"; + end if; + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + O_PC (3) <= r_portc(3); + O_PC_OE_L(3) <= '0'; + end if; + -- + else -- stolen + O_PC (3) <= a_intr; + O_PC_OE_L(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + O_PC (2 downto 0) <= r_portc(2 downto 0); + O_PC_OE_L(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + O_PC (1) <= b_obf_l; + O_PC_OE_L(1) <= '0'; + else -- input + O_PC (1) <= b_ibf; + O_PC_OE_L(1) <= '0'; + end if; + O_PC (0) <= b_intr; + O_PC_OE_L(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= I_PC(6); + else -- port a input + a_stb_l <= I_PC(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= I_PC(6); + a_stb_l <= I_PC(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= I_PC(2); + else -- input + b_stb_l <= I_PC(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= I_PC(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= I_PC(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= I_PA; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= I_PB; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/input_mapper.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/input_mapper.vhd new file mode 100644 index 00000000..bd898ba2 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/input_mapper.vhd @@ -0,0 +1,90 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; + +entity inputmapper is + generic + ( + NUM_DIPS : integer := 8; + NUM_INPUTS : integer := 2 + ); + port + ( + clk : in std_logic; + rst_n : in std_logic; + + -- inputs from keyboard controller + reset : in std_logic; + key_down : in std_logic; + key_up : in std_logic; + data : in std_logic_vector(7 downto 0); + -- inputs from jamma connector + jamma : in from_JAMMA_t; + + -- user outputs + dips : in std_logic_vector(NUM_DIPS-1 downto 0); + inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1) + ); +end inputmapper; + +architecture SYN of inputmapper is + +begin + + process (clk, rst_n) + variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1); + variable keybd_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1); + begin + + -- note: all inputs are active LOW + + if rst_n = '0' then + for i in 0 to NUM_INPUTS-1 loop + jamma_v(i).d := (others =>'1'); + keybd_v(i).d := (others =>'0'); + end loop; + + elsif rising_edge (clk) then + + -- handle JAMMA inputs + jamma_v(0).d(0) := jamma.p(1).start; + jamma_v(0).d(1) := jamma.p(2).start; + jamma_v(0).d(2) := jamma.service; + jamma_v(0).d(3) := jamma.coin(1) and jamma.p(1).button(3); + jamma_v(1).d(0) := jamma.p(1).right; + jamma_v(1).d(1) := jamma.p(1).left; + jamma_v(1).d(2) := jamma.p(1).down; + jamma_v(1).d(3) := jamma.p(1).up; + jamma_v(1).d(5) := jamma.p(1).button(2); + jamma_v(1).d(7) := jamma.p(1).button(1); + jamma_v(2).d(4) := jamma.coin(2); + + + -- this is PS/2 reset only + if (reset = '1') then + for i in 0 to NUM_INPUTS-2 loop + keybd_v(i).d := (others =>'1'); + end loop; + keybd_v(NUM_INPUTS-1).d := (others =>'0'); + end if; + end if; -- rising_edge (clk) + + -- assign outputs + inputs(0).d <= jamma_v(0).d and not keybd_v(0).d; + inputs(1).d <= jamma_v(1).d and not keybd_v(1).d; + inputs(2).d <= jamma_v(2).d and not keybd_v(2).d; + inputs(3).d <= "11111111"; -- 1C/1C, 10/30/50K, 3 lives + + inputs(4).d <= "11111100"; + -- activate service which is only checked on startup + -- inputs(4).d <= "01111100"; + inputs(NUM_INPUTS-1).d <= keybd_v(NUM_INPUTS-1).d; + + end process; + +end architecture SYN; + + diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/keyboard.v b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/keyboard.v new file mode 100644 index 00000000..d2e154b9 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/keyboard.v @@ -0,0 +1,80 @@ +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v new file mode 100644 index 00000000..4e20d2a1 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/mist_io.v @@ -0,0 +1,504 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match +// input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scan_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +`include "src\build_id.v" + +localparam conf_str = { + "Moon Patr.;;", +// "O2,HQ2x,On,Off;",no effect + "O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", + "T5,Reset;", + "V,v1.11.",`BUILD_DATE +}; + +localparam STRLEN = ($size(conf_str)>>3); + + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scan_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd new file mode 100644 index 00000000..11f5b5d7 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_board.vhd @@ -0,0 +1,419 @@ +--------------------------------------------------------------------------------- +-- Moon patrol sound board by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- cpu68 - Version 9th Jan 2004 0.8 +-- 6800/01 compatible CPU core +-- GNU public license - December 2002 : John E. Kent +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Version 0.0 -- 24/11/2017 -- +-- initial version +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity moon_patrol_sound_board is +port( + clock_3p58 : in std_logic; + reset : in std_logic; + + select_sound : in std_logic_vector(7 downto 0); + audio_out : out std_logic_vector(11 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) +); +end moon_patrol_sound_board; + +architecture struct of moon_patrol_sound_board is + + signal reset_n : std_logic; + signal clock_div : std_logic_vector(3 downto 0); + + signal cpu_clock : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_rw : std_logic; + signal cpu_irq : std_logic; + signal cpu_nmi : std_logic; + + signal irqraz_cs : std_logic; + signal irqraz_we : std_logic; + + signal wram_cs : std_logic; + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal rom_cs : std_logic; + signal rom_do : std_logic_vector( 7 downto 0); + + signal ay1_do : std_logic_vector(7 downto 0); + signal ay1_audio : std_logic_vector(7 downto 0); + signal ay1_port_b_do : std_logic_vector(7 downto 0); + + signal ay2_do : std_logic_vector(7 downto 0); + signal ay2_audio : std_logic_vector(7 downto 0); + + signal ports_cs : std_logic; + signal ports_we : std_logic; + + signal port1_bus : std_logic_vector(7 downto 0); + signal port1_data : std_logic_vector(7 downto 0); + signal port1_ddr : std_logic_vector(7 downto 0); + signal port1_in : std_logic_vector(7 downto 0); + + signal port2_bus : std_logic_vector(7 downto 0); + signal port2_data : std_logic_vector(7 downto 0); + signal port2_ddr : std_logic_vector(7 downto 0); + signal port2_in : std_logic_vector(7 downto 0); + + signal adpcm_cs : std_logic; + signal adpcm_we : std_logic; + signal adpcm_0_di : std_logic_vector(3 downto 0); + + signal select_sound_7r : std_logic; + + signal audio : std_logic_vector(12 downto 0); + + type t_step_size is array(0 to 48) of integer range 0 to 1552; + constant step_size : t_step_size := ( + 16, 17, 19, 21, 23, 25, 28, 31, + 34, 37, 41, 45, 50, 55, 60, 66, + 73, 80, 88, 97, 107, 118, 130, 143, + 157, 173, 190, 209, 230, 253, 279, 307, + 337, 371, 408, 449, 494, 544, 598, 658, + 724, 796, 876, 963, 1060, 1166, 1282, 1411, 1552); + + type t_delta_step is array(0 to 7) of integer range -1 to 8; + constant delta_step : t_delta_step := (-1,-1,-1,-1,2,4,6,8); + + signal adpcm_vclk : std_logic := '0'; + signal adpcm_signal : integer range -16384 to 16383 := 0; + +-- adpcm algorithm (4bits) [no pcm here] +-- +-- val : input value 3bits (0 - 7 : b2b1b0) +-- sign : input value sign (4th bit : 0=>sign=1 ,1=>sign=-1) +-- +-- step : internal data, init = 0 +-- signal : output value, init = 0; +-- +-- for each new val (and sign) : +-- | +-- | step_size = 16*1.1^(step) +-- | delta = sign * (step_size/8 + step_size/4*b0 + step_size/2*b1 + step_size*b2) +-- | signal = signal + delta +-- | step = step + delta_step(val) +-- | +-- | signal is then limited between -2048..2047 +-- | step is then limited between 0..48 + +begin + +reset_n <= not reset; + +dbg_cpu_addr <= cpu_addr; + +-- clock divider +process (reset, clock_3p58) +begin + if reset='1' then + clock_div <= (others => '0'); + else + if rising_edge(clock_3p58) then + clock_div <= clock_div + '1'; + end if; + end if; +end process; + +-- cpu_clock is 3.58/4 +cpu_clock <= clock_div(1); + +-- cs +wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF +ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F +adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF +irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF +rom_cs <= '1' when cpu_addr(14 downto 12) = "111" else '0'; -- 7000-7FFF / F000-FFFF + +-- write enables +wram_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and wram_cs = '1' else '0'; +ports_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and ports_cs = '1' else '0'; +adpcm_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and adpcm_cs = '1' else '0'; +irqraz_we <= '1' when cpu_rw = '0' and cpu_clock = '1' and irqraz_cs = '1' else '0'; + +-- mux cpu in data between roms/io/wram +cpu_di <= + wram_do when wram_cs = '1' else + port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else + port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else + port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else + port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else + rom_do when rom_cs = '1' else X"55"; + +-- irq to cpu +process (reset, clock_div(0)) + variable select_sound_7r : std_logic; +begin + if reset='1' then + cpu_irq <= '0'; + select_sound_7r := '0'; + else + if rising_edge(clock_div(0)) then + if select_sound_7r = '0' and select_sound(7) = '1' then + cpu_irq <= '1'; + end if; + if irqraz_we = '1' then + cpu_irq <= '0'; + end if; + select_sound_7r := select_sound(7); + end if; + end if; +end process; + +-- cpu nmi +cpu_nmi <= adpcm_vclk; + +-- 6803 ports 1 and 2 (only) +process (reset, clock_div(0)) +begin + if reset='1' then + port1_ddr <= (others=>'0'); -- port1 set as input + port1_data <= (others=>'0'); -- port1 data set to 0 + port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data + port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up) + else + if rising_edge(clock_div(0)) then + if ports_cs = '1' and ports_we = '1' then + if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if; + if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if; + if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if; + if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if; + end if; + end if; + end if; +end process; + +port1_in <= (port1_bus and not(port1_ddr)) or (port1_data and port1_ddr); +port2_in <= (port2_bus and not(port2_ddr)) or (port2_data and port2_ddr); + +-- port1 bus mux +port1_bus <= ay1_do when port2_data(4) = '0' else + ay2_do when port2_data(3) = '0' else X"FF"; + +-- port2 bus +port2_bus <= X"FF"; + + +-- latch adpcm (msm5205) data in +process (reset, clock_div(0)) +begin + if reset='1' then + adpcm_0_di <= (others=>'0'); + else + if rising_edge(clock_div(0)) then + if adpcm_cs = '1' and adpcm_we = '1' then + if cpu_addr(1) = '0' then adpcm_0_di <= cpu_do(3 downto 0); end if; + end if; + end if; + end if; +end process; + +-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz +adpcm_clocks : process(clock_3p58, ay1_port_b_do) + variable clock_div_a : integer range 0 to 148 := 0; + variable clock_div_b : integer range 0 to 5 := 0; + variable step : integer range 0 to 48; + variable step_n : integer range -1 to 48+8; + variable sz : integer range 0 to 1552; + variable dn : integer range -32768 to 32767; + variable adpcm_signal_n : integer range -32768 to 32767; +begin + if rising_edge(clock_3p58) then + if clock_div_a = 148 then -- 24kHz + clock_div_a := 0; + + case ay1_port_b_do(3 downto 2) is + when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 4kHz + when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 8kHz + when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 6kHz + when others => null; + end case; + + if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if; + else + clock_div_a := clock_div_a + 1; + end if; + + if ay1_port_b_do(0) = '1' then + step := 0; + adpcm_signal <= 0; + else + + if clock_div_b = 0 then + case clock_div_a is + + when 0 => -- it's time to get new nibble (adpcm_0_di) + + sz := step_size(step); + dn := sz/8; + if adpcm_0_di(0) = '1' then dn := dn + sz/4; end if; + if adpcm_0_di(1) = '1' then dn := dn + sz/2; end if; + if adpcm_0_di(2) = '1' then dn := dn + sz ; end if; + + if adpcm_0_di(3) = '1' then + dn := -dn; + end if; + + step_n := step + delta_step(to_integer(unsigned(adpcm_0_di(2 downto 0)))); + + when 4 => + + adpcm_signal_n := adpcm_signal + dn; + + if step_n > 48 then step := 48; else step := step_n; end if; + if step_n < 0 then step := 0; else step := step_n; end if; + + when 8 => + + if adpcm_signal_n > 2040 then adpcm_signal <= 2040; else adpcm_signal <= adpcm_signal_n; end if; + if adpcm_signal_n < -2040 then adpcm_signal <= -2040; else adpcm_signal <= adpcm_signal_n; end if; + + when others => null; + + end case; + end if; + + end if; + end if; +end process; + +-- audio mux +audio <= ("00000"&ay1_audio) + ("00000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12))); +audio_out <= audio(12 downto 1); + +-- microprocessor 6800/01/03 +main_cpu : entity work.cpu68 +port map( + clk => cpu_clock,-- E clock input (falling edge) + rst => reset, -- reset input (active high) + rw => cpu_rw, -- read not write output + vma => open, -- valid memory address (active high) + address => cpu_addr, -- address bus output + data_in => cpu_di, -- data bus input + data_out => cpu_do, -- data bus output + hold => '0', -- hold input (active high) extend bus cycle + halt => '0', -- halt input (active high) grants DMA + irq => cpu_irq, -- interrupt request input (active high) + nmi => cpu_nmi, -- non maskable interrupt request input (active high) + test_alu => open, + test_cc => open +); + +-- cpu program rom +cpu_prog_rom : entity work.moon_patrol_sound_prog +port map( + clk => clock_div(0), -- 3p58/2 + addr => cpu_addr(11 downto 0), + data => rom_do +); + +cpu_ram : entity work.spram +generic map( widthad_a => 7) +port map( + clock => clock_div(0), -- 3p58/2 + address => cpu_addr(6 downto 0), + data => cpu_do, + wren => wram_we, + q => wram_do +); + +-- cpu wram +--cpu_ram : entity work.gen_ram +--generic map( width_a => 8, aWidth => 7) +--port map( +-- clk => clock_div(0), -- 3p58/2 +-- we => wram_we, +-- addr => cpu_addr(6 downto 0), +-- d => cpu_do, +-- q => wram_do +--); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => port1_data,-- in std_logic_vector(7 downto 0); + O_DA => ay1_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => port2_data(4), -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => port2_data(0), -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => port2_data(2), -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio, -- out std_logic_vector(7 downto 0); +-- O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => select_sound, -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => ay1_port_b_do, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => cpu_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => port1_data,-- in std_logic_vector(7 downto 0); + O_DA => ay2_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => port2_data(3), -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => port2_data(0), -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => port2_data(2), -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio, -- out std_logic_vector(7 downto 0); +-- O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => cpu_clock -- in std_logic -- note 6 Mhz +); + + +end struct; \ No newline at end of file diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_prog.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_prog.vhd new file mode 100644 index 00000000..a9ee3564 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/moon_patrol_sound_prog.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity moon_patrol_sound_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of moon_patrol_sound_prog is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"08",X"14",X"3F",X"8D",X"51",X"0C",X"24",X"E0",X"91",X"00",X"F9",X"3A",X"1A",X"80",X"C2", + X"F1",X"35",X"00",X"D1",X"59",X"88",X"89",X"D4",X"2B",X"B0",X"52",X"8D",X"84",X"A1",X"2B",X"84", + X"A9",X"03",X"F0",X"88",X"21",X"30",X"BF",X"02",X"B9",X"B3",X"40",X"42",X"1D",X"98",X"B2",X"0C", + X"8A",X"02",X"80",X"09",X"7F",X"91",X"12",X"88",X"23",X"23",X"98",X"D9",X"C3",X"42",X"3B",X"8E", + X"C2",X"00",X"0A",X"A1",X"9C",X"33",X"38",X"89",X"C7",X"8A",X"10",X"02",X"F9",X"12",X"81",X"22", + X"2A",X"9B",X"E9",X"B2",X"0F",X"19",X"B9",X"63",X"9A",X"20",X"A0",X"08",X"9A",X"88",X"2F",X"A4", + X"35",X"20",X"A8",X"83",X"40",X"AA",X"C9",X"89",X"8B",X"90",X"BD",X"92",X"35",X"18",X"C9",X"52", + X"33",X"29",X"03",X"38",X"9B",X"FD",X"82",X"AA",X"18",X"11",X"0B",X"F9",X"13",X"19",X"92",X"62", + X"3A",X"CB",X"D8",X"32",X"1A",X"AB",X"83",X"49",X"B4",X"39",X"B9",X"AD",X"CC",X"A2",X"72",X"89", + X"11",X"09",X"82",X"28",X"88",X"99",X"0E",X"05",X"21",X"89",X"BC",X"CA",X"02",X"99",X"80",X"2A", + X"EB",X"13",X"33",X"25",X"42",X"43",X"10",X"36",X"09",X"B9",X"CE",X"90",X"14",X"31",X"10",X"9D", + X"D9",X"80",X"99",X"B8",X"8A",X"AB",X"A8",X"9B",X"B2",X"76",X"34",X"22",X"18",X"09",X"BB",X"98", + X"33",X"1B",X"DA",X"89",X"92",X"0A",X"BA",X"BD",X"47",X"20",X"9B",X"E9",X"01",X"18",X"88",X"25", + X"41",X"32",X"33",X"52",X"CD",X"98",X"08",X"09",X"82",X"31",X"AF",X"99",X"90",X"89",X"9C",X"CB", + X"CA",X"00",X"A0",X"11",X"10",X"B8",X"44",X"64",X"23",X"10",X"9C",X"99",X"C9",X"01",X"20",X"05", + X"28",X"26",X"22",X"00",X"38",X"DB",X"B0",X"8A",X"A0",X"43",X"53",X"18",X"CD",X"D8",X"03",X"19", + X"AA",X"9A",X"A9",X"AC",X"B2",X"76",X"22",X"AA",X"99",X"9A",X"90",X"0C",X"CA",X"AB",X"99",X"37", + X"61",X"00",X"89",X"02",X"09",X"22",X"81",X"BD",X"CB",X"C9",X"05",X"54",X"20",X"08",X"99",X"A9", + X"22",X"18",X"01",X"18",X"AE",X"B9",X"04",X"48",X"BC",X"88",X"8A",X"EC",X"80",X"11",X"9A",X"99", + X"93",X"75",X"08",X"98",X"88",X"91",X"89",X"12",X"02",X"9A",X"DB",X"04",X"33",X"82",X"39",X"FA", + X"24",X"10",X"9A",X"DD",X"91",X"35",X"33",X"10",X"19",X"A1",X"99",X"AB",X"C3",X"77",X"1A",X"AB", + X"CC",X"90",X"08",X"AC",X"A0",X"23",X"33",X"22",X"05",X"31",X"31",X"13",X"09",X"BA",X"91",X"24", + X"10",X"2C",X"FC",X"DC",X"A8",X"99",X"99",X"88",X"BE",X"92",X"43",X"14",X"31",X"12",X"34",X"35", + X"31",X"13",X"42",X"AA",X"CC",X"BD",X"CA",X"BA",X"01",X"00",X"99",X"9B",X"A0",X"82",X"34",X"63", + X"20",X"81",X"17",X"52",X"00",X"8A",X"9A",X"03",X"32",X"8C",X"CB",X"CD",X"BC",X"AB",X"DA",X"8A", + X"04",X"53",X"21",X"8A",X"81",X"45",X"42",X"28",X"AD",X"BB",X"A9",X"82",X"62",X"21",X"21",X"88", + X"88",X"02",X"00",X"AD",X"AA",X"92",X"70",X"8A",X"CC",X"CB",X"BA",X"A8",X"37",X"42",X"00",X"8A", + X"99",X"AA",X"B8",X"02",X"11",X"0A",X"CA",X"13",X"23",X"75",X"41",X"08",X"99",X"82",X"54",X"32", + X"98",X"A9",X"9A",X"A9",X"9A",X"82",X"54",X"1D",X"EB",X"CB",X"99",X"03",X"53",X"10",X"99",X"89", + X"BC",X"92",X"10",X"33",X"65",X"20",X"99",X"AA",X"A1",X"00",X"32",X"1B",X"EE",X"BA",X"01",X"44", + X"32",X"80",X"13",X"36",X"89",X"A9",X"ED",X"B9",X"88",X"09",X"A0",X"31",X"18",X"07",X"31",X"14", + X"08",X"80",X"31",X"20",X"09",X"DB",X"98",X"89",X"DD",X"90",X"03",X"82",X"50",X"9C",X"A9",X"12", + X"9C",X"D8",X"88",X"34",X"83",X"63",X"32",X"12",X"08",X"32",X"AF",X"BB",X"FC",X"9A",X"CC",X"A0", + X"13",X"42",X"08",X"81",X"11",X"35",X"32",X"42",X"22",X"0C",X"CD",X"98",X"98",X"02",X"08",X"22", + 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X"4C",X"A7",X"90",X"32",X"A7",X"94",X"32",X"A7",X"98",X"DE",X"CD",X"86",X"01",X"39",X"5C",X"27", + X"12",X"DE",X"D1",X"5C",X"26",X"10",X"DC",X"CD",X"A7",X"9C",X"E7",X"A0",X"DE",X"CD",X"EE",X"01", + X"86",X"01",X"39",X"86",X"FF",X"39",X"A6",X"9C",X"E6",X"A0",X"DD",X"CD",X"DE",X"CD",X"08",X"08", + X"08",X"86",X"01",X"39",X"96",X"CE",X"BD",X"FC",X"DD",X"5C",X"96",X"CD",X"BD",X"FC",X"DE",X"5C", + X"39",X"26",X"06",X"BD",X"FC",X"98",X"7E",X"FC",X"AD",X"81",X"10",X"2B",X"03",X"7E",X"FF",X"25", + X"97",X"CB",X"96",X"D8",X"8A",X"01",X"16",X"C4",X"FE",X"D7",X"D8",X"C6",X"0F",X"BD",X"FC",X"DE", + X"86",X"05",X"7F",X"00",X"BD",X"D6",X"BD",X"27",X"FC",X"4A",X"26",X"F6",X"D6",X"CB",X"58",X"58", + X"CE",X"F4",X"00",X"3A",X"3C",X"EE",X"00",X"DF",X"C7",X"38",X"EE",X"02",X"DF",X"C3",X"96",X"BE", + X"84",X"02",X"97",X"BE",X"39",X"16",X"58",X"CE",X"F4",X"24",X"3A",X"EE",X"00",X"81",X"14",X"2A", + X"1C",X"D6",X"82",X"5C",X"27",X"06",X"91",X"A6",X"27",X"02",X"2A",X"10",X"97",X"A6",X"DF",X"88", + X"7F",X"00",X"82",X"7F",X"00",X"8E",X"C6",X"89",X"DA",X"BB",X"D7",X"BB",X"39",X"26",X"11",X"DF", + X"8A",X"97",X"A7",X"7F",X"00",X"83",X"7F",X"00",X"8F",X"86",X"B6",X"9A",X"BB",X"97",X"BB",X"39", + X"81",X"18",X"2A",X"0B",X"DF",X"86",X"97",X"A5",X"7F",X"00",X"81",X"7F",X"00",X"8D",X"39",X"3C", + X"36",X"BD",X"FC",X"98",X"BD",X"FC",X"AD",X"32",X"38",X"DF",X"84",X"97",X"A4",X"7F",X"00",X"80", + X"7F",X"00",X"8C",X"86",X"BE",X"9A",X"BA",X"97",X"BA",X"39",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FB",X"00",X"FB",X"00",X"FB",X"00",X"FB",X"00",X"FC",X"8B",X"FB",X"00",X"FB",X"D9",X"FB",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd new file mode 100644 index 00000000..95c23a95 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd @@ -0,0 +1,293 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; + +entity mpatrol is + port + ( + CLOCK_27 : in std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_SS2 : in std_logic; + SPI_SS3 : in std_logic; + SPI_SS4 : in std_logic; + SPI_DO : out std_logic; + LED : out std_logic; + CONF_DATA0 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + VGA_VS : out std_logic; + VGA_HS : out std_logic; + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0) + ); + +end mpatrol; + +architecture SYN of mpatrol is + + signal init : std_logic := '1'; + signal clk_sys : std_logic; + signal clk_vid : std_logic; + signal clk_osd : std_logic; + signal clkrst_i : from_CLKRST_t; + signal buttons_i : from_BUTTONS_t; + signal switches_i : from_SWITCHES_t; + signal leds_o : to_LEDS_t; + signal inputs_i : from_INPUTS_t; + signal video_i : from_VIDEO_t; + signal video_o : to_VIDEO_t; + --MIST + signal audio : std_logic; + signal status : std_logic_vector(31 downto 0); + signal joystick1 : std_logic_vector(7 downto 0); + signal joystick2 : std_logic_vector(7 downto 0); + signal kbd_joy : std_logic_vector(9 downto 0); + signal switches : std_logic_vector(1 downto 0); + signal buttons : std_logic_vector(1 downto 0); + signal ps2_kbd_clk : std_logic; + signal ps2_kbd_data : std_logic; + signal scan_disable : std_logic; + signal ypbpr : std_logic; + signal r : std_logic_vector(5 downto 0); + signal g : std_logic_vector(5 downto 0); + signal b : std_logic_vector(5 downto 0); + signal hs : std_logic; + signal vs : std_logic; + signal reset : std_logic; + signal clock_3p58 : std_logic; + signal audio_out : std_logic_vector(11 downto 0); + signal sound_data : std_logic_vector(7 downto 0); + +component keyboard + port ( + clk :in STD_LOGIC; + reset :in STD_LOGIC; + ps2_kbd_clk :in STD_LOGIC; + ps2_kbd_data :in STD_LOGIC; + joystick :out STD_LOGIC_VECTOR(9 downto 0)); +end component; + +component mist_io + port ( + clk_sys :in STD_LOGIC; + SPI_SCK :in STD_LOGIC; + CONF_DATA0 :in STD_LOGIC; + SPI_DI :in STD_LOGIC; + SPI_DO :out STD_LOGIC; + SPI_SS2 :in STD_LOGIC; + switches :out STD_LOGIC_VECTOR(1 downto 0); + buttons :out STD_LOGIC_VECTOR(1 downto 0); + scan_disable :out STD_LOGIC; + ypbpr :out STD_LOGIC; + joystick_1 :out STD_LOGIC_VECTOR(7 downto 0); + joystick_0 :out STD_LOGIC_VECTOR(7 downto 0); + status :out STD_LOGIC_VECTOR(31 downto 0); + ps2_kbd_clk :out STD_LOGIC; + ps2_kbd_data :out STD_LOGIC); +end component; + +component video_mist + port ( + clk_sys :in STD_LOGIC; + ce_pix :in STD_LOGIC; + ce_pix_actual :in STD_LOGIC; + SPI_SCK :in STD_LOGIC; + SPI_SS3 :in STD_LOGIC; + SPI_DI :in STD_LOGIC; + R :in STD_LOGIC_VECTOR(5 downto 0); + G :in STD_LOGIC_VECTOR(5 downto 0); + B :in STD_LOGIC_VECTOR(5 downto 0); + HSync :in STD_LOGIC; + VSync :in STD_LOGIC; + VGA_R :out STD_LOGIC_VECTOR(5 downto 0); + VGA_G :out STD_LOGIC_VECTOR(5 downto 0); + VGA_B :out STD_LOGIC_VECTOR(5 downto 0); + VGA_HS :out STD_LOGIC; + VGA_VS :out STD_LOGIC; + scan_disable :in STD_LOGIC; + scanlines :in STD_LOGIC_VECTOR(1 downto 0); + hq2x :in STD_LOGIC; + ypbpr_full :in STD_LOGIC; + line_start :in STD_LOGIC; + mono :in STD_LOGIC); +end component; + + +begin +--CLOCK +Clock_inst : entity work.Clock + port map ( + inclk0 => CLOCK_27, + c0 => clock_3p58,--3.58 + c1 => clk_osd,--10 + c2 => clk_sys,--30 + c3 => clk_vid--40 + ); + + clkrst_i.clk_ref <= CLOCK_27; + clkrst_i.clk(0) <= clk_sys; + clkrst_i.clk(1) <= clk_vid; + +--RESET + process (clk_sys) + variable count : std_logic_vector (11 downto 0) := (others => '0'); + begin + if rising_edge(clk_sys) then + if count = X"FFF" then + init <= '0'; + else + count := count + 1; + init <= '1'; + end if; + end if; + end process; + + clkrst_i.arst <= init or status(5) or buttons(1); + clkrst_i.arst_n <= not clkrst_i.arst; + + GEN_RESETS : for i in 0 to 3 generate + + process (clkrst_i) + variable rst_r : std_logic_vector(2 downto 0) := (others => '0'); + begin + if clkrst_i.arst = '1' then + rst_r := (others => '1'); + elsif rising_edge(clkrst_i.clk(i)) then + rst_r := rst_r(rst_r'left-1 downto 0) & '0'; + end if; + clkrst_i.rst(i) <= rst_r(rst_r'left); + end process; + + end generate GEN_RESETS; + +mist_io_inst : mist_io + port map ( + clk_sys => clk_sys, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_DI => SPI_DI, + SPI_DO => SPI_DO, + SPI_SS2 => SPI_SS2, + switches => switches, + buttons => buttons, + scan_disable => scan_disable, + ypbpr => ypbpr, + joystick_1 => joystick2, + joystick_0 => joystick1, + status => status, + ps2_kbd_clk => ps2_kbd_clk, + ps2_kbd_data => ps2_kbd_data + ); + +video_mist_inst : video_mist + port map ( + clk_sys => clk_sys, + ce_pix => clk_osd, + ce_pix_actual => clk_osd, + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + R => video_o.rgb.r(9 downto 4), + G => video_o.rgb.g(9 downto 4), + B => video_o.rgb.b(9 downto 4), + HSync => video_o.hsync, + VSync => video_o.vsync, + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_HS => VGA_HS, + VGA_VS => VGA_VS, + --ToDo + scan_disable => '1',--scan_disable, + scanlines => status(4 downto 3), + hq2x => status(2), + ypbpr_full => '1', + line_start => '0', + mono => '0' + ); + + video_i.clk <= clk_vid; + video_i.clk_ena <= '1'; + video_i.reset <= clkrst_i.rst(1); + + +u_keyboard : keyboard + port map( + clk => clk_sys, + reset => '0', + ps2_kbd_clk => ps2_kbd_clk, + ps2_kbd_data => ps2_kbd_data, + joystick => kbd_joy +); + + inputs_i.jamma_n.coin(1) <= kbd_joy(3) or status(1);--ESC + inputs_i.jamma_n.p(1).start <= kbd_joy(1) or kbd_joy(2) or status(2);--KB 1+2 + inputs_i.jamma_n.p(1).up <= not (joystick1(3) or joystick2(3) or kbd_joy(4)); + inputs_i.jamma_n.p(1).down <= not (joystick1(2) or joystick2(2) or kbd_joy(5)); + inputs_i.jamma_n.p(1).left <= not (joystick1(1) or joystick2(1) or kbd_joy(6)); + inputs_i.jamma_n.p(1).right <= not (joystick1(0) or joystick2(0) or kbd_joy(7)); + inputs_i.jamma_n.p(1).button(1) <= not (joystick1(4) or joystick2(4) or kbd_joy(0));--Fire + inputs_i.jamma_n.p(1).button(2) <= not (joystick1(5) or joystick2(5) or kbd_joy(8) or joystick1(3) or joystick2(3) or kbd_joy(4));--Jump + inputs_i.jamma_n.p(1).button(3) <= '1'; + inputs_i.jamma_n.p(1).button(4) <= '1'; + inputs_i.jamma_n.p(1).button(5) <= '1'; + inputs_i.jamma_n.p(2).up <= not (joystick1(3) or joystick2(3) or kbd_joy(4)); + inputs_i.jamma_n.p(2).down <= not (joystick1(2) or joystick2(2) or kbd_joy(5)); + inputs_i.jamma_n.p(2).left <= not (joystick1(1) or joystick2(1) or kbd_joy(6)); + inputs_i.jamma_n.p(2).right <= not (joystick1(0) or joystick2(0) or kbd_joy(7)); + inputs_i.jamma_n.p(2).button(1) <= not (joystick1(4) or joystick2(4) or kbd_joy(0));--Fire + inputs_i.jamma_n.p(2).button(2) <= not (joystick1(5) or joystick2(5) or kbd_joy(8) or joystick1(3) or joystick2(3) or kbd_joy(4)); --Jump + inputs_i.jamma_n.p(2).button(3) <= '1'; + inputs_i.jamma_n.p(2).button(4) <= '1'; + inputs_i.jamma_n.p(2).button(5) <= '1'; + -- not currently wired to any inputs + inputs_i.jamma_n.coin_cnt <= (others => '1'); + inputs_i.jamma_n.coin(2) <= '1'; + inputs_i.jamma_n.service <= '1'; + inputs_i.jamma_n.tilt <= '1'; + inputs_i.jamma_n.test <= '1'; + + LED <= '1'; + +moon_patrol_sound_board : entity work.moon_patrol_sound_board + port map( + clock_3p58 => clock_3p58, + reset => clkrst_i.arst, + select_sound => sound_data, + audio_out => audio_out, + dbg_cpu_addr => open + ); + +dac : entity work.dac + port map ( + clk_i => clk_sys, + res_n_i => '1', + dac_i => audio_out, + dac_o => audio + ); + + AUDIO_R <= audio; + AUDIO_L <= audio; + + + + pace_inst : entity work.pace + port map + ( + clkrst_i => clkrst_i, + buttons_i => buttons_i, + switches_i => switches_i, + leds_o => open, + inputs_i => inputs_i, + video_i => video_i, + video_o => video_o, + sound_data_o => sound_data + ); +end SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/osd.v b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd new file mode 100644 index 00000000..48d2dcd0 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace.vhd @@ -0,0 +1,140 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +--use work.platform_pkg.all; +--use work.project_pkg.all; + +entity PACE is + port + ( + -- clocks and resets + clkrst_i : in from_CLKRST_t; + + -- misc I/O + buttons_i : in from_BUTTONS_t; + switches_i : in from_SWITCHES_t; + leds_o : out to_LEDS_t; + + -- controller inputs + inputs_i : in from_INPUTS_t; + + -- video + video_i : in from_VIDEO_t; + video_o : out to_VIDEO_t; + + sound_data_o : out std_logic_vector(7 downto 0) + + -- custom i/o + -- project_i : in from_PROJECT_IO_t; + -- project_o : out to_PROJECT_IO_t; + -- platform_i : in from_PLATFORM_IO_t; + -- platform_o : out to_PLATFORM_IO_t + ); +end entity PACE; + +architecture SYN of PACE is + + constant CLK_1US_COUNTS : integer := + integer(27 * 50 / 20); + + signal mapped_inputs : from_MAPPED_INPUTS_t(0 to 6-1); + + signal to_tilemap_ctl : to_TILEMAP_CTL_a(1 to 1); + signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to 1); + + signal to_bitmap_ctl : to_BITMAP_CTL_a(1 to 3); + signal from_bitmap_ctl : from_BITMAP_CTL_a(1 to 3); + + signal to_sprite_reg : to_SPRITE_REG_t; + signal to_sprite_ctl : to_SPRITE_CTL_t; + signal from_sprite_ctl : from_SPRITE_CTL_t; + signal spr0_hit : std_logic; + + signal to_graphics : to_GRAPHICS_t; + signal from_graphics : from_GRAPHICS_t; + +begin + + inputs_inst : entity work.inputs + generic map + ( + NUM_DIPS => PACE_NUM_SWITCHES, + NUM_INPUTS => 6, + CLK_1US_DIV => CLK_1US_COUNTS + ) + port map + ( + clk => clkrst_i.clk(0), + reset => clkrst_i.rst(0), + ps2clk => inputs_i.ps2_kclk, + ps2data => inputs_i.ps2_kdat, + jamma => inputs_i.jamma_n, + + dips => switches_i, + inputs => mapped_inputs + ); + + platform_inst : entity work.platform + generic map + ( + NUM_INPUT_BYTES => 6 + ) + port map + ( + -- clocking and reset + clkrst_i => clkrst_i, + + -- misc inputs and outputs + buttons_i => buttons_i, + switches_i => switches_i, + leds_o => leds_o, + + -- controller inputs + inputs_i => mapped_inputs, + + -- graphics + bitmap_i => from_bitmap_ctl, + bitmap_o => to_bitmap_ctl, + + tilemap_i => from_tilemap_ctl, + tilemap_o => to_tilemap_ctl, + + sprite_reg_o => to_sprite_reg, + sprite_i => from_sprite_ctl, + sprite_o => to_sprite_ctl, + spr0_hit => spr0_hit, + + graphics_i => from_graphics, + graphics_o => to_graphics, + + sound_data_o => sound_data_o + ); + + graphics_inst : entity work.Graphics + Port Map + ( + bitmap_ctl_i => to_bitmap_ctl, + bitmap_ctl_o => from_bitmap_ctl, + + tilemap_ctl_i => to_tilemap_ctl, + tilemap_ctl_o => from_tilemap_ctl, + + sprite_reg_i => to_sprite_reg, + sprite_ctl_i => to_sprite_ctl, + sprite_ctl_o => from_sprite_ctl, + spr0_hit => spr0_hit, + + graphics_i => to_graphics, + graphics_o => from_graphics, + + -- video (incl. clk) + video_i => video_i, + video_o => video_o + ); + +end SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd new file mode 100644 index 00000000..ec1b95e2 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg.vhd @@ -0,0 +1,155 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +package pace_pkg is + + -- + -- PACE constants which *MUST* be defined + -- + + type PACETargetType is + ( + PACE_TARGET_NANOBOARD_NB1, + PACE_TARGET_DE0, + PACE_TARGET_DE0_CV, -- 5CEBA4 + PACE_TARGET_DE0_NANO, -- EP4CE22 + PACE_TARGET_DE1, + PACE_TARGET_DE2, + PACE_TARGET_DE2_70, -- EP2C70 + PACE_TARGET_DE2_115, -- EP4CE115 + PACE_TARGET_P2, -- A02 build + PACE_TARGET_P2A, -- A04/A build (SRAM byte selects) + PACE_TARGET_P3M, + PACE_TARGET_S3A_700, -- Spartan 3A/N Starter Kit + PACE_TARGET_RC10, + PACE_TARGET_NX2_12, + PACE_TARGET_NEXYS_3, -- Digilent S6 board + PACE_TARGET_CYC3DEV, + PACE_TARGET_CYC5GXDEV, + PACE_TARGET_COCO3PLUS, + PACE_TARGET_S5A, + PACE_TARGET_CARTEBLANCHE_250, + PACE_TARGET_CARTEBLANCHE_500, + PACE_TARGET_BEMICRO, + PACE_TARGET_OPENEP3C16, + PACE_TARGET_MIST, + PACE_TARGET_CHAMELEON64, + PACE_TARGET_RETRORAMBLINGS_CYC3, -- Generic EP3C25 board with custom io boards + PACE_TARGET_S5A_R2_EP4C, + PACE_TARGET_S5A_R2_EP3SL, + PACE_TARGET_S5A_R2B0_EP4C, + PACE_TARGET_S5A_R2B0_EP3SL, + PACE_TARGET_S5A_R2C0_EP4C, + PACE_TARGET_S5A_R2C0_EP3SL, + PACE_TARGET_S5L_A0_EP4C, + PACE_TARGET_S5L_A0_EP3SL, + PACE_TARGET_NAVICO_ROCKY, + PACE_TARGET_NGPACE, + PACE_TARGET_S6M_A0 + ); + + type PACEFpgaVendor_t is + ( + PACE_FPGA_VENDOR_ALTERA, + PACE_FPGA_VENDOR_XILINX, + PACE_FPGA_VENDOR_LATTICE + ); + + type PACEFpgaFamily_t is + ( + PACE_FPGA_FAMILY_CYCLONE1, + PACE_FPGA_FAMILY_CYCLONE2, + PACE_FPGA_FAMILY_CYCLONE3, + PACE_FPGA_FAMILY_CYCLONE4, + PACE_FPGA_FAMILY_CYCLONE5, + PACE_FPGA_FAMILY_CYCLONE6, + PACE_FPGA_FAMILY_STRATIX_III, + PACE_FPGA_FAMILY_SPARTAN3, + PACE_FPGA_FAMILY_SPARTAN3A, + PACE_FPGA_FAMILY_SPARTAN3E + ); + + type PACEJamma_t is + ( + PACE_JAMMA_NONE, + PACE_JAMMA_MAPLE, + PACE_JAMMA_NGC, + PACE_JAMMA_PS2 + ); + + -- Types + + type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0); + + type from_CLKRST_t is record + arst : std_logic; + arst_n : std_logic; + rst : std_logic_vector(0 to 3); + clk_ref : std_logic; --reference clock + clk : std_logic_vector(0 to 3); + end record; + + -- maximums from the DE2 target + + constant PACE_NUM_SWITCHES : natural := 18; + subtype from_SWITCHES_t is std_logic_vector(PACE_NUM_SWITCHES-1 downto 0); + + constant PACE_NUM_BUTTONS : natural := 4; + subtype from_BUTTONS_t is std_logic_vector(PACE_NUM_BUTTONS-1 downto 0); + + constant PACE_NUM_LEDS : natural := 18; + subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0); + + -- + -- JAMMA interface data structures + -- - note: all signals are active LOW + -- + + type from_JAMMA_player_t is record + start : std_logic; + up : std_logic; + down : std_logic; + left : std_logic; + right : std_logic; + button : std_logic_vector(1 to 5); + end record; + + type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t; + + type from_JAMMA_t is record + coin_cnt : std_logic_vector(1 to 2); + service : std_logic; + tilt : std_logic; + test : std_logic; + coin : std_logic_vector(1 to 2); + p : from_JAMMA_player_a(1 to 2); + end record; + + -- + -- INPUTS + -- + subtype analogue_in_t is std_logic_vector(9 downto 0); + type analogue_in_a is array (natural range <>) of analogue_in_t; + + type from_INPUTS_t is record + ps2_kclk : std_logic; + ps2_kdat : std_logic; + ps2_mclk : std_logic; + ps2_mdat : std_logic; + jamma_n : from_JAMMA_t; + -- up to 4 10-bit analgue inputs + analogue : analogue_in_a(1 to 4); + end record; + + type in8_t is record + d : std_logic_vector(7 downto 0); + end record; + + type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t; + + + +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg_body.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg_body.vhd new file mode 100644 index 00000000..e1cedf87 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/pace_pkg_body.vhd @@ -0,0 +1,50 @@ +library work; + +package body pace_pkg is + + function NULL_TO_FLASH return to_FLASH_t is + begin + return ((others => '0'), (others => '0'), '0', '0', '0'); + end NULL_TO_FLASH; + + function NULL_TO_SRAM return to_SRAM_t is + begin + return ((others => '0'), (others => '0'), (others => '0'), '0', '0', '0'); + end NULL_TO_SRAM; + + function NULL_TO_AUDIO return to_AUDIO_t is + begin + return ('0', (others => '0'), (others => '0')); + end NULL_TO_AUDIO; + + function NULL_TO_SPI return to_SPI_t is + begin + return (others => '0'); + end NULL_TO_SPI; + + function NULL_TO_SERIAL return to_SERIAL_t is + begin + return (others => '0'); + end NULL_TO_SERIAL; + + function NULL_TO_SOUND return to_SOUND_t is + begin + return ((others => '0'), (others => '0'), '0', '0'); + end NULL_TO_SOUND; + + function NULL_FROM_OSD return from_OSD_t is + begin + return (others => (others => '0')); + end NULL_FROM_OSD; + + function NULL_TO_OSD return to_OSD_t is + begin + return ('0', (others => '0'), (others => '0'), '0'); + end NULL_TO_OSD; + + function NULL_TO_GP return to_GP_t is + begin + return ((others => '0'), (others => '0')); + end NULL_TO_GP; + +end package body pace_pkg; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd new file mode 100644 index 00000000..571e0ce2 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/platform.vhd @@ -0,0 +1,523 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.platform_variant_pkg.all; + +entity platform is + generic + ( + NUM_INPUT_BYTES : integer + ); + port + ( + -- clocking and reset + clkrst_i : in from_CLKRST_t; + + -- misc I/O + buttons_i : in from_BUTTONS_t; + switches_i : in from_SWITCHES_t; + leds_o : out to_LEDS_t; + + -- controller inputs + inputs_i : in from_MAPPED_INPUTS_t(0 to NUM_INPUT_BYTES-1); + -- graphics + + bitmap_i : in from_BITMAP_CTL_a(1 to 3); + bitmap_o : out to_BITMAP_CTL_a(1 to 3); + + tilemap_i : in from_TILEMAP_CTL_a(1 to 1); + tilemap_o : out to_TILEMAP_CTL_a(1 to 1); + + sprite_reg_o : out to_SPRITE_REG_t; + sprite_i : in from_SPRITE_CTL_t; + sprite_o : out to_SPRITE_CTL_t; + spr0_hit : in std_logic; + + -- various graphics information + graphics_i : in from_GRAPHICS_t; + graphics_o : out to_GRAPHICS_t; + + sound_data_o : out std_logic_vector(7 downto 0) + ); + +end platform; + +architecture SYN of platform is + + alias clk_sys : std_logic is clkrst_i.clk(0); + alias rst_sys : std_logic is clkrst_i.rst(0); + alias clk_video : std_logic is clkrst_i.clk(1); + + -- cpu signals + signal clk_3M072_en : std_logic; + signal cpu_clk_en : std_logic; + signal cpu_a : std_logic_vector(15 downto 0); + signal cpu_d_i : std_logic_vector(7 downto 0); + signal cpu_d_o : std_logic_vector(7 downto 0); + signal cpu_mem_wr : std_logic; + signal cpu_io_wr : std_logic; + signal cpu_irq : std_logic; + + -- ROM signals + signal rom_cs : std_logic; + signal rom_d_o : std_logic_vector(7 downto 0); + + -- keyboard signals + + -- VRAM signals + signal vram_cs : std_logic; + signal vram_wr : std_logic; + signal vram_d_o : std_logic_vector(7 downto 0); + + signal snd_cs : std_logic; + + -- RAM signals + signal wram_cs : std_logic; + signal wram_wr : std_logic; + signal wram_d_o : std_logic_vector(7 downto 0); + + -- CRAM/SPRITE signals + signal cram_cs : std_logic; + signal cram_wr : std_logic; + signal cram_d_o : std_logic_vector(7 downto 0); + signal sprite_cs : std_logic; + + -- misc signals + signal in_cs : std_logic; + signal in_d_o : std_logic_vector(7 downto 0); + signal prot_cs : std_logic; + signal prot_d_o : std_logic_vector(7 downto 0); + + -- other signals + signal rst_platform : std_logic; + signal pause : std_logic; + signal rot_en : std_logic; + +begin + + -- handle special keys + process (clk_sys, rst_sys) + variable spec_keys_r : std_logic_vector(7 downto 0); + alias spec_keys : std_logic_vector(7 downto 0) is inputs_i(6-1).d; + variable layer_en : std_logic_vector(4 downto 0); + begin + if rst_sys = '1' then + rst_platform <= '0'; + pause <= '0'; + rot_en <= '0'; -- to default later + spec_keys_r := (others => '0'); + layer_en := "11111"; + elsif rising_edge(clk_sys) then + rst_platform <= spec_keys(0); + if spec_keys_r(1) = '0' and spec_keys(1) = '1' then + pause <= not pause; + end if; + if spec_keys_r(2) = '0' and spec_keys(2) = '1' then + rot_en <= not rot_en; + if layer_en = "11111" then + layer_en := "00001"; + elsif layer_en = "10000" then + layer_en := "11111"; + else + layer_en := layer_en(3 downto 0) & layer_en(4); + end if; + end if; + spec_keys_r := spec_keys; + end if; + graphics_o.bit8(0)(4 downto 0) <= layer_en; + end process; + + --graphics_o.bit8(0)(0) <= rot_en; + + -- chip select logic + -- ROM $0000-$3FFF + rom_cs <= '1' when STD_MATCH(cpu_a, "00--------------") else '0'; + -- VRAM $8000-$83FF + vram_cs <= '1' when STD_MATCH(cpu_a, X"8"&"00----------") else '0'; + -- CRAM $8400-$87FF + cram_cs <= '1' when STD_MATCH(cpu_a, X"8"&"01----------") else '0'; + -- PROTECTION $8800-$8FFF + prot_cs <= '1' when STD_MATCH(cpu_a, X"8"&"1-----------") else '0'; + -- SPRITE $C800-$CBFF + sprite_cs <= '1' when STD_MATCH(cpu_a, X"C"&"10----------") else '0'; + -- INPUTS $D000-$D004 (-$D7FF) + in_cs <= '1' when STD_MATCH(cpu_a, X"D"&"0-----------") else '0'; + -- RAM $E000-$E7FF + wram_cs <= '1' when STD_MATCH(cpu_a, X"E"&"0-----------") else '0'; + + -- OUTPUT $DXX0 + snd_cs <= '1' when STD_MATCH(cpu_a, X"D"&"0---------00") else '0'; + + process (clk_sys, rst_sys) begin + if rst_sys = '1' then + sound_data_o <= X"00"; + elsif rising_edge(clk_sys) then + if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then + sound_data_o <= cpu_d_o; + end if; + end if; + end process; + + -- memory read mux + cpu_d_i <= rom_d_o when rom_cs = '1' else + vram_d_o when vram_cs = '1' else + cram_d_o when cram_cs = '1' else + prot_d_o when prot_cs = '1' else + in_d_o when in_cs = '1' else + wram_d_o when wram_cs = '1' else + (others => '1'); + + BLK_BGCONTROL : block + + signal m52_scroll : std_logic_vector(7 downto 0); + signal m52_bg1xpos : std_logic_vector(7 downto 0); + signal m52_bg1ypos : std_logic_vector(7 downto 0); + signal m52_bg2xpos : std_logic_vector(7 downto 0); + signal m52_bg2ypos : std_logic_vector(7 downto 0); + signal m52_bgcontrol : std_logic_vector(7 downto 0); + + signal prot_recalc : std_logic; + + begin + -- handle I/O (writes only) + process (clk_sys, rst_sys) + begin + if rst_sys = '1' then + m52_scroll <= (others => '0'); + m52_bg1xpos <= (others => '0'); + m52_bg1ypos <= (others => '0'); + m52_bg2xpos <= (others => '0'); + m52_bg2ypos <= (others => '0'); + m52_bgcontrol <= (others => '0'); + prot_recalc <= '0'; + elsif rising_edge(clk_sys) then + prot_recalc <= '0'; -- default + if cpu_clk_en = '1' and cpu_io_wr = '1' then + case cpu_a(7 downto 5) is + when "000" => + m52_scroll <= cpu_d_o; + when "010" => + m52_bg1xpos <= cpu_d_o; + prot_recalc <= '1'; + when "011" => + m52_bg1ypos <= cpu_d_o; + when "100" => + m52_bg2xpos <= cpu_d_o; + when "101" => + m52_bg2ypos <= cpu_d_o; + when "110" => + m52_bgcontrol <= cpu_d_o; + when others => + null; + end case; + end if; + end if; + end process; + + graphics_o.bit8(1) <= m52_scroll; + graphics_o.bit16(0) <= m52_bg1xpos & m52_bg1ypos; + graphics_o.bit16(1) <= m52_bg2xpos & m52_bg2ypos; + graphics_o.bit16(2) <= X"00" & m52_bgcontrol; + + process (clk_sys, rst_sys) + variable popcount : unsigned(2 downto 0); + begin + if rst_sys = '1' then + prot_d_o <= (others => '0'); + elsif rising_edge(clk_sys) then + if prot_recalc = '1' then + popcount := (others => '0'); + for i in 6 downto 0 loop + if m52_bg1xpos(i) /= '0' then + popcount := popcount + 1; + end if; + end loop; + popcount(0) := popcount(0) xor m52_bg1xpos(7); + end if; -- prot_recalc='1' + end if; -- rising_edge(clk_sys) + prot_d_o <= "00000" & std_logic_vector(popcount); + end process; + + end block BLK_BGCONTROL; + + -- memory block write signals + vram_wr <= vram_cs and cpu_mem_wr; + cram_wr <= cram_cs and cpu_mem_wr; + wram_wr <= wram_cs and cpu_mem_wr; + + -- sprite registers + sprite_reg_o.clk <= clk_sys; + sprite_reg_o.clk_ena <= clk_3M072_en; + sprite_reg_o.a <= cpu_a(7 downto 0); + sprite_reg_o.d <= cpu_d_o; + sprite_reg_o.wr <= sprite_cs and cpu_mem_wr; + + + + BLK_CPU : block + signal cpu_rst : std_logic; + begin + -- generate CPU enable clock (3MHz from 27/30MHz) + clk_en_inst : entity work.clk_div + generic map + ( + DIVISOR => 16 + ) + port map + ( + clk => clk_sys, + reset => rst_sys, + clk_en => clk_3M072_en + ); + + -- gated CPU signals + cpu_clk_en <= clk_3M072_en and not pause; + cpu_rst <= rst_sys or rst_platform; + + cpu_inst : entity work.Z80 + port map + ( + clk => clk_sys, + clk_en => cpu_clk_en, + reset => cpu_rst, + + addr => cpu_a, + datai => cpu_d_i, + datao => cpu_d_o, + + mem_rd => open, + mem_wr => cpu_mem_wr, + io_rd => open, + io_wr => cpu_io_wr, + + intreq => cpu_irq, + intvec => cpu_d_i, + intack => open, + nmi => '0' + ); + end block BLK_CPU; + + BLK_INTERRUPTS : block + + signal vblank_int : std_logic; + + begin + + process (clk_sys, rst_sys) + variable vblank_r : std_logic_vector(3 downto 0); + alias vblank_prev : std_logic is vblank_r(vblank_r'left); + alias vblank_um : std_logic is vblank_r(vblank_r'left-1); + -- 1us duty for VBLANK_INT + variable count : integer range 0 to 49 * 100; + begin + if rst_sys = '1' then + vblank_int <= '0'; + vblank_r := (others => '0'); + count := count'high; + elsif rising_edge(clk_sys) then + -- rising edge vblank only + if vblank_prev = '0' and vblank_um = '1' then + count := 0; + end if; + if count /= count'high then + vblank_int <= '1'; + count := count + 1; + else + vblank_int <= '0'; + end if; + vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank; + end if; -- rising_edge(clk_sys) + end process; + + -- generate INT + cpu_irq <= vblank_int; + + end block BLK_INTERRUPTS; + + BLK_INPUTS : block + begin + + in_d_o <= inputs_i(0).d when cpu_a(2 downto 0) = "000" else + inputs_i(1).d when cpu_a(2 downto 0) = "001" else + inputs_i(2).d when cpu_a(2 downto 0) = "010" else + inputs_i(3).d when cpu_a(2 downto 0) = "011" else + inputs_i(4).d when cpu_a(2 downto 0) = "100" else + X"FF"; + + end block BLK_INPUTS; + + BLK_CPU_ROMS : block + + type rom_d_a is array(0 to 4) of std_logic_vector(7 downto 0); + signal rom_d : rom_d_a; + + begin + + rom_d_o <= rom_d(0) when cpu_a(M52_ROM_WIDTHAD+1 downto M52_ROM_WIDTHAD) = "00" else + rom_d(1) when cpu_a(M52_ROM_WIDTHAD+1 downto M52_ROM_WIDTHAD) = "01" else + rom_d(2) when cpu_a(M52_ROM_WIDTHAD+1 downto M52_ROM_WIDTHAD) = "10" else + rom_d(3); + + GEN_CPU_ROMS : for i in M52_ROM'range generate + rom_inst : entity work.sprom + generic map + ( + init_file => PLATFORM_VARIANT_SRC_DIR & "roms/" & + M52_ROM(i) & ".hex", + widthad_a => M52_ROM_WIDTHAD + ) + port map + ( + clock => clk_sys, + address => cpu_a(M52_ROM_WIDTHAD-1 downto 0), + q => rom_d(i) + ); + end generate GEN_CPU_ROMS; + + end block BLK_CPU_ROMS; + + BLK_GFX_ROMS : block + + type gfx_rom_d_a is array(0 to 1) of std_logic_vector(7 downto 0); + signal chr_rom_d : gfx_rom_d_a; + signal spr_rom_left : gfx_rom_d_a; + signal spr_rom_right : gfx_rom_d_a; + + begin + + GEN_CHAR_ROMS : for i in M52_CHAR_ROM'range generate + char_rom_inst : entity work.sprom + generic map + ( + init_file => PLATFORM_VARIANT_SRC_DIR & "roms/" & + M52_CHAR_ROM(i) & ".hex", + widthad_a => 12 + ) + port map + ( + clock => clk_video, + address => tilemap_i(1).tile_a(11 downto 0), + q => chr_rom_d(i) + ); + end generate GEN_CHAR_ROMS; + + tilemap_o(1).tile_d(15 downto 0) <= chr_rom_d(0) & chr_rom_d(1); + + GEN_SPRITE_ROMS : for i in M52_SPRITE_ROM'range generate + sprite_rom_inst : entity work.dprom_2r + generic map + ( + init_file => PLATFORM_VARIANT_SRC_DIR & "roms/" & + M52_SPRITE_ROM(i) & ".hex", + widthad_a => 12, + widthad_b => 12 + ) + port map + ( + clock => clk_video, + address_a(11 downto 5) => sprite_i.a(11 downto 5), + address_a(4) => '0', + address_a(3 downto 0) => sprite_i.a(3 downto 0), + q_a => spr_rom_left(i), + address_b(11 downto 5) => sprite_i.a(11 downto 5), + address_b(4) => '1', + address_b(3 downto 0) => sprite_i.a(3 downto 0), + q_b => spr_rom_right(i) + ); + end generate GEN_SPRITE_ROMS; + + sprite_o.d(sprite_o.d'left downto 32) <= (others => '0'); + sprite_o.d(31 downto 0) <= spr_rom_left(0) & spr_rom_right(0) & + spr_rom_left(1) & spr_rom_right(1); + + GEN_BG_ROMS : for i in M52_BG_ROM'range generate + bg_rom_inst : entity work.sprom + generic map + ( + init_file => PLATFORM_VARIANT_SRC_DIR & "roms/" & + M52_BG_ROM(i) & ".hex", + widthad_a => 12 + ) + port map + ( + clock => clk_video, + address => bitmap_i(1+i).a(11 downto 0), + q => bitmap_o(1+i).d(7 downto 0) + ); + bitmap_o(1+i).d(15 downto 8) <= (others => '0'); + end generate GEN_BG_ROMS; + + end block BLK_GFX_ROMS; + + -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE + vram_inst : entity work.dpram + generic map + ( + init_file => "", + widthad_a => 10 + ) + port map + ( + clock_b => clk_sys, + address_b => cpu_a(9 downto 0), + wren_b => vram_wr, + data_b => cpu_d_o, + q_b => vram_d_o, + + clock_a => clk_video, + address_a => tilemap_i(1).map_a(9 downto 0), + wren_a => '0', + data_a => (others => 'X'), + q_a => tilemap_o(1).map_d(7 downto 0) + ); + tilemap_o(1).map_d(15 downto 8) <= (others => '0'); + + -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE + cram_inst : entity work.dpram + generic map + ( + init_file => "", + widthad_a => 10 + ) + port map + ( + clock_b => clk_sys, + address_b => cpu_a(9 downto 0), + wren_b => cram_wr, + data_b => cpu_d_o, + q_b => cram_d_o, + + clock_a => clk_video, + address_a => tilemap_i(1).attr_a(9 downto 0), + wren_a => '0', + data_a => (others => 'X'), + q_a => tilemap_o(1).attr_d(7 downto 0) + ); + + tilemap_o(1).attr_d(15 downto 8) <= (others => '0'); + + wram_inst : entity work.spram + generic map + ( + widthad_a => 11 + ) + port map + ( + clock => clk_sys, + address => cpu_a(10 downto 0), + data => cpu_d_o, + wren => wram_wr, + q => wram_d_o + ); + + + sprite_o.ld <= '0'; + leds_o <= (others => '0'); + +end SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd new file mode 100644 index 00000000..7b852809 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/platform_variant_pkg.vhd @@ -0,0 +1,209 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +--use work.target_pkg.all; +--use work.project_pkg.all; +--use work.platform_pkg.all; + +package platform_variant_pkg is + + -- + -- PACE constants which *MUST* be defined + -- + + -- + -- Platform-specific constants (optional) + -- + + constant PLATFORM_VARIANT : string := "mpatrol"; + constant PLATFORM_VARIANT_SRC_DIR : string := ""; + type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0); + type pal_a is array (natural range <>) of pal_rgb_t; + type rom_a is array (natural range <>) of string; + constant M52_ROM : rom_a(0 to 3) := + ( + 0 => "mpa-1.3m", + 1 => "mpa-2.3l", + 2 => "mpa-3.3k", + 3 => "mpa-4.3j" + ); + constant M52_ROM_WIDTHAD : natural := 12; + + constant M52_CHAR_ROM : rom_a(0 to 1) := + ( + 0 => "mpe-5.3e", + 1 => "mpe-4.3f" + ); + + constant M52_SPRITE_ROM : rom_a(0 to 1) := + ( + 0 => "mpb-2.3m", + 1 => "mpb-1.3n" + ); + + constant M52_BG_ROM : rom_a(0 to 2) := + ( + 2 => "mpe-1.3l", -- mountains + 1 => "mpe-2.3k", -- hills + 0 => "mpe-3.3h" -- cityscape + ); + + constant tile_pal : pal_a(0 to 127) := + ( + 1 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 2 => (0=>"11111111", 1=>"11111111", 2=>"11111111"), + 3 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 4 => (0=>"00000000", 1=>"00100001", 2=>"11111111"), + 5 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 6 => (0=>"11111111", 1=>"11111111", 2=>"00000000"), + 7 => (0=>"00000000", 1=>"00100001", 2=>"11111111"), + 8 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 9 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 10 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 11 => (0=>"00000000", 1=>"00100001", 2=>"11111111"), + 12 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 13 => (0=>"00000000", 1=>"10111000", 2=>"00000000"), + 14 => (0=>"11111111", 1=>"00000000", 2=>"10101110"), + 17 => (0=>"11111111", 1=>"10010111", 2=>"01010001"), + 19 => (0=>"10010111", 1=>"01101000", 2=>"01010001"), + 20 => (0=>"11111111", 1=>"10010111", 2=>"01010001"), + 21 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 24 => (0=>"00000000", 1=>"00100001", 2=>"11111111"), + 25 => (0=>"11111111", 1=>"00000000", 2=>"10101110"), + 26 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 27 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 28 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 29 => (0=>"11111111", 1=>"00000000", 2=>"10101110"), + 33 => (0=>"11111111", 1=>"11111111", 2=>"11111111"), + 36 => (0=>"00000000", 1=>"00100001", 2=>"11111111"), + 37 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 38 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 40 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 41 => (0=>"11111111", 1=>"00000000", 2=>"10101110"), + 44 => (0=>"10111000", 1=>"01101000", 2=>"10101110"), + 45 => (0=>"11111111", 1=>"00000000", 2=>"10101110"), + 46 => (0=>"00100001", 1=>"01000111", 2=>"10101110"), + 47 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 48 => (0=>"10111000", 1=>"01101000", 2=>"10101110"), + 49 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 50 => (0=>"11111111", 1=>"11111111", 2=>"00000000"), + 51 => (0=>"10111000", 1=>"01101000", 2=>"10101110"), + 52 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 53 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 54 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 55 => (0=>"10111000", 1=>"01101000", 2=>"10101110"), + 56 => (0=>"10111000", 1=>"01101000", 2=>"10101110"), + 57 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 58 => (0=>"11111111", 1=>"00100001", 2=>"00000000"), + 61 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 62 => (0=>"10111000", 1=>"11111111", 2=>"10101110"), + 63 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 65 => (0=>"11111111", 1=>"10010111", 2=>"01010001"), + 66 => (0=>"10111000", 1=>"11111111", 2=>"10101110"), + 67 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 69 => (0=>"11111111", 1=>"00000000", 2=>"00000000"), + 70 => (0=>"10111000", 1=>"11111111", 2=>"10101110"), + 71 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 73 => (0=>"11111111", 1=>"10010111", 2=>"01010001"), + 74 => (0=>"10111000", 1=>"11111111", 2=>"10101110"), + 75 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 77 => (0=>"11111111", 1=>"10010111", 2=>"01010001"), + 78 => (0=>"10111000", 1=>"11111111", 2=>"10101110"), + 79 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + 81 => (0=>"11111111", 1=>"10010111", 2=>"01010001"), + 82 => (0=>"00000000", 1=>"10111000", 2=>"11111111"), + 83 => (0=>"00100001", 1=>"00000000", 2=>"00000000"), + others => (others => (others => '0')) + ); + + constant bg_pal : pal_a(0 to 31) := + ( + 1 => (0=>"00000000", 1=>"10010111", 2=>"00000000"), + 3 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 4 => (0=>"00000000", 1=>"00000000", 2=>"11111111"), + 5 => (0=>"00000000", 1=>"10010111", 2=>"00000000"), + 7 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 9 => (0=>"00000000", 1=>"10010111", 2=>"00000000"), + 11 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 12 => (0=>"00000000", 1=>"10010111", 2=>"10101110"), + 13 => (0=>"00000000", 1=>"10010111", 2=>"00000000"), + 15 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 18 => (0=>"11111111", 1=>"11011110", 2=>"01010001"), + 19 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 20 => (0=>"00000000", 1=>"00000000", 2=>"11111111"), + 22 => (0=>"11111111", 1=>"11011110", 2=>"01010001"), + 23 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 26 => (0=>"11111111", 1=>"11011110", 2=>"01010001"), + 27 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + 28 => (0=>"00000000", 1=>"10010111", 2=>"10101110"), + 30 => (0=>"11111111", 1=>"11011110", 2=>"01010001"), + 31 => (0=>"00000000", 1=>"11011110", 2=>"01010001"), + others => (others => (others => '0')) + ); + + constant sprite_pal : pal_a(0 to 15) := + ( + 1 => (0=>"00000000", 1=>"00000000", 2=>"00011010"), + 2 => (0=>"11000001", 1=>"00000000", 2=>"10101110"), + 3 => (0=>"00000000", 1=>"10101110", 2=>"11001000"), + 4 => (0=>"10000100", 1=>"11001000", 2=>"00000000"), + 5 => (0=>"11000001", 1=>"00000000", 2=>"00000000"), + 6 => (0=>"00000000", 1=>"11001000", 2=>"00000000"), + 7 => (0=>"10000100", 1=>"00000000", 2=>"00000000"), + 8 => (0=>"11000001", 1=>"11001000", 2=>"11001000"), + 9 => (0=>"11000001", 1=>"11001000", 2=>"00000000"), + 10 => (0=>"10000100", 1=>"01010001", 2=>"00000000"), + 11 => (0=>"00111110", 1=>"00110111", 2=>"00000000"), + 12 => (0=>"00111110", 1=>"00000000", 2=>"11001000"), + 13 => (0=>"11000001", 1=>"10010000", 2=>"00000000"), + 14 => (0=>"00111110", 1=>"10010000", 2=>"11001000"), + 15 => (0=>"00000000", 1=>"01010001", 2=>"00000000"), + others => (others => (others => '0')) + ); + + type table_a is array (natural range <>) of integer range 0 to 15; + constant sprite_table : table_a(0 to 63) := + ( + 1 => 1, + 2 => 2, + 3 => 3, + 5 => 4, + 6 => 2, + 7 => 5, + 9 => 5, + 10 => 6, + 11 => 7, + 13 => 7, + 14 => 8, + 15 => 9, + 17 => 10, + 19 => 11, + 29 => 9, + 30 => 14, + 31 => 5, + 33 => 5, + 34 => 3, + 35 => 15, + 37 => 9, + 38 => 1, + 39 => 5, + 41 => 1, + 42 => 8, + 45 => 1, + 46 => 5, + 49 => 1, + 50 => 5, + 51 => 3, + 53 => 4, + 54 => 13, + 55 => 5, + 57 => 5, + 59 => 5, + 62 => 5, + 63 => 5, + others => 0 + ); + +end package platform_variant_pkg; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/roms/mpa-1.3m.hex b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/roms/mpa-1.3m.hex new file mode 100644 index 00000000..d0c47e2b --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/roms/mpa-1.3m.hex @@ -0,0 +1,257 @@ +:10000000F33100E8ED563A04D0A7F20033CDF40501 +:10001000CDF206CD290DC3680000000000000000ED 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+:100FE000F8000000000000000000000000003FE0EA +:100FF000004040C080808000000101010302020225 +:00000001FF diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spram.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spram.vhd new file mode 100644 index 00000000..d86010fc --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spram.vhd @@ -0,0 +1,91 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + init_file : string := ""; + --numwords_a : natural; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd new file mode 100644 index 00000000..2addead5 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_array.vhd @@ -0,0 +1,164 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +--use ieee.std_logic_arith.all; +--use IEEE.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +--use work.platform_pkg.all; + +entity sprite_array is + generic + ( + N_SPRITES : integer; + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- register interface + reg_i : in to_SPRITE_REG_t; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- extra data + graphics_i : in to_GRAPHICS_t; + + -- sprite data + row_a : out SPRITE_ROW_A_t; + row_d : in SPRITE_ROW_D_t; + + -- video data + rgb : out RGB_t; + set : out std_logic; + pri : out std_logic; + spr0_set : out std_logic + ); +end entity sprite_array; + +architecture SYN of sprite_array is + + type reg_a_t is array (natural range <>) of from_SPRITE_REG_t; + type ctl_i_a_t is array (natural range <>) of to_SPRITE_CTL_t; + type ctl_o_a_t is array (natural range <>) of from_SPRITE_CTL_t; + + alias clk : std_logic is video_ctl.clk; + alias clk_ena : std_logic is video_ctl.clk_ena; + + signal reg_o : reg_a_t(0 to N_SPRITES-1); + signal ctl_i : ctl_i_a_t(0 to N_SPRITES-1); + signal ctl_o : ctl_o_a_t(0 to N_SPRITES-1); + + signal ld_r : std_logic_vector(N_SPRITES-1 downto 0); + +begin + + -- Sprite Data Load Arbiter + -- - enables each sprite controller during hblank + -- to allow loading of sprite row data into row buffer + process (clk, clk_ena, reset) + variable i : integer range 0 to N_SPRITES-1; + begin + if reset = '1' then + -- enable must be 1 clock behind address to latch data after fetch + --ld_r <= (N_SPRITES-1 => '1', others => '0'); + -- make ISE 9.2.03i happy... + ld_r(ld_r'left) <= '1'; + ld_r(ld_r'left-1 downto 0) <= (others => '0'); + i := 0; + elsif rising_edge(clk) and clk_ena = '1' then + ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left); + if i = N_SPRITES-1 then + i := 0; + else + i := i + 1; + end if; + row_a <= ctl_o(i).a; + end if; + end process; + + -- sprite row data fan-out + GEN_ROW_D : for i in 0 to N_SPRITES-1 generate + ctl_i(i).ld <= ld_r(i); + ctl_i(i).d <= row_d; + end generate GEN_ROW_D; + + -- Sprite Priority Encoder + -- - determines which sprite pixel (if any) is to be displayed + -- We can use a clocked process here because the tilemap + -- output is 1 clock behind at this point + process (clk, clk_ena) + variable spr_on_v : std_logic := '0'; + variable spr_pri_v : std_logic := '0'; + begin + if rising_edge(clk) and clk_ena = '1' then + spr_on_v := '0'; + spr_pri_v := '0'; + for i in 0 to N_SPRITES-1 loop + -- if highest priority = 0 and pixel on + if spr_pri_v = '0' and ctl_o(i).set = '1' then + -- if no sprite on or this priority = 1 + if spr_on_v = '0' or reg_o(i).pri = '1' then + rgb <= ctl_o(i).rgb; + spr_on_v := '1'; -- flag as sprite on + spr_pri_v := reg_o(i).pri; -- store priority + end if; + end if; + end loop; + end if; + set <= spr_on_v; + pri <= spr_pri_v; + end process; + + -- for NES, and perhaps others + -- it's actually more complicated than this + -- but it'll do for now... + spr0_set <= ctl_o(0).set; + + -- + -- Component Instantiation + -- + + GEN_REGS : for i in 0 to N_SPRITES-1 generate + + sptReg_inst : entity work.sptReg + generic map + ( + INDEX => i + ) + port map + ( + reg_i => reg_i, + reg_o => reg_o(i) + ); + + sptCtl_inst : entity work.spritectl + generic map + ( + INDEX => i, + DELAY => DELAY + ) + port map + ( + -- sprite registers + reg_i => reg_o(i), + + -- video control signals + video_ctl => video_ctl, + + -- sprite control signals + ctl_i => ctl_i(i), + ctl_o => ctl_o(i), + + graphics_i => graphics_i + ); + + end generate GEN_REGS; + +end SYN; + diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_pkg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_pkg.vhd new file mode 100644 index 00000000..ee5cf179 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_pkg.vhd @@ -0,0 +1,97 @@ +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.numeric_std.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.video_controller_pkg.all; + +package sprite_pkg is + + subtype SPRITE_N_t is std_logic_vector(11 downto 0); + subtype SPRITE_A_t is std_logic_vector(7 downto 0); + subtype SPRITE_D_t is std_logic_vector(7 downto 0); + + type from_SPRITE_REG_t is record + n : SPRITE_N_t; + x : std_logic_vector(10 downto 0); + y : std_logic_vector(10 downto 0); + xflip : std_logic; + yflip : std_logic; + colour : std_logic_vector(7 downto 0); + pri : std_logic; + end record; + + type to_SPRITE_REG_t is record + clk : std_logic; + clk_ena : std_logic; + wr : std_logic; + a : SPRITE_A_t; + d : SPRITE_D_t; + end record; + + function NULL_TO_SPRITE_REG return to_SPRITE_REG_t; + + subtype SPRITE_ROW_D_t is std_logic_vector(63 downto 0); + subtype SPRITE_ROW_A_t is std_logic_vector(15 downto 0); + + type to_SPRITE_CTL_t is record + ld : std_logic; + d : SPRITE_ROW_D_t; + end record; + + type from_SPRITE_CTL_t is record + a : SPRITE_ROW_A_t; + rgb : RGB_t; + set : std_logic; + end record; + + function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t; + + component sprite_array is + generic + ( + N_SPRITES : integer; + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- register interface + reg_i : in to_SPRITE_REG_t; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- extra data + graphics_i : in to_GRAPHICS_t; + + -- sprite data + row_a : out SPRITE_ROW_A_t; + row_d : in SPRITE_ROW_D_t; + + -- video data + rgb : out RGB_t; + set : out std_logic; + pri : out std_logic; + spr0_set : out std_logic + ); + end component sprite_array; + + function flip_row + ( + row_in : std_logic_vector; + flip : std_logic + ) + return SPRITE_ROW_D_t; + + function flip_1 + ( + d_i : std_logic_vector; + flip : std_logic + ) + return std_logic_vector; + +end package sprite_pkg; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_pkg_body.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_pkg_body.vhd new file mode 100644 index 00000000..551261b2 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprite_pkg_body.vhd @@ -0,0 +1,62 @@ +library work; +use work.pace_pkg.all; +--use work.sprite_pkg.all; + +package body sprite_pkg is + + function NULL_TO_SPRITE_REG return to_SPRITE_REG_t is + begin + return ('0', '0', '0', (others => '0'), (others => '0')); + end function NULL_TO_SPRITE_REG; + + function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t is + begin + return ('0', (others => '0')); + end function NULL_TO_SPRITE_CTL; + + function flip_row + ( + row_in : std_logic_vector; + flip : std_logic + ) + return std_logic_vector is + + constant HALF : natural := (row_in'length / 2) - 1; + + alias row_in_0 : std_logic_vector(row_in'length-1 downto 0) + is row_in; + variable row_out : std_logic_vector(row_in_0'range); + + begin + + if flip = '0' then + return row_in; + else + for i in 0 to HALF loop + row_out ((HALF-i)*2+1 downto (HALF-i)*2) := row_in_0(i*2+1 downto i*2); + end loop; + return row_out; + end if; + + end flip_row; + + function flip_1 + ( + d_i : std_logic_vector; + flip : std_logic + ) + return std_logic_vector is + alias d_i_0 : std_logic_vector(d_i'length-1 downto 0) is d_i; + variable d_o : std_logic_vector(d_i_0'range); + begin + if flip = '0' then + return d_i; + else + for i in d_i_0'range loop + d_o(i) := d_i_0(d_i_0'high-i); + end loop; + return d_o; + end if; + end function flip_1; + +end package body sprite_pkg; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd new file mode 100644 index 00000000..900bd5fa --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spritectl.vhd @@ -0,0 +1,154 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.platform_variant_pkg.all; + +entity spritectl is + generic + ( + INDEX : natural; + DELAY : integer + ); + port + ( + -- sprite registers + reg_i : in from_SPRITE_REG_t; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- sprite control signals + ctl_i : in to_SPRITE_CTL_t; + ctl_o : out from_SPRITE_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity spritectl; + +architecture SYN of spritectl is + + alias clk : std_logic is video_ctl.clk; + alias clk_ena : std_logic is video_ctl.clk_ena; + + signal flipData : std_logic_vector(31 downto 0); -- flipped row data + + alias rgb : RGB_t is ctl_o.rgb; + +begin + + flipData(31 downto 16) <= flip_1 (ctl_i.d(31 downto 16), reg_i.xflip); + flipData(15 downto 0) <= flip_1 (ctl_i.d(15 downto 0), reg_i.xflip); + + process (clk, clk_ena, reg_i) + + variable rowStore : std_logic_vector(31 downto 0); -- saved row of spt to show during visibile period + variable pel : std_logic_vector(1 downto 0); + variable x : unsigned(video_ctl.x'range); + variable y : unsigned(video_ctl.y'range); + variable yMat : boolean; -- raster is between first and last line of sprite + variable xMat : boolean; -- raster in between left edge and end of line + + -- the width of rowCount determines the scanline multipler + -- - eg. (4 downto 0) is 1:1 + -- (5 downto 0) is 2:1 (scan-doubling) + variable rowCount : unsigned(3+2 downto 0); + alias row : unsigned(4 downto 0) is + rowCount(rowCount'left downto rowCount'left-4); + + variable tbl_i : std_logic_vector(5 downto 0); -- 64 table entries + variable pal_i : integer range 0 to 15; + variable pal_rgb : pal_rgb_t; + + begin + + if rising_edge(clk) then + if clk_ena = '1' then + + x := unsigned(reg_i.x) + 7 - 3; + y := 254 - unsigned(reg_i.y) - 16; + + if video_ctl.hblank = '1' then + + xMat := false; + -- stop sprites wrapping from bottom of screen + if y = 0 then + yMat := false; + end if; + + if y = unsigned(video_ctl.y) then + -- start counting sprite row + rowCount := (others => '0'); + yMat := true; + elsif row = "10000" then + yMat := false; + end if; + + -- sprites not visible before row 16 + if ctl_i.ld = '1' then + if yMat then + rowStore := flipData; -- load sprite data + else + rowStore := (others => '0'); + end if; + end if; + + end if; + + if video_ctl.stb = '1' then + + if x = unsigned(video_ctl.x) then + -- count up at left edge of sprite + rowCount := rowCount + 1; + -- start of sprite + --if unsigned(x) /= 0 and unsigned(x) < 240 then + xMat := true; + --end if; + end if; + + if xMat then + -- shift in next pixel + pel := rowStore(rowStore'left) & rowStore(rowStore'left-16); + rowStore(31 downto 16) := rowStore(30 downto 16) & '0'; + rowStore(15 downto 0) := rowStore(14 downto 0) & '0'; + end if; + + end if; + + -- the sprite table is pre-calculated and + -- contains 64 entries for palette look-up + -- the palette itself contains just 16 entries + tbl_i := reg_i.colour(3 downto 0) & pel; + pal_i := sprite_table(to_integer(unsigned(tbl_i))); + pal_rgb := sprite_pal(pal_i); + rgb.r <= pal_rgb(0) & "00"; + rgb.g <= pal_rgb(1) & "00"; + rgb.b <= pal_rgb(2) & "00"; + + -- set pixel transparency based on match + ctl_o.set <= '0'; + if xMat and pel /= "00" then + if graphics_i.bit8(0)(4) = '1' then + ctl_o.set <= '1'; + end if; + end if; + + end if; -- clk_ena='1' + end if; -- rising_edge(clk) + + -- generate sprite data address + ctl_o.a(11 downto 5) <= reg_i.n(6 downto 0); + ctl_o.a(4) <= '0'; -- dual-port RAM + if reg_i.yflip = '0' then + ctl_o.a(3 downto 0) <= std_logic_vector(row(3 downto 0)); + else + ctl_o.a(3 downto 0) <= not std_logic_vector(row(3 downto 0)); + end if; + + end process; + +end architecture SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spritereg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spritereg.vhd new file mode 100644 index 00000000..d7c3714b --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/spritereg.vhd @@ -0,0 +1,60 @@ +Library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.sprite_pkg.all; + +entity sptReg is + + generic + ( + INDEX : natural + ); + port + ( + reg_i : in to_SPRITE_REG_t; + reg_o : out from_SPRITE_REG_t + ); + +end sptReg; + +architecture SYN of sptReg is + + alias clk : std_logic is reg_i.clk; + alias clk_ena : std_logic is reg_i.clk_ena; + +begin + + process (clk, clk_ena) + begin + if rising_edge(clk) and clk_ena = '1' then + if reg_i.a(7 downto 2) = std_logic_vector(to_unsigned(INDEX, 6)) then + if reg_i.wr = '1' then + case reg_i.a(1 downto 0) is + when "00" => + reg_o.y(7 downto 0) <= reg_i.d; + when "01" => + -- actually only 32 colours, but encoded as 64??? + reg_o.colour(5 downto 0) <= reg_i.d(5 downto 0); + reg_o.xflip <= reg_i.d(6); + reg_o.yflip <= reg_i.d(7); + when "10" => + -- 128 sprite tiles + reg_o.n(6 downto 0) <= reg_i.d(6 downto 0); + when others => + reg_o.x(7 downto 0) <= reg_i.d; + end case; + end if; -- reg_i.wr='1' + end if; -- reg_i.a()=INDEX + end if; + end process; + + reg_o.x(reg_o.x'left downto 8) <= (others => '0'); + reg_o.y(reg_o.y'left downto 8) <= (others => '0'); + reg_o.n(reg_o.n'left downto 7) <= (others => '0'); + reg_o.colour(reg_o.colour'left downto 6) <= (others => '0'); + reg_o.pri <= '1'; + +end SYN; + diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprom.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprom.vhd new file mode 100644 index 00000000..292a214f --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/sprom.vhd @@ -0,0 +1,83 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + init_file : string := ""; + --numwords_a : natural; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END sprom; + + +ARCHITECTURE SYN OF sprom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80.vhd new file mode 100644 index 00000000..1ea66542 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80.vhd @@ -0,0 +1,1088 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if Mode = 3 then + IStatus <= "10"; + elsif IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusA <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_ALU.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_MCode.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_MCode.vhd new file mode 100644 index 00000000..198dac66 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_MCode.vhd @@ -0,0 +1,2024 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + --I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + if mode = 3 then + MCycles <= "011"; + else + MCycles <= "101"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_Pack.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_Pack.vhd new file mode 100644 index 00000000..907db408 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_Pack.vhd @@ -0,0 +1,228 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_Reg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_Reg.vhd new file mode 100644 index 00000000..1c0f2638 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80se.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80se.vhd new file mode 100644 index 00000000..1b0cb9b5 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/T80se.vhd @@ -0,0 +1,192 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0240 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/Z80.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/Z80.vhd new file mode 100644 index 00000000..db1ad947 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/t80/Z80.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.T80_Pack.all; + +entity Z80 is port + ( + clk : in std_logic; + clk_en : in std_logic; + reset : in std_logic; + + addr : out std_logic_vector(15 downto 0); + datai : in std_logic_vector(7 downto 0); + datao : out std_logic_vector(7 downto 0); + + m1 : out std_logic; + mem_rd : out std_logic; + mem_wr : out std_logic; + io_rd : out std_logic; + io_wr : out std_logic; + + wait_n : in std_logic := '1'; + busrq_n : in std_logic := '1'; + intreq : in std_logic := '0'; + intvec : in std_logic_vector(7 downto 0); + intack : out std_logic; + nmi : in std_logic := '0' + ); +end Z80; + +architecture SYN of Z80 is + + component T80se is + generic + ( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port + ( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); + end component T80se; + + -- Signal Declarations + + signal reset_n : std_logic; + signal int_n : std_logic; + signal nmi_n : std_logic; + + signal z80_m1 : std_logic; + signal z80_memreq : std_logic; + signal z80_ioreq : std_logic; + signal z80_rd : std_logic; + signal z80_wr : std_logic; + signal z80_datai : std_logic_vector(7 downto 0); + + -- derived signals (outputs we need to read) + signal z80_memrd : std_logic; + signal z80_iord : std_logic; + signal fetch : std_logic; + + begin + + -- simple inversions + reset_n <= not reset; + int_n <= not intreq; + nmi_n <= not nmi; + + -- direct-connect (outputs we need to read) + m1 <= z80_m1; + mem_rd <= z80_memrd; + io_rd <= z80_iord; + + -- memory signals + z80_memrd <= z80_memreq nor z80_rd; + mem_wr <= z80_memreq nor z80_wr; + + -- io signals + z80_iord <= z80_ioreq nor z80_rd; + io_wr <= z80_ioreq nor z80_wr; + + -- other signals + fetch <= z80_m1 nor z80_memreq; + intack <= z80_m1 nor z80_ioreq; + + -- data in mux + z80_datai <= intvec when ((z80_memrd or z80_iord) = '0') else + datai; + + Z80_uP : T80se + generic map + ( + Mode => 0 -- Z80 + ) + port map + ( + RESET_n => reset_n, + CLK_n => clk, + CLKEN => clk_en, + WAIT_n => wait_n, + INT_n => int_n, + NMI_n => nmi_n, + BUSRQ_n => busrq_n, + M1_n => z80_m1, + MREQ_n => z80_memreq, + IORQ_n => z80_ioreq, + RD_n => z80_rd, + WR_n => z80_wr, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => addr, + DI => z80_datai, + DO => datao + ); + +end architecture SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/target_pkg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/target_pkg.vhd new file mode 100644 index 00000000..0ff511e1 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/target_pkg.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; + +package target_pkg is + + -- + -- PACE constants which *MUST* be defined + -- +constant PACE_TARGET : PACETargetType := PACE_TARGET_MIST; +constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA; +constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3; + +constant PACE_CLKIN0 : natural := 27; +constant PACE_HAS_SPI : boolean := false; + + -- + -- DE1-specific constants + -- + type from_TARGET_IO_t is record + not_used : std_logic; + end record; + + type to_TARGET_IO_t is record + not_used : std_logic; + end record; + + end; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd new file mode 100644 index 00000000..42e2c180 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/tilemapctl.vhd @@ -0,0 +1,131 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; +use work.video_controller_pkg.all; + +-- +-- Galaxian Tilemap Controller +-- +-- Tile data is 2 BPP. +-- + +entity TILEMAP_1 is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- tilemap controller signals + ctl_i : in to_TILEMAP_CTL_t; + ctl_o : out from_TILEMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity TILEMAP_1; + +architecture tile1 of TILEMAP_1 is + + alias clk : std_logic is video_ctl.clk; + alias clk_ena : std_logic is video_ctl.clk_ena; + alias stb : std_logic is video_ctl.stb; + alias hblank : std_logic is video_ctl.hblank; + alias vblank : std_logic is video_ctl.vblank; + + signal x : std_logic_vector(video_ctl.x'range); + signal y : std_logic_vector(video_ctl.y'range); + + alias rot_en : std_logic is graphics_i.bit8(0)(0); + alias scroll : std_logic_vector(7 downto 0) is graphics_i.bit8(1); + +begin + + -- not used + ctl_o.map_a(ctl_o.map_a'left downto 10) <= (others => '0'); + ctl_o.attr_a(ctl_o.attr_a'left downto 10) <= (others => '0'); + ctl_o.tile_a(ctl_o.tile_a'left downto 12) <= (others => '0'); + + -- screen rotation + x <= video_ctl.x when unsigned(y) < 192 else + std_logic_vector(unsigned(video_ctl.x) + not unsigned(scroll)); + -- when rot_en = '0' else not video_ctl.y; + --y <= not video_ctl.y when rot_en = '0' else 32 + video_ctl.x; + y <= video_ctl.y; -- when rot_en = '0' else video_ctl.x; + + -- generate pixel + process (clk, clk_ena) + + variable tile_d_r : std_logic_vector(15 downto 0); + variable attr_d_r : std_logic_vector(7 downto 0); + variable pel : std_logic_vector(1 downto 0); + variable pal_i : std_logic_vector(6 downto 0); + variable pal_rgb : pal_rgb_t; + + begin + + if rising_edge(clk) then + if clk_ena = '1' then + + -- 1st stage of pipeline + -- - set tilemap, attribute address + ctl_o.map_a(9 downto 5) <= y(7 downto 3); + ctl_o.map_a(4 downto 0) <= x(7 downto 3); + ctl_o.attr_a(9 downto 5) <= y(7 downto 3); + ctl_o.attr_a(4 downto 0) <= x(7 downto 3); + + -- 2nd stage of pipeline + -- - set tile address + if x(2 downto 0) = "010" then + ctl_o.tile_a(11) <= ctl_i.attr_d(7); + ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0); + ctl_o.tile_a(2 downto 0) <= y(2 downto 0); + + end if; + + -- 3rd stage of pipeline + -- - read tile, attribute data from ROM + if x(2 downto 0) = "100" then + tile_d_r := ctl_i.tile_d(tile_d_r'range); + attr_d_r := ctl_i.attr_d(7 downto 0); + elsif stb = '1' then + tile_d_r := tile_d_r(tile_d_r'left-1 downto 0) & '0'; + end if; + + -- extract R,G,B from colour palette + -- MAME says there are 512 palette entries + -- although the code uses 6 bits of colour only + -- the highest colour in the PROM is 83 + -- so we're going with 128 (5+2 bits) + pel := tile_d_r(tile_d_r'left) & tile_d_r(tile_d_r'left-8); + pal_i := attr_d_r(4 downto 0) & pel; + pal_rgb := tile_pal(to_integer(unsigned(pal_i))); + ctl_o.rgb.r <= pal_rgb(0) & "00"; + ctl_o.rgb.g <= pal_rgb(1) & "00"; + ctl_o.rgb.b <= pal_rgb(2) & "00"; + ctl_o.set <= '0'; -- default + -- lines 0-6 are opaque apparently + if unsigned(y) < 7*8 or + pel /= "00" then +-- pal_rgb(0)(7 downto 5) /= "000" or +-- pal_rgb(1)(7 downto 5) /= "000" or +-- pal_rgb(2)(7 downto 5) /= "000" then + if graphics_i.bit8(0)(3) = '1' then + ctl_o.set <= '1'; + end if; + end if; + + end if; -- clk_ena + end if; -- rising_edge_clk + + end process; + +end architecture tile1; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd new file mode 100644 index 00000000..155afc5a --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller.vhd @@ -0,0 +1,456 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.video_controller_pkg.all; + +entity pace_video_controller is + generic + ( + CONFIG : PACEVideoController_t := PACE_VIDEO_NONE; + DELAY : integer := 1; + H_SIZE : integer; + V_SIZE : integer; + L_CROP : integer range 0 to 255; + R_CROP : integer range 0 to 255; + H_SCALE : integer; + V_SCALE : integer; + H_SYNC_POL : std_logic := '1'; + V_SYNC_POL : std_logic := '1'; + BORDER_RGB : RGB_t := RGB_BLACK + ); + port + ( + -- clocking etc + video_i : in from_VIDEO_t; + + -- register interface + reg_i : in VIDEO_REG_t; + + -- video input data + rgb_i : in RGB_t; + + -- control signals (out) + video_ctl_o : out from_VIDEO_CTL_t; + + -- video output control & data + video_o : out to_VIDEO_t + ); +end pace_video_controller; + +architecture SYN of pace_video_controller is + + constant SIM_DELAY : time := 2 ns; + + constant VIDEO_H_SIZE : integer := H_SIZE * H_SCALE; + constant VIDEO_V_SIZE : integer := V_SIZE * V_SCALE; + + subtype reg_t is integer range 0 to 2047; + + alias clk : std_logic is video_i.clk; + alias clk_ena : std_logic is video_i.clk_ena; + alias reset : std_logic is video_i.reset; + + -- registers + signal h_front_porch_r : reg_t := 0; + signal h_sync_r : reg_t := 0; + signal h_back_porch_r : reg_t := 0; + signal h_border_r : reg_t := 0; + signal h_video_r : reg_t := 0; + signal v_front_porch_r : reg_t := 0; + signal v_sync_r : reg_t := 0; + signal v_back_porch_r : reg_t := 0; + signal v_border_r : reg_t := 0; + signal v_video_r : reg_t := 0; + + signal border_rgb_r : RGB_t := ((others=>'0'), (others=>'0'), (others=>'0')); + + -- derived values + signal h_sync_start : reg_t := 0; + signal h_back_porch_start : reg_t := 0; + signal h_left_border_start : reg_t := 0; + signal h_video_start : reg_t := 0; + signal h_right_border_start : reg_t := 0; + signal h_line_end : reg_t := 0; + signal v_sync_start : reg_t := 0; + signal v_back_porch_start : reg_t := 0; + signal v_top_border_start : reg_t := 0; + signal v_video_start : reg_t := 0; + signal v_bottom_border_start : reg_t := 0; + signal v_screen_end : reg_t := 0; + + signal hsync_s : std_logic := '0'; + signal vsync_s : std_logic := '0'; + signal hactive_s : std_logic := '0'; + signal vactive_s : std_logic := '0'; + signal hblank_s : std_logic := '0'; + signal vblank_s : std_logic := '0'; + + subtype count_t is integer range 0 to 2047; + signal x_count : count_t := 0; + signal y_count : count_t := 0; + + signal x_s : unsigned(10 downto 0) := (others => '0'); + signal y_s : unsigned(10 downto 0) := (others => '0'); + + --signal extended_reset : std_logic := '1'; + alias extended_reset : std_logic is video_i.reset; + +begin + + -- registers + reg_proc: process (reset, clk) + + begin + --if reset = '1' then + case CONFIG is + + when PACE_VIDEO_VGA_240x320_60Hz => + -- P3M, clk=11.136MHz, clk_ena=5.568MHz + h_front_porch_r <= 272-240; + h_sync_r <= 5; + h_back_porch_r <= 22; + h_border_r <= (240-VIDEO_H_SIZE)/2; + v_front_porch_r <= 326-320; + v_sync_r <= 1; + v_back_porch_r <= 5; + v_border_r <= (320-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_320x480_60Hz => + -- VGA, clk=12.588MHz + --# 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio + --Modeline "320x240" 12.588 320 336 384 400 240 245 246 262 Doublescan + h_front_porch_r <= 16; + h_sync_r <= 48; + h_back_porch_r <= 16; + h_border_r <= (320-VIDEO_H_SIZE)/2; + v_front_porch_r <= (5*2); + v_sync_r <= (1*2); + v_back_porch_r <= (16*2); + v_border_r <= (480-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_640x480_60Hz => + -- VGA, clk=25.175MHz + h_front_porch_r <= 16; + h_sync_r <= 96; + h_back_porch_r <= 48; + h_border_r <= (640-VIDEO_H_SIZE)/2; + v_front_porch_r <= 10; + v_sync_r <= 2; + v_back_porch_r <= 33; + v_border_r <= (480-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_800x600_60Hz => + -- SVGA, clk=40MHz + h_front_porch_r <= 40; + h_sync_r <= 128; + h_back_porch_r <= 88; + h_border_r <= (800-VIDEO_H_SIZE)/2; + v_front_porch_r <= 1; + v_sync_r <= 4; + v_back_porch_r <= 23; + v_border_r <= (600-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1024x768_60Hz => + -- XVGA, clk=65MHz + h_front_porch_r <= 24; + h_sync_r <= 136; + h_back_porch_r <= 160; + h_border_r <= (1024-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 6; + v_back_porch_r <= 29; + v_border_r <= (768-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1366x768_60Hz => + -- XVGA(NAVICO ROCKY), clk=72MHz + h_front_porch_r <= 88; --64; + h_sync_r <= 44; --112; + h_back_porch_r <= 148; --248; + h_border_r <= (1366-VIDEO_H_SIZE)/2; + v_front_porch_r <= 4; --3; + v_sync_r <= 5; --6; + v_back_porch_r <= 36; --18; + v_border_r <= (768-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1280x800_60Hz => + -- Sentinel Mode 36, clk=103.2MHz + h_front_porch_r <= 64; + h_sync_r <= 32; + h_back_porch_r <= 362-32-64; + h_border_r <= (1280-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 4; + v_back_porch_r <= 38-4-3; + v_border_r <= (800-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1280x1024_60Hz => + -- SXGA, clk=108MHz + h_front_porch_r <= 48; + h_sync_r <= 112; + h_back_porch_r <= 248; + h_border_r <= (1280-VIDEO_H_SIZE)/2; + v_front_porch_r <= 1; + v_sync_r <= 3; + v_back_porch_r <= 38; + v_border_r <= (1024-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1680x1050_60Hz => + -- WSXGA+, clk=147.14MHz + h_front_porch_r <= 104; + h_sync_r <= 184; + h_back_porch_r <= 288; + v_front_porch_r <= 1; + v_sync_r <= 3; + v_back_porch_r <= 33; + -- WSXGA+, clk=118MHz + --h_front_porch_r <= 48; + --h_sync_r <= 32; + --h_back_porch_r <= 80; + --v_front_porch_r <= 3; + --v_sync_r <= 6; + --v_back_porch_r <= 21; + h_border_r <= (1680-VIDEO_H_SIZE)/2; + v_border_r <= (1050-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_ARCADE_STD_336x240_60Hz => + -- arcade standard resolution, clk=7.16MHz + h_front_porch_r <= 34; + h_sync_r <= 34; + h_back_porch_r <= 51; + h_border_r <= (336-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 3; + v_back_porch_r <= 16; + v_border_r <= (240-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64 => + -- arcade standard resolution, clk=28.64MHz + h_front_porch_r <= 4*34; + h_sync_r <= 4*34; + h_back_porch_r <= 4*51; + h_border_r <= 4*(336-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 3; + v_back_porch_r <= 16; + v_border_r <= (240-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_CVBS_720x288p_50Hz => + -- generic composite, clk=13.5MHz + h_front_porch_r <= (8+12); + h_sync_r <= 64; + h_back_porch_r <= (144-64-(8+12)); + h_border_r <= (720-VIDEO_H_SIZE)/2; + v_front_porch_r <= 1; + v_sync_r <= 3; + v_back_porch_r <= 20; + v_border_r <= (288-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_LCM_320x240_60Hz => + -- DE1/2, clk=18MHz + h_front_porch_r <= 59; + h_sync_r <= 1; + h_back_porch_r <= 151; + h_border_r <= (320-VIDEO_H_SIZE)*3/2; + v_front_porch_r <= 8; + v_sync_r <= 1; + v_back_porch_r <= 13; + v_border_r <= (240-VIDEO_V_SIZE)/2; + + when others => + null; + end case; + + h_video_r <= VIDEO_H_SIZE; + v_video_r <= VIDEO_V_SIZE; + border_rgb_r <= BORDER_RGB; + + --end if; + end process reg_proc; + + -- register some arithmetic + init_proc: process (reset, clk, clk_ena) + begin + if reset = '1' then + null; + elsif rising_edge(clk) then + h_sync_start <= h_front_porch_r - 1; + h_back_porch_start <= h_sync_start + h_sync_r; + h_left_border_start <= h_back_porch_start + h_back_porch_r; + h_video_start <= h_left_border_start + h_border_r; + h_right_border_start <= h_video_start + h_video_r; + h_line_end <= h_right_border_start + h_border_r; + v_sync_start <= v_front_porch_r - 1; + v_back_porch_start <= v_sync_start + v_sync_r; + v_top_border_start <= v_back_porch_start + v_back_porch_r; + v_video_start <= v_top_border_start + v_border_r; + v_bottom_border_start <= v_video_start + v_video_r; + v_screen_end <= v_bottom_border_start + v_border_r; + end if; + end process init_proc; + + reset_proc: process (reset, clk) + variable count_v : integer; + begin + if reset = '1' then + --extended_reset <= '1'; + count_v := 7; + elsif rising_edge(clk) then + if count_v = 0 then + --extended_reset <= '0'; + else + count_v := count_v - 1; + end if; + end if; + end process reset_proc; + + -- video control outputs + timer_proc: process (extended_reset, clk, clk_ena) + begin + if extended_reset = '1' then + hblank_s <= '1'; + vblank_s <= '1'; + hactive_s <= '0'; + vactive_s <= '0'; + hsync_s <= not H_SYNC_POL; + x_count <= 0; + y_count <= 0; + elsif rising_edge(clk) and clk_ena = '1' then + if x_count = h_line_end then + hblank_s <= '1'; + hactive_s <= '0'; -- for 0 borders + if y_count = v_screen_end then + vblank_s <= '1'; + vactive_s <= '0'; -- for 0 borders + y_count <= 0; + else + y_s <= y_s + 1; + if y_count = v_sync_start then + vsync_s <= V_SYNC_POL; + elsif y_count = v_back_porch_start then + vsync_s <= not V_SYNC_POL; + elsif y_count = v_video_start then + vblank_s <= '0'; -- for 0 borders + vactive_s <= '1'; + y_s <= (others => '0'); + -- check the borders last in case they're 0 + elsif y_count = v_top_border_start then + vblank_s <= '0'; + elsif y_count = v_bottom_border_start then + vactive_s <= '0'; + end if; + y_count <= y_count + 1; + end if; + x_count <= 0; + else + x_s <= x_s + 1; + if x_count = h_sync_start then + hsync_s <= H_SYNC_POL; + elsif x_count = h_back_porch_start then + hsync_s <= not H_SYNC_POL; + elsif x_count = h_video_start then + hblank_s <= '0'; -- for 0 borders + hactive_s <= '1'; + x_s <= (others => '0'); + -- check the borders last in case they're 0 + elsif x_count = h_left_border_start then + hblank_s <= '0'; + elsif x_count = h_right_border_start then + hactive_s <= '0'; + end if; + x_count <= x_count + 1; + end if; + end if; -- rising_edge(clk) and clk_ena = '1' + end process timer_proc; + + -- pass-through for tile/bitmap & sprite controllers + video_ctl_o.clk <= clk; + video_ctl_o.clk_ena <= clk_ena; + + -- for video DACs and TFT output + video_o.clk <= clk; + + BLK_VIDEO_O : block + + constant PIPELINE_DELAY : natural := DELAY+1; + + -- won't synthesize correctly under ISE if these are variables + signal hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + signal vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + + begin + + video_o_proc: process (extended_reset, clk, clk_ena) + variable hsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + variable vsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + --variable hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + --variable vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + variable hblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + variable vblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + alias hsync_v : std_logic is hsync_v_r(hsync_v_r'left); + alias vsync_v : std_logic is vsync_v_r(vsync_v_r'left); + alias hactive_v : std_logic is hactive_v_r(hactive_v_r'left); + alias vactive_v : std_logic is vactive_v_r(vactive_v_r'left); + alias hblank_v : std_logic is hblank_v_r(hblank_v_r'left); + alias vblank_v : std_logic is vblank_v_r(vblank_v_r'left); + variable stb_cnt_v : unsigned(3 downto 0); -- up to 16x scaling + begin + if extended_reset = '1' then + hsync_v_r := (others => not H_SYNC_POL); + vsync_v_r := (others => not V_SYNC_POL); + hactive_v_r <= (others => '0'); + vactive_v_r <= (others => '0'); + hblank_v_r := (others => '0'); + vblank_v_r := (others => '0'); + stb_cnt_v := (others => '1'); + elsif rising_edge(clk) and clk_ena = '1' then + + -- register control signals and handle scaling + video_ctl_o.hblank <= not hactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers + video_ctl_o.vblank <= not vactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers + -- handle scaling + video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY; + if hactive_s = '1' and vactive_s = '1' then + stb_cnt_v := stb_cnt_v + 2; + elsif hblank_s = '0' and vblank_s = '0' then + stb_cnt_v := (others => '1'); + end if; + video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY; + video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY; + + -- register video outputs + if hactive_v = '1' and vactive_v = '1' then + -- active video + if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or + x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then + video_o.rgb <= RGB_BLACK after SIM_DELAY; + else + video_o.rgb <= rgb_i after SIM_DELAY; + end if; + elsif hblank_v = '0' and vblank_v = '0' then + -- border + video_o.rgb <= border_rgb_r after SIM_DELAY; + else + video_o.rgb.r <= (others => '0') after SIM_DELAY; + video_o.rgb.g <= (others => '0') after SIM_DELAY; + video_o.rgb.b <= (others => '0') after SIM_DELAY; + end if; + video_o.hsync <= hsync_v after SIM_DELAY; + video_o.vsync <= vsync_v after SIM_DELAY; + video_o.hblank <= hblank_v after SIM_DELAY; + video_o.vblank <= vblank_v after SIM_DELAY; + -- pipelined signals + hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s; + vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s; + hactive_v_r <= hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s; + vactive_v_r <= vactive_v_r(vactive_v_r'left-1 downto 0) & vactive_s; + hblank_v_r := hblank_v_r(hblank_v_r'left-1 downto 0) & hblank_s; + vblank_v_r := vblank_v_r(vblank_v_r'left-1 downto 0) & vblank_s; + end if; + end process video_o_proc; + + end block BLK_VIDEO_O; + +end SYN; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd new file mode 100644 index 00000000..183bfe23 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg.vhd @@ -0,0 +1,229 @@ +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.numeric_std.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +package video_controller_pkg is + + type PACEVideoController_t is + ( + PACE_VIDEO_NONE, -- PACE video controller not used + PACE_VIDEO_VGA_240x320_60Hz, -- P3M video + PACE_VIDEO_VGA_320x480_60Hz, -- for 320x200 (12.588MHz) + PACE_VIDEO_VGA_640x480_60Hz, -- generic VGA (25.175MHz) + PACE_VIDEO_VGA_800x600_60Hz, -- generic VGA (40MHz) + PACE_VIDEO_VGA_1024x768_60Hz, -- XVGA (65MHz) + PACE_VIDEO_VGA_1366x768_60Hz, -- (NAVICO ROCKY) (72MHz) + PACE_VIDEO_VGA_1280x800_60Hz, -- Sentinel Mode 36 + PACE_VIDEO_VGA_1280x1024_60Hz, -- SXGA (108MHz) + PACE_VIDEO_VGA_1680x1050_60Hz, -- WSXGA+ (147MHz) + PACE_VIDEO_ARCADE_STD_336x240_60Hz, -- arcade std resolution (7.16MHz) + PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64, -- arcade std resolution (28.64MHz) + PACE_VIDEO_CVBS_720x288p_50Hz, -- generic composite + PACE_VIDEO_LCM_320x240_60Hz -- DE2 LCD + ); + + type PACEVideoDisplay_t is + ( + PACE_DISPLAY_NONE, + PACE_DISPLAY_VGA, + PACE_DISPLAY_CVBS, + PACE_DISPLAY_TFT + ); + + type RGB_t is record + r : std_logic_vector(9 downto 0); + g : std_logic_vector(9 downto 0); + b : std_logic_vector(9 downto 0); + end record; + + type RGB_a is array (natural range <>) of RGB_t; + + function NULL_RGB return RGB_t; + + constant RGB_BLACK : RGB_t := ((others=>'0'),(others=>'0'),(others=>'0')); + constant RGB_RED : RGB_t := ((others=>'1'),(others=>'0'),(others=>'0')); + constant RGB_GREEN : RGB_t := ((others=>'0'),(others=>'1'),(others=>'0')); + constant RGB_YELLOW : RGB_t := ((others=>'1'),(others=>'1'),(others=>'0')); + constant RGB_BLUE : RGB_t := ((others=>'0'),(others=>'0'),(others=>'1')); + constant RGB_MAGENTA : RGB_t := ((others=>'1'),(others=>'0'),(others=>'1')); + constant RGB_CYAN : RGB_t := ((others=>'0'),(others=>'1'),(others=>'1')); + constant RGB_WHITE : RGB_t := ((others=>'1'),(others=>'1'),(others=>'1')); + + type VIDEO_REG_t is record + h_scale : std_logic_vector(2 downto 0); + v_scale : std_logic_vector(2 downto 0); + end record; + + type from_VIDEO_t is record + clk : std_logic; + clk_ena : std_logic; + reset : std_logic; + end record; + + type to_VIDEO_t is record + clk : std_logic; + rgb : rgb_t; + hsync : std_logic; + vsync : std_logic; + hblank : std_logic; + vblank : std_logic; + de : std_logic; + end record; + + type from_VIDEO_CTL_t is record + clk : std_logic; + clk_ena : std_logic; + stb : std_logic; + hblank : std_logic; + vblank : std_logic; + x : std_logic_vector(10 downto 0); + y : std_logic_vector(10 downto 0); + end record; + + subtype BITMAP_D_t is std_logic_vector(23 downto 0); + subtype BITMAP_A_t is std_logic_vector(15 downto 0); + + type to_BITMAP_CTL_t is record + d : BITMAP_D_t; + end record; + + type to_BITMAP_CTL_a is array (natural range <>) of to_BITMAP_CTL_t; + + function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t; + + type from_BITMAP_CTL_t is record + a : BITMAP_A_t; + rgb : RGB_t; + set : std_logic; + end record; + + type from_BITMAP_CTL_a is array (natural range <>) of from_BITMAP_CTL_t; + + subtype TILEMAP_D_t is std_logic_vector(15 downto 0); + subtype TILEMAP_A_t is std_logic_vector(15 downto 0); + subtype TILE_A_t is std_logic_vector(16 downto 0); + subtype TILE_D_t is std_logic_vector(23 downto 0); + subtype ATTR_A_t is std_logic_vector(15 downto 0); + subtype ATTR_D_t is std_logic_vector(15 downto 0); + + type to_TILEMAP_CTL_t is record + map_d : TILEMAP_D_t; + tile_d : TILE_D_t; + attr_d : ATTR_D_t; + end record; + + type to_TILEMAP_CTL_a is array (natural range <>) of to_TILEMAP_CTL_t; + + function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t; + + type from_TILEMAP_CTL_t is record + map_a : TILEMAP_A_t; + tile_a : TILE_A_t; + attr_a : ATTR_A_t; + rgb : RGB_t; + set : std_logic; + end record; + + type from_TILEMAP_CTL_a is array (natural range <>) of from_TILEMAP_CTL_t; + + subtype PAL_ENTRY_t is std_logic_vector(15 downto 0); + type PAL_A_t is array (natural range <>) of PAL_ENTRY_t; + + subtype BYTE_t is std_logic_vector(7 downto 0); + type BYTE_A_t is array (natural range <>) of BYTE_t; + + subtype WORD_t is std_logic_vector(15 downto 0); + type WORD_A_t is array (natural range <>) of WORD_t; + + type to_GRAPHICS_t is record + pal : PAL_A_t(0 to 15); + -- for various uses + bit8 : BYTE_A_t(0 to 7); + bit16 : WORD_A_t(0 to 3); + -- 'native' graphics stream + hsync : std_logic; + vsync : std_logic; + rgb : RGB_t; + end record; + + function NULL_TO_GRAPHICS return to_GRAPHICS_t; + + type from_GRAPHICS_t is record + y : std_logic_vector(10 downto 0); + hblank : std_logic; + vblank : std_logic; + end record; + + component pace_video_controller is + generic + ( + CONFIG : PACEVideoController_t := PACE_VIDEO_NONE; + DELAY : integer := 1; + H_SIZE : integer; + V_SIZE : integer; + --H_SCALE : integer; + --V_SCALE : integer; + BORDER_RGB : RGB_t := RGB_BLACK + ); + port + ( + -- clocking etc + video_i : in from_VIDEO_t; + + -- register interface + reg_i : in VIDEO_REG_t; + + -- video input data + rgb_i : in RGB_t; + + -- control signals (out) + video_ctl_o : from_VIDEO_CTL_t; + + -- Outputs to video + video_o : out to_VIDEO_t + ); + end component pace_video_controller; + + component tilemapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- tilemap controller signals + ctl_i : in to_TILEMAP_CTL_t; + ctl_o : out from_TILEMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); + end component tilemapCtl; + + component bitmapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); + end component bitmapCtl; + +end package video_controller_pkg; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg_body.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg_body.vhd new file mode 100644 index 00000000..996e5867 --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_controller_pkg_body.vhd @@ -0,0 +1,29 @@ +library work; +--use work.pace_pkg.all; + +package body video_controller_pkg is + + function NULL_RGB return RGB_t is + begin + return (others => (others => '0')); + end NULL_RGB; + + function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t is + begin + return (others => (others => '0')); + end NULL_TO_BITMAP_CTL; + + function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t is + begin + return ((others => '0'), (others => '0'), (others => '0')); + end NULL_TO_TILEMAP_CTL; + + function NULL_TO_GRAPHICS return to_GRAPHICS_t is + begin + return ((others => (others => '0')), + (others => (others => '0')), + (others => (others => '0')), + '0', '0', NULL_RGB); + end NULL_TO_GRAPHICS; + +end package body video_controller_pkg; diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_mist.sv b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_mist.sv new file mode 100644 index 00000000..fb9e499a --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_mist.sv @@ -0,0 +1,233 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mist +/*#( + parameter LINE_LENGTH = 256, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +)*/ +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scan_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [5:0] R, + input [5:0] G, + input [5:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +wire [5:0] R_sd; +wire [5:0] G_sd; +wire [5:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(800), .HALF_DEPTH(0)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [5:0] rt = (scan_disable ? R : R_sd); +wire [5:0] gt = (scan_disable ? G : G_sd); +wire [5:0] bt = (scan_disable ? B : B_sd); + + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + + +wire hs = (scan_disable ? HSync : hs_sd); +wire vs = (scan_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(10'd0, 10'd0, 3'd4) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scan_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scan_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd new file mode 100644 index 00000000..ab2cccaf --- /dev/null +++ b/Arcade/IremM52 Hardware/MoonPatrol_MIST/src/video_mixer.vhd @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +--use work.platform_pkg.all; + +entity pace_video_mixer is + port + ( + --bitmap_rgb : in RGB_t; + --bitmap_set : in std_logic; + bitmap_ctl_o : in from_BITMAP_CTL_a(1 to 3); + tilemap_ctl_o : in from_TILEMAP_CTL_a(1 to 1); + sprite_rgb : in RGB_t; + sprite_set : in std_logic; + sprite_pri : in std_logic; + + video_ctl_i : in from_VIDEO_CTL_t; + graphics_i : in to_GRAPHICS_t; + rgb_o : out RGB_t + ); +end entity pace_video_mixer; + +architecture SYN of pace_video_mixer is + signal bg_rgb : RGB_t; +begin + + bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else + bitmap_ctl_o(2).rgb when bitmap_ctl_o(2).set = '1' else + bitmap_ctl_o(3).rgb when bitmap_ctl_o(3).set = '1' else + (others => (others => '0')); + + + rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else + tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else + sprite_rgb when sprite_set = '1' else + bg_rgb; + +end architecture SYN; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/clean.bat b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/pooyan_mist.qpf b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/pooyan_mist.qpf new file mode 100644 index 00000000..f6253900 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/pooyan_mist.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 11:17:10 October 25, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "11:17:10 October 25, 2017" + +# Revisions + +PROJECT_REVISION = "pooyan_mist" diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/pooyan_mist.qsf b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/pooyan_mist.qsf new file mode 100644 index 00000000..c0acdee6 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/pooyan_mist.qsf @@ -0,0 +1,162 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:18:08 November 05, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# pooyan_mist_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name TOP_LEVEL_ENTITY pooyan_mist + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" + +# Fitter Assignments +# ================== +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + + + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 + + + +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE rtl/pooyan_mist.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sprite_grphx2.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sprite_grphx1.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sprite_color_lut.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sound_prog.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_prog.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_palette.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_char_grphx2.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_char_grphx1.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_char_color_lut.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80se.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name QIP_FILE rtl/mist_pll_12M_14M.qip +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name VHDL_FILE rtl/gen_video.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/pooyan_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/pooyan.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/DebugSystem.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/DebugSystem.vhd new file mode 100644 index 00000000..27f115c9 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/DebugSystem.vhd @@ -0,0 +1,197 @@ +-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs +-- that can be synthesized and used with +-- the NoICE debugger that can be found at +-- http://www.noicedebugger.com/ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity DebugSystem is + port( + Reset_n : in std_logic; + Clk : in std_logic; + NMI_n : in std_logic; + RXD0 : in std_logic; + CTS0 : in std_logic; + DSR0 : in std_logic; + RI0 : in std_logic; + DCD0 : in std_logic; + RXD1 : in std_logic; + CTS1 : in std_logic; + DSR1 : in std_logic; + RI1 : in std_logic; + DCD1 : in std_logic; + TXD0 : out std_logic; + RTS0 : out std_logic; + DTR0 : out std_logic; + TXD1 : out std_logic; + RTS1 : out std_logic; + DTR1 : out std_logic; +As : out std_logic_vector(15 downto 0); +Ds : out std_logic_vector(7 downto 0); +ROM_Ds : out std_logic_vector(7 downto 0) + ); +end DebugSystem; + +architecture struct of DebugSystem is + + signal M1_n : std_logic; + signal MREQ_n : std_logic; + signal IORQ_n : std_logic; + signal RD_n : std_logic; + signal WR_n : std_logic; + signal RFSH_n : std_logic; + signal HALT_n : std_logic; + signal WAIT_n : std_logic; + signal INT_n : std_logic; + signal RESET_s : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal A : std_logic_vector(15 downto 0); + signal D : std_logic_vector(7 downto 0); + signal ROM_D : std_logic_vector(7 downto 0); + signal SRAM_D : std_logic_vector(7 downto 0); + signal UART0_D : std_logic_vector(7 downto 0); + signal UART1_D : std_logic_vector(7 downto 0); + signal CPU_D : std_logic_vector(7 downto 0); + + signal Mirror : std_logic; + + signal IOWR_n : std_logic; + signal RAMCS_n : std_logic; + signal UART0CS_n : std_logic; + signal UART1CS_n : std_logic; + + signal BaudOut0 : std_logic; + signal BaudOut1 : std_logic; + +begin + As <= A; + Ds <= D; + ROM_Ds <= ROM_D; + + Wait_n <= '1'; + BusRq_n <= '1'; + INT_n <= '1'; + + process (Reset_n, Clk) + begin + if Reset_n = '0' then + Reset_s <= '0'; + Mirror <= '0'; + elsif Clk'event and Clk = '1' then + Reset_s <= '1'; + if IORQ_n = '0' and A(7 downto 4) = "1111" then + Mirror <= D(0); + end if; + end if; + end process; + + IOWR_n <= WR_n or IORQ_n; + RAMCS_n <= (not Mirror and not A(15)) or MREQ_n; + UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1'; + UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1'; + +-- CPU_D <= +-- SRAM_D when RAMCS_n = '0' else +-- UART0_D when UART0CS_n = '0' else +-- UART1_D when UART1CS_n = '0' else +-- ROM_D; + + CPU_D <= + ROM_D; + + u0 : entity work.T80s + generic map(Mode => 0, T2Write => 1, IOWait => 0) +-- generic map(Mode => 1, T2Write => 1, IOWait => 0) + port map( + RESET_n => RESET_s, + CLK_n => Clk, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + RD_n => RD_n, + WR_n => WR_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + A => A, + DI => CPU_D, + DO => D); + + -- u1 : entity work.MonZ80 + -- port map( + -- Clk => Clk, + -- A => A(10 downto 0), + -- D => ROM_D); + + u1 : entity work.bagmanrom + port map( + clock => not Clk, + address => A(14 downto 0), + q => ROM_D); + + u2 : entity work.SSRAM + generic map( + AddrWidth => 12) + port map( + Clk => Clk, + CE_n => RAMCS_n, + WE_n => WR_n, + A => A(11 downto 0), + DIn => D, + DOut => SRAM_D); + + u3 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut0, + CS_n => UART0CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A(2 downto 0), + D_In => D, + D_Out => UART0_D, + SIn => RXD0, + CTS_n => CTS0, + DSR_n => DSR0, + RI_n => RI0, + DCD_n => DCD0, + SOut => TXD0, + RTS_n => RTS0, + DTR_n => DTR0, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut0, + Intr => open); + + u4 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut1, + CS_n => UART1CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A(2 downto 0), + D_In => D, + D_Out => UART1_D, + SIn => RXD1, + CTS_n => CTS1, + DSR_n => DSR1, + RI_n => RI1, + DCD_n => DCD1, + SOut => TXD1, + RTS_n => RTS1, + DTR_n => DTR1, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut1, + Intr => open); + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/DebugSystemXR.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/DebugSystemXR.vhd new file mode 100644 index 00000000..ca8fa877 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/DebugSystemXR.vhd @@ -0,0 +1,185 @@ +-- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs +-- that can be synthesized and used with +-- the NoICE debugger that can be found at +-- http://www.noicedebugger.com/ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity DebugSystemXR is + port( + Reset_n : in std_logic; + Clk : in std_logic; + NMI_n : in std_logic; + OE_n : out std_logic; + WE_n : out std_logic; + RAMCS_n : out std_logic; + ROMCS_n : out std_logic; + PGM_n : out std_logic; + A : out std_logic_vector(16 downto 0); + D : inout std_logic_vector(7 downto 0); + RXD0 : in std_logic; + CTS0 : in std_logic; + DSR0 : in std_logic; + RI0 : in std_logic; + DCD0 : in std_logic; + RXD1 : in std_logic; + CTS1 : in std_logic; + DSR1 : in std_logic; + RI1 : in std_logic; + DCD1 : in std_logic; + TXD0 : out std_logic; + RTS0 : out std_logic; + DTR0 : out std_logic; + TXD1 : out std_logic; + RTS1 : out std_logic; + DTR1 : out std_logic + ); +end entity DebugSystemXR; + +architecture struct of DebugSystemXR is + + signal M1_n : std_logic; + signal MREQ_n : std_logic; + signal IORQ_n : std_logic; + signal RD_n : std_logic; + signal WR_n : std_logic; + signal RFSH_n : std_logic; + signal HALT_n : std_logic; + signal WAIT_n : std_logic; + signal INT_n : std_logic; + signal RESET_s : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal D_i : std_logic_vector(7 downto 0); + signal ROM_D : std_logic_vector(7 downto 0); + signal UART0_D : std_logic_vector(7 downto 0); + signal UART1_D : std_logic_vector(7 downto 0); + signal CPU_D : std_logic_vector(7 downto 0); + + signal Mirror : std_logic; + + signal IOWR_n : std_logic; + signal RAMCS_n_i : std_logic; + signal UART0CS_n : std_logic; + signal UART1CS_n : std_logic; + + signal BaudOut0 : std_logic; + signal BaudOut1 : std_logic; + +begin + + Wait_n <= '1'; + BusRq_n <= '1'; + INT_n <= '1'; + + OE_n <= RD_n; + WE_n <= WR_n; + RAMCS_n <= RAMCS_n_i; + ROMCS_n <= '1'; + PGM_n <= '1'; + A(14 downto 0) <= A_i(14 downto 0); + A(16 downto 15) <= "00"; + D <= D_i when WR_n = '0' else "ZZZZZZZZ"; + + process (Reset_n, Clk) + begin + if Reset_n = '0' then + Reset_s <= '0'; + Mirror <= '0'; + elsif Clk'event and Clk = '1' then + Reset_s <= '1'; + if IORQ_n = '0' and A_i(7 downto 4) = "1111" then + Mirror <= D_i(0); + end if; + end if; + end process; + + IOWR_n <= WR_n or IORQ_n; + RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n; + UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1'; + UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1'; + + CPU_D <= + D when RAMCS_n_i = '0' else + UART0_D when UART0CS_n = '0' else + UART1_D when UART1CS_n = '0' else + ROM_D; + + u0 : entity work.T80s + generic map(Mode => 1, T2Write => 1, IOWait => 0) + port map( + RESET_n => RESET_s, + CLK_n => Clk, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + RD_n => RD_n, + WR_n => WR_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + A => A_i, + DI => CPU_D, + DO => D_i); + + u1 : entity work.MonZ80 + port map( + Clk => Clk, + A => A_i(10 downto 0), + D => ROM_D); + + u3 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut0, + CS_n => UART0CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A_i(2 downto 0), + D_In => D_i, + D_Out => UART0_D, + SIn => RXD0, + CTS_n => CTS0, + DSR_n => DSR0, + RI_n => RI0, + DCD_n => DCD0, + SOut => TXD0, + RTS_n => RTS0, + DTR_n => DTR0, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut0, + Intr => open); + + u4 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut1, + CS_n => UART1CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A_i(2 downto 0), + D_In => D_i, + D_Out => UART1_D, + SIn => RXD1, + CTS_n => CTS1, + DSR_n => DSR1, + RI_n => RI1, + DCD_n => DCD1, + SOut => TXD1, + RTS_n => RTS1, + DTR_n => DTR1, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut1, + Intr => open); + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T8080se.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T8080se.vhd new file mode 100644 index 00000000..2b6d28f8 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T8080se.vhd @@ -0,0 +1,185 @@ +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_ALU.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_MCode.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_Pack.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_Reg.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80se.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80se.vhd new file mode 100644 index 00000000..ac8886a8 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/T80se.vhd @@ -0,0 +1,184 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/YM2149_linmix_sep.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..27f26749 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,553 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/dac.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/dac.vhd new file mode 100644 index 00000000..9f696b0b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/gen_ram.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/gen_video.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/gen_video.vhd new file mode 100644 index 00000000..da8d77d4 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/gen_video.vhd @@ -0,0 +1,70 @@ +--------------------------------------------------------------------------------- +-- Galaga video horizontal/vertical and sync generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.ALL; + +entity gen_video is +port( + clk : in std_logic; + enable : in std_logic; + hcnt : out std_logic_vector(5 downto 0); + vcnt : out std_logic_vector(5 downto 0); + hsync : out std_logic; + vsync : out std_logic; + blankn : out std_logic +); +end gen_video; + +architecture struct of gen_video is + signal hblank : std_logic; + signal vblank : std_logic; + signal hcntReg : unsigned (5 DOWNTO 0) := to_unsigned(000,9); + signal vcntReg : unsigned (5 DOWNTO 0) := to_unsigned(015,9); +begin + +hcnt <= std_logic_vector(hcntReg); +vcnt <= std_logic_vector(vcntReg); + + +process(clk) begin + + if enable = '1' then + + if hcntReg = 511 then + hcntReg <= to_unsigned (128,9); + else + hcntReg <= hcntReg + 1; + end if; + + if hcntReg = 191 then + if vcntReg = 261 then + vcntReg <= to_unsigned(0,9); + else + vcntReg <= vcntReg + 1; + end if; + end if; + + if hcntReg = (175+ 0-8+8) then hsync <= '1'; -- 1 + elsif hcntReg = (175+29-8+8) then hsync <= '0'; + end if; + + if vcntReg = 252 then vsync <= '1'; + elsif vcntReg = 260 then vsync <= '0'; + end if; + + if hcntReg = (127+16+8) then hblank <= '1'; + elsif hcntReg = (255-17+8+1) then hblank <= '0'; + end if; + + if vcntReg = (240+1-1) then vblank <= '1'; + elsif vcntReg = (015+1) then vblank <= '0'; + end if; + + blankn <= not (hblank or vblank); + end if; + +end process; + +end architecture; \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/hq2x.sv b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/hq2x.sv new file mode 100644 index 00000000..3e406318 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bxx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/keyboard.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_io.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_pll_12M_14M.qip b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_pll_12M_14M.qip new file mode 100644 index 00000000..02816126 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_pll_12M_14M.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.ppf"] diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_pll_12M_14M.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_pll_12M_14M.vhd new file mode 100644 index 00000000..4865e696 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/mist_pll_12M_14M.vhd @@ -0,0 +1,424 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: mist_pll_12M_14M.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY mist_pll_12M_14M IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END mist_pll_12M_14M; + + +ARCHITECTURE SYN OF mist_pll_12m_14m IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 420, + clk0_duty_cycle => 50, + clk0_multiply_by => 191, + clk0_phase_shift => "0", + clk1_divide_by => 360, + clk1_duty_cycle => 50, + clk1_multiply_by => 191, + clk1_phase_shift => "0", + clk2_divide_by => 105, + clk2_duty_cycle => 50, + clk2_multiply_by => 191, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=mist_pll_12M_14M", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "420" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "360" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "105" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.278571" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.325000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "49.114285" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "191" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.28800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "49.15200000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "mist_pll_12M_14M.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "420" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "360" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "105" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/osd.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan.vhd new file mode 100644 index 00000000..e95413af --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan.vhd @@ -0,0 +1,821 @@ +--------------------------------------------------------------------------------- +-- Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok + +-- Use with MAME roms from pooyan.zip +-- +-- Use make_pooyan_proms.bat to build vhd file from binaries +-- +-- Pooyan Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 32Kx8bits program rom +-- +-- One char tile map 32x28 +-- 8Kx16bits graphics rom 4bits/pixel +-- 16colors/16sets among 16 colors +-- +-- 24 sprites with priorities and flip H/V +-- 16Kx16bits graphics rom 4bits/pixel +-- 15 colors/16sets among 16 colors (different of char colors). +-- +-- Char/sprites color palette 2x16 colors among 256 colors +-- 3red 3green 2blue +-- +-- Working ram : 4Kx8bits +-- Sprites data ram : 256x16bits +-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits + +-- SOUND : 1xZ80@1.79MHz CPU accessing its program rom, working ram, 2x-AY3-8910 +-- 16Kx8bits program rom +-- +-- 1xAY-3-8910 +-- I/O noise input and command/trigger from video board. +-- 3 sound channels +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- 6 RC filters with 4 states : transparent or cut 600Hz, 700Hz, 3.4KHz +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity pooyan is +port( + clock_12 : in std_logic; + clock_14 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(2 downto 0); + video_clk : out std_logic; + video_vblank : out std_logic; + video_hblank : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(10 downto 0); + + dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B / Coinage_A + dip_switch_2 : in std_logic_vector(7 downto 0); -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + + fire1 : in std_logic; + right1 : in std_logic; + left1 : in std_logic; + down1 : in std_logic; + up1 : in std_logic; + + fire2 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + down2 : in std_logic; + up2 : in std_logic; + + sw : in std_logic_vector(9 downto 0); + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end pooyan; + +architecture struct of pooyan is + + signal reset_n: std_logic; + signal clock_12n : std_logic; + signal clock_6 : std_logic := '0'; + signal clock_6n : std_logic; + signal clock_div : std_logic_vector(1 downto 0) := "00"; + + signal hcnt : std_logic_vector(5 downto 0); -- horizontal counter + signal vcnt : std_logic_vector(8 downto 0); -- vertical counter + signal pxcnt : std_logic_vector(2 downto 0); -- pixel counter + signal spcnt : std_logic_vector(4 downto 0); -- sprite counter + + signal csync : std_logic; + signal hsync0 : std_logic; + signal hsync1 : std_logic; + signal hsync2 : std_logic; + + signal hblank : std_logic; + signal vblank : std_logic; + + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_nmi_n : std_logic; + + signal cpu_rom_do : std_logic_vector( 7 downto 0); + + signal wram_addr : std_logic_vector(11 downto 0); + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal ch_graphx_addr_f: std_logic_vector(11 downto 0); + signal ch_graphx_addr : std_logic_vector(11 downto 0); + signal ch_graphx1_do : std_logic_vector( 7 downto 0); + signal ch_graphx2_do : std_logic_vector( 7 downto 0); + signal ch_pixels : std_logic_vector(15 downto 0); + signal ch_data1 : std_logic_vector( 7 downto 0); + signal ch_color_set : std_logic_vector(3 downto 0); + signal ch_palette_addr : std_logic_vector(7 downto 0); + signal ch_palette_do : std_logic_vector(7 downto 0); + + signal spram_addr : std_logic_vector(7 downto 0); + signal spram1_we : std_logic; + signal spram1_do : std_logic_vector(7 downto 0); + signal spram2_we : std_logic; + signal spram2_do : std_logic_vector(7 downto 0); + + signal sp_graphx_addr : std_logic_vector(11 downto 0); + signal sp_graphx1_do : std_logic_vector(7 downto 0); + signal sp_graphx2_do : std_logic_vector(7 downto 0); + signal vcnt_r : std_logic_vector(8 downto 0); + signal sp_line : std_logic_vector(7 downto 0); + signal sp_on_line : std_logic; + signal sp_attr : std_logic_vector(7 downto 0); + signal sp_posh : std_logic_vector(7 downto 0); + signal sp_pixels : std_logic_vector(15 downto 0); + signal sp_color_set : std_logic_vector(3 downto 0); + signal sp_palette_addr : std_logic_vector(7 downto 0); + signal sp_palette_do : std_logic_vector(7 downto 0); + signal sp_read_out : std_logic_vector(3 downto 0); + signal sp_blank : std_logic; + + signal rgb_palette_addr : std_logic_vector(4 downto 0); + signal rgb_palette_do : std_logic_vector(7 downto 0); + + signal sp_buffer_write_addr : std_logic_vector(7 downto 0); + signal sp_buffer_write_we : std_logic; + signal sp_buffer_read_addr : std_logic_vector(7 downto 0); + + signal sp_buffer_ram1_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram1_we : std_logic; + signal sp_buffer_ram1_di : std_logic_vector(3 downto 0); + signal sp_buffer_ram1_do : std_logic_vector(3 downto 0); + + signal sp_buffer_ram2_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram2_we : std_logic; + signal sp_buffer_ram2_di : std_logic_vector(3 downto 0); + signal sp_buffer_ram2_do : std_logic_vector(3 downto 0); + + signal sp_buffer_sel : std_logic; + + signal itt_n : std_logic; + signal flip : std_logic; + signal A10x_we : std_logic; + signal A18x_we : std_logic; + signal sound_cmd : std_logic_vector(7 downto 0); + signal sound_trig : std_logic; + + signal input_0 : std_logic_vector(7 downto 0); + signal input_1 : std_logic_vector(7 downto 0); + signal input_2 : std_logic_vector(7 downto 0); + +begin +video_clk <= clock_6n; +clock_12n <= not clock_12; +clock_6n <= not clock_6; +reset_n <= not reset; + +-- debug +process (reset, clock_12) +begin + if rising_edge(clock_12) and cpu_ena ='1' and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-- make 6MHz clock from 12MHz +process (clock_12) +begin + if reset='1' then + clock_6 <= '0'; + else + if rising_edge(clock_12) then + clock_6 <= not clock_6; + end if; + end if; +end process; + + +-------------------------- +-- Video/sprite scanner -- +-------------------------- + +-- make hcnt and vcnt video scanner from pixel clocks and counts +-- +-- pxcnt |0|1|2|3|4|5|6|7|0|1|2|3|4|5|6|7| +-- hcnt | N | N+1 | +-- cpu_adr/do | | + +-- +-- hcnt [0..47] => 48 x 8 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz) +-- vcnt [252..255,256..511] => 260 lines, 1 frame is 260 x 62.5us = 16.250ms (61.54Hz) + +process (reset, clock_6) +begin + if reset='1' then + pxcnt <= "000"; + hcnt <= "000000"; + vcnt <= '0'&X"FC"; + spcnt <= "00000"; + else + if rising_edge(clock_6) then + pxcnt <= pxcnt + '1'; + if pxcnt = "111" then + hcnt <= hcnt + '1'; + + if hcnt = "101111" then -- char from #0 to #47 (one line) + hcnt <= "000000"; + if vcnt = '1'&X"FF" then + vcnt <= '0'&X"FC"; + else + vcnt <= vcnt + '1'; + end if; + end if; + + -- sprite down counter + if hcnt(0) = '1' then -- every is 16 bits (2 char) + if hcnt = "101111" then + spcnt <= "01000"; -- start with sprite #8 + else + spcnt <= spcnt + '1'; -- upto sprite #31 + end if; + end if; + + end if; + end if; + end if; +end process; + +cpu_ena <= not pxcnt(0); + +-- inputs +input_0 <= "111" & not start2 & not start1 & '1' & '1' & not coin1; -- ?/ ?/ ?/ 2S/ 1S/SVC/ C2/ C1 +input_1 <= "111" & not fire1 & not down1 & not up1 & not right1 & not left1; -- ?/1FL/1SR/1SL/1DW/1UP/1RI/1LE +input_2 <= "111" & not fire2 & not down2 & not up2 & not right2 & not left2; -- ?/2FL/2SR/2SL/2DW/2UP/2RI/2LE + +-- cpu input address decoding (mirror mostly from Mame) +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"8" else -- 0000-7FFF + wram_do when cpu_addr(15 downto 12) = X"8" else -- 8000-8FFF + + spram1_do when cpu_addr(15 downto 12) = X"9" and + cpu_addr(10) = '0' else -- 9000-93FF + + spram2_do when cpu_addr(15 downto 12) = X"9" and + cpu_addr(10) = '1' else -- 9400-97FF + + dip_switch_2 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "000" else -- A000-A000 + + input_0 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "100" else -- A080-A080 + + input_1 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "101" else -- A0A0-A0A0 + + input_2 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "110" else -- A0C0-A0C0 + + dip_switch_1 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "111" else -- A0E0-A0E0 + + X"FF"; + +-- working ram address multiplexer cpu/video scanner +wram_addr <= cpu_addr(11 downto 0) when cpu_ena = '1' else + '0' & pxcnt(1) & vcnt(7 downto 3) & hcnt(4 downto 0) when flip = '0' else + '0' & pxcnt(1) & not vcnt(7 downto 3) & not hcnt(4 downto 0); + +-- sprite data ram address multiplexer cpu/sprite scanner +spram_addr <= cpu_addr(7 downto 0) when cpu_ena = '1' else "00" & spcnt & pxcnt(1); + +-- write enable to working ram, sprite data ram and misc registers +wram_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"8" else '0'; +spram1_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"9" and cpu_addr(10) = '0' else '0'; +spram2_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"9" and cpu_addr(10) = '1' else '0'; +A10x_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" and cpu_addr(8 downto 7) = "10" else '0'; +A18x_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" and cpu_addr(8 downto 7) = "11" else '0'; + +-- Misc registers : interrupt enable/clear, cocktail flip, sound trigger +process (clock_6) +begin + if rising_edge(clock_6) then + if A10x_we = '1' then + sound_cmd <= cpu_do; + end if; + + if A18x_we = '1' then + if cpu_addr(2 downto 0) = "000" then itt_n <= cpu_do(0); end if; + if cpu_addr(2 downto 0) = "111" then flip <= not cpu_do(0); end if; + if cpu_addr(2 downto 0) = "001" then sound_trig <= cpu_do(0); end if; + end if; + + if itt_n = '0' then + cpu_nmi_n <= '1'; + else -- lauch nmi and end of frame + if (vcnt = 493) and (hcnt = "000000") and (pxcnt = "000") then + cpu_nmi_n <= '0'; + end if; + end if; + end if; +end process; + + +---------------------- +--- sprite machine --- +---------------------- +-- sprite data rams are scanned from sprites addresse 31 to 8 at each line + +-- latch current sprite data with respect to pixel and hcnt in relation +-- with sprite data ram addressing +process (clock_6) +begin + if rising_edge(clock_6) then + + if (hcnt(0) = '0') and (pxcnt = "001") then + sp_posh <= spram1_do ; -- a.k.a. X + sp_attr <= spram2_do ; -- color and flip x/y + vcnt_r <= vcnt; + end if; + + -- sprite is on current line if sp_line is below 16 + -- and if sprite vertical position (a.k.a. Y) is below xF0 + if (hcnt(0) = '0') and (pxcnt = "011") then + if sp_line(7 downto 4) = "0000" and spram2_do < X"F0" then + sp_on_line <= '1'; + else + sp_on_line <= '0'; + end if; + end if; + + -- delay sp_color_set + if (hcnt(0) = '0') and (pxcnt = "100") then + sp_color_set <= sp_attr(3 downto 0); + end if; + + end if; +end process; + +-- sp_line (valid only when pxcnt = "011") +sp_line <= not(vcnt_r(7 downto 0)) - spram2_do; + +-- address sprite graphics rom with sprite code and tile number and sprite line counter +-- with respect to sprite flip x/y controls +with sp_attr(7 downto 6) select + sp_graphx_addr <= spram1_do(5 downto 0) & sp_line(3) & hcnt(0) & pxcnt(2) & sp_line(2 downto 0) when "11", + spram1_do(5 downto 0) & sp_line(3) & not hcnt(0) & not pxcnt(2) & sp_line(2 downto 0) when "10", + spram1_do(5 downto 0) & not sp_line(3) & hcnt(0) & pxcnt(2) & not sp_line(2 downto 0) when "01", + spram1_do(5 downto 0) & not sp_line(3) & not hcnt(0) & not pxcnt(2) & not sp_line(2 downto 0) when others; + +-- latch and shift sprite graphics data with respect to flipx control +-- 16bits => 4x4bits = 4pixels / 16colors (15colors + transparent) +process (clock_6) +begin + if rising_edge(clock_6) then + + if pxcnt(1 downto 0) = "00" then + if sp_on_line = '1' then + if sp_attr(6) = '1' then + sp_pixels <= sp_graphx1_do & sp_graphx2_do; + else + sp_pixels( 3 downto 0) <= sp_graphx2_do(0) & sp_graphx2_do(1) & sp_graphx2_do(2) & sp_graphx2_do(3); + sp_pixels( 7 downto 4) <= sp_graphx2_do(4) & sp_graphx2_do(5) & sp_graphx2_do(6) & sp_graphx2_do(7); + sp_pixels(11 downto 8) <= sp_graphx1_do(0) & sp_graphx1_do(1) & sp_graphx1_do(2) & sp_graphx1_do(3); + sp_pixels(15 downto 12) <= sp_graphx1_do(4) & sp_graphx1_do(5) & sp_graphx1_do(6) & sp_graphx1_do(7); + end if; + else + sp_pixels <= (others => '0'); + end if; + else + sp_pixels( 3 downto 0) <= sp_pixels( 2 downto 0) & '0'; + sp_pixels( 7 downto 4) <= sp_pixels( 6 downto 4) & '0'; + sp_pixels(11 downto 8) <= sp_pixels(10 downto 8) & '0'; + sp_pixels(15 downto 12) <= sp_pixels(14 downto 12) & '0'; + end if; + + end if; + +end process; + +-- address sprite color palette 16colors/pixel, 16 sets => 16 colors +sp_palette_addr <= sp_color_set & sp_pixels(3) & sp_pixels(7) & sp_pixels(11) & sp_pixels(15); + +-- write sprite to line buffer at posh position +process (clock_6) +begin + if rising_edge(clock_6) then + if hcnt(0) = '0' and pxcnt = "101" then + sp_buffer_write_addr <= sp_posh; + else + sp_buffer_write_addr <= sp_buffer_write_addr + '1'; + end if; + end if; +end process; + +-- write colors to buffer when not transparent +sp_buffer_write_we <= '0' when sp_palette_do(3 downto 0) = "0000" else '1'; + +-- read sprite line buffer and erase after read +process (clock_12) +begin + if rising_edge(clock_12) then + if hcnt = "101111" and pxcnt = "111" then + sp_buffer_read_addr <= "11111010"; -- tune horizontal position of sprites + else + if clock_6 = '0' then + sp_buffer_read_addr <= sp_buffer_read_addr + '1'; + else + if vcnt(0) = '0' then + sp_read_out <= sp_buffer_ram1_do; + else + sp_read_out <= sp_buffer_ram2_do; + end if; + end if; + end if; + end if; +end process; + +-- toggle read/write sprite line buffer every other line + +-- wait pxcnt = "101" to allow last sprite (#31) to be written to line buffer +process (clock_6) +begin + if rising_edge(clock_6) then + if pxcnt = "101" then sp_buffer_sel <= vcnt(0); end if; + end if; +end process; + +sp_buffer_ram1_addr <= sp_buffer_read_addr when sp_buffer_sel = '0' else sp_buffer_write_addr; +sp_buffer_ram2_addr <= sp_buffer_read_addr when sp_buffer_sel = '1' else sp_buffer_write_addr; + +sp_buffer_ram1_di <= "0000" when sp_buffer_sel = '0' else sp_palette_do(3 downto 0); +sp_buffer_ram2_di <= "0000" when sp_buffer_sel = '1' else sp_palette_do(3 downto 0); + +sp_buffer_ram1_we <= not clock_6 when sp_buffer_sel = '0' else sp_buffer_write_we; +sp_buffer_ram2_we <= not clock_6 when sp_buffer_sel = '1' else sp_buffer_write_we; + +-------------------- +--- char machine --- +-------------------- + +-- latch current char data with respect to vcnt and hcnt in relation +-- with wram ram addressing +process (clock_6) +begin + if rising_edge(clock_6) and pxcnt = "001" then + ch_data1 <= wram_do ; + end if; + + if rising_edge(clock_6) and pxcnt = "100" then + ch_color_set <= ch_data1(3 downto 0) ; + end if; + +end process; + +-- address char graphics rom with char code, pixel count and vertical line counter +-- with respect to char flip x/y controls +with ch_data1(7 downto 6) select +ch_graphx_addr_f <= wram_do & pxcnt(2) & vcnt(2 downto 0) when "00", + wram_do & not pxcnt(2) & vcnt(2 downto 0) when "01", + wram_do & pxcnt(2) & not(vcnt(2 downto 0)) when "10", + wram_do & not pxcnt(2) & not(vcnt(2 downto 0)) when others; + +-- in cocktail flip mode negate h/v counters +ch_graphx_addr <= ch_graphx_addr_f when flip ='0' else ch_graphx_addr_f xor "000000001111"; + +-- latch and shift char graphics data with respect to flipx control and cocktail flip control +-- 16bits => 4x4bits = 4pixels / 16colors +process (clock_6) +begin + if rising_edge(clock_6) then + if pxcnt(1 downto 0) = "00" then + if (ch_data1(6) xor flip) = '0' then + ch_pixels <= ch_graphx1_do & ch_graphx2_do; + else + ch_pixels( 3 downto 0) <= ch_graphx2_do(0) & ch_graphx2_do(1) &ch_graphx2_do(2) &ch_graphx2_do(3); + ch_pixels( 7 downto 4) <= ch_graphx2_do(4) & ch_graphx2_do(5) &ch_graphx2_do(6) &ch_graphx2_do(7); + ch_pixels(11 downto 8) <= ch_graphx1_do(0) & ch_graphx1_do(1) &ch_graphx1_do(2) &ch_graphx1_do(3); + ch_pixels(15 downto 12) <= ch_graphx1_do(4) & ch_graphx1_do(5) &ch_graphx1_do(6) &ch_graphx1_do(7); + end if; + else + ch_pixels( 3 downto 0) <= ch_pixels( 2 downto 0) & '0'; + ch_pixels( 7 downto 4) <= ch_pixels( 6 downto 4) & '0'; + ch_pixels(11 downto 8) <= ch_pixels(10 downto 8) & '0'; + ch_pixels(15 downto 12) <= ch_pixels(14 downto 12) & '0'; + end if; + end if; + +end process; + +-- address char color palette 4 colors, 64 sets => 16 colors +with sw(4 downto 0) select +ch_palette_addr <= +ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(11) & ch_pixels(15) when '0'&X"0", +ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(15) & ch_pixels(11) when '0'&X"1", +ch_color_set & ch_pixels(3) & ch_pixels(11) & ch_pixels( 7) & ch_pixels(15) when '0'&X"2", +ch_color_set & ch_pixels(3) & ch_pixels(11) & ch_pixels(15) & ch_pixels( 7) when '0'&X"3", +ch_color_set & ch_pixels(3) & ch_pixels(15) & ch_pixels( 7) & ch_pixels(11) when '0'&X"4", +ch_color_set & ch_pixels(3) & ch_pixels(15) & ch_pixels(11) & ch_pixels( 7) when '0'&X"5", + +ch_color_set & ch_pixels(7) & ch_pixels( 3) & ch_pixels(11) & ch_pixels(15) when '0'&X"6", +ch_color_set & ch_pixels(7) & ch_pixels( 3) & ch_pixels(15) & ch_pixels(11) when '0'&X"7", +ch_color_set & ch_pixels(7) & ch_pixels(11) & ch_pixels( 3) & ch_pixels(15) when '0'&X"8", +ch_color_set & ch_pixels(7) & ch_pixels(11) & ch_pixels(15) & ch_pixels( 3) when '0'&X"9", +ch_color_set & ch_pixels(7) & ch_pixels(15) & ch_pixels( 3) & ch_pixels(11) when '0'&X"A", +ch_color_set & ch_pixels(7) & ch_pixels(15) & ch_pixels(11) & ch_pixels( 3) when '0'&X"B", + +ch_color_set & ch_pixels(11) & ch_pixels( 3) & ch_pixels( 7) & ch_pixels(15) when '0'&X"C", +ch_color_set & ch_pixels(11) & ch_pixels( 3) & ch_pixels(15) & ch_pixels( 7) when '0'&X"D", +ch_color_set & ch_pixels(11) & ch_pixels( 7) & ch_pixels( 3) & ch_pixels(15) when '0'&X"E", +ch_color_set & ch_pixels(11) & ch_pixels( 7) & ch_pixels(15) & ch_pixels( 3) when '0'&X"F", +ch_color_set & ch_pixels(11) & ch_pixels(15) & ch_pixels( 3) & ch_pixels( 7) when '1'&X"0", +ch_color_set & ch_pixels(11) & ch_pixels(15) & ch_pixels( 7) & ch_pixels( 3) when '1'&X"1", + +ch_color_set & ch_pixels(15) & ch_pixels( 3) & ch_pixels( 7) & ch_pixels(11) when '1'&X"2", +ch_color_set & ch_pixels(15) & ch_pixels( 3) & ch_pixels(11) & ch_pixels( 7) when '1'&X"3", +ch_color_set & ch_pixels(15) & ch_pixels( 7) & ch_pixels( 3) & ch_pixels(11) when '1'&X"4", +ch_color_set & ch_pixels(15) & ch_pixels( 7) & ch_pixels(11) & ch_pixels( 3) when '1'&X"5", +ch_color_set & ch_pixels(15) & ch_pixels(11) & ch_pixels( 3) & ch_pixels( 7) when '1'&X"6", +ch_color_set & ch_pixels(15) & ch_pixels(11) & ch_pixels( 7) & ch_pixels( 3) when others; + +--------------------- +-- mux char/sprite -- +--------------------- + +-- char data controls sprite display/hide +--process (clock_6) +--begin +-- if rising_edge(clock_6) then +-- sp_blank <= ch_color_set(4); +-- end if; +--end process; + +-- select rbg color and bank with respect to char/sprite selection +rgb_palette_addr <= +-- '1' & ch_palette_do(3 downto 0) when (sp_read_out = "0000" or sp_blank = '1') else + '1' & ch_palette_do(3 downto 0) when (sp_read_out = "0000" ) else + '0' & sp_read_out; + + + + +-- register and assign rbg palette output +process (clock_6) +begin + if rising_edge(clock_6) then + if hblank = '1' or vblank = '1' then + video_r <= "000"; + video_g <= "000"; + video_b <= "000"; + else + video_r <= rgb_palette_do(2 downto 0); + video_g <= rgb_palette_do(5 downto 3); + video_b <= rgb_palette_do(7 downto 6) & '0'; + end if; + end if; +end process; + +video_hblank <= hblank; +video_vblank <= vblank; + +---------------------------- +-- video syncs and blanks -- +---------------------------- + +process(clock_6) + constant hcnt_base : integer := 36; + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + if rising_edge(clock_6) and pxcnt = "110" then + + if hcnt = hcnt_base+0 then hsync0 <= '0'; + elsif hcnt = hcnt_base+3 then hsync0 <= '1'; + end if; + + if hcnt = hcnt_base then + if vcnt = 500 then + vsync_cnt := X"0"; + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if; + end if; + end if; + + if hcnt = hcnt_base-4 then + hblank <= '1'; + if vcnt = 496 then + vblank <= '1'; -- 492 ok + elsif vcnt = 262 then + vblank <= '0'; -- 262 ok + end if; + elsif hcnt = 0 then + hblank <= '0'; + end if; + + video_hs <= hsync0; + + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 8 then video_vs <= '1'; + end if; + + end if; +end process; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_6, + CLKEN => cpu_ena, + WAIT_n => '1', + INT_n => '1', --cpu_irq_n, + NMI_n => cpu_nmi_n, + BUSRQ_n => '1', + M1_n => open, + MREQ_n => cpu_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.pooyan_prog +port map( + clk => clock_6n, + addr => cpu_addr(14 downto 0), + data => cpu_rom_do +); + +-- working/char RAM 0x8000-0x8FFF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_6n, + we => wram_we, + addr => wram_addr, + d => cpu_do, + q => wram_do +); + +-- sprite RAM1 0x9000-0x90FF +spram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_6n, + we => spram1_we, + addr => spram_addr, + d => cpu_do, + q => spram1_do +); + +-- sprite RAM2 0x9400-0x94FF +spram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_6n, + we => spram2_we, + addr => spram_addr, + d => cpu_do, + q => spram2_do +); + +-- sprite line buffer 1 +splinebuf1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_12n, + we => sp_buffer_ram1_we, + addr => sp_buffer_ram1_addr, + d => sp_buffer_ram1_di, + q => sp_buffer_ram1_do +); + +-- sprite line buffer 2 +splinebuf2 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_12n, + we => sp_buffer_ram2_we, + addr => sp_buffer_ram2_addr, + d => sp_buffer_ram2_di, + q => sp_buffer_ram2_do +); + +-- char graphics ROM G10 +char_graphics_1 : entity work.pooyan_char_grphx1 +port map( + clk => clock_6, + addr => ch_graphx_addr, + data => ch_graphx1_do +); + +-- char graphics ROM G9 +char_graphics_2 : entity work.pooyan_char_grphx2 +port map( + clk => clock_6, + addr => ch_graphx_addr, + data => ch_graphx2_do +); + +-- char palette ROM +ch_palette : entity work.pooyan_char_color_lut +port map( + clk => clock_6, + addr => ch_palette_addr, + data => ch_palette_do +); + +-- sprite graphics ROM A9 +sp_graphics_1 : entity work.pooyan_sprite_grphx1 +port map( + clk => clock_6, + addr => sp_graphx_addr, + data => sp_graphx1_do +); + +-- sprite graphics ROM A8 +sp_graphics_2 : entity work.pooyan_sprite_grphx2 +port map( + clk => clock_6, + addr => sp_graphx_addr, + data => sp_graphx2_do +); + +-- sprite palette ROM +sp_palette : entity work.pooyan_sprite_color_lut +port map( + clk => clock_6, + addr => sp_palette_addr, + data => sp_palette_do +); + +-- rgb palette ROM +rgb_palette_gb : entity work.pooyan_palette +port map( + clk => clock_6, + addr => rgb_palette_addr, + data => rgb_palette_do +); + + +-- sound board +pooyan_sound_board : entity work.pooyan_sound_board +port map( + clock_14 => clock_14, + reset => reset, + + sound_trig => sound_trig, + sound_cmd => sound_cmd, + + audio_out => audio_out, + + dbg_cpu_addr => open + ); + +end struct; \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan_mist.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan_mist.vhd new file mode 100644 index 00000000..bb5088a5 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan_mist.vhd @@ -0,0 +1,279 @@ +--------------------------------------------------------------------------------- +-- Mist Top level for Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Use time_pilot_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +-- Uses 1 pll for 12MHz and 14MHz generation from 27MHz +-- +-- Mist key : +-- Right Button : reset game +-- +-- Keyboard players inputs : +-- +-- ESC : Add coin +-- 2 : Start 2 players +-- 1 : Start 1 player +-- SPACE : Fire +-- RIGHT arrow : rotate right +-- LEFT arrow : rotate left +-- UP arrow : rotate up +-- DOWN arrow : rotate down +-- +-- Other details : see time_pilot.vhd + +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; + +entity pooyan_mist is +port( + CLOCK_27 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0); + VGA_VS : out std_logic; + VGA_HS : out std_logic; + LED : out std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic +); +end pooyan_mist; + +architecture struct of pooyan_mist is + + signal clock_48 : std_logic; + signal clock_12 : std_logic; + signal clock_14 : std_logic; + signal reset : std_logic; + signal pll_locked: std_logic; + + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic; + signal audio : std_logic_vector(10 downto 0); + signal audio_pwm : std_logic; + + signal reset_n : std_logic; + signal ps2_clk : std_logic; + signal ps2_dat : std_logic; + signal joy_u : std_logic; + signal joy_l : std_logic; + signal joy_r : std_logic; + signal joy_d : std_logic; + signal kbd_intr : std_logic; + signal kbd_scancode : std_logic_vector(7 downto 0); + + + -- User IO + signal buttons : std_logic_vector(1 downto 0); + signal joy0 : std_logic_vector(7 downto 0); + signal joy1 : std_logic_vector(7 downto 0); + signal status : std_logic_vector(31 downto 0); + signal pix_ce : std_logic; + signal kbd_joy0 : std_logic_vector(7 downto 0); + signal kbd_joy1 : std_logic_vector(7 downto 0); + signal ps2Clk : std_logic; + signal ps2Data : std_logic; + signal ps2_scancode : std_logic_vector(7 downto 0); + + signal VGA_R_O : std_logic_vector(2 downto 0); + signal VGA_G_O : std_logic_vector(2 downto 0); + signal VGA_B_O : std_logic_vector(2 downto 0); + signal R : std_logic_vector(5 downto 0); + signal G : std_logic_vector(5 downto 0); + signal B : std_logic_vector(5 downto 0); + + constant CONF_STR : string := + "POOYAN;;O4,Joystick Control,Upright,Normal;T5,Reset;"; + + + function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + end function; + + component mist_io + generic ( STRLEN : integer := 0 ); + port ( + clk_sys :in std_logic; + SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; + SPI_DO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + buttons : out std_logic_vector(1 downto 0); + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + status : out std_logic_vector(31 downto 0); + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); + end component mist_io; + + component video_mixer + generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 ); + port ( + clk_sys, ce_pix, ce_pix_actual : in std_logic; + SPI_SCK, SPI_SS3, SPI_DI : in std_logic; + R, G, B : in std_logic_vector(2 downto 0); + HSync, VSync, line_start: in std_logic; + VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); + VGA_VS, VGA_HS : out std_logic + ); + end component video_mixer; + + component keyboard + PORT( + clk : in std_logic; + reset : in std_logic; + ps2_kbd_clk : in std_logic; + ps2_kbd_data : in std_logic; + joystick : out std_logic_vector (7 downto 0) + ); + end component; + +begin + +reset <= status(0) or status(5) or buttons(1) or not pll_locked; + +clocks : entity work.mist_pll_12M_14M + port map( + inclk0 => CLOCK_27, + c0 => clock_12,--12.28800000 + c1 => clock_14,--14.31800000 + c2 => clock_48,--49.15200000 + locked => pll_locked +); + + +vmixer : video_mixer + port map ( + clk_sys => clock_48, + ce_pix => pix_ce, + ce_pix_actual => pix_ce, + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + R => VGA_R_O, + G => VGA_G_O, + B => VGA_B_O, + HSync => hsync, + VSync => vsync, + line_start => '0', + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_VS => VGA_VS, + VGA_HS => VGA_HS +); + +mist_io_inst : mist_io + generic map (STRLEN => CONF_STR'length) + port map ( + clk_sys => clock_48, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_DI => SPI_DI, + SPI_DO => SPI_DO, + conf_str => to_slv(CONF_STR), + buttons => buttons, + joystick_1 => joy1, + joystick_0 => joy0, + status => status, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data +); + +Joy_r <= joy0(0) or joy1(0) or kbd_joy0(7) when status(4) = '0' + else joy0(3) or joy1(3) or kbd_joy0(4);--normal +Joy_l <= joy0(1) or joy1(1) or kbd_joy0(6) when status(4) = '0' + else joy0(2) or joy1(2) or kbd_joy0(5); +Joy_u <= joy0(3) or joy1(3) or kbd_joy0(4) when status(4) = '0' + else joy0(1) or joy1(1) or kbd_joy0(6); +Joy_d <= joy0(2) or joy1(2) or kbd_joy0(5) when status(4) = '0' + else joy0(0) or joy1(0) or kbd_joy0(7); + + +pooyan : entity work.pooyan + port map( + clock_12 => clock_12, + clock_14 => clock_14, + reset => reset, + video_r => VGA_R_O, + video_g => VGA_G_O, + video_b => VGA_B_O, + video_hblank => hblank, + video_vblank => vblank, + video_clk => pix_ce, + video_hs => hsync, + video_vs => vsync, + audio_out => audio, + dip_switch_1 => X"FF", -- Coinage_B / Coinage_A + dip_switch_2 => X"FB", -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + start2 => kbd_joy0(2) or status(3), + start1 => kbd_joy0(1) or status(2), + coin1 => kbd_joy0(3) or status(1), + fire1 => joy0(4) or joy1(4) or kbd_joy0(0), + right1 => Joy_r, + left1 => Joy_l, + down1 => Joy_d, + up1 => Joy_u, + fire2 => joy0(4) or joy1(4) or kbd_joy0(0), + right2 => Joy_r, + left2 => Joy_l, + down2 => Joy_d, + up2 => Joy_u, + sw => "0000000000", + dbg_cpu_addr => open +); + + +u_keyboard : keyboard + port map( + clk => clock_48, + reset => reset, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data, + joystick => kbd_joy0 +); + +u_dac : entity work.dac + port map( + clk_i => clock_48, + res_n_i => not reset, + dac_i => audio, + dac_o => audio_pwm +); + +AUDIO_L <= audio_pwm; +AUDIO_R <= audio_pwm; + + LED <= '1'; +end struct; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan_sound_board.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan_sound_board.vhd new file mode 100644 index 00000000..a4b38c7d --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/pooyan_sound_board.vhd @@ -0,0 +1,426 @@ +--------------------------------------------------------------------------------- +-- Pooyan sound board by Dar (darfpga@aol.fr) (08/11/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity pooyan_sound_board is +port( + clock_14 : in std_logic; + reset : in std_logic; + + sound_cmd : in std_logic_vector(7 downto 0); + sound_trig : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end pooyan_sound_board; + +architecture struct of pooyan_sound_board is + + signal reset_n: std_logic; + signal clock_14n : std_logic; + + signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0'); + signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0'); + + signal cpu_clock : std_logic; + signal ayx_clock : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_iorq_n : std_logic; + signal cpu_m1_n : std_logic; + + signal cpu_rom_do : std_logic_vector( 7 downto 0); + signal wram_do : std_logic_vector( 7 downto 0); + signal wram_we : std_logic; + + signal clr_irq_n : std_logic; + signal sen1_n : std_logic; + signal sen2_n : std_logic; + signal sen3_n : std_logic; + signal sen4_n : std_logic; + + signal sound_trig_r : std_logic; + + signal ay1_do : std_logic_vector(7 downto 0); + signal ay1_cs_n : std_logic; + signal ay1_bdir : std_logic; + signal ay1_bc1 : std_logic; + signal ay1_audio_muxed : std_logic_vector(7 downto 0); + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_port_b_di : std_logic_vector(7 downto 0); + + signal ay2_do : std_logic_vector(7 downto 0); + signal ay2_cs_n : std_logic; + signal ay2_bdir : std_logic; + signal ay2_bc1 : std_logic; + signal ay2_audio_muxed : std_logic_vector(7 downto 0); + signal ay2_audio_chan : std_logic_vector(1 downto 0); + + signal ay1_chan_a : std_logic_vector(7 downto 0); + signal ay1_chan_b : std_logic_vector(7 downto 0); + signal ay1_chan_c : std_logic_vector(7 downto 0); + signal ay2_chan_a : std_logic_vector(7 downto 0); + signal ay2_chan_b : std_logic_vector(7 downto 0); + signal ay2_chan_c : std_logic_vector(7 downto 0); + + signal filter_cmd_we : std_logic; + signal filter_cmd : std_logic_vector(11 downto 0); + signal mult_cmd : std_logic_vector(1 downto 0); + signal mult_value : integer range 0 to 779; + + signal Vc_1a : integer range -256*1024 to 256*1024-1; + signal Vc_1b : integer range -256*1024 to 256*1024-1; + signal Vc_1c : integer range -256*1024 to 256*1024-1; + signal Vc_2a : integer range -256*1024 to 256*1024-1; + signal Vc_2b : integer range -256*1024 to 256*1024-1; + signal Vc_2c : integer range -256*1024 to 256*1024-1; + signal Vc : integer range -256*1024 to 256*1024-1; + signal Vin : integer range -256 to 255; + signal dV : integer range -512 to 511; + signal Vcn_a : integer range -1024*1024 to 1024*1024-1; + signal Vcn_b : integer range -1024*1024 to 1024*1024-1; + signal Vcn_c : integer range -256*1024 to 256*1024-1; + +begin + +clock_14n <= not clock_14; +reset_n <= not reset; + +-- debug +process (reset, clock_14) +begin + if rising_edge(clock_14) and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-------------------------------------------------------- +-- RC filters equation +-- +-- Vc : capacitor voltage = output voltage +-- fs : sample frequency +-- Vin : voltage at resistor input +-- +-- Vc(k+1) = Vc(k) + (Vin-Vc(k))/(fs.R.C) +-- +-- Vcn * 1024 <= Vcn * 1024 + (Vin-Vc) * 1024/(fs.R.C) +-- With Vcn = 1024 * Vc +-------------------------------------------------------- +-- Filters will be run at 14.318MHz/512 = 27.96KHz +-------------------------------------------------------- +-- 6 filters have to be implemented +-- RC equation is time multiplexed to save multiplier +-- for small FPGA +-------------------------------------------------------- + +-- mux Vc +with clock_div1(3 downto 0) select +Vc <= Vc_1a when X"0", -- Vc_xy : [0..255*1024] + Vc_1b when X"1", -- => Vc : [-256*1024..255*1024] + Vc_1c when X"2", + Vc_2a when X"3", + Vc_2b when X"4", + Vc_2c when others; + +-- mux Vin +with clock_div1(3 downto 0) select +Vin <= to_integer(unsigned(ay1_chan_a)) when X"0", -- ayx_chan_y : [0..255] + to_integer(unsigned(ay1_chan_b)) when X"1", -- => Vin : [-256:255] + to_integer(unsigned(ay1_chan_c)) when X"2", + to_integer(unsigned(ay2_chan_a)) when X"3", + to_integer(unsigned(ay2_chan_b)) when X"4", + to_integer(unsigned(ay2_chan_c)) when others; + +-- compute dV +dV <= Vin-Vc/1024; -- Vc/1024 : [0..255], dv : [-255..511] => [-512..511] + +-- mux filter cmd +with clock_div1(3 downto 0) select +mult_cmd <= filter_cmd( 7 downto 6) when X"0", + filter_cmd( 9 downto 8) when X"1", + filter_cmd(11 downto 10) when X"2", + filter_cmd( 1 downto 0) when X"3", + filter_cmd( 3 downto 2) when X"4", + filter_cmd( 5 downto 4) when others; + +-- mux multiplier value +with mult_cmd select +mult_value <= 779 when "10", -- 0.047uF/1KOhm => (1024/fs.R.C = 779, cut fcy 3386Hz) + 166 when "01", -- 0.220uF/1KOhm => (1024/fs.R.C = 166, cut fcy 723Hz) + 137 when "11", -- 0.267uF/1KOhm => (1024/fs.R.C = 137, cut fcy 596Hz) + 779 when others; -- Not use + +-- compute Vcn +Vcn_a <= Vin*1024 when mult_cmd = "00" else Vc + dv*mult_value; -- => Vcn_a : [-1024*1024..1023*1024] + +-- limit to > 0 +Vcn_b <= 0 when Vcn_a < 0 else Vcn_a; + +-- limit to < 255*1024 +Vcn_c <= 255*1024 when Vcn_b > 255*1024 else Vcn_b; + +-- demux/store result and mix channels +process (clock_14) +begin + if rising_edge(clock_14) then -- 14.318MHz/512 => fs = 27.96KHz + + -- demux & down sample + if clock_div1(8 downto 0) = '0'&X"00" then Vc_1a <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"01" then Vc_1b <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"02" then Vc_1c <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"03" then Vc_2a <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"04" then Vc_2b <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"05" then Vc_2c <= Vcn_c; end if; + + -- rescale and mix channels with down sample + if clock_div1(8 downto 0) = '0'&X"06" then + audio_out <= std_logic_vector(to_unsigned(Vc_1a/1024,11)) + + std_logic_vector(to_unsigned(Vc_1b/1024,11)) + + std_logic_vector(to_unsigned(Vc_1c/1024,11)) + + std_logic_vector(to_unsigned(Vc_2a/1024,11)) + + std_logic_vector(to_unsigned(Vc_2b/1024,11)) + + std_logic_vector(to_unsigned(Vc_2c/1024,11)); + end if; + end if; +end process; + + +-- divide clocks +-- random generator ? +process (clock_14) +begin + if reset='1' then + clock_div1 <= (others =>'0'); + biquinary_div <= (others =>'0'); + else + if rising_edge(clock_14) then + clock_div1 <= clock_div1 + '1'; + + if clock_div1 = X"800" then + if biquinary_div(3 downto 1) = "100" then + biquinary_div(3 downto 1) <= "000"; + biquinary_div(0) <= not biquinary_div(0); + else + biquinary_div(3 downto 1) <= biquinary_div(3 downto 1) + '1'; + end if; + end if; + + end if; + end if; +end process; + +-- make clocks for cpu and sound generators +cpu_clock <= clock_div1(2); +ayx_clock <= not clock_div1(2); + +-- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF + wram_do when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF + ay1_do when cpu_addr(15 downto 13) = "010" else -- 4000-5FFF + ay2_do when cpu_addr(15 downto 13) = "011" else -- 6000-7FFF + X"FF"; + +-- write enable to working ram and filter command register +wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = "0011" else '0'; +filter_cmd_we <= '1' when cpu_wr_n = '0' and cpu_addr(15) = '1' else '0'; + +-- chip select with r/w direction to AY chips +sen1_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"4" else '1'; +sen2_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"5" else '1'; +sen3_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"6" else '1'; +sen4_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"7" else '1'; + +-- finalise AY r/w & address controls +ay1_bc1 <= not sen2_n or ( cpu_wr_n and not sen1_n); +ay1_bdir <= not sen2_n or (not cpu_wr_n and not sen1_n); +ay1_cs_n <= sen1_n and sen2_n; + +ay2_bc1 <= not sen4_n or ( cpu_wr_n and not sen3_n); +ay2_bdir <= not sen4_n or (not cpu_wr_n and not sen3_n); +ay2_cs_n <= sen3_n and sen4_n; + +-- input random (?) to AY1 chip +ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(11)&"0000"; + +-- clear irq when reset and irq acknowledge +clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n); + +-- regsiter filters commands (11 bits data are cpu address) +process (cpu_clock) +begin + if rising_edge(cpu_clock) then + if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if; + end if; +end process; + +-- latch sound trigger rising edge to set cpu_irq, and manage clear +process (clock_14) +begin + if rising_edge(clock_14) then + + sound_trig_r <= sound_trig; + + if clr_irq_n = '0' then + cpu_irq_n <= '1'; + else + if sound_trig ='1' and sound_trig_r = '0' then + cpu_irq_n <= '0'; + end if; + end if; + + end if; +end process; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => cpu_clock, + CLKEN => '1', + WAIT_n => '1', + INT_n => cpu_irq_n, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_iorq_n, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.pooyan_sound_prog +port map( + clk => clock_14n, + addr => cpu_addr(12 downto 0), + data => cpu_rom_do +); + +-- working RAM +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_14n, + we => wram_we, + addr => cpu_addr(9 downto 0), + d => cpu_do, + q => wram_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => ay1_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => ay1_cs_n, -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => sound_cmd, -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => ay1_port_b_di, -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => ay2_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => ay2_cs_n, -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end struct; \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_color_lut.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_color_lut.vhd new file mode 100644 index 00000000..d8739c6b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_color_lut.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_char_color_lut is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_char_color_lut is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"03",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"03",X"01",X"03",X"03",X"04",X"04",X"07",X"08",X"09",X"0F",X"0B",X"0C",X"0D",X"0E",X"0F",X"03", + X"03",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"03",X"04",X"05",X"06",X"0F",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"01",X"02",X"03", + X"03",X"05",X"06",X"07",X"0F",X"09",X"07",X"08",X"06",X"0D",X"0E",X"0F",X"01",X"02",X"03",X"04", + X"03",X"02",X"07",X"08",X"04",X"0A",X"08",X"06",X"07",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05", + X"03",X"07",X"08",X"09",X"0A",X"0B",X"07",X"06",X"08",X"0F",X"01",X"02",X"03",X"04",X"05",X"06", + X"03",X"08",X"09",X"0A",X"05",X"0C",X"06",X"08",X"07",X"01",X"02",X"03",X"04",X"05",X"06",X"07", + X"03",X"09",X"0A",X"0B",X"0C",X"0D",X"08",X"06",X"06",X"02",X"03",X"04",X"05",X"06",X"07",X"08", + X"03",X"03",X"0B",X"0C",X"04",X"0E",X"07",X"07",X"08",X"03",X"04",X"05",X"06",X"07",X"08",X"09", + X"03",X"0B",X"0C",X"0D",X"0E",X"0F",X"07",X"06",X"08",X"04",X"05",X"06",X"07",X"08",X"09",X"0A", + X"03",X"0C",X"0D",X"0E",X"0F",X"01",X"08",X"07",X"06",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B", + X"03",X"0D",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C", + X"03",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D", + X"03",X"0F",X"01",X"02",X"04",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E", + X"03",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_grphx1.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_grphx1.vhd new file mode 100644 index 00000000..9e545ca5 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_grphx1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_char_grphx1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_char_grphx1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"74",X"CC",X"00",X"70",X"F0",X"F0",X"F0",X"70",X"C0",X"60",X"FC",X"F2",X"F0",X"F0",X"F0",X"F0", + X"00",X"00",X"33",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"00",X"30",X"A8",X"E0",X"F0",X"F0",X"F0", + X"70",X"F0",X"F0",X"F0",X"70",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"E0",X"E2",X"CC",X"00",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"33",X"30",X"E0",X"F0",X"F0",X"F0",X"F0",X"D8",X"D0",X"80",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_grphx2.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_grphx2.vhd new file mode 100644 index 00000000..34c88aeb --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_char_grphx2.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_char_grphx2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_char_grphx2 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"30",X"70",X"C0",X"80",X"80",X"70",X"30",X"00",X"80",X"C0",X"20",X"20",X"60",X"C0",X"80",X"00", + X"00",X"00",X"F0",X"F0",X"40",X"00",X"00",X"00",X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00", + X"60",X"F0",X"B0",X"90",X"90",X"C0",X"40",X"00",X"20",X"20",X"A0",X"A0",X"E0",X"E0",X"60",X"00", + X"80",X"D0",X"F0",X"B0",X"90",X"80",X"00",X"00",X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00", + X"00",X"F0",X"F0",X"C0",X"60",X"30",X"10",X"00",X"80",X"E0",X"E0",X"80",X"80",X"80",X"80",X"00", + X"10",X"B0",X"A0",X"A0",X"A0",X"E0",X"E0",X"00",X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00", + X"00",X"90",X"90",X"90",X"D0",X"70",X"30",X"00",X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00", + 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if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_palette.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_palette.vhd new file mode 100644 index 00000000..522f4290 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_palette.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_palette is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_palette is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"38",X"C0",X"3F",X"C7",X"26",X"03",X"0D",X"2F",X"D1",X"C3",X"F0",X"B8",X"D8",X"FE", + X"00",X"07",X"38",X"80",X"3F",X"C7",X"26",X"03",X"0D",X"2F",X"34",X"20",X"F0",X"B8",X"D8",X"FE"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_prog.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_prog.vhd new file mode 100644 index 00000000..aca0bf96 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_prog.vhd @@ -0,0 +1,2070 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_prog is + type rom is array(0 to 32767) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"80",X"A1",X"C3",X"92",X"00",X"FF",X"77",X"3C",X"23",X"77",X"3C",X"19",X"C9",X"FF", + X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"87",X"E1",X"5F",X"16",X"00",X"19",X"5E",X"23", + X"56",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"FF",X"E5",X"26",X"88",X"3A",X"A0",X"88",X"6F",X"CB", + X"7E",X"28",X"0E",X"72",X"2C",X"73",X"2C",X"7D",X"FE",X"C0",X"30",X"02",X"3E",X"C0",X"32",X"A0", + X"88",X"E1",X"C9",X"0F",X"33",X"31",X"24",X"22",X"21",X"15",X"13",X"11",X"07",X"06",X"05",X"04", + X"03",X"02",X"01",X"FF",X"FF",X"FF",X"C3",X"6D",X"06",X"00",X"11",X"22",X"04",X"31",X"06",X"15", + X"02",X"33",X"07",X"21",X"03",X"24",X"05",X"13",X"01",X"00",X"33",X"05",X"61",X"BE",X"05",X"66", + X"07",X"06",X"DD",X"A8",X"05",X"60",X"BC",X"04",X"A6",X"51",X"05",X"38",X"8A",X"06",X"AD",X"BA", + X"05",X"CA",X"32",X"00",X"A0",X"31",X"00",X"90",X"32",X"00",X"88",X"06",X"08",X"C5",X"21",X"00", + X"00",X"DD",X"21",X"79",X"00",X"11",X"00",X"00",X"4A",X"7B",X"86",X"5F",X"30",X"04",X"14",X"20", + X"01",X"0C",X"2C",X"20",X"F4",X"24",X"7C",X"E6",X"0F",X"20",X"EE",X"32",X"00",X"A0",X"7B",X"DD", + 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Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sound_prog.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sound_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sound_prog is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"30",X"06",X"00",X"C3",X"AC",X"00",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF", + X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"40",X"57",X"E6",X"7F",X"FE",X"2B",X"D0",X"CB",X"7A",X"28",X"03", + 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Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_color_lut.vhd new file mode 100644 index 00000000..79da34bd --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_color_lut.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sprite_color_lut is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sprite_color_lut is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"02",X"02",X"04",X"02",X"06",X"07",X"08",X"09",X"04",X"0B",X"0C",X"06",X"0E",X"0F",X"0F", + X"00",X"03",X"02",X"05",X"03",X"07",X"08",X"09",X"0A",X"0B",X"0F",X"0F",X"0F",X"0F",X"0F",X"00", + X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F", + X"00",X"05",X"02",X"0B",X"05",X"09",X"0A",X"0B",X"0C",X"04",X"0E",X"0F",X"01",X"02",X"03",X"04", + X"00",X"04",X"07",X"0D",X"04",X"05",X"0B",X"0C",X"0D",X"0E",X"0A",X"01",X"02",X"03",X"04",X"0F", + X"00",X"01",X"01",X"02",X"01",X"0F",X"02",X"02",X"0F",X"0F",X"01",X"0F",X"00",X"01",X"00",X"00", + X"00",X"01",X"01",X"02",X"01",X"0F",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"0F",X"00",X"00", + X"00",X"01",X"01",X"04",X"01",X"0F",X"01",X"00",X"01",X"0F",X"0F",X"0F",X"00",X"0F",X"0F",X"00", + X"00",X"0A",X"02",X"01",X"03",X"0E",X"0F",X"01",X"02",X"04",X"04",X"05",X"06",X"07",X"08",X"0F", + X"00",X"04",X"02",X"0D",X"01",X"0F",X"01",X"01",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0F", + X"00",X"04",X"04",X"0F",X"0F",X"04",X"04",X"04",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"0D",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0F", + X"00",X"04",X"04",X"04",X"0F",X"0F",X"0F",X"00",X"04",X"0F",X"0F",X"0F",X"04",X"00",X"00",X"00", + X"00",X"0F",X"02",X"02",X"0F",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"04", + X"00",X"01",X"02",X"03",X"0C",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_grphx1.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_grphx1.vhd new file mode 100644 index 00000000..f45fdfb4 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_grphx1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sprite_grphx1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sprite_grphx1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",X"00", + X"E0",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"88",X"E8",X"30",X"30",X"31",X"00",X"10",X"30",X"31",X"71",X"F2",X"F2",X"EE", + X"88",X"00",X"88",X"FC",X"F8",X"F7",X"F7",X"F0",X"00",X"00",X"00",X"80",X"E0",X"F0",X"C0",X"80", + X"31",X"30",X"30",X"E8",X"88",X"00",X"00",X"00",X"EE",X"F2",X"F2",X"71",X"31",X"30",X"10",X"00", + X"F3",X"F7",X"F7",X"FB",X"FC",X"88",X"00",X"88",X"80",X"C8",X"F8",X"E0",X"80",X"00",X"00",X"00", + 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Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_grphx2.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_grphx2.vhd new file mode 100644 index 00000000..51fd267b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/proms/pooyan_sprite_grphx2.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sprite_grphx2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sprite_grphx2 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"12",X"34",X"69", + X"00",X"00",X"00",X"00",X"0C",X"C2",X"C2",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"4B",X"4B",X"0F",X"07",X"03",X"00",X"00",X"00", + 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X"00",X"00",X"0B",X"B4",X"87",X"0F",X"0F",X"0F",X"00",X"00",X"08",X"84",X"C2",X"68",X"2C",X"3C", + X"0F",X"0F",X"87",X"87",X"C3",X"E1",X"78",X"1E",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"87",X"87", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"1E",X"1E",X"0F",X"0F",X"0E",X"0E",X"0E",X"0E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/scandoubler.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/video_mixer.sv b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/video_mixer.sv new file mode 100644 index 00000000..4968eeda --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistRGB/rtl/video_mixer.sv @@ -0,0 +1,93 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // color + input [2:0] R, + input [2:0] G, + input [2:0] B, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +wire hs = HSync; +wire vs = VSync; + + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in({R,R}), + .G_in({G,G}), + .B_in({B,B}), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + + +assign VGA_R = red; +assign VGA_G = green; +assign VGA_B = blue; +assign VGA_VS = 1'b1; +assign VGA_HS = ~(HSync ^ VSync); + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/clean.bat b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/pooyan_mist.qpf b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/pooyan_mist.qpf new file mode 100644 index 00000000..f6253900 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/pooyan_mist.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 11:17:10 October 25, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "11:17:10 October 25, 2017" + +# Revisions + +PROJECT_REVISION = "pooyan_mist" diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/pooyan_mist.qsf b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/pooyan_mist.qsf new file mode 100644 index 00000000..eee0e35c --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/pooyan_mist.qsf @@ -0,0 +1,164 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:18:08 November 05, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# pooyan_mist_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name TOP_LEVEL_ENTITY pooyan_mist + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" + +# Fitter Assignments +# ================== +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + + + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 + + + +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE rtl/pooyan_mist.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sprite_grphx2.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sprite_grphx1.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sprite_color_lut.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_sound_prog.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_prog.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_palette.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_char_grphx2.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_char_grphx1.vhd +set_global_assignment -name VHDL_FILE rtl/proms/pooyan_char_color_lut.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80se.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name QIP_FILE rtl/mist_pll_12M_14M.qip +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_video.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/pooyan_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/pooyan.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/DebugSystem.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/DebugSystem.vhd new file mode 100644 index 00000000..27f115c9 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/DebugSystem.vhd @@ -0,0 +1,197 @@ +-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs +-- that can be synthesized and used with +-- the NoICE debugger that can be found at +-- http://www.noicedebugger.com/ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity DebugSystem is + port( + Reset_n : in std_logic; + Clk : in std_logic; + NMI_n : in std_logic; + RXD0 : in std_logic; + CTS0 : in std_logic; + DSR0 : in std_logic; + RI0 : in std_logic; + DCD0 : in std_logic; + RXD1 : in std_logic; + CTS1 : in std_logic; + DSR1 : in std_logic; + RI1 : in std_logic; + DCD1 : in std_logic; + TXD0 : out std_logic; + RTS0 : out std_logic; + DTR0 : out std_logic; + TXD1 : out std_logic; + RTS1 : out std_logic; + DTR1 : out std_logic; +As : out std_logic_vector(15 downto 0); +Ds : out std_logic_vector(7 downto 0); +ROM_Ds : out std_logic_vector(7 downto 0) + ); +end DebugSystem; + +architecture struct of DebugSystem is + + signal M1_n : std_logic; + signal MREQ_n : std_logic; + signal IORQ_n : std_logic; + signal RD_n : std_logic; + signal WR_n : std_logic; + signal RFSH_n : std_logic; + signal HALT_n : std_logic; + signal WAIT_n : std_logic; + signal INT_n : std_logic; + signal RESET_s : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal A : std_logic_vector(15 downto 0); + signal D : std_logic_vector(7 downto 0); + signal ROM_D : std_logic_vector(7 downto 0); + signal SRAM_D : std_logic_vector(7 downto 0); + signal UART0_D : std_logic_vector(7 downto 0); + signal UART1_D : std_logic_vector(7 downto 0); + signal CPU_D : std_logic_vector(7 downto 0); + + signal Mirror : std_logic; + + signal IOWR_n : std_logic; + signal RAMCS_n : std_logic; + signal UART0CS_n : std_logic; + signal UART1CS_n : std_logic; + + signal BaudOut0 : std_logic; + signal BaudOut1 : std_logic; + +begin + As <= A; + Ds <= D; + ROM_Ds <= ROM_D; + + Wait_n <= '1'; + BusRq_n <= '1'; + INT_n <= '1'; + + process (Reset_n, Clk) + begin + if Reset_n = '0' then + Reset_s <= '0'; + Mirror <= '0'; + elsif Clk'event and Clk = '1' then + Reset_s <= '1'; + if IORQ_n = '0' and A(7 downto 4) = "1111" then + Mirror <= D(0); + end if; + end if; + end process; + + IOWR_n <= WR_n or IORQ_n; + RAMCS_n <= (not Mirror and not A(15)) or MREQ_n; + UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1'; + UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1'; + +-- CPU_D <= +-- SRAM_D when RAMCS_n = '0' else +-- UART0_D when UART0CS_n = '0' else +-- UART1_D when UART1CS_n = '0' else +-- ROM_D; + + CPU_D <= + ROM_D; + + u0 : entity work.T80s + generic map(Mode => 0, T2Write => 1, IOWait => 0) +-- generic map(Mode => 1, T2Write => 1, IOWait => 0) + port map( + RESET_n => RESET_s, + CLK_n => Clk, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + RD_n => RD_n, + WR_n => WR_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + A => A, + DI => CPU_D, + DO => D); + + -- u1 : entity work.MonZ80 + -- port map( + -- Clk => Clk, + -- A => A(10 downto 0), + -- D => ROM_D); + + u1 : entity work.bagmanrom + port map( + clock => not Clk, + address => A(14 downto 0), + q => ROM_D); + + u2 : entity work.SSRAM + generic map( + AddrWidth => 12) + port map( + Clk => Clk, + CE_n => RAMCS_n, + WE_n => WR_n, + A => A(11 downto 0), + DIn => D, + DOut => SRAM_D); + + u3 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut0, + CS_n => UART0CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A(2 downto 0), + D_In => D, + D_Out => UART0_D, + SIn => RXD0, + CTS_n => CTS0, + DSR_n => DSR0, + RI_n => RI0, + DCD_n => DCD0, + SOut => TXD0, + RTS_n => RTS0, + DTR_n => DTR0, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut0, + Intr => open); + + u4 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut1, + CS_n => UART1CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A(2 downto 0), + D_In => D, + D_Out => UART1_D, + SIn => RXD1, + CTS_n => CTS1, + DSR_n => DSR1, + RI_n => RI1, + DCD_n => DCD1, + SOut => TXD1, + RTS_n => RTS1, + DTR_n => DTR1, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut1, + Intr => open); + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/DebugSystemXR.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/DebugSystemXR.vhd new file mode 100644 index 00000000..ca8fa877 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/DebugSystemXR.vhd @@ -0,0 +1,185 @@ +-- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs +-- that can be synthesized and used with +-- the NoICE debugger that can be found at +-- http://www.noicedebugger.com/ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity DebugSystemXR is + port( + Reset_n : in std_logic; + Clk : in std_logic; + NMI_n : in std_logic; + OE_n : out std_logic; + WE_n : out std_logic; + RAMCS_n : out std_logic; + ROMCS_n : out std_logic; + PGM_n : out std_logic; + A : out std_logic_vector(16 downto 0); + D : inout std_logic_vector(7 downto 0); + RXD0 : in std_logic; + CTS0 : in std_logic; + DSR0 : in std_logic; + RI0 : in std_logic; + DCD0 : in std_logic; + RXD1 : in std_logic; + CTS1 : in std_logic; + DSR1 : in std_logic; + RI1 : in std_logic; + DCD1 : in std_logic; + TXD0 : out std_logic; + RTS0 : out std_logic; + DTR0 : out std_logic; + TXD1 : out std_logic; + RTS1 : out std_logic; + DTR1 : out std_logic + ); +end entity DebugSystemXR; + +architecture struct of DebugSystemXR is + + signal M1_n : std_logic; + signal MREQ_n : std_logic; + signal IORQ_n : std_logic; + signal RD_n : std_logic; + signal WR_n : std_logic; + signal RFSH_n : std_logic; + signal HALT_n : std_logic; + signal WAIT_n : std_logic; + signal INT_n : std_logic; + signal RESET_s : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal D_i : std_logic_vector(7 downto 0); + signal ROM_D : std_logic_vector(7 downto 0); + signal UART0_D : std_logic_vector(7 downto 0); + signal UART1_D : std_logic_vector(7 downto 0); + signal CPU_D : std_logic_vector(7 downto 0); + + signal Mirror : std_logic; + + signal IOWR_n : std_logic; + signal RAMCS_n_i : std_logic; + signal UART0CS_n : std_logic; + signal UART1CS_n : std_logic; + + signal BaudOut0 : std_logic; + signal BaudOut1 : std_logic; + +begin + + Wait_n <= '1'; + BusRq_n <= '1'; + INT_n <= '1'; + + OE_n <= RD_n; + WE_n <= WR_n; + RAMCS_n <= RAMCS_n_i; + ROMCS_n <= '1'; + PGM_n <= '1'; + A(14 downto 0) <= A_i(14 downto 0); + A(16 downto 15) <= "00"; + D <= D_i when WR_n = '0' else "ZZZZZZZZ"; + + process (Reset_n, Clk) + begin + if Reset_n = '0' then + Reset_s <= '0'; + Mirror <= '0'; + elsif Clk'event and Clk = '1' then + Reset_s <= '1'; + if IORQ_n = '0' and A_i(7 downto 4) = "1111" then + Mirror <= D_i(0); + end if; + end if; + end process; + + IOWR_n <= WR_n or IORQ_n; + RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n; + UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1'; + UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1'; + + CPU_D <= + D when RAMCS_n_i = '0' else + UART0_D when UART0CS_n = '0' else + UART1_D when UART1CS_n = '0' else + ROM_D; + + u0 : entity work.T80s + generic map(Mode => 1, T2Write => 1, IOWait => 0) + port map( + RESET_n => RESET_s, + CLK_n => Clk, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + RD_n => RD_n, + WR_n => WR_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + A => A_i, + DI => CPU_D, + DO => D_i); + + u1 : entity work.MonZ80 + port map( + Clk => Clk, + A => A_i(10 downto 0), + D => ROM_D); + + u3 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut0, + CS_n => UART0CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A_i(2 downto 0), + D_In => D_i, + D_Out => UART0_D, + SIn => RXD0, + CTS_n => CTS0, + DSR_n => DSR0, + RI_n => RI0, + DCD_n => DCD0, + SOut => TXD0, + RTS_n => RTS0, + DTR_n => DTR0, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut0, + Intr => open); + + u4 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut1, + CS_n => UART1CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A_i(2 downto 0), + D_In => D_i, + D_Out => UART1_D, + SIn => RXD1, + CTS_n => CTS1, + DSR_n => DSR1, + RI_n => RI1, + DCD_n => DCD1, + SOut => TXD1, + RTS_n => RTS1, + DTR_n => DTR1, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut1, + Intr => open); + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T8080se.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T8080se.vhd new file mode 100644 index 00000000..2b6d28f8 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T8080se.vhd @@ -0,0 +1,185 @@ +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_ALU.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_MCode.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_Pack.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_Reg.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80se.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80se.vhd new file mode 100644 index 00000000..ac8886a8 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/T80se.vhd @@ -0,0 +1,184 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/YM2149_linmix_sep.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..27f26749 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,553 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/dac.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/dac.vhd new file mode 100644 index 00000000..9f696b0b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/gen_ram.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/gen_video.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/gen_video.vhd new file mode 100644 index 00000000..da8d77d4 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/gen_video.vhd @@ -0,0 +1,70 @@ +--------------------------------------------------------------------------------- +-- Galaga video horizontal/vertical and sync generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.ALL; + +entity gen_video is +port( + clk : in std_logic; + enable : in std_logic; + hcnt : out std_logic_vector(5 downto 0); + vcnt : out std_logic_vector(5 downto 0); + hsync : out std_logic; + vsync : out std_logic; + blankn : out std_logic +); +end gen_video; + +architecture struct of gen_video is + signal hblank : std_logic; + signal vblank : std_logic; + signal hcntReg : unsigned (5 DOWNTO 0) := to_unsigned(000,9); + signal vcntReg : unsigned (5 DOWNTO 0) := to_unsigned(015,9); +begin + +hcnt <= std_logic_vector(hcntReg); +vcnt <= std_logic_vector(vcntReg); + + +process(clk) begin + + if enable = '1' then + + if hcntReg = 511 then + hcntReg <= to_unsigned (128,9); + else + hcntReg <= hcntReg + 1; + end if; + + if hcntReg = 191 then + if vcntReg = 261 then + vcntReg <= to_unsigned(0,9); + else + vcntReg <= vcntReg + 1; + end if; + end if; + + if hcntReg = (175+ 0-8+8) then hsync <= '1'; -- 1 + elsif hcntReg = (175+29-8+8) then hsync <= '0'; + end if; + + if vcntReg = 252 then vsync <= '1'; + elsif vcntReg = 260 then vsync <= '0'; + end if; + + if hcntReg = (127+16+8) then hblank <= '1'; + elsif hcntReg = (255-17+8+1) then hblank <= '0'; + end if; + + if vcntReg = (240+1-1) then vblank <= '1'; + elsif vcntReg = (015+1) then vblank <= '0'; + end if; + + blankn <= not (hblank or vblank); + end if; + +end process; + +end architecture; \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/hq2x.sv b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/hq2x.sv new file mode 100644 index 00000000..3e406318 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bxx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/keyboard.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/keyboard.v new file mode 100644 index 00000000..70c8a56e --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/keyboard.v @@ -0,0 +1,83 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 +// 'h26: joystick[2] <= ~release_btn; +// 'h25: joystick[2] <= ~release_btn; + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_io.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_pll_12M_14M.qip b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_pll_12M_14M.qip new file mode 100644 index 00000000..02816126 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_pll_12M_14M.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.ppf"] diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_pll_12M_14M.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_pll_12M_14M.vhd new file mode 100644 index 00000000..4865e696 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/mist_pll_12M_14M.vhd @@ -0,0 +1,424 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: mist_pll_12M_14M.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY mist_pll_12M_14M IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END mist_pll_12M_14M; + + +ARCHITECTURE SYN OF mist_pll_12m_14m IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 420, + clk0_duty_cycle => 50, + clk0_multiply_by => 191, + clk0_phase_shift => "0", + clk1_divide_by => 360, + clk1_duty_cycle => 50, + clk1_multiply_by => 191, + clk1_phase_shift => "0", + clk2_divide_by => 105, + clk2_duty_cycle => 50, + clk2_multiply_by => 191, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=mist_pll_12M_14M", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "420" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "360" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "105" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.278571" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.325000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "49.114285" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "191" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.28800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "49.15200000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "mist_pll_12M_14M.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "420" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "360" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "105" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/osd.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/osd.v new file mode 100644 index 00000000..3e1815d1 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +//(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[1023:0]; // the OSD buffer itself +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [9:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan.vhd new file mode 100644 index 00000000..431ca119 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan.vhd @@ -0,0 +1,818 @@ +--------------------------------------------------------------------------------- +-- Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok + +-- Use with MAME roms from pooyan.zip +-- +-- Use make_pooyan_proms.bat to build vhd file from binaries +-- +-- Pooyan Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 32Kx8bits program rom +-- +-- One char tile map 32x28 +-- 8Kx16bits graphics rom 4bits/pixel +-- 16colors/16sets among 16 colors +-- +-- 24 sprites with priorities and flip H/V +-- 16Kx16bits graphics rom 4bits/pixel +-- 15 colors/16sets among 16 colors (different of char colors). +-- +-- Char/sprites color palette 2x16 colors among 256 colors +-- 3red 3green 2blue +-- +-- Working ram : 4Kx8bits +-- Sprites data ram : 256x16bits +-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits + +-- SOUND : 1xZ80@1.79MHz CPU accessing its program rom, working ram, 2x-AY3-8910 +-- 16Kx8bits program rom +-- +-- 1xAY-3-8910 +-- I/O noise input and command/trigger from video board. +-- 3 sound channels +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- 6 RC filters with 4 states : transparent or cut 600Hz, 700Hz, 3.4KHz +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity pooyan is +port( + clock_12 : in std_logic; + clock_14 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(2 downto 0); + video_clk : out std_logic; + video_vblank : out std_logic; + video_hblank : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(10 downto 0); + + dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B / Coinage_A + dip_switch_2 : in std_logic_vector(7 downto 0); -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + + fire1 : in std_logic; + right1 : in std_logic; + left1 : in std_logic; + down1 : in std_logic; + up1 : in std_logic; + + fire2 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + down2 : in std_logic; + up2 : in std_logic; + + sw : in std_logic_vector(9 downto 0); + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end pooyan; + +architecture struct of pooyan is + + signal reset_n: std_logic; + signal clock_12n : std_logic; + signal clock_6 : std_logic := '0'; + signal clock_6n : std_logic; + signal clock_div : std_logic_vector(1 downto 0) := "00"; + + signal hcnt : std_logic_vector(5 downto 0); -- horizontal counter + signal vcnt : std_logic_vector(8 downto 0); -- vertical counter + signal pxcnt : std_logic_vector(2 downto 0); -- pixel counter + signal spcnt : std_logic_vector(4 downto 0); -- sprite counter + + signal csync : std_logic; + signal hsync0 : std_logic; + signal hsync1 : std_logic; + signal hsync2 : std_logic; + + signal hblank : std_logic; + signal vblank : std_logic; + + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_nmi_n : std_logic; + + signal cpu_rom_do : std_logic_vector( 7 downto 0); + + signal wram_addr : std_logic_vector(11 downto 0); + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal ch_graphx_addr_f: std_logic_vector(11 downto 0); + signal ch_graphx_addr : std_logic_vector(11 downto 0); + signal ch_graphx1_do : std_logic_vector( 7 downto 0); + signal ch_graphx2_do : std_logic_vector( 7 downto 0); + signal ch_pixels : std_logic_vector(15 downto 0); + signal ch_data1 : std_logic_vector( 7 downto 0); + signal ch_color_set : std_logic_vector(3 downto 0); + signal ch_palette_addr : std_logic_vector(7 downto 0); + signal ch_palette_do : std_logic_vector(7 downto 0); + + signal spram_addr : std_logic_vector(7 downto 0); + signal spram1_we : std_logic; + signal spram1_do : std_logic_vector(7 downto 0); + signal spram2_we : std_logic; + signal spram2_do : std_logic_vector(7 downto 0); + + signal sp_graphx_addr : std_logic_vector(11 downto 0); + signal sp_graphx1_do : std_logic_vector(7 downto 0); + signal sp_graphx2_do : std_logic_vector(7 downto 0); + signal vcnt_r : std_logic_vector(8 downto 0); + signal sp_line : std_logic_vector(7 downto 0); + signal sp_on_line : std_logic; + signal sp_attr : std_logic_vector(7 downto 0); + signal sp_posh : std_logic_vector(7 downto 0); + signal sp_pixels : std_logic_vector(15 downto 0); + signal sp_color_set : std_logic_vector(3 downto 0); + signal sp_palette_addr : std_logic_vector(7 downto 0); + signal sp_palette_do : std_logic_vector(7 downto 0); + signal sp_read_out : std_logic_vector(3 downto 0); + signal sp_blank : std_logic; + + signal rgb_palette_addr : std_logic_vector(4 downto 0); + signal rgb_palette_do : std_logic_vector(7 downto 0); + + signal sp_buffer_write_addr : std_logic_vector(7 downto 0); + signal sp_buffer_write_we : std_logic; + signal sp_buffer_read_addr : std_logic_vector(7 downto 0); + + signal sp_buffer_ram1_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram1_we : std_logic; + signal sp_buffer_ram1_di : std_logic_vector(3 downto 0); + signal sp_buffer_ram1_do : std_logic_vector(3 downto 0); + + signal sp_buffer_ram2_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram2_we : std_logic; + signal sp_buffer_ram2_di : std_logic_vector(3 downto 0); + signal sp_buffer_ram2_do : std_logic_vector(3 downto 0); + + signal sp_buffer_sel : std_logic; + + signal itt_n : std_logic; + signal flip : std_logic; + signal A10x_we : std_logic; + signal A18x_we : std_logic; + signal sound_cmd : std_logic_vector(7 downto 0); + signal sound_trig : std_logic; + + signal input_0 : std_logic_vector(7 downto 0); + signal input_1 : std_logic_vector(7 downto 0); + signal input_2 : std_logic_vector(7 downto 0); + +begin +video_clk <= clock_6n; +clock_12n <= not clock_12; +clock_6n <= not clock_6; +reset_n <= not reset; + +-- debug +process (reset, clock_12) +begin + if rising_edge(clock_12) and cpu_ena ='1' and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-- make 6MHz clock from 12MHz +process (clock_12) +begin + if reset='1' then + clock_6 <= '0'; + else + if rising_edge(clock_12) then + clock_6 <= not clock_6; + end if; + end if; +end process; + + +-------------------------- +-- Video/sprite scanner -- +-------------------------- + +-- make hcnt and vcnt video scanner from pixel clocks and counts +-- +-- pxcnt |0|1|2|3|4|5|6|7|0|1|2|3|4|5|6|7| +-- hcnt | N | N+1 | +-- cpu_adr/do | | + +-- +-- hcnt [0..47] => 48 x 8 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz) +-- vcnt [252..255,256..511] => 260 lines, 1 frame is 260 x 62.5us = 16.250ms (61.54Hz) + +process (reset, clock_6) +begin + if reset='1' then + pxcnt <= "000"; + hcnt <= "000000"; + vcnt <= '0'&X"FC"; + spcnt <= "00000"; + else + if rising_edge(clock_6) then + pxcnt <= pxcnt + '1'; + if pxcnt = "111" then + hcnt <= hcnt + '1'; + + if hcnt = "101111" then -- char from #0 to #47 (one line) + hcnt <= "000000"; + if vcnt = '1'&X"FF" then + vcnt <= '0'&X"FC"; + else + vcnt <= vcnt + '1'; + end if; + end if; + + -- sprite down counter + if hcnt(0) = '1' then -- every is 16 bits (2 char) + if hcnt = "101111" then + spcnt <= "01000"; -- start with sprite #8 + else + spcnt <= spcnt + '1'; -- upto sprite #31 + end if; + end if; + + end if; + end if; + end if; +end process; + +cpu_ena <= not pxcnt(0); + +-- inputs +input_0 <= "111" & not start2 & not start1 & '1' & '1' & not coin1; -- ?/ ?/ ?/ 2S/ 1S/SVC/ C2/ C1 +input_1 <= "111" & not fire1 & not down1 & not up1 & not right1 & not left1; -- ?/1FL/1SR/1SL/1DW/1UP/1RI/1LE +input_2 <= "111" & not fire2 & not down2 & not up2 & not right2 & not left2; -- ?/2FL/2SR/2SL/2DW/2UP/2RI/2LE + +-- cpu input address decoding (mirror mostly from Mame) +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"8" else -- 0000-7FFF + wram_do when cpu_addr(15 downto 12) = X"8" else -- 8000-8FFF + + spram1_do when cpu_addr(15 downto 12) = X"9" and + cpu_addr(10) = '0' else -- 9000-93FF + + spram2_do when cpu_addr(15 downto 12) = X"9" and + cpu_addr(10) = '1' else -- 9400-97FF + + dip_switch_2 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "000" else -- A000-A000 + + input_0 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "100" else -- A080-A080 + + input_1 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "101" else -- A0A0-A0A0 + + input_2 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "110" else -- A0C0-A0C0 + + dip_switch_1 when cpu_addr(15 downto 12) = X"A" and + cpu_addr( 7 downto 5) = "111" else -- A0E0-A0E0 + + X"FF"; + +-- working ram address multiplexer cpu/video scanner +wram_addr <= cpu_addr(11 downto 0) when cpu_ena = '1' else + '0' & pxcnt(1) & vcnt(7 downto 3) & hcnt(4 downto 0) when flip = '0' else + '0' & pxcnt(1) & not vcnt(7 downto 3) & not hcnt(4 downto 0); + +-- sprite data ram address multiplexer cpu/sprite scanner +spram_addr <= cpu_addr(7 downto 0) when cpu_ena = '1' else "00" & spcnt & pxcnt(1); + +-- write enable to working ram, sprite data ram and misc registers +wram_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"8" else '0'; +spram1_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"9" and cpu_addr(10) = '0' else '0'; +spram2_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"9" and cpu_addr(10) = '1' else '0'; +A10x_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" and cpu_addr(8 downto 7) = "10" else '0'; +A18x_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" and cpu_addr(8 downto 7) = "11" else '0'; + +-- Misc registers : interrupt enable/clear, cocktail flip, sound trigger +process (clock_6) +begin + if rising_edge(clock_6) then + if A10x_we = '1' then + sound_cmd <= cpu_do; + end if; + + if A18x_we = '1' then + if cpu_addr(2 downto 0) = "000" then itt_n <= cpu_do(0); end if; + if cpu_addr(2 downto 0) = "111" then flip <= not cpu_do(0); end if; + if cpu_addr(2 downto 0) = "001" then sound_trig <= cpu_do(0); end if; + end if; + + if itt_n = '0' then + cpu_nmi_n <= '1'; + else -- lauch nmi and end of frame + if (vcnt = 493) and (hcnt = "000000") and (pxcnt = "000") then + cpu_nmi_n <= '0'; + end if; + end if; + end if; +end process; + + +---------------------- +--- sprite machine --- +---------------------- +-- sprite data rams are scanned from sprites addresse 31 to 8 at each line + +-- latch current sprite data with respect to pixel and hcnt in relation +-- with sprite data ram addressing +process (clock_6) +begin + if rising_edge(clock_6) then + + if (hcnt(0) = '0') and (pxcnt = "001") then + sp_posh <= spram1_do ; -- a.k.a. X + sp_attr <= spram2_do ; -- color and flip x/y + vcnt_r <= vcnt; + end if; + + -- sprite is on current line if sp_line is below 16 + -- and if sprite vertical position (a.k.a. Y) is below xF0 + if (hcnt(0) = '0') and (pxcnt = "011") then + if sp_line(7 downto 4) = "0000" and spram2_do < X"F0" then + sp_on_line <= '1'; + else + sp_on_line <= '0'; + end if; + end if; + + -- delay sp_color_set + if (hcnt(0) = '0') and (pxcnt = "100") then + sp_color_set <= sp_attr(3 downto 0); + end if; + + end if; +end process; + +-- sp_line (valid only when pxcnt = "011") +sp_line <= not(vcnt_r(7 downto 0)) - spram2_do; + +-- address sprite graphics rom with sprite code and tile number and sprite line counter +-- with respect to sprite flip x/y controls +with sp_attr(7 downto 6) select + sp_graphx_addr <= spram1_do(5 downto 0) & sp_line(3) & hcnt(0) & pxcnt(2) & sp_line(2 downto 0) when "11", + spram1_do(5 downto 0) & sp_line(3) & not hcnt(0) & not pxcnt(2) & sp_line(2 downto 0) when "10", + spram1_do(5 downto 0) & not sp_line(3) & hcnt(0) & pxcnt(2) & not sp_line(2 downto 0) when "01", + spram1_do(5 downto 0) & not sp_line(3) & not hcnt(0) & not pxcnt(2) & not sp_line(2 downto 0) when others; + +-- latch and shift sprite graphics data with respect to flipx control +-- 16bits => 4x4bits = 4pixels / 16colors (15colors + transparent) +process (clock_6) +begin + if rising_edge(clock_6) then + + if pxcnt(1 downto 0) = "00" then + if sp_on_line = '1' then + if sp_attr(6) = '1' then + sp_pixels <= sp_graphx1_do & sp_graphx2_do; + else + sp_pixels( 3 downto 0) <= sp_graphx2_do(0) & sp_graphx2_do(1) & sp_graphx2_do(2) & sp_graphx2_do(3); + sp_pixels( 7 downto 4) <= sp_graphx2_do(4) & sp_graphx2_do(5) & sp_graphx2_do(6) & sp_graphx2_do(7); + sp_pixels(11 downto 8) <= sp_graphx1_do(0) & sp_graphx1_do(1) & sp_graphx1_do(2) & sp_graphx1_do(3); + sp_pixels(15 downto 12) <= sp_graphx1_do(4) & sp_graphx1_do(5) & sp_graphx1_do(6) & sp_graphx1_do(7); + end if; + else + sp_pixels <= (others => '0'); + end if; + else + sp_pixels( 3 downto 0) <= sp_pixels( 2 downto 0) & '0'; + sp_pixels( 7 downto 4) <= sp_pixels( 6 downto 4) & '0'; + sp_pixels(11 downto 8) <= sp_pixels(10 downto 8) & '0'; + sp_pixels(15 downto 12) <= sp_pixels(14 downto 12) & '0'; + end if; + + end if; + +end process; + +-- address sprite color palette 16colors/pixel, 16 sets => 16 colors +sp_palette_addr <= sp_color_set & sp_pixels(3) & sp_pixels(7) & sp_pixels(11) & sp_pixels(15); + +-- write sprite to line buffer at posh position +process (clock_6) +begin + if rising_edge(clock_6) then + if hcnt(0) = '0' and pxcnt = "101" then + sp_buffer_write_addr <= sp_posh; + else + sp_buffer_write_addr <= sp_buffer_write_addr + '1'; + end if; + end if; +end process; + +-- write colors to buffer when not transparent +sp_buffer_write_we <= '0' when sp_palette_do(3 downto 0) = "0000" else '1'; + +-- read sprite line buffer and erase after read +process (clock_12) +begin + if rising_edge(clock_12) then + if hcnt = "101111" and pxcnt = "111" then + sp_buffer_read_addr <= "11111010"; -- tune horizontal position of sprites + else + if clock_6 = '0' then + sp_buffer_read_addr <= sp_buffer_read_addr + '1'; + else + if vcnt(0) = '0' then + sp_read_out <= sp_buffer_ram1_do; + else + sp_read_out <= sp_buffer_ram2_do; + end if; + end if; + end if; + end if; +end process; + +-- toggle read/write sprite line buffer every other line + +-- wait pxcnt = "101" to allow last sprite (#31) to be written to line buffer +process (clock_6) +begin + if rising_edge(clock_6) then + if pxcnt = "101" then sp_buffer_sel <= vcnt(0); end if; + end if; +end process; + +sp_buffer_ram1_addr <= sp_buffer_read_addr when sp_buffer_sel = '0' else sp_buffer_write_addr; +sp_buffer_ram2_addr <= sp_buffer_read_addr when sp_buffer_sel = '1' else sp_buffer_write_addr; + +sp_buffer_ram1_di <= "0000" when sp_buffer_sel = '0' else sp_palette_do(3 downto 0); +sp_buffer_ram2_di <= "0000" when sp_buffer_sel = '1' else sp_palette_do(3 downto 0); + +sp_buffer_ram1_we <= not clock_6 when sp_buffer_sel = '0' else sp_buffer_write_we; +sp_buffer_ram2_we <= not clock_6 when sp_buffer_sel = '1' else sp_buffer_write_we; + +-------------------- +--- char machine --- +-------------------- + +-- latch current char data with respect to vcnt and hcnt in relation +-- with wram ram addressing +process (clock_6) +begin + if rising_edge(clock_6) and pxcnt = "001" then + ch_data1 <= wram_do ; + end if; + + if rising_edge(clock_6) and pxcnt = "100" then + ch_color_set <= ch_data1(3 downto 0) ; + end if; + +end process; + +-- address char graphics rom with char code, pixel count and vertical line counter +-- with respect to char flip x/y controls +with ch_data1(7 downto 6) select +ch_graphx_addr_f <= wram_do & pxcnt(2) & vcnt(2 downto 0) when "00", + wram_do & not pxcnt(2) & vcnt(2 downto 0) when "01", + wram_do & pxcnt(2) & not(vcnt(2 downto 0)) when "10", + wram_do & not pxcnt(2) & not(vcnt(2 downto 0)) when others; + +-- in cocktail flip mode negate h/v counters +ch_graphx_addr <= ch_graphx_addr_f when flip ='0' else ch_graphx_addr_f xor "000000001111"; + +-- latch and shift char graphics data with respect to flipx control and cocktail flip control +-- 16bits => 4x4bits = 4pixels / 16colors +process (clock_6) +begin + if rising_edge(clock_6) then + if pxcnt(1 downto 0) = "00" then + if (ch_data1(6) xor flip) = '0' then + ch_pixels <= ch_graphx1_do & ch_graphx2_do; + else + ch_pixels( 3 downto 0) <= ch_graphx2_do(0) & ch_graphx2_do(1) &ch_graphx2_do(2) &ch_graphx2_do(3); + ch_pixels( 7 downto 4) <= ch_graphx2_do(4) & ch_graphx2_do(5) &ch_graphx2_do(6) &ch_graphx2_do(7); + ch_pixels(11 downto 8) <= ch_graphx1_do(0) & ch_graphx1_do(1) &ch_graphx1_do(2) &ch_graphx1_do(3); + ch_pixels(15 downto 12) <= ch_graphx1_do(4) & ch_graphx1_do(5) &ch_graphx1_do(6) &ch_graphx1_do(7); + end if; + else + ch_pixels( 3 downto 0) <= ch_pixels( 2 downto 0) & '0'; + ch_pixels( 7 downto 4) <= ch_pixels( 6 downto 4) & '0'; + ch_pixels(11 downto 8) <= ch_pixels(10 downto 8) & '0'; + ch_pixels(15 downto 12) <= ch_pixels(14 downto 12) & '0'; + end if; + end if; + +end process; + +-- address char color palette 4 colors, 64 sets => 16 colors +with sw(4 downto 0) select +ch_palette_addr <= +ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(11) & ch_pixels(15) when '0'&X"0", +ch_color_set & ch_pixels(3) & ch_pixels( 7) & ch_pixels(15) & ch_pixels(11) when '0'&X"1", +ch_color_set & ch_pixels(3) & ch_pixels(11) & ch_pixels( 7) & ch_pixels(15) when '0'&X"2", +ch_color_set & ch_pixels(3) & ch_pixels(11) & ch_pixels(15) & ch_pixels( 7) when '0'&X"3", +ch_color_set & ch_pixels(3) & ch_pixels(15) & ch_pixels( 7) & ch_pixels(11) when '0'&X"4", +ch_color_set & ch_pixels(3) & ch_pixels(15) & ch_pixels(11) & ch_pixels( 7) when '0'&X"5", + +ch_color_set & ch_pixels(7) & ch_pixels( 3) & ch_pixels(11) & ch_pixels(15) when '0'&X"6", +ch_color_set & ch_pixels(7) & ch_pixels( 3) & ch_pixels(15) & ch_pixels(11) when '0'&X"7", +ch_color_set & ch_pixels(7) & ch_pixels(11) & ch_pixels( 3) & ch_pixels(15) when '0'&X"8", +ch_color_set & ch_pixels(7) & ch_pixels(11) & ch_pixels(15) & ch_pixels( 3) when '0'&X"9", +ch_color_set & ch_pixels(7) & ch_pixels(15) & ch_pixels( 3) & ch_pixels(11) when '0'&X"A", +ch_color_set & ch_pixels(7) & ch_pixels(15) & ch_pixels(11) & ch_pixels( 3) when '0'&X"B", + +ch_color_set & ch_pixels(11) & ch_pixels( 3) & ch_pixels( 7) & ch_pixels(15) when '0'&X"C", +ch_color_set & ch_pixels(11) & ch_pixels( 3) & ch_pixels(15) & ch_pixels( 7) when '0'&X"D", +ch_color_set & ch_pixels(11) & ch_pixels( 7) & ch_pixels( 3) & ch_pixels(15) when '0'&X"E", +ch_color_set & ch_pixels(11) & ch_pixels( 7) & ch_pixels(15) & ch_pixels( 3) when '0'&X"F", +ch_color_set & ch_pixels(11) & ch_pixels(15) & ch_pixels( 3) & ch_pixels( 7) when '1'&X"0", +ch_color_set & ch_pixels(11) & ch_pixels(15) & ch_pixels( 7) & ch_pixels( 3) when '1'&X"1", + +ch_color_set & ch_pixels(15) & ch_pixels( 3) & ch_pixels( 7) & ch_pixels(11) when '1'&X"2", +ch_color_set & ch_pixels(15) & ch_pixels( 3) & ch_pixels(11) & ch_pixels( 7) when '1'&X"3", +ch_color_set & ch_pixels(15) & ch_pixels( 7) & ch_pixels( 3) & ch_pixels(11) when '1'&X"4", +ch_color_set & ch_pixels(15) & ch_pixels( 7) & ch_pixels(11) & ch_pixels( 3) when '1'&X"5", +ch_color_set & ch_pixels(15) & ch_pixels(11) & ch_pixels( 3) & ch_pixels( 7) when '1'&X"6", +ch_color_set & ch_pixels(15) & ch_pixels(11) & ch_pixels( 7) & ch_pixels( 3) when others; + +--------------------- +-- mux char/sprite -- +--------------------- + +-- char data controls sprite display/hide +--process (clock_6) +--begin +-- if rising_edge(clock_6) then +-- sp_blank <= ch_color_set(4); +-- end if; +--end process; + +-- select rbg color and bank with respect to char/sprite selection +rgb_palette_addr <= +-- '1' & ch_palette_do(3 downto 0) when (sp_read_out = "0000" or sp_blank = '1') else + '1' & ch_palette_do(3 downto 0) when (sp_read_out = "0000" ) else + '0' & sp_read_out; + + + + +-- register and assign rbg palette output +process (clock_6) +begin + if rising_edge(clock_6) then + if hblank = '1' or vblank = '1' then + video_r <= "000"; + video_g <= "000"; + video_b <= "000"; + else + video_r <= rgb_palette_do(2 downto 0); + video_g <= rgb_palette_do(5 downto 3); + video_b <= rgb_palette_do(7 downto 6) & '0'; + end if; + end if; +end process; + +video_hblank <= hblank; +video_vblank <= vblank; + +---------------------------- +-- video syncs and blanks -- +---------------------------- + +process(clock_6) + constant hcnt_base : integer := 36; + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + if rising_edge(clock_6) and pxcnt = "110" then + + if hcnt = hcnt_base+0 then hsync0 <= '0'; + elsif hcnt = hcnt_base+3 then hsync0 <= '1'; + end if; + + if hcnt = hcnt_base then + if vcnt = 500 then + vsync_cnt := X"0"; + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if; + end if; + end if; + + if hcnt = hcnt_base-4 then + hblank <= '1'; + if vcnt = 496 then + vblank <= '1'; -- 492 ok + elsif vcnt = 262 then + vblank <= '0'; -- 262 ok + end if; + elsif hcnt = 0 then + hblank <= '0'; + end if; + + video_hs <= hsync0; + + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 8 then video_vs <= '1'; + end if; + + end if; +end process; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_6, + CLKEN => cpu_ena, + WAIT_n => '1', + INT_n => '1', --cpu_irq_n, + NMI_n => cpu_nmi_n, + BUSRQ_n => '1', + M1_n => open, + MREQ_n => cpu_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.pooyan_prog +port map( + clk => clock_6n, + addr => cpu_addr(14 downto 0), + data => cpu_rom_do +); + +-- working/char RAM 0x8000-0x8FFF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_6n, + we => wram_we, + addr => wram_addr, + d => cpu_do, + q => wram_do +); + +-- sprite RAM1 0x9000-0x90FF +spram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_6n, + we => spram1_we, + addr => spram_addr, + d => cpu_do, + q => spram1_do +); + +-- sprite RAM2 0x9400-0x94FF +spram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_6n, + we => spram2_we, + addr => spram_addr, + d => cpu_do, + q => spram2_do +); + +-- sprite line buffer 1 +splinebuf1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_12n, + we => sp_buffer_ram1_we, + addr => sp_buffer_ram1_addr, + d => sp_buffer_ram1_di, + q => sp_buffer_ram1_do +); + +-- sprite line buffer 2 +splinebuf2 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_12n, + we => sp_buffer_ram2_we, + addr => sp_buffer_ram2_addr, + d => sp_buffer_ram2_di, + q => sp_buffer_ram2_do +); + +-- char graphics ROM G10 +char_graphics_1 : entity work.pooyan_char_grphx1 +port map( + clk => clock_6, + addr => ch_graphx_addr, + data => ch_graphx1_do +); + +-- char graphics ROM G9 +char_graphics_2 : entity work.pooyan_char_grphx2 +port map( + clk => clock_6, + addr => ch_graphx_addr, + data => ch_graphx2_do +); + +-- char palette ROM +ch_palette : entity work.pooyan_char_color_lut +port map( + clk => clock_6, + addr => ch_palette_addr, + data => ch_palette_do +); + +-- sprite graphics ROM A9 +sp_graphics_1 : entity work.pooyan_sprite_grphx1 +port map( + clk => clock_6, + addr => sp_graphx_addr, + data => sp_graphx1_do +); + +-- sprite graphics ROM A8 +sp_graphics_2 : entity work.pooyan_sprite_grphx2 +port map( + clk => clock_6, + addr => sp_graphx_addr, + data => sp_graphx2_do +); + +-- sprite palette ROM +sp_palette : entity work.pooyan_sprite_color_lut +port map( + clk => clock_6, + addr => sp_palette_addr, + data => sp_palette_do +); + +-- rgb palette ROM +rgb_palette_gb : entity work.pooyan_palette +port map( + clk => clock_6, + addr => rgb_palette_addr, + data => rgb_palette_do +); + + +-- sound board +pooyan_sound_board : entity work.pooyan_sound_board +port map( + clock_14 => clock_14, + reset => reset, + sound_trig => sound_trig, + sound_cmd => sound_cmd, + audio_out => audio_out, + dbg_cpu_addr => open + ); + +end struct; \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan_mist.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan_mist.vhd new file mode 100644 index 00000000..c1df8803 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan_mist.vhd @@ -0,0 +1,303 @@ +--------------------------------------------------------------------------------- +-- Mist Top level for Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Use time_pilot_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +-- Uses 1 pll for 12MHz and 14MHz generation from 27MHz +-- +-- Mist key : +-- Right Button : reset game +-- +-- Keyboard players inputs : +-- +-- ESC : Add coin +-- 2 : Start 2 players +-- 1 : Start 1 player +-- SPACE : Fire +-- RIGHT arrow : rotate right +-- LEFT arrow : rotate left +-- UP arrow : rotate up +-- DOWN arrow : rotate down +-- +-- Other details : see time_pilot.vhd + +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; + +entity pooyan_mist is +port( + CLOCK_27 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0); + VGA_VS : out std_logic; + VGA_HS : out std_logic; + LED : out std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic +); +end pooyan_mist; + +architecture struct of pooyan_mist is + + signal clock_48 : std_logic; + signal clock_12 : std_logic; + signal clock_14 : std_logic; + signal reset : std_logic; + signal pll_locked: std_logic; + + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic; + signal audio : std_logic_vector(10 downto 0); + signal audio_pwm : std_logic; + + signal reset_n : std_logic; + signal ps2_clk : std_logic; + signal ps2_dat : std_logic; + signal joy_u : std_logic; + signal joy_l : std_logic; + signal joy_r : std_logic; + signal joy_d : std_logic; + signal kbd_intr : std_logic; + signal kbd_scancode : std_logic_vector(7 downto 0); + + + signal scanlines : std_logic_vector(1 downto 0); + signal hq2x : std_logic; + + -- User IO + signal buttons : std_logic_vector(1 downto 0); + signal joy0 : std_logic_vector(7 downto 0); + signal joy1 : std_logic_vector(7 downto 0); + signal status : std_logic_vector(31 downto 0); + signal scandoubler_disable : std_logic; + signal ypbpr : std_logic; + signal pix_ce : std_logic; + signal kbd_joy0 : std_logic_vector(9 downto 0); + signal ps2Clk : std_logic; + signal ps2Data : std_logic; + signal ps2_scancode : std_logic_vector(7 downto 0); + + signal VGA_R_O : std_logic_vector(2 downto 0); + signal VGA_G_O : std_logic_vector(2 downto 0); + signal VGA_B_O : std_logic_vector(2 downto 0); + signal newState : std_logic_vector(2 downto 0); + signal upright : boolean; + constant CONF_STR : string := + "POOYAN;;O4,Joystick Control,Upright,Normal;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;"; + + + function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + end function; + + component mist_io + generic ( STRLEN : integer := 0 ); + port ( + clk_sys :in std_logic; + SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; + SPI_DO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + buttons : out std_logic_vector(1 downto 0); + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + status : out std_logic_vector(31 downto 0); + scandoubler_disable, ypbpr : out std_logic; + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); + end component mist_io; + + component video_mixer + generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 ); + port ( + clk_sys, ce_pix, ce_pix_actual : in std_logic; + SPI_SCK, SPI_SS3, SPI_DI : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; + R, G, B : in std_logic_vector(2 downto 0); + HSync, VSync, line_start, mono : in std_logic; + VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); + VGA_VS, VGA_HS : out std_logic + ); + end component video_mixer; + + component keyboard + PORT( + clk : in std_logic; + reset : in std_logic; + ps2_kbd_clk : in std_logic; + ps2_kbd_data : in std_logic; + joystick : out std_logic_vector (9 downto 0) + ); + end component; + +begin + +reset <= status(0) or status(5) or buttons(1) or not pll_locked; + +clocks : entity work.mist_pll_12M_14M + port map( + inclk0 => CLOCK_27, + c0 => clock_12,--12.28800000 + c1 => clock_14,--14.31800000 + c2 => clock_48,--49.15200000 + locked => pll_locked +); + +scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0'; +scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0'; +hq2x <= '1' when status(9 downto 8) = "01" else '0'; + +vmixer : video_mixer + port map ( + clk_sys => clock_48, + ce_pix => pix_ce, + ce_pix_actual => pix_ce, + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + scanlines => scanlines, + scandoubler_disable => scandoubler_disable, + hq2x => hq2x, + ypbpr => ypbpr, + ypbpr_full => '1', + R => VGA_R_O, + G => VGA_G_O, + B => VGA_B_O, + HSync => hsync, + VSync => vsync, + line_start => '0', + mono => '0', + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_VS => VGA_VS, + VGA_HS => VGA_HS +); + +mist_io_inst : mist_io + generic map (STRLEN => CONF_STR'length) + port map ( + clk_sys => clock_48, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_DI => SPI_DI, + SPI_DO => SPI_DO, + conf_str => to_slv(CONF_STR), + buttons => buttons, + scandoubler_disable => scandoubler_disable, + ypbpr => ypbpr, + joystick_1 => joy1, + joystick_0 => joy0, + status => status, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data +); + +Joy_r <= joy0(0) or joy1(0) or kbd_joy0(7) when upright + else joy0(3) or joy1(3) or kbd_joy0(4); +Joy_l <= joy0(1) or joy1(1) or kbd_joy0(6) when upright + else joy0(2) or joy1(2) or kbd_joy0(5); +Joy_u <= joy0(3) or joy1(3) or kbd_joy0(4) when upright + else joy0(1) or joy1(1) or kbd_joy0(6); +Joy_d <= joy0(2) or joy1(2) or kbd_joy0(5) when upright + else joy0(0) or joy1(0) or kbd_joy0(7); + +process(kbd_joy0(9)) +begin + if kbd_joy0(9)= '1' then + upright <= not upright; + end if; +end process; + +--upright <= kbd_joy0(9);--Control Direction + +pooyan : entity work.pooyan + port map( + clock_12 => clock_12, + clock_14 => clock_14, + reset => reset, + video_r => VGA_R_O, + video_g => VGA_G_O, + video_b => VGA_B_O, + video_hblank => open, + video_vblank => open, + video_clk => pix_ce, + video_hs => hsync, + video_vs => vsync, + audio_out => audio, + dip_switch_1 => X"FF", -- Coinage_B / Coinage_A + dip_switch_2 => X"FB", -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + start2 => kbd_joy0(2) or status(3), + start1 => kbd_joy0(1) or status(2), + coin1 => kbd_joy0(3) or status(1), + fire1 => joy0(4) or joy1(4) or kbd_joy0(0), + right1 => Joy_r, + left1 => Joy_l, + down1 => Joy_d, + up1 => Joy_u, + fire2 => joy0(4) or joy1(4) or kbd_joy0(0), + right2 => Joy_r, + left2 => Joy_l, + down2 => Joy_d, + up2 => Joy_u, + sw => "0000000000", + dbg_cpu_addr => open +); + + +u_keyboard : keyboard + port map( + clk => clock_48, + reset => reset, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data, + joystick => kbd_joy0 +); + +u_dac : entity work.dac + port map( + clk_i => clock_48, + res_n_i => not reset, + dac_i => audio, + dac_o => audio_pwm +); + +AUDIO_L <= audio_pwm; +AUDIO_R <= audio_pwm; + + LED <= '1'; +end struct; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan_sound_board.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan_sound_board.vhd new file mode 100644 index 00000000..a4b38c7d --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/pooyan_sound_board.vhd @@ -0,0 +1,426 @@ +--------------------------------------------------------------------------------- +-- Pooyan sound board by Dar (darfpga@aol.fr) (08/11/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity pooyan_sound_board is +port( + clock_14 : in std_logic; + reset : in std_logic; + + sound_cmd : in std_logic_vector(7 downto 0); + sound_trig : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end pooyan_sound_board; + +architecture struct of pooyan_sound_board is + + signal reset_n: std_logic; + signal clock_14n : std_logic; + + signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0'); + signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0'); + + signal cpu_clock : std_logic; + signal ayx_clock : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_iorq_n : std_logic; + signal cpu_m1_n : std_logic; + + signal cpu_rom_do : std_logic_vector( 7 downto 0); + signal wram_do : std_logic_vector( 7 downto 0); + signal wram_we : std_logic; + + signal clr_irq_n : std_logic; + signal sen1_n : std_logic; + signal sen2_n : std_logic; + signal sen3_n : std_logic; + signal sen4_n : std_logic; + + signal sound_trig_r : std_logic; + + signal ay1_do : std_logic_vector(7 downto 0); + signal ay1_cs_n : std_logic; + signal ay1_bdir : std_logic; + signal ay1_bc1 : std_logic; + signal ay1_audio_muxed : std_logic_vector(7 downto 0); + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_port_b_di : std_logic_vector(7 downto 0); + + signal ay2_do : std_logic_vector(7 downto 0); + signal ay2_cs_n : std_logic; + signal ay2_bdir : std_logic; + signal ay2_bc1 : std_logic; + signal ay2_audio_muxed : std_logic_vector(7 downto 0); + signal ay2_audio_chan : std_logic_vector(1 downto 0); + + signal ay1_chan_a : std_logic_vector(7 downto 0); + signal ay1_chan_b : std_logic_vector(7 downto 0); + signal ay1_chan_c : std_logic_vector(7 downto 0); + signal ay2_chan_a : std_logic_vector(7 downto 0); + signal ay2_chan_b : std_logic_vector(7 downto 0); + signal ay2_chan_c : std_logic_vector(7 downto 0); + + signal filter_cmd_we : std_logic; + signal filter_cmd : std_logic_vector(11 downto 0); + signal mult_cmd : std_logic_vector(1 downto 0); + signal mult_value : integer range 0 to 779; + + signal Vc_1a : integer range -256*1024 to 256*1024-1; + signal Vc_1b : integer range -256*1024 to 256*1024-1; + signal Vc_1c : integer range -256*1024 to 256*1024-1; + signal Vc_2a : integer range -256*1024 to 256*1024-1; + signal Vc_2b : integer range -256*1024 to 256*1024-1; + signal Vc_2c : integer range -256*1024 to 256*1024-1; + signal Vc : integer range -256*1024 to 256*1024-1; + signal Vin : integer range -256 to 255; + signal dV : integer range -512 to 511; + signal Vcn_a : integer range -1024*1024 to 1024*1024-1; + signal Vcn_b : integer range -1024*1024 to 1024*1024-1; + signal Vcn_c : integer range -256*1024 to 256*1024-1; + +begin + +clock_14n <= not clock_14; +reset_n <= not reset; + +-- debug +process (reset, clock_14) +begin + if rising_edge(clock_14) and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-------------------------------------------------------- +-- RC filters equation +-- +-- Vc : capacitor voltage = output voltage +-- fs : sample frequency +-- Vin : voltage at resistor input +-- +-- Vc(k+1) = Vc(k) + (Vin-Vc(k))/(fs.R.C) +-- +-- Vcn * 1024 <= Vcn * 1024 + (Vin-Vc) * 1024/(fs.R.C) +-- With Vcn = 1024 * Vc +-------------------------------------------------------- +-- Filters will be run at 14.318MHz/512 = 27.96KHz +-------------------------------------------------------- +-- 6 filters have to be implemented +-- RC equation is time multiplexed to save multiplier +-- for small FPGA +-------------------------------------------------------- + +-- mux Vc +with clock_div1(3 downto 0) select +Vc <= Vc_1a when X"0", -- Vc_xy : [0..255*1024] + Vc_1b when X"1", -- => Vc : [-256*1024..255*1024] + Vc_1c when X"2", + Vc_2a when X"3", + Vc_2b when X"4", + Vc_2c when others; + +-- mux Vin +with clock_div1(3 downto 0) select +Vin <= to_integer(unsigned(ay1_chan_a)) when X"0", -- ayx_chan_y : [0..255] + to_integer(unsigned(ay1_chan_b)) when X"1", -- => Vin : [-256:255] + to_integer(unsigned(ay1_chan_c)) when X"2", + to_integer(unsigned(ay2_chan_a)) when X"3", + to_integer(unsigned(ay2_chan_b)) when X"4", + to_integer(unsigned(ay2_chan_c)) when others; + +-- compute dV +dV <= Vin-Vc/1024; -- Vc/1024 : [0..255], dv : [-255..511] => [-512..511] + +-- mux filter cmd +with clock_div1(3 downto 0) select +mult_cmd <= filter_cmd( 7 downto 6) when X"0", + filter_cmd( 9 downto 8) when X"1", + filter_cmd(11 downto 10) when X"2", + filter_cmd( 1 downto 0) when X"3", + filter_cmd( 3 downto 2) when X"4", + filter_cmd( 5 downto 4) when others; + +-- mux multiplier value +with mult_cmd select +mult_value <= 779 when "10", -- 0.047uF/1KOhm => (1024/fs.R.C = 779, cut fcy 3386Hz) + 166 when "01", -- 0.220uF/1KOhm => (1024/fs.R.C = 166, cut fcy 723Hz) + 137 when "11", -- 0.267uF/1KOhm => (1024/fs.R.C = 137, cut fcy 596Hz) + 779 when others; -- Not use + +-- compute Vcn +Vcn_a <= Vin*1024 when mult_cmd = "00" else Vc + dv*mult_value; -- => Vcn_a : [-1024*1024..1023*1024] + +-- limit to > 0 +Vcn_b <= 0 when Vcn_a < 0 else Vcn_a; + +-- limit to < 255*1024 +Vcn_c <= 255*1024 when Vcn_b > 255*1024 else Vcn_b; + +-- demux/store result and mix channels +process (clock_14) +begin + if rising_edge(clock_14) then -- 14.318MHz/512 => fs = 27.96KHz + + -- demux & down sample + if clock_div1(8 downto 0) = '0'&X"00" then Vc_1a <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"01" then Vc_1b <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"02" then Vc_1c <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"03" then Vc_2a <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"04" then Vc_2b <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"05" then Vc_2c <= Vcn_c; end if; + + -- rescale and mix channels with down sample + if clock_div1(8 downto 0) = '0'&X"06" then + audio_out <= std_logic_vector(to_unsigned(Vc_1a/1024,11)) + + std_logic_vector(to_unsigned(Vc_1b/1024,11)) + + std_logic_vector(to_unsigned(Vc_1c/1024,11)) + + std_logic_vector(to_unsigned(Vc_2a/1024,11)) + + std_logic_vector(to_unsigned(Vc_2b/1024,11)) + + std_logic_vector(to_unsigned(Vc_2c/1024,11)); + end if; + end if; +end process; + + +-- divide clocks +-- random generator ? +process (clock_14) +begin + if reset='1' then + clock_div1 <= (others =>'0'); + biquinary_div <= (others =>'0'); + else + if rising_edge(clock_14) then + clock_div1 <= clock_div1 + '1'; + + if clock_div1 = X"800" then + if biquinary_div(3 downto 1) = "100" then + biquinary_div(3 downto 1) <= "000"; + biquinary_div(0) <= not biquinary_div(0); + else + biquinary_div(3 downto 1) <= biquinary_div(3 downto 1) + '1'; + end if; + end if; + + end if; + end if; +end process; + +-- make clocks for cpu and sound generators +cpu_clock <= clock_div1(2); +ayx_clock <= not clock_div1(2); + +-- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF + wram_do when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF + ay1_do when cpu_addr(15 downto 13) = "010" else -- 4000-5FFF + ay2_do when cpu_addr(15 downto 13) = "011" else -- 6000-7FFF + X"FF"; + +-- write enable to working ram and filter command register +wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = "0011" else '0'; +filter_cmd_we <= '1' when cpu_wr_n = '0' and cpu_addr(15) = '1' else '0'; + +-- chip select with r/w direction to AY chips +sen1_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"4" else '1'; +sen2_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"5" else '1'; +sen3_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"6" else '1'; +sen4_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"7" else '1'; + +-- finalise AY r/w & address controls +ay1_bc1 <= not sen2_n or ( cpu_wr_n and not sen1_n); +ay1_bdir <= not sen2_n or (not cpu_wr_n and not sen1_n); +ay1_cs_n <= sen1_n and sen2_n; + +ay2_bc1 <= not sen4_n or ( cpu_wr_n and not sen3_n); +ay2_bdir <= not sen4_n or (not cpu_wr_n and not sen3_n); +ay2_cs_n <= sen3_n and sen4_n; + +-- input random (?) to AY1 chip +ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(11)&"0000"; + +-- clear irq when reset and irq acknowledge +clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n); + +-- regsiter filters commands (11 bits data are cpu address) +process (cpu_clock) +begin + if rising_edge(cpu_clock) then + if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if; + end if; +end process; + +-- latch sound trigger rising edge to set cpu_irq, and manage clear +process (clock_14) +begin + if rising_edge(clock_14) then + + sound_trig_r <= sound_trig; + + if clr_irq_n = '0' then + cpu_irq_n <= '1'; + else + if sound_trig ='1' and sound_trig_r = '0' then + cpu_irq_n <= '0'; + end if; + end if; + + end if; +end process; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => cpu_clock, + CLKEN => '1', + WAIT_n => '1', + INT_n => cpu_irq_n, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_iorq_n, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.pooyan_sound_prog +port map( + clk => clock_14n, + addr => cpu_addr(12 downto 0), + data => cpu_rom_do +); + +-- working RAM +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_14n, + we => wram_we, + addr => cpu_addr(9 downto 0), + d => cpu_do, + q => wram_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => ay1_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => ay1_cs_n, -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => sound_cmd, -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => ay1_port_b_di, -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => ay2_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => ay2_cs_n, -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end struct; \ No newline at end of file diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_color_lut.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_color_lut.vhd new file mode 100644 index 00000000..d8739c6b --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_color_lut.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_char_color_lut is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_char_color_lut is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"03",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"03",X"01",X"03",X"03",X"04",X"04",X"07",X"08",X"09",X"0F",X"0B",X"0C",X"0D",X"0E",X"0F",X"03", + X"03",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"03",X"04",X"05",X"06",X"0F",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"01",X"02",X"03", + X"03",X"05",X"06",X"07",X"0F",X"09",X"07",X"08",X"06",X"0D",X"0E",X"0F",X"01",X"02",X"03",X"04", + X"03",X"02",X"07",X"08",X"04",X"0A",X"08",X"06",X"07",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05", + X"03",X"07",X"08",X"09",X"0A",X"0B",X"07",X"06",X"08",X"0F",X"01",X"02",X"03",X"04",X"05",X"06", + X"03",X"08",X"09",X"0A",X"05",X"0C",X"06",X"08",X"07",X"01",X"02",X"03",X"04",X"05",X"06",X"07", + X"03",X"09",X"0A",X"0B",X"0C",X"0D",X"08",X"06",X"06",X"02",X"03",X"04",X"05",X"06",X"07",X"08", + X"03",X"03",X"0B",X"0C",X"04",X"0E",X"07",X"07",X"08",X"03",X"04",X"05",X"06",X"07",X"08",X"09", + X"03",X"0B",X"0C",X"0D",X"0E",X"0F",X"07",X"06",X"08",X"04",X"05",X"06",X"07",X"08",X"09",X"0A", + X"03",X"0C",X"0D",X"0E",X"0F",X"01",X"08",X"07",X"06",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B", + X"03",X"0D",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C", + X"03",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D", + X"03",X"0F",X"01",X"02",X"04",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E", + X"03",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_grphx1.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_grphx1.vhd new file mode 100644 index 00000000..9e545ca5 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_grphx1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_char_grphx1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_char_grphx1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"30",X"30",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"F0",X"F0",X"30",X"00", + X"00",X"10",X"30",X"00",X"F0",X"F0",X"F0",X"00",X"C0",X"80",X"00",X"00",X"C0",X"E0",X"C0",X"00", + X"00",X"00",X"00",X"00",X"30",X"30",X"10",X"00",X"00",X"10",X"10",X"70",X"F0",X"E0",X"C0",X"00", + X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"70",X"F0",X"F0",X"F0",X"70",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"E0",X"E2",X"CC",X"00",X"00", + X"F0",X"F0",X"F0",X"F0",X"F0",X"33",X"30",X"E0",X"F0",X"F0",X"F0",X"F0",X"D8",X"D0",X"80",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_grphx2.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_grphx2.vhd new file mode 100644 index 00000000..34c88aeb --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_char_grphx2.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_char_grphx2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_char_grphx2 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"30",X"70",X"C0",X"80",X"80",X"70",X"30",X"00",X"80",X"C0",X"20",X"20",X"60",X"C0",X"80",X"00", + X"00",X"00",X"F0",X"F0",X"40",X"00",X"00",X"00",X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00", + X"60",X"F0",X"B0",X"90",X"90",X"C0",X"40",X"00",X"20",X"20",X"A0",X"A0",X"E0",X"E0",X"60",X"00", + X"80",X"D0",X"F0",X"B0",X"90",X"80",X"00",X"00",X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00", + X"00",X"F0",X"F0",X"C0",X"60",X"30",X"10",X"00",X"80",X"E0",X"E0",X"80",X"80",X"80",X"80",X"00", + X"10",X"B0",X"A0",X"A0",X"A0",X"E0",X"E0",X"00",X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00", + X"00",X"90",X"90",X"90",X"D0",X"70",X"30",X"00",X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00", + X"C0",X"E0",X"B0",X"90",X"80",X"C0",X"C0",X"00",X"00",X"00",X"00",X"E0",X"E0",X"00",X"00",X"00", + X"00",X"60",X"90",X"90",X"B0",X"F0",X"60",X"00",X"C0",X"E0",X"A0",X"20",X"20",X"20",X"C0",X"00", + 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X"00",X"F0",X"20",X"20",X"00",X"00",X"00",X"20",X"00",X"F0",X"33",X"00",X"00",X"00",X"00",X"00", + X"20",X"20",X"00",X"20",X"20",X"20",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"F0",X"00", + X"20",X"00",X"00",X"00",X"20",X"20",X"F1",X"33",X"00",X"00",X"00",X"00",X"00",X"33",X"E0",X"00", + X"44",X"FC",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"CC",X"22",X"00",X"00",X"00",X"00", + X"00",X"F0",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"88",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"20",X"F0",X"00",X"00",X"00",X"00",X"00",X"22",X"EC",X"F0",X"00", + X"00",X"00",X"00",X"00",X"00",X"33",X"C0",X"00",X"00",X"00",X"00",X"00",X"A8",X"20",X"70",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_palette.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_palette.vhd new file mode 100644 index 00000000..522f4290 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_palette.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_palette is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_palette is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"38",X"C0",X"3F",X"C7",X"26",X"03",X"0D",X"2F",X"D1",X"C3",X"F0",X"B8",X"D8",X"FE", + X"00",X"07",X"38",X"80",X"3F",X"C7",X"26",X"03",X"0D",X"2F",X"34",X"20",X"F0",X"B8",X"D8",X"FE"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_prog.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_prog.vhd new file mode 100644 index 00000000..aca0bf96 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_prog.vhd @@ -0,0 +1,2070 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_prog is + type rom is array(0 to 32767) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"80",X"A1",X"C3",X"92",X"00",X"FF",X"77",X"3C",X"23",X"77",X"3C",X"19",X"C9",X"FF", + X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"87",X"E1",X"5F",X"16",X"00",X"19",X"5E",X"23", + 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+use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sound_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sound_prog is + type rom is array(0 to 5615) of std_logic_vector(7 downto 0);--2576 + signal rom_data: rom := ( + X"21",X"00",X"30",X"06",X"00",X"C3",X"AC",X"00",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF", + X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"40",X"57",X"E6",X"7F",X"FE",X"2B",X"D0",X"CB",X"7A",X"28",X"03", + X"C3",X"A3",X"00",X"57",X"CD",X"91",X"00",X"28",X"04",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"91", + 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+library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sprite_color_lut is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sprite_color_lut is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"02",X"02",X"04",X"02",X"06",X"07",X"08",X"09",X"04",X"0B",X"0C",X"06",X"0E",X"0F",X"0F", + X"00",X"03",X"02",X"05",X"03",X"07",X"08",X"09",X"0A",X"0B",X"0F",X"0F",X"0F",X"0F",X"0F",X"00", + X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F", + X"00",X"05",X"02",X"0B",X"05",X"09",X"0A",X"0B",X"0C",X"04",X"0E",X"0F",X"01",X"02",X"03",X"04", + X"00",X"04",X"07",X"0D",X"04",X"05",X"0B",X"0C",X"0D",X"0E",X"0A",X"01",X"02",X"03",X"04",X"0F", + X"00",X"01",X"01",X"02",X"01",X"0F",X"02",X"02",X"0F",X"0F",X"01",X"0F",X"00",X"01",X"00",X"00", + X"00",X"01",X"01",X"02",X"01",X"0F",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"0F",X"00",X"00", + X"00",X"01",X"01",X"04",X"01",X"0F",X"01",X"00",X"01",X"0F",X"0F",X"0F",X"00",X"0F",X"0F",X"00", + X"00",X"0A",X"02",X"01",X"03",X"0E",X"0F",X"01",X"02",X"04",X"04",X"05",X"06",X"07",X"08",X"0F", + X"00",X"04",X"02",X"0D",X"01",X"0F",X"01",X"01",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0F", + X"00",X"04",X"04",X"0F",X"0F",X"04",X"04",X"04",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"0D",X"0E",X"0F",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0F", + X"00",X"04",X"04",X"04",X"0F",X"0F",X"0F",X"00",X"04",X"0F",X"0F",X"0F",X"04",X"00",X"00",X"00", + X"00",X"0F",X"02",X"02",X"0F",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"04", + X"00",X"01",X"02",X"03",X"0C",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_sprite_grphx1.vhd b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_sprite_grphx1.vhd new file mode 100644 index 00000000..f45fdfb4 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/proms/pooyan_sprite_grphx1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sprite_grphx1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sprite_grphx1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity pooyan_sprite_grphx2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of pooyan_sprite_grphx2 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"12",X"34",X"69", + X"00",X"00",X"00",X"00",X"0C",X"C2",X"C2",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"4B",X"4B",X"0F",X"07",X"03",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0E",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"88",X"88",X"00",X"80",X"91",X"00",X"00",X"00",X"11",X"11",X"22",X"20",X"F0", + X"88",X"00",X"88",X"CC",X"88",X"77",X"74",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/scandoubler.v b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/video_mixer.sv b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/video_mixer.sv new file mode 100644 index 00000000..ee42674d --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/video_mixer.sv @@ -0,0 +1,228 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + + + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({r_out, 8'd0} + {r_out, 3'd0}) + ({g_out, 9'd0} + {g_out, 2'd0}) + ({b_out, 6'd0} + {b_out, 5'd0} + {b_out, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({r_out, 7'd0} + {r_out, 4'd0} + {r_out, 3'd0}) - ({g_out, 8'd0} + {g_out, 5'd0} + {g_out, 3'd0}) + ({b_out, 8'd0} + {b_out, 7'd0} + {b_out, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({r_out, 8'd0} + {r_out, 7'd0} + {r_out, 6'd0}) - ({g_out, 8'd0} + {g_out, 6'd0} + {g_out, 5'd0} + {g_out, 4'd0} + {g_out, 3'd0}) - ({b_out, 6'd0} + {b_out , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : r_out; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : g_out; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : b_out; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/video_mixer2.sv b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/video_mixer2.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/Pooyan_mistVGA/rtl/video_mixer2.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Konami Classic/Pooyan_MiST/README.txt b/Arcade/Konami Classic/Pooyan_MiST/README.txt new file mode 100644 index 00000000..2bc84c26 --- /dev/null +++ b/Arcade/Konami Classic/Pooyan_MiST/README.txt @@ -0,0 +1,208 @@ +--------------------------------------------------------------------------------- +-- POOYAN by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok +-- No external RAM/SDRAM required + +-- Use with MAME roms from timeplt.zip +-- +-- Use make_pooyan_proms.bat to build vhd file from binaries + +-- Time Pilot Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 24Kx8bits program rom +-- +-- One char tile map 32x28 +-- 8Kx8bits graphics rom 2bits/pixel +-- 4 colors/32sets among 16 colors +-- +-- 24 sprites with priorities and flip H/V +-- 16Kx8bits graphics rom 2bits/pixel +-- 3 colors/64sets among 16 colors (different of char colors). +-- +-- Char/sprites color palette 2x16 colors among 32768 colors +-- 15bits 5red/5green/5blue +-- +-- Working ram : 4Kx8bits +-- Sprites data ram : 256x16bits +-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits + +-- SOUND : 1xZ80@1.79MHz CPU accessing its program rom, working ram, 2x-AY3-8910 +-- 8Kx8bits program rom +-- +-- 1xAY-3-8910 +-- I/O noise input and command/trigger from video board. +-- 3 sound channels +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- 6 RC filters with 4 states : transparent or cut 600Hz, 700Hz, 3.4KHz +-- +--------------------------------------------------------------------------------- +-- +-- Uses 1 pll for 12MHz and 14MHz generation from 50MHz +-- +-- Board key : +-- 0 : reset game +-- +-- Keyboard players inputs : +-- +-- F3 : Add coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire +-- RIGHT arrow : rotate right +-- LEFT arrow : rotate left +-- UP arrow : rotate up +-- DOWN arrow : rotate down +-- +-- Other details : see pooyan.vhd + +--------------------------------------------------------------------------------- +-- Use pooyan_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sun Nov 05 10:17:02 2017 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; pooyan_de10_lite ; +; Top-level Entity Name ; pooyan_de10_lite ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 6,231 / 49,760 ( 13 % ) ; +; Total combinational functions ; 6,005 / 49,760 ( 12 % ) ; +; Dedicated logic registers ; 1,579 / 49,760 ( 3 % ) ; +; Total registers ; 1579 ; +; Total pins ; 105 / 360 ( 29 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 475,648 / 1,677,312 ( 28 % ) ; +; Embedded Multiplier 9-bit elements ; 2 / 288 ( < 1 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + +--------------- +VHDL File list +--------------- + +de_10/max10_pll_12M_14M.vhd Pll 12MHz and 14 MHz from 50MHz altera mf + +rtl_dar/pooyan_de10_lite.vhd Top level for de10_lite board +rtl_dar/pooyan.vhd Main video board logic +rtl_dar/pooyan_sound_board.vhd Main sound board logic + +rtl_mikej/YM2149_linmix_sep.vhd Copyright (c) MikeJ - Jan 2005 + +rtl_T80/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +rtl_T80/T80_Reg.vhd +rtl_T80/T80_Pack.vhd +rtl_T80/T80_MCode.vhd +rtl_T80/T80_ALU.vhd +rtl_T80/T80.vhd + +rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input +rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) +rtl_dar/decodeur_7_seg.vhd 7 segments display decoder + +rtl_dar/pooyan_prog.vhd Time pilot video board PROMs +rtl_dar/pooyan_char_grphx.vhd +rtl_dar/pooyan_char_color_lut.vhd +rtl_dar/pooyan_sprite_grphx.vhd +rtl_dar/pooyan_sprite_color_lut.vhd +rtl_dar/pooyan_palette_green_red.vhd +rtl_dar/pooyan_palette_blue_green.vhd + +rtl_dar/pooyan_sound_prog.vhd Time pilot sound board PROM + +---------------------- +Quartus project files +---------------------- +de10_lite/pooyan_de10_lite.sdc Timequest constraints file +de10_lite/pooyan_de10_lite.qsf de10_lite settings (files,pins...) +de10_lite/pooyan_de10_lite.qpf de10_lite project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 11 ROMs binary files from timeplt.zip (MAME) + +tm1, tm2,tm3, tm4, tm5, tm6, tm7 +timeplt.b4 +timeplt.b5 +timeplt.e9 +timeplt.e12 + +------ +Tools +------ +You need to build vhdl files from the binary file : + - Unzip the roms file in the tools/pooyan_unzip directory + - Double click (execute) the script tools/make_pooyan_proms.bat to get the following files + +pooyan_prog.vhd : tm1, tm2,tm3 +pooyan_sprite_grphx.vhd : tm4, tm5 +pooyan_char_grphx.vhd : tm6 +pooyan_sound_prog.vhd : tm7 +pooyan_palette_blue_green.vhd : timeplt.b4 +pooyan_palette_green_red.vhd : timeplt.b5 +pooyan_sprite_color_lut.vhd : timeplt.e9 +pooyan_char_color_lut.vhd : timeplt.e12 + + +*DO NOT REDISTRIBUTE THESE FILES* + +VHDL files are needed to compile and include roms into the project + +The script make_pooyan_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c is also delivered. + +--------------------------------- +Compiling for de10_lite +--------------------------------- +You can build the project with ROM image embeded in the sof file. +*DO NOT REDISTRIBUTE THESE FILES* + +3 steps + + - put the VHDL ROM files (.vhd) into the rtl_dar directory + - build pooyan_de10_lite + - program pooyan_de10_lite.sof + +------------------------ +------------------------ +End of file +------------------------ diff --git a/Arcade/Konami Classic/Pooyan_MiST/pooyan_mist(RGB).rbf b/Arcade/Konami Classic/Pooyan_MiST/pooyan_mist(RGB).rbf new file mode 100644 index 00000000..3019a6a0 Binary files /dev/null and b/Arcade/Konami Classic/Pooyan_MiST/pooyan_mist(RGB).rbf differ diff --git a/Arcade/Konami Classic/Pooyan_MiST/pooyan_mist(wo OSD).rbf b/Arcade/Konami Classic/Pooyan_MiST/pooyan_mist(wo OSD).rbf new file mode 100644 index 00000000..ef990afc Binary files /dev/null and b/Arcade/Konami Classic/Pooyan_MiST/pooyan_mist(wo OSD).rbf differ diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/README.txt b/Arcade/Konami Classic/Time_Pilot_MiST/README.txt new file mode 100644 index 00000000..0340f2d6 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/README.txt @@ -0,0 +1,208 @@ +--------------------------------------------------------------------------------- +-- Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok +-- No external RAM/SDRAM required + +-- Use with MAME roms from timeplt.zip +-- +-- Use make_time_pilot_proms.bat to build vhd file from binaries + +-- Time Pilot Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 24Kx8bits program rom +-- +-- One char tile map 32x28 +-- 8Kx8bits graphics rom 2bits/pixel +-- 4 colors/32sets among 16 colors +-- +-- 24 sprites with priorities and flip H/V +-- 16Kx8bits graphics rom 2bits/pixel +-- 3 colors/64sets among 16 colors (different of char colors). +-- +-- Char/sprites color palette 2x16 colors among 32768 colors +-- 15bits 5red/5green/5blue +-- +-- Working ram : 4Kx8bits +-- Sprites data ram : 256x16bits +-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits + +-- SOUND : 1xZ80@1.79MHz CPU accessing its program rom, working ram, 2x-AY3-8910 +-- 8Kx8bits program rom +-- +-- 1xAY-3-8910 +-- I/O noise input and command/trigger from video board. +-- 3 sound channels +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- 6 RC filters with 4 states : transparent or cut 600Hz, 700Hz, 3.4KHz +-- +--------------------------------------------------------------------------------- +-- +-- Uses 1 pll for 12MHz and 14MHz generation from 50MHz +-- +-- Board key : +-- 0 : reset game +-- +-- Keyboard players inputs : +-- +-- F3 : Add coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire +-- RIGHT arrow : rotate right +-- LEFT arrow : rotate left +-- UP arrow : rotate up +-- DOWN arrow : rotate down +-- +-- Other details : see time_pilot.vhd + +--------------------------------------------------------------------------------- +-- Use time_pilot_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Sun Nov 05 10:17:02 2017 ; +; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; +; Revision Name ; time_pilot_de10_lite ; +; Top-level Entity Name ; time_pilot_de10_lite ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 6,231 / 49,760 ( 13 % ) ; +; Total combinational functions ; 6,005 / 49,760 ( 12 % ) ; +; Dedicated logic registers ; 1,579 / 49,760 ( 3 % ) ; +; Total registers ; 1579 ; +; Total pins ; 105 / 360 ( 29 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 475,648 / 1,677,312 ( 28 % ) ; +; Embedded Multiplier 9-bit elements ; 2 / 288 ( < 1 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + +--------------- +VHDL File list +--------------- + +de_10/max10_pll_12M_14M.vhd Pll 12MHz and 14 MHz from 50MHz altera mf + +rtl_dar/time_pilot_de10_lite.vhd Top level for de10_lite board +rtl_dar/time_pilot.vhd Main video board logic +rtl_dar/time_pilot_sound_board.vhd Main sound board logic + +rtl_mikej/YM2149_linmix_sep.vhd Copyright (c) MikeJ - Jan 2005 + +rtl_T80/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +rtl_T80/T80_Reg.vhd +rtl_T80/T80_Pack.vhd +rtl_T80/T80_MCode.vhd +rtl_T80/T80_ALU.vhd +rtl_T80/T80.vhd + +rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input +rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) +rtl_dar/decodeur_7_seg.vhd 7 segments display decoder + +rtl_dar/time_pilot_prog.vhd Time pilot video board PROMs +rtl_dar/time_pilot_char_grphx.vhd +rtl_dar/time_pilot_char_color_lut.vhd +rtl_dar/time_pilot_sprite_grphx.vhd +rtl_dar/time_pilot_sprite_color_lut.vhd +rtl_dar/time_pilot_palette_green_red.vhd +rtl_dar/time_pilot_palette_blue_green.vhd + +rtl_dar/time_pilot_sound_prog.vhd Time pilot sound board PROM + +---------------------- +Quartus project files +---------------------- +de10_lite/time_pilot_de10_lite.sdc Timequest constraints file +de10_lite/time_pilot_de10_lite.qsf de10_lite settings (files,pins...) +de10_lite/time_pilot_de10_lite.qpf de10_lite project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 11 ROMs binary files from timeplt.zip (MAME) + +tm1, tm2,tm3, tm4, tm5, tm6, tm7 +timeplt.b4 +timeplt.b5 +timeplt.e9 +timeplt.e12 + +------ +Tools +------ +You need to build vhdl files from the binary file : + - Unzip the roms file in the tools/time_pilot_unzip directory + - Double click (execute) the script tools/make_time_pilot_proms.bat to get the following files + +time_pilot_prog.vhd : tm1, tm2,tm3 +time_pilot_sprite_grphx.vhd : tm4, tm5 +time_pilot_char_grphx.vhd : tm6 +time_pilot_sound_prog.vhd : tm7 +time_pilot_palette_blue_green.vhd : timeplt.b4 +time_pilot_palette_green_red.vhd : timeplt.b5 +time_pilot_sprite_color_lut.vhd : timeplt.e9 +time_pilot_char_color_lut.vhd : timeplt.e12 + + +*DO NOT REDISTRIBUTE THESE FILES* + +VHDL files are needed to compile and include roms into the project + +The script make_time_pilot_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c is also delivered. + +--------------------------------- +Compiling for de10_lite +--------------------------------- +You can build the project with ROM image embeded in the sof file. +*DO NOT REDISTRIBUTE THESE FILES* + +3 steps + + - put the VHDL ROM files (.vhd) into the rtl_dar directory + - build time_pilot_de10_lite + - program time_pilot_de10_lite.sof + +------------------------ +------------------------ +End of file +------------------------ diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf b/Arcade/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf new file mode 100644 index 00000000..e61d146f Binary files /dev/null and b/Arcade/Konami Classic/Time_Pilot_MiST/Release/time_pilot_mist.rbf differ diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/clean.bat b/Arcade/Konami Classic/Time_Pilot_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/DebugSystem.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/DebugSystem.vhd new file mode 100644 index 00000000..27f115c9 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/DebugSystem.vhd @@ -0,0 +1,197 @@ +-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs +-- that can be synthesized and used with +-- the NoICE debugger that can be found at +-- http://www.noicedebugger.com/ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity DebugSystem is + port( + Reset_n : in std_logic; + Clk : in std_logic; + NMI_n : in std_logic; + RXD0 : in std_logic; + CTS0 : in std_logic; + DSR0 : in std_logic; + RI0 : in std_logic; + DCD0 : in std_logic; + RXD1 : in std_logic; + CTS1 : in std_logic; + DSR1 : in std_logic; + RI1 : in std_logic; + DCD1 : in std_logic; + TXD0 : out std_logic; + RTS0 : out std_logic; + DTR0 : out std_logic; + TXD1 : out std_logic; + RTS1 : out std_logic; + DTR1 : out std_logic; +As : out std_logic_vector(15 downto 0); +Ds : out std_logic_vector(7 downto 0); +ROM_Ds : out std_logic_vector(7 downto 0) + ); +end DebugSystem; + +architecture struct of DebugSystem is + + signal M1_n : std_logic; + signal MREQ_n : std_logic; + signal IORQ_n : std_logic; + signal RD_n : std_logic; + signal WR_n : std_logic; + signal RFSH_n : std_logic; + signal HALT_n : std_logic; + signal WAIT_n : std_logic; + signal INT_n : std_logic; + signal RESET_s : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal A : std_logic_vector(15 downto 0); + signal D : std_logic_vector(7 downto 0); + signal ROM_D : std_logic_vector(7 downto 0); + signal SRAM_D : std_logic_vector(7 downto 0); + signal UART0_D : std_logic_vector(7 downto 0); + signal UART1_D : std_logic_vector(7 downto 0); + signal CPU_D : std_logic_vector(7 downto 0); + + signal Mirror : std_logic; + + signal IOWR_n : std_logic; + signal RAMCS_n : std_logic; + signal UART0CS_n : std_logic; + signal UART1CS_n : std_logic; + + signal BaudOut0 : std_logic; + signal BaudOut1 : std_logic; + +begin + As <= A; + Ds <= D; + ROM_Ds <= ROM_D; + + Wait_n <= '1'; + BusRq_n <= '1'; + INT_n <= '1'; + + process (Reset_n, Clk) + begin + if Reset_n = '0' then + Reset_s <= '0'; + Mirror <= '0'; + elsif Clk'event and Clk = '1' then + Reset_s <= '1'; + if IORQ_n = '0' and A(7 downto 4) = "1111" then + Mirror <= D(0); + end if; + end if; + end process; + + IOWR_n <= WR_n or IORQ_n; + RAMCS_n <= (not Mirror and not A(15)) or MREQ_n; + UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1'; + UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1'; + +-- CPU_D <= +-- SRAM_D when RAMCS_n = '0' else +-- UART0_D when UART0CS_n = '0' else +-- UART1_D when UART1CS_n = '0' else +-- ROM_D; + + CPU_D <= + ROM_D; + + u0 : entity work.T80s + generic map(Mode => 0, T2Write => 1, IOWait => 0) +-- generic map(Mode => 1, T2Write => 1, IOWait => 0) + port map( + RESET_n => RESET_s, + CLK_n => Clk, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + RD_n => RD_n, + WR_n => WR_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + A => A, + DI => CPU_D, + DO => D); + + -- u1 : entity work.MonZ80 + -- port map( + -- Clk => Clk, + -- A => A(10 downto 0), + -- D => ROM_D); + + u1 : entity work.bagmanrom + port map( + clock => not Clk, + address => A(14 downto 0), + q => ROM_D); + + u2 : entity work.SSRAM + generic map( + AddrWidth => 12) + port map( + Clk => Clk, + CE_n => RAMCS_n, + WE_n => WR_n, + A => A(11 downto 0), + DIn => D, + DOut => SRAM_D); + + u3 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut0, + CS_n => UART0CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A(2 downto 0), + D_In => D, + D_Out => UART0_D, + SIn => RXD0, + CTS_n => CTS0, + DSR_n => DSR0, + RI_n => RI0, + DCD_n => DCD0, + SOut => TXD0, + RTS_n => RTS0, + DTR_n => DTR0, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut0, + Intr => open); + + u4 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut1, + CS_n => UART1CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A(2 downto 0), + D_In => D, + D_Out => UART1_D, + SIn => RXD1, + CTS_n => CTS1, + DSR_n => DSR1, + RI_n => RI1, + DCD_n => DCD1, + SOut => TXD1, + RTS_n => RTS1, + DTR_n => DTR1, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut1, + Intr => open); + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/DebugSystemXR.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/DebugSystemXR.vhd new file mode 100644 index 00000000..ca8fa877 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/DebugSystemXR.vhd @@ -0,0 +1,185 @@ +-- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs +-- that can be synthesized and used with +-- the NoICE debugger that can be found at +-- http://www.noicedebugger.com/ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity DebugSystemXR is + port( + Reset_n : in std_logic; + Clk : in std_logic; + NMI_n : in std_logic; + OE_n : out std_logic; + WE_n : out std_logic; + RAMCS_n : out std_logic; + ROMCS_n : out std_logic; + PGM_n : out std_logic; + A : out std_logic_vector(16 downto 0); + D : inout std_logic_vector(7 downto 0); + RXD0 : in std_logic; + CTS0 : in std_logic; + DSR0 : in std_logic; + RI0 : in std_logic; + DCD0 : in std_logic; + RXD1 : in std_logic; + CTS1 : in std_logic; + DSR1 : in std_logic; + RI1 : in std_logic; + DCD1 : in std_logic; + TXD0 : out std_logic; + RTS0 : out std_logic; + DTR0 : out std_logic; + TXD1 : out std_logic; + RTS1 : out std_logic; + DTR1 : out std_logic + ); +end entity DebugSystemXR; + +architecture struct of DebugSystemXR is + + signal M1_n : std_logic; + signal MREQ_n : std_logic; + signal IORQ_n : std_logic; + signal RD_n : std_logic; + signal WR_n : std_logic; + signal RFSH_n : std_logic; + signal HALT_n : std_logic; + signal WAIT_n : std_logic; + signal INT_n : std_logic; + signal RESET_s : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal D_i : std_logic_vector(7 downto 0); + signal ROM_D : std_logic_vector(7 downto 0); + signal UART0_D : std_logic_vector(7 downto 0); + signal UART1_D : std_logic_vector(7 downto 0); + signal CPU_D : std_logic_vector(7 downto 0); + + signal Mirror : std_logic; + + signal IOWR_n : std_logic; + signal RAMCS_n_i : std_logic; + signal UART0CS_n : std_logic; + signal UART1CS_n : std_logic; + + signal BaudOut0 : std_logic; + signal BaudOut1 : std_logic; + +begin + + Wait_n <= '1'; + BusRq_n <= '1'; + INT_n <= '1'; + + OE_n <= RD_n; + WE_n <= WR_n; + RAMCS_n <= RAMCS_n_i; + ROMCS_n <= '1'; + PGM_n <= '1'; + A(14 downto 0) <= A_i(14 downto 0); + A(16 downto 15) <= "00"; + D <= D_i when WR_n = '0' else "ZZZZZZZZ"; + + process (Reset_n, Clk) + begin + if Reset_n = '0' then + Reset_s <= '0'; + Mirror <= '0'; + elsif Clk'event and Clk = '1' then + Reset_s <= '1'; + if IORQ_n = '0' and A_i(7 downto 4) = "1111" then + Mirror <= D_i(0); + end if; + end if; + end process; + + IOWR_n <= WR_n or IORQ_n; + RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n; + UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1'; + UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1'; + + CPU_D <= + D when RAMCS_n_i = '0' else + UART0_D when UART0CS_n = '0' else + UART1_D when UART1CS_n = '0' else + ROM_D; + + u0 : entity work.T80s + generic map(Mode => 1, T2Write => 1, IOWait => 0) + port map( + RESET_n => RESET_s, + CLK_n => Clk, + WAIT_n => WAIT_n, + INT_n => INT_n, + NMI_n => NMI_n, + BUSRQ_n => BUSRQ_n, + M1_n => M1_n, + MREQ_n => MREQ_n, + IORQ_n => IORQ_n, + RD_n => RD_n, + WR_n => WR_n, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + BUSAK_n => BUSAK_n, + A => A_i, + DI => CPU_D, + DO => D_i); + + u1 : entity work.MonZ80 + port map( + Clk => Clk, + A => A_i(10 downto 0), + D => ROM_D); + + u3 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut0, + CS_n => UART0CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A_i(2 downto 0), + D_In => D_i, + D_Out => UART0_D, + SIn => RXD0, + CTS_n => CTS0, + DSR_n => DSR0, + RI_n => RI0, + DCD_n => DCD0, + SOut => TXD0, + RTS_n => RTS0, + DTR_n => DTR0, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut0, + Intr => open); + + u4 : entity work.T16450 + port map( + MR_n => Reset_s, + XIn => Clk, + RClk => BaudOut1, + CS_n => UART1CS_n, + Rd_n => RD_n, + Wr_n => IOWR_n, + A => A_i(2 downto 0), + D_In => D_i, + D_Out => UART1_D, + SIn => RXD1, + CTS_n => CTS1, + DSR_n => DSR1, + RI_n => RI1, + DCD_n => DCD1, + SOut => TXD1, + RTS_n => RTS1, + DTR_n => DTR1, + OUT1_n => open, + OUT2_n => open, + BaudOut => BaudOut1, + Intr => open); + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T8080se.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T8080se.vhd new file mode 100644 index 00000000..2b6d28f8 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T8080se.vhd @@ -0,0 +1,185 @@ +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_ALU.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_MCode.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_Pack.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_Reg.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80se.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80se.vhd new file mode 100644 index 00000000..ac8886a8 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/T80se.vhd @@ -0,0 +1,184 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..27f26749 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,553 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..5c0eba0c --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "build_id.vhd" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "constant BUILD_DATE : String(1 to 6) := \"$buildDate\"" + puts $outputFile "constant BUILD_TIME : String(1 to 6) := \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd new file mode 100644 index 00000000..9f696b0b --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 11 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/gen_ram.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/gen_video.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/gen_video.vhd new file mode 100644 index 00000000..da8d77d4 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/gen_video.vhd @@ -0,0 +1,70 @@ +--------------------------------------------------------------------------------- +-- Galaga video horizontal/vertical and sync generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.ALL; + +entity gen_video is +port( + clk : in std_logic; + enable : in std_logic; + hcnt : out std_logic_vector(5 downto 0); + vcnt : out std_logic_vector(5 downto 0); + hsync : out std_logic; + vsync : out std_logic; + blankn : out std_logic +); +end gen_video; + +architecture struct of gen_video is + signal hblank : std_logic; + signal vblank : std_logic; + signal hcntReg : unsigned (5 DOWNTO 0) := to_unsigned(000,9); + signal vcntReg : unsigned (5 DOWNTO 0) := to_unsigned(015,9); +begin + +hcnt <= std_logic_vector(hcntReg); +vcnt <= std_logic_vector(vcntReg); + + +process(clk) begin + + if enable = '1' then + + if hcntReg = 511 then + hcntReg <= to_unsigned (128,9); + else + hcntReg <= hcntReg + 1; + end if; + + if hcntReg = 191 then + if vcntReg = 261 then + vcntReg <= to_unsigned(0,9); + else + vcntReg <= vcntReg + 1; + end if; + end if; + + if hcntReg = (175+ 0-8+8) then hsync <= '1'; -- 1 + elsif hcntReg = (175+29-8+8) then hsync <= '0'; + end if; + + if vcntReg = 252 then vsync <= '1'; + elsif vcntReg = 260 then vsync <= '0'; + end if; + + if hcntReg = (127+16+8) then hblank <= '1'; + elsif hcntReg = (255-17+8+1) then hblank <= '0'; + end if; + + if vcntReg = (240+1-1) then vblank <= '1'; + elsif vcntReg = (015+1) then vblank <= '0'; + end if; + + blankn <= not (hblank or vblank); + end if; + +end process; + +end architecture; \ No newline at end of file diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/hq2x.sv b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..3e406318 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bxx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/keyboard.v b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.qip b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.qip new file mode 100644 index 00000000..02816126 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_pll_12M_14M.ppf"] diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.vhd new file mode 100644 index 00000000..4865e696 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/mist_pll_12M_14M.vhd @@ -0,0 +1,424 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: mist_pll_12M_14M.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY mist_pll_12M_14M IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END mist_pll_12M_14M; + + +ARCHITECTURE SYN OF mist_pll_12m_14m IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 420, + clk0_duty_cycle => 50, + clk0_multiply_by => 191, + clk0_phase_shift => "0", + clk1_divide_by => 360, + clk1_duty_cycle => 50, + clk1_multiply_by => 191, + clk1_phase_shift => "0", + clk2_divide_by => 105, + clk2_duty_cycle => 50, + clk2_multiply_by => 191, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=mist_pll_12M_14M", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "420" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "360" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "105" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.278571" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.325000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "49.114285" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "191" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.28800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31800000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "49.15200000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "mist_pll_12M_14M.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "420" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "360" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "105" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "191" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_pll_12M_14M_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/osd.v b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/scandoubler.v b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd new file mode 100644 index 00000000..7ec1d6d4 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot.vhd @@ -0,0 +1,792 @@ +--------------------------------------------------------------------------------- +-- Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- TV 15KHz mode only (atm) +-- Coctail mode ok +-- Sound ok + +-- Use with MAME roms from timeplt.zip +-- +-- Use make_time_pilot_proms.bat to build vhd file from binaries + +-- time_pilot_prog.vhd : tm1, tm2,tm3 +-- time_pilot_sprite_grphx.vhd : tm4, tm5 +-- time_pilot_char_grphx.vhd : tm6 +-- time_pilot_sound_prog.vhd : tm7 +-- time_pilot_palette_blue_green.vhd : timeplt.b4 +-- time_pilot_palette_green_red.vhd : timeplt.b5 +-- time_pilot_sprite_color_lut.vhd : timeplt.e9 +-- time_pilot_char_color_lut.vhd : timeplt.e12 + +-- Time Pilot Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 24Kx8bits program rom +-- +-- One char tile map 32x28 +-- 8Kx8bits graphics rom 2bits/pixel +-- 4 colors/32sets among 16 colors +-- +-- 24 sprites with priorities and flip H/V +-- 16Kx8bits graphics rom 2bits/pixel +-- 3 colors/64sets among 16 colors (different of char colors). +-- +-- Char/sprites color palette 2x16 colors among 32768 colors +-- 15bits 5red/5green/5blue +-- +-- Working ram : 4Kx8bits +-- Sprites data ram : 256x16bits +-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits + +-- SOUND : 1xZ80@1.79MHz CPU accessing its program rom, working ram, 2x-AY3-8910 +-- 8Kx8bits program rom +-- +-- 1xAY-3-8910 +-- I/O noise input and command/trigger from video board. +-- 3 sound channels +-- +-- 1xAY-3-8910 +-- 3 sound channels +-- +-- 6 RC filters with 4 states : transparent or cut 600Hz, 700Hz, 3.4KHz +-- +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity time_pilot is +port( + clock_12 : in std_logic; + clock_14 : in std_logic; + reset : in std_logic; + + -- tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(4 downto 0); + video_g : out std_logic_vector(4 downto 0); + video_b : out std_logic_vector(4 downto 0); + video_clk : out std_logic; + video_hblank : out std_logic; + video_vblank : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(10 downto 0); + + dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B / Coinage_A + dip_switch_2 : in std_logic_vector(7 downto 0); -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + + fire1 : in std_logic; + right1 : in std_logic; + left1 : in std_logic; + down1 : in std_logic; + up1 : in std_logic; + + fire2 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + down2 : in std_logic; + up2 : in std_logic; + + dbg_cpu_addr : out std_logic_vector(15 downto 0) +); +end time_pilot; + +architecture struct of time_pilot is + + signal reset_n: std_logic; + signal clock_12n : std_logic; + signal clock_6 : std_logic := '0'; + signal clock_6n : std_logic; + signal clock_div : std_logic_vector(1 downto 0) := "00"; + + signal hcnt : std_logic_vector(5 downto 0); -- horizontal counter + signal vcnt : std_logic_vector(8 downto 0); -- vertical counter + signal pxcnt : std_logic_vector(2 downto 0); -- pixel counter + signal spcnt : std_logic_vector(4 downto 0); -- sprite counter + + signal hsync0 : std_logic; + + signal hblank : std_logic; + signal vblank : std_logic; + + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_nmi_n : std_logic; + + signal cpu_rom_do : std_logic_vector( 7 downto 0); + + signal wram_addr : std_logic_vector(11 downto 0); + signal wram_we : std_logic; + signal wram_do : std_logic_vector( 7 downto 0); + + signal ch_graphx_addr_f: std_logic_vector(12 downto 0); + signal ch_graphx_addr : std_logic_vector(12 downto 0); + signal ch_graphx_do : std_logic_vector( 7 downto 0); + signal ch_pixels : std_logic_vector( 7 downto 0); + signal ch_data1 : std_logic_vector( 7 downto 0); + signal ch_pixel_bit1 : std_logic; + signal ch_pixel_bit2 : std_logic; + signal ch_color_set : std_logic_vector(4 downto 0); + signal ch_palette_addr : std_logic_vector(7 downto 0); + signal ch_palette_do : std_logic_vector(7 downto 0); + + signal spram_addr : std_logic_vector(7 downto 0); + signal spram1_we : std_logic; + signal spram1_do : std_logic_vector(7 downto 0); + signal spram2_we : std_logic; + signal spram2_do : std_logic_vector(7 downto 0); + + signal sp_graphx_addr : std_logic_vector(13 downto 0); + signal sp_graphx_do : std_logic_vector(7 downto 0); + signal vcnt_r : std_logic_vector(8 downto 0); + signal sp_line : std_logic_vector(7 downto 0); + signal sp_on_line : std_logic; + signal sp_attr : std_logic_vector(7 downto 0); + signal sp_posh : std_logic_vector(7 downto 0); + signal sp_pixels : std_logic_vector(7 downto 0); + signal sp_color_set : std_logic_vector(5 downto 0); + signal sp_palette_addr : std_logic_vector(7 downto 0); + signal sp_palette_do : std_logic_vector(7 downto 0); + signal sp_read_out : std_logic_vector(3 downto 0); + signal sp_blank : std_logic; + + signal rgb_palette_addr : std_logic_vector(4 downto 0); + signal rgb_palette_bg_do : std_logic_vector(7 downto 0); + signal rgb_palette_gr_do : std_logic_vector(7 downto 0); + + signal sp_buffer_write_addr : std_logic_vector(7 downto 0); + signal sp_buffer_write_we : std_logic; + signal sp_buffer_read_addr : std_logic_vector(7 downto 0); + + signal sp_buffer_ram1_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram1_we : std_logic; + signal sp_buffer_ram1_di : std_logic_vector(3 downto 0); + signal sp_buffer_ram1_do : std_logic_vector(3 downto 0); + + signal sp_buffer_ram2_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram2_we : std_logic; + signal sp_buffer_ram2_di : std_logic_vector(3 downto 0); + signal sp_buffer_ram2_do : std_logic_vector(3 downto 0); + + signal sp_buffer_sel : std_logic; + + signal itt_n : std_logic; + signal flip : std_logic; + signal C0xx_we : std_logic; + signal C3xx_we : std_logic; + signal sound_cmd : std_logic_vector(7 downto 0); + signal sound_trig : std_logic; + + signal input_0 : std_logic_vector(7 downto 0); + signal input_1 : std_logic_vector(7 downto 0); + signal input_2 : std_logic_vector(7 downto 0); + +begin + +video_clk <= clock_6n; +clock_12n <= not clock_12; +clock_6n <= not clock_6; +reset_n <= not reset; + +-- debug +process (reset, clock_12) +begin + if rising_edge(clock_12) and cpu_ena ='1' and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-- make 6MHz clock from 12MHz +process (clock_12) +begin + if reset='1' then + clock_6 <= '0'; + else + if rising_edge(clock_12) then + clock_6 <= not clock_6; + end if; + end if; +end process; + + +-------------------------- +-- Video/sprite scanner -- +-------------------------- + +-- make hcnt and vcnt video scanner from pixel clocks and counts +-- +-- pxcnt |0|1|2|3|4|5|6|7|0|1|2|3|4|5|6|7| +-- hcnt | N | N+1 | +-- cpu_adr/do | | + +-- +-- hcnt [0..47] => 48 x 8 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz) +-- vcnt [252..255,256..511] => 260 lines, 1 frame is 260 x 62.5us = 16.250ms (61.54Hz) + +process (reset, clock_6) +begin + if reset='1' then + pxcnt <= "000"; + hcnt <= "000000"; + vcnt <= '0'&X"FC"; + spcnt <= "00000"; + else + if rising_edge(clock_6) then + pxcnt <= pxcnt + '1'; + if pxcnt = "111" then + hcnt <= hcnt + '1'; + + if hcnt = "101111" then -- char from #0 to #47 (one line) + hcnt <= "000000"; + if vcnt = '1'&X"FF" then + vcnt <= '0'&X"FC"; + else + vcnt <= vcnt + '1'; + end if; + end if; + + -- sprite down counter + if hcnt(0) = '1' then -- every is 16 bits (2 char) + if hcnt = "101111" then + spcnt <= "11111"; -- start with sprite #31 + else + spcnt <= spcnt - '1'; -- downto sprite #8 + end if; + end if; + + end if; + end if; + end if; +end process; + +cpu_ena <= not pxcnt(0); + +-- inputs +input_0 <= "111" & not start2 & not start1 & '1' & '1' & not coin1; -- ?/ ?/ ?/ 2S/ 1S/SVC/ C2/ C1 +input_1 <= "111" & not fire1 & not down1 & not up1 & not right1 & not left1; -- ?/1FL/1SR/1SL/1DW/1UP/1RI/1LE +input_2 <= "111" & not fire2 & not down2 & not up2 & not right2 & not left2; -- ?/2FL/2SR/2SL/2DW/2UP/2RI/2LE + +-- cpu input address decoding (mirror mostly from Mame) +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"6" else -- 0000-5FFF + X"FF" when cpu_addr(15 downto 12) < X"A" else -- 6000-9FFF + wram_do when cpu_addr(15 downto 12) = X"A" else -- A000-AFFF + + spram1_do when cpu_addr(15 downto 12) = X"B" and + cpu_addr(10) = '0' else -- B000-B3FF + + spram2_do when cpu_addr(15 downto 12) = X"B" and + cpu_addr(10) = '1' else -- B400-B7FF + + vcnt(7 downto 0) when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "00" else -- C000-C0FF + + X"FF" when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "01" else -- C100-C1FF + + dip_switch_2 when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "10" else -- C200-C2FF + + input_0 when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "11" and + cpu_addr( 6 downto 5) = "00" else -- C300-C31F + + input_1 when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "11" and + cpu_addr( 6 downto 5) = "01" else -- C320-C32F + + input_2 when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "11" and + cpu_addr( 6 downto 5) = "10" else -- C340-C34F + + dip_switch_1 when cpu_addr(15 downto 12) = X"C" and + cpu_addr( 9 downto 8) = "11" and + cpu_addr( 6 downto 5) = "11" else -- C360-C36F + + X"FF"; + +-- working ram address multiplexer cpu/video scanner +wram_addr <= cpu_addr(11 downto 0) when cpu_ena = '1' else + '0' & pxcnt(1) & vcnt(7 downto 3) & hcnt(4 downto 0) when flip = '0' else + '0' & pxcnt(1) & not vcnt(7 downto 3) & not hcnt(4 downto 0); + +-- sprite data ram address multiplexer cpu/sprite scanner +spram_addr <= cpu_addr(7 downto 0) when cpu_ena = '1' else "00" & spcnt & pxcnt(1); + +-- write enable to working ram, sprite data ram and misc registers +wram_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"A" else '0'; +spram1_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"B" and cpu_addr(10) = '0' else '0'; +spram2_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"B" and cpu_addr(10) = '1' else '0'; +C0xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"C" and cpu_addr(9 downto 8) = "00" else '0'; +C3xx_we <= '1' when cpu_wr_n = '0' and cpu_ena = '1' and cpu_addr(15 downto 12) = X"C" and cpu_addr(9 downto 8) = "11" else '0'; + +-- Misc registers : interrupt enable/clear, cocktail flip, sound trigger +process (clock_6) +begin + if rising_edge(clock_6) then + if C0xx_we = '1' then + sound_cmd <= cpu_do; + end if; + + if C3xx_we = '1' then + if cpu_addr(3 downto 1) = "000" then itt_n <= cpu_do(0); end if; + if cpu_addr(3 downto 1) = "001" then flip <= not cpu_do(0); end if; + if cpu_addr(3 downto 1) = "010" then sound_trig <= cpu_do(0); end if; + end if; + + if itt_n = '0' then + cpu_nmi_n <= '1'; + else -- lauch nmi and end of frame + if (vcnt = 493) and (hcnt = "000000") and (pxcnt = "000") then + cpu_nmi_n <= '0'; + end if; + end if; + end if; +end process; + + +---------------------- +--- sprite machine --- +---------------------- +-- sprite data rams are scanned from sprites addresse 31 to 8 at each line + +-- latch current sprite data with respect to pixel and hcnt in relation +-- with sprite data ram addressing +process (clock_6) +begin + if rising_edge(clock_6) then + + if (hcnt(0) = '0') and (pxcnt = "001") then + sp_posh <= spram1_do ; -- a.k.a. X + sp_attr <= spram2_do ; -- color and flip x/y + vcnt_r <= vcnt; + end if; + + -- sprite is on current line if sp_line is below 16 + -- and if sprite vertical position (a.k.a. Y) is below xF0 + if (hcnt(0) = '0') and (pxcnt = "011") then + if sp_line(7 downto 4) = "0000" and spram2_do < X"F0" then + sp_on_line <= '1'; + else + sp_on_line <= '0'; + end if; + end if; + + -- delay sp_color_set + if (hcnt(0) = '0') and (pxcnt = "100") then + sp_color_set <= sp_attr(5 downto 0); + end if; + + end if; +end process; + +-- sp_line (valid only when pxcnt = "011") +sp_line <= not(vcnt_r(7 downto 0)) - spram2_do; + +-- address sprite graphics rom with sprite code and tile number and sprite line counter +-- with respect to sprite flip x/y controls +with sp_attr(7 downto 6) select + sp_graphx_addr <= spram1_do & sp_line(3) & hcnt(0) & pxcnt(2) & sp_line(2 downto 0) when "11", + spram1_do & sp_line(3) & not hcnt(0) & not pxcnt(2) & sp_line(2 downto 0) when "10", + spram1_do & not sp_line(3) & hcnt(0) & pxcnt(2) & not sp_line(2 downto 0) when "01", + spram1_do & not sp_line(3) & not hcnt(0) & not pxcnt(2) & not sp_line(2 downto 0) when others; + +-- latch and shift sprite graphics data with respect to flipx control +-- 8bits => 4x2bits = 4pixels / 4colors (3colors + transparent) +process (clock_6) +begin + if rising_edge(clock_6) then + + if pxcnt(1 downto 0) = "00" then + if sp_on_line = '1' then + if sp_attr(6) = '1' then + sp_pixels <= sp_graphx_do; + else + sp_pixels(3 downto 0) <= sp_graphx_do(0) & sp_graphx_do(1) & sp_graphx_do(2) & sp_graphx_do(3); + sp_pixels(7 downto 4) <= sp_graphx_do(4) & sp_graphx_do(5) & sp_graphx_do(6) & sp_graphx_do(7); + end if; + else + sp_pixels <= (others => '0'); + end if; + else + sp_pixels(3 downto 0) <= sp_pixels(2 downto 0) & '0'; + sp_pixels(7 downto 4) <= sp_pixels(6 downto 4) & '0'; + end if; + + end if; + +end process; + +-- address sprite color palette 4 colors, 64 sets => 16 colors +sp_palette_addr <= sp_color_set & sp_pixels(3) & sp_pixels(7); + +-- write sprite to line buffer at posh position +process (clock_6) +begin + if rising_edge(clock_6) then + if hcnt(0) = '0' and pxcnt = "101" then + sp_buffer_write_addr <= sp_posh; + else + sp_buffer_write_addr <= sp_buffer_write_addr + '1'; + end if; + end if; +end process; + +-- write colors to buffer when not transparent +sp_buffer_write_we <= '0' when sp_palette_do = "0000" else '1'; + +-- read sprite line buffer and erase after read +process (clock_12) +begin + if rising_edge(clock_12) then + if hcnt = "101111" and pxcnt = "111" then + sp_buffer_read_addr <= "11111010"; -- tune horizontal position of sprites + else + if clock_6 = '0' then + sp_buffer_read_addr <= sp_buffer_read_addr + '1'; + else + if vcnt(0) = '0' then + sp_read_out <= sp_buffer_ram1_do; + else + sp_read_out <= sp_buffer_ram2_do; + end if; + end if; + end if; + end if; +end process; + +-- toggle read/write sprite line buffer every other line + +-- wait pxcnt = "101" to allow last sprite (#8) to be written to line buffer +process (clock_6) +begin + if rising_edge(clock_6) then + if pxcnt = "101" then sp_buffer_sel <= vcnt(0); end if; + end if; +end process; + +sp_buffer_ram1_addr <= sp_buffer_read_addr when sp_buffer_sel = '0' else sp_buffer_write_addr; +sp_buffer_ram2_addr <= sp_buffer_read_addr when sp_buffer_sel = '1' else sp_buffer_write_addr; + +sp_buffer_ram1_di <= "0000" when sp_buffer_sel = '0' else sp_palette_do(3 downto 0); +sp_buffer_ram2_di <= "0000" when sp_buffer_sel = '1' else sp_palette_do(3 downto 0); + +sp_buffer_ram1_we <= not clock_6 when sp_buffer_sel = '0' else sp_buffer_write_we; +sp_buffer_ram2_we <= not clock_6 when sp_buffer_sel = '1' else sp_buffer_write_we; + +-------------------- +--- char machine --- +-------------------- + +-- latch current char data with respect to vcnt and hcnt in relation +-- with wram ram addressing +process (clock_6) +begin + if rising_edge(clock_6) and pxcnt = "001" then + ch_data1 <= wram_do ; + end if; + + if rising_edge(clock_6) and pxcnt = "100" then + ch_color_set <= ch_data1(4 downto 0) ; + end if; + +end process; + +-- address char graphics rom with char code, pixel count and vertical line counter +-- with respect to char flip x/y controls +with ch_data1(7 downto 6) select + ch_graphx_addr_f <= ch_data1(5) & wram_do & pxcnt(2) & vcnt(2 downto 0) when "00", + ch_data1(5) & wram_do & not pxcnt(2) & vcnt(2 downto 0) when "01", + ch_data1(5) & wram_do & pxcnt(2) & not(vcnt(2 downto 0)) when "10", + ch_data1(5) & wram_do & not pxcnt(2) & not(vcnt(2 downto 0)) when others; + +-- in cocktail flip mode negate h/v counters +ch_graphx_addr <= ch_graphx_addr_f when flip ='0' else ch_graphx_addr_f xor "0000000001111"; + +-- latch and shift char graphics data with respect to flipx control and cocktail flip control +-- 8bits => 4x2bits = 4pixels / 4colors +process (clock_6) +begin + if rising_edge(clock_6) then + if pxcnt(1 downto 0) = "00" then + if (ch_data1(6) xor flip) = '0' then + ch_pixels <= ch_graphx_do; + else + ch_pixels(3 downto 0) <= ch_graphx_do(0) & ch_graphx_do(1) &ch_graphx_do(2) &ch_graphx_do(3); + ch_pixels(7 downto 4) <= ch_graphx_do(4) & ch_graphx_do(5) &ch_graphx_do(6) &ch_graphx_do(7); + end if; + else + ch_pixels(3 downto 0) <= ch_pixels(2 downto 0) & '0'; + ch_pixels(7 downto 4) <= ch_pixels(6 downto 4) & '0'; + end if; + end if; + +end process; + +-- address char color palette 4 colors, 64 sets => 16 colors +ch_palette_addr <= '0' & ch_color_set & ch_pixels(3) & ch_pixels(7); + +--------------------- +-- mux char/sprite -- +--------------------- + +-- char data controls sprite display/hide +process (clock_6) +begin + if rising_edge(clock_6) then + sp_blank <= ch_color_set(4); + end if; +end process; + +-- select rbg color and bank with respect to char/sprite selection +rgb_palette_addr <= + '1' & ch_palette_do(3 downto 0) when (sp_read_out = "0000" or sp_blank = '1') else + '0' & sp_read_out; + +-- register and assign rbg palette output +process (clock_6) +begin + if rising_edge(clock_6) then + if hblank = '1' or vblank = '1' then + video_r <= "00000"; + video_g <= "00000"; + video_b <= "00000"; + else + video_r <= rgb_palette_gr_do(5 downto 1); + video_g <= rgb_palette_bg_do(2 downto 0) & rgb_palette_gr_do(7 downto 6); + video_b <= rgb_palette_bg_do(7 downto 3); + end if; + end if; +end process; + +video_hblank <= hblank; +video_vblank <= vblank; + +---------------------------- +-- video syncs and blanks -- +---------------------------- + +process(clock_6) + constant hcnt_base : integer := 36; + variable vsync_cnt : std_logic_vector(3 downto 0); +begin + if rising_edge(clock_6) and pxcnt = "110" then + + if hcnt = hcnt_base+0 then hsync0 <= '0'; + elsif hcnt = hcnt_base+3 then hsync0 <= '1'; + end if; + + if hcnt = hcnt_base then + if vcnt = 500 then + vsync_cnt := X"0"; + else + if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + '1'; end if; + end if; + end if; + + if hcnt = hcnt_base-4 then + hblank <= '1'; + if vcnt = 496 then + vblank <= '1'; -- 492 ok + elsif vcnt = 262 then + vblank <= '0'; -- 262 ok + end if; + elsif hcnt = 0 then + hblank <= '0'; + end if; + + video_hs <= hsync0; + + if vsync_cnt = 0 then video_vs <= '0'; + elsif vsync_cnt = 8 then video_vs <= '1'; + end if; + + end if; +end process; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_6, + CLKEN => cpu_ena, + WAIT_n => '1', + INT_n => '1', --cpu_irq_n, + NMI_n => cpu_nmi_n, + BUSRQ_n => '1', + M1_n => open, + MREQ_n => cpu_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.time_pilot_prog +port map( + clk => clock_6n, + addr => cpu_addr(14 downto 0), + data => cpu_rom_do +); + +-- working/char RAM 0xA000-0xAFFF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_6n, + we => wram_we, + addr => wram_addr, + d => cpu_do, + q => wram_do +); + +-- sprite RAM1 0xB000-0xB0FF +spram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_6n, + we => spram1_we, + addr => spram_addr, + d => cpu_do, + q => spram1_do +); + +-- sprite RAM2 0xB400-0xB4FF +spram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_6n, + we => spram2_we, + addr => spram_addr, + d => cpu_do, + q => spram2_do +); + +-- sprite line buffer 1 +splinebuf1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_12n, + we => sp_buffer_ram1_we, + addr => sp_buffer_ram1_addr, + d => sp_buffer_ram1_di, + q => sp_buffer_ram1_do +); + +-- sprite line buffer 2 +splinebuf2 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 8) +port map( + clk => clock_12n, + we => sp_buffer_ram2_we, + addr => sp_buffer_ram2_addr, + d => sp_buffer_ram2_di, + q => sp_buffer_ram2_do +); + +-- char graphics ROM +char_graphics : entity work.time_pilot_char_grphx +port map( + clk => clock_6, + addr => ch_graphx_addr, + data => ch_graphx_do +); + +-- char palette ROM +ch_palette : entity work.time_pilot_char_color_lut +port map( + clk => clock_6, + addr => ch_palette_addr, + data => ch_palette_do +); + +-- sprite graphics ROM +sp_graphics : entity work.time_pilot_sprite_grphx +port map( + clk => clock_6, + addr => sp_graphx_addr, + data => sp_graphx_do +); + +-- sprite palette ROM +sp_palette : entity work.time_pilot_sprite_color_lut +port map( + clk => clock_6, + addr => sp_palette_addr, + data => sp_palette_do +); + +-- rgb palette ROM 1 +rgb_palette_gb : entity work.time_pilot_palette_blue_green +port map( + clk => clock_6, + addr => rgb_palette_addr, + data => rgb_palette_bg_do +); + +-- rgb palette ROM 2 +rgb_palette_br : entity work.time_pilot_palette_green_red +port map( + clk => clock_6, + addr => rgb_palette_addr, + data => rgb_palette_gr_do +); + +-- sound board +time_pilot_sound_board : entity work.time_pilot_sound_board +port map( + clock_14 => clock_14, + reset => reset, + + sound_trig => sound_trig, + sound_cmd => sound_cmd, + + audio_out => audio_out, + + dbg_cpu_addr => open + ); + +end struct; \ No newline at end of file diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_char_color_lut.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_char_color_lut.vhd new file mode 100644 index 00000000..19c3dff9 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_char_color_lut.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_char_color_lut is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_char_color_lut is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"0D",X"0F",X"0C",X"0A",X"04",X"01",X"0F",X"0B",X"04",X"01",X"0F",X"0C",X"04",X"01",X"0F", + X"0E",X"04",X"01",X"0F",X"00",X"04",X"01",X"0F",X"0A",X"04",X"05",X"01",X"0B",X"04",X"05",X"01", + X"0C",X"04",X"05",X"01",X"0E",X"04",X"05",X"01",X"00",X"04",X"05",X"01",X"0A",X"06",X"08",X"02", + X"0B",X"06",X"08",X"02",X"0C",X"06",X"08",X"02",X"0E",X"06",X"08",X"02",X"00",X"06",X"08",X"02", + X"00",X"01",X"04",X"0F",X"00",X"04",X"02",X"06",X"00",X"01",X"08",X"04",X"00",X"0D",X"01",X"05", + X"00",X"02",X"03",X"01",X"00",X"0C",X"0F",X"03",X"00",X"05",X"02",X"08",X"0A",X"01",X"04",X"03", + X"00",X"06",X"0F",X"02",X"00",X"0F",X"03",X"05",X"00",X"03",X"01",X"0F",X"0A",X"02",X"0D",X"05", + X"00",X"01",X"0F",X"08",X"0A",X"02",X"0D",X"05",X"0A",X"0B",X"09",X"0F",X"09",X"09",X"09",X"09", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_char_grphx.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_char_grphx.vhd new file mode 100644 index 00000000..3ca4ff51 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_char_grphx.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_char_grphx is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_char_grphx is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"99",X"99",X"99",X"99",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"EE",X"00", + X"70",X"30",X"10",X"32",X"32",X"32",X"30",X"1E",X"00",X"80",X"C4",X"C4",X"C4",X"C4",X"80",X"0E", + X"CC",X"EE",X"BB",X"99",X"88",X"CC",X"CC",X"00",X"00",X"00",X"00",X"EE",X"EE",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"04", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"CF",X"FF",X"FF",X"FF",X"EC",X"07",X"9E",X"FC",X"3F",X"FF",X"FF",X"FF",X"11",X"00",X"00",X"0C", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"8F",X"0F",X"08",X"00",X"00",X"11",X"FF",X"FC",X"FC",X"9E",X"03",X"EC",X"FC",X"FC",X"FC", + X"07",X"9E",X"FC",X"EF",X"EF",X"FF",X"FF",X"FF",X"33",X"80",X"0C",X"0F",X"0F",X"8F",X"EF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_mist.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_mist.vhd new file mode 100644 index 00000000..9e263c43 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_mist.vhd @@ -0,0 +1,290 @@ +--------------------------------------------------------------------------------- +-- Mist Top level for Time pilot by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Use time_pilot_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +-- Uses 1 pll for 12MHz and 14MHz generation from 27MHz +-- +-- Mist key : +-- Right Button : reset game +-- +-- Keyboard players inputs : +-- +-- ESC : Add coin +-- 2 : Start 2 players +-- 1 : Start 1 player +-- SPACE : Fire +-- RIGHT arrow : rotate right +-- LEFT arrow : rotate left +-- UP arrow : rotate up +-- DOWN arrow : rotate down +-- +-- Other details : see time_pilot.vhd + +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; + +entity time_pilot_mist is +port( + CLOCK_27 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0); + VGA_VS : out std_logic; + VGA_HS : out std_logic; + LED : out std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic +); +end time_pilot_mist; + +architecture struct of time_pilot_mist is + + signal clock_48 : std_logic; + signal clock_12 : std_logic; + signal clock_14 : std_logic; + signal reset : std_logic; + signal pll_locked: std_logic; + + signal r : std_logic_vector(4 downto 0); + signal g : std_logic_vector(4 downto 0); + signal b : std_logic_vector(4 downto 0); + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic; + signal audio : std_logic_vector(10 downto 0); + signal audio_pwm : std_logic; + signal reset_n : std_logic; + signal ps2_clk : std_logic; + signal ps2_dat : std_logic; + signal joy_u : std_logic; + signal joy_l : std_logic; + signal joy_r : std_logic; + signal joy_d : std_logic; + signal scanlines : std_logic_vector(1 downto 0); + signal hq2x : std_logic; + signal buttons : std_logic_vector(1 downto 0); + signal joy0 : std_logic_vector(7 downto 0); + signal joy1 : std_logic_vector(7 downto 0); + signal status : std_logic_vector(31 downto 0); + signal scandoubler_disable : std_logic; + signal ypbpr : std_logic; + signal pix_ce : std_logic; + signal kbd_joy0 : std_logic_vector(7 downto 0); + signal ps2Clk : std_logic; + signal ps2Data : std_logic; + signal VGA_R_O : std_logic_vector(2 downto 0); + signal VGA_G_O : std_logic_vector(2 downto 0); + signal VGA_B_O : std_logic_vector(2 downto 0); + + + constant CONF_STR : string := + "Time Pilot;;O4,Joystick Control,Upright,Normal;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.00"; + + function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + end function; + + component mist_io + generic ( STRLEN : integer := 0 ); + port ( + clk_sys :in std_logic; + SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; + SPI_DO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + buttons : out std_logic_vector(1 downto 0); + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + status : out std_logic_vector(31 downto 0); + scandoubler_disable, ypbpr : out std_logic; + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); + end component mist_io; + + component video_mixer + generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 ); + port ( + clk_sys, ce_pix, ce_pix_actual : in std_logic; + SPI_SCK, SPI_SS3, SPI_DI : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; + R, G, B : in std_logic_vector(2 downto 0); + HSync, VSync, line_start, mono : in std_logic; + VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); + VGA_VS, VGA_HS : out std_logic + ); + end component video_mixer; + + component keyboard + PORT( + clk : in std_logic; + reset : in std_logic; + ps2_kbd_clk : in std_logic; + ps2_kbd_data : in std_logic; + joystick : out std_logic_vector (7 downto 0) + ); + end component; + +begin + +reset <= status(0) or status(5) or buttons(1) or not pll_locked; + +clocks : entity work.mist_pll_12M_14M + port map( + inclk0 => CLOCK_27, + c0 => clock_12,--12.28800000 + c1 => clock_14,--14.31800000 + c2 => clock_48, + locked => pll_locked +); + +scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0'; +scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0'; +hq2x <= '1' when status(9 downto 8) = "01" else '0'; + +vmixer : video_mixer + port map ( + clk_sys => clock_48, + ce_pix => pix_ce, + ce_pix_actual => pix_ce, + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + scanlines => scanlines, + scandoubler_disable => scandoubler_disable, + hq2x => hq2x, + ypbpr => ypbpr, + ypbpr_full => '1', + R => VGA_R_O, + G => VGA_G_O, + B => VGA_B_O, + HSync => hsync, + VSync => vsync, + line_start => '0', + mono => '0', + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_VS => VGA_VS, + VGA_HS => VGA_HS +); + +mist_io_inst : mist_io + generic map (STRLEN => CONF_STR'length) + port map ( + clk_sys => clock_48, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_DI => SPI_DI, + SPI_DO => SPI_DO, + conf_str => to_slv(CONF_STR), + buttons => buttons, + scandoubler_disable => scandoubler_disable, + ypbpr => ypbpr, + joystick_1 => joy1, + joystick_0 => joy0, + status => status, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data +); + +Joy_r <= joy0(0) or joy1(0) or kbd_joy0(7) when status(4) = '0' + else joy0(3) or joy1(3) or kbd_joy0(4); +Joy_l <= joy0(1) or joy1(1) or kbd_joy0(6) when status(4) = '0' + else joy0(2) or joy1(2) or kbd_joy0(5); +Joy_u <= joy0(3) or joy1(3) or kbd_joy0(4) when status(4) = '0' + else joy0(1) or joy1(1) or kbd_joy0(6); +Joy_d <= joy0(2) or joy1(2) or kbd_joy0(5) when status(4) = '0' + else joy0(0) or joy1(0) or kbd_joy0(7); + +time_pilot : entity work.time_pilot + port map( + clock_12 => clock_12, + clock_14 => clock_14, + reset => reset, + video_r => r, + video_g => g, + video_b => b, + video_hblank => open, + video_vblank => open, + video_clk => pix_ce, + video_hs => hsync, + video_vs => vsync, + audio_out => audio, + dip_switch_1 => X"FF", -- Coinage_B / Coinage_A + dip_switch_2 => X"4B", -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + start2 => kbd_joy0(2) or status(3), + start1 => kbd_joy0(1) or status(2), + coin1 => kbd_joy0(3) or status(1), + fire1 => joy0(4) or joy1(4) or kbd_joy0(0), + right1 => Joy_r, + left1 => Joy_l, + down1 => Joy_d, + up1 => Joy_u, + fire2 => joy0(4) or joy1(4) or kbd_joy0(0), + right2 => Joy_r, + left2 => Joy_l, + down2 => Joy_d, + up2 => Joy_u, + dbg_cpu_addr => open +); + + +VGA_R_O <= r(4 downto 2); +VGA_G_O <= g(4 downto 2); +VGA_B_O <= b(4 downto 2); + +u_keyboard : keyboard + port map( + clk => clock_48, + reset => reset, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data, + joystick => kbd_joy0 +); + +u_dac : entity work.dac + port map( + clk_i => clock_48, + res_n_i => not reset, + dac_i => audio, + dac_o => audio_pwm +); + +AUDIO_L <= audio_pwm; +AUDIO_R <= audio_pwm; + + LED <= '1'; +end struct; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_palette_blue_green.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_palette_blue_green.vhd new file mode 100644 index 00000000..7e5dbed5 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_palette_blue_green.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_palette_blue_green is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_palette_blue_green is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"05",X"06",X"07",X"FC",X"05",X"BD",X"B5",X"FD",X"05",X"B0",X"A5",X"E0",X"00",X"F7", + X"00",X"00",X"F8",X"07",X"07",X"FD",X"F8",X"FA",X"05",X"DE",X"50",X"51",X"32",X"FD",X"30",X"F7"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_palette_green_red.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_palette_green_red.vhd new file mode 100644 index 00000000..868befaf --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_palette_green_red.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_palette_green_red is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_palette_green_red is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"3E",X"3E",X"80",X"FE",X"00",X"AC",X"EE",X"AC",X"C0",X"14",X"00",X"28",X"38",X"16",X"BC", + X"00",X"3E",X"00",X"C0",X"FE",X"C0",X"3E",X"80",X"3E",X"F6",X"00",X"80",X"80",X"00",X"0C",X"BC"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_prog.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_prog.vhd new file mode 100644 index 00000000..d310fd8c --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_prog.vhd @@ -0,0 +1,1558 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_prog is + type rom is array(0 to 24575) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C3",X"B1",X"07",X"FF",X"FF",X"FF",X"33",X"4B",X"85",X"6F",X"30",X"01",X"24",X"7E",X"C9",X"4F", + X"87",X"DF",X"5E",X"23",X"56",X"23",X"C9",X"4E",X"85",X"6F",X"D0",X"24",X"C9",X"FF",X"FF",X"41", + X"7B",X"D6",X"20",X"5F",X"D0",X"15",X"C9",X"4D",X"7B",X"C6",X"20",X"5F",X"D0",X"14",X"C9",X"49", + X"E1",X"D7",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"E5",X"26",X"AC",X"3A",X"B2",X"A9",X"6F",X"CB", + X"7E",X"28",X"0A",X"72",X"2C",X"73",X"2C",X"7D",X"E6",X"3F",X"32",X"B2",X"A9",X"E1",X"C9",X"0F", + X"A7",X"11",X"ED",X"77",X"68",X"D7",X"34",X"F1",X"D7",X"A5",X"3B",X"7C",X"FD",X"3B",X"7D",X"F1", + X"DC",X"A5",X"8C",X"57",X"34",X"B9",X"C3",X"D8",X"00",X"32",X"00",X"C2",X"21",X"11",X"B4",X"06", + X"30",X"36",X"00",X"23",X"10",X"FB",X"32",X"00",X"C2",X"21",X"10",X"B4",X"06",X"30",X"36",X"00", + X"23",X"10",X"FB",X"32",X"00",X"C2",X"21",X"00",X"A8",X"11",X"01",X"A8",X"01",X"FF",X"07",X"36", + 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mode 100644 index 00000000..44bbb38f --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd @@ -0,0 +1,426 @@ +--------------------------------------------------------------------------------- +-- Time pilot sound board by Dar (darfpga@aol.fr) (29/10/2017) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- YM2149 (AY-3-8910) +-- Copyright (c) MikeJ - Jan 2005 +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity time_pilot_sound_board is +port( + clock_14 : in std_logic; + reset : in std_logic; + + sound_cmd : in std_logic_vector(7 downto 0); + sound_trig : in std_logic; + + audio_out : out std_logic_vector(10 downto 0); + + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end time_pilot_sound_board; + +architecture struct of time_pilot_sound_board is + + signal reset_n: std_logic; + signal clock_14n : std_logic; + + signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0'); + signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0'); + + signal cpu_clock : std_logic; + signal ayx_clock : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_iorq_n : std_logic; + signal cpu_m1_n : std_logic; + + signal cpu_rom_do : std_logic_vector( 7 downto 0); + signal wram_do : std_logic_vector( 7 downto 0); + signal wram_we : std_logic; + + signal clr_irq_n : std_logic; + signal sen1_n : std_logic; + signal sen2_n : std_logic; + signal sen3_n : std_logic; + signal sen4_n : std_logic; + + signal sound_trig_r : std_logic; + + signal ay1_do : std_logic_vector(7 downto 0); + signal ay1_cs_n : std_logic; + signal ay1_bdir : std_logic; + signal ay1_bc1 : std_logic; + signal ay1_audio_muxed : std_logic_vector(7 downto 0); + signal ay1_audio_chan : std_logic_vector(1 downto 0); + signal ay1_port_b_di : std_logic_vector(7 downto 0); + + signal ay2_do : std_logic_vector(7 downto 0); + signal ay2_cs_n : std_logic; + signal ay2_bdir : std_logic; + signal ay2_bc1 : std_logic; + signal ay2_audio_muxed : std_logic_vector(7 downto 0); + signal ay2_audio_chan : std_logic_vector(1 downto 0); + + signal ay1_chan_a : std_logic_vector(7 downto 0); + signal ay1_chan_b : std_logic_vector(7 downto 0); + signal ay1_chan_c : std_logic_vector(7 downto 0); + signal ay2_chan_a : std_logic_vector(7 downto 0); + signal ay2_chan_b : std_logic_vector(7 downto 0); + signal ay2_chan_c : std_logic_vector(7 downto 0); + + signal filter_cmd_we : std_logic; + signal filter_cmd : std_logic_vector(11 downto 0); + signal mult_cmd : std_logic_vector(1 downto 0); + signal mult_value : integer range 0 to 779; + + signal Vc_1a : integer range -256*1024 to 256*1024-1; + signal Vc_1b : integer range -256*1024 to 256*1024-1; + signal Vc_1c : integer range -256*1024 to 256*1024-1; + signal Vc_2a : integer range -256*1024 to 256*1024-1; + signal Vc_2b : integer range -256*1024 to 256*1024-1; + signal Vc_2c : integer range -256*1024 to 256*1024-1; + signal Vc : integer range -256*1024 to 256*1024-1; + signal Vin : integer range -256 to 255; + signal dV : integer range -512 to 511; + signal Vcn_a : integer range -1024*1024 to 1024*1024-1; + signal Vcn_b : integer range -1024*1024 to 1024*1024-1; + signal Vcn_c : integer range -256*1024 to 256*1024-1; + +begin + +clock_14n <= not clock_14; +reset_n <= not reset; + +-- debug +process (reset, clock_14) +begin + if rising_edge(clock_14) and cpu_mreq_n ='0' then + dbg_cpu_addr <= cpu_addr; + end if; +end process; + +-------------------------------------------------------- +-- RC filters equation +-- +-- Vc : capacitor voltage = output voltage +-- fs : sample frequency +-- Vin : voltage at resistor input +-- +-- Vc(k+1) = Vc(k) + (Vin-Vc(k))/(fs.R.C) +-- +-- Vcn * 1024 <= Vcn * 1024 + (Vin-Vc) * 1024/(fs.R.C) +-- With Vcn = 1024 * Vc +-------------------------------------------------------- +-- Filters will be run at 14.318MHz/512 = 27.96KHz +-------------------------------------------------------- +-- 6 filters have to be implemented +-- RC equation is time multiplexed to save multiplier +-- for small FPGA +-------------------------------------------------------- + +-- mux Vc +with clock_div1(3 downto 0) select +Vc <= Vc_1a when X"0", -- Vc_xy : [0..255*1024] + Vc_1b when X"1", -- => Vc : [-256*1024..255*1024] + Vc_1c when X"2", + Vc_2a when X"3", + Vc_2b when X"4", + Vc_2c when others; + +-- mux Vin +with clock_div1(3 downto 0) select +Vin <= to_integer(unsigned(ay1_chan_a)) when X"0", -- ayx_chan_y : [0..255] + to_integer(unsigned(ay1_chan_b)) when X"1", -- => Vin : [-256:255] + to_integer(unsigned(ay1_chan_c)) when X"2", + to_integer(unsigned(ay2_chan_a)) when X"3", + to_integer(unsigned(ay2_chan_b)) when X"4", + to_integer(unsigned(ay2_chan_c)) when others; + +-- compute dV +dV <= Vin-Vc/1024; -- Vc/1024 : [0..255], dv : [-255..511] => [-512..511] + +-- mux filter cmd +with clock_div1(3 downto 0) select +mult_cmd <= filter_cmd( 7 downto 6) when X"0", + filter_cmd( 9 downto 8) when X"1", + filter_cmd(11 downto 10) when X"2", + filter_cmd( 1 downto 0) when X"3", + filter_cmd( 3 downto 2) when X"4", + filter_cmd( 5 downto 4) when others; + +-- mux multiplier value +with mult_cmd select +mult_value <= 779 when "10", -- 0.047uF/1KOhm => (1024/fs.R.C = 779, cut fcy 3386Hz) + 166 when "01", -- 0.220uF/1KOhm => (1024/fs.R.C = 166, cut fcy 723Hz) + 137 when "11", -- 0.267uF/1KOhm => (1024/fs.R.C = 137, cut fcy 596Hz) + 779 when others; -- Not use + +-- compute Vcn +Vcn_a <= Vin*1024 when mult_cmd = "00" else Vc + dv*mult_value; -- => Vcn_a : [-1024*1024..1023*1024] + +-- limit to > 0 +Vcn_b <= 0 when Vcn_a < 0 else Vcn_a; + +-- limit to < 255*1024 +Vcn_c <= 255*1024 when Vcn_b > 255*1024 else Vcn_b; + +-- demux/store result and mix channels +process (clock_14) +begin + if rising_edge(clock_14) then -- 14.318MHz/512 => fs = 27.96KHz + + -- demux & down sample + if clock_div1(8 downto 0) = '0'&X"00" then Vc_1a <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"01" then Vc_1b <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"02" then Vc_1c <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"03" then Vc_2a <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"04" then Vc_2b <= Vcn_c; end if; + if clock_div1(8 downto 0) = '0'&X"05" then Vc_2c <= Vcn_c; end if; + + -- rescale and mix channels with down sample + if clock_div1(8 downto 0) = '0'&X"06" then + audio_out <= std_logic_vector(to_unsigned(Vc_1a/1024,11)) + + std_logic_vector(to_unsigned(Vc_1b/1024,11)) + + std_logic_vector(to_unsigned(Vc_1c/1024,11)) + + std_logic_vector(to_unsigned(Vc_2a/1024,11)) + + std_logic_vector(to_unsigned(Vc_2b/1024,11)) + + std_logic_vector(to_unsigned(Vc_2c/1024,11)); + end if; + end if; +end process; + + +-- divide clocks +-- random generator ? +process (clock_14) +begin + if reset='1' then + clock_div1 <= (others =>'0'); + biquinary_div <= (others =>'0'); + else + if rising_edge(clock_14) then + clock_div1 <= clock_div1 + '1'; + + if clock_div1 = X"800" then + if biquinary_div(3 downto 1) = "100" then + biquinary_div(3 downto 1) <= "000"; + biquinary_div(0) <= not biquinary_div(0); + else + biquinary_div(3 downto 1) <= biquinary_div(3 downto 1) + '1'; + end if; + end if; + + end if; + end if; +end process; + +-- make clocks for cpu and sound generators +cpu_clock <= clock_div1(2); +ayx_clock <= not clock_div1(2); + +-- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF + wram_do when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF + ay1_do when cpu_addr(15 downto 13) = "010" else -- 4000-5FFF + ay2_do when cpu_addr(15 downto 13) = "011" else -- 6000-7FFF + X"FF"; + +-- write enable to working ram and filter command register +wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = "0011" else '0'; +filter_cmd_we <= '1' when cpu_wr_n = '0' and cpu_addr(15) = '1' else '0'; + +-- chip select with r/w direction to AY chips +sen1_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"4" else '1'; +sen2_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"5" else '1'; +sen3_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"6" else '1'; +sen4_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"7" else '1'; + +-- finalise AY r/w & address controls +ay1_bc1 <= not sen2_n or ( cpu_wr_n and not sen1_n); +ay1_bdir <= not sen2_n or (not cpu_wr_n and not sen1_n); +ay1_cs_n <= sen1_n and sen2_n; + +ay2_bc1 <= not sen4_n or ( cpu_wr_n and not sen3_n); +ay2_bdir <= not sen4_n or (not cpu_wr_n and not sen3_n); +ay2_cs_n <= sen3_n and sen4_n; + +-- input random (?) to AY1 chip +ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(11)&"0000"; + +-- clear irq when reset and irq acknowledge +clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n); + +-- regsiter filters commands (11 bits data are cpu address) +process (cpu_clock) +begin + if rising_edge(cpu_clock) then + if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if; + end if; +end process; + +-- latch sound trigger rising edge to set cpu_irq, and manage clear +process (clock_14) +begin + if rising_edge(clock_14) then + + sound_trig_r <= sound_trig; + + if clr_irq_n = '0' then + cpu_irq_n <= '1'; + else + if sound_trig ='1' and sound_trig_r = '0' then + cpu_irq_n <= '0'; + end if; + end if; + + end if; +end process; + +-- demux AY chips output +process (ayx_clock) +begin + if rising_edge(ayx_clock) then + if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; + if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; + if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; + if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; + if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; + if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; + end if; +end process; + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => cpu_clock, + CLKEN => '1', + WAIT_n => '1', + INT_n => cpu_irq_n, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_iorq_n, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu1 program ROM +rom_cpu1 : entity work.time_pilot_sound_prog +port map( + clk => clock_14n, + addr => cpu_addr(11 downto 0), + data => cpu_rom_do +); + +-- working RAM +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_14n, + we => wram_we, + addr => cpu_addr(9 downto 0), + d => cpu_do, + q => wram_do +); + +-- AY-3-8910 #1 +ay_3_8910_1 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => ay1_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => ay1_cs_n, -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay1_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay1_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => sound_cmd, -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => ay1_port_b_di, -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + +-- AY-3-8910 #2 +ay_3_8910_2 : entity work.YM2149 +port map( + -- data bus + I_DA => cpu_do, -- in std_logic_vector(7 downto 0); + O_DA => ay2_do, -- out std_logic_vector(7 downto 0); + O_DA_OE_L => open, -- out std_logic; + -- control + I_A9_L => ay2_cs_n, -- in std_logic; + I_A8 => '1', -- in std_logic; + I_BDIR => ay2_bdir, -- in std_logic; + I_BC2 => '1', -- in std_logic; + I_BC1 => ay2_bc1, -- in std_logic; + I_SEL_L => '1', -- in std_logic; + + O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); + O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); + + -- port a + I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOA => open, -- out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, -- out std_logic; + -- port b + I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); + O_IOB => open, -- out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, -- out std_logic; + + ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation + RESET_L => reset_n, -- in std_logic; + CLK => ayx_clock -- in std_logic -- note 6 Mhz +); + + +end struct; \ No newline at end of file diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_prog.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_prog.vhd new file mode 100644 index 00000000..220e010c --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sound_prog.vhd @@ -0,0 +1,236 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_sound_prog is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_sound_prog is + type rom is array(0 to 3419) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"30",X"06",X"00",X"C3",X"9B",X"00",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF", + X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"32",X"00",X"50",X"79",X"32",X"00",X"40",X"C9", + X"32",X"00",X"70",X"79",X"32",X"00",X"60",X"C9",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9", + X"3E",X"0E",X"CF",X"B7",X"28",X"2F",X"57",X"E6",X"7F",X"FE",X"21",X"D0",X"CB",X"7A",X"20",X"42", + X"CD",X"80",X"00",X"20",X"1C",X"CD",X"80",X"00",X"20",X"16",X"21",X"00",X"30",X"1E",X"06",X"7E", + X"1D",X"28",X"08",X"2C",X"2C",X"BE",X"38",X"F8",X"C3",X"5F",X"00",X"BA",X"D0",X"CD",X"80",X"00", + X"72",X"2C",X"36",X"00",X"C9",X"21",X"00",X"30",X"06",X"0C",X"AF",X"77",X"2C",X"10",X"FC",X"C9", + X"21",X"00",X"30",X"06",X"06",X"0E",X"07",X"BE",X"28",X"05",X"2C",X"2C",X"10",X"F9",X"41",X"79", + X"90",X"C9",X"CD",X"80",X"00",X"C8",X"AF",X"77",X"2C",X"77",X"C9",X"70",X"23",X"7C",X"FE",X"34", + X"20",X"F9",X"F9",X"ED",X"56",X"21",X"00",X"80",X"22",X"0C",X"30",X"77",X"0E",X"00",X"16",X"06", + X"7A",X"CD",X"9C",X"01",X"15",X"20",X"F9",X"0E",X"38",X"3E",X"07",X"DF",X"3E",X"07",X"E7",X"FB", + X"3E",X"0F",X"CF",X"E6",X"F0",X"20",X"F9",X"F3",X"3E",X"01",X"32",X"0E",X"30",X"3A",X"01",X"30", + X"B7",X"3A",X"00",X"30",X"28",X"06",X"CD",X"7F",X"01",X"C3",X"DF",X"00",X"CD",X"69",X"01",X"FB", + X"00",X"00",X"F3",X"3E",X"02",X"32",X"0E",X"30",X"3A",X"03",X"30",X"B7",X"3A",X"02",X"30",X"28", + X"06",X"CD",X"7F",X"01",X"C3",X"FA",X"00",X"CD",X"69",X"01",X"FB",X"00",X"00",X"F3",X"3E",X"03", + X"32",X"0E",X"30",X"3A",X"05",X"30",X"B7",X"3A",X"04",X"30",X"28",X"06",X"CD",X"7F",X"01",X"C3", + X"15",X"01",X"CD",X"69",X"01",X"FB",X"00",X"00",X"F3",X"3E",X"04",X"32",X"0E",X"30",X"3A",X"07", + X"30",X"B7",X"3A",X"06",X"30",X"28",X"06",X"CD",X"7F",X"01",X"C3",X"30",X"01",X"CD",X"69",X"01", + X"FB",X"00",X"00",X"F3",X"3E",X"05",X"32",X"0E",X"30",X"3A",X"09",X"30",X"B7",X"3A",X"08",X"30", + X"28",X"06",X"CD",X"7F",X"01",X"C3",X"4B",X"01",X"CD",X"69",X"01",X"FB",X"00",X"00",X"F3",X"3E", + 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X"6F",X"2A",X"2A",X"2A",X"2A",X"8A",X"60",X"8F",X"60",X"6F",X"8A",X"60",X"8F",X"8F",X"6F",X"6A", + X"6F",X"6A",X"6E",X"DF",X"0A",X"0D",X"1F",X"0E",X"3F",X"16",X"5F",X"09",X"BF",X"B3",X"B2",X"A9", + X"B0",X"B9",X"BB",X"BA",X"AE",X"E2",X"B7",X"B3",X"B4",X"C1",X"B5",X"B9"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sprite_color_lut.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sprite_color_lut.vhd new file mode 100644 index 00000000..4ca4a971 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sprite_color_lut.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_sprite_color_lut is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_sprite_color_lut is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"0D",X"0F",X"05",X"00",X"0E",X"06",X"0A",X"00",X"04",X"09",X"01",X"00",X"04",X"09",X"01", + X"00",X"04",X"09",X"01",X"00",X"0C",X"05",X"01",X"00",X"0E",X"05",X"01",X"00",X"0D",X"05",X"01", + X"00",X"0B",X"05",X"01",X"00",X"01",X"0F",X"04",X"00",X"01",X"0F",X"04",X"00",X"01",X"0F",X"04", + X"00",X"08",X"07",X"0C",X"00",X"01",X"0F",X"04",X"00",X"01",X"0F",X"04",X"00",X"0A",X"05",X"01", + X"00",X"05",X"09",X"01",X"00",X"0B",X"0D",X"05",X"00",X"06",X"05",X"01",X"00",X"0A",X"03",X"01", + X"00",X"0C",X"03",X"01",X"00",X"0E",X"03",X"01",X"00",X"0D",X"03",X"01",X"00",X"0B",X"03",X"01", + X"00",X"0E",X"0C",X"0F",X"00",X"05",X"03",X"01",X"00",X"0E",X"06",X"09",X"00",X"04",X"09",X"05", + X"00",X"09",X"0E",X"06",X"00",X"04",X"0E",X"05",X"00",X"09",X"0E",X"05",X"00",X"0B",X"05",X"01", + X"00",X"0C",X"07",X"01",X"00",X"05",X"0F",X"09",X"00",X"05",X"04",X"09",X"00",X"0A",X"03",X"01", + X"00",X"0C",X"02",X"03",X"00",X"0C",X"06",X"03",X"00",X"0C",X"06",X"09",X"00",X"0C",X"06",X"01", + X"00",X"0E",X"06",X"0C",X"00",X"0C",X"02",X"0F",X"00",X"0C",X"02",X"09",X"00",X"0C",X"02",X"01", + X"00",X"01",X"08",X"0F",X"00",X"0E",X"06",X"0F",X"00",X"09",X"0A",X"0F",X"00",X"05",X"06",X"0F", + X"00",X"0B",X"09",X"05",X"00",X"0A",X"06",X"0C",X"00",X"0A",X"06",X"09",X"00",X"0A",X"02",X"09", + X"00",X"06",X"01",X"0F",X"00",X"04",X"01",X"0F",X"00",X"0A",X"03",X"01",X"00",X"0A",X"02",X"0C", + X"00",X"05",X"09",X"01",X"00",X"0A",X"02",X"01",X"00",X"0E",X"02",X"09",X"00",X"0E",X"02",X"0C", + X"00",X"01",X"04",X"0F",X"00",X"01",X"04",X"0F",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sprite_grphx.vhd b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sprite_grphx.vhd new file mode 100644 index 00000000..f25833f9 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/time_pilot_sprite_grphx.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity time_pilot_sprite_grphx is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of time_pilot_sprite_grphx is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"11",X"33",X"67",X"47",X"8F",X"CF",X"9F",X"77",X"FF",X"FF",X"7F",X"FF",X"7F",X"7F",X"CC", + X"EE",X"CD",X"88",X"00",X"88",X"8C",X"06",X"03",X"00",X"00",X"08",X"08",X"08",X"04",X"04",X"04", + X"FF",X"FF",X"FF",X"77",X"77",X"33",X"11",X"00",X"CC",X"EE",X"EF",X"00",X"00",X"01",X"8E",X"00", + X"21",X"70",X"1F",X"10",X"01",X"0E",X"00",X"00",X"94",X"BC",X"88",X"08",X"40",X"40",X"80",X"00", + X"00",X"11",X"33",X"77",X"67",X"CF",X"8F",X"CF",X"77",X"FF",X"EE",X"EE",X"FF",X"FF",X"6E",X"4C", + X"CE",X"8A",X"01",X"01",X"00",X"8C",X"02",X"01",X"00",X"00",X"00",X"00",X"08",X"08",X"14",X"94", + X"DF",X"DF",X"FF",X"77",X"77",X"33",X"11",X"00",X"CC",X"EE",X"EF",X"CC",X"88",X"88",X"CD",X"46", + X"30",X"30",X"0F",X"00",X"01",X"06",X"08",X"00",X"EC",X"CC",X"84",X"28",X"10",X"10",X"00",X"00", + X"00",X"11",X"33",X"77",X"77",X"FF",X"DF",X"DF",X"46",X"CD",X"88",X"88",X"CC",X"EF",X"EE",X"CC", + X"00",X"08",X"06",X"01",X"00",X"0F",X"30",X"30",X"00",X"00",X"10",X"10",X"28",X"84",X"CC",X"EC", + X"CF",X"8F",X"CF",X"67",X"77",X"33",X"11",X"00",X"4C",X"6E",X"FF",X"FF",X"EE",X"EE",X"FF",X"77", + X"01",X"02",X"8C",X"00",X"01",X"01",X"8A",X"CE",X"94",X"14",X"08",X"08",X"00",X"00",X"00",X"00", + X"00",X"11",X"33",X"77",X"77",X"FF",X"FF",X"FF",X"00",X"8E",X"01",X"00",X"00",X"EF",X"EE",X"CC", + X"00",X"00",X"0E",X"01",X"10",X"1F",X"70",X"21",X"00",X"80",X"40",X"40",X"08",X"88",X"BC",X"94", + X"9F",X"CF",X"8F",X"47",X"67",X"33",X"11",X"00",X"CC",X"7F",X"7F",X"FF",X"7F",X"FF",X"FF",X"77", + X"03",X"06",X"8C",X"88",X"00",X"88",X"CD",X"EE",X"04",X"04",X"04",X"08",X"08",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"33",X"44",X"88",X"AA",X"AA",X"99",X"44",X"33",X"CC",X"22",X"11",X"55",X"55",X"99",X"22",X"CC", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"FF",X"88",X"88",X"88",X"FF",X"77",X"00",X"CC",X"EE",X"22",X"22",X"22",X"EE",X"CC",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qpf b/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qpf new file mode 100644 index 00000000..91b40ed1 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2016 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition +# Date created = 11:17:10 October 25, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "11:17:10 October 25, 2017" + +# Revisions + +PROJECT_REVISION = "time_pilot_mist" diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf b/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf new file mode 100644 index 00000000..14700b3e --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf @@ -0,0 +1,166 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 14:18:08 November 05, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# time_pilot_mist_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name TOP_LEVEL_ENTITY time_pilot_mist + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" + +# Fitter Assignments +# ================== +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + + + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 + + + +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE rtl/time_pilot_mist.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot.vhd +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/time_pilot_sprite_grphx.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_sprite_color_lut.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_prog.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_prog.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_palette_green_red.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_palette_blue_green.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_char_grphx.vhd +set_global_assignment -name VHDL_FILE rtl/time_pilot_char_color_lut.vhd +set_global_assignment -name VHDL_FILE rtl/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80se.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name QIP_FILE rtl/mist_pll_12M_14M.qip +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_video.vhd +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.srf b/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.srf new file mode 100644 index 00000000..e413eda9 --- /dev/null +++ b/Arcade/Konami Classic/Time_Pilot_MiST/time_pilot_mist.srf @@ -0,0 +1 @@ +{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qpf b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qpf new file mode 100644 index 00000000..790ac5e0 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "CosmicAvenger" diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf new file mode 100644 index 00000000..2ed25465 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.qsf @@ -0,0 +1,206 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:02:22 November 16, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CosmicAvenger_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd +set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_timing.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rgb.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_res.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rams.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_machine.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_gpio.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_dip_pack.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_cpu_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_counter.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_clk.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/CosmicAvenger.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TOP_LEVEL_ENTITY CosmicAvenger + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(CosmicAvenger) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(CosmicAvenger) +# ------------------- +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.srf b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/CosmicAvenger.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/README.txt b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/README.txt new file mode 100644 index 00000000..fa035762 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Cosmic Avenger port to MiST by Gehstock +-- 14 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Lady Bug hardware +-- Unknown Author on Papilio Plus board. +--------------------------------------------------------------------------------- +-- +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- L. ALT : Bomb +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + + +ToDo : Sound diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/Release/CosmicAvenger.rbf b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/Release/CosmicAvenger.rbf new file mode 100644 index 00000000..c41379dd Binary files /dev/null and b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/Release/CosmicAvenger.rbf differ diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/clean.bat b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv new file mode 100644 index 00000000..95eed6d1 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/CosmicAvenger.sv @@ -0,0 +1,194 @@ +//============================================================================ +// Arcade: Cosmic Avenger +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module CosmicAvenger +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "C.Avenger;;", +// "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire signed[7:0] audio_s; +reg [6:0] audio; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(440), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_vid), + .ce_pix_actual(ce_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? {r} : "0"), + .G(blankn ? {g&g} : "00"), + .B(blankn ? {b} : "0"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire blankn = ~(hblank | vblank); + + + +//condition ? if true : if false +ladybugt ladybugt +( + .CLK_IN(clk_sys), + .I_RESET(status[0] | status[6] | buttons[1]), + .O_PIXCE(ce_vid), + + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_VSYNC(vs), + .O_HSYNC(hs), + .O_VBLANK(vblank), + .O_HBLANK(hblank), + + .O_AUDIO(audio_s), + + .but_coin_s(~{1'b0,m_coin}), + .but_fire_s(~{1'b0,m_fire}), + .but_bomb_s(~{1'b0,m_bomb}), + .but_tilt_s(~{1'b0,1'b0}), + .but_select_s(~{m_start2,m_start1}), + .but_up_s(~{1'b0,m_up}), + .but_down_s(~{1'b0,m_down}), + .but_left_s(~{1'b0,m_left}), + .but_right_s(~{1'b0,m_right}) +); + +assign audio = audio_s; + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_1.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_1.vhd new file mode 100644 index 00000000..3f3f748f --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_1.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_1 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"78",X"A3",X"B5",X"00",X"8C",X"79",X"64",X"00",X"C3",X"EE",X"DD",X"00",X"3C",X"A2",X"4A", + X"00",X"87",X"BA",X"DE",X"00",X"2A",X"AE",X"BB",X"00",X"8C",X"C2",X"B7",X"00",X"AC",X"E2",X"1D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_2.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_2.vhd new file mode 100644 index 00000000..c0b51aff --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_2.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_2 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F5",X"C4",X"D0",X"B1",X"D4",X"90",X"45",X"44",X"00",X"54",X"91",X"94",X"25",X"21",X"65",X"F5", + X"21",X"00",X"25",X"D0",X"B1",X"90",X"D4",X"D4",X"25",X"B1",X"C4",X"90",X"65",X"D4",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_3.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_3.vhd new file mode 100644 index 00000000..a731ff5c --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_10_3.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_3 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"3A",X"3A",X"3A",X"3A",X"28",X"28",X"38",X"38", + X"08",X"08",X"38",X"38",X"20",X"20",X"38",X"38",X"20",X"20",X"38",X"38",X"3E",X"3E",X"3E",X"3E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_decrypt.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_decrypt.vhd new file mode 100644 index 00000000..00f98d21 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/prom_decrypt.vhd @@ -0,0 +1,63 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity prom_decrypt is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(7 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of prom_decrypt is + + + type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07", -- 0x0000 + x"08",x"09",x"0A",x"0B",x"0C",x"0D",x"0E",x"0F", -- 0x0008 + x"10",x"11",x"12",x"13",x"14",x"15",x"16",x"17", -- 0x0010 + x"18",x"19",x"1A",x"1B",x"1C",x"1D",x"1E",x"1F", -- 0x0018 + x"20",x"21",x"22",x"23",x"24",x"25",x"26",x"27", -- 0x0020 + x"28",x"29",x"2A",x"2B",x"2C",x"2D",x"2E",x"2F", -- 0x0028 + x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37", -- 0x0030 + x"38",x"39",x"3A",x"3B",x"3C",x"3D",x"3E",x"3F", -- 0x0038 + x"40",x"41",x"42",x"43",x"44",x"45",x"46",x"47", -- 0x0040 + x"48",x"49",x"4A",x"4B",x"4C",x"4D",x"4E",x"4F", -- 0x0048 + x"50",x"51",x"52",x"53",x"54",x"55",x"56",x"57", -- 0x0050 + x"58",x"59",x"5A",x"5B",x"5C",x"5D",x"5E",x"5F", -- 0x0058 + x"60",x"61",x"62",x"63",x"64",x"65",x"66",x"67", -- 0x0060 + x"68",x"69",x"6A",x"6B",x"6C",x"6D",x"6E",x"6F", -- 0x0068 + x"70",x"71",x"72",x"73",x"74",x"75",x"76",x"77", -- 0x0070 + x"78",x"79",x"7A",x"7B",x"7C",x"7D",x"7E",x"7F", -- 0x0078 + x"80",x"81",x"82",x"83",x"84",x"85",x"86",x"87", -- 0x0080 + x"88",x"89",x"8A",x"8B",x"8C",x"8D",x"8E",x"8F", -- 0x0088 + x"90",x"91",x"92",x"93",x"94",x"95",x"96",x"97", -- 0x0090 + x"98",x"99",x"9A",x"9B",x"9C",x"9D",x"9E",x"9F", -- 0x0098 + x"A0",x"A1",x"A2",x"A3",x"A4",x"A5",x"A6",x"A7", -- 0x00A0 + x"A8",x"A9",x"AA",x"AB",x"AC",x"AD",x"AE",x"AF", -- 0x00A8 + x"B0",x"B1",x"B2",x"B3",x"B4",x"B5",x"B6",x"B7", -- 0x00B0 + x"B8",x"B9",x"BA",x"BB",x"BC",x"BD",x"BE",x"BF", -- 0x00B8 + x"C0",x"C1",x"C2",x"C3",x"C4",x"C5",x"C6",x"C7", -- 0x00C0 + x"C8",x"C9",x"CA",x"CB",x"CC",x"CD",x"CE",x"CF", -- 0x00C8 + x"D0",x"D1",x"D2",x"D3",x"D4",x"D5",x"D6",x"D7", -- 0x00D0 + x"D8",x"D9",x"DA",x"DB",x"DC",x"DD",x"DE",x"DF", -- 0x00D8 + x"E0",x"E1",x"E2",x"E3",x"E4",x"E5",x"E6",x"E7", -- 0x00E0 + x"E8",x"E9",x"EA",x"EB",x"EC",x"ED",x"EE",x"EF", -- 0x00E8 + x"F0",x"F1",x"F2",x"F3",x"F4",x"F5",x"F6",x"F7", -- 0x00F0 + x"F8",x"F9",x"FA",x"FB",x"FC",x"FD",x"FE",x"FF" -- 0x00F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_char_l.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_char_l.vhd new file mode 100644 index 00000000..209a2c92 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_char_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7C",X"C6",X"C6",X"C6",X"C6",X"C6",X"7C",X"00",X"18",X"1C",X"18",X"18",X"18",X"18",X"3C", + X"00",X"7C",X"E6",X"C6",X"30",X"0C",X"C6",X"7E",X"00",X"7C",X"C6",X"C0",X"70",X"C6",X"C6",X"7C", + X"00",X"68",X"68",X"6C",X"64",X"FE",X"60",X"F0",X"00",X"7E",X"02",X"7E",X"C2",X"C0",X"C6",X"7C", + X"00",X"7C",X"C6",X"06",X"7E",X"C6",X"C6",X"7C",X"00",X"FE",X"C2",X"C2",X"60",X"30",X"18",X"18", + X"00",X"7C",X"C6",X"C6",X"7C",X"C6",X"C6",X"7C",X"00",X"7C",X"C6",X"C6",X"FC",X"C0",X"C6",X"7C", + X"00",X"70",X"58",X"C8",X"CC",X"FC",X"C6",X"C6",X"00",X"7E",X"CC",X"CC",X"7C",X"CC",X"CC",X"7E", + X"00",X"78",X"CC",X"06",X"06",X"86",X"CC",X"78",X"00",X"3E",X"6C",X"CC",X"CC",X"CC",X"6C",X"3E", + X"00",X"FE",X"CC",X"0C",X"3C",X"0C",X"CC",X"FE",X"00",X"FE",X"CC",X"0C",X"3C",X"0C",X"0C",X"1E", + X"00",X"78",X"CC",X"06",X"06",X"E6",X"CC",X"78",X"00",X"EE",X"6C",X"6C",X"7C",X"6C",X"6C",X"EE", + X"00",X"3C",X"18",X"18",X"18",X"18",X"18",X"3C",X"00",X"F0",X"60",X"60",X"60",X"60",X"6C",X"38", + X"00",X"9E",X"CC",X"6C",X"3C",X"6C",X"CC",X"DE",X"00",X"1E",X"0C",X"0C",X"0C",X"0C",X"CC",X"FE", + X"00",X"C6",X"EE",X"FE",X"D6",X"D6",X"C6",X"C6",X"00",X"C6",X"CE",X"DE",X"F6",X"E6",X"C6",X"C6", + X"00",X"7C",X"C6",X"C6",X"C6",X"C6",X"C6",X"7C",X"00",X"7E",X"CC",X"CC",X"7C",X"0C",X"0C",X"1E", + X"00",X"38",X"6C",X"C6",X"C6",X"D6",X"6C",X"D8",X"00",X"7E",X"CC",X"CC",X"7C",X"6C",X"CC",X"DE", + X"00",X"7C",X"8E",X"1C",X"78",X"F0",X"E2",X"7C",X"00",X"7E",X"5A",X"18",X"18",X"18",X"18",X"3C", + X"00",X"DE",X"8C",X"8C",X"8C",X"8C",X"8C",X"78",X"00",X"DE",X"8C",X"8C",X"8C",X"58",X"58",X"30", + X"00",X"B6",X"B6",X"B6",X"B6",X"FE",X"6C",X"28",X"00",X"C6",X"6E",X"3C",X"38",X"78",X"EC",X"C6", + X"00",X"E6",X"6C",X"78",X"30",X"30",X"18",X"1C",X"00",X"FE",X"E6",X"70",X"38",X"1C",X"CE",X"FE", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00", + X"00",X"00",X"10",X"00",X"00",X"10",X"00",X"00",X"00",X"0C",X"12",X"14",X"08",X"14",X"22",X"7C", + X"30",X"30",X"38",X"38",X"18",X"08",X"00",X"04",X"38",X"44",X"44",X"20",X"10",X"10",X"00",X"10", + X"00",X"20",X"10",X"08",X"08",X"08",X"10",X"20",X"00",X"08",X"10",X"20",X"20",X"20",X"10",X"08", + X"00",X"10",X"10",X"10",X"FE",X"10",X"10",X"10",X"00",X"00",X"00",X"00",X"7E",X"00",X"00",X"00", + X"00",X"00",X"7E",X"00",X"00",X"7E",X"00",X"00",X"00",X"44",X"EE",X"EE",X"FE",X"7C",X"38",X"10", + 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Hardware/CosmicAvenger_MiST/rtl/ROM/rom_cpu1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"00",X"6C",X"C3",X"1E",X"01",X"FF",X"FF",X"5E",X"23",X"56",X"23",X"EB",X"C9",X"FF",X"FF", + X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"21",X"01",X"90",X"C3",X"71",X"05",X"FF",X"FF",X"F5",X"C5",X"D5",X"E5",X"C3",X"7C",X"00",X"C1", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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100644 index 00000000..d6ac057a --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_cpu2.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu2 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"2A",X"04",X"4B",X"03",X"2C",X"04",X"4D",X"03",X"2E",X"04",X"2E",X"07",X"2D",X"07",X"2C",X"06", + X"2A",X"02",X"48",X"07",X"29",X"06",X"27",X"00",X"28",X"01",X"49",X"03",X"2A",X"04",X"2B",X"01", + X"2B",X"00",X"2B",X"06",X"2A",X"06",X"29",X"06",X"28",X"02",X"27",X"00",X"27",X"02",X"00",X"38", + X"00",X"38",X"12",X"03",X"12",X"04",X"12",X"02",X"13",X"02",X"14",X"05",X"14",X"06",X"15",X"02", + X"16",X"02",X"17",X"02",X"17",X"01",X"16",X"01",X"15",X"01",X"14",X"01",X"14",X"02",X"15",X"02", + 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100644 index 00000000..1d8e63da --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_cpu3.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu3 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"60",X"FD",X"77",X"07",X"FD",X"36",X"08",X"00",X"DD",X"36",X"08",X"08",X"1E",X"09",X"CD",X"FB", + X"06",X"C9",X"CD",X"7B",X"0B",X"FD",X"7E",X"14",X"E6",X"60",X"FE",X"40",X"CC",X"85",X"0B",X"DD", + X"7E",X"02",X"FE",X"FD",X"38",X"23",X"C9",X"DD",X"7E",X"07",X"FE",X"0C",X"30",X"1B",X"A7",X"20", + X"10",X"11",X"95",X"40",X"CD",X"21",X"07",X"1E",X"14",X"CD",X"0E",X"07",X"1E",X"02",X"CD",X"FB", + X"06",X"CD",X"7B",X"0B",X"38",X"03",X"C3",X"C7",X"3D",X"DD",X"36",X"00",X"00",X"21",X"F8",X"63", + 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mode 100644 index 00000000..f825258c --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_sprite_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"80",X"2A",X"A0",X"1A",X"A9",X"D5",X"55", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"55",X"40",X"55",X"55", + X"D5",X"7F",X"05",X"FF",X"05",X"00",X"14",X"00",X"55",X"50",X"00",X"00",X"00",X"00",X"00",X"00", + X"F5",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"81",X"0A",X"05",X"28",X"15",X"2A",X"AA", + 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X"A5",X"55",X"A9",X"55",X"6A",X"55",X"5A",X"95",X"56",X"A5",X"5A",X"A9",X"55",X"55",X"55",X"55"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_sprite_u.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_sprite_u.vhd new file mode 100644 index 00000000..5fc0eddb --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ROM/rom_sprite_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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X"0A",X"BA",X"0A",X"BA",X"0A",X"BA",X"02",X"AA",X"02",X"AB",X"00",X"A8",X"00",X"A0",X"00",X"00", + X"CA",X"C2",X"EA",X"C2",X"EA",X"C2",X"2A",X"C2",X"2A",X"CA",X"AA",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"0A",X"80",X"C2",X"AA",X"C2",X"AA",X"C2",X"AF",X"C2",X"AC",X"BA",X"AA",X"B2",X"AA", + X"00",X"00",X"00",X"00",X"A2",X"A8",X"AC",X"AF",X"EC",X"AC",X"0C",X"AC",X"B0",X"AF",X"C0",X"AE", + X"B2",X"AC",X"B2",X"AF",X"B2",X"AA",X"B2",X"AA",X"8A",X"A8",X"00",X"00",X"00",X"00",X"00",X"00", + X"0C",X"AE",X"EC",X"AA",X"AC",X"AB",X"A2",X"AA",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"2A",X"82",X"EA",X"0A",X"EA",X"0A",X"AA",X"EA",X"BA",X"EA",X"BA",X"EA", + X"00",X"00",X"00",X"00",X"AA",X"0A",X"BA",X"BA",X"3A",X"BA",X"3A",X"BA",X"EA",X"BA",X"00",X"3A", + X"BA",X"EA",X"3A",X"EA",X"FA",X"3A",X"2A",X"8A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"3F",X"3A",X"FA",X"BA",X"BA",X"BA",X"AA",X"BA",X"AA",X"0A",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"2A",X"A2",X"AA",X"AE",X"AB",X"AE",X"BF",X"8E",X"83",X"0E",X"AA",X"0E",X"AA",X"0E", + X"00",X"AA",X"A3",X"A8",X"A2",X"A0",X"AE",X"A0",X"AE",X"80",X"AA",X"80",X"AA",X"00",X"AA",X"A8", + X"8E",X"0E",X"80",X"CE",X"B0",X"EE",X"AB",X"EE",X"AA",X"AE",X"2A",X"A2",X"00",X"00",X"00",X"00", + X"A0",X"EA",X"A0",X"EA",X"A3",X"EA",X"AF",X"AA",X"AA",X"A8",X"AA",X"A8",X"0A",X"80",X"00",X"00", + X"00",X"00",X"01",X"31",X"10",X"5A",X"04",X"6F",X"05",X"2E",X"01",X"79",X"54",X"A9",X"07",X"65", + X"43",X"00",X"14",X"C4",X"94",X"50",X"E1",X"9C",X"9E",X"80",X"DA",X"E4",X"F6",X"95",X"5A",X"E0", + X"03",X"6A",X"0C",X"AB",X"30",X"59",X"01",X"45",X"0C",X"54",X"00",X"10",X"00",X"C0",X"00",X"00", + X"DA",X"A7",X"AB",X"10",X"AE",X"54",X"51",X"40",X"90",X"50",X"44",X"24",X"41",X"00",X"40",X"00", + X"00",X"30",X"02",X"04",X"1C",X"68",X"C5",X"85",X"06",X"97",X"10",X"AF",X"05",X"AA",X"2B",X"FE", + X"8C",X"00",X"A3",X"20",X"6C",X"80",X"BC",X"78",X"F9",X"61",X"AA",X"99",X"A6",X"8C",X"61",X"F0", + X"0F",X"8A",X"30",X"9F",X"0A",X"53",X"11",X"0B",X"40",X"36",X"00",X"38",X"00",X"C0",X"03",X"00", + X"9F",X"87",X"A5",X"F0",X"E5",X"8C",X"4E",X"42",X"53",X"90",X"00",X"84",X"91",X"00",X"00",X"30", + X"00",X"80",X"00",X"E0",X"04",X"08",X"01",X"C1",X"C0",X"74",X"30",X"07",X"03",X"31",X"00",X"87", + X"30",X"0C",X"8C",X"80",X"12",X"10",X"58",X"40",X"61",X"00",X"44",X"00",X"1D",X"50",X"51",X"03", + X"20",X"D1",X"08",X"14",X"00",X"50",X"20",X"42",X"03",X"08",X"0C",X"00",X"00",X"20",X"80",X"00", + X"D4",X"80",X"75",X"0E",X"12",X"40",X"10",X"10",X"08",X"00",X"00",X"30",X"10",X"0C",X"00",X"00", + X"00",X"02",X"02",X"08",X"2B",X"EA",X"AC",X"38",X"BF",X"D3",X"AD",X"7F",X"95",X"CF",X"57",X"FB", + X"00",X"00",X"00",X"00",X"30",X"00",X"F0",X"00",X"E4",X"00",X"90",X"00",X"C3",X"00",X"C0",X"00", + X"5A",X"A1",X"6A",X"97",X"9A",X"7E",X"A9",X"FF",X"6A",X"F4",X"5A",X"BD",X"A6",X"FF",X"EA",X"8F", + X"7C",X"00",X"FF",X"C0",X"B0",X"30",X"E0",X"00",X"08",X"0C",X"00",X"C0",X"C0",X"00",X"FC",X"00", + X"00",X"00",X"00",X"08",X"00",X"20",X"00",X"33",X"01",X"01",X"04",X"04",X"00",X"40",X"00",X"00", + X"0F",X"EA",X"35",X"E8",X"D3",X"EA",X"0F",X"AE",X"2E",X"BE",X"3F",X"FF",X"BC",X"F7",X"F0",X"1D", + X"0C",X"05",X"30",X"04",X"00",X"C0",X"00",X"82",X"02",X"00",X"00",X"03",X"00",X"08",X"00",X"00", + X"CB",X"7C",X"43",X"F0",X"8F",X"14",X"0F",X"00",X"3C",X"12",X"00",X"10",X"00",X"40",X"04",X"00", + X"8F",X"D0",X"DF",X"F4",X"F7",X"39",X"FD",X"82",X"B7",X"70",X"B1",X"FC",X"FC",X"71",X"CE",X"1C", + X"00",X"00",X"C4",X"00",X"40",X"00",X"00",X"80",X"A0",X"00",X"0C",X"00",X"03",X"00",X"20",X"10", + X"F0",X"35",X"FC",X"BD",X"34",X"30",X"3C",X"0C",X"0C",X"00",X"83",X"20",X"80",X"08",X"20",X"02", + X"00",X"04",X"02",X"00",X"80",X"80",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FE",X"EF",X"6F",X"EF",X"67",X"FE",X"66",X"FF",X"66",X"6E",X"26",X"6F",X"26",X"6E",X"26",X"6F", + X"FB",X"BF",X"FB",X"F9",X"BF",X"D9",X"FF",X"99",X"B9",X"99",X"F9",X"99",X"B9",X"98",X"F9",X"98", + X"26",X"6F",X"06",X"55",X"01",X"55",X"03",X"FF",X"02",X"AA",X"00",X"FF",X"00",X"0A",X"00",X"03", + X"F9",X"98",X"55",X"90",X"55",X"40",X"FF",X"C0",X"AA",X"80",X"FF",X"00",X"A0",X"00",X"C0",X"00", + X"55",X"55",X"55",X"55",X"6A",X"A5",X"5A",X"95",X"56",X"A5",X"55",X"A9",X"55",X"6A",X"55",X"5A", + X"55",X"55",X"55",X"55",X"5A",X"A9",X"56",X"A5",X"5A",X"95",X"6A",X"55",X"A9",X"55",X"A5",X"55", + X"55",X"5A",X"55",X"6A",X"55",X"A9",X"56",X"A5",X"5A",X"95",X"6A",X"A5",X"55",X"55",X"55",X"55", + X"A5",X"55",X"A9",X"55",X"6A",X"55",X"5A",X"95",X"56",X"A5",X"5A",X"A9",X"55",X"55",X"55",X"55"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/build_id.tcl b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/build_id.v b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/build_id.v new file mode 100644 index 00000000..75d3f865 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "122617" diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c3e13c5c --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1094 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..7e8a9995 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,370 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..7d407fb8 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2027 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..6904b66b --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..998033ef --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd new file mode 100644 index 00000000..33d61068 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/cpu/T80a.vhd @@ -0,0 +1,280 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80a is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLK_EN_SYS : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80a; + +architecture rtl of T80a is + + signal CEN : std_logic; + signal Reset_s : std_logic; + signal IntCycle_n : std_logic; + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal MREQ : std_logic; + signal MReq_Inhibit : std_logic; + signal Req_Inhibit : std_logic; + signal RD : std_logic; + signal MREQ_n_i : std_logic; + signal IORQ_n_i : std_logic; + signal RD_n_i : std_logic; + signal WR_n_i : std_logic; + signal RFSH_n_i : std_logic; + signal BUSAK_n_i : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal DO_Reg : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal Wait_s : std_logic; + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + -- clock enable supplied from clocking system + CEN <= CLK_EN_SYS; + + BUSAK_n <= BUSAK_n_i; + MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); + RD_n_i <= not RD or Req_Inhibit; + + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DO <= DO_Reg; + +-- process (RESET_n, CLK_n) +-- begin +-- if RESET_n = '0' then +-- Reset_s <= '0'; +-- elsif CLK_n'event and CLK_n = '1' then +-- Reset_s <= '1'; +-- end if; +-- end process; + -- T80 reset input has already proper characteristics: + -- * asynchronous assertion + -- * deassertion synchronous to CLK_n (main_clk) + Reset_s <= RESET_n; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, + DInst => DI, + DI => DI_Reg, + DO => DO_Reg, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + if CEN = '1' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then + DI_Reg <= to_x01(DI); + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + WR_n_i <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + WR_n_i <= '1'; + if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! + WR_n_i <= not Write; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + Req_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + Req_Inhibit <= '1'; + else + Req_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + MReq_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + MReq_Inhibit <= '1'; + else + MReq_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process(Reset_s,CLK_n) + begin + if Reset_s = '0' then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + + if MCycle = "001" then + if TState = "001" then + RD <= IntCycle_n; + MREQ <= IntCycle_n; + IORQ_n_i <= IntCycle_n; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '1'; + end if; + if TState = "100" then + MREQ <= '0'; + end if; + else + if TState = "001" and NoRead = '0' then + RD <= not Write; + IORQ_n_i <= not IORQ; + MREQ <= not IORQ; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + end if; + end if; + + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/dac.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/dac.vhd new file mode 100644 index 00000000..75d941cb --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 6 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/dpram.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/hq2x.sv b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/keyboard.v b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd new file mode 100644 index 00000000..a1a186fe --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug.vhd @@ -0,0 +1,243 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- Toplevel port for Papilio Plus board. +-- +------------------------------------------------------------------------------- +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library ieee; + use ieee.numeric_std.all; + +use work.ladybug_dip_pack.all; + +entity ladybugt is +port ( + -- Global Interface ------------------------------------------------------- + CLK_IN : in std_logic; -- 20MHz + I_RESET : in std_logic; + + -- VGA Interface ---------------------------------------------------------- + O_VIDEO_R : out std_logic_vector( 1 downto 0); + O_VIDEO_G : out std_logic_vector( 1 downto 0); + O_VIDEO_B : out std_logic_vector( 1 downto 0); + O_VSYNC : out std_logic; + O_HSYNC : out std_logic; + O_VBLANK : out std_logic; + O_HBLANK : out std_logic; + O_PIXCE : out std_logic; + + -- Audio Interface -------------------------------------------------------- + O_AUDIO : out signed(7 downto 0); + + but_coin_s : in std_logic_vector( 1 downto 0); + but_fire_s : in std_logic_vector( 1 downto 0); + but_bomb_s : in std_logic_vector( 1 downto 0); + but_tilt_s : in std_logic_vector( 1 downto 0); + but_select_s : in std_logic_vector( 1 downto 0); + but_up_s : in std_logic_vector( 1 downto 0); + but_down_s : in std_logic_vector( 1 downto 0); + but_left_s : in std_logic_vector( 1 downto 0); + but_right_s : in std_logic_vector( 1 downto 0) +); +end ladybugt; + +architecture struct of ladybugt is + + signal + ps2_codeready, + clk_20mhz_s, + clk_en_5mhz_s, + ext_res_n_s, + ext_res_s, + audio_s, + vid_hsync, + vid_vsync, + vga_hsync, + vid_comp_sync_n, + vga_vsync : std_logic; + + signal rom_cpu_a_s : std_logic_vector(14 downto 0); + signal rom_cpu_d_s : std_logic_vector( 7 downto 0); + signal rom_cpu_d1 : std_logic_vector( 7 downto 0); + signal rom_cpu_d2 : std_logic_vector( 7 downto 0); + signal rom_cpu_d3 : std_logic_vector( 7 downto 0); + signal rom_cpu_d4 : std_logic_vector( 7 downto 0); + signal rom_cpu_d5 : std_logic_vector( 7 downto 0); + signal rom_cpu_d6 : std_logic_vector( 7 downto 0); + + signal rom_char_a_s : std_logic_vector(11 downto 0); + signal rom_char_d_s : std_logic_vector(15 downto 0); + + signal rom_sprite_a_s : std_logic_vector(11 downto 0); + signal rom_sprite_d_s : std_logic_vector(15 downto 0); + + signal + dac_audio_s, + dip_block_1_s, + dip_block_2_s : std_logic_vector( 7 downto 0) := (others => '0'); + + signal ps2_scancode : std_logic_vector( 9 downto 0) := (others => '0'); + + signal + vid_rgb, + vga_rgb : std_logic_vector(15 downto 0) := (others => '0'); + + signal but_chute_s : std_logic_vector( 1 downto 0) := (others=>'0'); + +begin + + O_PIXCE <= clk_en_5mhz_s; + + but_chute_s <= not but_coin_s(1) & not but_coin_s(0); + + ----------------------------------------------------------------------------- + -- inputs assignments + ----------------------------------------------------------------------------- + ext_res_s <= I_RESET; + ext_res_n_s <= not ext_res_s; + clk_20mhz_s <= CLK_IN; + + ----------------------------------------------------------------------------- + -- Ladybug Machine + ----------------------------------------------------------------------------- + machine_b : entity work.ladybug_machine + port map ( + ext_res_n_i => ext_res_n_s, + clk_20mhz_i => clk_20mhz_s, + clk_en_5mhz_o => clk_en_5mhz_s, + tilt_n_i => but_tilt_s(0), + player_select_n_i => but_select_s, + player_fire_n_i => but_fire_s, + player_up_n_i => but_up_s, + player_right_n_i => but_right_s, + player_down_n_i => but_down_s, + player_left_n_i => but_left_s, + player_bomb_n_i => but_bomb_s, + right_chute_i => but_chute_s(0), + left_chute_i => but_chute_s(1), + dip_block_1_i => dip_block_1_s, + dip_block_2_i => dip_block_2_s, + rgb_r_o => O_VIDEO_R, + rgb_g_o => O_VIDEO_G, + rgb_b_o => O_VIDEO_B, + hsync_n_o => O_HSYNC, + vsync_n_o => O_VSYNC, + vblank_o => O_VBLANK, + hblank_o => O_HBLANK, + audio_o => O_AUDIO, + rom_cpu_a_o => rom_cpu_a_s, + rom_cpu_d_i => rom_cpu_d_s, + rom_char_a_o => rom_char_a_s, + rom_char_d_i => rom_char_d_s, + rom_sprite_a_o => rom_sprite_a_s, + rom_sprite_d_i => rom_sprite_d_s + ); + + ----------------------------------------------------------------------------- + -- Building the DIP Switches - see file ladybug_dip_pack.vhd + ----------------------------------------------------------------------------- +-- dip_block_1_s <= lb_dip_block_1_c; -- Lady Bug +-- dip_block_1_s <= do_dip_block_1_c; -- Dorodon + dip_block_1_s <= ca_dip_block_1_c; -- Cosmic Avenger + dip_block_2_s <= price_dip_block_2_c; -- Common for all games (coins per game pricing) + + ----------------------------------------------------------------------------- + -- Game ROMs + ----------------------------------------------------------------------------- + inst_rom_spritel : entity work.rom_sprite_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s( 7 downto 0) + ); + + inst_rom_spriteu : entity work.rom_sprite_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s(15 downto 8) + ); + + inst_rom_charl : entity work.rom_char_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s( 7 downto 0) + ); + + inst_rom_charu : entity work.rom_char_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s(15 downto 8) + ); + + inst_rom_cpu1 : entity work.rom_cpu1 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d1 + ); + + inst_rom_cpu2 : entity work.rom_cpu2 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d2 + ); + + inst_rom_cpu3 : entity work.rom_cpu3 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d3 + ); + + ----------------------------------------------------------------------------- + -- Program ROMs data mux + ----------------------------------------------------------------------------- + rom_cpu_d_s <= + rom_cpu_d1 when rom_cpu_a_s(14 downto 13) = "00" else + rom_cpu_d2 when rom_cpu_a_s(14 downto 13) = "01" else + rom_cpu_d3 when rom_cpu_a_s(14 downto 13) = "10" else + (others=>'0'); + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_addr_dec.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_addr_dec.vhd new file mode 100644 index 00000000..6d857f6c --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_addr_dec.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_addr_dec.vhd,v 1.10 2005/12/10 14:51:46 arnim Exp $ +-- +-- Address decoder of the CPU Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_addr_dec is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + a_i : in std_logic_vector(15 downto 12); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + mreq_n_i : in std_logic; + rfsh_n_i : in std_logic; + cs_n_o : out std_logic_vector(15 downto 0); + ram_cpu_cs_n_o : out std_logic + ); + +end ladybug_addr_dec; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_addr_dec is + +begin + + ----------------------------------------------------------------------------- + -- Process adec + -- + -- Purpose: + -- Decode the CPU address and generate one-hot chip select signals. + -- Each chip select enables a 4 KByte address segment. + -- + -- The chip select outputs are registered with the 20 MHz clock to + -- break potentially long combinational paths here. + -- + adec: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + cs_n_o <= (others => '1'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- default assignment + cs_n_o <= (others => '1'); + + if a_i(15) = '0' then + if rd_n_i = '0' or wr_n_i = '0' then + cs_n_o(to_integer(unsigned( '0' & a_i(14 downto 12) ))) <= '0'; + end if; + + else + if mreq_n_i = '0' and rfsh_n_i = '1' then + cs_n_o(to_integer(unsigned( '1' & a_i(14 downto 12) ))) <= '0'; + end if; + + end if; + + end if; + end process adec; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cs_ext_ram + -- + -- Purpose: + -- Builds the combinational chip select signal for the external CPU RAM. + -- + cs_ext_ram: process (a_i, + rd_n_i, wr_n_i) + begin + if (rd_n_i = '0' or wr_n_i = '0') and + a_i(15 downto 12) = "0110" then + ram_cpu_cs_n_o <= '0'; + else + ram_cpu_cs_n_o <= '1'; + end if; + end process cs_ext_ram; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_char.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_char.vhd new file mode 100644 index 00000000..1ca149f3 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_char.vhd @@ -0,0 +1,740 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char.vhd,v 1.18 2005/10/10 22:02:14 arnim Exp $ +-- +-- Character Video Module of Lady Bug Machine. +-- +-- This unit contains most of the logic found on schematic page three. +-- Excluded parts are: +-- * the 10 MHz and 5 MHz clock generation +-- moved into separate module on toplevel of Lady Bug machine +-- * the video timing circuitry +-- moved into separate module on toplevel of video unit +-- * the video MUX and RGB conversion unit +-- moved into separate module at toplevel of video unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity ladybug_char is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_char_o : out std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + ha_t_rise_i : in std_logic; + hx_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + hbl_i : in std_logic; + blank_flont_i : in std_logic; + blank_o : out std_logic; + crg_o : out std_logic_vector( 5 downto 1); + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_char; + +architecture rtl of ladybug_char is + + signal flip_screen_q : std_logic; + + signal h0_s, + h1_s, + h2_s : std_logic; + signal h_flip_s, + h_t_flip_s : std_logic_vector(3 downto 0); + signal v_flip_s, + v_t_flip_s : std_logic_vector(3 downto 0); + + signal h_ctrl_d_s, + h_ctrl_s, + h_ctrl_n_s, + h_ctrl_d_out_s, + h_ctrl_d_n_out_s, + h_ctrl_rise_s, + h_ctrl_n_rise_s : std_logic_vector(4 downto 1); + + signal hx_ctrl_q, + hx_ctrl_s, + hx_ctrl_n_rise_s : std_logic; + signal hx_ctrl_clear_q : std_logic; + + signal b1_ff_q, + b1_ff_s, + b1_ff_n_rise_s : std_logic; + + signal wait_q : std_logic; + signal wait_clear_q : std_logic; + + signal cgs_q, + cgs_s, + cgs_rise_s : std_logic; + + signal ram_addr_s : std_logic_vector(9 downto 0); + signal select_a_s : std_logic; + + signal char_ram_cs_n_s, + char_ram_we_n_s : std_logic; + signal col_ram_cs_n_s, + col_ram_we_n_s : std_logic; + signal d_from_char_ram_s : std_logic_vector(7 downto 0); + signal d_from_col_ram_s : std_logic_vector(3 downto 0); + + signal s_q : std_logic_vector( 7 downto 0); + signal d_char_ram_q : std_logic_vector( 7 downto 0); + signal d_col_ram_q : std_logic_vector( 3 downto 0); + + signal d_char_rom_q : std_logic_vector(15 downto 0); + signal crg1_s, + crg2_s, + crg3_q, + crg4_q, + crg5_q : std_logic; + + signal hbl_q,hbl_d : std_logic; + + signal hcnt : integer; + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Process flip + -- + -- Purpose: + -- Implement the flip_screen flag. + -- + flip: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + -- Actually, this asynchronous reset of the ls259 is not 100% + -- equivalent to the real behavior of this circuit. However, + -- the flip_screen latch is modelled like this for the sake of + -- simplicity. It's sufficient for the purpose here. + flip_screen_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if a_i(2 downto 0) = "000" and cs10_n_i = '0' then + flip_screen_q <= d_from_cpu_i(0); + end if; + + end if; + end process flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process h_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + h_flip: process (flip_screen_q, + h_i, h_t_i, + s_q) + variable a_v, b_v, + sum_v : unsigned(8 downto 0); + begin + -- calculate sum + a_v := '0' & unsigned(s_q); + b_v := '0' & unsigned(h_t_i) & unsigned(h_i); + sum_v := a_v + b_v; + + -- h0,1,2 are taken from directly from sum + h0_s <= sum_v(0); + h1_s <= sum_v(1); + h2_s <= sum_v(2); + + -- now flip + for idx in 3 downto 0 loop + h_flip_s(idx) <= flip_screen_q xor sum_v(idx); + h_t_flip_s(idx) <= flip_screen_q xor sum_v(idx + 4); + end loop; + end process h_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process v_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + v_flip: process (flip_screen_q, + v_i, v_t_i) + begin + for idx in 3 downto 0 loop + v_flip_s(idx) <= flip_screen_q xor v_i(idx); + v_t_flip_s(idx) <= flip_screen_q xor v_t_i(idx); + end loop; + end process v_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The Horizontal Control Signals + -- Detailed purpose/meaning is unknown. + ----------------------------------------------------------------------------- + h_ctrl_d_s(1) <= not (not h2_s and (h1_s xor h0_s)); + h_ctrl_d_s(2) <= hx_i; + h_ctrl_d_s(3) <= not ((h1_s xor h0_s) or (not h2_s xor h1_s)); + h_ctrl_d_s(4) <= '0'; + h_ctrl_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + por_n_i => por_n_i, + cl_n_i => vdd_s, + d_i => h_ctrl_d_s, + q_o => h_ctrl_s, + q_n_o => h_ctrl_n_s, + d_o => h_ctrl_d_out_s, + d_n_o => h_ctrl_d_n_out_s + ); + h_ctrl_rise_s <= not h_ctrl_s and h_ctrl_d_out_s; + h_ctrl_n_rise_s <= h_ctrl_s and not h_ctrl_d_n_out_s; + + + ----------------------------------------------------------------------------- + -- Process ctrl_seq + -- + -- Purpose: + -- Implemente the various sequential elements for horizontal control. + -- + ctrl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_ctrl_q <= '0'; + hx_ctrl_clear_q <= '0'; + b1_ff_q <= '0'; + wait_q <= '0'; + wait_clear_q <= '0'; + cgs_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- the HX control flip-flop + hx_ctrl_q <= hx_ctrl_s; + + -- the clear counterpart of hx_ctrl_q + if h_ctrl_s(2) = '0' then + -- pseudo-asynchronous clear + hx_ctrl_clear_q <= '0'; + elsif hx_ctrl_n_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + hx_ctrl_clear_q <= '1'; + end if; + + -- the mysterious B1 flip-flop + b1_ff_q <= b1_ff_s; + + -- the CGS rising edge indicator support flip-flops + cgs_q <= cgs_s; + + -- the WAIT flip-flop + if wait_clear_q = '1' then + -- pseudo-asynchronous clear + wait_q <= '0'; + elsif cgs_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + wait_q <= '1'; + end if; + + -- the clear counterpart of wait_q + if clk_en_4mhz_i = '1' then + wait_clear_q <= wait_q and (h_ctrl_s(3) and (b1_ff_q or hx_ctrl_q)); + end if; + + end if; + end process ctrl_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ctrl_comp + -- + -- Purpose: + -- Implements the combination logic for the horizontal control + -- elements. + -- + ctrl_comp: process (h_ctrl_rise_s, + hx_i, hx_ctrl_q, + hx_ctrl_clear_q, + h_ctrl_n_rise_s, + b1_ff_q, + cgs_q, cs13_n_i) + begin + -- default assignments + hx_ctrl_s <= hx_ctrl_q; + hx_ctrl_n_rise_s <= '0'; + b1_ff_s <= b1_ff_q; + b1_ff_n_rise_s <= '0'; + cgs_s <= cgs_q; + cgs_rise_s <= '0'; + + -- the HX control flip-flop ----------------------------------------------- + if hx_ctrl_clear_q = '1' then + -- pseudo-asynchronous clear + hx_ctrl_s <= '0'; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + elsif h_ctrl_rise_s(1) = '1' then + -- rising edge indicator acts as clock enable instead of clock + if hx_i = '1' then + -- toggle FF + hx_ctrl_s <= not hx_ctrl_q; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + end if; + end if; + + -- the mysterious B1 flip-flop -------------------------------------------- + if hx_ctrl_q = '1' then + -- pseudo-asynchronous clear + b1_ff_s <= '0'; + + if (not b1_ff_q) = '0' then + -- detct rising edge of inverted ouput + b1_ff_n_rise_s <= '1'; + end if; + elsif h_ctrl_n_rise_s(3) = '1' then + -- rising edge indicator acts as clock enable instead of clock + b1_ff_s <= '1'; + end if; + + -- the CGS rising edge indicator support flip-flop ------------------------ + cgs_s <= not cs13_n_i; + cgs_rise_s <= not cgs_q and not cs13_n_i; + + end process ctrl_comp; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_addr + -- + -- Purpose: + -- Multiplexes the CPU address bus and the h+v timing control signals to + -- form the RAM address bus. + -- + ram_addr: process (h_flip_s, h_t_flip_s, + v_flip_s, v_t_flip_s, + a_i, + h_ctrl_s, h_ctrl_n_s, + hx_ctrl_q, + b1_ff_q) + variable a_v, b_v, g_n_v : std_logic; + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + ram_addr_s <= (others => '0'); + + -- logic that drives A input of IC L4 and K4 + a_v := not (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + -- logic that drives B input of IC L4 and K4 + b_v := hx_ctrl_q; + -- logic that drives /G input of IC J4 + g_n_v := hx_ctrl_q and (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + + -- IC L4 and K4: Dual 4:1 Multiplexer ------------------------------------- + vec_v := b_v & a_v; + case vec_v is + when "00" => + ram_addr_s(0) <= h_flip_s (3); + ram_addr_s(1) <= h_t_flip_s(0); + -- + ram_addr_s(2) <= h_t_flip_s(1); + ram_addr_s(3) <= h_t_flip_s(2); + when "01" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when "10" => + ram_addr_s(0) <= v_t_flip_s(1); + ram_addr_s(1) <= v_t_flip_s(2); + -- + ram_addr_s(2) <= v_t_flip_s(3); + ram_addr_s(3) <= '0'; + when "11" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when others => + null; + end case; + + -- IC J4 and H4: Quad 2:1 Multiplexer ------------------------------------- + case a_v is + when '0' => + ram_addr_s(4) <= h_t_flip_s(3) and not g_n_v; + ram_addr_s(7) <= v_t_flip_s(1) and not g_n_v; + ram_addr_s(8) <= v_t_flip_s(2) and not g_n_v; + ram_addr_s(9) <= v_t_flip_s(3) and not g_n_v; + -- + ram_addr_s(5) <= v_flip_s (3); + ram_addr_s(6) <= v_t_flip_s(0); + when '1' => + ram_addr_s(4) <= a_i (4) and not g_n_v; + ram_addr_s(7) <= a_i (7) and not g_n_v; + ram_addr_s(8) <= a_i (8) and not g_n_v; + ram_addr_s(9) <= a_i (9) and not g_n_v; + -- + ram_addr_s(5) <= a_i (5); + ram_addr_s(6) <= a_i (6); + when others => + null; + end case; + + select_a_s <= a_v; + + end process ram_addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_ctrl + -- + -- Purpose: + -- Generate the control signals for the character and color RAMs. + -- This comprises: + -- * reading RAMs while the beam sweeps the screen + -- * reading RAMs to the CPU + -- * writing RAMs from the CPU + -- + ram_ctrl: process (cs13_n_i, + wait_q, + select_a_s, + a_i, + wr_n_i, rd_n_i, + d_from_char_ram_s, d_from_col_ram_s, + clk_en_4mhz_i) + variable cpu_read_char_ram_v : boolean; + variable cpu_write_char_ram_v : boolean; + variable cpu_read_col_ram_v : boolean; + variable cpu_write_col_ram_v : boolean; + variable vec_v : std_logic_vector(2 downto 0); + begin + -- default assignments + char_ram_cs_n_s <= '1'; + char_ram_we_n_s <= '1'; + col_ram_cs_n_s <= '1'; + col_ram_we_n_s <= '1'; + d_from_char_o <= (others => '1'); + cpu_read_char_ram_v := false; + cpu_write_char_ram_v := false; + cpu_read_col_ram_v := false; + cpu_write_col_ram_v := false; + + -- detect and decode CPU access + if clk_en_4mhz_i = '1' and -- operate RAMs with CPU clock + (not cs13_n_i and select_a_s and not wait_q) = '1' then + vec_v := a_i(10) & rd_n_i & wr_n_i; + case vec_v is + when "001" => + cpu_read_char_ram_v := true; + when "010" => + cpu_write_char_ram_v := true; + when "101" => + cpu_read_col_ram_v := true; + when "110" => + cpu_write_col_ram_v := true; + when others => + null; + end case; + end if; + + -- now we are prepared to generate the /CS and /WE signals for the RAMs + if select_a_s = '0' or + cpu_read_char_ram_v or cpu_write_char_ram_v then + char_ram_cs_n_s <= '0'; + end if; + if select_a_s = '0' or + cpu_read_col_ram_v or cpu_write_col_ram_v then + col_ram_cs_n_s <= '0'; + end if; + if cpu_write_char_ram_v then + char_ram_we_n_s <= '0'; + end if; + if cpu_write_col_ram_v then + col_ram_we_n_s <= '0'; + end if; + + -- and we can multiplex the data bus towards the CPU + if cpu_read_char_ram_v then + d_from_char_o <= d_from_char_ram_s; + elsif cpu_read_col_ram_v then + d_from_char_o(3 downto 0) <= d_from_col_ram_s; + end if; + + end process ram_ctrl; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The character RAM + ----------------------------------------------------------------------------- + char_ram_b : entity work.ladybug_char_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => char_ram_cs_n_s, + we_n_i => char_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => d_from_char_ram_s + ); + ----------------------------------------------------------------------------- + -- The color RAM + ----------------------------------------------------------------------------- + col_ram_b : entity work.ladybug_char_col_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => col_ram_cs_n_s, + we_n_i => col_ram_we_n_s, + d_i => d_from_cpu_i(3 downto 0), + d_o => d_from_col_ram_s + ); + + + ----------------------------------------------------------------------------- + -- Process ram_d_seq + -- + -- Purpose: + -- Implements three latch banks that save the output of the character + -- and color RAMs. + -- + ram_d_seq: process (clk_20mhz_i, por_n_i) + variable complex_rising_edge_v : boolean; + begin + if por_n_i = '0' then + s_q <= (others => '0'); + d_char_ram_q <= (others => '0'); + d_col_ram_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- latch data from the character RAM to form input for h_flip ----------- + if hx_ctrl_n_rise_s = '1' then + s_q <= d_from_char_ram_s; + end if; + + -- latch data from the character RAM for ROM address generation --------- + -- there are three sources for a rising edge: + -- 1) falling edge of h_ctrl_n_s(1) + -- => equivalen to rising edge of h_ctrl_s(1) + -- 2) rising edge of hx_ctrl_n_q + -- 3) rising edge of b1_ff_n + -- For each source, the two have to be in a defined state to let + -- the edge propage to the latches. + complex_rising_edge_v := ((h_ctrl_rise_s(1) and + (b1_ff_q or hx_ctrl_q)) or + (hx_ctrl_n_rise_s and + (not b1_ff_q and not h_ctrl_n_s(1))) or + (b1_ff_n_rise_s and + (not hx_ctrl_q and not h_ctrl_s(1)))) = '1'; + if complex_rising_edge_v then + d_char_ram_q <= d_from_char_ram_s; + d_col_ram_q <= d_from_col_ram_s; + end if; + + end if; + end process ram_d_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process latch_rom_d + -- + -- Purpose: + -- Latch the output of the character ROM. + -- + latch_rom_d: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + d_char_rom_q <= (others => '0'); + crg3_q <= '0'; + crg4_q <= '0'; + crg5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if (clk_en_5mhz_i and + h2_s and h1_s and h0_s) = '1' then + d_char_rom_q <= rom_char_d_i; + crg3_q <= d_col_ram_q(0); + crg4_q <= d_col_ram_q(1); + crg5_q <= d_col_ram_q(2); + end if; + + end if; + end process latch_rom_d; + -- + ----------------------------------------------------------------------------- + -- Process hbl_seq + -- + -- Purpose: + -- Implements the flip-flop that latches HBL. + -- + hbl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hbl_q <= '0'; + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + if hcnt /= 255 then + hcnt <= hcnt + 1; + end if; + end if; + if ha_t_rise_i = '1' then + hbl_q <= hbl_i; + if hbl_q = '1' and hbl_i = '0' then + hcnt <= 0; + end if; + end if; + end if; + end process hbl_seq; + -- + ----------------------------------------------------------------------------- + + process (clk_20mhz_i) + begin + if rising_edge(clk_20mhz_i) then + if clk_en_5mhz_i = '1' then + hbl_d <= hbl_q; + + if hcnt < 240 then + hblank_o <= '0'; + else + hblank_o <= '1'; + end if; + + if hbl_d = '0' and hbl_q = '1' then + vblank_o <= not blank_flont_i; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process crg_mux + -- + -- Purpose: + -- Multiplexes the latched character ROM data to CRG1 and CRG2. + -- + crg_mux: process (d_char_rom_q, + h_flip_s, + blank_flont_i, + hbl_q) + variable blank_v : std_logic; + variable idx_v : unsigned(2 downto 0); + begin + blank_v := not (blank_flont_i and not hbl_q); + idx_v := unsigned(h_flip_s(2 downto 0)); + + if blank_v = '0' then + crg1_s <= d_char_rom_q(to_integer('0' & idx_v)); + crg2_s <= d_char_rom_q(to_integer('1' & idx_v)); + else + crg1_s <= '0'; + crg2_s <= '0'; + end if; + + blank_o <= blank_v; + end process crg_mux; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + wait_n_o <= not wait_q; + crg_o(5) <= crg5_q; + crg_o(4) <= crg4_q; + crg_o(3) <= crg3_q; + crg_o(2) <= crg2_s; + crg_o(1) <= crg1_s; + rom_char_a_o( 2 downto 0) <= v_flip_s(2 downto 0); + rom_char_a_o(10 downto 3) <= d_char_ram_q; + rom_char_a_o(11) <= d_col_ram_q(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_chute.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_chute.vhd new file mode 100644 index 00000000..b3255fe0 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_chute.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chute.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaper for a chute input. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chute is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + chute_i : in std_logic; + chute_o : out std_logic + ); + +end ladybug_chute; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_chute is + + -- 2.35e-2 s = 1 / 20,000,000 Hz * 470000 + constant chute_delay_c : natural := 470000; + + signal chute_cnt_q : unsigned(18 downto 0); + + signal chute_sync_q : std_logic_vector(1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process sync + -- + -- Purpose: + -- Synchronize the asynchronous chute input. + -- + sync: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_sync_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + chute_sync_q(0) <= chute_i; + chute_sync_q(1) <= chute_sync_q(0); + + end if; + end process sync; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cnt + -- + -- Purpose: + -- Count the required number of 20 MHz clock cycles before emitting + -- chute event. This is a low pass filter for the rising edge of chute_i. + -- + cnt: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if chute_sync_q(1) = '1' then + if chute_cnt_q = chute_delay_c then + chute_o <= '1'; + else + chute_cnt_q <= chute_cnt_q + 1; + end if; + + else + -- reset counter when chute input goes back to 0 + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + end if; + + end if; + end process cnt; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_chutes.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_chutes.vhd new file mode 100644 index 00000000..7584de89 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_chutes.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chutes.vhd,v 1.4 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaping for the two chute inputs. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chutes is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + cs8_n_i : in std_logic; + nmi_n_o : out std_logic; + int_n_o : out std_logic + ); + +end ladybug_chutes; + +architecture rtl of ladybug_chutes is + + signal right_chute_s, + left_chute_s : std_logic; + signal left_chute_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Pulse shaper for Right Chute + ----------------------------------------------------------------------------- + right_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => right_chute_i, + chute_o => right_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Pulse shaper for Left Chute + ----------------------------------------------------------------------------- + left_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => left_chute_i, + chute_o => left_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Process left_edge + -- + -- Purpose: + -- Implement the edge detector for the left chute. + -- Only a rising edge of the filtered chute input can trigger a new + -- interrupt to the CPU. + -- + left_edge: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + left_chute_q <= '0'; + int_n_o <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + left_chute_q <= left_chute_s; + + if cs8_n_i = '0' then + -- synchronous set, has priority over data path + int_n_o <= '1'; + + -- edge detector + elsif left_chute_s = '1' and left_chute_q = '0' then + int_n_o <= '0'; + + end if; + + end if; + end process left_edge; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + nmi_n_o <= not right_chute_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_clk.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_clk.vhd new file mode 100644 index 00000000..d3e00484 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_clk.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_clk.vhd,v 1.5 2005/10/28 21:17:41 arnim Exp $ +-- +-- Clock generator for the Lady Bug machine. +-- +-- This module generates the clock enables which are required to mimic the +-- different clocks of the Lady Bug boards. +-- +-- Theory of Operation: +-- A PLL is used to tune the external clock to 20 MHz. This forms the +-- main clock which is used by all sequential elements. +-- All derived clocks are built with clock enables to allow a synchronous +-- design style (sort of). +-- +-- Note: +-- The counters and enable signals are reset by the power-on reset. +-- Thus, the "derived clocks" run during normal system reset. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_clk is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_10mhz_n_o : out std_logic; + clk_en_5mhz_o : out std_logic; + clk_en_5mhz_n_o : out std_logic; + clk_en_4mhz_o : out std_logic + ); + +end ladybug_clk; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_clk is + + -- counter for 5 MHz and 10 MHz clock enables + signal clk_cnt_5mhz_q : unsigned(1 downto 0); + -- counter for 4 MHz clock enable + signal clk_cnt_4mhz_q : unsigned(2 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process clk_en + -- + -- Purpose: + -- Generates the clock enables for 10 MHz, 5 MHz, 4 MHz. + -- + clk_en: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_cnt_5mhz_q <= (others => '0'); + clk_cnt_4mhz_q <= (others => '0'); + clk_en_10mhz_o <= '0'; + clk_en_10mhz_n_o <= '0'; + clk_en_5mhz_o <= '0'; + clk_en_5mhz_n_o <= '0'; + clk_en_4mhz_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + + ------------------------------------------------------------------------- + -- 10 MHz / 5 MHz clock domain + -- + -- counter for 10 MHz and 5 MHz clock enables + clk_cnt_5mhz_q <= clk_cnt_5mhz_q + 1; + + -- generate clock enable for 10 MHz + -- enable on every second clock of clk_20mhz_i + clk_en_10mhz_o <= clk_cnt_5mhz_q(0); + -- enable with 180 deg phase shift + clk_en_10mhz_n_o <= not clk_cnt_5mhz_q(0); + + -- generate clock enables for 5 MHz: + -- enable on every forth clock of clk_20mhz_i + if clk_cnt_5mhz_q = "11" then + clk_en_5mhz_o <= '1'; + else + clk_en_5mhz_o <= '0'; + end if; + -- enable with 180 deg phase shift + if clk_cnt_5mhz_q = "01" then + clk_en_5mhz_n_o <= '1'; + else + clk_en_5mhz_n_o <= '0'; + end if; + -- + ------------------------------------------------------------------------- + + + ------------------------------------------------------------------------- + -- 4 MHz domain + -- + -- counter for 4 MHz clock enable, wrap around after 5 clocks + clk_en_4mhz_o <= clk_cnt_4mhz_q(2); + + if clk_cnt_4mhz_q = "100" then + clk_cnt_4mhz_q <= (others => '0'); + else + clk_cnt_4mhz_q <= clk_cnt_4mhz_q + 1; + end if; + -- + ------------------------------------------------------------------------- + + end if; + end process clk_en; + -- + ----------------------------------------------------------------------------- + + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_counter.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_counter.vhd new file mode 100644 index 00000000..d07256bb --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_counter.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------- +-- +-- Synchronous 8-Bit Binary Counter with preset. +-- +-- $Id: ladybug_counter.vhd,v 1.9 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity counter is +port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + reset_n_i : in std_logic; + load_i : in std_logic; + preset_i : in std_logic_vector(7 downto 0); + q_o : out std_logic_vector(7 downto 0); + rise_q_o : out std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0); + co_o : out std_logic +); +end counter; + +architecture rtl of counter is + signal cnt_q : std_logic_vector(7 downto 0); + signal cnt_s : std_logic_vector(7 downto 0); +begin + + seq: process (ck_i, reset_n_i) + begin + if reset_n_i = '0' then + cnt_q <= (others => '0'); + elsif rising_edge(ck_i) then + cnt_q <= cnt_s; + end if; + end process seq; + + adder: process (ck_en_i, cnt_q, load_i, preset_i) + begin + cnt_s <= cnt_q; + + if ck_en_i = '1' then + if load_i = '1' then + cnt_s <= preset_i; + else + cnt_s <= cnt_q + 1; + end if; + end if; + end process adder; + + co_o <= '1' when cnt_q = x"FF" else '0'; + rise_q_o <= cnt_s and not cnt_q; + q_o <= cnt_q; + d_o <= cnt_s; +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd new file mode 100644 index 00000000..7d41074f --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_cpu_unit.vhd @@ -0,0 +1,260 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_unit.vhd,v 1.19 2005/12/10 14:51:51 arnim Exp $ +-- +-- CPU Main Unit of the Lady Bug Machine. +-- +-- Actually, the PCB where the CPU resides on contains also the sound chips and +-- parts of the video controller. For the sake of simplicity, the CPU and chip +-- select logic has been moved into this separate unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_unit is + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + res_n_i : in std_logic; + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + sound_wait_n_i : in std_logic; + wait_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + gpio_in0_i : in std_logic_vector( 7 downto 0); + gpio_in1_i : in std_logic_vector( 7 downto 0); + gpio_in2_i : in std_logic_vector( 7 downto 0); + gpio_in3_i : in std_logic_vector( 7 downto 0); + gpio_extra_i : in std_logic_vector( 7 downto 0); + a_o : out std_logic_vector(10 downto 0); + d_to_cpu_i : in std_logic_vector( 7 downto 0); + d_from_cpu_o : out std_logic_vector( 7 downto 0); + rd_n_o : out std_logic; + wr_n_o : out std_logic; + cs7_n_o : out std_logic; + cs10_n_o : out std_logic; + cs11_n_o : out std_logic; + cs12_n_o : out std_logic; + cs13_n_o : out std_logic + ); + +end ladybug_cpu_unit; + +architecture struct of ladybug_cpu_unit is + + signal t80_clk_en_s : std_logic; + + signal wait_n_s : std_logic; + signal int_n_s : std_logic; + signal nmi_n_s : std_logic; + signal mreq_n_s : std_logic; + signal rd_n_s : std_logic; + signal wr_n_s : std_logic; + signal rfsh_n_s : std_logic; + signal m1_n_s : std_logic; + signal a_s : std_logic_vector(15 downto 0); + signal d_to_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_rom_s, + d_decrypted_s, + d_rom_mux_s : std_logic_vector( 7 downto 0); + signal d_from_ram_s : std_logic_vector( 7 downto 0); + signal d_from_gpio_s : std_logic_vector( 7 downto 0); + + signal cs_n_s : std_logic_vector(15 downto 0); + + signal ram_cpu_cs_n_s : std_logic; + + signal vcc_s : std_logic; + +begin + vcc_s <= '1'; + + wait_n_s <= sound_wait_n_i and wait_n_i; + + ----------------------------------------------------------------------------- + -- The T80 CPU + ----------------------------------------------------------------------------- + -- "wait" has to be modelled with the clock enable because the T80 is not + -- able to enlarge write accesses properly when they are delayed with "wait" + t80_clk_en_s <= clk_en_4mhz_i and wait_n_s; + T80a_b : entity work.T80a + generic map ( + Mode => 0 + ) + port map ( + RESET_n => res_n_i, + CLK_n => clk_20mhz_i, + CLK_EN_SYS => t80_clk_en_s, + WAIT_n => wait_n_s, + INT_n => int_n_s, + NMI_n => nmi_n_s, + BUSRQ_n => vcc_s, + M1_n => m1_n_s, + MREQ_n => mreq_n_s, + IORQ_n => open, + RD_n => rd_n_s, + WR_n => wr_n_s, + RFSH_n => rfsh_n_s, + HALT_n => open, + BUSAK_n => open, + A => a_s, + DI => d_to_cpu_s, + DO => d_from_cpu_s + ); + d_from_cpu_o <= d_from_cpu_s; + + + ----------------------------------------------------------------------------- + -- The CPU RAM + ----------------------------------------------------------------------------- + cpu_ram_b : entity work.ladybug_cpu_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => a_s(11 downto 0), + cs_n_i => cs_n_s(6), + we_n_i => wr_n_s, + d_i => d_from_cpu_s, + d_o => d_from_ram_s + ); + + ----------------------------------------------------------------------------- + -- The Address Decoder + ----------------------------------------------------------------------------- + addr_dec_b : entity work.ladybug_addr_dec + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + a_i => a_s(15 downto 12), + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + mreq_n_i => mreq_n_s, + rfsh_n_i => rfsh_n_s, + cs_n_o => cs_n_s, + ram_cpu_cs_n_o => ram_cpu_cs_n_s + ); + + + ----------------------------------------------------------------------------- + -- The General Purpose IO + ----------------------------------------------------------------------------- + gpio_b : entity work.ladybug_gpio + port map ( + a_i => a_s(1 downto 0), + cs_in_n_i => cs_n_s(9), + cs_extra_n_i => cs_n_s(14), + in0_i => gpio_in0_i, + in1_i => gpio_in1_i, + in2_i => gpio_in2_i, + in3_i => gpio_in3_i, + extra_i => gpio_extra_i, + d_o => d_from_gpio_s + ); + + + ----------------------------------------------------------------------------- + -- The Coin Chutes + ----------------------------------------------------------------------------- + coin_chutes_b : entity work.ladybug_chutes + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + cs8_n_i => cs_n_s(8), + nmi_n_o => nmi_n_s, + int_n_o => int_n_s + ); + + + ----------------------------------------------------------------------------- + -- Decrytion PROMs + ----------------------------------------------------------------------------- + + decrypt_prom : entity work.prom_decrypt + port map ( + CLK => clk_20mhz_i, + ADDR => rom_cpu_d_i, + DATA => d_decrypted_s + ); + + ----------------------------------------------------------------------------- + -- Only opcodes (i.e. instruction fetches) have to be decrypted + ----------------------------------------------------------------------------- + d_rom_mux_s <= d_decrypted_s when m1_n_s = '0' else rom_cpu_d_i; + + ----------------------------------------------------------------------------- + -- Gate Data Bus from ROM + -- The ROM puts data on the data bus within the CPU Main Unit so we do + -- gating here. + ----------------------------------------------------------------------------- + d_from_rom_s <= d_rom_mux_s + when cs_n_s(0) = '0' or cs_n_s(1) = '0' or cs_n_s(2) = '0' or + cs_n_s(3) = '0' or cs_n_s(4) = '0' or cs_n_s(5) = '0' else + (others => '1'); + + + ----------------------------------------------------------------------------- + -- Combine Data Buses + -- Uses an AND of all incoming buses from submodules. Each module has to + -- drive ones when not active so we can save logic complexity here. + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_to_cpu_i and d_from_rom_s and d_from_ram_s and d_from_gpio_s; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + a_o <= a_s(10 downto 0); + rom_cpu_a_o <= a_s(14 downto 0); + rd_n_o <= rd_n_s; + wr_n_o <= wr_n_s; + cs7_n_o <= cs_n_s(7); + cs10_n_o <= cs_n_s(10); + cs11_n_o <= cs_n_s(11); + cs12_n_o <= cs_n_s(12); + cs13_n_o <= cs_n_s(13); + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_dip_pack.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_dip_pack.vhd new file mode 100644 index 00000000..ebff8ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_dip_pack.vhd @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------- +-- +-- $Id: ladybug_dip_pack-p.vhd,v 1.4 2005/10/10 20:52:04 arnim Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package ladybug_dip_pack is + + ----------------------------------------------------------------------------- + -- DIP switch settings for Lady Bug + ----------------------------------------------------------------------------- + constant lb_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- High Score Initials ---------------------------------------------------- + -- 0 = 3-Letter Initials + -- 1 = 10-Letter Initials + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + ----------------------------------------------------------------------------- + -- DIP switch settings for Dorodon + ----------------------------------------------------------------------------- + constant do_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- Bonus Life ------------------------------------------------------------- + -- 0 = 40000 + -- 1 = 20000 + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + + ----------------------------------------------------------------------------- + -- DIP switch settings for Cosmic Avenger + ----------------------------------------------------------------------------- + constant ca_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives per Game --------------------------------------------------------- + -- 00 = 2 Lives + -- 11 = 3 Lives + -- 10 = 4 Lives + -- 01 = 5 Lives + "01" & + -- Initial High Score ----------------------------------------------------- + -- 00 = 0 + -- 11 = 5000 + -- 10 = 8000 + -- 01 = 10000 + "11" & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- High Score Names ------------------------------------------------------- + -- 0 = 3 Letters + -- 1 = 10 Letters + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + constant price_dip_block_2_c : std_logic_vector(7 downto 0) := + -- Pricing Options -------------------------------------------------------- + -- 1111 = 1 coin 1 credit + -- 1110 = 1 coin 2 credits + -- 1101 = 1 coin 3 credits + -- 1100 = 1 coin 4 credits + -- 1011 = 1 coin 5 credits + -- 1010 = 2 coins 1 credit + -- 1001 = 2 coins 3 credits + -- 1000 = 3 coins 1 credit + -- 0111 = 3 coins 2 credit + -- 0110 = 4 coins 1 credit + -- 0101 = 1 coin 1 credit + -- 0100 = 1 coin 1 credit + -- 0011 = 1 coin 1 credit + -- 0010 = 1 coin 1 credit + -- 0001 = 1 coin 1 credit + -- 0000 = 1 coin 1 credit + -- + -- Left Chute + "1111" & + -- Right Chute + "1111"; + +end ladybug_dip_pack; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_gpio.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_gpio.vhd new file mode 100644 index 00000000..6ca21711 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_gpio.vhd @@ -0,0 +1,139 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_gpio.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- General purpose IO input for CPU Main Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_gpio is + + port ( + a_i : in std_logic_vector(1 downto 0); + cs_in_n_i : in std_logic; + cs_extra_n_i : in std_logic; + in0_i : in std_logic_vector(7 downto 0); + in1_i : in std_logic_vector(7 downto 0); + in2_i : in std_logic_vector(7 downto 0); + in3_i : in std_logic_vector(7 downto 0); + extra_i : in std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0) + ); + +end ladybug_gpio; + + +architecture rtl of ladybug_gpio is + +begin + + ----------------------------------------------------------------------------- + -- Process gpio + -- + -- Purpose: + -- Multiplex the IN and EXTRA inputs onto the data bus for CPU. + -- + gpio: process (a_i, + cs_in_n_i, + cs_extra_n_i, + in0_i, + in1_i, + in2_i, + in3_i, + extra_i) + variable cs_n_v : std_logic_vector(1 downto 0); + begin + -- default assignment with inactive bus value + d_o <= (others => '1'); + + cs_n_v := cs_extra_n_i & cs_in_n_i; + case cs_n_v is + -- IN ports and DIP switches selected ----------------------------------- + when "10" => + case a_i is + -- IN 0 addressed + when "00" => + d_o <= in0_i; + -- IN 1 addressed + when "01" => + d_o <= in1_i; + -- DIP 0 addressed + when "10" => + d_o <= in2_i; + -- DIP 1 addressed + when "11" => + d_o <= in3_i; + + when others => + null; + end case; + + -- Extra bank selected -------------------------------------------------- + when "01" => + case a_i is + when "00" => + d_o(1) <= extra_i(7); + d_o(0) <= extra_i(3); + when "01" => + d_o(1) <= extra_i(6); + d_o(0) <= extra_i(2); + when "10" => + d_o(1) <= extra_i(5); + d_o(0) <= extra_i(1); + when "11" => + d_o(1) <= extra_i(4); + d_o(0) <= extra_i(0); + when others => + null; + end case; + + when others => + null; + end case; + + end process gpio; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd new file mode 100644 index 00000000..584b8391 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_machine.vhd @@ -0,0 +1,295 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_machine.vhd,v 1.23 2006/02/07 00:44:21 arnim Exp $ +-- +-- Toplevel of the Lady Bug machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_machine is + port ( + -- Clock and Reset Interface ---------------------------------------------- + ext_res_n_i : in std_logic; + clk_20mhz_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_5mhz_o : out std_logic; + por_n_o : out std_logic; + -- Control Interface ------------------------------------------------------ + tilt_n_i : in std_logic; + player_select_n_i : in std_logic_vector( 1 downto 0); + player_fire_n_i : in std_logic_vector( 1 downto 0); + player_up_n_i : in std_logic_vector( 1 downto 0); + player_right_n_i : in std_logic_vector( 1 downto 0); + player_down_n_i : in std_logic_vector( 1 downto 0); + player_left_n_i : in std_logic_vector( 1 downto 0); + player_bomb_n_i : in std_logic_vector( 1 downto 0); + right_chute_i : in std_logic; + left_chute_i : in std_logic; + -- DIP Switch Interface --------------------------------------------------- + dip_block_1_i : in std_logic_vector( 7 downto 0); + dip_block_2_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Audio Interface -------------------------------------------------------- + audio_o : out signed( 7 downto 0); + -- CPU ROM Interface ------------------------------------------------------ + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + + +end ladybug_machine; + +architecture struct of ladybug_machine is + + -- Clock System ------------------------------------------------------------- + signal clk_en_10mhz_s, + clk_en_10mhz_n_s : std_logic; + signal clk_en_5mhz_s, + clk_en_5mhz_n_s : std_logic; + signal clk_en_4mhz_s : std_logic; + + -- Reset System ------------------------------------------------------------- + signal por_n_s : std_logic; + signal res_n_s : std_logic; + + signal sound_wait_n_s : std_logic; + signal wait_n_s : std_logic; + signal a_s : std_logic_vector(10 downto 0); + signal d_to_cpu_s, + d_from_cpu_s, + d_from_video_s : std_logic_vector( 7 downto 0); + signal rd_n_s, + wr_n_s : std_logic; + signal cs7_n_s, + cs10_n_s, + cs11_n_s, + cs12_n_s, + cs13_n_s : std_logic; + signal vc_s, + vbl_tick_n_s, + vbl_buf_s : std_logic; + + signal gpio_in0_s, + gpio_in1_s, + gpio_in2_s, + gpio_in3_s, + gpio_extra_s : std_logic_vector( 7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk_b : entity work.ladybug_clk + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + clk_en_10mhz_o => clk_en_10mhz_s, + clk_en_10mhz_n_o => clk_en_10mhz_n_s, + clk_en_5mhz_o => clk_en_5mhz_s, + clk_en_5mhz_n_o => clk_en_5mhz_n_s, + clk_en_4mhz_o => clk_en_4mhz_s + ); + -- + clk_en_5mhz_o <= clk_en_5mhz_s; + clk_en_10mhz_o <= clk_en_10mhz_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + res_b : entity work.ladybug_res + port map ( + clk_20mhz_i => clk_20mhz_i, + ext_res_n_i => ext_res_n_i, + res_n_o => res_n_s, + por_n_o => por_n_s + ); + -- + por_n_o <= por_n_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Joystick and DIP Switch Mapping + ----------------------------------------------------------------------------- + gpio_in0_s <= tilt_n_i & + player_select_n_i(1) & + player_select_n_i(0) & + player_fire_n_i(0) & + player_up_n_i(0) & + player_right_n_i(0) & + player_down_n_i(0) & + player_left_n_i(0); + gpio_in1_s <= vbl_buf_s & + vbl_tick_n_s & + vc_s & + player_fire_n_i(1) & + player_up_n_i(1) & + player_right_n_i(1) & + player_down_n_i(1) & + player_left_n_i(1); + gpio_in2_s <= dip_block_1_i; + gpio_in3_s <= dip_block_2_i; + gpio_extra_s <= player_bomb_n_i(1) & + '1' & + '1' & + '1' & + player_bomb_n_i(0) & + '1' & + '1' & + '1'; + + + ----------------------------------------------------------------------------- + -- CPU Unit + ----------------------------------------------------------------------------- + cpu_b : entity work.ladybug_cpu_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + res_n_i => res_n_s, + rom_cpu_a_o => rom_cpu_a_o, + rom_cpu_d_i => rom_cpu_d_i, + + sound_wait_n_i => sound_wait_n_s, + wait_n_i => wait_n_s, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + gpio_in0_i => gpio_in0_s, + gpio_in1_i => gpio_in1_s, + gpio_in2_i => gpio_in2_s, + gpio_in3_i => gpio_in3_s, + gpio_extra_i => gpio_extra_s, + a_o => a_s, + d_to_cpu_i => d_to_cpu_s, + d_from_cpu_o => d_from_cpu_s, + rd_n_o => rd_n_s, + wr_n_o => wr_n_s, + cs7_n_o => cs7_n_s, + cs10_n_o => cs10_n_s, + cs11_n_o => cs11_n_s, + cs12_n_o => cs12_n_s, + cs13_n_o => cs13_n_s + ); + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_from_video_s when (cs7_n_s and cs13_n_s) = '0' else (others => '1'); + + ----------------------------------------------------------------------------- + -- Video Unit + ----------------------------------------------------------------------------- + video_b : entity work.ladybug_video_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + res_n_i => res_n_s, + clk_en_10mhz_i => clk_en_10mhz_s, + clk_en_10mhz_n_i => clk_en_10mhz_n_s, + clk_en_5mhz_i => clk_en_5mhz_s, + clk_en_5mhz_n_i => clk_en_5mhz_n_s, + clk_en_4mhz_i => clk_en_4mhz_s, + cs7_n_i => cs7_n_s, + cs10_n_i => cs10_n_s, + cs13_n_i => cs13_n_s, + a_i => a_s, + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + wait_n_o => wait_n_s, + d_from_cpu_i => d_from_cpu_s, + d_from_video_o => d_from_video_s, + vc_o => vc_s, + vbl_tick_n_o => vbl_tick_n_s, + vbl_buf_o => vbl_buf_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n_o, + vblank_o => vblank_o, + hblank_o => hblank_o, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + ----------------------------------------------------------------------------- + -- Sound Unit + ----------------------------------------------------------------------------- + sound_b : entity work.ladybug_sound_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + por_n_i => por_n_s, + cs11_n_i => cs11_n_s, + cs12_n_i => cs12_n_s, + wr_n_i => wr_n_s, + d_from_cpu_i => d_from_cpu_s, + sound_wait_n_o => sound_wait_n_s, + audio_o => audio_o + ); + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_rams.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_rams.vhd new file mode 100644 index 00000000..578d08e7 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_rams.vhd @@ -0,0 +1,340 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_char_ram; + +architecture struct of ladybug_char_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_sprite_ram; + +architecture struct of ladybug_sprite_ram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_col_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character color RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_col_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_char_col_ram; + +architecture struct of ladybug_char_col_ram is + + signal d_s : std_logic_vector(3 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_vram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite VRAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_vram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_sprite_vram; + +architecture struct of ladybug_sprite_vram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_ram.vhd,v 1.1 2005/11/06 15:43:38 arnim Exp $ +-- +-- Wrapper for technology dependent CPU RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 4 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(11 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_cpu_ram; + +architecture struct of ladybug_cpu_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram1_inst: work.spram generic map(12,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_res.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_res.vhd new file mode 100644 index 00000000..85998a10 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_res.vhd @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_res.vhd,v 1.8 2005/10/10 20:52:04 arnim Exp $ +-- +-- Reset generator for the Lady Bug machine. +-- +-- This module generates a reset signal for the whole system synchronous to +-- the main clock. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity ladybug_res is + + port ( + clk_20mhz_i : in std_logic; + ext_res_n_i : in std_logic; + res_n_o : out std_logic; + por_n_o : out std_logic + ); + +end ladybug_res; + +architecture rtl of ladybug_res is + + -- 4.7e-2 s = 1 / 20,000,000 Hz * 940000 + constant res_delay_c : natural := 940000; + + signal res_sync_n_q : std_logic_vector(1 downto 0); + + signal res_delay_q : unsigned(19 downto 0); + signal res_n_q : std_logic; + + signal por_cnt_q : unsigned(1 downto 0) := "00"; + signal por_n_q : std_logic := '0'; +begin + + por_n_o <= por_n_q; + res_n_o <= res_n_q; + + ----------------------------------------------------------------------------- + -- Process por_cnt + -- + -- Purpose: + -- Generate a power-on reset for 4 clock cycles. + -- + por_cnt: process (clk_20mhz_i) + begin + if clk_20mhz_i'event and clk_20mhz_i = '1' then + if por_cnt_q = "11" then + por_n_q <= '1'; + else + por_cnt_q <= por_cnt_q + 1; + end if; + end if; + end process por_cnt; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_sync + -- + -- Purpose: + -- Synchronize asynchronous external reset to main 20 MHz clock. + -- + res_sync: process (clk_20mhz_i, ext_res_n_i, por_n_q) + begin + if ext_res_n_i = '0' or por_n_q = '0' then + res_sync_n_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + res_sync_n_q(0) <= '1'; + res_sync_n_q(1) <= res_sync_n_q(0); + end if; + end process res_sync; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_delay + -- + -- Purpose: + -- Delay reset event (external or power-on) by 4.7e-2 s. + -- Reset delay is taken from Lady Bug reset circuit using NE555. + -- This duration might be too long for the actual requirements of the + -- FPGA circuit. + -- + res_delay: process (clk_20mhz_i, res_sync_n_q) + begin + if res_sync_n_q(1) = '0' then + res_delay_q <= (others => '0'); + res_n_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if res_delay_q = res_delay_c then + res_n_q <= '1'; + else + res_delay_q <= res_delay_q + 1; + end if; + end if; + end process res_delay; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_rgb.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_rgb.vhd new file mode 100644 index 00000000..1bfcd53c --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_rgb.vhd @@ -0,0 +1,135 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_rgb.vhd,v 1.4 2005/10/10 22:02:14 arnim Exp $ +-- +-- RGB Generation Module of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_rgb is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + crg_i : in std_logic_vector(5 downto 1); + sig_i : in std_logic_vector(4 downto 1); + rgb_r_o : out std_logic_vector(1 downto 0); + rgb_g_o : out std_logic_vector(1 downto 0); + rgb_b_o : out std_logic_vector(1 downto 0) + ); + +end ladybug_rgb; + +architecture rtl of ladybug_rgb is + + signal a_s : std_logic_vector(5 downto 1); + signal rgb_s : std_logic_vector(8 downto 1); + signal rgb_n_q : std_logic_vector(8 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process addr + -- + -- Purpose: + -- Generates the PROM address. + -- + addr: process (crg_i, + sig_i) + variable sig_and_v : std_logic; + begin + sig_and_v := sig_i(1) and sig_i(2) and sig_i(3) and sig_i(4); + + a_s(5) <= crg_i(1) and sig_and_v; + + if not (sig_and_v and (crg_i(1) or crg_i(2))) = '0' then + a_s(4 downto 1) <= crg_i(2) & crg_i(5) & crg_i(4) & crg_i(3); + else + a_s(4 downto 1) <= sig_i; + end if; + + end process addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The RGB Conversion PROM + ----------------------------------------------------------------------------- + rgb_prom_b : entity work.prom_10_2 + port map ( + CLK => clk_20mhz_i, + ADDR => a_s, + DATA => rgb_s + ); + + ----------------------------------------------------------------------------- + -- Process rgb_latch + -- + -- Purpose: + -- Implements the output latch for the RGB values. + -- + rgb_latch: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rgb_n_q <= (others => '1'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + rgb_n_q <= not rgb_s; + end if; + end if; + end process rgb_latch; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rgb_r_o <= rgb_n_q(5+1) & rgb_n_q(0+1); + rgb_g_o <= rgb_n_q(6+1) & rgb_n_q(2+1); + rgb_b_o <= rgb_n_q(7+1) & rgb_n_q(4+1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sprite.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sprite.vhd new file mode 100644 index 00000000..941d997c --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sprite.vhd @@ -0,0 +1,857 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite.vhd,v 1.12 2005/10/10 22:02:14 arnim Exp $ +-- +-- Sprite Video Module of Lady Bug Machine. +-- +-- This unit contains the whole sprite logic which is distributed on the +-- CPU and video boards. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_sprite is +port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + a_i : in std_logic_vector( 9 downto 0); + d_from_cpu_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + hx_i : in std_logic; + ha_d_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_d_i : in std_logic; + blank_flont_i : in std_logic; + blank_i : in std_logic; + sig_o : out std_logic_vector( 4 downto 1); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) +); + +end ladybug_sprite; + +architecture rtl of ladybug_sprite is + + signal sprite_ram_cs_n_s, + sprite_ram_we_n_s, + clk_5mhz_n_q, + clk_en_eck_s, + clk_en_rd_s, + clk_en_5ck_n_s, + clk_en_6ck_n_s, + clk_en_7ck_n_s, + clk_en_b7_p3_s, + clk_en_e7_3_s, + s6ck_n_s, + s7ck_n_s, + e5_p8_s, + a8_p5_n_s, + ct0_s, + ct1_s, + cr_mux_sel_s, + ck_inh_s, + ck_inh_n_q, + qh1_s, + qh2_s : std_logic; + + signal rb_s, + rb_unflip_s, + rc_s : std_logic_vector( 7 downto 0); + + signal c_s : std_logic_vector(10 downto 0); + signal v_cnt_s : std_logic_vector( 4 downto 0); + signal ra_s : std_logic_vector( 9 downto 0); + + signal ma_s : std_logic_vector(11 downto 0); + signal ma_q : std_logic_vector(11 downto 6); + signal mb_q : std_logic_vector( 1 downto 0); + signal mc_q : std_logic_vector( 6 downto 0); + signal cl_q : std_logic_vector( 4 downto 0); + + signal j7_s : std_logic_vector( 2 downto 0); + signal df_muxed_s : std_logic_vector( 7 downto 0); + + signal lu_a_s : std_logic_vector( 4 downto 0); + signal lu_d_s : std_logic_vector( 7 downto 0); + signal lu_d_mux_s : std_logic_vector( 3 downto 0); + + signal rd_shift_s, + rd_shift_int, + rd_vram_s : std_logic_vector(15 downto 0); + signal rs_s, + rs_int, + rs_n_s : std_logic_vector( 3 downto 0); + signal rs_enable_s : std_logic; + signal shift_oc_n_s : std_logic; + + signal j6_shifter : std_logic_vector( 3 downto 0); + signal h6_shifter : std_logic_vector( 3 downto 0); + signal ctrl_lu_a_s : std_logic_vector( 4 downto 0); + signal ctrl_lu_d_s : std_logic_vector( 7 downto 0); + signal v_cnt_a5_a6_s : std_logic_vector( 7 downto 0); + + signal ctrl_lu_q_d_s, + ctrl_lu_q : std_logic_vector( 6 downto 1); + + signal vram_we_n_s : std_logic; + signal vram_a6_in_s, + vram_a6_out_s, + vram_b6_in_s, + vram_b6_out_s, + vram_c6_in_s, + vram_c6_out_s, + vram_d6_in_s, + vram_d6_out_s : std_logic_vector( 3 downto 0); + + signal ca_q : std_logic_vector( 3 downto 1); + signal ca6_s, + ca7_s, + ca8_s : std_logic; + signal x_s : std_logic_vector( 5 downto 0); + + signal cr_s : std_logic_vector( 9 downto 0); + + signal vram_q : std_logic_vector(15 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- The Vertical Counters C5 D5 + ----------------------------------------------------------------------------- + v_cnt_c5_c6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_b7_p3_s = '1' then + if e5_p8_s = '0' then + v_cnt_s <= (v_t_i & "0"); + else + v_cnt_s <= v_cnt_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Counter J7 + ----------------------------------------------------------------------------- + j7_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + j7_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s6ck_n_s = '0' then + j7_s <= not mc_q(6) & mc_q(6) & '0'; + elsif (ct0_s or ct1_s or a8_p5_n_s or ck_inh_s) = '0' then + j7_s <= j7_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Sprite VRAM Counters A5 A6 + ----------------------------------------------------------------------------- + ct0_s <= v_cnt_a5_a6_s(0); + ct1_s <= v_cnt_a5_a6_s(1); + x_s <= v_cnt_a5_a6_s(7 downto 2); + + v_cnt_a5_a6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_a5_a6_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s7ck_n_s = '0' then + v_cnt_a5_a6_s(7 downto 4) <= (rb_s(7 downto 4)); + v_cnt_a5_a6_s(3 downto 0) <= (rb_s(3 downto 2) & not rc_s(7) & not rc_s(6)); + elsif ck_inh_n_q = '1' then + v_cnt_a5_a6_s <=v_cnt_a5_a6_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process sprite_ram_ctrl + -- + -- Purpose: + -- Generates the control signals for the sprite RAM. + -- + sprite_ram_ctrl: process ( cs7_n_i, + vbl_n_i, + a_i, + c_s, v_cnt_s) + variable cpu_access_v : std_logic; + begin + cpu_access_v := not cs7_n_i and not vbl_n_i; + + sprite_ram_we_n_s <= not cpu_access_v; + sprite_ram_cs_n_s <= cpu_access_v nor vbl_n_i; + + if vbl_n_i = '0' then + ra_s <= a_i; + else + ra_s <= v_cnt_s(4 downto 0) & c_s(4 downto 0); + end if; + end process sprite_ram_ctrl; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Sprite RAM P5 N5 + ----------------------------------------------------------------------------- + sprite_ram_b : entity work.ladybug_sprite_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_5mhz_i, + a_i => ra_s, + cs_n_i => sprite_ram_cs_n_s, + we_n_i => sprite_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => rb_s + ); + + ----------------------------------------------------------------------------- + -- Process rc_add + -- + -- Purpose: + -- Implements IC N6 and E6 which add sprite RAM data and Cx signals to + -- form RCx bus. + -- + rc_add: process (rb_s, c_s, v_i) + variable a_v, b_v, + sum_v : std_logic_vector(7 downto 0); + begin + -- prepare the inputs of the adder + a_v(3 downto 0) := rb_s(3 downto 0); + a_v(4) := '1'; + a_v(5) := '0'; + a_v(7 downto 6) := rb_s(1 downto 0); + + b_v(0) := not c_s(6); + b_v(1) := not c_s(7); + b_v(2) := not c_s(8); + b_v(3) := not v_i(3); + b_v(4) := c_s(10); + b_v(5) := '0'; + b_v(7 downto 6) := "11"; + + sum_v := a_v + b_v; + + rc_s <= sum_v; + + end process rc_add; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Sprite Control Logic + ----------------------------------------------------------------------------- + sprite_ctrl_b : entity work.ladybug_sprite_ctrl + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + por_n_i => por_n_i, + vbl_n_i => vbl_n_i, + vbl_d_n_i => vbl_d_n_i, + vc_i => v_i(2), + vc_d_i => vc_d_i, + ha_i => h_i(0), + ha_d_i => ha_d_i, + rb6_i => rb_s(6), + rb7_i => rb_s(7), + rc3_i => rc_s(3), + rc4_i => rc_s(4), + rc5_i => rc_s(5), + j7_b_i => j7_s(1), + j7_c_i => j7_s(2), + clk_en_eck_i => clk_en_eck_s, + c_o => c_s, + clk_en_5ck_n_o => clk_en_5ck_n_s, + clk_en_6ck_n_o => clk_en_6ck_n_s, + clk_en_7ck_n_o => clk_en_7ck_n_s, + s6ck_n_o => s6ck_n_s, + s7ck_n_o => s7ck_n_s, + clk_en_b7_p3_o => clk_en_b7_p3_s, + e5_p8_o => e5_p8_s, + clk_en_e7_3_o => clk_en_e7_3_s, + a8_p5_n_o => a8_p5_n_s + ); + + ----------------------------------------------------------------------------- + -- Process misc_seq + -- + -- Purpose: + -- Implements several sequential elements. + -- + misc_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_n_q <= '0'; + ma_q <= (others => '0'); + mb_q <= (others => '0'); + mc_q <= (others => '0'); + cl_q <= (others => '0'); + ck_inh_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz_n into clock waveform ---------------------------------- + if clk_en_5mhz_n_i = '1' then + clk_5mhz_n_q <= '1'; + elsif clk_en_5mhz_i = '1' then + clk_5mhz_n_q <= '0'; + end if; + + -- 8-Bit Register M6 ---------------------------------------------------- + if clk_en_5ck_n_s = '1' then + mb_q <= rb_s(1 downto 0); + ma_q <= rb_s(7 downto 2); + end if; + + -- 8-Bit Register P6 ---------------------------------------------------- + if clk_en_e7_3_s = '1' then + -- these are inverted based on mc_q(4) + mc_q(3 downto 0) <= rc_s(3 downto 0); + -- inverts sprites horizontally + mc_q(4) <= rb_s(4); + -- inverts sprites vertically + mc_q(5) <= rb_s(5); + -- + mc_q(6) <= rb_s(6); + end if; + + -- 6-Bit Register B6 ---------------------------------------------------- + if clk_en_6ck_n_s = '1' then + cl_q <= rb_s(4 downto 0); + end if; + + -- Flip-Flop H8 --------------------------------------------------------- + if clk_en_10mhz_n_i = '1' then + ck_inh_n_q <= not ck_inh_s; + end if; + + end if; + end process misc_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ma_vec + -- + -- Purpose: + -- Build the ma_s vector. + -- + ma_vec: process ( ma_q, + mb_q, + mc_q, + j7_s) + begin + ma_s(11 downto 6) <= ma_q; + + if mc_q(6) = '0' then + ma_s(5) <= mb_q(1); + ma_s(4) <= mb_q(0); + else + ma_s(5) <= mc_q(3) xor mc_q(4); + ma_s(4) <= mc_q(5) xor j7_s(2); + end if; + + ma_s(3) <= mc_q(2) xor mc_q(4); + ma_s(2) <= mc_q(1) xor mc_q(4); + ma_s(1) <= mc_q(0) xor mc_q(4); + ma_s(0) <= mc_q(5) xor j7_s(0); + end process ma_vec; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process df_mux + -- + -- Purpose: + -- Builds the multiplexed data from Sprite ROM. + -- Two-stage multiplexer: + -- 1) ROM data to DFx: 16->8 + -- 2) DF to input for shift register: 8->8 + -- This is actually a scrambler. + -- + df_mux: process ( rom_sprite_d_i, + cl_q, + mc_q) + variable df_v : std_logic_vector(7 downto 0); + begin + if cl_q(4) = '0' then + -- ROM L7 + df_v := rom_sprite_d_i( 7 downto 0); + else + -- ROM M7 + df_v := rom_sprite_d_i(15 downto 8); + end if; + + if mc_q(5) = '0' then + df_muxed_s(0) <= df_v(1); + df_muxed_s(1) <= df_v(3); + df_muxed_s(2) <= df_v(5); + df_muxed_s(3) <= df_v(7); + -- + df_muxed_s(4) <= df_v(0); + df_muxed_s(5) <= df_v(2); + df_muxed_s(6) <= df_v(4); + df_muxed_s(7) <= df_v(6); + else + df_muxed_s(0) <= df_v(7); + df_muxed_s(1) <= df_v(5); + df_muxed_s(2) <= df_v(3); + df_muxed_s(3) <= df_v(1); + -- + df_muxed_s(4) <= df_v(6); + df_muxed_s(5) <= df_v(4); + df_muxed_s(6) <= df_v(2); + df_muxed_s(7) <= df_v(0); + end if; + + end process df_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Two 8-Bit Shift Registers H6 J6 + ----------------------------------------------------------------------------- + shifters_h6_j6 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + h6_shifter <= (others=>'0'); + j6_shifter <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + if (ct0_s or ct1_s or a8_p5_n_s) = '0' then + h6_shifter <= df_muxed_s(3 downto 0); + j6_shifter <= df_muxed_s(7 downto 4); + else + h6_shifter <= h6_shifter(2 downto 0) & "0"; + j6_shifter <= j6_shifter(2 downto 0) & "0"; + end if; + end if; + end if; + end process; + + qh1_s <= h6_shifter(3); + qh2_s <= j6_shifter(3); + + ----------------------------------------------------------------------------- + -- Sprite Look-up PROM F4 + ----------------------------------------------------------------------------- + lu_a_s(4 downto 2) <= cl_q(2 downto 0); + lu_a_s(1) <= qh2_s; + lu_a_s(0) <= qh1_s; + + prom_F4 : entity work.prom_10_1 + port map ( + CLK => clk_20mhz_i, + ADDR => lu_a_s, + DATA => lu_d_s + ); + + lu_d_mux_s <= lu_d_s(3 downto 0) when cl_q(3) = '0' else lu_d_s(7 downto 4); + + ----------------------------------------------------------------------------- + -- Sprite Control Look-up PROM C4 + ----------------------------------------------------------------------------- + ctrl_lu_a_s(0) <= '1'; + ctrl_lu_a_s(1) <= hx_i; + ctrl_lu_a_s(2) <= clk_5mhz_n_q; + ctrl_lu_a_s(3) <= h_i(0); + ctrl_lu_a_s(4) <= h_i(1); + + prom_C4 : entity work.prom_10_3 + port map ( + CLK => clk_20mhz_i, + ADDR => ctrl_lu_a_s, + DATA => ctrl_lu_d_s + ); + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_seq + -- + -- Purpose: + -- Registers output of Sprite Control Look-up PROM. + -- + ctrl_lu_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ctrl_lu_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + ctrl_lu_q <= ctrl_lu_q_d_s; + end if; + end process ctrl_lu_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_comb + -- + -- Purpose: + -- Combinational logic for the sprite control registers. + -- + ctrl_lu_comb: process ( clk_en_10mhz_i, + ctrl_lu_d_s, + ctrl_lu_q, + ctrl_lu_q_d_s) + begin + -- default assignments + ctrl_lu_q_d_s <= ctrl_lu_q; + clk_en_eck_s <= '0'; + clk_en_rd_s <= '0'; + + -- register control + if clk_en_10mhz_i = '1' then + ctrl_lu_q_d_s <= ctrl_lu_d_s(5 downto 0); + + if ctrl_lu_q(1) = '0' and ctrl_lu_q_d_s(1) = '1' then + -- detect rising edge on ctrl_lu_q(1) + clk_en_eck_s <= '1'; + end if; + + if ctrl_lu_q(6) = '0' and ctrl_lu_q_d_s(6) = '1' then + -- detect rising edge on ctrl_lu_q(6) + clk_en_rd_s <= '1'; + end if; + end if; + + end process ctrl_lu_comb; + -- + shift_oc_n_s <= ctrl_lu_q(1) nand res_n_i; + ck_inh_s <= ctrl_lu_q(2); + cr_mux_sel_s <= ctrl_lu_q(3); + vram_we_n_s <= ctrl_lu_q(4); + rs_enable_s <= ctrl_lu_q(5); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ca_seq + -- + -- Purpose: + -- Implements B5, the register that holds the CS flip-flops. + -- + ca_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ca_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_7ck_n_s = '1' then + ca_q <= c_s(8 downto 6); + end if; + end if; + end process ca_seq; + -- + ca6_s <= ca_q(1); + ca7_s <= ca_q(2); + ca8_s <= ca_q(3); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process vram_mux + -- + -- Purpose: + -- Generates the VRAM address CRx. + -- It implements chips D5, C5 and B5. + -- + vram_mux: process ( h_i, h_t_i, + v_i, + x_s, + ca6_s, ca7_s, ca8_s, + cr_mux_sel_s) + begin + if cr_mux_sel_s = '0' then + -- D5 + cr_s(0) <= h_i(2); + cr_s(1) <= h_i(3); + cr_s(2) <= h_t_i(0); + cr_s(3) <= h_t_i(1); + -- C5 + cr_s(4) <= h_t_i(2); + cr_s(5) <= h_t_i(3); + cr_s(6) <= v_i(0); + cr_s(7) <= v_i(1); + -- B5 + cr_s(8) <= v_i(2); + cr_s(9) <= v_i(3); + + else + -- D5 + cr_s(0) <= x_s(0); + cr_s(1) <= x_s(1); + cr_s(2) <= x_s(2); + cr_s(3) <= x_s(3); + -- C5 + cr_s(4) <= x_s(4); + cr_s(5) <= x_s(5); + cr_s(6) <= ca6_s; + cr_s(7) <= ca7_s; + -- B5 + cr_s(8) <= ca8_s; + cr_s(9) <= not v_i(3); + + end if; + end process vram_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Shift Registers + ----------------------------------------------------------------------------- + shifters_a7_a8_d7_d8_f8 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rd_shift_int <= (others=>'1'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + rs_int <= (qh1_s nor qh2_s) & rs_int(3 downto 1); + rd_shift_int <= + lu_d_mux_s(0) & rd_shift_int(15 downto 13) & + lu_d_mux_s(1) & rd_shift_int(11 downto 9) & + lu_d_mux_s(2) & rd_shift_int( 7 downto 5) & + lu_d_mux_s(3) & rd_shift_int( 3 downto 1); + end if; + end if; + end process; + + rd_shift_s <= rd_shift_int when shift_oc_n_s = '0' else (others=>'1'); + rs_s <= rs_int when shift_oc_n_s = '0' else (others=>'1'); +-- rs_n_s(3) <= not rs_s(3) or not rs_enable_s; +-- rs_n_s(2) <= not rs_s(2) or not rs_enable_s; +-- rs_n_s(1) <= not rs_s(1) or not rs_enable_s; +-- rs_n_s(0) <= not rs_s(0) or not rs_enable_s; + rs_n_s(3) <= rs_s(3) and rs_enable_s; + rs_n_s(2) <= rs_s(2) and rs_enable_s; + rs_n_s(1) <= rs_s(1) and rs_enable_s; + rs_n_s(0) <= rs_s(0) and rs_enable_s; + + ----------------------------------------------------------------------------- + -- Sprite VRAM + ----------------------------------------------------------------------------- + vram_a6_in_s(0) <= rd_shift_s( 0); + vram_a6_in_s(1) <= rd_shift_s( 4); + vram_a6_in_s(2) <= rd_shift_s( 8); + vram_a6_in_s(3) <= rd_shift_s(12); + vram_a6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(0), + we_n_i => vram_we_n_s, + d_i => vram_a6_in_s, + d_o => vram_a6_out_s + ); + -- + vram_b6_in_s(0) <= rd_shift_s( 1); + vram_b6_in_s(1) <= rd_shift_s( 5); + vram_b6_in_s(2) <= rd_shift_s( 9); + vram_b6_in_s(3) <= rd_shift_s(13); + vram_b6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(1), + we_n_i => vram_we_n_s, + d_i => vram_b6_in_s, + d_o => vram_b6_out_s + ); + -- + vram_c6_in_s(0) <= rd_shift_s( 2); + vram_c6_in_s(1) <= rd_shift_s( 6); + vram_c6_in_s(2) <= rd_shift_s(10); + vram_c6_in_s(3) <= rd_shift_s(14); + vram_c6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(2), + we_n_i => vram_we_n_s, + d_i => vram_c6_in_s, + d_o => vram_c6_out_s + ); + -- + vram_d6_in_s(0) <= rd_shift_s( 3); + vram_d6_in_s(1) <= rd_shift_s( 7); + vram_d6_in_s(2) <= rd_shift_s(11); + vram_d6_in_s(3) <= rd_shift_s(15); + vram_d6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(3), + we_n_i => vram_we_n_s, + d_i => vram_d6_in_s, + d_o => vram_d6_out_s + ); + -- Remap VRAM data outputs to the complete bus ------------------------------ + rd_vram_s(15) <= vram_d6_out_s(3) or rs_n_s(3); + rd_vram_s(14) <= vram_c6_out_s(3) or rs_n_s(2); + rd_vram_s(13) <= vram_b6_out_s(3) or rs_n_s(1); + rd_vram_s(12) <= vram_a6_out_s(3) or rs_n_s(0); + -- + rd_vram_s(11) <= vram_d6_out_s(2) or rs_n_s(3); + rd_vram_s(10) <= vram_c6_out_s(2) or rs_n_s(2); + rd_vram_s( 9) <= vram_b6_out_s(2) or rs_n_s(1); + rd_vram_s( 8) <= vram_a6_out_s(2) or rs_n_s(0); + -- + rd_vram_s( 7) <= vram_d6_out_s(1) or rs_n_s(3); + rd_vram_s( 6) <= vram_c6_out_s(1) or rs_n_s(2); + rd_vram_s( 5) <= vram_b6_out_s(1) or rs_n_s(1); + rd_vram_s( 4) <= vram_a6_out_s(1) or rs_n_s(0); + -- + rd_vram_s( 3) <= vram_d6_out_s(0) or rs_n_s(3); + rd_vram_s( 2) <= vram_c6_out_s(0) or rs_n_s(2); + rd_vram_s( 1) <= vram_b6_out_s(0) or rs_n_s(1); + rd_vram_s( 0) <= vram_a6_out_s(0) or rs_n_s(0); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process rd_seq + -- + -- Purpose: + -- Implements the registers saving the RDx bus. + -- + rd_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + vram_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if blank_flont_i = '0' then + -- pseudo-asynchronous clear + vram_q <= (others => '0'); + + elsif clk_en_rd_s = '1' then + if shift_oc_n_s = '0' then + -- take data from shift registers + vram_q <= rd_shift_s; + else + -- take data from VRAM + vram_q <= rd_vram_s; + end if; + end if; + end if; + end process rd_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process sig_mux + -- + -- Purpose: + -- Multiplexes the saved VRAM data to generate the four SIG outputs. + -- + sig_mux: process (vram_q, + h_i, + blank_i) + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + sig_o <= (others => '0'); + + vec_v := (h_i(1) & h_i(0)); + + if blank_i = '0' then + case vec_v is + when "00" => + sig_o(1) <= vram_q( 1); + sig_o(2) <= vram_q( 5); + sig_o(3) <= vram_q( 9); + sig_o(4) <= vram_q(13); + when "01" => + sig_o(1) <= vram_q( 2); + sig_o(2) <= vram_q( 6); + sig_o(3) <= vram_q(10); + sig_o(4) <= vram_q(14); + when "10" => + sig_o(1) <= vram_q( 3); + sig_o(2) <= vram_q( 7); + sig_o(3) <= vram_q(11); + sig_o(4) <= vram_q(15); + when "11" => + sig_o(1) <= vram_q( 0); + sig_o(2) <= vram_q( 4); + sig_o(3) <= vram_q( 8); + sig_o(4) <= vram_q(12); + when others => + null; + end case; + end if; + end process sig_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rom_sprite_a_o <= ma_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sprite_ctrl.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sprite_ctrl.vhd new file mode 100644 index 00000000..f0eaff48 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_sprite_ctrl.vhd @@ -0,0 +1,491 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ctrl.vhd,v 1.8 2005/10/10 22:02:14 arnim Exp $ +-- +-- Control logic of the Sprite module. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +library ieee; +use ieee.numeric_std.all; + +entity ladybug_sprite_ctrl is + + port ( + clk_20mhz_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + por_n_i : in std_logic; + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_i : in std_logic; + vc_d_i : in std_logic; + ha_i : in std_logic; + ha_d_i : in std_logic; + rb6_i : in std_logic; + rb7_i : in std_logic; + rc3_i : in std_logic; + rc4_i : in std_logic; + rc5_i : in std_logic; + j7_b_i : in std_logic; + j7_c_i : in std_logic; + clk_en_eck_i : in std_logic; + c_o : out std_logic_vector(10 downto 0); + clk_en_5ck_n_o : out std_logic; + clk_en_6ck_n_o : out std_logic; + clk_en_7ck_n_o : out std_logic; + s6ck_n_o : out std_logic; + s7ck_n_o : out std_logic; + clk_en_b7_p3_o : out std_logic; + e5_p8_o : out std_logic; + clk_en_e7_3_o : out std_logic; + a8_p5_n_o : out std_logic + ); + +end ladybug_sprite_ctrl; + + +architecture rtl of ladybug_sprite_ctrl is + + signal clk_5mhz_q : std_logic; + + signal a7_p5_s, + a7_p5_q : std_logic; + signal a7_p9_q : std_logic; + + signal a8_p5_q : std_logic; + + signal n4_p5_s, + n4_p5_q : std_logic; + + signal f7_ck_en_s, + f7_cl_s, + f7_qa_s, f7_qb_s, f7_qc_s, f7_qd_s, + f7_da_s, f7_db_s, f7_dc_s, f7_dd_s : std_logic_vector(2 downto 1); + + signal j5_ck_en_s, + j5_cl_s, + j5_qa_s, j5_qb_s, j5_qc_s, j5_qd_s, + j5_da_s, j5_db_s, j5_dc_s, j5_dd_s : std_logic_vector(2 downto 1); + + signal e7_ck_en_s, + e7_cl_n_s : std_logic; + signal e7_d_s, + e7_q_s, e7_q_n_s, + e7_d_out_s, e7_d_out_n_s : std_logic_vector(4 downto 1); + + signal h5_n_s : std_logic_vector(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements various sequential elements. + -- + seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_q <= '0'; + a7_p5_q <= '0'; + a7_p9_q <= '0'; + a8_p5_q <= '0'; + n4_p5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz enable into clock waveform ----------------------------- + if clk_en_5mhz_i = '1' then + clk_5mhz_q <= '1'; + elsif clk_en_5mhz_n_i = '1' then + clk_5mhz_q <= '0'; + end if; + + -- Flip-Flop A7 --------------------------------------------------------- + a7_p5_q <= a7_p5_s; + -- + if clk_en_5mhz_n_i = '1' then + a7_p9_q <= j5_qd_s(2); + end if; + + -- Flip-Flop A8 --------------------------------------------------------- + if clk_en_eck_i = '1' then + a8_p5_q <= j7_b_i nand j7_c_i; + end if; + + -- Flip-Flop N4 --------------------------------------------------------- + n4_p5_q <= n4_p5_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements various combinational signals. + -- + comb: process (a7_p5_q, + vc_i, vc_d_i, + n4_p5_q, + ha_i, ha_d_i, + f7_qd_s) + begin + -- D Input for Flip-Flop N4 ----------------------------------------------- + if a7_p5_q = '0' then + -- pseudo-asynchronous clear + n4_p5_s <= '0'; + elsif (vc_i and not vc_d_i) = '1' then + -- falling edge on VC + n4_p5_s <= '1'; + else + n4_p5_s <= n4_p5_q; + end if; + + -- D-Input for Flip-Flop A7.5 --------------------------------------------- + if (ha_i and not ha_d_i) = '1' then + -- falling edge on HA + a7_p5_s <= f7_qd_s(2); + else + a7_p5_s <= a7_p5_q; + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- F7 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + f7_cl_s(1) <= n4_p5_q and ha_i and vbl_n_i; + f7_cl_s(2) <= f7_cl_s(1); + -- + f7_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => f7_ck_en_s, + por_n_i => por_n_i, + cl_i => f7_cl_s, + qa_o => f7_qa_s, + qb_o => f7_qb_s, + qc_o => f7_qc_s, + qd_o => f7_qd_s, + da_o => f7_da_s, + db_o => f7_db_s, + dc_o => f7_dc_s, + dd_o => f7_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process f7_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in F7. + -- + f7_ck_en: process (j5_qd_s, j5_dd_s, + vbl_n_i, vbl_d_n_i, + ha_i, ha_d_i, + n4_p5_q, n4_p5_s, + f7_qd_s, f7_dd_s, + e7_q_n_s, e7_d_out_n_s, + f7_qb_s, f7_db_s) + + variable ff_q_v, ff_d_v : std_logic; + + begin + + -- combinational result based on flip-flop outputs + ff_q_v := j5_qd_s(2) or ( not ( not ( vbl_n_i and ha_i and n4_p5_q ) ) or not ( not f7_qd_s(2) nand not e7_q_n_s(1) ) ); + + -- combinational result based on flip-flop inputs + ff_d_v := j5_dd_s(2) or ( not ( not ( vbl_d_n_i and ha_d_i and n4_p5_s ) ) or not ( not f7_qd_s(2) nand not e7_d_out_n_s(1) ) ); +-- B7.3 D7.8 D7.8 F6.3 B7.6 + -- rising edge detector on B7.3 + f7_ck_en_s(1) <= not ff_q_v and ff_d_v; + + -- falling edge detector on F7.QB(1) + f7_ck_en_s(2) <= f7_qb_s(1) and not f7_db_s(1); + + end process f7_ck_en; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- J5 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + j5_cl_s(1) <= not vbl_n_i + or -- D7.6 + not( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) + or -- D7.6 + n4_p5_q; + j5_cl_s(2) <= a7_p9_q + or -- B7.8 + ( + not ( + not ( + n4_p5_q + and -- D7.8 + ha_i + and -- D7.8 + vbl_n_i + ) + ) + or -- F6.3 + not ( + not f7_qd_s(2) + nand -- B7.6 + not e7_q_n_s(1) + ) + ); + -- + j5_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => j5_ck_en_s, + por_n_i => por_n_i, + cl_i => j5_cl_s, + qa_o => j5_qa_s, + qb_o => j5_qb_s, + qc_o => j5_qc_s, + qd_o => j5_qd_s, + da_o => j5_da_s, + db_o => j5_db_s, + dc_o => j5_dc_s, + dd_o => j5_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process j5_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in J5. + -- + j5_ck_en: process (ha_i, ha_d_i, + e7_q_s, e7_d_out_s, + j5_qc_s, j5_dc_s) + begin + -- falling edge detector on F6.11 + j5_ck_en_s(1) <= -- Flip-Flop Outputs + ( + not ha_i + nand + e7_q_s(3) + ) + and not -- Flip-Flop Inputs + ( + not ha_d_i + nand + e7_d_out_s(3) + ); + + -- falling edge detector on C7.10 + j5_ck_en_s(2) <= -- Flip-Flop Outputs + ( + j5_qc_s(1) + nor + e7_q_s(2) + ) + and not -- Flip-Flop Inputs + ( + j5_dc_s(1) + nor + e7_d_out_s(2) + ); + end process j5_ck_en; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- E7 - Quad D-Type Flip-Flops with Clear + ----------------------------------------------------------------------------- + e7_d_s(1) <= not rb7_i; + e7_d_s(2) <= not ( + rb7_i + and -- D7.12 + rc5_i + and -- D7.12 + ( + not rc4_i + and -- C7.1 + not ( + not rc3_i + nor -- C6.3 + rb6_i + ) + ) + ); + e7_d_s(3) <= not e7_d_s(2) + and -- C7.4 + not a8_p5_q; + e7_d_s(4) <= '0'; + + -- This clock enable is not 100% equivalent to the schematics. + -- There, h5_n_s(4) could also generate a rising edge for E7 + -- but this is ignored here. It is believed that h5_n_s(4) acts + -- only as a clock enable/suppress for the 5 MHz clock. + -- This implementation suppresses as well a combinational feedback + -- loop from J5/1. + e7_ck_en_s <= clk_en_5mhz_i and not h5_n_s(4); + + e7_cl_n_s <= f7_qd_s(2) + or -- B7.3?? + ( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) after 20 ns; + + e7_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => e7_ck_en_s, + por_n_i => por_n_i, + cl_n_i => e7_cl_n_s, + d_i => e7_d_s, + q_o => e7_q_s, + q_n_o => e7_q_n_s, + d_o => e7_d_out_s, + d_n_o => e7_d_out_n_s + ); + + clk_en_e7_3_o <= not e7_q_s(3) and e7_d_out_s(3); + + + ----------------------------------------------------------------------------- + -- Process h5 + -- + -- Purpose: + -- Implements all functionality regarding H5. + -- + h5: process (j5_qa_s, j5_da_s, + j5_qb_s, j5_db_s, + ha_i, ha_d_i, + vbl_n_i, vbl_d_n_i, + a7_p5_q, a7_p5_s) + variable ff_q_v, ff_d_v : std_logic_vector(7 downto 0); + variable f5_p3_q_v, f5_p3_d_v : std_logic; + + ----------------------------------------------------------------------------- + -- 7445 - BCD to Decimal Decoder + ----------------------------------------------------------------------------- + function ttl_45_f(a, b, c, d : in std_logic) return + std_logic_vector is + variable idx_v : std_logic_vector( 3 downto 0); + variable vec_v : std_logic_vector(15 downto 0); + begin + vec_v := (others => '1'); + + idx_v := d & c & b & a; + vec_v(to_integer(unsigned(idx_v))) := '0'; + + return vec_v(7 downto 0); + end ttl_45_f; + + begin + -- combinational result based on flip-flop outputs + f5_p3_q_v := not a7_p5_q nand vbl_n_i; + ff_q_v := ttl_45_f(a => j5_qa_s(1), + b => j5_qb_s(1), + c => ha_i, + d => f5_p3_q_v); + -- combinational result based on flip-flop inputs + f5_p3_d_v := not a7_p5_s nand vbl_d_n_i; + ff_d_v := ttl_45_f(a => j5_da_s(1), + b => j5_db_s(1), + c => ha_d_i, + d => f5_p3_d_v); + + -- combinational output of H5 is based on flip-flop outputs + h5_n_s <= ff_q_v; + + -- clock enable for flip-flops on /5CK + clk_en_5ck_n_o <= not ff_q_v(5) and ff_d_v(5); + -- clock enable for flip-flops on /6CK + clk_en_6ck_n_o <= not ff_q_v(6) and ff_d_v(6); + -- clock enable for flip-flops on /7CK + clk_en_7ck_n_o <= not ff_q_v(7) and ff_d_v(7); + + s6ck_n_o <= ff_q_v(6); + s7ck_n_o <= ff_q_v(7); + end process h5; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + clk_en_b7_p3_o <= f7_ck_en_s(1); + e5_p8_o <= n4_p5_q + nor -- E5.8 + not ( + f7_qa_s(1) + nand -- F6.8 + f7_qb_s(1) + ); + a8_p5_n_o <= not a8_p5_q; + + c_o( 0) <= j5_qa_s(1); + c_o( 1) <= j5_qb_s(1); + c_o( 2) <= j5_qa_s(2); + c_o( 3) <= j5_qb_s(2); + c_o( 4) <= j5_qc_s(2); + c_o( 5) <= j5_qd_s(2); + c_o( 6) <= f7_qa_s(2); + c_o( 7) <= f7_qb_s(2); + c_o( 8) <= f7_qc_s(2); + c_o( 9) <= f7_qa_s(1); + c_o(10) <= f7_qb_s(1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_video_timing.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_video_timing.vhd new file mode 100644 index 00000000..58a3a818 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_video_timing.vhd @@ -0,0 +1,356 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_timing.vhd,v 1.16 2006/02/07 19:27:38 arnim Exp $ +-- +-- The Video Timing Module of Lady Bug Machine. +-- +-- It implements the horizontal and vertical timing signals including composite +-- sync information. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_video_timing is + + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + -- Horizontal Timing Interface -------------------------------------------- + h_o : out std_logic_vector(3 downto 0); + h_t_o : out std_logic_vector(3 downto 0); + hbl_o : out std_logic; + hx_o : out std_logic; + ha_d_o : out std_logic; + ha_t_rise_o : out std_logic; + -- Vertical Timing Interface ---------------------------------------------- + v_o : out std_logic_vector(3 downto 0); + v_t_o : out std_logic_vector(3 downto 0); + vc_d_o : out std_logic; + vbl_n_o : out std_logic; + vbl_d_n_o : out std_logic; + vbl_t_n_o : out std_logic; + blank_flont_o : out std_logic; + -- RBG Video Interface ---------------------------------------------------- + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic + ); + +end ladybug_video_timing; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_video_timing is + + -- horizontal timing circuit + signal h_preset : std_logic_vector(7 downto 0); + signal h_rise : std_logic_vector(7 downto 0); + signal h_do : std_logic_vector(7 downto 0); + signal h_j2_h2 : std_logic_vector(7 downto 0); + signal h_s : std_logic_vector(7 downto 0); + signal hx_q, + hx_s, + hx_n_s : std_logic; + signal hx_rise_s : std_logic; + signal hbl_q : std_logic; +-- signal hbl_n_s : std_logic; + signal hsync_n_q : std_logic; + signal h_carry_s : std_logic; + signal hd_rise_s : std_logic; + + -- vertical timing circuit + signal v_preset : std_logic_vector(7 downto 0); + signal v_rise : std_logic_vector(7 downto 0); + signal v_do : std_logic_vector(7 downto 0); + signal v_s : std_logic_vector(7 downto 0); + signal vx_q, + vx_n_s : std_logic; + signal vbl_q, + vbl_s, + vbl_n_s : std_logic; + signal vbl_t_q, + vbl_t_s, + vbl_t_n_s : std_logic; + signal vsync_n_q : std_logic; + signal v_carry_s : std_logic; + signal vc_rise_s, + vd_rise_s : std_logic; + signal vb_t_rise_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Horizontal Timing counters J2 H2 + ----------------------------------------------------------------------------- + hd_rise_s <= h_rise(3); + ha_t_rise_o <= h_rise(4); + ha_d_o <= h_do(0); + h_preset <= hx_n_s & hx_n_s & "00" & hx_n_s & "000"; + + h_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + reset_n_i => por_n_i, + load_i => h_carry_s, + preset_i => h_preset, + q_o => h_s, + co_o => h_carry_s, + rise_q_o => h_rise, + d_o => h_do + ); + + ----------------------------------------------------------------------------- + -- Process h_timing + -- + -- Purpose: + -- Implement the horizontal timing circuit. + -- + -- The original circuit has no asynchronous reset. To have a stable + -- behavior on silicon, all sequential elements are cleared with the + -- power-on reset. This assumes that the original chips power-up to + -- these values. + -- + -- See also instantiations of ttl_161. + -- + h_timing: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_q <= '0'; + hbl_q <= '0'; + hsync_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Flip-flops on 5 MHz clock -------------------------------------------- + -- HX + hx_q <= hx_s; + + -- Free running flip-flops ---------------------------------------------- + -- HBL + if (hx_q and not h_s(3)) = '1' then + -- pseudo-asynchronous preset + hbl_q <= '1'; + elsif hd_rise_s = '1' then + -- Rising edge on HD + hbl_q <= hx_q; + end if; + + -- HSYNC + if hx_q = '0' then + -- pseudo-asynchronous preset + hsync_n_q <= '1'; + elsif hd_rise_s = '1' then + -- rising edge on HD + hsync_n_q <= h_s(5); + end if; + + end if; + + end process h_timing; + -- + ----------------------------------------------------------------------------- + + hx_n_s <= not hx_q; +--hbl_n_s <= not hbl_q; + + ----------------------------------------------------------------------------- + -- Process hx_comb + -- + -- Purpose: + -- Implements the combinational logic for hx. Including rising edge + -- detection. + -- + hx_comb: process (clk_en_5mhz_i, h_carry_s, hx_q) + begin + -- default assignments + hx_s <= hx_q; + hx_rise_s <= '0'; + + -- HX + if clk_en_5mhz_i = '1' then + if h_carry_s = '1' then + hx_s <= not hx_q; + + -- flag rising edge of hx_q + if hx_q = '0' then + hx_rise_s <= '1'; + end if; + end if; + end if; + + end process hx_comb; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Vertical Timing counters E5 E2 + ----------------------------------------------------------------------------- + vb_t_rise_s <= v_rise(5); + vd_rise_s <= v_rise(3); + vc_rise_s <= v_rise(2); + vc_d_o <= v_do(2); + v_preset <= vx_n_s & vx_n_s & vx_n_s & vx_q & vx_n_s & '0' & vx_n_s & '0'; + + v_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => hx_rise_s, + reset_n_i => por_n_i, + load_i => v_carry_s, + preset_i => v_preset, + q_o => v_s, + co_o => v_carry_s, + rise_q_o => v_rise, + d_o => v_do + ); + + ----------------------------------------------------------------------------- + -- Process v_timing + -- + -- Purpose: + -- Implement the vertical timing circuit. + -- + -- See process h_timing for reset discussion. + -- + v_timing: process (clk_20mhz_i, por_n_i) + variable preset_v : boolean; + begin + if por_n_i = '0' then + vx_q <= '0'; + vbl_q <= '0'; + vsync_n_q <= '1'; + vbl_t_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Free running flip-flops ---------------------------------------------- + -- VX + if hx_rise_s = '1' then + if v_carry_s = '1' then + vx_q <= vx_n_s; + end if; + end if; + + -- VSYNC + if vc_rise_s = '1' then + -- rising edge on VC + vsync_n_q <= not (v_s(7) and v_s(6) and v_s(5) and v_s(4) and v_s(3) and vx_n_s); + end if; + + -- VBL + vbl_q <= vbl_s; + + -- VBL' + vbl_t_q <= vbl_t_s; + + end if; + end process v_timing; + -- + ----------------------------------------------------------------------------- + + vx_n_s <= not vx_q; + vbl_n_s <= not vbl_q; + vbl_t_n_s <= not vbl_t_q; + + + ----------------------------------------------------------------------------- + -- Process vbl_comb + -- + -- Purpose: + -- Combinational logic for vbl_q and vbl_t_q. + -- + vbl_comb: process (v_s, vb_t_rise_s, vd_rise_s, vx_q, vbl_q, vbl_t_q) + variable preset_v : boolean; + begin + preset_v := (v_s(5) and v_s(6) and v_s(7)) = '1'; + -- VBL + vbl_s <= vbl_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_s <= '1'; + elsif vb_t_rise_s = '1' then + -- rising edge on VB' + vbl_s <= vx_q; + end if; + + -- VBL' + vbl_t_s <= vbl_t_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_t_s <= '1'; + elsif vd_rise_s = '1' then + -- rising edge on VD + vbl_t_s <= vx_q; + end if; + + end process vbl_comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + h_o <= h_s(3 downto 0); + h_t_o <= h_s(7 downto 4); + hbl_o <= hbl_q; + hx_o <= hx_q; + v_o <= v_s(3 downto 0); + v_t_o <= v_s(7 downto 4); + vbl_n_o <= vbl_n_s; + vbl_t_n_o <= vbl_t_n_s; + vbl_d_n_o <= not vbl_s; + hsync_n_o <= hsync_n_q; + vsync_n_o <= vsync_n_q; + comp_sync_n_o <= not hsync_n_q xor vsync_n_q; + + -- I have no idea why there is an additional wire called BLANK FLONT. + -- From the schematics, it is the same as /VBL (just buffered). + blank_flont_o <= vbl_n_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_video_unit.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_video_unit.vhd new file mode 100644 index 00000000..96d58e5f --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ladybug_video_unit.vhd @@ -0,0 +1,240 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_unit.vhd,v 1.22 2006/02/07 00:44:35 arnim Exp $ +-- +-- The Video Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_video_unit is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_video_o : out std_logic_vector( 7 downto 0); + vc_o : out std_logic; + vbl_tick_n_o : out std_logic; + vbl_buf_o : out std_logic; + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_video_unit; + +architecture struct of ladybug_video_unit is + + signal h_s, + h_t_s : std_logic_vector(3 downto 0); + signal ha_d_s, + ha_t_rise_s : std_logic; + signal hbl_s : std_logic; + signal hx_s : std_logic; + + signal v_s, + v_t_s : std_logic_vector(3 downto 0); + signal vc_d_s : std_logic; + signal vbl_n_s, + vbl_d_n_s : std_logic; + + signal blank_flont_s : std_logic; + + signal d_from_char_s : std_logic_vector(7 downto 0); + + signal blank_s : std_logic; + signal crg_s : std_logic_vector(5 downto 1); + + signal sig_s : std_logic_vector(4 downto 1); + + signal comp_sync_n : std_logic; + +begin + comp_sync_n_o <= comp_sync_n and vbl_n_s; + vbl_buf_o <= not vbl_n_s; + ----------------------------------------------------------------------------- + -- Horizontal and Vertical Timing Generator + ----------------------------------------------------------------------------- + timing_b : entity work.ladybug_video_timing + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + h_o => h_s, + h_t_o => h_t_s, + hbl_o => hbl_s, + hx_o => hx_s, + ha_d_o => ha_d_s, + ha_t_rise_o => ha_t_rise_s, + v_o => v_s, + v_t_o => v_t_s, + vc_d_o => vc_d_s, + vbl_n_o => vbl_n_s, + vbl_d_n_o => vbl_d_n_s, + vbl_t_n_o => vbl_tick_n_o, + blank_flont_o => blank_flont_s, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n + ); + vc_o <= v_s(2); + + + ----------------------------------------------------------------------------- + -- Character Module + ----------------------------------------------------------------------------- + char_b : entity work.ladybug_char + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_4mhz_i => clk_en_4mhz_i, + cs10_n_i => cs10_n_i, + cs13_n_i => cs13_n_i, + a_i => a_i, + rd_n_i => rd_n_i, + wr_n_i => wr_n_i, + wait_n_o => wait_n_o, + d_from_cpu_i => d_from_cpu_i, + d_from_char_o => d_from_char_s, + h_i => h_s, + h_t_i => h_t_s, + ha_t_rise_i => ha_t_rise_s, + hx_i => hx_s, + v_i => v_s, + v_t_i => v_t_s, + hbl_i => hbl_s, + blank_flont_i => blank_flont_s, + blank_o => blank_s, + vblank_o => vblank_o, + hblank_o => hblank_o, + crg_o => crg_s, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i + ); + + + ----------------------------------------------------------------------------- + -- Sprite Module + ----------------------------------------------------------------------------- + sprite_b : entity work.ladybug_sprite + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_10mhz_i => clk_en_10mhz_i, + clk_en_10mhz_n_i => clk_en_10mhz_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + cs7_n_i => cs7_n_i, + a_i => a_i(9 downto 0), + d_from_cpu_i => d_from_cpu_i, + h_i => h_s, + h_t_i => h_t_s, + hx_i => hx_s, + ha_d_i => ha_d_s, + v_i => v_s, + v_t_i => v_t_s, + vbl_n_i => vbl_n_s, + vbl_d_n_i => vbl_d_n_s, + vc_d_i => vc_d_s, + blank_flont_i => blank_flont_s, + blank_i => blank_s, + sig_o => sig_s, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + + ----------------------------------------------------------------------------- + -- RGB Generator + ----------------------------------------------------------------------------- + rgb_b : entity work.ladybug_rgb + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + crg_i => crg_s, + sig_i => sig_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o + ); + + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_from_video_o <= d_from_char_s + when cs13_n_i = '0' else + (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/mist_io.v b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/osd.v b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/pll.qip b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/pll.v b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/pll.v new file mode 100644 index 00000000..65715540 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 20, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/scandoubler.v b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/ladybug_sound_unit.vhd new file mode 100644 index 00000000..23ad2a6a --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/ladybug_sound_unit.vhd @@ -0,0 +1,143 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sound_unit.vhd,v 1.4 2006/06/16 22:41:37 arnim Exp $ +-- +-- Sound Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_sound_unit is + + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + por_n_i : in std_logic; + cs11_n_i : in std_logic; + cs12_n_i : in std_logic; + wr_n_i : in std_logic; + d_from_cpu_i : in std_logic_vector(7 downto 0); + sound_wait_n_o : out std_logic; + audio_o : out signed(7 downto 0) + ); + +end ladybug_sound_unit; + +architecture struct of ladybug_sound_unit is + + signal ready_b1_s, + ready_c1_s : std_logic; + + signal aout_b1_s, + aout_c1_s : signed(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip B1 + ----------------------------------------------------------------------------- + snd_b1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs11_n_i, + we_n_i => wr_n_i, + ready_o => ready_b1_s, + d_i => d_from_cpu_i, + aout_o => aout_b1_s + ); + + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip C1 + ----------------------------------------------------------------------------- + snd_c1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs12_n_i, + we_n_i => wr_n_i, + ready_o => ready_c1_s, + d_i => d_from_cpu_i, + aout_o => aout_c1_s + ); + + + ----------------------------------------------------------------------------- + -- Process mix + -- + -- Purpose: + -- Mix the digital audio of the two SN76489 instances. + -- Additional care is taken to avoid audio overfow/clipping. + -- + mix: process (aout_b1_s, + aout_c1_s) + variable sum_v : signed(8 downto 0); + begin + sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9); + + if sum_v > 127 then + audio_o <= to_signed(127, 8); + elsif sum_v < -128 then + audio_o <= to_signed(-128, 8); + else + audio_o <= RESIZE(sum_v, 8); + end if; + + end process mix; + -- + ----------------------------------------------------------------------------- + + + sound_wait_n_o <= ready_b1_s and ready_c1_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING new file mode 100644 index 00000000..60549be5 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README new file mode 100644 index 00000000..33630144 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/README @@ -0,0 +1,143 @@ + +An SN76489AN Compatible Implementation in VHDL +============================================== +Version: $Date: 2006/06/18 19:28:40 $ + +Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +See the file COPYING. + + +Integration +----------- + +The sn76489 design exhibits all interface signals as the original chip. It +only differs in the audio data output which is provided as an 8 bit signed +vector instead of an analog output pin. + + generic ( + clock_div_16_g : integer := 1 + -- Set to '1' when operating the design in SN76489 mode. The primary clock + -- input is divided by 16 in this variant. The data sheet mentions the + -- SN76494 which contains a divide-by-2 clock input stage. Set the generic + -- to '0' to enable this mode. + ); + port ( + clock_i : in std_logic; + -- Primary clock input + -- Drive with the target frequency or any integer multiple of it. + + clock_en_i : in std_logic; + -- Clock enable + -- A '1' on this input qualifies a valid rising edge on clock_i. A '0' + -- disables the next rising clock edge, effectivley halting the design + -- until the next enabled rising clock edge. + -- Can be used to run the core at lower frequencies than applied on + -- clock_i. + + res_n_i : in std_logic; + -- Asynchronous low active reset input. + -- Sets all sequential elements to a known state. + + ce_n_i : in std_logic; + -- Chip enable, low active. + + we_n_i : in std_logic; + -- Write enable, low active. + + ready_o : out std_logic; + -- Ready indication to microprocessor. + + d_i : in std_logic_vector(0 to 7); + -- Data input + -- MSB 0 ... 7 LSB + + aout_o : out signed(0 to 7) + -- Audio output, signed vector + -- MSB/SIGN 0 ... 7 LSB + ); + + +Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the +MSB and bit 7 to be the LSB. This has been implemented according to TI's data +sheet, thus all register/data format figures apply 1:1 for this design. +Many systems will flip the system data bus bit wise before it is connected to +this PSG. This is simply achieved with the following VHDL construct: + + signal data_s : std_logic_vector(7 downto 0); + + ... + d_i => data_s, + ... + +d_i and data_s will be assigned from left to right, resulting in the expected +bit assignment: + + d_i data_s + 0 7 + 1 6 + ... + 6 1 + 7 0 + + +As this design is fully synchronous, care has to be taken when the design +replaces an SN76489 in asynchronous mode. No problems are expected when +interfacing the code to other synchronous components. + + +Design Hierarchy +---------------- + + sn76489_top + | + +-- sn76489_latch_ctrl + | + +-- sn76489_clock_div + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + \-- sn76489_noise + | + \-- sn76489_attentuator + +Resulting compilation sequence: + + sn76489_comp_pack-p.vhd + sn76489_top.vhd + sn76489_latch_ctrl.vhd + sn76489_latch_ctrl-c.vhd + sn76489_clock_div.vhd + sn76489_clock_div-c.vhd + sn76489_attenuator.vhd + sn76489_attenuator-c.vhd + sn76489_tone.vhd + sn76489_tone-c.vhd + sn76489_noise.vhd + sn76489_noise-c.vhd + sn76489_top-c.vhd + +Skip the files containing VHDL configurations when analyzing the code for +synthesis. + + +References +---------- + +* TI Data sheet SN76489.pdf + ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf + +* John Kortink's article on the SN76489: + http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ + +* Maxim's "SN76489 notes" in + http://www.smspower.org/maxim/docs/SN76489.txt diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd new file mode 100644 index 00000000..444064e5 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $ +-- +-- Attenuator Module +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_attenuator is + + port ( + attenuation_i : in std_logic_vector(0 to 3); + factor_i : in signed(0 to 1); + product_o : out signed(0 to 7) + ); + +end sn76489_attenuator; + + +architecture rtl of sn76489_attenuator is + +begin + + ----------------------------------------------------------------------------- + -- Process attenuate + -- + -- Purpose: + -- Determine the attenuation and generate the resulting product. + -- + -- The maximum attenuation value is 31 which corresponds to volume off. + -- As described in the data sheet, the maximum "playing" attenuation is + -- 28 = 16 + 8 + 4 + -- + -- The table for the volume constants is derived from the following + -- formula (each step is 2dB voltage): + -- v(0) = 31 + -- v(n+1) = v(n) * 0.79432823 + -- + attenuate: process (attenuation_i, + factor_i) + + type volume_t is array (natural range 0 to 15) of natural; + constant volume_c : volume_t := + (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0); + + variable attenuation_v : unsigned(attenuation_i'range); + variable volume_v : signed(product_o'range); + + begin + + attenuation_v := unsigned(attenuation_i); + + -- volume look-up table + volume_v := to_signed(volume_c(to_integer(attenuation_v)), + product_o'length); + + -- this replaces a multiplier and consumes a bit fewer + -- resources + case to_integer(factor_i) is + when +1 => + product_o <= volume_v; + when -1 => + product_o <= -volume_v; + when others => + product_o <= (others => '0'); + end case; + + end process attenuate; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd new file mode 100644 index 00000000..eab86beb --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $ +-- +-- Clock Divider Circuit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_clock_div is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + clk_en_o : out boolean + ); + +end sn76489_clock_div; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_clock_div is + + signal cnt_s, + cnt_q : unsigned(3 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential counter element. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + cnt_q <= (others => '0'); + elsif clock_i'event and clock_i = '1' then + cnt_q <= cnt_s; + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational counter logic. + -- + comb: process (clock_en_i, + cnt_q) + begin + -- default assignments + cnt_s <= cnt_q; + clk_en_o <= false; + + if clock_en_i = '1' then + + if cnt_q = 0 then + clk_en_o <= true; + + if clock_div_16_g = 1 then + cnt_s <= to_unsigned(15, cnt_q'length); + elsif clock_div_16_g = 0 then + cnt_s <= to_unsigned( 1, cnt_q'length); + else + -- pragma translate_off + assert false + report "Generic clock_div_16_g must be either 0 or 1." + severity failure; + -- pragma translate_on + end if; + + else + cnt_s <= cnt_q - 1; + + end if; + + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd new file mode 100644 index 00000000..789720c2 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd @@ -0,0 +1,138 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Latch Control Unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_latch_ctrl is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector(0 to 7); + ready_o : out std_logic; + tone1_we_o : out boolean; + tone2_we_o : out boolean; + tone3_we_o : out boolean; + noise_we_o : out boolean; + r2_o : out std_logic + ); + +end sn76489_latch_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_latch_ctrl is + + signal reg_q : std_logic_vector(0 to 2); + signal we_q : boolean; + signal ready_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + reg_q <= (others => '0'); + we_q <= false; + ready_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + -- READY Flag Output ---------------------------------------------------- + if ready_q = '0' and we_q then + if clk_en_i then + -- assert READY when write access happened + ready_q <= '1'; + end if; + elsif ce_n_i = '1' then + -- deassert READY when access has finished + ready_q <= '0'; + end if; + + -- Register Selection --------------------------------------------------- + if ce_n_i = '0' and we_n_i = '0' then + if clk_en_i then + if d_i(0) = '1' then + reg_q <= d_i(1 to 3); + end if; + we_q <= true; + end if; + else + we_q <= false; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + tone1_we_o <= reg_q(0 to 1) = "00" and we_q; + tone2_we_o <= reg_q(0 to 1) = "01" and we_q; + tone3_we_o <= reg_q(0 to 1) = "10" and we_q; + noise_we_o <= reg_q(0 to 1) = "11" and we_q; + + r2_o <= reg_q(2); + + ready_o <= ready_q + when ce_n_i = '0' else + '1'; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd new file mode 100644 index 00000000..688bdd56 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_noise.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Noise Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_noise is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + tone3_ff_i : in std_logic; + noise_o : out signed(0 to 7) + ); + +end sn76489_noise; + +architecture rtl of sn76489_noise is + + signal nf_q : std_logic_vector(0 to 1); + signal fb_q : std_logic; + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 6); + signal freq_ff_q : std_logic; + + signal shift_source_s, + shift_source_q : std_logic; + signal shift_rise_edge_s : boolean; + + signal lfsr_q : std_logic_vector(0 to 15); + + signal freq_s : signed(0 to 1); + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + nf_q <= (others => '0'); + fb_q <= '0'; + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to control register + -- both access types can write to the control register! + nf_q <= d_i(6 to 7); + fb_q <= d_i(5); + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- reload frequency counter according to NF setting + case nf_q is + when "00" => + freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length); + when "01" => + freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length); + when "10" => + freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length); + when others => + null; + end case; + + freq_ff_q <= not freq_ff_q; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Multiplex the source of the LFSR's shift enable + ----------------------------------------------------------------------------- + shift_source_s <= tone3_ff_i + when nf_q = "11" else + freq_ff_q; + + ----------------------------------------------------------------------------- + -- Process rise_edge + -- + -- Purpose: + -- Detect the rising edge of the selected LFSR shift source. + -- + rise_edge: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + shift_source_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + shift_source_q <= shift_source_s; + end if; + end if; + end process rise_edge; + -- + ----------------------------------------------------------------------------- + + -- detect rising edge on shift source + shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1'; + + + ----------------------------------------------------------------------------- + -- Process lfsr + -- + -- Purpose: + -- Implements the LFSR that generates noise. + -- Note: This implementation shifts the register right, i.e. from index + -- 15 towards 0 => bit 15 is the input, bit 0 is the output + -- + -- Tapped bits according to MAME's sn76496.c, implemented in function + -- lfsr_tapped_f. + -- + lfsr: process (clock_i, res_n_i) + + function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is + constant tapped_bits_c : std_logic_vector(0 to 15) + -- tapped bits are 0, 2, 15 + := "1010000000000001"; + variable parity_v : std_logic; + begin + parity_v := '0'; + + for idx in lfsr'low to lfsr'high loop + parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx)); + end loop; + + return parity_v; + end; + + begin + if res_n_i = '0' then + -- reset LFSR to "0000000000000001" + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if we_i and r2_i = '0' then + -- write to noise register + -- -> reset LFSR + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif shift_rise_edge_s then + + -- shift LFSR left towards MSB + for idx in lfsr_q'right-1 downto lfsr_q'left loop + lfsr_q(idx) <= lfsr_q(idx+1); + end loop; + + -- determine input bit + if fb_q = '0' then + -- "Periodic" Noise + -- -> input to LFSR is output + lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left); + else + -- "White" Noise + -- -> input to LFSR is parity of tapped bits + lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q); + end if; + + end if; + + end if; + end if; + end process lfsr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map output of LFSR to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when lfsr_q(0) = '1' else + to_signed( 0, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => noise_o + ); + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd new file mode 100644 index 00000000..3658efcc --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_tone.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $ +-- +-- Tone Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_tone is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + ff_o : out std_logic; + tone_o : out signed(0 to 7) + ); + +end sn76489_tone; + +architecture rtl of sn76489_tone is + + signal f_q : std_logic_vector(0 to 9); + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 9); + signal freq_ff_q : std_logic; + + signal freq_s : signed(0 to 1); + + function all_zero(a : in std_logic_vector) return boolean is + variable result_v : boolean; + begin + result_v := true; + + for idx in a'low to a'high loop + if a(idx) /= '0' then + result_v := false; + end if; + end loop; + + return result_v; + end; + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + f_q <= (others => '0'); + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to frequency register + if d_i(0) = '0' then + f_q(0 to 5) <= d_i(2 to 7); + else + f_q(6 to 9) <= d_i(4 to 7); + end if; + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- update counter from frequency register + freq_cnt_q <= unsigned(f_q); + + -- and toggle the frequency flip-flop if enabled + if not all_zero(f_q) then + freq_ff_q <= not freq_ff_q; + else + -- if frequency setting is 0, then keep flip-flop at +1 + freq_ff_q <= '1'; + end if; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map frequency flip-flop to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when freq_ff_q = '1' else + to_signed(-1, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => tone_o + ); + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + ff_o <= freq_ff_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd new file mode 100644 index 00000000..c26d0e1a --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/sound/sn76489/sn76489_top.vhd @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $ +-- +-- Chip Toplevel +-- +-- References: +-- +-- * TI Data sheet SN76489.pdf +-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf +-- +-- * John Kortink's article on the SN76489: +-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ +-- +-- * Maxim's "SN76489 notes" in +-- http://www.smspower.org/maxim/docs/SN76489.txt +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ieee; +use ieee.numeric_std.all; + +entity sn76489_top is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + ready_o : out std_logic; + d_i : in std_logic_vector(0 to 7); + aout_o : out signed(0 to 7) + ); + +end sn76489_top; + +architecture struct of sn76489_top is + + signal clk_en_s : boolean; + + signal tone1_we_s, + tone2_we_s, + tone3_we_s, + noise_we_s : boolean; + signal r2_s : std_logic; + + signal tone1_s, + tone2_s, + tone3_s, + noise_s : signed(0 to 7); + + signal tone3_ff_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock Divider + ----------------------------------------------------------------------------- + clock_div_b : entity work.sn76489_clock_div + generic map ( + clock_div_16_g => clock_div_16_g + ) + port map ( + clock_i => clock_i, + clock_en_i => clock_en_i, + res_n_i => res_n_i, + clk_en_o => clk_en_s + ); + + + ----------------------------------------------------------------------------- + -- Latch Control = CPU Interface + ----------------------------------------------------------------------------- + latch_ctrl_b : entity work.sn76489_latch_ctrl + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + ce_n_i => ce_n_i, + we_n_i => we_n_i, + d_i => d_i, + ready_o => ready_o, + tone1_we_o => tone1_we_s, + tone2_we_o => tone2_we_s, + tone3_we_o => tone3_we_s, + noise_we_o => noise_we_s, + r2_o => r2_s + ); + + + ----------------------------------------------------------------------------- + -- Tone Channel 1 + ----------------------------------------------------------------------------- + tone1_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone1_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone1_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 2 + ----------------------------------------------------------------------------- + tone2_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone2_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone2_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 3 + ----------------------------------------------------------------------------- + tone3_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone3_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => tone3_ff_s, + tone_o => tone3_s + ); + + ----------------------------------------------------------------------------- + -- Noise Channel + ----------------------------------------------------------------------------- + noise_b : entity work.sn76489_noise + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => noise_we_s, + d_i => d_i, + r2_i => r2_s, + tone3_ff_i => tone3_ff_s, + noise_o => noise_s + ); + + + aout_o <= tone1_s + tone2_s + tone3_s + noise_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/spram.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/spram.vhd new file mode 100644 index 00000000..fa4a1fd7 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/spram.vhd @@ -0,0 +1,84 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + widthad_a : natural; + width_a : natural := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ttl_175.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ttl_175.vhd new file mode 100644 index 00000000..b6459332 --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ttl_175.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74175 - Quad D-Type Flip-Flops with Clear +-- +-- $Id: ttl_175.vhd,v 1.5 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_175 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + por_n_i : in std_logic; + cl_n_i : in std_logic; + d_i : in std_logic_vector(4 downto 1); + q_o : out std_logic_vector(4 downto 1); + q_n_o : out std_logic_vector(4 downto 1); + d_o : out std_logic_vector(4 downto 1); + d_n_o : out std_logic_vector(4 downto 1) + ); + +end ttl_175; + + +architecture rtl of ttl_175 is + + signal flops_q, + flops_s : std_logic_vector(4 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process flops + -- + -- Purpose: + -- Implement the sequential elements. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_n_i. + -- + flops: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + flops_q <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + flops_q <= flops_s; + end if; + end process flops; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational logic. + -- + comb: process (flops_q, + cl_n_i, + d_i, + ck_en_i) + begin + -- default assignments + flops_s <= flops_q; + + if cl_n_i = '1' then + if ck_en_i = '1' then + flops_s <= d_i; + end if; + + else + -- pseudo-asynchronous clear + flops_s <= (others => '0'); + end if; + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + q_o <= flops_q; + q_n_o <= not flops_q; + d_o <= flops_s; + d_n_o <= not flops_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ttl_393.vhd b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ttl_393.vhd new file mode 100644 index 00000000..3ef25d4b --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/ttl_393.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74LS393 - Dual 4-Bit Binary Counter +-- +-- $Id: ttl_393.vhd,v 1.3 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_393 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic_vector(2 downto 1); + por_n_i : in std_logic; + cl_i : in std_logic_vector(2 downto 1); + qa_o : out std_logic_vector(2 downto 1); + qb_o : out std_logic_vector(2 downto 1); + qc_o : out std_logic_vector(2 downto 1); + qd_o : out std_logic_vector(2 downto 1); + da_o : out std_logic_vector(2 downto 1); + db_o : out std_logic_vector(2 downto 1); + dc_o : out std_logic_vector(2 downto 1); + dd_o : out std_logic_vector(2 downto 1) + ); + +end ttl_393; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ttl_393 is + + type cnt_q_t is array (natural range 2 downto 1) of unsigned(3 downto 0); + type cnt_d_t is array (natural range 2 downto 1) of unsigned(4 downto 0); + signal cnt_q : cnt_q_t; + signal cnt_s : cnt_d_t; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the flip-flops. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_i. + -- + seq: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + cnt_q(1) <= (others => '0'); + cnt_q(2) <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + cnt_q(1) <= cnt_s(1)(3 downto 0); + cnt_q(2) <= cnt_s(2)(3 downto 0); + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process adder + -- + -- Purpose: + -- Implements the adder. + -- + adder: process (ck_en_i, + cl_i, + cnt_q) + begin + for idx in 2 downto 1 loop + cnt_s(idx) <= '0' & cnt_q(idx); + + if cl_i(idx) = '0' then + if ck_en_i(idx) = '1' then + -- increment upon enable + cnt_s(idx) <= ('0' & cnt_q(idx)) + 1; + end if; + + else + -- pseudo-asynchronous clear + cnt_s(idx) <= (others => '0'); + end if; + end loop; + end process adder; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + qa_o(1) <= cnt_q(1)(0); + qb_o(1) <= cnt_q(1)(1); + qc_o(1) <= cnt_q(1)(2); + qd_o(1) <= cnt_q(1)(3); + qa_o(2) <= cnt_q(2)(0); + qb_o(2) <= cnt_q(2)(1); + qc_o(2) <= cnt_q(2)(2); + qd_o(2) <= cnt_q(2)(3); + da_o(1) <= cnt_s(1)(0); + db_o(1) <= cnt_s(1)(1); + dc_o(1) <= cnt_s(1)(2); + dd_o(1) <= cnt_s(1)(3); + da_o(2) <= cnt_s(2)(0); + db_o(2) <= cnt_s(2)(1); + dc_o(2) <= cnt_s(2)(2); + dd_o(2) <= cnt_s(2)(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/video_mixer.sv b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Ladybug Hardware/CosmicAvenger_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.qpf b/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.qpf new file mode 100644 index 00000000..d654a810 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Dorodon" diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf b/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf new file mode 100644 index 00000000..99c8897e --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.qsf @@ -0,0 +1,206 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:02:22 November 16, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Dorodon_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd +set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_timing.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rgb.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_res.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rams.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_machine.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_gpio.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_dip_pack.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_cpu_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_counter.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_clk.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Dorodon.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TOP_LEVEL_ENTITY Dorodon + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(CosmicAvenger) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(CosmicAvenger) +# ------------------- +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.srf b/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/Dorodon.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/README.txt b/Arcade/Ladybug Hardware/Dorodon_MiST/README.txt new file mode 100644 index 00000000..6c7fb60e --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Dorodon port to MiST by Gehstock +-- 14 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Lady Bug hardware +-- Unknown Author on Papilio Plus board. +--------------------------------------------------------------------------------- +-- +-- +-- Only controls are rotated on VGA output. +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + + +ToDo : Sound diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/Release/Dorodon.rbf b/Arcade/Ladybug Hardware/Dorodon_MiST/Release/Dorodon.rbf new file mode 100644 index 00000000..76f2ff7f Binary files /dev/null and b/Arcade/Ladybug Hardware/Dorodon_MiST/Release/Dorodon.rbf differ diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/clean.bat b/Arcade/Ladybug Hardware/Dorodon_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv new file mode 100644 index 00000000..53dc7473 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/Dorodon.sv @@ -0,0 +1,194 @@ +//============================================================================ +// Arcade: Dorodon +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Dorodon +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Dorodon;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire signed[7:0] audio_s; +reg [6:0] audio; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(440), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_vid), + .ce_pix_actual(ce_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? {r} : "0"), + .G(blankn ? {g&g} : "00"), + .B(blankn ? {b} : "0"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire blankn = ~(hblank | vblank); + + + +//condition ? if true : if false +ladybugt ladybugt +( + .CLK_IN(clk_sys), + .I_RESET(status[0] | status[6] | buttons[1]), + .O_PIXCE(ce_vid), + + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_VSYNC(vs), + .O_HSYNC(hs), + .O_VBLANK(vblank), + .O_HBLANK(hblank), + + .O_AUDIO(audio_s), + + .but_coin_s(~{1'b0,m_coin}), + .but_fire_s(~{1'b0,m_fire}), + .but_bomb_s(~{1'b0,m_bomb}), + .but_tilt_s(~{1'b0,1'b0}), + .but_select_s(~{m_start2,m_start1}), + .but_up_s(~{1'b0,m_up}), + .but_down_s(~{1'b0,m_down}), + .but_left_s(~{1'b0,m_left}), + .but_right_s(~{1'b0,m_right}) +); + +assign audio = audio_s; + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_1.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_1.vhd new file mode 100644 index 00000000..dc8bb30e --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_1.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_1 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"94",X"83",X"A7",X"00",X"F3",X"FC",X"F4",X"00",X"D5",X"E3",X"28",X"00",X"67",X"D3",X"15", + X"00",X"3F",X"CF",X"7F",X"00",X"F7",X"FA",X"F8",X"00",X"F1",X"F8",X"FA",X"00",X"F8",X"F3",X"F2"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_2.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_2.vhd new file mode 100644 index 00000000..35c1596b --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_2.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_2 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FF",X"BB",X"4E",X"21",X"9E",X"DB",X"DE",X"1E",X"9E",X"4F",X"DE",X"10",X"00",X"FF",X"90",X"FF", + X"21",X"21",X"21",X"21",X"90",X"00",X"00",X"00",X"90",X"DE",X"9E",X"00",X"DE",X"BB",X"1E",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_3.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_3.vhd new file mode 100644 index 00000000..a731ff5c --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_10_3.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_3 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"3A",X"3A",X"3A",X"3A",X"28",X"28",X"38",X"38", + X"08",X"08",X"38",X"38",X"20",X"20",X"38",X"38",X"20",X"20",X"38",X"38",X"3E",X"3E",X"3E",X"3E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_decrypt.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_decrypt.vhd new file mode 100644 index 00000000..43b4ae55 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/prom_decrypt.vhd @@ -0,0 +1,63 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity prom_decrypt is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(7 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of prom_decrypt is + + + type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"F1",x"3F",x"86",x"4F",x"66",x"07",x"73", -- 0x0000 + x"71",x"64",x"A7",x"59",x"2B",x"56",x"FB",x"8B", -- 0x0008 + x"8F",x"B6",x"9E",x"9D",x"04",x"11",x"BC",x"80", -- 0x0010 + x"12",x"CB",x"18",x"5D",x"D2",x"7A",x"85",x"75", -- 0x0018 + x"B5",x"BE",x"7E",x"05",x"6E",x"3E",x"D5",x"4B", -- 0x0020 + x"2E",x"52",x"15",x"84",x"38",x"6A",x"6C",x"53", -- 0x0028 + x"FA",x"C8",x"08",x"B8",x"D4",x"E9",x"5C",x"22", -- 0x0030 + x"1D",x"49",x"BD",x"AD",x"46",x"1F",x"E1",x"0A", -- 0x0038 + x"19",x"5B",x"41",x"45",x"4A",x"2A",x"B4",x"4D", -- 0x0040 + x"57",x"90",x"8E",x"3A",x"BB",x"9B",x"E4",x"29", -- 0x0048 + x"8A",x"EB",x"AA",x"F0",x"CE",x"EE",x"88",x"5F", -- 0x0050 + x"33",x"31",x"C6",x"60",x"3C",x"9A",x"3D",x"B7", -- 0x0058 + x"63",x"6D",x"AB",x"62",x"E3",x"78",x"E5",x"B9", -- 0x0060 + x"EF",x"5E",x"7B",x"83",x"94",x"E6",x"D6",x"A1", -- 0x0068 + x"D9",x"36",x"47",x"3B",x"C4",x"DF",x"21",x"0C", -- 0x0070 + x"14",x"E7",x"C3",x"1A",x"1C",x"28",x"4C",x"9C", -- 0x0078 + x"50",x"40",x"91",x"55",x"D8",x"A4",x"76",x"9F", -- 0x0080 + x"98",x"10",x"6B",x"2F",x"A3",x"43",x"39",x"B1", -- 0x0088 + x"42",x"72",x"7D",x"65",x"03",x"8D",x"F2",x"F5", -- 0x0090 + x"69",x"27",x"0D",x"CA",x"CF",x"1B",x"35",x"EC", -- 0x0098 + x"A2",x"F7",x"93",x"70",x"CD",x"68",x"97",x"2D", -- 0x00A0 + x"37",x"F9",x"AE",x"26",x"96",x"E8",x"48",x"99", -- 0x00A8 + x"95",x"D7",x"B0",x"06",x"DC",x"C9",x"ED",x"87", -- 0x00B0 + x"7F",x"B3",x"17",x"A0",x"0F",x"25",x"DB",x"DE", -- 0x00B8 + x"23",x"74",x"79",x"89",x"B2",x"FC",x"24",x"13", -- 0x00C0 + x"81",x"8C",x"D3",x"C5",x"BF",x"A6",x"16",x"44", -- 0x00C8 + x"0B",x"34",x"F8",x"D1",x"0E",x"E0",x"09",x"EA", -- 0x00D0 + x"02",x"DD",x"92",x"F4",x"C1",x"BA",x"32",x"D0", -- 0x00D8 + x"7C",x"2C",x"FD",x"F3",x"61",x"A5",x"CC",x"DA", -- 0x00E0 + x"5A",x"67",x"30",x"6F",x"82",x"20",x"AF",x"54", -- 0x00E8 + x"AC",x"E2",x"1E",x"C2",x"FE",x"A9",x"58",x"01", -- 0x00F0 + x"77",x"C0",x"4E",x"C7",x"A8",x"51",x"F6",x"FF" -- 0x00F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; + + diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_char_l.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_char_l.vhd new file mode 100644 index 00000000..105ec742 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_char_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"38",X"7C",X"86",X"82",X"C2",X"7C",X"38",X"00",X"00",X"02",X"42",X"FE",X"FE",X"02",X"02", + X"00",X"46",X"CE",X"9E",X"9A",X"BA",X"F2",X"62",X"00",X"04",X"86",X"92",X"B2",X"F2",X"DE",X"8C", + X"00",X"18",X"38",X"68",X"C8",X"FE",X"FE",X"08",X"00",X"E4",X"E6",X"A2",X"A2",X"A2",X"BE",X"1C", + X"00",X"3C",X"7E",X"D2",X"92",X"92",X"9E",X"0C",X"00",X"C0",X"C0",X"8E",X"9E",X"B0",X"E0",X"C0", + X"00",X"6C",X"F2",X"B2",X"9A",X"9A",X"6E",X"0C",X"00",X"60",X"F2",X"92",X"92",X"96",X"FC",X"78", + X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",X"FE",X"FE",X"92",X"92",X"92",X"FE",X"6C", + X"00",X"38",X"7C",X"C6",X"82",X"82",X"C6",X"44",X"00",X"FE",X"FE",X"82",X"82",X"C6",X"7C",X"38", + X"00",X"00",X"FE",X"FE",X"92",X"92",X"92",X"82",X"00",X"FE",X"FE",X"90",X"90",X"90",X"90",X"80", + X"00",X"38",X"7C",X"C6",X"82",X"92",X"9E",X"9E",X"00",X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE", + X"00",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"04",X"06",X"02",X"02",X"02",X"FE",X"FC", + X"00",X"FE",X"FE",X"18",X"3C",X"6E",X"C6",X"82",X"00",X"00",X"FE",X"FE",X"02",X"02",X"02",X"02", + X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",X"FE",X"FE",X"70",X"38",X"1C",X"FE",X"FE", + X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00",X"FE",X"FE",X"88",X"88",X"88",X"F8",X"70", + X"00",X"7C",X"FE",X"82",X"8A",X"8E",X"FC",X"7A",X"00",X"FE",X"FE",X"88",X"8C",X"9E",X"F6",X"72", + X"00",X"64",X"F6",X"92",X"92",X"D2",X"5E",X"0C",X"00",X"00",X"80",X"80",X"FE",X"FE",X"80",X"80", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_char_u.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_char_u.vhd new file mode 100644 index 00000000..60b0796a --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_char_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"38",X"7C",X"86",X"82",X"C2",X"7C",X"38",X"00",X"00",X"02",X"42",X"FE",X"FE",X"02",X"02", + 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+port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"B3",X"00",X"25",X"9F",X"DE",X"00",X"B0",X"DE",X"00",X"C0",X"25",X"BF",X"DE", + X"00",X"B0",X"DE",X"00",X"C0",X"25",X"DF",X"DE",X"00",X"B0",X"DE",X"00",X"C0",X"25",X"FF",X"DE", + X"00",X"B0",X"DE",X"00",X"C0",X"89",X"DE",X"76",X"00",X"62",X"B3",X"00",X"71",X"00",X"C0",X"89", + X"FB",X"7A",X"00",X"01",X"FF",X"FF",X"FF",X"FF",X"7A",X"9E",X"01",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7A",X"34",X"02",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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X"07",X"57",X"19",X"73",X"19",X"73",X"19",X"73",X"19",X"73",X"6D",X"0F",X"32",X"6A",X"F4",X"0B", + X"E7",X"C5",X"1F",X"F2",X"0B",X"32",X"B5",X"D9",X"66",X"A4",X"7D",X"44",X"A4",X"5A",X"2D",X"76", + X"01",X"90",X"19",X"22",X"9B",X"D2",X"1F",X"76",X"59",X"60",X"D1",X"22",X"76",X"5A",X"60",X"6D", + X"03",X"ED",X"01",X"D1",X"A4",X"3A",X"03",X"76",X"4E",X"60",X"EE",X"B3",X"0B",X"F8",X"C0",X"89", + X"FC",X"D9",X"76",X"1C",X"60",X"D9",X"22",X"00",X"6D",X"03",X"F3",X"0C",X"20",X"14",X"25",X"0A"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_cpu2.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_cpu2.vhd new file mode 100644 index 00000000..c49ef130 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_cpu2.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu2 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"33",X"9B",X"03",X"21",X"15",X"05",X"00",X"D9",X"40",X"7A",X"F5",X"1F",X"76",X"5F",X"60",X"19", + X"FA",X"7D",X"20",X"76",X"02",X"90",X"19",X"24",X"7D",X"19",X"04",X"4B",X"65",X"60",X"F4",X"00", + X"C2",X"7D",X"10",X"D9",X"FA",X"02",X"25",X"FE",X"82",X"04",X"D9",X"0D",X"01",X"25",X"AE",X"DA", + X"7A",X"39",X"20",X"D9",X"22",X"01",X"D9",X"FA",X"02",X"D9",X"0D",X"00",X"19",X"4B",X"19",X"4B", + X"19",X"4B",X"19",X"4B",X"A4",X"40",X"22",X"26",X"CE",X"00",X"E2",X"76",X"4E",X"60",X"E2",X"40", + X"97",X"E2",X"22",X"00",X"E2",X"D1",X"00",X"CB",X"8D",X"14",X"E2",X"76",X"80",X"70",X"15",X"40", + X"00",X"E2",X"40",X"89",X"FC",X"19",X"99",X"19",X"99",X"57",X"E2",X"40",X"DC",X"C2",X"6E",X"07", + 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+port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu3 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"18",X"D3",X"DC",X"01",X"B5",X"B3",X"06",X"D9",X"76",X"A8",X"61",X"D9",X"22",X"01",X"F4",X"00", + X"7D",X"1C",X"D9",X"24",X"00",X"D9",X"05",X"01",X"D9",X"66",X"CB",X"A4",X"2B",X"3D",X"00",X"00", + X"76",X"A9",X"60",X"D1",X"DC",X"D9",X"3E",X"EE",X"D9",X"F8",X"00",X"D9",X"F8",X"01",X"D9",X"C0", + X"D9",X"C0",X"89",X"D7",X"B5",X"EE",X"B3",X"03",X"D9",X"FA",X"00",X"A4",X"3B",X"33",X"E2",X"1F", + X"00",X"E2",X"C0",X"E2",X"C1",X"00",X"E2",X"C0",X"5C",X"D9",X"C0",X"D9",X"C0",X"D9",X"C0",X"D9", + X"C0",X"89",X"E5",X"B5",X"B3",X"0C",X"D9",X"76",X"9C",X"61",X"D9",X"22",X"01",X"F4",X"00",X"7D", + X"16",X"D9",X"24",X"00",X"D9",X"05",X"01",X"D9",X"66",X"CB",X"A4",X"2B",X"3D",X"DC",X"D9",X"3E", + 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rom_sprite_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"03",X"FF",X"0F",X"EB",X"3F",X"AB",X"3F",X"AB",X"3F",X"AB",X"0F",X"AB",X"03",X"EB", + X"00",X"00",X"00",X"00",X"54",X"00",X"43",X"00",X"43",X"00",X"FF",X"00",X"57",X"00",X"43",X"00", + X"0F",X"FB",X"3F",X"FF",X"3F",X"FF",X"3F",X"FF",X"3F",X"FF",X"0F",X"FF",X"03",X"F0",X"00",X"00", + X"43",X"00",X"FC",X"00",X"FC",X"00",X"F0",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"3F",X"03",X"FB",X"0F",X"EB",X"3F",X"EB",X"3F",X"EB",X"3F",X"EB",X"03",X"EB", + X"00",X"00",X"C0",X"00",X"54",X"00",X"04",X"00",X"07",X"00",X"FF",X"00",X"57",X"00",X"07",X"00", + X"3F",X"FB",X"3F",X"FF",X"3F",X"FF",X"0F",X"FF",X"03",X"FF",X"00",X"FF",X"00",X"00",X"00",X"00", + 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if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_sprite_u.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_sprite_u.vhd new file mode 100644 index 00000000..dbaf8985 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ROM/rom_sprite_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0A",X"00",X"AA",X"02",X"AA",X"0A",X"AA",X"0A",X"AA",X"0A",X"AA", + X"00",X"00",X"00",X"00",X"A8",X"00",X"AB",X"00",X"AB",X"C0",X"AB",X"C0",X"AA",X"C0",X"AA",X"E0", + X"02",X"AA",X"0A",X"AA",X"0A",X"AA",X"02",X"AA",X"00",X"AA",X"00",X"0A",X"00",X"00",X"00",X"00", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/build_id.tcl b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/build_id.v b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/build_id.v new file mode 100644 index 00000000..10dd7c3c --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "123540" diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c3e13c5c --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1094 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..7e8a9995 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,370 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..7d407fb8 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2027 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..6904b66b --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..998033ef --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd new file mode 100644 index 00000000..33d61068 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/cpu/T80a.vhd @@ -0,0 +1,280 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80a is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLK_EN_SYS : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80a; + +architecture rtl of T80a is + + signal CEN : std_logic; + signal Reset_s : std_logic; + signal IntCycle_n : std_logic; + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal MREQ : std_logic; + signal MReq_Inhibit : std_logic; + signal Req_Inhibit : std_logic; + signal RD : std_logic; + signal MREQ_n_i : std_logic; + signal IORQ_n_i : std_logic; + signal RD_n_i : std_logic; + signal WR_n_i : std_logic; + signal RFSH_n_i : std_logic; + signal BUSAK_n_i : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal DO_Reg : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal Wait_s : std_logic; + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + -- clock enable supplied from clocking system + CEN <= CLK_EN_SYS; + + BUSAK_n <= BUSAK_n_i; + MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); + RD_n_i <= not RD or Req_Inhibit; + + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DO <= DO_Reg; + +-- process (RESET_n, CLK_n) +-- begin +-- if RESET_n = '0' then +-- Reset_s <= '0'; +-- elsif CLK_n'event and CLK_n = '1' then +-- Reset_s <= '1'; +-- end if; +-- end process; + -- T80 reset input has already proper characteristics: + -- * asynchronous assertion + -- * deassertion synchronous to CLK_n (main_clk) + Reset_s <= RESET_n; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, + DInst => DI, + DI => DI_Reg, + DO => DO_Reg, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + if CEN = '1' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then + DI_Reg <= to_x01(DI); + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + WR_n_i <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + WR_n_i <= '1'; + if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! + WR_n_i <= not Write; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + Req_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + Req_Inhibit <= '1'; + else + Req_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + MReq_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + MReq_Inhibit <= '1'; + else + MReq_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process(Reset_s,CLK_n) + begin + if Reset_s = '0' then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + + if MCycle = "001" then + if TState = "001" then + RD <= IntCycle_n; + MREQ <= IntCycle_n; + IORQ_n_i <= IntCycle_n; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '1'; + end if; + if TState = "100" then + MREQ <= '0'; + end if; + else + if TState = "001" and NoRead = '0' then + RD <= not Write; + IORQ_n_i <= not IORQ; + MREQ <= not IORQ; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + end if; + end if; + + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/dac.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/dac.vhd new file mode 100644 index 00000000..c21b306b --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 7 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/dpram.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/hq2x.sv b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/keyboard.v b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd new file mode 100644 index 00000000..92348ed0 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug.vhd @@ -0,0 +1,243 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- Toplevel port for Papilio Plus board. +-- +------------------------------------------------------------------------------- +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library ieee; + use ieee.numeric_std.all; + +use work.ladybug_dip_pack.all; + +entity ladybugt is +port ( + -- Global Interface ------------------------------------------------------- + CLK_IN : in std_logic; -- 20MHz + I_RESET : in std_logic; + + -- VGA Interface ---------------------------------------------------------- + O_VIDEO_R : out std_logic_vector( 1 downto 0); + O_VIDEO_G : out std_logic_vector( 1 downto 0); + O_VIDEO_B : out std_logic_vector( 1 downto 0); + O_VSYNC : out std_logic; + O_HSYNC : out std_logic; + O_VBLANK : out std_logic; + O_HBLANK : out std_logic; + O_PIXCE : out std_logic; + + -- Audio Interface -------------------------------------------------------- + O_AUDIO : out signed(7 downto 0); + + but_coin_s : in std_logic_vector( 1 downto 0); + but_fire_s : in std_logic_vector( 1 downto 0); + but_bomb_s : in std_logic_vector( 1 downto 0); + but_tilt_s : in std_logic_vector( 1 downto 0); + but_select_s : in std_logic_vector( 1 downto 0); + but_up_s : in std_logic_vector( 1 downto 0); + but_down_s : in std_logic_vector( 1 downto 0); + but_left_s : in std_logic_vector( 1 downto 0); + but_right_s : in std_logic_vector( 1 downto 0) +); +end ladybugt; + +architecture struct of ladybugt is + + signal + ps2_codeready, + clk_20mhz_s, + clk_en_5mhz_s, + ext_res_n_s, + ext_res_s, + audio_s, + vid_hsync, + vid_vsync, + vga_hsync, + vid_comp_sync_n, + vga_vsync : std_logic; + + signal rom_cpu_a_s : std_logic_vector(14 downto 0); + signal rom_cpu_d_s : std_logic_vector( 7 downto 0); + signal rom_cpu_d1 : std_logic_vector( 7 downto 0); + signal rom_cpu_d2 : std_logic_vector( 7 downto 0); + signal rom_cpu_d3 : std_logic_vector( 7 downto 0); + signal rom_cpu_d4 : std_logic_vector( 7 downto 0); + signal rom_cpu_d5 : std_logic_vector( 7 downto 0); + signal rom_cpu_d6 : std_logic_vector( 7 downto 0); + + signal rom_char_a_s : std_logic_vector(11 downto 0); + signal rom_char_d_s : std_logic_vector(15 downto 0); + + signal rom_sprite_a_s : std_logic_vector(11 downto 0); + signal rom_sprite_d_s : std_logic_vector(15 downto 0); + + signal + dac_audio_s, + dip_block_1_s, + dip_block_2_s : std_logic_vector( 7 downto 0) := (others => '0'); + + signal ps2_scancode : std_logic_vector( 9 downto 0) := (others => '0'); + + signal + vid_rgb, + vga_rgb : std_logic_vector(15 downto 0) := (others => '0'); + + signal but_chute_s : std_logic_vector( 1 downto 0) := (others=>'0'); + +begin + + O_PIXCE <= clk_en_5mhz_s; + + but_chute_s <= not but_coin_s(1) & not but_coin_s(0); + + ----------------------------------------------------------------------------- + -- inputs assignments + ----------------------------------------------------------------------------- + ext_res_s <= I_RESET; + ext_res_n_s <= not ext_res_s; + clk_20mhz_s <= CLK_IN; + + ----------------------------------------------------------------------------- + -- Ladybug Machine + ----------------------------------------------------------------------------- + machine_b : entity work.ladybug_machine + port map ( + ext_res_n_i => ext_res_n_s, + clk_20mhz_i => clk_20mhz_s, + clk_en_5mhz_o => clk_en_5mhz_s, + tilt_n_i => but_tilt_s(0), + player_select_n_i => but_select_s, + player_fire_n_i => but_fire_s, + player_up_n_i => but_up_s, + player_right_n_i => but_right_s, + player_down_n_i => but_down_s, + player_left_n_i => but_left_s, + player_bomb_n_i => but_bomb_s, + right_chute_i => but_chute_s(0), + left_chute_i => but_chute_s(1), + dip_block_1_i => dip_block_1_s, + dip_block_2_i => dip_block_2_s, + rgb_r_o => O_VIDEO_R, + rgb_g_o => O_VIDEO_G, + rgb_b_o => O_VIDEO_B, + hsync_n_o => O_HSYNC, + vsync_n_o => O_VSYNC, + vblank_o => O_VBLANK, + hblank_o => O_HBLANK, + audio_o => O_AUDIO, + rom_cpu_a_o => rom_cpu_a_s, + rom_cpu_d_i => rom_cpu_d_s, + rom_char_a_o => rom_char_a_s, + rom_char_d_i => rom_char_d_s, + rom_sprite_a_o => rom_sprite_a_s, + rom_sprite_d_i => rom_sprite_d_s + ); + + ----------------------------------------------------------------------------- + -- Building the DIP Switches - see file ladybug_dip_pack.vhd + ----------------------------------------------------------------------------- +-- dip_block_1_s <= lb_dip_block_1_c; -- Lady Bug + dip_block_1_s <= do_dip_block_1_c; -- Dorodon +-- dip_block_1_s <= ca_dip_block_1_c; -- Cosmic Avenger + dip_block_2_s <= price_dip_block_2_c; -- Common for all games (coins per game pricing) + + ----------------------------------------------------------------------------- + -- Game ROMs + ----------------------------------------------------------------------------- + inst_rom_spritel : entity work.rom_sprite_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s( 7 downto 0) + ); + + inst_rom_spriteu : entity work.rom_sprite_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s(15 downto 8) + ); + + inst_rom_charl : entity work.rom_char_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s( 7 downto 0) + ); + + inst_rom_charu : entity work.rom_char_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s(15 downto 8) + ); + + inst_rom_cpu1 : entity work.rom_cpu1 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d1 + ); + + inst_rom_cpu2 : entity work.rom_cpu2 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d2 + ); + + inst_rom_cpu3 : entity work.rom_cpu3 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d3 + ); + + ----------------------------------------------------------------------------- + -- Program ROMs data mux + ----------------------------------------------------------------------------- + rom_cpu_d_s <= + rom_cpu_d1 when rom_cpu_a_s(14 downto 13) = "00" else + rom_cpu_d2 when rom_cpu_a_s(14 downto 13) = "01" else + rom_cpu_d3 when rom_cpu_a_s(14 downto 13) = "10" else + (others=>'0'); + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_addr_dec.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_addr_dec.vhd new file mode 100644 index 00000000..6d857f6c --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_addr_dec.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_addr_dec.vhd,v 1.10 2005/12/10 14:51:46 arnim Exp $ +-- +-- Address decoder of the CPU Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_addr_dec is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + a_i : in std_logic_vector(15 downto 12); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + mreq_n_i : in std_logic; + rfsh_n_i : in std_logic; + cs_n_o : out std_logic_vector(15 downto 0); + ram_cpu_cs_n_o : out std_logic + ); + +end ladybug_addr_dec; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_addr_dec is + +begin + + ----------------------------------------------------------------------------- + -- Process adec + -- + -- Purpose: + -- Decode the CPU address and generate one-hot chip select signals. + -- Each chip select enables a 4 KByte address segment. + -- + -- The chip select outputs are registered with the 20 MHz clock to + -- break potentially long combinational paths here. + -- + adec: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + cs_n_o <= (others => '1'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- default assignment + cs_n_o <= (others => '1'); + + if a_i(15) = '0' then + if rd_n_i = '0' or wr_n_i = '0' then + cs_n_o(to_integer(unsigned( '0' & a_i(14 downto 12) ))) <= '0'; + end if; + + else + if mreq_n_i = '0' and rfsh_n_i = '1' then + cs_n_o(to_integer(unsigned( '1' & a_i(14 downto 12) ))) <= '0'; + end if; + + end if; + + end if; + end process adec; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cs_ext_ram + -- + -- Purpose: + -- Builds the combinational chip select signal for the external CPU RAM. + -- + cs_ext_ram: process (a_i, + rd_n_i, wr_n_i) + begin + if (rd_n_i = '0' or wr_n_i = '0') and + a_i(15 downto 12) = "0110" then + ram_cpu_cs_n_o <= '0'; + else + ram_cpu_cs_n_o <= '1'; + end if; + end process cs_ext_ram; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_char.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_char.vhd new file mode 100644 index 00000000..1ca149f3 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_char.vhd @@ -0,0 +1,740 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char.vhd,v 1.18 2005/10/10 22:02:14 arnim Exp $ +-- +-- Character Video Module of Lady Bug Machine. +-- +-- This unit contains most of the logic found on schematic page three. +-- Excluded parts are: +-- * the 10 MHz and 5 MHz clock generation +-- moved into separate module on toplevel of Lady Bug machine +-- * the video timing circuitry +-- moved into separate module on toplevel of video unit +-- * the video MUX and RGB conversion unit +-- moved into separate module at toplevel of video unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity ladybug_char is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_char_o : out std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + ha_t_rise_i : in std_logic; + hx_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + hbl_i : in std_logic; + blank_flont_i : in std_logic; + blank_o : out std_logic; + crg_o : out std_logic_vector( 5 downto 1); + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_char; + +architecture rtl of ladybug_char is + + signal flip_screen_q : std_logic; + + signal h0_s, + h1_s, + h2_s : std_logic; + signal h_flip_s, + h_t_flip_s : std_logic_vector(3 downto 0); + signal v_flip_s, + v_t_flip_s : std_logic_vector(3 downto 0); + + signal h_ctrl_d_s, + h_ctrl_s, + h_ctrl_n_s, + h_ctrl_d_out_s, + h_ctrl_d_n_out_s, + h_ctrl_rise_s, + h_ctrl_n_rise_s : std_logic_vector(4 downto 1); + + signal hx_ctrl_q, + hx_ctrl_s, + hx_ctrl_n_rise_s : std_logic; + signal hx_ctrl_clear_q : std_logic; + + signal b1_ff_q, + b1_ff_s, + b1_ff_n_rise_s : std_logic; + + signal wait_q : std_logic; + signal wait_clear_q : std_logic; + + signal cgs_q, + cgs_s, + cgs_rise_s : std_logic; + + signal ram_addr_s : std_logic_vector(9 downto 0); + signal select_a_s : std_logic; + + signal char_ram_cs_n_s, + char_ram_we_n_s : std_logic; + signal col_ram_cs_n_s, + col_ram_we_n_s : std_logic; + signal d_from_char_ram_s : std_logic_vector(7 downto 0); + signal d_from_col_ram_s : std_logic_vector(3 downto 0); + + signal s_q : std_logic_vector( 7 downto 0); + signal d_char_ram_q : std_logic_vector( 7 downto 0); + signal d_col_ram_q : std_logic_vector( 3 downto 0); + + signal d_char_rom_q : std_logic_vector(15 downto 0); + signal crg1_s, + crg2_s, + crg3_q, + crg4_q, + crg5_q : std_logic; + + signal hbl_q,hbl_d : std_logic; + + signal hcnt : integer; + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Process flip + -- + -- Purpose: + -- Implement the flip_screen flag. + -- + flip: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + -- Actually, this asynchronous reset of the ls259 is not 100% + -- equivalent to the real behavior of this circuit. However, + -- the flip_screen latch is modelled like this for the sake of + -- simplicity. It's sufficient for the purpose here. + flip_screen_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if a_i(2 downto 0) = "000" and cs10_n_i = '0' then + flip_screen_q <= d_from_cpu_i(0); + end if; + + end if; + end process flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process h_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + h_flip: process (flip_screen_q, + h_i, h_t_i, + s_q) + variable a_v, b_v, + sum_v : unsigned(8 downto 0); + begin + -- calculate sum + a_v := '0' & unsigned(s_q); + b_v := '0' & unsigned(h_t_i) & unsigned(h_i); + sum_v := a_v + b_v; + + -- h0,1,2 are taken from directly from sum + h0_s <= sum_v(0); + h1_s <= sum_v(1); + h2_s <= sum_v(2); + + -- now flip + for idx in 3 downto 0 loop + h_flip_s(idx) <= flip_screen_q xor sum_v(idx); + h_t_flip_s(idx) <= flip_screen_q xor sum_v(idx + 4); + end loop; + end process h_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process v_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + v_flip: process (flip_screen_q, + v_i, v_t_i) + begin + for idx in 3 downto 0 loop + v_flip_s(idx) <= flip_screen_q xor v_i(idx); + v_t_flip_s(idx) <= flip_screen_q xor v_t_i(idx); + end loop; + end process v_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The Horizontal Control Signals + -- Detailed purpose/meaning is unknown. + ----------------------------------------------------------------------------- + h_ctrl_d_s(1) <= not (not h2_s and (h1_s xor h0_s)); + h_ctrl_d_s(2) <= hx_i; + h_ctrl_d_s(3) <= not ((h1_s xor h0_s) or (not h2_s xor h1_s)); + h_ctrl_d_s(4) <= '0'; + h_ctrl_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + por_n_i => por_n_i, + cl_n_i => vdd_s, + d_i => h_ctrl_d_s, + q_o => h_ctrl_s, + q_n_o => h_ctrl_n_s, + d_o => h_ctrl_d_out_s, + d_n_o => h_ctrl_d_n_out_s + ); + h_ctrl_rise_s <= not h_ctrl_s and h_ctrl_d_out_s; + h_ctrl_n_rise_s <= h_ctrl_s and not h_ctrl_d_n_out_s; + + + ----------------------------------------------------------------------------- + -- Process ctrl_seq + -- + -- Purpose: + -- Implemente the various sequential elements for horizontal control. + -- + ctrl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_ctrl_q <= '0'; + hx_ctrl_clear_q <= '0'; + b1_ff_q <= '0'; + wait_q <= '0'; + wait_clear_q <= '0'; + cgs_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- the HX control flip-flop + hx_ctrl_q <= hx_ctrl_s; + + -- the clear counterpart of hx_ctrl_q + if h_ctrl_s(2) = '0' then + -- pseudo-asynchronous clear + hx_ctrl_clear_q <= '0'; + elsif hx_ctrl_n_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + hx_ctrl_clear_q <= '1'; + end if; + + -- the mysterious B1 flip-flop + b1_ff_q <= b1_ff_s; + + -- the CGS rising edge indicator support flip-flops + cgs_q <= cgs_s; + + -- the WAIT flip-flop + if wait_clear_q = '1' then + -- pseudo-asynchronous clear + wait_q <= '0'; + elsif cgs_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + wait_q <= '1'; + end if; + + -- the clear counterpart of wait_q + if clk_en_4mhz_i = '1' then + wait_clear_q <= wait_q and (h_ctrl_s(3) and (b1_ff_q or hx_ctrl_q)); + end if; + + end if; + end process ctrl_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ctrl_comp + -- + -- Purpose: + -- Implements the combination logic for the horizontal control + -- elements. + -- + ctrl_comp: process (h_ctrl_rise_s, + hx_i, hx_ctrl_q, + hx_ctrl_clear_q, + h_ctrl_n_rise_s, + b1_ff_q, + cgs_q, cs13_n_i) + begin + -- default assignments + hx_ctrl_s <= hx_ctrl_q; + hx_ctrl_n_rise_s <= '0'; + b1_ff_s <= b1_ff_q; + b1_ff_n_rise_s <= '0'; + cgs_s <= cgs_q; + cgs_rise_s <= '0'; + + -- the HX control flip-flop ----------------------------------------------- + if hx_ctrl_clear_q = '1' then + -- pseudo-asynchronous clear + hx_ctrl_s <= '0'; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + elsif h_ctrl_rise_s(1) = '1' then + -- rising edge indicator acts as clock enable instead of clock + if hx_i = '1' then + -- toggle FF + hx_ctrl_s <= not hx_ctrl_q; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + end if; + end if; + + -- the mysterious B1 flip-flop -------------------------------------------- + if hx_ctrl_q = '1' then + -- pseudo-asynchronous clear + b1_ff_s <= '0'; + + if (not b1_ff_q) = '0' then + -- detct rising edge of inverted ouput + b1_ff_n_rise_s <= '1'; + end if; + elsif h_ctrl_n_rise_s(3) = '1' then + -- rising edge indicator acts as clock enable instead of clock + b1_ff_s <= '1'; + end if; + + -- the CGS rising edge indicator support flip-flop ------------------------ + cgs_s <= not cs13_n_i; + cgs_rise_s <= not cgs_q and not cs13_n_i; + + end process ctrl_comp; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_addr + -- + -- Purpose: + -- Multiplexes the CPU address bus and the h+v timing control signals to + -- form the RAM address bus. + -- + ram_addr: process (h_flip_s, h_t_flip_s, + v_flip_s, v_t_flip_s, + a_i, + h_ctrl_s, h_ctrl_n_s, + hx_ctrl_q, + b1_ff_q) + variable a_v, b_v, g_n_v : std_logic; + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + ram_addr_s <= (others => '0'); + + -- logic that drives A input of IC L4 and K4 + a_v := not (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + -- logic that drives B input of IC L4 and K4 + b_v := hx_ctrl_q; + -- logic that drives /G input of IC J4 + g_n_v := hx_ctrl_q and (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + + -- IC L4 and K4: Dual 4:1 Multiplexer ------------------------------------- + vec_v := b_v & a_v; + case vec_v is + when "00" => + ram_addr_s(0) <= h_flip_s (3); + ram_addr_s(1) <= h_t_flip_s(0); + -- + ram_addr_s(2) <= h_t_flip_s(1); + ram_addr_s(3) <= h_t_flip_s(2); + when "01" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when "10" => + ram_addr_s(0) <= v_t_flip_s(1); + ram_addr_s(1) <= v_t_flip_s(2); + -- + ram_addr_s(2) <= v_t_flip_s(3); + ram_addr_s(3) <= '0'; + when "11" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when others => + null; + end case; + + -- IC J4 and H4: Quad 2:1 Multiplexer ------------------------------------- + case a_v is + when '0' => + ram_addr_s(4) <= h_t_flip_s(3) and not g_n_v; + ram_addr_s(7) <= v_t_flip_s(1) and not g_n_v; + ram_addr_s(8) <= v_t_flip_s(2) and not g_n_v; + ram_addr_s(9) <= v_t_flip_s(3) and not g_n_v; + -- + ram_addr_s(5) <= v_flip_s (3); + ram_addr_s(6) <= v_t_flip_s(0); + when '1' => + ram_addr_s(4) <= a_i (4) and not g_n_v; + ram_addr_s(7) <= a_i (7) and not g_n_v; + ram_addr_s(8) <= a_i (8) and not g_n_v; + ram_addr_s(9) <= a_i (9) and not g_n_v; + -- + ram_addr_s(5) <= a_i (5); + ram_addr_s(6) <= a_i (6); + when others => + null; + end case; + + select_a_s <= a_v; + + end process ram_addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_ctrl + -- + -- Purpose: + -- Generate the control signals for the character and color RAMs. + -- This comprises: + -- * reading RAMs while the beam sweeps the screen + -- * reading RAMs to the CPU + -- * writing RAMs from the CPU + -- + ram_ctrl: process (cs13_n_i, + wait_q, + select_a_s, + a_i, + wr_n_i, rd_n_i, + d_from_char_ram_s, d_from_col_ram_s, + clk_en_4mhz_i) + variable cpu_read_char_ram_v : boolean; + variable cpu_write_char_ram_v : boolean; + variable cpu_read_col_ram_v : boolean; + variable cpu_write_col_ram_v : boolean; + variable vec_v : std_logic_vector(2 downto 0); + begin + -- default assignments + char_ram_cs_n_s <= '1'; + char_ram_we_n_s <= '1'; + col_ram_cs_n_s <= '1'; + col_ram_we_n_s <= '1'; + d_from_char_o <= (others => '1'); + cpu_read_char_ram_v := false; + cpu_write_char_ram_v := false; + cpu_read_col_ram_v := false; + cpu_write_col_ram_v := false; + + -- detect and decode CPU access + if clk_en_4mhz_i = '1' and -- operate RAMs with CPU clock + (not cs13_n_i and select_a_s and not wait_q) = '1' then + vec_v := a_i(10) & rd_n_i & wr_n_i; + case vec_v is + when "001" => + cpu_read_char_ram_v := true; + when "010" => + cpu_write_char_ram_v := true; + when "101" => + cpu_read_col_ram_v := true; + when "110" => + cpu_write_col_ram_v := true; + when others => + null; + end case; + end if; + + -- now we are prepared to generate the /CS and /WE signals for the RAMs + if select_a_s = '0' or + cpu_read_char_ram_v or cpu_write_char_ram_v then + char_ram_cs_n_s <= '0'; + end if; + if select_a_s = '0' or + cpu_read_col_ram_v or cpu_write_col_ram_v then + col_ram_cs_n_s <= '0'; + end if; + if cpu_write_char_ram_v then + char_ram_we_n_s <= '0'; + end if; + if cpu_write_col_ram_v then + col_ram_we_n_s <= '0'; + end if; + + -- and we can multiplex the data bus towards the CPU + if cpu_read_char_ram_v then + d_from_char_o <= d_from_char_ram_s; + elsif cpu_read_col_ram_v then + d_from_char_o(3 downto 0) <= d_from_col_ram_s; + end if; + + end process ram_ctrl; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The character RAM + ----------------------------------------------------------------------------- + char_ram_b : entity work.ladybug_char_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => char_ram_cs_n_s, + we_n_i => char_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => d_from_char_ram_s + ); + ----------------------------------------------------------------------------- + -- The color RAM + ----------------------------------------------------------------------------- + col_ram_b : entity work.ladybug_char_col_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => col_ram_cs_n_s, + we_n_i => col_ram_we_n_s, + d_i => d_from_cpu_i(3 downto 0), + d_o => d_from_col_ram_s + ); + + + ----------------------------------------------------------------------------- + -- Process ram_d_seq + -- + -- Purpose: + -- Implements three latch banks that save the output of the character + -- and color RAMs. + -- + ram_d_seq: process (clk_20mhz_i, por_n_i) + variable complex_rising_edge_v : boolean; + begin + if por_n_i = '0' then + s_q <= (others => '0'); + d_char_ram_q <= (others => '0'); + d_col_ram_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- latch data from the character RAM to form input for h_flip ----------- + if hx_ctrl_n_rise_s = '1' then + s_q <= d_from_char_ram_s; + end if; + + -- latch data from the character RAM for ROM address generation --------- + -- there are three sources for a rising edge: + -- 1) falling edge of h_ctrl_n_s(1) + -- => equivalen to rising edge of h_ctrl_s(1) + -- 2) rising edge of hx_ctrl_n_q + -- 3) rising edge of b1_ff_n + -- For each source, the two have to be in a defined state to let + -- the edge propage to the latches. + complex_rising_edge_v := ((h_ctrl_rise_s(1) and + (b1_ff_q or hx_ctrl_q)) or + (hx_ctrl_n_rise_s and + (not b1_ff_q and not h_ctrl_n_s(1))) or + (b1_ff_n_rise_s and + (not hx_ctrl_q and not h_ctrl_s(1)))) = '1'; + if complex_rising_edge_v then + d_char_ram_q <= d_from_char_ram_s; + d_col_ram_q <= d_from_col_ram_s; + end if; + + end if; + end process ram_d_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process latch_rom_d + -- + -- Purpose: + -- Latch the output of the character ROM. + -- + latch_rom_d: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + d_char_rom_q <= (others => '0'); + crg3_q <= '0'; + crg4_q <= '0'; + crg5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if (clk_en_5mhz_i and + h2_s and h1_s and h0_s) = '1' then + d_char_rom_q <= rom_char_d_i; + crg3_q <= d_col_ram_q(0); + crg4_q <= d_col_ram_q(1); + crg5_q <= d_col_ram_q(2); + end if; + + end if; + end process latch_rom_d; + -- + ----------------------------------------------------------------------------- + -- Process hbl_seq + -- + -- Purpose: + -- Implements the flip-flop that latches HBL. + -- + hbl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hbl_q <= '0'; + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + if hcnt /= 255 then + hcnt <= hcnt + 1; + end if; + end if; + if ha_t_rise_i = '1' then + hbl_q <= hbl_i; + if hbl_q = '1' and hbl_i = '0' then + hcnt <= 0; + end if; + end if; + end if; + end process hbl_seq; + -- + ----------------------------------------------------------------------------- + + process (clk_20mhz_i) + begin + if rising_edge(clk_20mhz_i) then + if clk_en_5mhz_i = '1' then + hbl_d <= hbl_q; + + if hcnt < 240 then + hblank_o <= '0'; + else + hblank_o <= '1'; + end if; + + if hbl_d = '0' and hbl_q = '1' then + vblank_o <= not blank_flont_i; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process crg_mux + -- + -- Purpose: + -- Multiplexes the latched character ROM data to CRG1 and CRG2. + -- + crg_mux: process (d_char_rom_q, + h_flip_s, + blank_flont_i, + hbl_q) + variable blank_v : std_logic; + variable idx_v : unsigned(2 downto 0); + begin + blank_v := not (blank_flont_i and not hbl_q); + idx_v := unsigned(h_flip_s(2 downto 0)); + + if blank_v = '0' then + crg1_s <= d_char_rom_q(to_integer('0' & idx_v)); + crg2_s <= d_char_rom_q(to_integer('1' & idx_v)); + else + crg1_s <= '0'; + crg2_s <= '0'; + end if; + + blank_o <= blank_v; + end process crg_mux; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + wait_n_o <= not wait_q; + crg_o(5) <= crg5_q; + crg_o(4) <= crg4_q; + crg_o(3) <= crg3_q; + crg_o(2) <= crg2_s; + crg_o(1) <= crg1_s; + rom_char_a_o( 2 downto 0) <= v_flip_s(2 downto 0); + rom_char_a_o(10 downto 3) <= d_char_ram_q; + rom_char_a_o(11) <= d_col_ram_q(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_chute.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_chute.vhd new file mode 100644 index 00000000..b3255fe0 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_chute.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chute.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaper for a chute input. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chute is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + chute_i : in std_logic; + chute_o : out std_logic + ); + +end ladybug_chute; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_chute is + + -- 2.35e-2 s = 1 / 20,000,000 Hz * 470000 + constant chute_delay_c : natural := 470000; + + signal chute_cnt_q : unsigned(18 downto 0); + + signal chute_sync_q : std_logic_vector(1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process sync + -- + -- Purpose: + -- Synchronize the asynchronous chute input. + -- + sync: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_sync_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + chute_sync_q(0) <= chute_i; + chute_sync_q(1) <= chute_sync_q(0); + + end if; + end process sync; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cnt + -- + -- Purpose: + -- Count the required number of 20 MHz clock cycles before emitting + -- chute event. This is a low pass filter for the rising edge of chute_i. + -- + cnt: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if chute_sync_q(1) = '1' then + if chute_cnt_q = chute_delay_c then + chute_o <= '1'; + else + chute_cnt_q <= chute_cnt_q + 1; + end if; + + else + -- reset counter when chute input goes back to 0 + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + end if; + + end if; + end process cnt; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_chutes.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_chutes.vhd new file mode 100644 index 00000000..7584de89 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_chutes.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chutes.vhd,v 1.4 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaping for the two chute inputs. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chutes is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + cs8_n_i : in std_logic; + nmi_n_o : out std_logic; + int_n_o : out std_logic + ); + +end ladybug_chutes; + +architecture rtl of ladybug_chutes is + + signal right_chute_s, + left_chute_s : std_logic; + signal left_chute_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Pulse shaper for Right Chute + ----------------------------------------------------------------------------- + right_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => right_chute_i, + chute_o => right_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Pulse shaper for Left Chute + ----------------------------------------------------------------------------- + left_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => left_chute_i, + chute_o => left_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Process left_edge + -- + -- Purpose: + -- Implement the edge detector for the left chute. + -- Only a rising edge of the filtered chute input can trigger a new + -- interrupt to the CPU. + -- + left_edge: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + left_chute_q <= '0'; + int_n_o <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + left_chute_q <= left_chute_s; + + if cs8_n_i = '0' then + -- synchronous set, has priority over data path + int_n_o <= '1'; + + -- edge detector + elsif left_chute_s = '1' and left_chute_q = '0' then + int_n_o <= '0'; + + end if; + + end if; + end process left_edge; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + nmi_n_o <= not right_chute_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_clk.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_clk.vhd new file mode 100644 index 00000000..d3e00484 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_clk.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_clk.vhd,v 1.5 2005/10/28 21:17:41 arnim Exp $ +-- +-- Clock generator for the Lady Bug machine. +-- +-- This module generates the clock enables which are required to mimic the +-- different clocks of the Lady Bug boards. +-- +-- Theory of Operation: +-- A PLL is used to tune the external clock to 20 MHz. This forms the +-- main clock which is used by all sequential elements. +-- All derived clocks are built with clock enables to allow a synchronous +-- design style (sort of). +-- +-- Note: +-- The counters and enable signals are reset by the power-on reset. +-- Thus, the "derived clocks" run during normal system reset. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_clk is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_10mhz_n_o : out std_logic; + clk_en_5mhz_o : out std_logic; + clk_en_5mhz_n_o : out std_logic; + clk_en_4mhz_o : out std_logic + ); + +end ladybug_clk; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_clk is + + -- counter for 5 MHz and 10 MHz clock enables + signal clk_cnt_5mhz_q : unsigned(1 downto 0); + -- counter for 4 MHz clock enable + signal clk_cnt_4mhz_q : unsigned(2 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process clk_en + -- + -- Purpose: + -- Generates the clock enables for 10 MHz, 5 MHz, 4 MHz. + -- + clk_en: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_cnt_5mhz_q <= (others => '0'); + clk_cnt_4mhz_q <= (others => '0'); + clk_en_10mhz_o <= '0'; + clk_en_10mhz_n_o <= '0'; + clk_en_5mhz_o <= '0'; + clk_en_5mhz_n_o <= '0'; + clk_en_4mhz_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + + ------------------------------------------------------------------------- + -- 10 MHz / 5 MHz clock domain + -- + -- counter for 10 MHz and 5 MHz clock enables + clk_cnt_5mhz_q <= clk_cnt_5mhz_q + 1; + + -- generate clock enable for 10 MHz + -- enable on every second clock of clk_20mhz_i + clk_en_10mhz_o <= clk_cnt_5mhz_q(0); + -- enable with 180 deg phase shift + clk_en_10mhz_n_o <= not clk_cnt_5mhz_q(0); + + -- generate clock enables for 5 MHz: + -- enable on every forth clock of clk_20mhz_i + if clk_cnt_5mhz_q = "11" then + clk_en_5mhz_o <= '1'; + else + clk_en_5mhz_o <= '0'; + end if; + -- enable with 180 deg phase shift + if clk_cnt_5mhz_q = "01" then + clk_en_5mhz_n_o <= '1'; + else + clk_en_5mhz_n_o <= '0'; + end if; + -- + ------------------------------------------------------------------------- + + + ------------------------------------------------------------------------- + -- 4 MHz domain + -- + -- counter for 4 MHz clock enable, wrap around after 5 clocks + clk_en_4mhz_o <= clk_cnt_4mhz_q(2); + + if clk_cnt_4mhz_q = "100" then + clk_cnt_4mhz_q <= (others => '0'); + else + clk_cnt_4mhz_q <= clk_cnt_4mhz_q + 1; + end if; + -- + ------------------------------------------------------------------------- + + end if; + end process clk_en; + -- + ----------------------------------------------------------------------------- + + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_counter.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_counter.vhd new file mode 100644 index 00000000..d07256bb --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_counter.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------- +-- +-- Synchronous 8-Bit Binary Counter with preset. +-- +-- $Id: ladybug_counter.vhd,v 1.9 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity counter is +port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + reset_n_i : in std_logic; + load_i : in std_logic; + preset_i : in std_logic_vector(7 downto 0); + q_o : out std_logic_vector(7 downto 0); + rise_q_o : out std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0); + co_o : out std_logic +); +end counter; + +architecture rtl of counter is + signal cnt_q : std_logic_vector(7 downto 0); + signal cnt_s : std_logic_vector(7 downto 0); +begin + + seq: process (ck_i, reset_n_i) + begin + if reset_n_i = '0' then + cnt_q <= (others => '0'); + elsif rising_edge(ck_i) then + cnt_q <= cnt_s; + end if; + end process seq; + + adder: process (ck_en_i, cnt_q, load_i, preset_i) + begin + cnt_s <= cnt_q; + + if ck_en_i = '1' then + if load_i = '1' then + cnt_s <= preset_i; + else + cnt_s <= cnt_q + 1; + end if; + end if; + end process adder; + + co_o <= '1' when cnt_q = x"FF" else '0'; + rise_q_o <= cnt_s and not cnt_q; + q_o <= cnt_q; + d_o <= cnt_s; +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd new file mode 100644 index 00000000..7d41074f --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_cpu_unit.vhd @@ -0,0 +1,260 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_unit.vhd,v 1.19 2005/12/10 14:51:51 arnim Exp $ +-- +-- CPU Main Unit of the Lady Bug Machine. +-- +-- Actually, the PCB where the CPU resides on contains also the sound chips and +-- parts of the video controller. For the sake of simplicity, the CPU and chip +-- select logic has been moved into this separate unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_unit is + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + res_n_i : in std_logic; + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + sound_wait_n_i : in std_logic; + wait_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + gpio_in0_i : in std_logic_vector( 7 downto 0); + gpio_in1_i : in std_logic_vector( 7 downto 0); + gpio_in2_i : in std_logic_vector( 7 downto 0); + gpio_in3_i : in std_logic_vector( 7 downto 0); + gpio_extra_i : in std_logic_vector( 7 downto 0); + a_o : out std_logic_vector(10 downto 0); + d_to_cpu_i : in std_logic_vector( 7 downto 0); + d_from_cpu_o : out std_logic_vector( 7 downto 0); + rd_n_o : out std_logic; + wr_n_o : out std_logic; + cs7_n_o : out std_logic; + cs10_n_o : out std_logic; + cs11_n_o : out std_logic; + cs12_n_o : out std_logic; + cs13_n_o : out std_logic + ); + +end ladybug_cpu_unit; + +architecture struct of ladybug_cpu_unit is + + signal t80_clk_en_s : std_logic; + + signal wait_n_s : std_logic; + signal int_n_s : std_logic; + signal nmi_n_s : std_logic; + signal mreq_n_s : std_logic; + signal rd_n_s : std_logic; + signal wr_n_s : std_logic; + signal rfsh_n_s : std_logic; + signal m1_n_s : std_logic; + signal a_s : std_logic_vector(15 downto 0); + signal d_to_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_rom_s, + d_decrypted_s, + d_rom_mux_s : std_logic_vector( 7 downto 0); + signal d_from_ram_s : std_logic_vector( 7 downto 0); + signal d_from_gpio_s : std_logic_vector( 7 downto 0); + + signal cs_n_s : std_logic_vector(15 downto 0); + + signal ram_cpu_cs_n_s : std_logic; + + signal vcc_s : std_logic; + +begin + vcc_s <= '1'; + + wait_n_s <= sound_wait_n_i and wait_n_i; + + ----------------------------------------------------------------------------- + -- The T80 CPU + ----------------------------------------------------------------------------- + -- "wait" has to be modelled with the clock enable because the T80 is not + -- able to enlarge write accesses properly when they are delayed with "wait" + t80_clk_en_s <= clk_en_4mhz_i and wait_n_s; + T80a_b : entity work.T80a + generic map ( + Mode => 0 + ) + port map ( + RESET_n => res_n_i, + CLK_n => clk_20mhz_i, + CLK_EN_SYS => t80_clk_en_s, + WAIT_n => wait_n_s, + INT_n => int_n_s, + NMI_n => nmi_n_s, + BUSRQ_n => vcc_s, + M1_n => m1_n_s, + MREQ_n => mreq_n_s, + IORQ_n => open, + RD_n => rd_n_s, + WR_n => wr_n_s, + RFSH_n => rfsh_n_s, + HALT_n => open, + BUSAK_n => open, + A => a_s, + DI => d_to_cpu_s, + DO => d_from_cpu_s + ); + d_from_cpu_o <= d_from_cpu_s; + + + ----------------------------------------------------------------------------- + -- The CPU RAM + ----------------------------------------------------------------------------- + cpu_ram_b : entity work.ladybug_cpu_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => a_s(11 downto 0), + cs_n_i => cs_n_s(6), + we_n_i => wr_n_s, + d_i => d_from_cpu_s, + d_o => d_from_ram_s + ); + + ----------------------------------------------------------------------------- + -- The Address Decoder + ----------------------------------------------------------------------------- + addr_dec_b : entity work.ladybug_addr_dec + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + a_i => a_s(15 downto 12), + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + mreq_n_i => mreq_n_s, + rfsh_n_i => rfsh_n_s, + cs_n_o => cs_n_s, + ram_cpu_cs_n_o => ram_cpu_cs_n_s + ); + + + ----------------------------------------------------------------------------- + -- The General Purpose IO + ----------------------------------------------------------------------------- + gpio_b : entity work.ladybug_gpio + port map ( + a_i => a_s(1 downto 0), + cs_in_n_i => cs_n_s(9), + cs_extra_n_i => cs_n_s(14), + in0_i => gpio_in0_i, + in1_i => gpio_in1_i, + in2_i => gpio_in2_i, + in3_i => gpio_in3_i, + extra_i => gpio_extra_i, + d_o => d_from_gpio_s + ); + + + ----------------------------------------------------------------------------- + -- The Coin Chutes + ----------------------------------------------------------------------------- + coin_chutes_b : entity work.ladybug_chutes + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + cs8_n_i => cs_n_s(8), + nmi_n_o => nmi_n_s, + int_n_o => int_n_s + ); + + + ----------------------------------------------------------------------------- + -- Decrytion PROMs + ----------------------------------------------------------------------------- + + decrypt_prom : entity work.prom_decrypt + port map ( + CLK => clk_20mhz_i, + ADDR => rom_cpu_d_i, + DATA => d_decrypted_s + ); + + ----------------------------------------------------------------------------- + -- Only opcodes (i.e. instruction fetches) have to be decrypted + ----------------------------------------------------------------------------- + d_rom_mux_s <= d_decrypted_s when m1_n_s = '0' else rom_cpu_d_i; + + ----------------------------------------------------------------------------- + -- Gate Data Bus from ROM + -- The ROM puts data on the data bus within the CPU Main Unit so we do + -- gating here. + ----------------------------------------------------------------------------- + d_from_rom_s <= d_rom_mux_s + when cs_n_s(0) = '0' or cs_n_s(1) = '0' or cs_n_s(2) = '0' or + cs_n_s(3) = '0' or cs_n_s(4) = '0' or cs_n_s(5) = '0' else + (others => '1'); + + + ----------------------------------------------------------------------------- + -- Combine Data Buses + -- Uses an AND of all incoming buses from submodules. Each module has to + -- drive ones when not active so we can save logic complexity here. + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_to_cpu_i and d_from_rom_s and d_from_ram_s and d_from_gpio_s; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + a_o <= a_s(10 downto 0); + rom_cpu_a_o <= a_s(14 downto 0); + rd_n_o <= rd_n_s; + wr_n_o <= wr_n_s; + cs7_n_o <= cs_n_s(7); + cs10_n_o <= cs_n_s(10); + cs11_n_o <= cs_n_s(11); + cs12_n_o <= cs_n_s(12); + cs13_n_o <= cs_n_s(13); + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_dip_pack.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_dip_pack.vhd new file mode 100644 index 00000000..ebff8ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_dip_pack.vhd @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------- +-- +-- $Id: ladybug_dip_pack-p.vhd,v 1.4 2005/10/10 20:52:04 arnim Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package ladybug_dip_pack is + + ----------------------------------------------------------------------------- + -- DIP switch settings for Lady Bug + ----------------------------------------------------------------------------- + constant lb_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- High Score Initials ---------------------------------------------------- + -- 0 = 3-Letter Initials + -- 1 = 10-Letter Initials + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + ----------------------------------------------------------------------------- + -- DIP switch settings for Dorodon + ----------------------------------------------------------------------------- + constant do_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- Bonus Life ------------------------------------------------------------- + -- 0 = 40000 + -- 1 = 20000 + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + + ----------------------------------------------------------------------------- + -- DIP switch settings for Cosmic Avenger + ----------------------------------------------------------------------------- + constant ca_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives per Game --------------------------------------------------------- + -- 00 = 2 Lives + -- 11 = 3 Lives + -- 10 = 4 Lives + -- 01 = 5 Lives + "01" & + -- Initial High Score ----------------------------------------------------- + -- 00 = 0 + -- 11 = 5000 + -- 10 = 8000 + -- 01 = 10000 + "11" & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- High Score Names ------------------------------------------------------- + -- 0 = 3 Letters + -- 1 = 10 Letters + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + constant price_dip_block_2_c : std_logic_vector(7 downto 0) := + -- Pricing Options -------------------------------------------------------- + -- 1111 = 1 coin 1 credit + -- 1110 = 1 coin 2 credits + -- 1101 = 1 coin 3 credits + -- 1100 = 1 coin 4 credits + -- 1011 = 1 coin 5 credits + -- 1010 = 2 coins 1 credit + -- 1001 = 2 coins 3 credits + -- 1000 = 3 coins 1 credit + -- 0111 = 3 coins 2 credit + -- 0110 = 4 coins 1 credit + -- 0101 = 1 coin 1 credit + -- 0100 = 1 coin 1 credit + -- 0011 = 1 coin 1 credit + -- 0010 = 1 coin 1 credit + -- 0001 = 1 coin 1 credit + -- 0000 = 1 coin 1 credit + -- + -- Left Chute + "1111" & + -- Right Chute + "1111"; + +end ladybug_dip_pack; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_gpio.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_gpio.vhd new file mode 100644 index 00000000..6ca21711 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_gpio.vhd @@ -0,0 +1,139 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_gpio.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- General purpose IO input for CPU Main Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_gpio is + + port ( + a_i : in std_logic_vector(1 downto 0); + cs_in_n_i : in std_logic; + cs_extra_n_i : in std_logic; + in0_i : in std_logic_vector(7 downto 0); + in1_i : in std_logic_vector(7 downto 0); + in2_i : in std_logic_vector(7 downto 0); + in3_i : in std_logic_vector(7 downto 0); + extra_i : in std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0) + ); + +end ladybug_gpio; + + +architecture rtl of ladybug_gpio is + +begin + + ----------------------------------------------------------------------------- + -- Process gpio + -- + -- Purpose: + -- Multiplex the IN and EXTRA inputs onto the data bus for CPU. + -- + gpio: process (a_i, + cs_in_n_i, + cs_extra_n_i, + in0_i, + in1_i, + in2_i, + in3_i, + extra_i) + variable cs_n_v : std_logic_vector(1 downto 0); + begin + -- default assignment with inactive bus value + d_o <= (others => '1'); + + cs_n_v := cs_extra_n_i & cs_in_n_i; + case cs_n_v is + -- IN ports and DIP switches selected ----------------------------------- + when "10" => + case a_i is + -- IN 0 addressed + when "00" => + d_o <= in0_i; + -- IN 1 addressed + when "01" => + d_o <= in1_i; + -- DIP 0 addressed + when "10" => + d_o <= in2_i; + -- DIP 1 addressed + when "11" => + d_o <= in3_i; + + when others => + null; + end case; + + -- Extra bank selected -------------------------------------------------- + when "01" => + case a_i is + when "00" => + d_o(1) <= extra_i(7); + d_o(0) <= extra_i(3); + when "01" => + d_o(1) <= extra_i(6); + d_o(0) <= extra_i(2); + when "10" => + d_o(1) <= extra_i(5); + d_o(0) <= extra_i(1); + when "11" => + d_o(1) <= extra_i(4); + d_o(0) <= extra_i(0); + when others => + null; + end case; + + when others => + null; + end case; + + end process gpio; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd new file mode 100644 index 00000000..584b8391 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_machine.vhd @@ -0,0 +1,295 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_machine.vhd,v 1.23 2006/02/07 00:44:21 arnim Exp $ +-- +-- Toplevel of the Lady Bug machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_machine is + port ( + -- Clock and Reset Interface ---------------------------------------------- + ext_res_n_i : in std_logic; + clk_20mhz_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_5mhz_o : out std_logic; + por_n_o : out std_logic; + -- Control Interface ------------------------------------------------------ + tilt_n_i : in std_logic; + player_select_n_i : in std_logic_vector( 1 downto 0); + player_fire_n_i : in std_logic_vector( 1 downto 0); + player_up_n_i : in std_logic_vector( 1 downto 0); + player_right_n_i : in std_logic_vector( 1 downto 0); + player_down_n_i : in std_logic_vector( 1 downto 0); + player_left_n_i : in std_logic_vector( 1 downto 0); + player_bomb_n_i : in std_logic_vector( 1 downto 0); + right_chute_i : in std_logic; + left_chute_i : in std_logic; + -- DIP Switch Interface --------------------------------------------------- + dip_block_1_i : in std_logic_vector( 7 downto 0); + dip_block_2_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Audio Interface -------------------------------------------------------- + audio_o : out signed( 7 downto 0); + -- CPU ROM Interface ------------------------------------------------------ + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + + +end ladybug_machine; + +architecture struct of ladybug_machine is + + -- Clock System ------------------------------------------------------------- + signal clk_en_10mhz_s, + clk_en_10mhz_n_s : std_logic; + signal clk_en_5mhz_s, + clk_en_5mhz_n_s : std_logic; + signal clk_en_4mhz_s : std_logic; + + -- Reset System ------------------------------------------------------------- + signal por_n_s : std_logic; + signal res_n_s : std_logic; + + signal sound_wait_n_s : std_logic; + signal wait_n_s : std_logic; + signal a_s : std_logic_vector(10 downto 0); + signal d_to_cpu_s, + d_from_cpu_s, + d_from_video_s : std_logic_vector( 7 downto 0); + signal rd_n_s, + wr_n_s : std_logic; + signal cs7_n_s, + cs10_n_s, + cs11_n_s, + cs12_n_s, + cs13_n_s : std_logic; + signal vc_s, + vbl_tick_n_s, + vbl_buf_s : std_logic; + + signal gpio_in0_s, + gpio_in1_s, + gpio_in2_s, + gpio_in3_s, + gpio_extra_s : std_logic_vector( 7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk_b : entity work.ladybug_clk + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + clk_en_10mhz_o => clk_en_10mhz_s, + clk_en_10mhz_n_o => clk_en_10mhz_n_s, + clk_en_5mhz_o => clk_en_5mhz_s, + clk_en_5mhz_n_o => clk_en_5mhz_n_s, + clk_en_4mhz_o => clk_en_4mhz_s + ); + -- + clk_en_5mhz_o <= clk_en_5mhz_s; + clk_en_10mhz_o <= clk_en_10mhz_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + res_b : entity work.ladybug_res + port map ( + clk_20mhz_i => clk_20mhz_i, + ext_res_n_i => ext_res_n_i, + res_n_o => res_n_s, + por_n_o => por_n_s + ); + -- + por_n_o <= por_n_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Joystick and DIP Switch Mapping + ----------------------------------------------------------------------------- + gpio_in0_s <= tilt_n_i & + player_select_n_i(1) & + player_select_n_i(0) & + player_fire_n_i(0) & + player_up_n_i(0) & + player_right_n_i(0) & + player_down_n_i(0) & + player_left_n_i(0); + gpio_in1_s <= vbl_buf_s & + vbl_tick_n_s & + vc_s & + player_fire_n_i(1) & + player_up_n_i(1) & + player_right_n_i(1) & + player_down_n_i(1) & + player_left_n_i(1); + gpio_in2_s <= dip_block_1_i; + gpio_in3_s <= dip_block_2_i; + gpio_extra_s <= player_bomb_n_i(1) & + '1' & + '1' & + '1' & + player_bomb_n_i(0) & + '1' & + '1' & + '1'; + + + ----------------------------------------------------------------------------- + -- CPU Unit + ----------------------------------------------------------------------------- + cpu_b : entity work.ladybug_cpu_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + res_n_i => res_n_s, + rom_cpu_a_o => rom_cpu_a_o, + rom_cpu_d_i => rom_cpu_d_i, + + sound_wait_n_i => sound_wait_n_s, + wait_n_i => wait_n_s, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + gpio_in0_i => gpio_in0_s, + gpio_in1_i => gpio_in1_s, + gpio_in2_i => gpio_in2_s, + gpio_in3_i => gpio_in3_s, + gpio_extra_i => gpio_extra_s, + a_o => a_s, + d_to_cpu_i => d_to_cpu_s, + d_from_cpu_o => d_from_cpu_s, + rd_n_o => rd_n_s, + wr_n_o => wr_n_s, + cs7_n_o => cs7_n_s, + cs10_n_o => cs10_n_s, + cs11_n_o => cs11_n_s, + cs12_n_o => cs12_n_s, + cs13_n_o => cs13_n_s + ); + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_from_video_s when (cs7_n_s and cs13_n_s) = '0' else (others => '1'); + + ----------------------------------------------------------------------------- + -- Video Unit + ----------------------------------------------------------------------------- + video_b : entity work.ladybug_video_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + res_n_i => res_n_s, + clk_en_10mhz_i => clk_en_10mhz_s, + clk_en_10mhz_n_i => clk_en_10mhz_n_s, + clk_en_5mhz_i => clk_en_5mhz_s, + clk_en_5mhz_n_i => clk_en_5mhz_n_s, + clk_en_4mhz_i => clk_en_4mhz_s, + cs7_n_i => cs7_n_s, + cs10_n_i => cs10_n_s, + cs13_n_i => cs13_n_s, + a_i => a_s, + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + wait_n_o => wait_n_s, + d_from_cpu_i => d_from_cpu_s, + d_from_video_o => d_from_video_s, + vc_o => vc_s, + vbl_tick_n_o => vbl_tick_n_s, + vbl_buf_o => vbl_buf_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n_o, + vblank_o => vblank_o, + hblank_o => hblank_o, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + ----------------------------------------------------------------------------- + -- Sound Unit + ----------------------------------------------------------------------------- + sound_b : entity work.ladybug_sound_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + por_n_i => por_n_s, + cs11_n_i => cs11_n_s, + cs12_n_i => cs12_n_s, + wr_n_i => wr_n_s, + d_from_cpu_i => d_from_cpu_s, + sound_wait_n_o => sound_wait_n_s, + audio_o => audio_o + ); + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_rams.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_rams.vhd new file mode 100644 index 00000000..578d08e7 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_rams.vhd @@ -0,0 +1,340 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_char_ram; + +architecture struct of ladybug_char_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_sprite_ram; + +architecture struct of ladybug_sprite_ram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_col_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character color RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_col_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_char_col_ram; + +architecture struct of ladybug_char_col_ram is + + signal d_s : std_logic_vector(3 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_vram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite VRAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_vram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_sprite_vram; + +architecture struct of ladybug_sprite_vram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_ram.vhd,v 1.1 2005/11/06 15:43:38 arnim Exp $ +-- +-- Wrapper for technology dependent CPU RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 4 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(11 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_cpu_ram; + +architecture struct of ladybug_cpu_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram1_inst: work.spram generic map(12,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_res.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_res.vhd new file mode 100644 index 00000000..85998a10 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_res.vhd @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_res.vhd,v 1.8 2005/10/10 20:52:04 arnim Exp $ +-- +-- Reset generator for the Lady Bug machine. +-- +-- This module generates a reset signal for the whole system synchronous to +-- the main clock. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity ladybug_res is + + port ( + clk_20mhz_i : in std_logic; + ext_res_n_i : in std_logic; + res_n_o : out std_logic; + por_n_o : out std_logic + ); + +end ladybug_res; + +architecture rtl of ladybug_res is + + -- 4.7e-2 s = 1 / 20,000,000 Hz * 940000 + constant res_delay_c : natural := 940000; + + signal res_sync_n_q : std_logic_vector(1 downto 0); + + signal res_delay_q : unsigned(19 downto 0); + signal res_n_q : std_logic; + + signal por_cnt_q : unsigned(1 downto 0) := "00"; + signal por_n_q : std_logic := '0'; +begin + + por_n_o <= por_n_q; + res_n_o <= res_n_q; + + ----------------------------------------------------------------------------- + -- Process por_cnt + -- + -- Purpose: + -- Generate a power-on reset for 4 clock cycles. + -- + por_cnt: process (clk_20mhz_i) + begin + if clk_20mhz_i'event and clk_20mhz_i = '1' then + if por_cnt_q = "11" then + por_n_q <= '1'; + else + por_cnt_q <= por_cnt_q + 1; + end if; + end if; + end process por_cnt; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_sync + -- + -- Purpose: + -- Synchronize asynchronous external reset to main 20 MHz clock. + -- + res_sync: process (clk_20mhz_i, ext_res_n_i, por_n_q) + begin + if ext_res_n_i = '0' or por_n_q = '0' then + res_sync_n_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + res_sync_n_q(0) <= '1'; + res_sync_n_q(1) <= res_sync_n_q(0); + end if; + end process res_sync; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_delay + -- + -- Purpose: + -- Delay reset event (external or power-on) by 4.7e-2 s. + -- Reset delay is taken from Lady Bug reset circuit using NE555. + -- This duration might be too long for the actual requirements of the + -- FPGA circuit. + -- + res_delay: process (clk_20mhz_i, res_sync_n_q) + begin + if res_sync_n_q(1) = '0' then + res_delay_q <= (others => '0'); + res_n_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if res_delay_q = res_delay_c then + res_n_q <= '1'; + else + res_delay_q <= res_delay_q + 1; + end if; + end if; + end process res_delay; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_rgb.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_rgb.vhd new file mode 100644 index 00000000..1bfcd53c --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_rgb.vhd @@ -0,0 +1,135 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_rgb.vhd,v 1.4 2005/10/10 22:02:14 arnim Exp $ +-- +-- RGB Generation Module of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_rgb is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + crg_i : in std_logic_vector(5 downto 1); + sig_i : in std_logic_vector(4 downto 1); + rgb_r_o : out std_logic_vector(1 downto 0); + rgb_g_o : out std_logic_vector(1 downto 0); + rgb_b_o : out std_logic_vector(1 downto 0) + ); + +end ladybug_rgb; + +architecture rtl of ladybug_rgb is + + signal a_s : std_logic_vector(5 downto 1); + signal rgb_s : std_logic_vector(8 downto 1); + signal rgb_n_q : std_logic_vector(8 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process addr + -- + -- Purpose: + -- Generates the PROM address. + -- + addr: process (crg_i, + sig_i) + variable sig_and_v : std_logic; + begin + sig_and_v := sig_i(1) and sig_i(2) and sig_i(3) and sig_i(4); + + a_s(5) <= crg_i(1) and sig_and_v; + + if not (sig_and_v and (crg_i(1) or crg_i(2))) = '0' then + a_s(4 downto 1) <= crg_i(2) & crg_i(5) & crg_i(4) & crg_i(3); + else + a_s(4 downto 1) <= sig_i; + end if; + + end process addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The RGB Conversion PROM + ----------------------------------------------------------------------------- + rgb_prom_b : entity work.prom_10_2 + port map ( + CLK => clk_20mhz_i, + ADDR => a_s, + DATA => rgb_s + ); + + ----------------------------------------------------------------------------- + -- Process rgb_latch + -- + -- Purpose: + -- Implements the output latch for the RGB values. + -- + rgb_latch: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rgb_n_q <= (others => '1'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + rgb_n_q <= not rgb_s; + end if; + end if; + end process rgb_latch; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rgb_r_o <= rgb_n_q(5+1) & rgb_n_q(0+1); + rgb_g_o <= rgb_n_q(6+1) & rgb_n_q(2+1); + rgb_b_o <= rgb_n_q(7+1) & rgb_n_q(4+1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sprite.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sprite.vhd new file mode 100644 index 00000000..941d997c --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sprite.vhd @@ -0,0 +1,857 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite.vhd,v 1.12 2005/10/10 22:02:14 arnim Exp $ +-- +-- Sprite Video Module of Lady Bug Machine. +-- +-- This unit contains the whole sprite logic which is distributed on the +-- CPU and video boards. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_sprite is +port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + a_i : in std_logic_vector( 9 downto 0); + d_from_cpu_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + hx_i : in std_logic; + ha_d_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_d_i : in std_logic; + blank_flont_i : in std_logic; + blank_i : in std_logic; + sig_o : out std_logic_vector( 4 downto 1); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) +); + +end ladybug_sprite; + +architecture rtl of ladybug_sprite is + + signal sprite_ram_cs_n_s, + sprite_ram_we_n_s, + clk_5mhz_n_q, + clk_en_eck_s, + clk_en_rd_s, + clk_en_5ck_n_s, + clk_en_6ck_n_s, + clk_en_7ck_n_s, + clk_en_b7_p3_s, + clk_en_e7_3_s, + s6ck_n_s, + s7ck_n_s, + e5_p8_s, + a8_p5_n_s, + ct0_s, + ct1_s, + cr_mux_sel_s, + ck_inh_s, + ck_inh_n_q, + qh1_s, + qh2_s : std_logic; + + signal rb_s, + rb_unflip_s, + rc_s : std_logic_vector( 7 downto 0); + + signal c_s : std_logic_vector(10 downto 0); + signal v_cnt_s : std_logic_vector( 4 downto 0); + signal ra_s : std_logic_vector( 9 downto 0); + + signal ma_s : std_logic_vector(11 downto 0); + signal ma_q : std_logic_vector(11 downto 6); + signal mb_q : std_logic_vector( 1 downto 0); + signal mc_q : std_logic_vector( 6 downto 0); + signal cl_q : std_logic_vector( 4 downto 0); + + signal j7_s : std_logic_vector( 2 downto 0); + signal df_muxed_s : std_logic_vector( 7 downto 0); + + signal lu_a_s : std_logic_vector( 4 downto 0); + signal lu_d_s : std_logic_vector( 7 downto 0); + signal lu_d_mux_s : std_logic_vector( 3 downto 0); + + signal rd_shift_s, + rd_shift_int, + rd_vram_s : std_logic_vector(15 downto 0); + signal rs_s, + rs_int, + rs_n_s : std_logic_vector( 3 downto 0); + signal rs_enable_s : std_logic; + signal shift_oc_n_s : std_logic; + + signal j6_shifter : std_logic_vector( 3 downto 0); + signal h6_shifter : std_logic_vector( 3 downto 0); + signal ctrl_lu_a_s : std_logic_vector( 4 downto 0); + signal ctrl_lu_d_s : std_logic_vector( 7 downto 0); + signal v_cnt_a5_a6_s : std_logic_vector( 7 downto 0); + + signal ctrl_lu_q_d_s, + ctrl_lu_q : std_logic_vector( 6 downto 1); + + signal vram_we_n_s : std_logic; + signal vram_a6_in_s, + vram_a6_out_s, + vram_b6_in_s, + vram_b6_out_s, + vram_c6_in_s, + vram_c6_out_s, + vram_d6_in_s, + vram_d6_out_s : std_logic_vector( 3 downto 0); + + signal ca_q : std_logic_vector( 3 downto 1); + signal ca6_s, + ca7_s, + ca8_s : std_logic; + signal x_s : std_logic_vector( 5 downto 0); + + signal cr_s : std_logic_vector( 9 downto 0); + + signal vram_q : std_logic_vector(15 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- The Vertical Counters C5 D5 + ----------------------------------------------------------------------------- + v_cnt_c5_c6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_b7_p3_s = '1' then + if e5_p8_s = '0' then + v_cnt_s <= (v_t_i & "0"); + else + v_cnt_s <= v_cnt_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Counter J7 + ----------------------------------------------------------------------------- + j7_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + j7_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s6ck_n_s = '0' then + j7_s <= not mc_q(6) & mc_q(6) & '0'; + elsif (ct0_s or ct1_s or a8_p5_n_s or ck_inh_s) = '0' then + j7_s <= j7_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Sprite VRAM Counters A5 A6 + ----------------------------------------------------------------------------- + ct0_s <= v_cnt_a5_a6_s(0); + ct1_s <= v_cnt_a5_a6_s(1); + x_s <= v_cnt_a5_a6_s(7 downto 2); + + v_cnt_a5_a6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_a5_a6_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s7ck_n_s = '0' then + v_cnt_a5_a6_s(7 downto 4) <= (rb_s(7 downto 4)); + v_cnt_a5_a6_s(3 downto 0) <= (rb_s(3 downto 2) & not rc_s(7) & not rc_s(6)); + elsif ck_inh_n_q = '1' then + v_cnt_a5_a6_s <=v_cnt_a5_a6_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process sprite_ram_ctrl + -- + -- Purpose: + -- Generates the control signals for the sprite RAM. + -- + sprite_ram_ctrl: process ( cs7_n_i, + vbl_n_i, + a_i, + c_s, v_cnt_s) + variable cpu_access_v : std_logic; + begin + cpu_access_v := not cs7_n_i and not vbl_n_i; + + sprite_ram_we_n_s <= not cpu_access_v; + sprite_ram_cs_n_s <= cpu_access_v nor vbl_n_i; + + if vbl_n_i = '0' then + ra_s <= a_i; + else + ra_s <= v_cnt_s(4 downto 0) & c_s(4 downto 0); + end if; + end process sprite_ram_ctrl; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Sprite RAM P5 N5 + ----------------------------------------------------------------------------- + sprite_ram_b : entity work.ladybug_sprite_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_5mhz_i, + a_i => ra_s, + cs_n_i => sprite_ram_cs_n_s, + we_n_i => sprite_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => rb_s + ); + + ----------------------------------------------------------------------------- + -- Process rc_add + -- + -- Purpose: + -- Implements IC N6 and E6 which add sprite RAM data and Cx signals to + -- form RCx bus. + -- + rc_add: process (rb_s, c_s, v_i) + variable a_v, b_v, + sum_v : std_logic_vector(7 downto 0); + begin + -- prepare the inputs of the adder + a_v(3 downto 0) := rb_s(3 downto 0); + a_v(4) := '1'; + a_v(5) := '0'; + a_v(7 downto 6) := rb_s(1 downto 0); + + b_v(0) := not c_s(6); + b_v(1) := not c_s(7); + b_v(2) := not c_s(8); + b_v(3) := not v_i(3); + b_v(4) := c_s(10); + b_v(5) := '0'; + b_v(7 downto 6) := "11"; + + sum_v := a_v + b_v; + + rc_s <= sum_v; + + end process rc_add; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Sprite Control Logic + ----------------------------------------------------------------------------- + sprite_ctrl_b : entity work.ladybug_sprite_ctrl + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + por_n_i => por_n_i, + vbl_n_i => vbl_n_i, + vbl_d_n_i => vbl_d_n_i, + vc_i => v_i(2), + vc_d_i => vc_d_i, + ha_i => h_i(0), + ha_d_i => ha_d_i, + rb6_i => rb_s(6), + rb7_i => rb_s(7), + rc3_i => rc_s(3), + rc4_i => rc_s(4), + rc5_i => rc_s(5), + j7_b_i => j7_s(1), + j7_c_i => j7_s(2), + clk_en_eck_i => clk_en_eck_s, + c_o => c_s, + clk_en_5ck_n_o => clk_en_5ck_n_s, + clk_en_6ck_n_o => clk_en_6ck_n_s, + clk_en_7ck_n_o => clk_en_7ck_n_s, + s6ck_n_o => s6ck_n_s, + s7ck_n_o => s7ck_n_s, + clk_en_b7_p3_o => clk_en_b7_p3_s, + e5_p8_o => e5_p8_s, + clk_en_e7_3_o => clk_en_e7_3_s, + a8_p5_n_o => a8_p5_n_s + ); + + ----------------------------------------------------------------------------- + -- Process misc_seq + -- + -- Purpose: + -- Implements several sequential elements. + -- + misc_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_n_q <= '0'; + ma_q <= (others => '0'); + mb_q <= (others => '0'); + mc_q <= (others => '0'); + cl_q <= (others => '0'); + ck_inh_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz_n into clock waveform ---------------------------------- + if clk_en_5mhz_n_i = '1' then + clk_5mhz_n_q <= '1'; + elsif clk_en_5mhz_i = '1' then + clk_5mhz_n_q <= '0'; + end if; + + -- 8-Bit Register M6 ---------------------------------------------------- + if clk_en_5ck_n_s = '1' then + mb_q <= rb_s(1 downto 0); + ma_q <= rb_s(7 downto 2); + end if; + + -- 8-Bit Register P6 ---------------------------------------------------- + if clk_en_e7_3_s = '1' then + -- these are inverted based on mc_q(4) + mc_q(3 downto 0) <= rc_s(3 downto 0); + -- inverts sprites horizontally + mc_q(4) <= rb_s(4); + -- inverts sprites vertically + mc_q(5) <= rb_s(5); + -- + mc_q(6) <= rb_s(6); + end if; + + -- 6-Bit Register B6 ---------------------------------------------------- + if clk_en_6ck_n_s = '1' then + cl_q <= rb_s(4 downto 0); + end if; + + -- Flip-Flop H8 --------------------------------------------------------- + if clk_en_10mhz_n_i = '1' then + ck_inh_n_q <= not ck_inh_s; + end if; + + end if; + end process misc_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ma_vec + -- + -- Purpose: + -- Build the ma_s vector. + -- + ma_vec: process ( ma_q, + mb_q, + mc_q, + j7_s) + begin + ma_s(11 downto 6) <= ma_q; + + if mc_q(6) = '0' then + ma_s(5) <= mb_q(1); + ma_s(4) <= mb_q(0); + else + ma_s(5) <= mc_q(3) xor mc_q(4); + ma_s(4) <= mc_q(5) xor j7_s(2); + end if; + + ma_s(3) <= mc_q(2) xor mc_q(4); + ma_s(2) <= mc_q(1) xor mc_q(4); + ma_s(1) <= mc_q(0) xor mc_q(4); + ma_s(0) <= mc_q(5) xor j7_s(0); + end process ma_vec; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process df_mux + -- + -- Purpose: + -- Builds the multiplexed data from Sprite ROM. + -- Two-stage multiplexer: + -- 1) ROM data to DFx: 16->8 + -- 2) DF to input for shift register: 8->8 + -- This is actually a scrambler. + -- + df_mux: process ( rom_sprite_d_i, + cl_q, + mc_q) + variable df_v : std_logic_vector(7 downto 0); + begin + if cl_q(4) = '0' then + -- ROM L7 + df_v := rom_sprite_d_i( 7 downto 0); + else + -- ROM M7 + df_v := rom_sprite_d_i(15 downto 8); + end if; + + if mc_q(5) = '0' then + df_muxed_s(0) <= df_v(1); + df_muxed_s(1) <= df_v(3); + df_muxed_s(2) <= df_v(5); + df_muxed_s(3) <= df_v(7); + -- + df_muxed_s(4) <= df_v(0); + df_muxed_s(5) <= df_v(2); + df_muxed_s(6) <= df_v(4); + df_muxed_s(7) <= df_v(6); + else + df_muxed_s(0) <= df_v(7); + df_muxed_s(1) <= df_v(5); + df_muxed_s(2) <= df_v(3); + df_muxed_s(3) <= df_v(1); + -- + df_muxed_s(4) <= df_v(6); + df_muxed_s(5) <= df_v(4); + df_muxed_s(6) <= df_v(2); + df_muxed_s(7) <= df_v(0); + end if; + + end process df_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Two 8-Bit Shift Registers H6 J6 + ----------------------------------------------------------------------------- + shifters_h6_j6 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + h6_shifter <= (others=>'0'); + j6_shifter <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + if (ct0_s or ct1_s or a8_p5_n_s) = '0' then + h6_shifter <= df_muxed_s(3 downto 0); + j6_shifter <= df_muxed_s(7 downto 4); + else + h6_shifter <= h6_shifter(2 downto 0) & "0"; + j6_shifter <= j6_shifter(2 downto 0) & "0"; + end if; + end if; + end if; + end process; + + qh1_s <= h6_shifter(3); + qh2_s <= j6_shifter(3); + + ----------------------------------------------------------------------------- + -- Sprite Look-up PROM F4 + ----------------------------------------------------------------------------- + lu_a_s(4 downto 2) <= cl_q(2 downto 0); + lu_a_s(1) <= qh2_s; + lu_a_s(0) <= qh1_s; + + prom_F4 : entity work.prom_10_1 + port map ( + CLK => clk_20mhz_i, + ADDR => lu_a_s, + DATA => lu_d_s + ); + + lu_d_mux_s <= lu_d_s(3 downto 0) when cl_q(3) = '0' else lu_d_s(7 downto 4); + + ----------------------------------------------------------------------------- + -- Sprite Control Look-up PROM C4 + ----------------------------------------------------------------------------- + ctrl_lu_a_s(0) <= '1'; + ctrl_lu_a_s(1) <= hx_i; + ctrl_lu_a_s(2) <= clk_5mhz_n_q; + ctrl_lu_a_s(3) <= h_i(0); + ctrl_lu_a_s(4) <= h_i(1); + + prom_C4 : entity work.prom_10_3 + port map ( + CLK => clk_20mhz_i, + ADDR => ctrl_lu_a_s, + DATA => ctrl_lu_d_s + ); + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_seq + -- + -- Purpose: + -- Registers output of Sprite Control Look-up PROM. + -- + ctrl_lu_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ctrl_lu_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + ctrl_lu_q <= ctrl_lu_q_d_s; + end if; + end process ctrl_lu_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_comb + -- + -- Purpose: + -- Combinational logic for the sprite control registers. + -- + ctrl_lu_comb: process ( clk_en_10mhz_i, + ctrl_lu_d_s, + ctrl_lu_q, + ctrl_lu_q_d_s) + begin + -- default assignments + ctrl_lu_q_d_s <= ctrl_lu_q; + clk_en_eck_s <= '0'; + clk_en_rd_s <= '0'; + + -- register control + if clk_en_10mhz_i = '1' then + ctrl_lu_q_d_s <= ctrl_lu_d_s(5 downto 0); + + if ctrl_lu_q(1) = '0' and ctrl_lu_q_d_s(1) = '1' then + -- detect rising edge on ctrl_lu_q(1) + clk_en_eck_s <= '1'; + end if; + + if ctrl_lu_q(6) = '0' and ctrl_lu_q_d_s(6) = '1' then + -- detect rising edge on ctrl_lu_q(6) + clk_en_rd_s <= '1'; + end if; + end if; + + end process ctrl_lu_comb; + -- + shift_oc_n_s <= ctrl_lu_q(1) nand res_n_i; + ck_inh_s <= ctrl_lu_q(2); + cr_mux_sel_s <= ctrl_lu_q(3); + vram_we_n_s <= ctrl_lu_q(4); + rs_enable_s <= ctrl_lu_q(5); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ca_seq + -- + -- Purpose: + -- Implements B5, the register that holds the CS flip-flops. + -- + ca_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ca_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_7ck_n_s = '1' then + ca_q <= c_s(8 downto 6); + end if; + end if; + end process ca_seq; + -- + ca6_s <= ca_q(1); + ca7_s <= ca_q(2); + ca8_s <= ca_q(3); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process vram_mux + -- + -- Purpose: + -- Generates the VRAM address CRx. + -- It implements chips D5, C5 and B5. + -- + vram_mux: process ( h_i, h_t_i, + v_i, + x_s, + ca6_s, ca7_s, ca8_s, + cr_mux_sel_s) + begin + if cr_mux_sel_s = '0' then + -- D5 + cr_s(0) <= h_i(2); + cr_s(1) <= h_i(3); + cr_s(2) <= h_t_i(0); + cr_s(3) <= h_t_i(1); + -- C5 + cr_s(4) <= h_t_i(2); + cr_s(5) <= h_t_i(3); + cr_s(6) <= v_i(0); + cr_s(7) <= v_i(1); + -- B5 + cr_s(8) <= v_i(2); + cr_s(9) <= v_i(3); + + else + -- D5 + cr_s(0) <= x_s(0); + cr_s(1) <= x_s(1); + cr_s(2) <= x_s(2); + cr_s(3) <= x_s(3); + -- C5 + cr_s(4) <= x_s(4); + cr_s(5) <= x_s(5); + cr_s(6) <= ca6_s; + cr_s(7) <= ca7_s; + -- B5 + cr_s(8) <= ca8_s; + cr_s(9) <= not v_i(3); + + end if; + end process vram_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Shift Registers + ----------------------------------------------------------------------------- + shifters_a7_a8_d7_d8_f8 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rd_shift_int <= (others=>'1'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + rs_int <= (qh1_s nor qh2_s) & rs_int(3 downto 1); + rd_shift_int <= + lu_d_mux_s(0) & rd_shift_int(15 downto 13) & + lu_d_mux_s(1) & rd_shift_int(11 downto 9) & + lu_d_mux_s(2) & rd_shift_int( 7 downto 5) & + lu_d_mux_s(3) & rd_shift_int( 3 downto 1); + end if; + end if; + end process; + + rd_shift_s <= rd_shift_int when shift_oc_n_s = '0' else (others=>'1'); + rs_s <= rs_int when shift_oc_n_s = '0' else (others=>'1'); +-- rs_n_s(3) <= not rs_s(3) or not rs_enable_s; +-- rs_n_s(2) <= not rs_s(2) or not rs_enable_s; +-- rs_n_s(1) <= not rs_s(1) or not rs_enable_s; +-- rs_n_s(0) <= not rs_s(0) or not rs_enable_s; + rs_n_s(3) <= rs_s(3) and rs_enable_s; + rs_n_s(2) <= rs_s(2) and rs_enable_s; + rs_n_s(1) <= rs_s(1) and rs_enable_s; + rs_n_s(0) <= rs_s(0) and rs_enable_s; + + ----------------------------------------------------------------------------- + -- Sprite VRAM + ----------------------------------------------------------------------------- + vram_a6_in_s(0) <= rd_shift_s( 0); + vram_a6_in_s(1) <= rd_shift_s( 4); + vram_a6_in_s(2) <= rd_shift_s( 8); + vram_a6_in_s(3) <= rd_shift_s(12); + vram_a6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(0), + we_n_i => vram_we_n_s, + d_i => vram_a6_in_s, + d_o => vram_a6_out_s + ); + -- + vram_b6_in_s(0) <= rd_shift_s( 1); + vram_b6_in_s(1) <= rd_shift_s( 5); + vram_b6_in_s(2) <= rd_shift_s( 9); + vram_b6_in_s(3) <= rd_shift_s(13); + vram_b6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(1), + we_n_i => vram_we_n_s, + d_i => vram_b6_in_s, + d_o => vram_b6_out_s + ); + -- + vram_c6_in_s(0) <= rd_shift_s( 2); + vram_c6_in_s(1) <= rd_shift_s( 6); + vram_c6_in_s(2) <= rd_shift_s(10); + vram_c6_in_s(3) <= rd_shift_s(14); + vram_c6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(2), + we_n_i => vram_we_n_s, + d_i => vram_c6_in_s, + d_o => vram_c6_out_s + ); + -- + vram_d6_in_s(0) <= rd_shift_s( 3); + vram_d6_in_s(1) <= rd_shift_s( 7); + vram_d6_in_s(2) <= rd_shift_s(11); + vram_d6_in_s(3) <= rd_shift_s(15); + vram_d6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(3), + we_n_i => vram_we_n_s, + d_i => vram_d6_in_s, + d_o => vram_d6_out_s + ); + -- Remap VRAM data outputs to the complete bus ------------------------------ + rd_vram_s(15) <= vram_d6_out_s(3) or rs_n_s(3); + rd_vram_s(14) <= vram_c6_out_s(3) or rs_n_s(2); + rd_vram_s(13) <= vram_b6_out_s(3) or rs_n_s(1); + rd_vram_s(12) <= vram_a6_out_s(3) or rs_n_s(0); + -- + rd_vram_s(11) <= vram_d6_out_s(2) or rs_n_s(3); + rd_vram_s(10) <= vram_c6_out_s(2) or rs_n_s(2); + rd_vram_s( 9) <= vram_b6_out_s(2) or rs_n_s(1); + rd_vram_s( 8) <= vram_a6_out_s(2) or rs_n_s(0); + -- + rd_vram_s( 7) <= vram_d6_out_s(1) or rs_n_s(3); + rd_vram_s( 6) <= vram_c6_out_s(1) or rs_n_s(2); + rd_vram_s( 5) <= vram_b6_out_s(1) or rs_n_s(1); + rd_vram_s( 4) <= vram_a6_out_s(1) or rs_n_s(0); + -- + rd_vram_s( 3) <= vram_d6_out_s(0) or rs_n_s(3); + rd_vram_s( 2) <= vram_c6_out_s(0) or rs_n_s(2); + rd_vram_s( 1) <= vram_b6_out_s(0) or rs_n_s(1); + rd_vram_s( 0) <= vram_a6_out_s(0) or rs_n_s(0); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process rd_seq + -- + -- Purpose: + -- Implements the registers saving the RDx bus. + -- + rd_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + vram_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if blank_flont_i = '0' then + -- pseudo-asynchronous clear + vram_q <= (others => '0'); + + elsif clk_en_rd_s = '1' then + if shift_oc_n_s = '0' then + -- take data from shift registers + vram_q <= rd_shift_s; + else + -- take data from VRAM + vram_q <= rd_vram_s; + end if; + end if; + end if; + end process rd_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process sig_mux + -- + -- Purpose: + -- Multiplexes the saved VRAM data to generate the four SIG outputs. + -- + sig_mux: process (vram_q, + h_i, + blank_i) + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + sig_o <= (others => '0'); + + vec_v := (h_i(1) & h_i(0)); + + if blank_i = '0' then + case vec_v is + when "00" => + sig_o(1) <= vram_q( 1); + sig_o(2) <= vram_q( 5); + sig_o(3) <= vram_q( 9); + sig_o(4) <= vram_q(13); + when "01" => + sig_o(1) <= vram_q( 2); + sig_o(2) <= vram_q( 6); + sig_o(3) <= vram_q(10); + sig_o(4) <= vram_q(14); + when "10" => + sig_o(1) <= vram_q( 3); + sig_o(2) <= vram_q( 7); + sig_o(3) <= vram_q(11); + sig_o(4) <= vram_q(15); + when "11" => + sig_o(1) <= vram_q( 0); + sig_o(2) <= vram_q( 4); + sig_o(3) <= vram_q( 8); + sig_o(4) <= vram_q(12); + when others => + null; + end case; + end if; + end process sig_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rom_sprite_a_o <= ma_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sprite_ctrl.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sprite_ctrl.vhd new file mode 100644 index 00000000..f0eaff48 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_sprite_ctrl.vhd @@ -0,0 +1,491 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ctrl.vhd,v 1.8 2005/10/10 22:02:14 arnim Exp $ +-- +-- Control logic of the Sprite module. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +library ieee; +use ieee.numeric_std.all; + +entity ladybug_sprite_ctrl is + + port ( + clk_20mhz_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + por_n_i : in std_logic; + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_i : in std_logic; + vc_d_i : in std_logic; + ha_i : in std_logic; + ha_d_i : in std_logic; + rb6_i : in std_logic; + rb7_i : in std_logic; + rc3_i : in std_logic; + rc4_i : in std_logic; + rc5_i : in std_logic; + j7_b_i : in std_logic; + j7_c_i : in std_logic; + clk_en_eck_i : in std_logic; + c_o : out std_logic_vector(10 downto 0); + clk_en_5ck_n_o : out std_logic; + clk_en_6ck_n_o : out std_logic; + clk_en_7ck_n_o : out std_logic; + s6ck_n_o : out std_logic; + s7ck_n_o : out std_logic; + clk_en_b7_p3_o : out std_logic; + e5_p8_o : out std_logic; + clk_en_e7_3_o : out std_logic; + a8_p5_n_o : out std_logic + ); + +end ladybug_sprite_ctrl; + + +architecture rtl of ladybug_sprite_ctrl is + + signal clk_5mhz_q : std_logic; + + signal a7_p5_s, + a7_p5_q : std_logic; + signal a7_p9_q : std_logic; + + signal a8_p5_q : std_logic; + + signal n4_p5_s, + n4_p5_q : std_logic; + + signal f7_ck_en_s, + f7_cl_s, + f7_qa_s, f7_qb_s, f7_qc_s, f7_qd_s, + f7_da_s, f7_db_s, f7_dc_s, f7_dd_s : std_logic_vector(2 downto 1); + + signal j5_ck_en_s, + j5_cl_s, + j5_qa_s, j5_qb_s, j5_qc_s, j5_qd_s, + j5_da_s, j5_db_s, j5_dc_s, j5_dd_s : std_logic_vector(2 downto 1); + + signal e7_ck_en_s, + e7_cl_n_s : std_logic; + signal e7_d_s, + e7_q_s, e7_q_n_s, + e7_d_out_s, e7_d_out_n_s : std_logic_vector(4 downto 1); + + signal h5_n_s : std_logic_vector(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements various sequential elements. + -- + seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_q <= '0'; + a7_p5_q <= '0'; + a7_p9_q <= '0'; + a8_p5_q <= '0'; + n4_p5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz enable into clock waveform ----------------------------- + if clk_en_5mhz_i = '1' then + clk_5mhz_q <= '1'; + elsif clk_en_5mhz_n_i = '1' then + clk_5mhz_q <= '0'; + end if; + + -- Flip-Flop A7 --------------------------------------------------------- + a7_p5_q <= a7_p5_s; + -- + if clk_en_5mhz_n_i = '1' then + a7_p9_q <= j5_qd_s(2); + end if; + + -- Flip-Flop A8 --------------------------------------------------------- + if clk_en_eck_i = '1' then + a8_p5_q <= j7_b_i nand j7_c_i; + end if; + + -- Flip-Flop N4 --------------------------------------------------------- + n4_p5_q <= n4_p5_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements various combinational signals. + -- + comb: process (a7_p5_q, + vc_i, vc_d_i, + n4_p5_q, + ha_i, ha_d_i, + f7_qd_s) + begin + -- D Input for Flip-Flop N4 ----------------------------------------------- + if a7_p5_q = '0' then + -- pseudo-asynchronous clear + n4_p5_s <= '0'; + elsif (vc_i and not vc_d_i) = '1' then + -- falling edge on VC + n4_p5_s <= '1'; + else + n4_p5_s <= n4_p5_q; + end if; + + -- D-Input for Flip-Flop A7.5 --------------------------------------------- + if (ha_i and not ha_d_i) = '1' then + -- falling edge on HA + a7_p5_s <= f7_qd_s(2); + else + a7_p5_s <= a7_p5_q; + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- F7 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + f7_cl_s(1) <= n4_p5_q and ha_i and vbl_n_i; + f7_cl_s(2) <= f7_cl_s(1); + -- + f7_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => f7_ck_en_s, + por_n_i => por_n_i, + cl_i => f7_cl_s, + qa_o => f7_qa_s, + qb_o => f7_qb_s, + qc_o => f7_qc_s, + qd_o => f7_qd_s, + da_o => f7_da_s, + db_o => f7_db_s, + dc_o => f7_dc_s, + dd_o => f7_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process f7_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in F7. + -- + f7_ck_en: process (j5_qd_s, j5_dd_s, + vbl_n_i, vbl_d_n_i, + ha_i, ha_d_i, + n4_p5_q, n4_p5_s, + f7_qd_s, f7_dd_s, + e7_q_n_s, e7_d_out_n_s, + f7_qb_s, f7_db_s) + + variable ff_q_v, ff_d_v : std_logic; + + begin + + -- combinational result based on flip-flop outputs + ff_q_v := j5_qd_s(2) or ( not ( not ( vbl_n_i and ha_i and n4_p5_q ) ) or not ( not f7_qd_s(2) nand not e7_q_n_s(1) ) ); + + -- combinational result based on flip-flop inputs + ff_d_v := j5_dd_s(2) or ( not ( not ( vbl_d_n_i and ha_d_i and n4_p5_s ) ) or not ( not f7_qd_s(2) nand not e7_d_out_n_s(1) ) ); +-- B7.3 D7.8 D7.8 F6.3 B7.6 + -- rising edge detector on B7.3 + f7_ck_en_s(1) <= not ff_q_v and ff_d_v; + + -- falling edge detector on F7.QB(1) + f7_ck_en_s(2) <= f7_qb_s(1) and not f7_db_s(1); + + end process f7_ck_en; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- J5 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + j5_cl_s(1) <= not vbl_n_i + or -- D7.6 + not( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) + or -- D7.6 + n4_p5_q; + j5_cl_s(2) <= a7_p9_q + or -- B7.8 + ( + not ( + not ( + n4_p5_q + and -- D7.8 + ha_i + and -- D7.8 + vbl_n_i + ) + ) + or -- F6.3 + not ( + not f7_qd_s(2) + nand -- B7.6 + not e7_q_n_s(1) + ) + ); + -- + j5_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => j5_ck_en_s, + por_n_i => por_n_i, + cl_i => j5_cl_s, + qa_o => j5_qa_s, + qb_o => j5_qb_s, + qc_o => j5_qc_s, + qd_o => j5_qd_s, + da_o => j5_da_s, + db_o => j5_db_s, + dc_o => j5_dc_s, + dd_o => j5_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process j5_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in J5. + -- + j5_ck_en: process (ha_i, ha_d_i, + e7_q_s, e7_d_out_s, + j5_qc_s, j5_dc_s) + begin + -- falling edge detector on F6.11 + j5_ck_en_s(1) <= -- Flip-Flop Outputs + ( + not ha_i + nand + e7_q_s(3) + ) + and not -- Flip-Flop Inputs + ( + not ha_d_i + nand + e7_d_out_s(3) + ); + + -- falling edge detector on C7.10 + j5_ck_en_s(2) <= -- Flip-Flop Outputs + ( + j5_qc_s(1) + nor + e7_q_s(2) + ) + and not -- Flip-Flop Inputs + ( + j5_dc_s(1) + nor + e7_d_out_s(2) + ); + end process j5_ck_en; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- E7 - Quad D-Type Flip-Flops with Clear + ----------------------------------------------------------------------------- + e7_d_s(1) <= not rb7_i; + e7_d_s(2) <= not ( + rb7_i + and -- D7.12 + rc5_i + and -- D7.12 + ( + not rc4_i + and -- C7.1 + not ( + not rc3_i + nor -- C6.3 + rb6_i + ) + ) + ); + e7_d_s(3) <= not e7_d_s(2) + and -- C7.4 + not a8_p5_q; + e7_d_s(4) <= '0'; + + -- This clock enable is not 100% equivalent to the schematics. + -- There, h5_n_s(4) could also generate a rising edge for E7 + -- but this is ignored here. It is believed that h5_n_s(4) acts + -- only as a clock enable/suppress for the 5 MHz clock. + -- This implementation suppresses as well a combinational feedback + -- loop from J5/1. + e7_ck_en_s <= clk_en_5mhz_i and not h5_n_s(4); + + e7_cl_n_s <= f7_qd_s(2) + or -- B7.3?? + ( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) after 20 ns; + + e7_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => e7_ck_en_s, + por_n_i => por_n_i, + cl_n_i => e7_cl_n_s, + d_i => e7_d_s, + q_o => e7_q_s, + q_n_o => e7_q_n_s, + d_o => e7_d_out_s, + d_n_o => e7_d_out_n_s + ); + + clk_en_e7_3_o <= not e7_q_s(3) and e7_d_out_s(3); + + + ----------------------------------------------------------------------------- + -- Process h5 + -- + -- Purpose: + -- Implements all functionality regarding H5. + -- + h5: process (j5_qa_s, j5_da_s, + j5_qb_s, j5_db_s, + ha_i, ha_d_i, + vbl_n_i, vbl_d_n_i, + a7_p5_q, a7_p5_s) + variable ff_q_v, ff_d_v : std_logic_vector(7 downto 0); + variable f5_p3_q_v, f5_p3_d_v : std_logic; + + ----------------------------------------------------------------------------- + -- 7445 - BCD to Decimal Decoder + ----------------------------------------------------------------------------- + function ttl_45_f(a, b, c, d : in std_logic) return + std_logic_vector is + variable idx_v : std_logic_vector( 3 downto 0); + variable vec_v : std_logic_vector(15 downto 0); + begin + vec_v := (others => '1'); + + idx_v := d & c & b & a; + vec_v(to_integer(unsigned(idx_v))) := '0'; + + return vec_v(7 downto 0); + end ttl_45_f; + + begin + -- combinational result based on flip-flop outputs + f5_p3_q_v := not a7_p5_q nand vbl_n_i; + ff_q_v := ttl_45_f(a => j5_qa_s(1), + b => j5_qb_s(1), + c => ha_i, + d => f5_p3_q_v); + -- combinational result based on flip-flop inputs + f5_p3_d_v := not a7_p5_s nand vbl_d_n_i; + ff_d_v := ttl_45_f(a => j5_da_s(1), + b => j5_db_s(1), + c => ha_d_i, + d => f5_p3_d_v); + + -- combinational output of H5 is based on flip-flop outputs + h5_n_s <= ff_q_v; + + -- clock enable for flip-flops on /5CK + clk_en_5ck_n_o <= not ff_q_v(5) and ff_d_v(5); + -- clock enable for flip-flops on /6CK + clk_en_6ck_n_o <= not ff_q_v(6) and ff_d_v(6); + -- clock enable for flip-flops on /7CK + clk_en_7ck_n_o <= not ff_q_v(7) and ff_d_v(7); + + s6ck_n_o <= ff_q_v(6); + s7ck_n_o <= ff_q_v(7); + end process h5; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + clk_en_b7_p3_o <= f7_ck_en_s(1); + e5_p8_o <= n4_p5_q + nor -- E5.8 + not ( + f7_qa_s(1) + nand -- F6.8 + f7_qb_s(1) + ); + a8_p5_n_o <= not a8_p5_q; + + c_o( 0) <= j5_qa_s(1); + c_o( 1) <= j5_qb_s(1); + c_o( 2) <= j5_qa_s(2); + c_o( 3) <= j5_qb_s(2); + c_o( 4) <= j5_qc_s(2); + c_o( 5) <= j5_qd_s(2); + c_o( 6) <= f7_qa_s(2); + c_o( 7) <= f7_qb_s(2); + c_o( 8) <= f7_qc_s(2); + c_o( 9) <= f7_qa_s(1); + c_o(10) <= f7_qb_s(1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_video_timing.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_video_timing.vhd new file mode 100644 index 00000000..58a3a818 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_video_timing.vhd @@ -0,0 +1,356 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_timing.vhd,v 1.16 2006/02/07 19:27:38 arnim Exp $ +-- +-- The Video Timing Module of Lady Bug Machine. +-- +-- It implements the horizontal and vertical timing signals including composite +-- sync information. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_video_timing is + + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + -- Horizontal Timing Interface -------------------------------------------- + h_o : out std_logic_vector(3 downto 0); + h_t_o : out std_logic_vector(3 downto 0); + hbl_o : out std_logic; + hx_o : out std_logic; + ha_d_o : out std_logic; + ha_t_rise_o : out std_logic; + -- Vertical Timing Interface ---------------------------------------------- + v_o : out std_logic_vector(3 downto 0); + v_t_o : out std_logic_vector(3 downto 0); + vc_d_o : out std_logic; + vbl_n_o : out std_logic; + vbl_d_n_o : out std_logic; + vbl_t_n_o : out std_logic; + blank_flont_o : out std_logic; + -- RBG Video Interface ---------------------------------------------------- + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic + ); + +end ladybug_video_timing; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_video_timing is + + -- horizontal timing circuit + signal h_preset : std_logic_vector(7 downto 0); + signal h_rise : std_logic_vector(7 downto 0); + signal h_do : std_logic_vector(7 downto 0); + signal h_j2_h2 : std_logic_vector(7 downto 0); + signal h_s : std_logic_vector(7 downto 0); + signal hx_q, + hx_s, + hx_n_s : std_logic; + signal hx_rise_s : std_logic; + signal hbl_q : std_logic; +-- signal hbl_n_s : std_logic; + signal hsync_n_q : std_logic; + signal h_carry_s : std_logic; + signal hd_rise_s : std_logic; + + -- vertical timing circuit + signal v_preset : std_logic_vector(7 downto 0); + signal v_rise : std_logic_vector(7 downto 0); + signal v_do : std_logic_vector(7 downto 0); + signal v_s : std_logic_vector(7 downto 0); + signal vx_q, + vx_n_s : std_logic; + signal vbl_q, + vbl_s, + vbl_n_s : std_logic; + signal vbl_t_q, + vbl_t_s, + vbl_t_n_s : std_logic; + signal vsync_n_q : std_logic; + signal v_carry_s : std_logic; + signal vc_rise_s, + vd_rise_s : std_logic; + signal vb_t_rise_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Horizontal Timing counters J2 H2 + ----------------------------------------------------------------------------- + hd_rise_s <= h_rise(3); + ha_t_rise_o <= h_rise(4); + ha_d_o <= h_do(0); + h_preset <= hx_n_s & hx_n_s & "00" & hx_n_s & "000"; + + h_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + reset_n_i => por_n_i, + load_i => h_carry_s, + preset_i => h_preset, + q_o => h_s, + co_o => h_carry_s, + rise_q_o => h_rise, + d_o => h_do + ); + + ----------------------------------------------------------------------------- + -- Process h_timing + -- + -- Purpose: + -- Implement the horizontal timing circuit. + -- + -- The original circuit has no asynchronous reset. To have a stable + -- behavior on silicon, all sequential elements are cleared with the + -- power-on reset. This assumes that the original chips power-up to + -- these values. + -- + -- See also instantiations of ttl_161. + -- + h_timing: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_q <= '0'; + hbl_q <= '0'; + hsync_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Flip-flops on 5 MHz clock -------------------------------------------- + -- HX + hx_q <= hx_s; + + -- Free running flip-flops ---------------------------------------------- + -- HBL + if (hx_q and not h_s(3)) = '1' then + -- pseudo-asynchronous preset + hbl_q <= '1'; + elsif hd_rise_s = '1' then + -- Rising edge on HD + hbl_q <= hx_q; + end if; + + -- HSYNC + if hx_q = '0' then + -- pseudo-asynchronous preset + hsync_n_q <= '1'; + elsif hd_rise_s = '1' then + -- rising edge on HD + hsync_n_q <= h_s(5); + end if; + + end if; + + end process h_timing; + -- + ----------------------------------------------------------------------------- + + hx_n_s <= not hx_q; +--hbl_n_s <= not hbl_q; + + ----------------------------------------------------------------------------- + -- Process hx_comb + -- + -- Purpose: + -- Implements the combinational logic for hx. Including rising edge + -- detection. + -- + hx_comb: process (clk_en_5mhz_i, h_carry_s, hx_q) + begin + -- default assignments + hx_s <= hx_q; + hx_rise_s <= '0'; + + -- HX + if clk_en_5mhz_i = '1' then + if h_carry_s = '1' then + hx_s <= not hx_q; + + -- flag rising edge of hx_q + if hx_q = '0' then + hx_rise_s <= '1'; + end if; + end if; + end if; + + end process hx_comb; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Vertical Timing counters E5 E2 + ----------------------------------------------------------------------------- + vb_t_rise_s <= v_rise(5); + vd_rise_s <= v_rise(3); + vc_rise_s <= v_rise(2); + vc_d_o <= v_do(2); + v_preset <= vx_n_s & vx_n_s & vx_n_s & vx_q & vx_n_s & '0' & vx_n_s & '0'; + + v_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => hx_rise_s, + reset_n_i => por_n_i, + load_i => v_carry_s, + preset_i => v_preset, + q_o => v_s, + co_o => v_carry_s, + rise_q_o => v_rise, + d_o => v_do + ); + + ----------------------------------------------------------------------------- + -- Process v_timing + -- + -- Purpose: + -- Implement the vertical timing circuit. + -- + -- See process h_timing for reset discussion. + -- + v_timing: process (clk_20mhz_i, por_n_i) + variable preset_v : boolean; + begin + if por_n_i = '0' then + vx_q <= '0'; + vbl_q <= '0'; + vsync_n_q <= '1'; + vbl_t_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Free running flip-flops ---------------------------------------------- + -- VX + if hx_rise_s = '1' then + if v_carry_s = '1' then + vx_q <= vx_n_s; + end if; + end if; + + -- VSYNC + if vc_rise_s = '1' then + -- rising edge on VC + vsync_n_q <= not (v_s(7) and v_s(6) and v_s(5) and v_s(4) and v_s(3) and vx_n_s); + end if; + + -- VBL + vbl_q <= vbl_s; + + -- VBL' + vbl_t_q <= vbl_t_s; + + end if; + end process v_timing; + -- + ----------------------------------------------------------------------------- + + vx_n_s <= not vx_q; + vbl_n_s <= not vbl_q; + vbl_t_n_s <= not vbl_t_q; + + + ----------------------------------------------------------------------------- + -- Process vbl_comb + -- + -- Purpose: + -- Combinational logic for vbl_q and vbl_t_q. + -- + vbl_comb: process (v_s, vb_t_rise_s, vd_rise_s, vx_q, vbl_q, vbl_t_q) + variable preset_v : boolean; + begin + preset_v := (v_s(5) and v_s(6) and v_s(7)) = '1'; + -- VBL + vbl_s <= vbl_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_s <= '1'; + elsif vb_t_rise_s = '1' then + -- rising edge on VB' + vbl_s <= vx_q; + end if; + + -- VBL' + vbl_t_s <= vbl_t_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_t_s <= '1'; + elsif vd_rise_s = '1' then + -- rising edge on VD + vbl_t_s <= vx_q; + end if; + + end process vbl_comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + h_o <= h_s(3 downto 0); + h_t_o <= h_s(7 downto 4); + hbl_o <= hbl_q; + hx_o <= hx_q; + v_o <= v_s(3 downto 0); + v_t_o <= v_s(7 downto 4); + vbl_n_o <= vbl_n_s; + vbl_t_n_o <= vbl_t_n_s; + vbl_d_n_o <= not vbl_s; + hsync_n_o <= hsync_n_q; + vsync_n_o <= vsync_n_q; + comp_sync_n_o <= not hsync_n_q xor vsync_n_q; + + -- I have no idea why there is an additional wire called BLANK FLONT. + -- From the schematics, it is the same as /VBL (just buffered). + blank_flont_o <= vbl_n_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_video_unit.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_video_unit.vhd new file mode 100644 index 00000000..96d58e5f --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ladybug_video_unit.vhd @@ -0,0 +1,240 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_unit.vhd,v 1.22 2006/02/07 00:44:35 arnim Exp $ +-- +-- The Video Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_video_unit is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_video_o : out std_logic_vector( 7 downto 0); + vc_o : out std_logic; + vbl_tick_n_o : out std_logic; + vbl_buf_o : out std_logic; + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_video_unit; + +architecture struct of ladybug_video_unit is + + signal h_s, + h_t_s : std_logic_vector(3 downto 0); + signal ha_d_s, + ha_t_rise_s : std_logic; + signal hbl_s : std_logic; + signal hx_s : std_logic; + + signal v_s, + v_t_s : std_logic_vector(3 downto 0); + signal vc_d_s : std_logic; + signal vbl_n_s, + vbl_d_n_s : std_logic; + + signal blank_flont_s : std_logic; + + signal d_from_char_s : std_logic_vector(7 downto 0); + + signal blank_s : std_logic; + signal crg_s : std_logic_vector(5 downto 1); + + signal sig_s : std_logic_vector(4 downto 1); + + signal comp_sync_n : std_logic; + +begin + comp_sync_n_o <= comp_sync_n and vbl_n_s; + vbl_buf_o <= not vbl_n_s; + ----------------------------------------------------------------------------- + -- Horizontal and Vertical Timing Generator + ----------------------------------------------------------------------------- + timing_b : entity work.ladybug_video_timing + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + h_o => h_s, + h_t_o => h_t_s, + hbl_o => hbl_s, + hx_o => hx_s, + ha_d_o => ha_d_s, + ha_t_rise_o => ha_t_rise_s, + v_o => v_s, + v_t_o => v_t_s, + vc_d_o => vc_d_s, + vbl_n_o => vbl_n_s, + vbl_d_n_o => vbl_d_n_s, + vbl_t_n_o => vbl_tick_n_o, + blank_flont_o => blank_flont_s, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n + ); + vc_o <= v_s(2); + + + ----------------------------------------------------------------------------- + -- Character Module + ----------------------------------------------------------------------------- + char_b : entity work.ladybug_char + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_4mhz_i => clk_en_4mhz_i, + cs10_n_i => cs10_n_i, + cs13_n_i => cs13_n_i, + a_i => a_i, + rd_n_i => rd_n_i, + wr_n_i => wr_n_i, + wait_n_o => wait_n_o, + d_from_cpu_i => d_from_cpu_i, + d_from_char_o => d_from_char_s, + h_i => h_s, + h_t_i => h_t_s, + ha_t_rise_i => ha_t_rise_s, + hx_i => hx_s, + v_i => v_s, + v_t_i => v_t_s, + hbl_i => hbl_s, + blank_flont_i => blank_flont_s, + blank_o => blank_s, + vblank_o => vblank_o, + hblank_o => hblank_o, + crg_o => crg_s, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i + ); + + + ----------------------------------------------------------------------------- + -- Sprite Module + ----------------------------------------------------------------------------- + sprite_b : entity work.ladybug_sprite + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_10mhz_i => clk_en_10mhz_i, + clk_en_10mhz_n_i => clk_en_10mhz_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + cs7_n_i => cs7_n_i, + a_i => a_i(9 downto 0), + d_from_cpu_i => d_from_cpu_i, + h_i => h_s, + h_t_i => h_t_s, + hx_i => hx_s, + ha_d_i => ha_d_s, + v_i => v_s, + v_t_i => v_t_s, + vbl_n_i => vbl_n_s, + vbl_d_n_i => vbl_d_n_s, + vc_d_i => vc_d_s, + blank_flont_i => blank_flont_s, + blank_i => blank_s, + sig_o => sig_s, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + + ----------------------------------------------------------------------------- + -- RGB Generator + ----------------------------------------------------------------------------- + rgb_b : entity work.ladybug_rgb + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + crg_i => crg_s, + sig_i => sig_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o + ); + + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_from_video_o <= d_from_char_s + when cs13_n_i = '0' else + (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/mist_io.v b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/osd.v b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/pll.qip b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/pll.v b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/pll.v new file mode 100644 index 00000000..65715540 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 20, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/scandoubler.v b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/ladybug_sound_unit.vhd new file mode 100644 index 00000000..23ad2a6a --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/ladybug_sound_unit.vhd @@ -0,0 +1,143 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sound_unit.vhd,v 1.4 2006/06/16 22:41:37 arnim Exp $ +-- +-- Sound Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_sound_unit is + + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + por_n_i : in std_logic; + cs11_n_i : in std_logic; + cs12_n_i : in std_logic; + wr_n_i : in std_logic; + d_from_cpu_i : in std_logic_vector(7 downto 0); + sound_wait_n_o : out std_logic; + audio_o : out signed(7 downto 0) + ); + +end ladybug_sound_unit; + +architecture struct of ladybug_sound_unit is + + signal ready_b1_s, + ready_c1_s : std_logic; + + signal aout_b1_s, + aout_c1_s : signed(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip B1 + ----------------------------------------------------------------------------- + snd_b1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs11_n_i, + we_n_i => wr_n_i, + ready_o => ready_b1_s, + d_i => d_from_cpu_i, + aout_o => aout_b1_s + ); + + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip C1 + ----------------------------------------------------------------------------- + snd_c1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs12_n_i, + we_n_i => wr_n_i, + ready_o => ready_c1_s, + d_i => d_from_cpu_i, + aout_o => aout_c1_s + ); + + + ----------------------------------------------------------------------------- + -- Process mix + -- + -- Purpose: + -- Mix the digital audio of the two SN76489 instances. + -- Additional care is taken to avoid audio overfow/clipping. + -- + mix: process (aout_b1_s, + aout_c1_s) + variable sum_v : signed(8 downto 0); + begin + sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9); + + if sum_v > 127 then + audio_o <= to_signed(127, 8); + elsif sum_v < -128 then + audio_o <= to_signed(-128, 8); + else + audio_o <= RESIZE(sum_v, 8); + end if; + + end process mix; + -- + ----------------------------------------------------------------------------- + + + sound_wait_n_o <= ready_b1_s and ready_c1_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING new file mode 100644 index 00000000..60549be5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) 19yy + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README new file mode 100644 index 00000000..33630144 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/README @@ -0,0 +1,143 @@ + +An SN76489AN Compatible Implementation in VHDL +============================================== +Version: $Date: 2006/06/18 19:28:40 $ + +Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +See the file COPYING. + + +Integration +----------- + +The sn76489 design exhibits all interface signals as the original chip. It +only differs in the audio data output which is provided as an 8 bit signed +vector instead of an analog output pin. + + generic ( + clock_div_16_g : integer := 1 + -- Set to '1' when operating the design in SN76489 mode. The primary clock + -- input is divided by 16 in this variant. The data sheet mentions the + -- SN76494 which contains a divide-by-2 clock input stage. Set the generic + -- to '0' to enable this mode. + ); + port ( + clock_i : in std_logic; + -- Primary clock input + -- Drive with the target frequency or any integer multiple of it. + + clock_en_i : in std_logic; + -- Clock enable + -- A '1' on this input qualifies a valid rising edge on clock_i. A '0' + -- disables the next rising clock edge, effectivley halting the design + -- until the next enabled rising clock edge. + -- Can be used to run the core at lower frequencies than applied on + -- clock_i. + + res_n_i : in std_logic; + -- Asynchronous low active reset input. + -- Sets all sequential elements to a known state. + + ce_n_i : in std_logic; + -- Chip enable, low active. + + we_n_i : in std_logic; + -- Write enable, low active. + + ready_o : out std_logic; + -- Ready indication to microprocessor. + + d_i : in std_logic_vector(0 to 7); + -- Data input + -- MSB 0 ... 7 LSB + + aout_o : out signed(0 to 7) + -- Audio output, signed vector + -- MSB/SIGN 0 ... 7 LSB + ); + + +Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the +MSB and bit 7 to be the LSB. This has been implemented according to TI's data +sheet, thus all register/data format figures apply 1:1 for this design. +Many systems will flip the system data bus bit wise before it is connected to +this PSG. This is simply achieved with the following VHDL construct: + + signal data_s : std_logic_vector(7 downto 0); + + ... + d_i => data_s, + ... + +d_i and data_s will be assigned from left to right, resulting in the expected +bit assignment: + + d_i data_s + 0 7 + 1 6 + ... + 6 1 + 7 0 + + +As this design is fully synchronous, care has to be taken when the design +replaces an SN76489 in asynchronous mode. No problems are expected when +interfacing the code to other synchronous components. + + +Design Hierarchy +---------------- + + sn76489_top + | + +-- sn76489_latch_ctrl + | + +-- sn76489_clock_div + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + \-- sn76489_noise + | + \-- sn76489_attentuator + +Resulting compilation sequence: + + sn76489_comp_pack-p.vhd + sn76489_top.vhd + sn76489_latch_ctrl.vhd + sn76489_latch_ctrl-c.vhd + sn76489_clock_div.vhd + sn76489_clock_div-c.vhd + sn76489_attenuator.vhd + sn76489_attenuator-c.vhd + sn76489_tone.vhd + sn76489_tone-c.vhd + sn76489_noise.vhd + sn76489_noise-c.vhd + sn76489_top-c.vhd + +Skip the files containing VHDL configurations when analyzing the code for +synthesis. + + +References +---------- + +* TI Data sheet SN76489.pdf + ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf + +* John Kortink's article on the SN76489: + http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ + +* Maxim's "SN76489 notes" in + http://www.smspower.org/maxim/docs/SN76489.txt diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd new file mode 100644 index 00000000..444064e5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $ +-- +-- Attenuator Module +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_attenuator is + + port ( + attenuation_i : in std_logic_vector(0 to 3); + factor_i : in signed(0 to 1); + product_o : out signed(0 to 7) + ); + +end sn76489_attenuator; + + +architecture rtl of sn76489_attenuator is + +begin + + ----------------------------------------------------------------------------- + -- Process attenuate + -- + -- Purpose: + -- Determine the attenuation and generate the resulting product. + -- + -- The maximum attenuation value is 31 which corresponds to volume off. + -- As described in the data sheet, the maximum "playing" attenuation is + -- 28 = 16 + 8 + 4 + -- + -- The table for the volume constants is derived from the following + -- formula (each step is 2dB voltage): + -- v(0) = 31 + -- v(n+1) = v(n) * 0.79432823 + -- + attenuate: process (attenuation_i, + factor_i) + + type volume_t is array (natural range 0 to 15) of natural; + constant volume_c : volume_t := + (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0); + + variable attenuation_v : unsigned(attenuation_i'range); + variable volume_v : signed(product_o'range); + + begin + + attenuation_v := unsigned(attenuation_i); + + -- volume look-up table + volume_v := to_signed(volume_c(to_integer(attenuation_v)), + product_o'length); + + -- this replaces a multiplier and consumes a bit fewer + -- resources + case to_integer(factor_i) is + when +1 => + product_o <= volume_v; + when -1 => + product_o <= -volume_v; + when others => + product_o <= (others => '0'); + end case; + + end process attenuate; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd new file mode 100644 index 00000000..eab86beb --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $ +-- +-- Clock Divider Circuit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_clock_div is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + clk_en_o : out boolean + ); + +end sn76489_clock_div; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_clock_div is + + signal cnt_s, + cnt_q : unsigned(3 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential counter element. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + cnt_q <= (others => '0'); + elsif clock_i'event and clock_i = '1' then + cnt_q <= cnt_s; + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational counter logic. + -- + comb: process (clock_en_i, + cnt_q) + begin + -- default assignments + cnt_s <= cnt_q; + clk_en_o <= false; + + if clock_en_i = '1' then + + if cnt_q = 0 then + clk_en_o <= true; + + if clock_div_16_g = 1 then + cnt_s <= to_unsigned(15, cnt_q'length); + elsif clock_div_16_g = 0 then + cnt_s <= to_unsigned( 1, cnt_q'length); + else + -- pragma translate_off + assert false + report "Generic clock_div_16_g must be either 0 or 1." + severity failure; + -- pragma translate_on + end if; + + else + cnt_s <= cnt_q - 1; + + end if; + + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd new file mode 100644 index 00000000..789720c2 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd @@ -0,0 +1,138 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Latch Control Unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_latch_ctrl is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector(0 to 7); + ready_o : out std_logic; + tone1_we_o : out boolean; + tone2_we_o : out boolean; + tone3_we_o : out boolean; + noise_we_o : out boolean; + r2_o : out std_logic + ); + +end sn76489_latch_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_latch_ctrl is + + signal reg_q : std_logic_vector(0 to 2); + signal we_q : boolean; + signal ready_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + reg_q <= (others => '0'); + we_q <= false; + ready_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + -- READY Flag Output ---------------------------------------------------- + if ready_q = '0' and we_q then + if clk_en_i then + -- assert READY when write access happened + ready_q <= '1'; + end if; + elsif ce_n_i = '1' then + -- deassert READY when access has finished + ready_q <= '0'; + end if; + + -- Register Selection --------------------------------------------------- + if ce_n_i = '0' and we_n_i = '0' then + if clk_en_i then + if d_i(0) = '1' then + reg_q <= d_i(1 to 3); + end if; + we_q <= true; + end if; + else + we_q <= false; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + tone1_we_o <= reg_q(0 to 1) = "00" and we_q; + tone2_we_o <= reg_q(0 to 1) = "01" and we_q; + tone3_we_o <= reg_q(0 to 1) = "10" and we_q; + noise_we_o <= reg_q(0 to 1) = "11" and we_q; + + r2_o <= reg_q(2); + + ready_o <= ready_q + when ce_n_i = '0' else + '1'; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd new file mode 100644 index 00000000..688bdd56 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_noise.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Noise Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_noise is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + tone3_ff_i : in std_logic; + noise_o : out signed(0 to 7) + ); + +end sn76489_noise; + +architecture rtl of sn76489_noise is + + signal nf_q : std_logic_vector(0 to 1); + signal fb_q : std_logic; + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 6); + signal freq_ff_q : std_logic; + + signal shift_source_s, + shift_source_q : std_logic; + signal shift_rise_edge_s : boolean; + + signal lfsr_q : std_logic_vector(0 to 15); + + signal freq_s : signed(0 to 1); + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + nf_q <= (others => '0'); + fb_q <= '0'; + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to control register + -- both access types can write to the control register! + nf_q <= d_i(6 to 7); + fb_q <= d_i(5); + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- reload frequency counter according to NF setting + case nf_q is + when "00" => + freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length); + when "01" => + freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length); + when "10" => + freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length); + when others => + null; + end case; + + freq_ff_q <= not freq_ff_q; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Multiplex the source of the LFSR's shift enable + ----------------------------------------------------------------------------- + shift_source_s <= tone3_ff_i + when nf_q = "11" else + freq_ff_q; + + ----------------------------------------------------------------------------- + -- Process rise_edge + -- + -- Purpose: + -- Detect the rising edge of the selected LFSR shift source. + -- + rise_edge: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + shift_source_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + shift_source_q <= shift_source_s; + end if; + end if; + end process rise_edge; + -- + ----------------------------------------------------------------------------- + + -- detect rising edge on shift source + shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1'; + + + ----------------------------------------------------------------------------- + -- Process lfsr + -- + -- Purpose: + -- Implements the LFSR that generates noise. + -- Note: This implementation shifts the register right, i.e. from index + -- 15 towards 0 => bit 15 is the input, bit 0 is the output + -- + -- Tapped bits according to MAME's sn76496.c, implemented in function + -- lfsr_tapped_f. + -- + lfsr: process (clock_i, res_n_i) + + function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is + constant tapped_bits_c : std_logic_vector(0 to 15) + -- tapped bits are 0, 2, 15 + := "1010000000000001"; + variable parity_v : std_logic; + begin + parity_v := '0'; + + for idx in lfsr'low to lfsr'high loop + parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx)); + end loop; + + return parity_v; + end; + + begin + if res_n_i = '0' then + -- reset LFSR to "0000000000000001" + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if we_i and r2_i = '0' then + -- write to noise register + -- -> reset LFSR + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif shift_rise_edge_s then + + -- shift LFSR left towards MSB + for idx in lfsr_q'right-1 downto lfsr_q'left loop + lfsr_q(idx) <= lfsr_q(idx+1); + end loop; + + -- determine input bit + if fb_q = '0' then + -- "Periodic" Noise + -- -> input to LFSR is output + lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left); + else + -- "White" Noise + -- -> input to LFSR is parity of tapped bits + lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q); + end if; + + end if; + + end if; + end if; + end process lfsr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map output of LFSR to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when lfsr_q(0) = '1' else + to_signed( 0, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => noise_o + ); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd new file mode 100644 index 00000000..3658efcc --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_tone.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $ +-- +-- Tone Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_tone is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + ff_o : out std_logic; + tone_o : out signed(0 to 7) + ); + +end sn76489_tone; + +architecture rtl of sn76489_tone is + + signal f_q : std_logic_vector(0 to 9); + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 9); + signal freq_ff_q : std_logic; + + signal freq_s : signed(0 to 1); + + function all_zero(a : in std_logic_vector) return boolean is + variable result_v : boolean; + begin + result_v := true; + + for idx in a'low to a'high loop + if a(idx) /= '0' then + result_v := false; + end if; + end loop; + + return result_v; + end; + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + f_q <= (others => '0'); + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to frequency register + if d_i(0) = '0' then + f_q(0 to 5) <= d_i(2 to 7); + else + f_q(6 to 9) <= d_i(4 to 7); + end if; + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- update counter from frequency register + freq_cnt_q <= unsigned(f_q); + + -- and toggle the frequency flip-flop if enabled + if not all_zero(f_q) then + freq_ff_q <= not freq_ff_q; + else + -- if frequency setting is 0, then keep flip-flop at +1 + freq_ff_q <= '1'; + end if; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map frequency flip-flop to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when freq_ff_q = '1' else + to_signed(-1, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => tone_o + ); + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + ff_o <= freq_ff_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd new file mode 100644 index 00000000..c26d0e1a --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/sound/sn76489/sn76489_top.vhd @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $ +-- +-- Chip Toplevel +-- +-- References: +-- +-- * TI Data sheet SN76489.pdf +-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf +-- +-- * John Kortink's article on the SN76489: +-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ +-- +-- * Maxim's "SN76489 notes" in +-- http://www.smspower.org/maxim/docs/SN76489.txt +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ieee; +use ieee.numeric_std.all; + +entity sn76489_top is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + ready_o : out std_logic; + d_i : in std_logic_vector(0 to 7); + aout_o : out signed(0 to 7) + ); + +end sn76489_top; + +architecture struct of sn76489_top is + + signal clk_en_s : boolean; + + signal tone1_we_s, + tone2_we_s, + tone3_we_s, + noise_we_s : boolean; + signal r2_s : std_logic; + + signal tone1_s, + tone2_s, + tone3_s, + noise_s : signed(0 to 7); + + signal tone3_ff_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock Divider + ----------------------------------------------------------------------------- + clock_div_b : entity work.sn76489_clock_div + generic map ( + clock_div_16_g => clock_div_16_g + ) + port map ( + clock_i => clock_i, + clock_en_i => clock_en_i, + res_n_i => res_n_i, + clk_en_o => clk_en_s + ); + + + ----------------------------------------------------------------------------- + -- Latch Control = CPU Interface + ----------------------------------------------------------------------------- + latch_ctrl_b : entity work.sn76489_latch_ctrl + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + ce_n_i => ce_n_i, + we_n_i => we_n_i, + d_i => d_i, + ready_o => ready_o, + tone1_we_o => tone1_we_s, + tone2_we_o => tone2_we_s, + tone3_we_o => tone3_we_s, + noise_we_o => noise_we_s, + r2_o => r2_s + ); + + + ----------------------------------------------------------------------------- + -- Tone Channel 1 + ----------------------------------------------------------------------------- + tone1_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone1_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone1_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 2 + ----------------------------------------------------------------------------- + tone2_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone2_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone2_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 3 + ----------------------------------------------------------------------------- + tone3_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone3_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => tone3_ff_s, + tone_o => tone3_s + ); + + ----------------------------------------------------------------------------- + -- Noise Channel + ----------------------------------------------------------------------------- + noise_b : entity work.sn76489_noise + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => noise_we_s, + d_i => d_i, + r2_i => r2_s, + tone3_ff_i => tone3_ff_s, + noise_o => noise_s + ); + + + aout_o <= tone1_s + tone2_s + tone3_s + noise_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/spram.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/spram.vhd new file mode 100644 index 00000000..fa4a1fd7 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/spram.vhd @@ -0,0 +1,84 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + widthad_a : natural; + width_a : natural := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ttl_175.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ttl_175.vhd new file mode 100644 index 00000000..b6459332 --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ttl_175.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74175 - Quad D-Type Flip-Flops with Clear +-- +-- $Id: ttl_175.vhd,v 1.5 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_175 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + por_n_i : in std_logic; + cl_n_i : in std_logic; + d_i : in std_logic_vector(4 downto 1); + q_o : out std_logic_vector(4 downto 1); + q_n_o : out std_logic_vector(4 downto 1); + d_o : out std_logic_vector(4 downto 1); + d_n_o : out std_logic_vector(4 downto 1) + ); + +end ttl_175; + + +architecture rtl of ttl_175 is + + signal flops_q, + flops_s : std_logic_vector(4 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process flops + -- + -- Purpose: + -- Implement the sequential elements. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_n_i. + -- + flops: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + flops_q <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + flops_q <= flops_s; + end if; + end process flops; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational logic. + -- + comb: process (flops_q, + cl_n_i, + d_i, + ck_en_i) + begin + -- default assignments + flops_s <= flops_q; + + if cl_n_i = '1' then + if ck_en_i = '1' then + flops_s <= d_i; + end if; + + else + -- pseudo-asynchronous clear + flops_s <= (others => '0'); + end if; + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + q_o <= flops_q; + q_n_o <= not flops_q; + d_o <= flops_s; + d_n_o <= not flops_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ttl_393.vhd b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ttl_393.vhd new file mode 100644 index 00000000..3ef25d4b --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/ttl_393.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74LS393 - Dual 4-Bit Binary Counter +-- +-- $Id: ttl_393.vhd,v 1.3 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_393 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic_vector(2 downto 1); + por_n_i : in std_logic; + cl_i : in std_logic_vector(2 downto 1); + qa_o : out std_logic_vector(2 downto 1); + qb_o : out std_logic_vector(2 downto 1); + qc_o : out std_logic_vector(2 downto 1); + qd_o : out std_logic_vector(2 downto 1); + da_o : out std_logic_vector(2 downto 1); + db_o : out std_logic_vector(2 downto 1); + dc_o : out std_logic_vector(2 downto 1); + dd_o : out std_logic_vector(2 downto 1) + ); + +end ttl_393; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ttl_393 is + + type cnt_q_t is array (natural range 2 downto 1) of unsigned(3 downto 0); + type cnt_d_t is array (natural range 2 downto 1) of unsigned(4 downto 0); + signal cnt_q : cnt_q_t; + signal cnt_s : cnt_d_t; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the flip-flops. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_i. + -- + seq: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + cnt_q(1) <= (others => '0'); + cnt_q(2) <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + cnt_q(1) <= cnt_s(1)(3 downto 0); + cnt_q(2) <= cnt_s(2)(3 downto 0); + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process adder + -- + -- Purpose: + -- Implements the adder. + -- + adder: process (ck_en_i, + cl_i, + cnt_q) + begin + for idx in 2 downto 1 loop + cnt_s(idx) <= '0' & cnt_q(idx); + + if cl_i(idx) = '0' then + if ck_en_i(idx) = '1' then + -- increment upon enable + cnt_s(idx) <= ('0' & cnt_q(idx)) + 1; + end if; + + else + -- pseudo-asynchronous clear + cnt_s(idx) <= (others => '0'); + end if; + end loop; + end process adder; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + qa_o(1) <= cnt_q(1)(0); + qb_o(1) <= cnt_q(1)(1); + qc_o(1) <= cnt_q(1)(2); + qd_o(1) <= cnt_q(1)(3); + qa_o(2) <= cnt_q(2)(0); + qb_o(2) <= cnt_q(2)(1); + qc_o(2) <= cnt_q(2)(2); + qd_o(2) <= cnt_q(2)(3); + da_o(1) <= cnt_s(1)(0); + db_o(1) <= cnt_s(1)(1); + dc_o(1) <= cnt_s(1)(2); + dd_o(1) <= cnt_s(1)(3); + da_o(2) <= cnt_s(2)(0); + db_o(2) <= cnt_s(2)(1); + dc_o(2) <= cnt_s(2)(2); + dd_o(2) <= cnt_s(2)(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/video_mixer.sv b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Ladybug Hardware/Dorodon_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.qpf b/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.qpf new file mode 100644 index 00000000..7af75589 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "LadyBug" diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf b/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf new file mode 100644 index 00000000..56238f32 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.qsf @@ -0,0 +1,205 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:02:22 November 16, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Arcade-LadyBug_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd +set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_timing.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rgb.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_res.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rams.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_machine.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_gpio.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_dip_pack.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_cpu_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_counter.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_clk.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/LadyBug.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TOP_LEVEL_ENTITY LadyBug + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(LadyBug) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(LadyBug) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.srf b/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/LadyBug.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/README.txt b/Arcade/Ladybug Hardware/LadyBug_MiST/README.txt new file mode 100644 index 00000000..59c4a482 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Lady Bug port to MiST by Gehstock +-- 14 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Lady Bug hardware +-- Unknown Author on Papilio Plus board. +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + + +ToDo : Sound diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/Release/LadyBug.rbf b/Arcade/Ladybug Hardware/LadyBug_MiST/Release/LadyBug.rbf new file mode 100644 index 00000000..c3a0193c Binary files /dev/null and b/Arcade/Ladybug Hardware/LadyBug_MiST/Release/LadyBug.rbf differ diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/clean.bat b/Arcade/Ladybug Hardware/LadyBug_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv new file mode 100644 index 00000000..88349241 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/LadyBug.sv @@ -0,0 +1,194 @@ +//============================================================================ +// Arcade: Lady Bug +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module LadyBug +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Ladybug;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire signed[7:0] audio_s; +reg [6:0] audio; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_vid), + .ce_pix_actual(ce_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? {r} : "0"), + .G(blankn ? {g&g} : "00"), + .B(blankn ? {b} : "0"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire blankn = ~(hblank | vblank); + + + +//condition ? if true : if false +ladybugt ladybugt +( + .CLK_IN(clk_sys), + .I_RESET(status[0] | status[6] | buttons[1]), + .O_PIXCE(ce_vid), + + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_VSYNC(vs), + .O_HSYNC(hs), + .O_VBLANK(vblank), + .O_HBLANK(hblank), + + .O_AUDIO(audio_s), + + .but_coin_s(~{1'b0,m_coin}), + .but_fire_s(~{1'b0,m_fire}), + .but_bomb_s(~{1'b0,m_bomb}), + .but_tilt_s(~{1'b0,1'b0}), + .but_select_s(~{m_start2,m_start1}), + .but_up_s(~{1'b0,m_up}), + .but_down_s(~{1'b0,m_down}), + .but_left_s(~{1'b0,m_left}), + .but_right_s(~{1'b0,m_right}) +); + +assign audio = audio_s; + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_1.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_1.vhd new file mode 100644 index 00000000..e1045eae --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_1.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_1 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"59",X"33",X"B8",X"00",X"D4",X"A3",X"8D",X"00",X"2C",X"63",X"DD",X"00",X"22",X"38",X"1D", + X"00",X"93",X"3A",X"DD",X"00",X"E2",X"38",X"DD",X"00",X"82",X"3A",X"D8",X"00",X"22",X"68",X"1D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_2.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_2.vhd new file mode 100644 index 00000000..3027d172 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_2.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_2 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F5",X"90",X"41",X"54",X"94",X"11",X"80",X"65",X"05",X"D4",X"01",X"00",X"B1",X"A0",X"00",X"F5", + X"04",X"B1",X"00",X"15",X"11",X"25",X"90",X"D0",X"A0",X"90",X"15",X"84",X"B5",X"04",X"04",X"04"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_3.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_3.vhd new file mode 100644 index 00000000..a731ff5c --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_10_3.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_3 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"3A",X"3A",X"3A",X"3A",X"28",X"28",X"38",X"38", + X"08",X"08",X"38",X"38",X"20",X"20",X"38",X"38",X"20",X"20",X"38",X"38",X"3E",X"3E",X"3E",X"3E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_decrypt.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_decrypt.vhd new file mode 100644 index 00000000..00f98d21 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/prom_decrypt.vhd @@ -0,0 +1,63 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity prom_decrypt is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(7 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of prom_decrypt is + + + type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07", -- 0x0000 + x"08",x"09",x"0A",x"0B",x"0C",x"0D",x"0E",x"0F", -- 0x0008 + x"10",x"11",x"12",x"13",x"14",x"15",x"16",x"17", -- 0x0010 + x"18",x"19",x"1A",x"1B",x"1C",x"1D",x"1E",x"1F", -- 0x0018 + x"20",x"21",x"22",x"23",x"24",x"25",x"26",x"27", -- 0x0020 + x"28",x"29",x"2A",x"2B",x"2C",x"2D",x"2E",x"2F", -- 0x0028 + x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37", -- 0x0030 + x"38",x"39",x"3A",x"3B",x"3C",x"3D",x"3E",x"3F", -- 0x0038 + x"40",x"41",x"42",x"43",x"44",x"45",x"46",x"47", -- 0x0040 + x"48",x"49",x"4A",x"4B",x"4C",x"4D",x"4E",x"4F", -- 0x0048 + x"50",x"51",x"52",x"53",x"54",x"55",x"56",x"57", -- 0x0050 + x"58",x"59",x"5A",x"5B",x"5C",x"5D",x"5E",x"5F", -- 0x0058 + x"60",x"61",x"62",x"63",x"64",x"65",x"66",x"67", -- 0x0060 + x"68",x"69",x"6A",x"6B",x"6C",x"6D",x"6E",x"6F", -- 0x0068 + x"70",x"71",x"72",x"73",x"74",x"75",x"76",x"77", -- 0x0070 + x"78",x"79",x"7A",x"7B",x"7C",x"7D",x"7E",x"7F", -- 0x0078 + x"80",x"81",x"82",x"83",x"84",x"85",x"86",x"87", -- 0x0080 + x"88",x"89",x"8A",x"8B",x"8C",x"8D",x"8E",x"8F", -- 0x0088 + x"90",x"91",x"92",x"93",x"94",x"95",x"96",x"97", -- 0x0090 + x"98",x"99",x"9A",x"9B",x"9C",x"9D",x"9E",x"9F", -- 0x0098 + x"A0",x"A1",x"A2",x"A3",x"A4",x"A5",x"A6",x"A7", -- 0x00A0 + x"A8",x"A9",x"AA",x"AB",x"AC",x"AD",x"AE",x"AF", -- 0x00A8 + x"B0",x"B1",x"B2",x"B3",x"B4",x"B5",x"B6",x"B7", -- 0x00B0 + x"B8",x"B9",x"BA",x"BB",x"BC",x"BD",x"BE",x"BF", -- 0x00B8 + x"C0",x"C1",x"C2",x"C3",x"C4",x"C5",x"C6",x"C7", -- 0x00C0 + x"C8",x"C9",x"CA",x"CB",x"CC",x"CD",x"CE",x"CF", -- 0x00C8 + x"D0",x"D1",x"D2",x"D3",x"D4",x"D5",x"D6",x"D7", -- 0x00D0 + x"D8",x"D9",x"DA",x"DB",x"DC",x"DD",x"DE",x"DF", -- 0x00D8 + x"E0",x"E1",x"E2",x"E3",x"E4",x"E5",x"E6",x"E7", -- 0x00E0 + x"E8",x"E9",x"EA",x"EB",x"EC",x"ED",x"EE",x"EF", -- 0x00E8 + x"F0",x"F1",x"F2",x"F3",x"F4",x"F5",x"F6",x"F7", -- 0x00F0 + x"F8",x"F9",x"FA",x"FB",x"FC",x"FD",x"FE",x"FF" -- 0x00F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_char_l.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_char_l.vhd new file mode 100644 index 00000000..8d1f1092 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_char_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"3C",X"66",X"42",X"42",X"42",X"66",X"3C",X"00",X"00",X"00",X"22",X"7E",X"02",X"00",X"00", + X"00",X"26",X"6E",X"4A",X"4A",X"4A",X"7A",X"32",X"00",X"44",X"46",X"52",X"52",X"52",X"7E",X"6C", + X"00",X"0C",X"1C",X"34",X"64",X"44",X"7E",X"04",X"00",X"74",X"56",X"52",X"52",X"52",X"5E",X"0C", + X"00",X"3C",X"76",X"52",X"52",X"52",X"5E",X"0C",X"00",X"40",X"42",X"46",X"4C",X"58",X"70",X"60", + X"00",X"2C",X"7E",X"52",X"52",X"52",X"7E",X"2C",X"00",X"30",X"7A",X"4A",X"4A",X"4A",X"6E",X"3C", + X"00",X"1E",X"34",X"64",X"44",X"64",X"34",X"1E",X"00",X"7E",X"52",X"52",X"52",X"52",X"7E",X"2C", + X"00",X"3C",X"66",X"42",X"42",X"42",X"66",X"24",X"00",X"7E",X"42",X"42",X"42",X"42",X"66",X"3C", + X"00",X"7E",X"52",X"52",X"52",X"52",X"42",X"42",X"00",X"7E",X"50",X"50",X"50",X"50",X"40",X"40", + X"00",X"3C",X"66",X"42",X"42",X"4A",X"6A",X"2E",X"00",X"7E",X"10",X"10",X"10",X"10",X"10",X"7E", + X"00",X"00",X"00",X"42",X"7E",X"42",X"00",X"00",X"00",X"0C",X"06",X"02",X"02",X"02",X"06",X"7C", + X"00",X"7E",X"06",X"0C",X"18",X"34",X"66",X"42",X"00",X"7E",X"02",X"02",X"02",X"02",X"02",X"02", + X"00",X"7E",X"30",X"18",X"0C",X"18",X"30",X"7E",X"00",X"7E",X"60",X"30",X"18",X"0C",X"06",X"7E", + X"00",X"3C",X"66",X"42",X"42",X"42",X"66",X"3C",X"00",X"7E",X"48",X"48",X"48",X"48",X"78",X"30", + X"00",X"3C",X"66",X"42",X"4A",X"4C",X"66",X"3A",X"00",X"7E",X"48",X"48",X"48",X"4E",X"7A",X"32", + X"00",X"24",X"76",X"52",X"5A",X"4A",X"6E",X"24",X"00",X"40",X"40",X"40",X"7E",X"40",X"40",X"40", + X"00",X"7C",X"06",X"02",X"02",X"02",X"06",X"7C",X"00",X"70",X"1C",X"06",X"02",X"06",X"1C",X"70", + X"00",X"7C",X"06",X"0C",X"18",X"0C",X"06",X"7C",X"00",X"42",X"66",X"2C",X"18",X"34",X"66",X"42", + X"00",X"60",X"30",X"18",X"0E",X"18",X"30",X"60",X"00",X"42",X"46",X"4E",X"5A",X"72",X"62",X"42", + X"00",X"6C",X"7E",X"52",X"42",X"16",X"1C",X"10",X"00",X"24",X"7E",X"24",X"24",X"24",X"7E",X"24", + X"00",X"2E",X"6A",X"4E",X"42",X"42",X"66",X"3C",X"00",X"20",X"60",X"40",X"5A",X"50",X"70",X"20", + X"00",X"00",X"00",X"00",X"7A",X"60",X"00",X"00",X"00",X"30",X"78",X"7C",X"3E",X"7C",X"78",X"30", + X"00",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"00",X"00",X"18",X"3C",X"66",X"42",X"00",X"00", + X"00",X"00",X"42",X"66",X"3C",X"18",X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00", + X"00",X"00",X"60",X"70",X"00",X"00",X"00",X"00",X"00",X"7C",X"82",X"BA",X"AA",X"AA",X"82",X"7C", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_char_u.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_char_u.vhd new file mode 100644 index 00000000..e21d3747 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_char_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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-0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C3",X"18",X"50",X"69",X"30",X"81",X"00",X"10",X"14",X"02",X"80",X"10",X"98",X"01",X"80",X"4C", + X"C0",X"02",X"00",X"C4",X"40",X"22",X"00",X"88",X"00",X"12",X"92",X"82",X"60",X"12",X"03",X"00", + X"00",X"20",X"82",X"00",X"00",X"00",X"A0",X"40",X"00",X"30",X"02",X"68",X"40",X"00",X"00",X"00", + X"10",X"00",X"00",X"00",X"02",X"10",X"00",X"20",X"C3",X"9E",X"01",X"68",X"42",X"80",X"48",X"00", + X"14",X"80",X"08",X"71",X"25",X"29",X"05",X"08",X"0D",X"05",X"00",X"11",X"70",X"80",X"45",X"03", + X"4C",X"8E",X"04",X"4D",X"41",X"21",X"00",X"05",X"08",X"0D",X"89",X"01",X"85",X"03",X"25",X"00", + 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X"27",X"81",X"DD",X"E1",X"C9",X"DD",X"7E",X"01",X"FE",X"07",X"D2",X"AF",X"1F",X"3E",X"07",X"D6", + X"07",X"5F",X"CB",X"3B",X"CB",X"3B",X"CB",X"3B",X"CB",X"3B",X"E6",X"0F",X"08",X"7B",X"FE",X"0B", + X"DA",X"C5",X"1F",X"1E",X"0B",X"08",X"C9",X"DD",X"E5",X"CD",X"7D",X"44",X"CD",X"5A",X"2D",X"21", + X"01",X"90",X"CB",X"7E",X"CA",X"D2",X"1F",X"21",X"59",X"60",X"34",X"7E",X"21",X"5A",X"60",X"E6", + X"07",X"20",X"01",X"34",X"CD",X"3A",X"03",X"21",X"4E",X"60",X"AF",X"06",X"0B",X"77",X"23",X"10", + X"FC",X"DD",X"21",X"1C",X"60",X"DD",X"7E",X"00",X"E6",X"03",X"C2",X"0C",X"20",X"04",X"3E",X"0A"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_cpu2.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_cpu2.vhd new file mode 100644 index 00000000..a7f5b86f --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_cpu2.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu2 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"B8",X"CA",X"03",X"21",X"11",X"05",X"00",X"DD",X"19",X"C3",X"F5",X"1F",X"21",X"5F",X"60",X"CB", + X"4E",X"28",X"20",X"21",X"02",X"90",X"CB",X"6E",X"28",X"19",X"4F",X"3A",X"65",X"60",X"FE",X"00", + X"79",X"28",X"10",X"DD",X"4E",X"02",X"3E",X"FE",X"91",X"4F",X"DD",X"56",X"01",X"3E",X"AE",X"92", + X"C3",X"39",X"20",X"DD",X"7E",X"01",X"DD",X"4E",X"02",X"DD",X"56",X"00",X"CB",X"3A",X"CB",X"3A", + X"CB",X"3A",X"CB",X"3A",X"CD",X"A8",X"1F",X"D5",X"16",X"00",X"FD",X"21",X"4E",X"60",X"FD",X"19", + X"F5",X"FD",X"7E",X"00",X"FD",X"34",X"00",X"C5",X"43",X"04",X"FD",X"21",X"80",X"70",X"11",X"40", + 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-0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu3 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"12",X"D1",X"C1",X"F1",X"C9",X"06",X"06",X"DD",X"21",X"A8",X"61",X"DD",X"7E",X"01",X"FE",X"00", + X"28",X"1C",X"DD",X"6E",X"00",X"DD",X"66",X"01",X"DD",X"E5",X"C5",X"CD",X"2B",X"3D",X"36",X"E5", + X"21",X"A9",X"60",X"34",X"C1",X"DD",X"E1",X"AF",X"DD",X"77",X"00",X"DD",X"77",X"01",X"DD",X"23", + X"DD",X"23",X"10",X"D7",X"C9",X"AF",X"06",X"03",X"DD",X"4E",X"00",X"CD",X"3B",X"33",X"FD",X"75", + X"00",X"FD",X"23",X"FD",X"74",X"00",X"FD",X"23",X"3C",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"DD", + X"23",X"10",X"E5",X"C9",X"06",X"0C",X"DD",X"21",X"9C",X"61",X"DD",X"7E",X"01",X"FE",X"00",X"28", + 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Hardware/LadyBug_MiST/rtl/ROM/rom_sprite_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"01",X"00",X"01",X"00",X"35",X"00",X"AA",X"02",X"AA",X"0A",X"AA",X"0B",X"E9", + X"00",X"00",X"40",X"00",X"40",X"00",X"5C",X"00",X"AA",X"00",X"AA",X"80",X"AA",X"A0",X"6B",X"E0", + X"0B",X"E5",X"0A",X"A5",X"0A",X"E9",X"02",X"AA",X"02",X"A6",X"00",X"AA",X"00",X"0A",X"00",X"00", + X"5B",X"E0",X"5A",X"A0",X"6B",X"A0",X"AA",X"80",X"9A",X"80",X"AA",X"00",X"A0",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"00",X"01",X"00",X"35",X"00",X"AA",X"02",X"AA",X"0A",X"AA",X"0B",X"EB", + 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X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_sprite_u.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_sprite_u.vhd new file mode 100644 index 00000000..a8d873d5 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ROM/rom_sprite_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"35",X"00",X"55",X"01",X"DD", + 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X"5A",X"5F",X"69",X"F5",X"67",X"D4",X"A7",X"55",X"A7",X"55",X"A7",X"D4",X"A9",X"F5",X"AA",X"5F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"55",X"40",X"55",X"55", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00", + X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55", + X"50",X"00",X"54",X"00",X"55",X"40",X"55",X"56",X"55",X"56",X"55",X"56",X"55",X"5A",X"55",X"6A", + X"A5",X"54",X"A5",X"54",X"A5",X"54",X"A5",X"55",X"A5",X"55",X"A9",X"55",X"A9",X"55",X"A9",X"55", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"40",X"00", + X"A9",X"55",X"AA",X"55",X"2A",X"55",X"2A",X"55",X"2A",X"95",X"0A",X"95",X"0A",X"A5",X"0A",X"A5", + X"50",X"00",X"50",X"00",X"54",X"00",X"55",X"00",X"55",X"40",X"55",X"50",X"55",X"54",X"55",X"55", + X"0A",X"95",X"0A",X"55",X"0A",X"55",X"2A",X"55",X"2A",X"55",X"29",X"55",X"A9",X"55",X"A9",X"55", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/build_id.tcl b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/build_id.v b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/build_id.v new file mode 100644 index 00000000..744846ed --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "111346" diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c3e13c5c --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1094 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..7e8a9995 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,370 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..7d407fb8 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2027 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..6904b66b --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..998033ef --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd new file mode 100644 index 00000000..33d61068 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/cpu/T80a.vhd @@ -0,0 +1,280 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80a is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLK_EN_SYS : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80a; + +architecture rtl of T80a is + + signal CEN : std_logic; + signal Reset_s : std_logic; + signal IntCycle_n : std_logic; + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal MREQ : std_logic; + signal MReq_Inhibit : std_logic; + signal Req_Inhibit : std_logic; + signal RD : std_logic; + signal MREQ_n_i : std_logic; + signal IORQ_n_i : std_logic; + signal RD_n_i : std_logic; + signal WR_n_i : std_logic; + signal RFSH_n_i : std_logic; + signal BUSAK_n_i : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal DO_Reg : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal Wait_s : std_logic; + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + -- clock enable supplied from clocking system + CEN <= CLK_EN_SYS; + + BUSAK_n <= BUSAK_n_i; + MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); + RD_n_i <= not RD or Req_Inhibit; + + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DO <= DO_Reg; + +-- process (RESET_n, CLK_n) +-- begin +-- if RESET_n = '0' then +-- Reset_s <= '0'; +-- elsif CLK_n'event and CLK_n = '1' then +-- Reset_s <= '1'; +-- end if; +-- end process; + -- T80 reset input has already proper characteristics: + -- * asynchronous assertion + -- * deassertion synchronous to CLK_n (main_clk) + Reset_s <= RESET_n; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, + DInst => DI, + DI => DI_Reg, + DO => DO_Reg, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + if CEN = '1' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then + DI_Reg <= to_x01(DI); + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + WR_n_i <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + WR_n_i <= '1'; + if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! + WR_n_i <= not Write; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + Req_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + Req_Inhibit <= '1'; + else + Req_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + MReq_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + MReq_Inhibit <= '1'; + else + MReq_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process(Reset_s,CLK_n) + begin + if Reset_s = '0' then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + + if MCycle = "001" then + if TState = "001" then + RD <= IntCycle_n; + MREQ <= IntCycle_n; + IORQ_n_i <= IntCycle_n; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '1'; + end if; + if TState = "100" then + MREQ <= '0'; + end if; + else + if TState = "001" and NoRead = '0' then + RD <= not Write; + IORQ_n_i <= not IORQ; + MREQ <= not IORQ; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + end if; + end if; + + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/dac.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/dac.vhd new file mode 100644 index 00000000..75d941cb --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 6 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/dpram.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/hq2x.sv b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/keyboard.v b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd new file mode 100644 index 00000000..b19b5cf8 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug.vhd @@ -0,0 +1,243 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- Toplevel port for Papilio Plus board. +-- +------------------------------------------------------------------------------- +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library ieee; + use ieee.numeric_std.all; + +use work.ladybug_dip_pack.all; + +entity ladybugt is +port ( + -- Global Interface ------------------------------------------------------- + CLK_IN : in std_logic; -- 20MHz + I_RESET : in std_logic; + + -- VGA Interface ---------------------------------------------------------- + O_VIDEO_R : out std_logic_vector( 1 downto 0); + O_VIDEO_G : out std_logic_vector( 1 downto 0); + O_VIDEO_B : out std_logic_vector( 1 downto 0); + O_VSYNC : out std_logic; + O_HSYNC : out std_logic; + O_VBLANK : out std_logic; + O_HBLANK : out std_logic; + O_PIXCE : out std_logic; + + -- Audio Interface -------------------------------------------------------- + O_AUDIO : out signed(7 downto 0); + + but_coin_s : in std_logic_vector( 1 downto 0); + but_fire_s : in std_logic_vector( 1 downto 0); + but_bomb_s : in std_logic_vector( 1 downto 0); + but_tilt_s : in std_logic_vector( 1 downto 0); + but_select_s : in std_logic_vector( 1 downto 0); + but_up_s : in std_logic_vector( 1 downto 0); + but_down_s : in std_logic_vector( 1 downto 0); + but_left_s : in std_logic_vector( 1 downto 0); + but_right_s : in std_logic_vector( 1 downto 0) +); +end ladybugt; + +architecture struct of ladybugt is + + signal + ps2_codeready, + clk_20mhz_s, + clk_en_5mhz_s, + ext_res_n_s, + ext_res_s, + audio_s, + vid_hsync, + vid_vsync, + vga_hsync, + vid_comp_sync_n, + vga_vsync : std_logic; + + signal rom_cpu_a_s : std_logic_vector(14 downto 0); + signal rom_cpu_d_s : std_logic_vector( 7 downto 0); + signal rom_cpu_d1 : std_logic_vector( 7 downto 0); + signal rom_cpu_d2 : std_logic_vector( 7 downto 0); + signal rom_cpu_d3 : std_logic_vector( 7 downto 0); + signal rom_cpu_d4 : std_logic_vector( 7 downto 0); + signal rom_cpu_d5 : std_logic_vector( 7 downto 0); + signal rom_cpu_d6 : std_logic_vector( 7 downto 0); + + signal rom_char_a_s : std_logic_vector(11 downto 0); + signal rom_char_d_s : std_logic_vector(15 downto 0); + + signal rom_sprite_a_s : std_logic_vector(11 downto 0); + signal rom_sprite_d_s : std_logic_vector(15 downto 0); + + signal + dac_audio_s, + dip_block_1_s, + dip_block_2_s : std_logic_vector( 7 downto 0) := (others => '0'); + + signal ps2_scancode : std_logic_vector( 9 downto 0) := (others => '0'); + + signal + vid_rgb, + vga_rgb : std_logic_vector(15 downto 0) := (others => '0'); + + signal but_chute_s : std_logic_vector( 1 downto 0) := (others=>'0'); + +begin + + O_PIXCE <= clk_en_5mhz_s; + + but_chute_s <= not but_coin_s(1) & not but_coin_s(0); + + ----------------------------------------------------------------------------- + -- inputs assignments + ----------------------------------------------------------------------------- + ext_res_s <= I_RESET; + ext_res_n_s <= not ext_res_s; + clk_20mhz_s <= CLK_IN; + + ----------------------------------------------------------------------------- + -- Ladybug Machine + ----------------------------------------------------------------------------- + machine_b : entity work.ladybug_machine + port map ( + ext_res_n_i => ext_res_n_s, + clk_20mhz_i => clk_20mhz_s, + clk_en_5mhz_o => clk_en_5mhz_s, + tilt_n_i => but_tilt_s(0), + player_select_n_i => but_select_s, + player_fire_n_i => but_fire_s, + player_up_n_i => but_up_s, + player_right_n_i => but_right_s, + player_down_n_i => but_down_s, + player_left_n_i => but_left_s, + player_bomb_n_i => but_bomb_s, + right_chute_i => but_chute_s(0), + left_chute_i => but_chute_s(1), + dip_block_1_i => dip_block_1_s, + dip_block_2_i => dip_block_2_s, + rgb_r_o => O_VIDEO_R, + rgb_g_o => O_VIDEO_G, + rgb_b_o => O_VIDEO_B, + hsync_n_o => O_HSYNC, + vsync_n_o => O_VSYNC, + vblank_o => O_VBLANK, + hblank_o => O_HBLANK, + audio_o => O_AUDIO, + rom_cpu_a_o => rom_cpu_a_s, + rom_cpu_d_i => rom_cpu_d_s, + rom_char_a_o => rom_char_a_s, + rom_char_d_i => rom_char_d_s, + rom_sprite_a_o => rom_sprite_a_s, + rom_sprite_d_i => rom_sprite_d_s + ); + + ----------------------------------------------------------------------------- + -- Building the DIP Switches - see file ladybug_dip_pack.vhd + ----------------------------------------------------------------------------- + dip_block_1_s <= lb_dip_block_1_c; -- Lady Bug +-- dip_block_1_s <= do_dip_block_1_c; -- Dorodon +-- dip_block_1_s <= ca_dip_block_1_c; -- Cosmic Avenger + dip_block_2_s <= price_dip_block_2_c; -- Common for all games (coins per game pricing) + + ----------------------------------------------------------------------------- + -- Game ROMs + ----------------------------------------------------------------------------- + inst_rom_spritel : entity work.rom_sprite_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s( 7 downto 0) + ); + + inst_rom_spriteu : entity work.rom_sprite_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s(15 downto 8) + ); + + inst_rom_charl : entity work.rom_char_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s( 7 downto 0) + ); + + inst_rom_charu : entity work.rom_char_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s(15 downto 8) + ); + + inst_rom_cpu1 : entity work.rom_cpu1 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d1 + ); + + inst_rom_cpu2 : entity work.rom_cpu2 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d2 + ); + + inst_rom_cpu3 : entity work.rom_cpu3 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d3 + ); + + ----------------------------------------------------------------------------- + -- Program ROMs data mux + ----------------------------------------------------------------------------- + rom_cpu_d_s <= + rom_cpu_d1 when rom_cpu_a_s(14 downto 13) = "00" else + rom_cpu_d2 when rom_cpu_a_s(14 downto 13) = "01" else + rom_cpu_d3 when rom_cpu_a_s(14 downto 13) = "10" else + (others=>'0'); + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_addr_dec.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_addr_dec.vhd new file mode 100644 index 00000000..6d857f6c --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_addr_dec.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_addr_dec.vhd,v 1.10 2005/12/10 14:51:46 arnim Exp $ +-- +-- Address decoder of the CPU Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_addr_dec is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + a_i : in std_logic_vector(15 downto 12); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + mreq_n_i : in std_logic; + rfsh_n_i : in std_logic; + cs_n_o : out std_logic_vector(15 downto 0); + ram_cpu_cs_n_o : out std_logic + ); + +end ladybug_addr_dec; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_addr_dec is + +begin + + ----------------------------------------------------------------------------- + -- Process adec + -- + -- Purpose: + -- Decode the CPU address and generate one-hot chip select signals. + -- Each chip select enables a 4 KByte address segment. + -- + -- The chip select outputs are registered with the 20 MHz clock to + -- break potentially long combinational paths here. + -- + adec: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + cs_n_o <= (others => '1'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- default assignment + cs_n_o <= (others => '1'); + + if a_i(15) = '0' then + if rd_n_i = '0' or wr_n_i = '0' then + cs_n_o(to_integer(unsigned( '0' & a_i(14 downto 12) ))) <= '0'; + end if; + + else + if mreq_n_i = '0' and rfsh_n_i = '1' then + cs_n_o(to_integer(unsigned( '1' & a_i(14 downto 12) ))) <= '0'; + end if; + + end if; + + end if; + end process adec; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cs_ext_ram + -- + -- Purpose: + -- Builds the combinational chip select signal for the external CPU RAM. + -- + cs_ext_ram: process (a_i, + rd_n_i, wr_n_i) + begin + if (rd_n_i = '0' or wr_n_i = '0') and + a_i(15 downto 12) = "0110" then + ram_cpu_cs_n_o <= '0'; + else + ram_cpu_cs_n_o <= '1'; + end if; + end process cs_ext_ram; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_char.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_char.vhd new file mode 100644 index 00000000..1ca149f3 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_char.vhd @@ -0,0 +1,740 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char.vhd,v 1.18 2005/10/10 22:02:14 arnim Exp $ +-- +-- Character Video Module of Lady Bug Machine. +-- +-- This unit contains most of the logic found on schematic page three. +-- Excluded parts are: +-- * the 10 MHz and 5 MHz clock generation +-- moved into separate module on toplevel of Lady Bug machine +-- * the video timing circuitry +-- moved into separate module on toplevel of video unit +-- * the video MUX and RGB conversion unit +-- moved into separate module at toplevel of video unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity ladybug_char is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_char_o : out std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + ha_t_rise_i : in std_logic; + hx_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + hbl_i : in std_logic; + blank_flont_i : in std_logic; + blank_o : out std_logic; + crg_o : out std_logic_vector( 5 downto 1); + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_char; + +architecture rtl of ladybug_char is + + signal flip_screen_q : std_logic; + + signal h0_s, + h1_s, + h2_s : std_logic; + signal h_flip_s, + h_t_flip_s : std_logic_vector(3 downto 0); + signal v_flip_s, + v_t_flip_s : std_logic_vector(3 downto 0); + + signal h_ctrl_d_s, + h_ctrl_s, + h_ctrl_n_s, + h_ctrl_d_out_s, + h_ctrl_d_n_out_s, + h_ctrl_rise_s, + h_ctrl_n_rise_s : std_logic_vector(4 downto 1); + + signal hx_ctrl_q, + hx_ctrl_s, + hx_ctrl_n_rise_s : std_logic; + signal hx_ctrl_clear_q : std_logic; + + signal b1_ff_q, + b1_ff_s, + b1_ff_n_rise_s : std_logic; + + signal wait_q : std_logic; + signal wait_clear_q : std_logic; + + signal cgs_q, + cgs_s, + cgs_rise_s : std_logic; + + signal ram_addr_s : std_logic_vector(9 downto 0); + signal select_a_s : std_logic; + + signal char_ram_cs_n_s, + char_ram_we_n_s : std_logic; + signal col_ram_cs_n_s, + col_ram_we_n_s : std_logic; + signal d_from_char_ram_s : std_logic_vector(7 downto 0); + signal d_from_col_ram_s : std_logic_vector(3 downto 0); + + signal s_q : std_logic_vector( 7 downto 0); + signal d_char_ram_q : std_logic_vector( 7 downto 0); + signal d_col_ram_q : std_logic_vector( 3 downto 0); + + signal d_char_rom_q : std_logic_vector(15 downto 0); + signal crg1_s, + crg2_s, + crg3_q, + crg4_q, + crg5_q : std_logic; + + signal hbl_q,hbl_d : std_logic; + + signal hcnt : integer; + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Process flip + -- + -- Purpose: + -- Implement the flip_screen flag. + -- + flip: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + -- Actually, this asynchronous reset of the ls259 is not 100% + -- equivalent to the real behavior of this circuit. However, + -- the flip_screen latch is modelled like this for the sake of + -- simplicity. It's sufficient for the purpose here. + flip_screen_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if a_i(2 downto 0) = "000" and cs10_n_i = '0' then + flip_screen_q <= d_from_cpu_i(0); + end if; + + end if; + end process flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process h_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + h_flip: process (flip_screen_q, + h_i, h_t_i, + s_q) + variable a_v, b_v, + sum_v : unsigned(8 downto 0); + begin + -- calculate sum + a_v := '0' & unsigned(s_q); + b_v := '0' & unsigned(h_t_i) & unsigned(h_i); + sum_v := a_v + b_v; + + -- h0,1,2 are taken from directly from sum + h0_s <= sum_v(0); + h1_s <= sum_v(1); + h2_s <= sum_v(2); + + -- now flip + for idx in 3 downto 0 loop + h_flip_s(idx) <= flip_screen_q xor sum_v(idx); + h_t_flip_s(idx) <= flip_screen_q xor sum_v(idx + 4); + end loop; + end process h_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process v_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + v_flip: process (flip_screen_q, + v_i, v_t_i) + begin + for idx in 3 downto 0 loop + v_flip_s(idx) <= flip_screen_q xor v_i(idx); + v_t_flip_s(idx) <= flip_screen_q xor v_t_i(idx); + end loop; + end process v_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The Horizontal Control Signals + -- Detailed purpose/meaning is unknown. + ----------------------------------------------------------------------------- + h_ctrl_d_s(1) <= not (not h2_s and (h1_s xor h0_s)); + h_ctrl_d_s(2) <= hx_i; + h_ctrl_d_s(3) <= not ((h1_s xor h0_s) or (not h2_s xor h1_s)); + h_ctrl_d_s(4) <= '0'; + h_ctrl_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + por_n_i => por_n_i, + cl_n_i => vdd_s, + d_i => h_ctrl_d_s, + q_o => h_ctrl_s, + q_n_o => h_ctrl_n_s, + d_o => h_ctrl_d_out_s, + d_n_o => h_ctrl_d_n_out_s + ); + h_ctrl_rise_s <= not h_ctrl_s and h_ctrl_d_out_s; + h_ctrl_n_rise_s <= h_ctrl_s and not h_ctrl_d_n_out_s; + + + ----------------------------------------------------------------------------- + -- Process ctrl_seq + -- + -- Purpose: + -- Implemente the various sequential elements for horizontal control. + -- + ctrl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_ctrl_q <= '0'; + hx_ctrl_clear_q <= '0'; + b1_ff_q <= '0'; + wait_q <= '0'; + wait_clear_q <= '0'; + cgs_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- the HX control flip-flop + hx_ctrl_q <= hx_ctrl_s; + + -- the clear counterpart of hx_ctrl_q + if h_ctrl_s(2) = '0' then + -- pseudo-asynchronous clear + hx_ctrl_clear_q <= '0'; + elsif hx_ctrl_n_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + hx_ctrl_clear_q <= '1'; + end if; + + -- the mysterious B1 flip-flop + b1_ff_q <= b1_ff_s; + + -- the CGS rising edge indicator support flip-flops + cgs_q <= cgs_s; + + -- the WAIT flip-flop + if wait_clear_q = '1' then + -- pseudo-asynchronous clear + wait_q <= '0'; + elsif cgs_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + wait_q <= '1'; + end if; + + -- the clear counterpart of wait_q + if clk_en_4mhz_i = '1' then + wait_clear_q <= wait_q and (h_ctrl_s(3) and (b1_ff_q or hx_ctrl_q)); + end if; + + end if; + end process ctrl_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ctrl_comp + -- + -- Purpose: + -- Implements the combination logic for the horizontal control + -- elements. + -- + ctrl_comp: process (h_ctrl_rise_s, + hx_i, hx_ctrl_q, + hx_ctrl_clear_q, + h_ctrl_n_rise_s, + b1_ff_q, + cgs_q, cs13_n_i) + begin + -- default assignments + hx_ctrl_s <= hx_ctrl_q; + hx_ctrl_n_rise_s <= '0'; + b1_ff_s <= b1_ff_q; + b1_ff_n_rise_s <= '0'; + cgs_s <= cgs_q; + cgs_rise_s <= '0'; + + -- the HX control flip-flop ----------------------------------------------- + if hx_ctrl_clear_q = '1' then + -- pseudo-asynchronous clear + hx_ctrl_s <= '0'; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + elsif h_ctrl_rise_s(1) = '1' then + -- rising edge indicator acts as clock enable instead of clock + if hx_i = '1' then + -- toggle FF + hx_ctrl_s <= not hx_ctrl_q; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + end if; + end if; + + -- the mysterious B1 flip-flop -------------------------------------------- + if hx_ctrl_q = '1' then + -- pseudo-asynchronous clear + b1_ff_s <= '0'; + + if (not b1_ff_q) = '0' then + -- detct rising edge of inverted ouput + b1_ff_n_rise_s <= '1'; + end if; + elsif h_ctrl_n_rise_s(3) = '1' then + -- rising edge indicator acts as clock enable instead of clock + b1_ff_s <= '1'; + end if; + + -- the CGS rising edge indicator support flip-flop ------------------------ + cgs_s <= not cs13_n_i; + cgs_rise_s <= not cgs_q and not cs13_n_i; + + end process ctrl_comp; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_addr + -- + -- Purpose: + -- Multiplexes the CPU address bus and the h+v timing control signals to + -- form the RAM address bus. + -- + ram_addr: process (h_flip_s, h_t_flip_s, + v_flip_s, v_t_flip_s, + a_i, + h_ctrl_s, h_ctrl_n_s, + hx_ctrl_q, + b1_ff_q) + variable a_v, b_v, g_n_v : std_logic; + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + ram_addr_s <= (others => '0'); + + -- logic that drives A input of IC L4 and K4 + a_v := not (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + -- logic that drives B input of IC L4 and K4 + b_v := hx_ctrl_q; + -- logic that drives /G input of IC J4 + g_n_v := hx_ctrl_q and (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + + -- IC L4 and K4: Dual 4:1 Multiplexer ------------------------------------- + vec_v := b_v & a_v; + case vec_v is + when "00" => + ram_addr_s(0) <= h_flip_s (3); + ram_addr_s(1) <= h_t_flip_s(0); + -- + ram_addr_s(2) <= h_t_flip_s(1); + ram_addr_s(3) <= h_t_flip_s(2); + when "01" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when "10" => + ram_addr_s(0) <= v_t_flip_s(1); + ram_addr_s(1) <= v_t_flip_s(2); + -- + ram_addr_s(2) <= v_t_flip_s(3); + ram_addr_s(3) <= '0'; + when "11" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when others => + null; + end case; + + -- IC J4 and H4: Quad 2:1 Multiplexer ------------------------------------- + case a_v is + when '0' => + ram_addr_s(4) <= h_t_flip_s(3) and not g_n_v; + ram_addr_s(7) <= v_t_flip_s(1) and not g_n_v; + ram_addr_s(8) <= v_t_flip_s(2) and not g_n_v; + ram_addr_s(9) <= v_t_flip_s(3) and not g_n_v; + -- + ram_addr_s(5) <= v_flip_s (3); + ram_addr_s(6) <= v_t_flip_s(0); + when '1' => + ram_addr_s(4) <= a_i (4) and not g_n_v; + ram_addr_s(7) <= a_i (7) and not g_n_v; + ram_addr_s(8) <= a_i (8) and not g_n_v; + ram_addr_s(9) <= a_i (9) and not g_n_v; + -- + ram_addr_s(5) <= a_i (5); + ram_addr_s(6) <= a_i (6); + when others => + null; + end case; + + select_a_s <= a_v; + + end process ram_addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_ctrl + -- + -- Purpose: + -- Generate the control signals for the character and color RAMs. + -- This comprises: + -- * reading RAMs while the beam sweeps the screen + -- * reading RAMs to the CPU + -- * writing RAMs from the CPU + -- + ram_ctrl: process (cs13_n_i, + wait_q, + select_a_s, + a_i, + wr_n_i, rd_n_i, + d_from_char_ram_s, d_from_col_ram_s, + clk_en_4mhz_i) + variable cpu_read_char_ram_v : boolean; + variable cpu_write_char_ram_v : boolean; + variable cpu_read_col_ram_v : boolean; + variable cpu_write_col_ram_v : boolean; + variable vec_v : std_logic_vector(2 downto 0); + begin + -- default assignments + char_ram_cs_n_s <= '1'; + char_ram_we_n_s <= '1'; + col_ram_cs_n_s <= '1'; + col_ram_we_n_s <= '1'; + d_from_char_o <= (others => '1'); + cpu_read_char_ram_v := false; + cpu_write_char_ram_v := false; + cpu_read_col_ram_v := false; + cpu_write_col_ram_v := false; + + -- detect and decode CPU access + if clk_en_4mhz_i = '1' and -- operate RAMs with CPU clock + (not cs13_n_i and select_a_s and not wait_q) = '1' then + vec_v := a_i(10) & rd_n_i & wr_n_i; + case vec_v is + when "001" => + cpu_read_char_ram_v := true; + when "010" => + cpu_write_char_ram_v := true; + when "101" => + cpu_read_col_ram_v := true; + when "110" => + cpu_write_col_ram_v := true; + when others => + null; + end case; + end if; + + -- now we are prepared to generate the /CS and /WE signals for the RAMs + if select_a_s = '0' or + cpu_read_char_ram_v or cpu_write_char_ram_v then + char_ram_cs_n_s <= '0'; + end if; + if select_a_s = '0' or + cpu_read_col_ram_v or cpu_write_col_ram_v then + col_ram_cs_n_s <= '0'; + end if; + if cpu_write_char_ram_v then + char_ram_we_n_s <= '0'; + end if; + if cpu_write_col_ram_v then + col_ram_we_n_s <= '0'; + end if; + + -- and we can multiplex the data bus towards the CPU + if cpu_read_char_ram_v then + d_from_char_o <= d_from_char_ram_s; + elsif cpu_read_col_ram_v then + d_from_char_o(3 downto 0) <= d_from_col_ram_s; + end if; + + end process ram_ctrl; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The character RAM + ----------------------------------------------------------------------------- + char_ram_b : entity work.ladybug_char_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => char_ram_cs_n_s, + we_n_i => char_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => d_from_char_ram_s + ); + ----------------------------------------------------------------------------- + -- The color RAM + ----------------------------------------------------------------------------- + col_ram_b : entity work.ladybug_char_col_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => col_ram_cs_n_s, + we_n_i => col_ram_we_n_s, + d_i => d_from_cpu_i(3 downto 0), + d_o => d_from_col_ram_s + ); + + + ----------------------------------------------------------------------------- + -- Process ram_d_seq + -- + -- Purpose: + -- Implements three latch banks that save the output of the character + -- and color RAMs. + -- + ram_d_seq: process (clk_20mhz_i, por_n_i) + variable complex_rising_edge_v : boolean; + begin + if por_n_i = '0' then + s_q <= (others => '0'); + d_char_ram_q <= (others => '0'); + d_col_ram_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- latch data from the character RAM to form input for h_flip ----------- + if hx_ctrl_n_rise_s = '1' then + s_q <= d_from_char_ram_s; + end if; + + -- latch data from the character RAM for ROM address generation --------- + -- there are three sources for a rising edge: + -- 1) falling edge of h_ctrl_n_s(1) + -- => equivalen to rising edge of h_ctrl_s(1) + -- 2) rising edge of hx_ctrl_n_q + -- 3) rising edge of b1_ff_n + -- For each source, the two have to be in a defined state to let + -- the edge propage to the latches. + complex_rising_edge_v := ((h_ctrl_rise_s(1) and + (b1_ff_q or hx_ctrl_q)) or + (hx_ctrl_n_rise_s and + (not b1_ff_q and not h_ctrl_n_s(1))) or + (b1_ff_n_rise_s and + (not hx_ctrl_q and not h_ctrl_s(1)))) = '1'; + if complex_rising_edge_v then + d_char_ram_q <= d_from_char_ram_s; + d_col_ram_q <= d_from_col_ram_s; + end if; + + end if; + end process ram_d_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process latch_rom_d + -- + -- Purpose: + -- Latch the output of the character ROM. + -- + latch_rom_d: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + d_char_rom_q <= (others => '0'); + crg3_q <= '0'; + crg4_q <= '0'; + crg5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if (clk_en_5mhz_i and + h2_s and h1_s and h0_s) = '1' then + d_char_rom_q <= rom_char_d_i; + crg3_q <= d_col_ram_q(0); + crg4_q <= d_col_ram_q(1); + crg5_q <= d_col_ram_q(2); + end if; + + end if; + end process latch_rom_d; + -- + ----------------------------------------------------------------------------- + -- Process hbl_seq + -- + -- Purpose: + -- Implements the flip-flop that latches HBL. + -- + hbl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hbl_q <= '0'; + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + if hcnt /= 255 then + hcnt <= hcnt + 1; + end if; + end if; + if ha_t_rise_i = '1' then + hbl_q <= hbl_i; + if hbl_q = '1' and hbl_i = '0' then + hcnt <= 0; + end if; + end if; + end if; + end process hbl_seq; + -- + ----------------------------------------------------------------------------- + + process (clk_20mhz_i) + begin + if rising_edge(clk_20mhz_i) then + if clk_en_5mhz_i = '1' then + hbl_d <= hbl_q; + + if hcnt < 240 then + hblank_o <= '0'; + else + hblank_o <= '1'; + end if; + + if hbl_d = '0' and hbl_q = '1' then + vblank_o <= not blank_flont_i; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process crg_mux + -- + -- Purpose: + -- Multiplexes the latched character ROM data to CRG1 and CRG2. + -- + crg_mux: process (d_char_rom_q, + h_flip_s, + blank_flont_i, + hbl_q) + variable blank_v : std_logic; + variable idx_v : unsigned(2 downto 0); + begin + blank_v := not (blank_flont_i and not hbl_q); + idx_v := unsigned(h_flip_s(2 downto 0)); + + if blank_v = '0' then + crg1_s <= d_char_rom_q(to_integer('0' & idx_v)); + crg2_s <= d_char_rom_q(to_integer('1' & idx_v)); + else + crg1_s <= '0'; + crg2_s <= '0'; + end if; + + blank_o <= blank_v; + end process crg_mux; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + wait_n_o <= not wait_q; + crg_o(5) <= crg5_q; + crg_o(4) <= crg4_q; + crg_o(3) <= crg3_q; + crg_o(2) <= crg2_s; + crg_o(1) <= crg1_s; + rom_char_a_o( 2 downto 0) <= v_flip_s(2 downto 0); + rom_char_a_o(10 downto 3) <= d_char_ram_q; + rom_char_a_o(11) <= d_col_ram_q(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_chute.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_chute.vhd new file mode 100644 index 00000000..b3255fe0 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_chute.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chute.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaper for a chute input. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chute is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + chute_i : in std_logic; + chute_o : out std_logic + ); + +end ladybug_chute; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_chute is + + -- 2.35e-2 s = 1 / 20,000,000 Hz * 470000 + constant chute_delay_c : natural := 470000; + + signal chute_cnt_q : unsigned(18 downto 0); + + signal chute_sync_q : std_logic_vector(1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process sync + -- + -- Purpose: + -- Synchronize the asynchronous chute input. + -- + sync: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_sync_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + chute_sync_q(0) <= chute_i; + chute_sync_q(1) <= chute_sync_q(0); + + end if; + end process sync; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cnt + -- + -- Purpose: + -- Count the required number of 20 MHz clock cycles before emitting + -- chute event. This is a low pass filter for the rising edge of chute_i. + -- + cnt: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if chute_sync_q(1) = '1' then + if chute_cnt_q = chute_delay_c then + chute_o <= '1'; + else + chute_cnt_q <= chute_cnt_q + 1; + end if; + + else + -- reset counter when chute input goes back to 0 + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + end if; + + end if; + end process cnt; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_chutes.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_chutes.vhd new file mode 100644 index 00000000..7584de89 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_chutes.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chutes.vhd,v 1.4 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaping for the two chute inputs. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chutes is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + cs8_n_i : in std_logic; + nmi_n_o : out std_logic; + int_n_o : out std_logic + ); + +end ladybug_chutes; + +architecture rtl of ladybug_chutes is + + signal right_chute_s, + left_chute_s : std_logic; + signal left_chute_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Pulse shaper for Right Chute + ----------------------------------------------------------------------------- + right_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => right_chute_i, + chute_o => right_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Pulse shaper for Left Chute + ----------------------------------------------------------------------------- + left_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => left_chute_i, + chute_o => left_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Process left_edge + -- + -- Purpose: + -- Implement the edge detector for the left chute. + -- Only a rising edge of the filtered chute input can trigger a new + -- interrupt to the CPU. + -- + left_edge: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + left_chute_q <= '0'; + int_n_o <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + left_chute_q <= left_chute_s; + + if cs8_n_i = '0' then + -- synchronous set, has priority over data path + int_n_o <= '1'; + + -- edge detector + elsif left_chute_s = '1' and left_chute_q = '0' then + int_n_o <= '0'; + + end if; + + end if; + end process left_edge; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + nmi_n_o <= not right_chute_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_clk.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_clk.vhd new file mode 100644 index 00000000..d3e00484 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_clk.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_clk.vhd,v 1.5 2005/10/28 21:17:41 arnim Exp $ +-- +-- Clock generator for the Lady Bug machine. +-- +-- This module generates the clock enables which are required to mimic the +-- different clocks of the Lady Bug boards. +-- +-- Theory of Operation: +-- A PLL is used to tune the external clock to 20 MHz. This forms the +-- main clock which is used by all sequential elements. +-- All derived clocks are built with clock enables to allow a synchronous +-- design style (sort of). +-- +-- Note: +-- The counters and enable signals are reset by the power-on reset. +-- Thus, the "derived clocks" run during normal system reset. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_clk is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_10mhz_n_o : out std_logic; + clk_en_5mhz_o : out std_logic; + clk_en_5mhz_n_o : out std_logic; + clk_en_4mhz_o : out std_logic + ); + +end ladybug_clk; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_clk is + + -- counter for 5 MHz and 10 MHz clock enables + signal clk_cnt_5mhz_q : unsigned(1 downto 0); + -- counter for 4 MHz clock enable + signal clk_cnt_4mhz_q : unsigned(2 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process clk_en + -- + -- Purpose: + -- Generates the clock enables for 10 MHz, 5 MHz, 4 MHz. + -- + clk_en: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_cnt_5mhz_q <= (others => '0'); + clk_cnt_4mhz_q <= (others => '0'); + clk_en_10mhz_o <= '0'; + clk_en_10mhz_n_o <= '0'; + clk_en_5mhz_o <= '0'; + clk_en_5mhz_n_o <= '0'; + clk_en_4mhz_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + + ------------------------------------------------------------------------- + -- 10 MHz / 5 MHz clock domain + -- + -- counter for 10 MHz and 5 MHz clock enables + clk_cnt_5mhz_q <= clk_cnt_5mhz_q + 1; + + -- generate clock enable for 10 MHz + -- enable on every second clock of clk_20mhz_i + clk_en_10mhz_o <= clk_cnt_5mhz_q(0); + -- enable with 180 deg phase shift + clk_en_10mhz_n_o <= not clk_cnt_5mhz_q(0); + + -- generate clock enables for 5 MHz: + -- enable on every forth clock of clk_20mhz_i + if clk_cnt_5mhz_q = "11" then + clk_en_5mhz_o <= '1'; + else + clk_en_5mhz_o <= '0'; + end if; + -- enable with 180 deg phase shift + if clk_cnt_5mhz_q = "01" then + clk_en_5mhz_n_o <= '1'; + else + clk_en_5mhz_n_o <= '0'; + end if; + -- + ------------------------------------------------------------------------- + + + ------------------------------------------------------------------------- + -- 4 MHz domain + -- + -- counter for 4 MHz clock enable, wrap around after 5 clocks + clk_en_4mhz_o <= clk_cnt_4mhz_q(2); + + if clk_cnt_4mhz_q = "100" then + clk_cnt_4mhz_q <= (others => '0'); + else + clk_cnt_4mhz_q <= clk_cnt_4mhz_q + 1; + end if; + -- + ------------------------------------------------------------------------- + + end if; + end process clk_en; + -- + ----------------------------------------------------------------------------- + + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_counter.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_counter.vhd new file mode 100644 index 00000000..d07256bb --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_counter.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------- +-- +-- Synchronous 8-Bit Binary Counter with preset. +-- +-- $Id: ladybug_counter.vhd,v 1.9 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity counter is +port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + reset_n_i : in std_logic; + load_i : in std_logic; + preset_i : in std_logic_vector(7 downto 0); + q_o : out std_logic_vector(7 downto 0); + rise_q_o : out std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0); + co_o : out std_logic +); +end counter; + +architecture rtl of counter is + signal cnt_q : std_logic_vector(7 downto 0); + signal cnt_s : std_logic_vector(7 downto 0); +begin + + seq: process (ck_i, reset_n_i) + begin + if reset_n_i = '0' then + cnt_q <= (others => '0'); + elsif rising_edge(ck_i) then + cnt_q <= cnt_s; + end if; + end process seq; + + adder: process (ck_en_i, cnt_q, load_i, preset_i) + begin + cnt_s <= cnt_q; + + if ck_en_i = '1' then + if load_i = '1' then + cnt_s <= preset_i; + else + cnt_s <= cnt_q + 1; + end if; + end if; + end process adder; + + co_o <= '1' when cnt_q = x"FF" else '0'; + rise_q_o <= cnt_s and not cnt_q; + q_o <= cnt_q; + d_o <= cnt_s; +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd new file mode 100644 index 00000000..7d41074f --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_cpu_unit.vhd @@ -0,0 +1,260 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_unit.vhd,v 1.19 2005/12/10 14:51:51 arnim Exp $ +-- +-- CPU Main Unit of the Lady Bug Machine. +-- +-- Actually, the PCB where the CPU resides on contains also the sound chips and +-- parts of the video controller. For the sake of simplicity, the CPU and chip +-- select logic has been moved into this separate unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_unit is + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + res_n_i : in std_logic; + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + sound_wait_n_i : in std_logic; + wait_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + gpio_in0_i : in std_logic_vector( 7 downto 0); + gpio_in1_i : in std_logic_vector( 7 downto 0); + gpio_in2_i : in std_logic_vector( 7 downto 0); + gpio_in3_i : in std_logic_vector( 7 downto 0); + gpio_extra_i : in std_logic_vector( 7 downto 0); + a_o : out std_logic_vector(10 downto 0); + d_to_cpu_i : in std_logic_vector( 7 downto 0); + d_from_cpu_o : out std_logic_vector( 7 downto 0); + rd_n_o : out std_logic; + wr_n_o : out std_logic; + cs7_n_o : out std_logic; + cs10_n_o : out std_logic; + cs11_n_o : out std_logic; + cs12_n_o : out std_logic; + cs13_n_o : out std_logic + ); + +end ladybug_cpu_unit; + +architecture struct of ladybug_cpu_unit is + + signal t80_clk_en_s : std_logic; + + signal wait_n_s : std_logic; + signal int_n_s : std_logic; + signal nmi_n_s : std_logic; + signal mreq_n_s : std_logic; + signal rd_n_s : std_logic; + signal wr_n_s : std_logic; + signal rfsh_n_s : std_logic; + signal m1_n_s : std_logic; + signal a_s : std_logic_vector(15 downto 0); + signal d_to_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_rom_s, + d_decrypted_s, + d_rom_mux_s : std_logic_vector( 7 downto 0); + signal d_from_ram_s : std_logic_vector( 7 downto 0); + signal d_from_gpio_s : std_logic_vector( 7 downto 0); + + signal cs_n_s : std_logic_vector(15 downto 0); + + signal ram_cpu_cs_n_s : std_logic; + + signal vcc_s : std_logic; + +begin + vcc_s <= '1'; + + wait_n_s <= sound_wait_n_i and wait_n_i; + + ----------------------------------------------------------------------------- + -- The T80 CPU + ----------------------------------------------------------------------------- + -- "wait" has to be modelled with the clock enable because the T80 is not + -- able to enlarge write accesses properly when they are delayed with "wait" + t80_clk_en_s <= clk_en_4mhz_i and wait_n_s; + T80a_b : entity work.T80a + generic map ( + Mode => 0 + ) + port map ( + RESET_n => res_n_i, + CLK_n => clk_20mhz_i, + CLK_EN_SYS => t80_clk_en_s, + WAIT_n => wait_n_s, + INT_n => int_n_s, + NMI_n => nmi_n_s, + BUSRQ_n => vcc_s, + M1_n => m1_n_s, + MREQ_n => mreq_n_s, + IORQ_n => open, + RD_n => rd_n_s, + WR_n => wr_n_s, + RFSH_n => rfsh_n_s, + HALT_n => open, + BUSAK_n => open, + A => a_s, + DI => d_to_cpu_s, + DO => d_from_cpu_s + ); + d_from_cpu_o <= d_from_cpu_s; + + + ----------------------------------------------------------------------------- + -- The CPU RAM + ----------------------------------------------------------------------------- + cpu_ram_b : entity work.ladybug_cpu_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => a_s(11 downto 0), + cs_n_i => cs_n_s(6), + we_n_i => wr_n_s, + d_i => d_from_cpu_s, + d_o => d_from_ram_s + ); + + ----------------------------------------------------------------------------- + -- The Address Decoder + ----------------------------------------------------------------------------- + addr_dec_b : entity work.ladybug_addr_dec + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + a_i => a_s(15 downto 12), + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + mreq_n_i => mreq_n_s, + rfsh_n_i => rfsh_n_s, + cs_n_o => cs_n_s, + ram_cpu_cs_n_o => ram_cpu_cs_n_s + ); + + + ----------------------------------------------------------------------------- + -- The General Purpose IO + ----------------------------------------------------------------------------- + gpio_b : entity work.ladybug_gpio + port map ( + a_i => a_s(1 downto 0), + cs_in_n_i => cs_n_s(9), + cs_extra_n_i => cs_n_s(14), + in0_i => gpio_in0_i, + in1_i => gpio_in1_i, + in2_i => gpio_in2_i, + in3_i => gpio_in3_i, + extra_i => gpio_extra_i, + d_o => d_from_gpio_s + ); + + + ----------------------------------------------------------------------------- + -- The Coin Chutes + ----------------------------------------------------------------------------- + coin_chutes_b : entity work.ladybug_chutes + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + cs8_n_i => cs_n_s(8), + nmi_n_o => nmi_n_s, + int_n_o => int_n_s + ); + + + ----------------------------------------------------------------------------- + -- Decrytion PROMs + ----------------------------------------------------------------------------- + + decrypt_prom : entity work.prom_decrypt + port map ( + CLK => clk_20mhz_i, + ADDR => rom_cpu_d_i, + DATA => d_decrypted_s + ); + + ----------------------------------------------------------------------------- + -- Only opcodes (i.e. instruction fetches) have to be decrypted + ----------------------------------------------------------------------------- + d_rom_mux_s <= d_decrypted_s when m1_n_s = '0' else rom_cpu_d_i; + + ----------------------------------------------------------------------------- + -- Gate Data Bus from ROM + -- The ROM puts data on the data bus within the CPU Main Unit so we do + -- gating here. + ----------------------------------------------------------------------------- + d_from_rom_s <= d_rom_mux_s + when cs_n_s(0) = '0' or cs_n_s(1) = '0' or cs_n_s(2) = '0' or + cs_n_s(3) = '0' or cs_n_s(4) = '0' or cs_n_s(5) = '0' else + (others => '1'); + + + ----------------------------------------------------------------------------- + -- Combine Data Buses + -- Uses an AND of all incoming buses from submodules. Each module has to + -- drive ones when not active so we can save logic complexity here. + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_to_cpu_i and d_from_rom_s and d_from_ram_s and d_from_gpio_s; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + a_o <= a_s(10 downto 0); + rom_cpu_a_o <= a_s(14 downto 0); + rd_n_o <= rd_n_s; + wr_n_o <= wr_n_s; + cs7_n_o <= cs_n_s(7); + cs10_n_o <= cs_n_s(10); + cs11_n_o <= cs_n_s(11); + cs12_n_o <= cs_n_s(12); + cs13_n_o <= cs_n_s(13); + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_dip_pack.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_dip_pack.vhd new file mode 100644 index 00000000..ebff8ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_dip_pack.vhd @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------- +-- +-- $Id: ladybug_dip_pack-p.vhd,v 1.4 2005/10/10 20:52:04 arnim Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package ladybug_dip_pack is + + ----------------------------------------------------------------------------- + -- DIP switch settings for Lady Bug + ----------------------------------------------------------------------------- + constant lb_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- High Score Initials ---------------------------------------------------- + -- 0 = 3-Letter Initials + -- 1 = 10-Letter Initials + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + ----------------------------------------------------------------------------- + -- DIP switch settings for Dorodon + ----------------------------------------------------------------------------- + constant do_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- Bonus Life ------------------------------------------------------------- + -- 0 = 40000 + -- 1 = 20000 + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + + ----------------------------------------------------------------------------- + -- DIP switch settings for Cosmic Avenger + ----------------------------------------------------------------------------- + constant ca_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives per Game --------------------------------------------------------- + -- 00 = 2 Lives + -- 11 = 3 Lives + -- 10 = 4 Lives + -- 01 = 5 Lives + "01" & + -- Initial High Score ----------------------------------------------------- + -- 00 = 0 + -- 11 = 5000 + -- 10 = 8000 + -- 01 = 10000 + "11" & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- High Score Names ------------------------------------------------------- + -- 0 = 3 Letters + -- 1 = 10 Letters + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + constant price_dip_block_2_c : std_logic_vector(7 downto 0) := + -- Pricing Options -------------------------------------------------------- + -- 1111 = 1 coin 1 credit + -- 1110 = 1 coin 2 credits + -- 1101 = 1 coin 3 credits + -- 1100 = 1 coin 4 credits + -- 1011 = 1 coin 5 credits + -- 1010 = 2 coins 1 credit + -- 1001 = 2 coins 3 credits + -- 1000 = 3 coins 1 credit + -- 0111 = 3 coins 2 credit + -- 0110 = 4 coins 1 credit + -- 0101 = 1 coin 1 credit + -- 0100 = 1 coin 1 credit + -- 0011 = 1 coin 1 credit + -- 0010 = 1 coin 1 credit + -- 0001 = 1 coin 1 credit + -- 0000 = 1 coin 1 credit + -- + -- Left Chute + "1111" & + -- Right Chute + "1111"; + +end ladybug_dip_pack; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_gpio.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_gpio.vhd new file mode 100644 index 00000000..6ca21711 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_gpio.vhd @@ -0,0 +1,139 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_gpio.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- General purpose IO input for CPU Main Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_gpio is + + port ( + a_i : in std_logic_vector(1 downto 0); + cs_in_n_i : in std_logic; + cs_extra_n_i : in std_logic; + in0_i : in std_logic_vector(7 downto 0); + in1_i : in std_logic_vector(7 downto 0); + in2_i : in std_logic_vector(7 downto 0); + in3_i : in std_logic_vector(7 downto 0); + extra_i : in std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0) + ); + +end ladybug_gpio; + + +architecture rtl of ladybug_gpio is + +begin + + ----------------------------------------------------------------------------- + -- Process gpio + -- + -- Purpose: + -- Multiplex the IN and EXTRA inputs onto the data bus for CPU. + -- + gpio: process (a_i, + cs_in_n_i, + cs_extra_n_i, + in0_i, + in1_i, + in2_i, + in3_i, + extra_i) + variable cs_n_v : std_logic_vector(1 downto 0); + begin + -- default assignment with inactive bus value + d_o <= (others => '1'); + + cs_n_v := cs_extra_n_i & cs_in_n_i; + case cs_n_v is + -- IN ports and DIP switches selected ----------------------------------- + when "10" => + case a_i is + -- IN 0 addressed + when "00" => + d_o <= in0_i; + -- IN 1 addressed + when "01" => + d_o <= in1_i; + -- DIP 0 addressed + when "10" => + d_o <= in2_i; + -- DIP 1 addressed + when "11" => + d_o <= in3_i; + + when others => + null; + end case; + + -- Extra bank selected -------------------------------------------------- + when "01" => + case a_i is + when "00" => + d_o(1) <= extra_i(7); + d_o(0) <= extra_i(3); + when "01" => + d_o(1) <= extra_i(6); + d_o(0) <= extra_i(2); + when "10" => + d_o(1) <= extra_i(5); + d_o(0) <= extra_i(1); + when "11" => + d_o(1) <= extra_i(4); + d_o(0) <= extra_i(0); + when others => + null; + end case; + + when others => + null; + end case; + + end process gpio; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd new file mode 100644 index 00000000..584b8391 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_machine.vhd @@ -0,0 +1,295 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_machine.vhd,v 1.23 2006/02/07 00:44:21 arnim Exp $ +-- +-- Toplevel of the Lady Bug machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_machine is + port ( + -- Clock and Reset Interface ---------------------------------------------- + ext_res_n_i : in std_logic; + clk_20mhz_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_5mhz_o : out std_logic; + por_n_o : out std_logic; + -- Control Interface ------------------------------------------------------ + tilt_n_i : in std_logic; + player_select_n_i : in std_logic_vector( 1 downto 0); + player_fire_n_i : in std_logic_vector( 1 downto 0); + player_up_n_i : in std_logic_vector( 1 downto 0); + player_right_n_i : in std_logic_vector( 1 downto 0); + player_down_n_i : in std_logic_vector( 1 downto 0); + player_left_n_i : in std_logic_vector( 1 downto 0); + player_bomb_n_i : in std_logic_vector( 1 downto 0); + right_chute_i : in std_logic; + left_chute_i : in std_logic; + -- DIP Switch Interface --------------------------------------------------- + dip_block_1_i : in std_logic_vector( 7 downto 0); + dip_block_2_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Audio Interface -------------------------------------------------------- + audio_o : out signed( 7 downto 0); + -- CPU ROM Interface ------------------------------------------------------ + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + + +end ladybug_machine; + +architecture struct of ladybug_machine is + + -- Clock System ------------------------------------------------------------- + signal clk_en_10mhz_s, + clk_en_10mhz_n_s : std_logic; + signal clk_en_5mhz_s, + clk_en_5mhz_n_s : std_logic; + signal clk_en_4mhz_s : std_logic; + + -- Reset System ------------------------------------------------------------- + signal por_n_s : std_logic; + signal res_n_s : std_logic; + + signal sound_wait_n_s : std_logic; + signal wait_n_s : std_logic; + signal a_s : std_logic_vector(10 downto 0); + signal d_to_cpu_s, + d_from_cpu_s, + d_from_video_s : std_logic_vector( 7 downto 0); + signal rd_n_s, + wr_n_s : std_logic; + signal cs7_n_s, + cs10_n_s, + cs11_n_s, + cs12_n_s, + cs13_n_s : std_logic; + signal vc_s, + vbl_tick_n_s, + vbl_buf_s : std_logic; + + signal gpio_in0_s, + gpio_in1_s, + gpio_in2_s, + gpio_in3_s, + gpio_extra_s : std_logic_vector( 7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk_b : entity work.ladybug_clk + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + clk_en_10mhz_o => clk_en_10mhz_s, + clk_en_10mhz_n_o => clk_en_10mhz_n_s, + clk_en_5mhz_o => clk_en_5mhz_s, + clk_en_5mhz_n_o => clk_en_5mhz_n_s, + clk_en_4mhz_o => clk_en_4mhz_s + ); + -- + clk_en_5mhz_o <= clk_en_5mhz_s; + clk_en_10mhz_o <= clk_en_10mhz_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + res_b : entity work.ladybug_res + port map ( + clk_20mhz_i => clk_20mhz_i, + ext_res_n_i => ext_res_n_i, + res_n_o => res_n_s, + por_n_o => por_n_s + ); + -- + por_n_o <= por_n_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Joystick and DIP Switch Mapping + ----------------------------------------------------------------------------- + gpio_in0_s <= tilt_n_i & + player_select_n_i(1) & + player_select_n_i(0) & + player_fire_n_i(0) & + player_up_n_i(0) & + player_right_n_i(0) & + player_down_n_i(0) & + player_left_n_i(0); + gpio_in1_s <= vbl_buf_s & + vbl_tick_n_s & + vc_s & + player_fire_n_i(1) & + player_up_n_i(1) & + player_right_n_i(1) & + player_down_n_i(1) & + player_left_n_i(1); + gpio_in2_s <= dip_block_1_i; + gpio_in3_s <= dip_block_2_i; + gpio_extra_s <= player_bomb_n_i(1) & + '1' & + '1' & + '1' & + player_bomb_n_i(0) & + '1' & + '1' & + '1'; + + + ----------------------------------------------------------------------------- + -- CPU Unit + ----------------------------------------------------------------------------- + cpu_b : entity work.ladybug_cpu_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + res_n_i => res_n_s, + rom_cpu_a_o => rom_cpu_a_o, + rom_cpu_d_i => rom_cpu_d_i, + + sound_wait_n_i => sound_wait_n_s, + wait_n_i => wait_n_s, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + gpio_in0_i => gpio_in0_s, + gpio_in1_i => gpio_in1_s, + gpio_in2_i => gpio_in2_s, + gpio_in3_i => gpio_in3_s, + gpio_extra_i => gpio_extra_s, + a_o => a_s, + d_to_cpu_i => d_to_cpu_s, + d_from_cpu_o => d_from_cpu_s, + rd_n_o => rd_n_s, + wr_n_o => wr_n_s, + cs7_n_o => cs7_n_s, + cs10_n_o => cs10_n_s, + cs11_n_o => cs11_n_s, + cs12_n_o => cs12_n_s, + cs13_n_o => cs13_n_s + ); + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_from_video_s when (cs7_n_s and cs13_n_s) = '0' else (others => '1'); + + ----------------------------------------------------------------------------- + -- Video Unit + ----------------------------------------------------------------------------- + video_b : entity work.ladybug_video_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + res_n_i => res_n_s, + clk_en_10mhz_i => clk_en_10mhz_s, + clk_en_10mhz_n_i => clk_en_10mhz_n_s, + clk_en_5mhz_i => clk_en_5mhz_s, + clk_en_5mhz_n_i => clk_en_5mhz_n_s, + clk_en_4mhz_i => clk_en_4mhz_s, + cs7_n_i => cs7_n_s, + cs10_n_i => cs10_n_s, + cs13_n_i => cs13_n_s, + a_i => a_s, + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + wait_n_o => wait_n_s, + d_from_cpu_i => d_from_cpu_s, + d_from_video_o => d_from_video_s, + vc_o => vc_s, + vbl_tick_n_o => vbl_tick_n_s, + vbl_buf_o => vbl_buf_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n_o, + vblank_o => vblank_o, + hblank_o => hblank_o, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + ----------------------------------------------------------------------------- + -- Sound Unit + ----------------------------------------------------------------------------- + sound_b : entity work.ladybug_sound_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + por_n_i => por_n_s, + cs11_n_i => cs11_n_s, + cs12_n_i => cs12_n_s, + wr_n_i => wr_n_s, + d_from_cpu_i => d_from_cpu_s, + sound_wait_n_o => sound_wait_n_s, + audio_o => audio_o + ); + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_rams.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_rams.vhd new file mode 100644 index 00000000..578d08e7 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_rams.vhd @@ -0,0 +1,340 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_char_ram; + +architecture struct of ladybug_char_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_sprite_ram; + +architecture struct of ladybug_sprite_ram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_col_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character color RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_col_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_char_col_ram; + +architecture struct of ladybug_char_col_ram is + + signal d_s : std_logic_vector(3 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_vram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite VRAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_vram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_sprite_vram; + +architecture struct of ladybug_sprite_vram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_ram.vhd,v 1.1 2005/11/06 15:43:38 arnim Exp $ +-- +-- Wrapper for technology dependent CPU RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 4 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(11 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_cpu_ram; + +architecture struct of ladybug_cpu_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram1_inst: work.spram generic map(12,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_res.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_res.vhd new file mode 100644 index 00000000..85998a10 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_res.vhd @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_res.vhd,v 1.8 2005/10/10 20:52:04 arnim Exp $ +-- +-- Reset generator for the Lady Bug machine. +-- +-- This module generates a reset signal for the whole system synchronous to +-- the main clock. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity ladybug_res is + + port ( + clk_20mhz_i : in std_logic; + ext_res_n_i : in std_logic; + res_n_o : out std_logic; + por_n_o : out std_logic + ); + +end ladybug_res; + +architecture rtl of ladybug_res is + + -- 4.7e-2 s = 1 / 20,000,000 Hz * 940000 + constant res_delay_c : natural := 940000; + + signal res_sync_n_q : std_logic_vector(1 downto 0); + + signal res_delay_q : unsigned(19 downto 0); + signal res_n_q : std_logic; + + signal por_cnt_q : unsigned(1 downto 0) := "00"; + signal por_n_q : std_logic := '0'; +begin + + por_n_o <= por_n_q; + res_n_o <= res_n_q; + + ----------------------------------------------------------------------------- + -- Process por_cnt + -- + -- Purpose: + -- Generate a power-on reset for 4 clock cycles. + -- + por_cnt: process (clk_20mhz_i) + begin + if clk_20mhz_i'event and clk_20mhz_i = '1' then + if por_cnt_q = "11" then + por_n_q <= '1'; + else + por_cnt_q <= por_cnt_q + 1; + end if; + end if; + end process por_cnt; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_sync + -- + -- Purpose: + -- Synchronize asynchronous external reset to main 20 MHz clock. + -- + res_sync: process (clk_20mhz_i, ext_res_n_i, por_n_q) + begin + if ext_res_n_i = '0' or por_n_q = '0' then + res_sync_n_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + res_sync_n_q(0) <= '1'; + res_sync_n_q(1) <= res_sync_n_q(0); + end if; + end process res_sync; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_delay + -- + -- Purpose: + -- Delay reset event (external or power-on) by 4.7e-2 s. + -- Reset delay is taken from Lady Bug reset circuit using NE555. + -- This duration might be too long for the actual requirements of the + -- FPGA circuit. + -- + res_delay: process (clk_20mhz_i, res_sync_n_q) + begin + if res_sync_n_q(1) = '0' then + res_delay_q <= (others => '0'); + res_n_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if res_delay_q = res_delay_c then + res_n_q <= '1'; + else + res_delay_q <= res_delay_q + 1; + end if; + end if; + end process res_delay; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_rgb.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_rgb.vhd new file mode 100644 index 00000000..1bfcd53c --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_rgb.vhd @@ -0,0 +1,135 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_rgb.vhd,v 1.4 2005/10/10 22:02:14 arnim Exp $ +-- +-- RGB Generation Module of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_rgb is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + crg_i : in std_logic_vector(5 downto 1); + sig_i : in std_logic_vector(4 downto 1); + rgb_r_o : out std_logic_vector(1 downto 0); + rgb_g_o : out std_logic_vector(1 downto 0); + rgb_b_o : out std_logic_vector(1 downto 0) + ); + +end ladybug_rgb; + +architecture rtl of ladybug_rgb is + + signal a_s : std_logic_vector(5 downto 1); + signal rgb_s : std_logic_vector(8 downto 1); + signal rgb_n_q : std_logic_vector(8 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process addr + -- + -- Purpose: + -- Generates the PROM address. + -- + addr: process (crg_i, + sig_i) + variable sig_and_v : std_logic; + begin + sig_and_v := sig_i(1) and sig_i(2) and sig_i(3) and sig_i(4); + + a_s(5) <= crg_i(1) and sig_and_v; + + if not (sig_and_v and (crg_i(1) or crg_i(2))) = '0' then + a_s(4 downto 1) <= crg_i(2) & crg_i(5) & crg_i(4) & crg_i(3); + else + a_s(4 downto 1) <= sig_i; + end if; + + end process addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The RGB Conversion PROM + ----------------------------------------------------------------------------- + rgb_prom_b : entity work.prom_10_2 + port map ( + CLK => clk_20mhz_i, + ADDR => a_s, + DATA => rgb_s + ); + + ----------------------------------------------------------------------------- + -- Process rgb_latch + -- + -- Purpose: + -- Implements the output latch for the RGB values. + -- + rgb_latch: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rgb_n_q <= (others => '1'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + rgb_n_q <= not rgb_s; + end if; + end if; + end process rgb_latch; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rgb_r_o <= rgb_n_q(5+1) & rgb_n_q(0+1); + rgb_g_o <= rgb_n_q(6+1) & rgb_n_q(2+1); + rgb_b_o <= rgb_n_q(7+1) & rgb_n_q(4+1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sprite.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sprite.vhd new file mode 100644 index 00000000..941d997c --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sprite.vhd @@ -0,0 +1,857 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite.vhd,v 1.12 2005/10/10 22:02:14 arnim Exp $ +-- +-- Sprite Video Module of Lady Bug Machine. +-- +-- This unit contains the whole sprite logic which is distributed on the +-- CPU and video boards. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_sprite is +port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + a_i : in std_logic_vector( 9 downto 0); + d_from_cpu_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + hx_i : in std_logic; + ha_d_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_d_i : in std_logic; + blank_flont_i : in std_logic; + blank_i : in std_logic; + sig_o : out std_logic_vector( 4 downto 1); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) +); + +end ladybug_sprite; + +architecture rtl of ladybug_sprite is + + signal sprite_ram_cs_n_s, + sprite_ram_we_n_s, + clk_5mhz_n_q, + clk_en_eck_s, + clk_en_rd_s, + clk_en_5ck_n_s, + clk_en_6ck_n_s, + clk_en_7ck_n_s, + clk_en_b7_p3_s, + clk_en_e7_3_s, + s6ck_n_s, + s7ck_n_s, + e5_p8_s, + a8_p5_n_s, + ct0_s, + ct1_s, + cr_mux_sel_s, + ck_inh_s, + ck_inh_n_q, + qh1_s, + qh2_s : std_logic; + + signal rb_s, + rb_unflip_s, + rc_s : std_logic_vector( 7 downto 0); + + signal c_s : std_logic_vector(10 downto 0); + signal v_cnt_s : std_logic_vector( 4 downto 0); + signal ra_s : std_logic_vector( 9 downto 0); + + signal ma_s : std_logic_vector(11 downto 0); + signal ma_q : std_logic_vector(11 downto 6); + signal mb_q : std_logic_vector( 1 downto 0); + signal mc_q : std_logic_vector( 6 downto 0); + signal cl_q : std_logic_vector( 4 downto 0); + + signal j7_s : std_logic_vector( 2 downto 0); + signal df_muxed_s : std_logic_vector( 7 downto 0); + + signal lu_a_s : std_logic_vector( 4 downto 0); + signal lu_d_s : std_logic_vector( 7 downto 0); + signal lu_d_mux_s : std_logic_vector( 3 downto 0); + + signal rd_shift_s, + rd_shift_int, + rd_vram_s : std_logic_vector(15 downto 0); + signal rs_s, + rs_int, + rs_n_s : std_logic_vector( 3 downto 0); + signal rs_enable_s : std_logic; + signal shift_oc_n_s : std_logic; + + signal j6_shifter : std_logic_vector( 3 downto 0); + signal h6_shifter : std_logic_vector( 3 downto 0); + signal ctrl_lu_a_s : std_logic_vector( 4 downto 0); + signal ctrl_lu_d_s : std_logic_vector( 7 downto 0); + signal v_cnt_a5_a6_s : std_logic_vector( 7 downto 0); + + signal ctrl_lu_q_d_s, + ctrl_lu_q : std_logic_vector( 6 downto 1); + + signal vram_we_n_s : std_logic; + signal vram_a6_in_s, + vram_a6_out_s, + vram_b6_in_s, + vram_b6_out_s, + vram_c6_in_s, + vram_c6_out_s, + vram_d6_in_s, + vram_d6_out_s : std_logic_vector( 3 downto 0); + + signal ca_q : std_logic_vector( 3 downto 1); + signal ca6_s, + ca7_s, + ca8_s : std_logic; + signal x_s : std_logic_vector( 5 downto 0); + + signal cr_s : std_logic_vector( 9 downto 0); + + signal vram_q : std_logic_vector(15 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- The Vertical Counters C5 D5 + ----------------------------------------------------------------------------- + v_cnt_c5_c6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_b7_p3_s = '1' then + if e5_p8_s = '0' then + v_cnt_s <= (v_t_i & "0"); + else + v_cnt_s <= v_cnt_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Counter J7 + ----------------------------------------------------------------------------- + j7_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + j7_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s6ck_n_s = '0' then + j7_s <= not mc_q(6) & mc_q(6) & '0'; + elsif (ct0_s or ct1_s or a8_p5_n_s or ck_inh_s) = '0' then + j7_s <= j7_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Sprite VRAM Counters A5 A6 + ----------------------------------------------------------------------------- + ct0_s <= v_cnt_a5_a6_s(0); + ct1_s <= v_cnt_a5_a6_s(1); + x_s <= v_cnt_a5_a6_s(7 downto 2); + + v_cnt_a5_a6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_a5_a6_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s7ck_n_s = '0' then + v_cnt_a5_a6_s(7 downto 4) <= (rb_s(7 downto 4)); + v_cnt_a5_a6_s(3 downto 0) <= (rb_s(3 downto 2) & not rc_s(7) & not rc_s(6)); + elsif ck_inh_n_q = '1' then + v_cnt_a5_a6_s <=v_cnt_a5_a6_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process sprite_ram_ctrl + -- + -- Purpose: + -- Generates the control signals for the sprite RAM. + -- + sprite_ram_ctrl: process ( cs7_n_i, + vbl_n_i, + a_i, + c_s, v_cnt_s) + variable cpu_access_v : std_logic; + begin + cpu_access_v := not cs7_n_i and not vbl_n_i; + + sprite_ram_we_n_s <= not cpu_access_v; + sprite_ram_cs_n_s <= cpu_access_v nor vbl_n_i; + + if vbl_n_i = '0' then + ra_s <= a_i; + else + ra_s <= v_cnt_s(4 downto 0) & c_s(4 downto 0); + end if; + end process sprite_ram_ctrl; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Sprite RAM P5 N5 + ----------------------------------------------------------------------------- + sprite_ram_b : entity work.ladybug_sprite_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_5mhz_i, + a_i => ra_s, + cs_n_i => sprite_ram_cs_n_s, + we_n_i => sprite_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => rb_s + ); + + ----------------------------------------------------------------------------- + -- Process rc_add + -- + -- Purpose: + -- Implements IC N6 and E6 which add sprite RAM data and Cx signals to + -- form RCx bus. + -- + rc_add: process (rb_s, c_s, v_i) + variable a_v, b_v, + sum_v : std_logic_vector(7 downto 0); + begin + -- prepare the inputs of the adder + a_v(3 downto 0) := rb_s(3 downto 0); + a_v(4) := '1'; + a_v(5) := '0'; + a_v(7 downto 6) := rb_s(1 downto 0); + + b_v(0) := not c_s(6); + b_v(1) := not c_s(7); + b_v(2) := not c_s(8); + b_v(3) := not v_i(3); + b_v(4) := c_s(10); + b_v(5) := '0'; + b_v(7 downto 6) := "11"; + + sum_v := a_v + b_v; + + rc_s <= sum_v; + + end process rc_add; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Sprite Control Logic + ----------------------------------------------------------------------------- + sprite_ctrl_b : entity work.ladybug_sprite_ctrl + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + por_n_i => por_n_i, + vbl_n_i => vbl_n_i, + vbl_d_n_i => vbl_d_n_i, + vc_i => v_i(2), + vc_d_i => vc_d_i, + ha_i => h_i(0), + ha_d_i => ha_d_i, + rb6_i => rb_s(6), + rb7_i => rb_s(7), + rc3_i => rc_s(3), + rc4_i => rc_s(4), + rc5_i => rc_s(5), + j7_b_i => j7_s(1), + j7_c_i => j7_s(2), + clk_en_eck_i => clk_en_eck_s, + c_o => c_s, + clk_en_5ck_n_o => clk_en_5ck_n_s, + clk_en_6ck_n_o => clk_en_6ck_n_s, + clk_en_7ck_n_o => clk_en_7ck_n_s, + s6ck_n_o => s6ck_n_s, + s7ck_n_o => s7ck_n_s, + clk_en_b7_p3_o => clk_en_b7_p3_s, + e5_p8_o => e5_p8_s, + clk_en_e7_3_o => clk_en_e7_3_s, + a8_p5_n_o => a8_p5_n_s + ); + + ----------------------------------------------------------------------------- + -- Process misc_seq + -- + -- Purpose: + -- Implements several sequential elements. + -- + misc_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_n_q <= '0'; + ma_q <= (others => '0'); + mb_q <= (others => '0'); + mc_q <= (others => '0'); + cl_q <= (others => '0'); + ck_inh_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz_n into clock waveform ---------------------------------- + if clk_en_5mhz_n_i = '1' then + clk_5mhz_n_q <= '1'; + elsif clk_en_5mhz_i = '1' then + clk_5mhz_n_q <= '0'; + end if; + + -- 8-Bit Register M6 ---------------------------------------------------- + if clk_en_5ck_n_s = '1' then + mb_q <= rb_s(1 downto 0); + ma_q <= rb_s(7 downto 2); + end if; + + -- 8-Bit Register P6 ---------------------------------------------------- + if clk_en_e7_3_s = '1' then + -- these are inverted based on mc_q(4) + mc_q(3 downto 0) <= rc_s(3 downto 0); + -- inverts sprites horizontally + mc_q(4) <= rb_s(4); + -- inverts sprites vertically + mc_q(5) <= rb_s(5); + -- + mc_q(6) <= rb_s(6); + end if; + + -- 6-Bit Register B6 ---------------------------------------------------- + if clk_en_6ck_n_s = '1' then + cl_q <= rb_s(4 downto 0); + end if; + + -- Flip-Flop H8 --------------------------------------------------------- + if clk_en_10mhz_n_i = '1' then + ck_inh_n_q <= not ck_inh_s; + end if; + + end if; + end process misc_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ma_vec + -- + -- Purpose: + -- Build the ma_s vector. + -- + ma_vec: process ( ma_q, + mb_q, + mc_q, + j7_s) + begin + ma_s(11 downto 6) <= ma_q; + + if mc_q(6) = '0' then + ma_s(5) <= mb_q(1); + ma_s(4) <= mb_q(0); + else + ma_s(5) <= mc_q(3) xor mc_q(4); + ma_s(4) <= mc_q(5) xor j7_s(2); + end if; + + ma_s(3) <= mc_q(2) xor mc_q(4); + ma_s(2) <= mc_q(1) xor mc_q(4); + ma_s(1) <= mc_q(0) xor mc_q(4); + ma_s(0) <= mc_q(5) xor j7_s(0); + end process ma_vec; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process df_mux + -- + -- Purpose: + -- Builds the multiplexed data from Sprite ROM. + -- Two-stage multiplexer: + -- 1) ROM data to DFx: 16->8 + -- 2) DF to input for shift register: 8->8 + -- This is actually a scrambler. + -- + df_mux: process ( rom_sprite_d_i, + cl_q, + mc_q) + variable df_v : std_logic_vector(7 downto 0); + begin + if cl_q(4) = '0' then + -- ROM L7 + df_v := rom_sprite_d_i( 7 downto 0); + else + -- ROM M7 + df_v := rom_sprite_d_i(15 downto 8); + end if; + + if mc_q(5) = '0' then + df_muxed_s(0) <= df_v(1); + df_muxed_s(1) <= df_v(3); + df_muxed_s(2) <= df_v(5); + df_muxed_s(3) <= df_v(7); + -- + df_muxed_s(4) <= df_v(0); + df_muxed_s(5) <= df_v(2); + df_muxed_s(6) <= df_v(4); + df_muxed_s(7) <= df_v(6); + else + df_muxed_s(0) <= df_v(7); + df_muxed_s(1) <= df_v(5); + df_muxed_s(2) <= df_v(3); + df_muxed_s(3) <= df_v(1); + -- + df_muxed_s(4) <= df_v(6); + df_muxed_s(5) <= df_v(4); + df_muxed_s(6) <= df_v(2); + df_muxed_s(7) <= df_v(0); + end if; + + end process df_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Two 8-Bit Shift Registers H6 J6 + ----------------------------------------------------------------------------- + shifters_h6_j6 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + h6_shifter <= (others=>'0'); + j6_shifter <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + if (ct0_s or ct1_s or a8_p5_n_s) = '0' then + h6_shifter <= df_muxed_s(3 downto 0); + j6_shifter <= df_muxed_s(7 downto 4); + else + h6_shifter <= h6_shifter(2 downto 0) & "0"; + j6_shifter <= j6_shifter(2 downto 0) & "0"; + end if; + end if; + end if; + end process; + + qh1_s <= h6_shifter(3); + qh2_s <= j6_shifter(3); + + ----------------------------------------------------------------------------- + -- Sprite Look-up PROM F4 + ----------------------------------------------------------------------------- + lu_a_s(4 downto 2) <= cl_q(2 downto 0); + lu_a_s(1) <= qh2_s; + lu_a_s(0) <= qh1_s; + + prom_F4 : entity work.prom_10_1 + port map ( + CLK => clk_20mhz_i, + ADDR => lu_a_s, + DATA => lu_d_s + ); + + lu_d_mux_s <= lu_d_s(3 downto 0) when cl_q(3) = '0' else lu_d_s(7 downto 4); + + ----------------------------------------------------------------------------- + -- Sprite Control Look-up PROM C4 + ----------------------------------------------------------------------------- + ctrl_lu_a_s(0) <= '1'; + ctrl_lu_a_s(1) <= hx_i; + ctrl_lu_a_s(2) <= clk_5mhz_n_q; + ctrl_lu_a_s(3) <= h_i(0); + ctrl_lu_a_s(4) <= h_i(1); + + prom_C4 : entity work.prom_10_3 + port map ( + CLK => clk_20mhz_i, + ADDR => ctrl_lu_a_s, + DATA => ctrl_lu_d_s + ); + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_seq + -- + -- Purpose: + -- Registers output of Sprite Control Look-up PROM. + -- + ctrl_lu_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ctrl_lu_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + ctrl_lu_q <= ctrl_lu_q_d_s; + end if; + end process ctrl_lu_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_comb + -- + -- Purpose: + -- Combinational logic for the sprite control registers. + -- + ctrl_lu_comb: process ( clk_en_10mhz_i, + ctrl_lu_d_s, + ctrl_lu_q, + ctrl_lu_q_d_s) + begin + -- default assignments + ctrl_lu_q_d_s <= ctrl_lu_q; + clk_en_eck_s <= '0'; + clk_en_rd_s <= '0'; + + -- register control + if clk_en_10mhz_i = '1' then + ctrl_lu_q_d_s <= ctrl_lu_d_s(5 downto 0); + + if ctrl_lu_q(1) = '0' and ctrl_lu_q_d_s(1) = '1' then + -- detect rising edge on ctrl_lu_q(1) + clk_en_eck_s <= '1'; + end if; + + if ctrl_lu_q(6) = '0' and ctrl_lu_q_d_s(6) = '1' then + -- detect rising edge on ctrl_lu_q(6) + clk_en_rd_s <= '1'; + end if; + end if; + + end process ctrl_lu_comb; + -- + shift_oc_n_s <= ctrl_lu_q(1) nand res_n_i; + ck_inh_s <= ctrl_lu_q(2); + cr_mux_sel_s <= ctrl_lu_q(3); + vram_we_n_s <= ctrl_lu_q(4); + rs_enable_s <= ctrl_lu_q(5); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ca_seq + -- + -- Purpose: + -- Implements B5, the register that holds the CS flip-flops. + -- + ca_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ca_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_7ck_n_s = '1' then + ca_q <= c_s(8 downto 6); + end if; + end if; + end process ca_seq; + -- + ca6_s <= ca_q(1); + ca7_s <= ca_q(2); + ca8_s <= ca_q(3); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process vram_mux + -- + -- Purpose: + -- Generates the VRAM address CRx. + -- It implements chips D5, C5 and B5. + -- + vram_mux: process ( h_i, h_t_i, + v_i, + x_s, + ca6_s, ca7_s, ca8_s, + cr_mux_sel_s) + begin + if cr_mux_sel_s = '0' then + -- D5 + cr_s(0) <= h_i(2); + cr_s(1) <= h_i(3); + cr_s(2) <= h_t_i(0); + cr_s(3) <= h_t_i(1); + -- C5 + cr_s(4) <= h_t_i(2); + cr_s(5) <= h_t_i(3); + cr_s(6) <= v_i(0); + cr_s(7) <= v_i(1); + -- B5 + cr_s(8) <= v_i(2); + cr_s(9) <= v_i(3); + + else + -- D5 + cr_s(0) <= x_s(0); + cr_s(1) <= x_s(1); + cr_s(2) <= x_s(2); + cr_s(3) <= x_s(3); + -- C5 + cr_s(4) <= x_s(4); + cr_s(5) <= x_s(5); + cr_s(6) <= ca6_s; + cr_s(7) <= ca7_s; + -- B5 + cr_s(8) <= ca8_s; + cr_s(9) <= not v_i(3); + + end if; + end process vram_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Shift Registers + ----------------------------------------------------------------------------- + shifters_a7_a8_d7_d8_f8 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rd_shift_int <= (others=>'1'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + rs_int <= (qh1_s nor qh2_s) & rs_int(3 downto 1); + rd_shift_int <= + lu_d_mux_s(0) & rd_shift_int(15 downto 13) & + lu_d_mux_s(1) & rd_shift_int(11 downto 9) & + lu_d_mux_s(2) & rd_shift_int( 7 downto 5) & + lu_d_mux_s(3) & rd_shift_int( 3 downto 1); + end if; + end if; + end process; + + rd_shift_s <= rd_shift_int when shift_oc_n_s = '0' else (others=>'1'); + rs_s <= rs_int when shift_oc_n_s = '0' else (others=>'1'); +-- rs_n_s(3) <= not rs_s(3) or not rs_enable_s; +-- rs_n_s(2) <= not rs_s(2) or not rs_enable_s; +-- rs_n_s(1) <= not rs_s(1) or not rs_enable_s; +-- rs_n_s(0) <= not rs_s(0) or not rs_enable_s; + rs_n_s(3) <= rs_s(3) and rs_enable_s; + rs_n_s(2) <= rs_s(2) and rs_enable_s; + rs_n_s(1) <= rs_s(1) and rs_enable_s; + rs_n_s(0) <= rs_s(0) and rs_enable_s; + + ----------------------------------------------------------------------------- + -- Sprite VRAM + ----------------------------------------------------------------------------- + vram_a6_in_s(0) <= rd_shift_s( 0); + vram_a6_in_s(1) <= rd_shift_s( 4); + vram_a6_in_s(2) <= rd_shift_s( 8); + vram_a6_in_s(3) <= rd_shift_s(12); + vram_a6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(0), + we_n_i => vram_we_n_s, + d_i => vram_a6_in_s, + d_o => vram_a6_out_s + ); + -- + vram_b6_in_s(0) <= rd_shift_s( 1); + vram_b6_in_s(1) <= rd_shift_s( 5); + vram_b6_in_s(2) <= rd_shift_s( 9); + vram_b6_in_s(3) <= rd_shift_s(13); + vram_b6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(1), + we_n_i => vram_we_n_s, + d_i => vram_b6_in_s, + d_o => vram_b6_out_s + ); + -- + vram_c6_in_s(0) <= rd_shift_s( 2); + vram_c6_in_s(1) <= rd_shift_s( 6); + vram_c6_in_s(2) <= rd_shift_s(10); + vram_c6_in_s(3) <= rd_shift_s(14); + vram_c6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(2), + we_n_i => vram_we_n_s, + d_i => vram_c6_in_s, + d_o => vram_c6_out_s + ); + -- + vram_d6_in_s(0) <= rd_shift_s( 3); + vram_d6_in_s(1) <= rd_shift_s( 7); + vram_d6_in_s(2) <= rd_shift_s(11); + vram_d6_in_s(3) <= rd_shift_s(15); + vram_d6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(3), + we_n_i => vram_we_n_s, + d_i => vram_d6_in_s, + d_o => vram_d6_out_s + ); + -- Remap VRAM data outputs to the complete bus ------------------------------ + rd_vram_s(15) <= vram_d6_out_s(3) or rs_n_s(3); + rd_vram_s(14) <= vram_c6_out_s(3) or rs_n_s(2); + rd_vram_s(13) <= vram_b6_out_s(3) or rs_n_s(1); + rd_vram_s(12) <= vram_a6_out_s(3) or rs_n_s(0); + -- + rd_vram_s(11) <= vram_d6_out_s(2) or rs_n_s(3); + rd_vram_s(10) <= vram_c6_out_s(2) or rs_n_s(2); + rd_vram_s( 9) <= vram_b6_out_s(2) or rs_n_s(1); + rd_vram_s( 8) <= vram_a6_out_s(2) or rs_n_s(0); + -- + rd_vram_s( 7) <= vram_d6_out_s(1) or rs_n_s(3); + rd_vram_s( 6) <= vram_c6_out_s(1) or rs_n_s(2); + rd_vram_s( 5) <= vram_b6_out_s(1) or rs_n_s(1); + rd_vram_s( 4) <= vram_a6_out_s(1) or rs_n_s(0); + -- + rd_vram_s( 3) <= vram_d6_out_s(0) or rs_n_s(3); + rd_vram_s( 2) <= vram_c6_out_s(0) or rs_n_s(2); + rd_vram_s( 1) <= vram_b6_out_s(0) or rs_n_s(1); + rd_vram_s( 0) <= vram_a6_out_s(0) or rs_n_s(0); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process rd_seq + -- + -- Purpose: + -- Implements the registers saving the RDx bus. + -- + rd_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + vram_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if blank_flont_i = '0' then + -- pseudo-asynchronous clear + vram_q <= (others => '0'); + + elsif clk_en_rd_s = '1' then + if shift_oc_n_s = '0' then + -- take data from shift registers + vram_q <= rd_shift_s; + else + -- take data from VRAM + vram_q <= rd_vram_s; + end if; + end if; + end if; + end process rd_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process sig_mux + -- + -- Purpose: + -- Multiplexes the saved VRAM data to generate the four SIG outputs. + -- + sig_mux: process (vram_q, + h_i, + blank_i) + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + sig_o <= (others => '0'); + + vec_v := (h_i(1) & h_i(0)); + + if blank_i = '0' then + case vec_v is + when "00" => + sig_o(1) <= vram_q( 1); + sig_o(2) <= vram_q( 5); + sig_o(3) <= vram_q( 9); + sig_o(4) <= vram_q(13); + when "01" => + sig_o(1) <= vram_q( 2); + sig_o(2) <= vram_q( 6); + sig_o(3) <= vram_q(10); + sig_o(4) <= vram_q(14); + when "10" => + sig_o(1) <= vram_q( 3); + sig_o(2) <= vram_q( 7); + sig_o(3) <= vram_q(11); + sig_o(4) <= vram_q(15); + when "11" => + sig_o(1) <= vram_q( 0); + sig_o(2) <= vram_q( 4); + sig_o(3) <= vram_q( 8); + sig_o(4) <= vram_q(12); + when others => + null; + end case; + end if; + end process sig_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rom_sprite_a_o <= ma_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sprite_ctrl.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sprite_ctrl.vhd new file mode 100644 index 00000000..f0eaff48 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_sprite_ctrl.vhd @@ -0,0 +1,491 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ctrl.vhd,v 1.8 2005/10/10 22:02:14 arnim Exp $ +-- +-- Control logic of the Sprite module. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +library ieee; +use ieee.numeric_std.all; + +entity ladybug_sprite_ctrl is + + port ( + clk_20mhz_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + por_n_i : in std_logic; + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_i : in std_logic; + vc_d_i : in std_logic; + ha_i : in std_logic; + ha_d_i : in std_logic; + rb6_i : in std_logic; + rb7_i : in std_logic; + rc3_i : in std_logic; + rc4_i : in std_logic; + rc5_i : in std_logic; + j7_b_i : in std_logic; + j7_c_i : in std_logic; + clk_en_eck_i : in std_logic; + c_o : out std_logic_vector(10 downto 0); + clk_en_5ck_n_o : out std_logic; + clk_en_6ck_n_o : out std_logic; + clk_en_7ck_n_o : out std_logic; + s6ck_n_o : out std_logic; + s7ck_n_o : out std_logic; + clk_en_b7_p3_o : out std_logic; + e5_p8_o : out std_logic; + clk_en_e7_3_o : out std_logic; + a8_p5_n_o : out std_logic + ); + +end ladybug_sprite_ctrl; + + +architecture rtl of ladybug_sprite_ctrl is + + signal clk_5mhz_q : std_logic; + + signal a7_p5_s, + a7_p5_q : std_logic; + signal a7_p9_q : std_logic; + + signal a8_p5_q : std_logic; + + signal n4_p5_s, + n4_p5_q : std_logic; + + signal f7_ck_en_s, + f7_cl_s, + f7_qa_s, f7_qb_s, f7_qc_s, f7_qd_s, + f7_da_s, f7_db_s, f7_dc_s, f7_dd_s : std_logic_vector(2 downto 1); + + signal j5_ck_en_s, + j5_cl_s, + j5_qa_s, j5_qb_s, j5_qc_s, j5_qd_s, + j5_da_s, j5_db_s, j5_dc_s, j5_dd_s : std_logic_vector(2 downto 1); + + signal e7_ck_en_s, + e7_cl_n_s : std_logic; + signal e7_d_s, + e7_q_s, e7_q_n_s, + e7_d_out_s, e7_d_out_n_s : std_logic_vector(4 downto 1); + + signal h5_n_s : std_logic_vector(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements various sequential elements. + -- + seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_q <= '0'; + a7_p5_q <= '0'; + a7_p9_q <= '0'; + a8_p5_q <= '0'; + n4_p5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz enable into clock waveform ----------------------------- + if clk_en_5mhz_i = '1' then + clk_5mhz_q <= '1'; + elsif clk_en_5mhz_n_i = '1' then + clk_5mhz_q <= '0'; + end if; + + -- Flip-Flop A7 --------------------------------------------------------- + a7_p5_q <= a7_p5_s; + -- + if clk_en_5mhz_n_i = '1' then + a7_p9_q <= j5_qd_s(2); + end if; + + -- Flip-Flop A8 --------------------------------------------------------- + if clk_en_eck_i = '1' then + a8_p5_q <= j7_b_i nand j7_c_i; + end if; + + -- Flip-Flop N4 --------------------------------------------------------- + n4_p5_q <= n4_p5_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements various combinational signals. + -- + comb: process (a7_p5_q, + vc_i, vc_d_i, + n4_p5_q, + ha_i, ha_d_i, + f7_qd_s) + begin + -- D Input for Flip-Flop N4 ----------------------------------------------- + if a7_p5_q = '0' then + -- pseudo-asynchronous clear + n4_p5_s <= '0'; + elsif (vc_i and not vc_d_i) = '1' then + -- falling edge on VC + n4_p5_s <= '1'; + else + n4_p5_s <= n4_p5_q; + end if; + + -- D-Input for Flip-Flop A7.5 --------------------------------------------- + if (ha_i and not ha_d_i) = '1' then + -- falling edge on HA + a7_p5_s <= f7_qd_s(2); + else + a7_p5_s <= a7_p5_q; + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- F7 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + f7_cl_s(1) <= n4_p5_q and ha_i and vbl_n_i; + f7_cl_s(2) <= f7_cl_s(1); + -- + f7_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => f7_ck_en_s, + por_n_i => por_n_i, + cl_i => f7_cl_s, + qa_o => f7_qa_s, + qb_o => f7_qb_s, + qc_o => f7_qc_s, + qd_o => f7_qd_s, + da_o => f7_da_s, + db_o => f7_db_s, + dc_o => f7_dc_s, + dd_o => f7_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process f7_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in F7. + -- + f7_ck_en: process (j5_qd_s, j5_dd_s, + vbl_n_i, vbl_d_n_i, + ha_i, ha_d_i, + n4_p5_q, n4_p5_s, + f7_qd_s, f7_dd_s, + e7_q_n_s, e7_d_out_n_s, + f7_qb_s, f7_db_s) + + variable ff_q_v, ff_d_v : std_logic; + + begin + + -- combinational result based on flip-flop outputs + ff_q_v := j5_qd_s(2) or ( not ( not ( vbl_n_i and ha_i and n4_p5_q ) ) or not ( not f7_qd_s(2) nand not e7_q_n_s(1) ) ); + + -- combinational result based on flip-flop inputs + ff_d_v := j5_dd_s(2) or ( not ( not ( vbl_d_n_i and ha_d_i and n4_p5_s ) ) or not ( not f7_qd_s(2) nand not e7_d_out_n_s(1) ) ); +-- B7.3 D7.8 D7.8 F6.3 B7.6 + -- rising edge detector on B7.3 + f7_ck_en_s(1) <= not ff_q_v and ff_d_v; + + -- falling edge detector on F7.QB(1) + f7_ck_en_s(2) <= f7_qb_s(1) and not f7_db_s(1); + + end process f7_ck_en; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- J5 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + j5_cl_s(1) <= not vbl_n_i + or -- D7.6 + not( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) + or -- D7.6 + n4_p5_q; + j5_cl_s(2) <= a7_p9_q + or -- B7.8 + ( + not ( + not ( + n4_p5_q + and -- D7.8 + ha_i + and -- D7.8 + vbl_n_i + ) + ) + or -- F6.3 + not ( + not f7_qd_s(2) + nand -- B7.6 + not e7_q_n_s(1) + ) + ); + -- + j5_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => j5_ck_en_s, + por_n_i => por_n_i, + cl_i => j5_cl_s, + qa_o => j5_qa_s, + qb_o => j5_qb_s, + qc_o => j5_qc_s, + qd_o => j5_qd_s, + da_o => j5_da_s, + db_o => j5_db_s, + dc_o => j5_dc_s, + dd_o => j5_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process j5_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in J5. + -- + j5_ck_en: process (ha_i, ha_d_i, + e7_q_s, e7_d_out_s, + j5_qc_s, j5_dc_s) + begin + -- falling edge detector on F6.11 + j5_ck_en_s(1) <= -- Flip-Flop Outputs + ( + not ha_i + nand + e7_q_s(3) + ) + and not -- Flip-Flop Inputs + ( + not ha_d_i + nand + e7_d_out_s(3) + ); + + -- falling edge detector on C7.10 + j5_ck_en_s(2) <= -- Flip-Flop Outputs + ( + j5_qc_s(1) + nor + e7_q_s(2) + ) + and not -- Flip-Flop Inputs + ( + j5_dc_s(1) + nor + e7_d_out_s(2) + ); + end process j5_ck_en; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- E7 - Quad D-Type Flip-Flops with Clear + ----------------------------------------------------------------------------- + e7_d_s(1) <= not rb7_i; + e7_d_s(2) <= not ( + rb7_i + and -- D7.12 + rc5_i + and -- D7.12 + ( + not rc4_i + and -- C7.1 + not ( + not rc3_i + nor -- C6.3 + rb6_i + ) + ) + ); + e7_d_s(3) <= not e7_d_s(2) + and -- C7.4 + not a8_p5_q; + e7_d_s(4) <= '0'; + + -- This clock enable is not 100% equivalent to the schematics. + -- There, h5_n_s(4) could also generate a rising edge for E7 + -- but this is ignored here. It is believed that h5_n_s(4) acts + -- only as a clock enable/suppress for the 5 MHz clock. + -- This implementation suppresses as well a combinational feedback + -- loop from J5/1. + e7_ck_en_s <= clk_en_5mhz_i and not h5_n_s(4); + + e7_cl_n_s <= f7_qd_s(2) + or -- B7.3?? + ( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) after 20 ns; + + e7_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => e7_ck_en_s, + por_n_i => por_n_i, + cl_n_i => e7_cl_n_s, + d_i => e7_d_s, + q_o => e7_q_s, + q_n_o => e7_q_n_s, + d_o => e7_d_out_s, + d_n_o => e7_d_out_n_s + ); + + clk_en_e7_3_o <= not e7_q_s(3) and e7_d_out_s(3); + + + ----------------------------------------------------------------------------- + -- Process h5 + -- + -- Purpose: + -- Implements all functionality regarding H5. + -- + h5: process (j5_qa_s, j5_da_s, + j5_qb_s, j5_db_s, + ha_i, ha_d_i, + vbl_n_i, vbl_d_n_i, + a7_p5_q, a7_p5_s) + variable ff_q_v, ff_d_v : std_logic_vector(7 downto 0); + variable f5_p3_q_v, f5_p3_d_v : std_logic; + + ----------------------------------------------------------------------------- + -- 7445 - BCD to Decimal Decoder + ----------------------------------------------------------------------------- + function ttl_45_f(a, b, c, d : in std_logic) return + std_logic_vector is + variable idx_v : std_logic_vector( 3 downto 0); + variable vec_v : std_logic_vector(15 downto 0); + begin + vec_v := (others => '1'); + + idx_v := d & c & b & a; + vec_v(to_integer(unsigned(idx_v))) := '0'; + + return vec_v(7 downto 0); + end ttl_45_f; + + begin + -- combinational result based on flip-flop outputs + f5_p3_q_v := not a7_p5_q nand vbl_n_i; + ff_q_v := ttl_45_f(a => j5_qa_s(1), + b => j5_qb_s(1), + c => ha_i, + d => f5_p3_q_v); + -- combinational result based on flip-flop inputs + f5_p3_d_v := not a7_p5_s nand vbl_d_n_i; + ff_d_v := ttl_45_f(a => j5_da_s(1), + b => j5_db_s(1), + c => ha_d_i, + d => f5_p3_d_v); + + -- combinational output of H5 is based on flip-flop outputs + h5_n_s <= ff_q_v; + + -- clock enable for flip-flops on /5CK + clk_en_5ck_n_o <= not ff_q_v(5) and ff_d_v(5); + -- clock enable for flip-flops on /6CK + clk_en_6ck_n_o <= not ff_q_v(6) and ff_d_v(6); + -- clock enable for flip-flops on /7CK + clk_en_7ck_n_o <= not ff_q_v(7) and ff_d_v(7); + + s6ck_n_o <= ff_q_v(6); + s7ck_n_o <= ff_q_v(7); + end process h5; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + clk_en_b7_p3_o <= f7_ck_en_s(1); + e5_p8_o <= n4_p5_q + nor -- E5.8 + not ( + f7_qa_s(1) + nand -- F6.8 + f7_qb_s(1) + ); + a8_p5_n_o <= not a8_p5_q; + + c_o( 0) <= j5_qa_s(1); + c_o( 1) <= j5_qb_s(1); + c_o( 2) <= j5_qa_s(2); + c_o( 3) <= j5_qb_s(2); + c_o( 4) <= j5_qc_s(2); + c_o( 5) <= j5_qd_s(2); + c_o( 6) <= f7_qa_s(2); + c_o( 7) <= f7_qb_s(2); + c_o( 8) <= f7_qc_s(2); + c_o( 9) <= f7_qa_s(1); + c_o(10) <= f7_qb_s(1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_video_timing.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_video_timing.vhd new file mode 100644 index 00000000..58a3a818 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_video_timing.vhd @@ -0,0 +1,356 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_timing.vhd,v 1.16 2006/02/07 19:27:38 arnim Exp $ +-- +-- The Video Timing Module of Lady Bug Machine. +-- +-- It implements the horizontal and vertical timing signals including composite +-- sync information. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_video_timing is + + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + -- Horizontal Timing Interface -------------------------------------------- + h_o : out std_logic_vector(3 downto 0); + h_t_o : out std_logic_vector(3 downto 0); + hbl_o : out std_logic; + hx_o : out std_logic; + ha_d_o : out std_logic; + ha_t_rise_o : out std_logic; + -- Vertical Timing Interface ---------------------------------------------- + v_o : out std_logic_vector(3 downto 0); + v_t_o : out std_logic_vector(3 downto 0); + vc_d_o : out std_logic; + vbl_n_o : out std_logic; + vbl_d_n_o : out std_logic; + vbl_t_n_o : out std_logic; + blank_flont_o : out std_logic; + -- RBG Video Interface ---------------------------------------------------- + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic + ); + +end ladybug_video_timing; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_video_timing is + + -- horizontal timing circuit + signal h_preset : std_logic_vector(7 downto 0); + signal h_rise : std_logic_vector(7 downto 0); + signal h_do : std_logic_vector(7 downto 0); + signal h_j2_h2 : std_logic_vector(7 downto 0); + signal h_s : std_logic_vector(7 downto 0); + signal hx_q, + hx_s, + hx_n_s : std_logic; + signal hx_rise_s : std_logic; + signal hbl_q : std_logic; +-- signal hbl_n_s : std_logic; + signal hsync_n_q : std_logic; + signal h_carry_s : std_logic; + signal hd_rise_s : std_logic; + + -- vertical timing circuit + signal v_preset : std_logic_vector(7 downto 0); + signal v_rise : std_logic_vector(7 downto 0); + signal v_do : std_logic_vector(7 downto 0); + signal v_s : std_logic_vector(7 downto 0); + signal vx_q, + vx_n_s : std_logic; + signal vbl_q, + vbl_s, + vbl_n_s : std_logic; + signal vbl_t_q, + vbl_t_s, + vbl_t_n_s : std_logic; + signal vsync_n_q : std_logic; + signal v_carry_s : std_logic; + signal vc_rise_s, + vd_rise_s : std_logic; + signal vb_t_rise_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Horizontal Timing counters J2 H2 + ----------------------------------------------------------------------------- + hd_rise_s <= h_rise(3); + ha_t_rise_o <= h_rise(4); + ha_d_o <= h_do(0); + h_preset <= hx_n_s & hx_n_s & "00" & hx_n_s & "000"; + + h_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + reset_n_i => por_n_i, + load_i => h_carry_s, + preset_i => h_preset, + q_o => h_s, + co_o => h_carry_s, + rise_q_o => h_rise, + d_o => h_do + ); + + ----------------------------------------------------------------------------- + -- Process h_timing + -- + -- Purpose: + -- Implement the horizontal timing circuit. + -- + -- The original circuit has no asynchronous reset. To have a stable + -- behavior on silicon, all sequential elements are cleared with the + -- power-on reset. This assumes that the original chips power-up to + -- these values. + -- + -- See also instantiations of ttl_161. + -- + h_timing: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_q <= '0'; + hbl_q <= '0'; + hsync_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Flip-flops on 5 MHz clock -------------------------------------------- + -- HX + hx_q <= hx_s; + + -- Free running flip-flops ---------------------------------------------- + -- HBL + if (hx_q and not h_s(3)) = '1' then + -- pseudo-asynchronous preset + hbl_q <= '1'; + elsif hd_rise_s = '1' then + -- Rising edge on HD + hbl_q <= hx_q; + end if; + + -- HSYNC + if hx_q = '0' then + -- pseudo-asynchronous preset + hsync_n_q <= '1'; + elsif hd_rise_s = '1' then + -- rising edge on HD + hsync_n_q <= h_s(5); + end if; + + end if; + + end process h_timing; + -- + ----------------------------------------------------------------------------- + + hx_n_s <= not hx_q; +--hbl_n_s <= not hbl_q; + + ----------------------------------------------------------------------------- + -- Process hx_comb + -- + -- Purpose: + -- Implements the combinational logic for hx. Including rising edge + -- detection. + -- + hx_comb: process (clk_en_5mhz_i, h_carry_s, hx_q) + begin + -- default assignments + hx_s <= hx_q; + hx_rise_s <= '0'; + + -- HX + if clk_en_5mhz_i = '1' then + if h_carry_s = '1' then + hx_s <= not hx_q; + + -- flag rising edge of hx_q + if hx_q = '0' then + hx_rise_s <= '1'; + end if; + end if; + end if; + + end process hx_comb; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Vertical Timing counters E5 E2 + ----------------------------------------------------------------------------- + vb_t_rise_s <= v_rise(5); + vd_rise_s <= v_rise(3); + vc_rise_s <= v_rise(2); + vc_d_o <= v_do(2); + v_preset <= vx_n_s & vx_n_s & vx_n_s & vx_q & vx_n_s & '0' & vx_n_s & '0'; + + v_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => hx_rise_s, + reset_n_i => por_n_i, + load_i => v_carry_s, + preset_i => v_preset, + q_o => v_s, + co_o => v_carry_s, + rise_q_o => v_rise, + d_o => v_do + ); + + ----------------------------------------------------------------------------- + -- Process v_timing + -- + -- Purpose: + -- Implement the vertical timing circuit. + -- + -- See process h_timing for reset discussion. + -- + v_timing: process (clk_20mhz_i, por_n_i) + variable preset_v : boolean; + begin + if por_n_i = '0' then + vx_q <= '0'; + vbl_q <= '0'; + vsync_n_q <= '1'; + vbl_t_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Free running flip-flops ---------------------------------------------- + -- VX + if hx_rise_s = '1' then + if v_carry_s = '1' then + vx_q <= vx_n_s; + end if; + end if; + + -- VSYNC + if vc_rise_s = '1' then + -- rising edge on VC + vsync_n_q <= not (v_s(7) and v_s(6) and v_s(5) and v_s(4) and v_s(3) and vx_n_s); + end if; + + -- VBL + vbl_q <= vbl_s; + + -- VBL' + vbl_t_q <= vbl_t_s; + + end if; + end process v_timing; + -- + ----------------------------------------------------------------------------- + + vx_n_s <= not vx_q; + vbl_n_s <= not vbl_q; + vbl_t_n_s <= not vbl_t_q; + + + ----------------------------------------------------------------------------- + -- Process vbl_comb + -- + -- Purpose: + -- Combinational logic for vbl_q and vbl_t_q. + -- + vbl_comb: process (v_s, vb_t_rise_s, vd_rise_s, vx_q, vbl_q, vbl_t_q) + variable preset_v : boolean; + begin + preset_v := (v_s(5) and v_s(6) and v_s(7)) = '1'; + -- VBL + vbl_s <= vbl_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_s <= '1'; + elsif vb_t_rise_s = '1' then + -- rising edge on VB' + vbl_s <= vx_q; + end if; + + -- VBL' + vbl_t_s <= vbl_t_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_t_s <= '1'; + elsif vd_rise_s = '1' then + -- rising edge on VD + vbl_t_s <= vx_q; + end if; + + end process vbl_comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + h_o <= h_s(3 downto 0); + h_t_o <= h_s(7 downto 4); + hbl_o <= hbl_q; + hx_o <= hx_q; + v_o <= v_s(3 downto 0); + v_t_o <= v_s(7 downto 4); + vbl_n_o <= vbl_n_s; + vbl_t_n_o <= vbl_t_n_s; + vbl_d_n_o <= not vbl_s; + hsync_n_o <= hsync_n_q; + vsync_n_o <= vsync_n_q; + comp_sync_n_o <= not hsync_n_q xor vsync_n_q; + + -- I have no idea why there is an additional wire called BLANK FLONT. + -- From the schematics, it is the same as /VBL (just buffered). + blank_flont_o <= vbl_n_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_video_unit.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_video_unit.vhd new file mode 100644 index 00000000..96d58e5f --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ladybug_video_unit.vhd @@ -0,0 +1,240 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_unit.vhd,v 1.22 2006/02/07 00:44:35 arnim Exp $ +-- +-- The Video Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_video_unit is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_video_o : out std_logic_vector( 7 downto 0); + vc_o : out std_logic; + vbl_tick_n_o : out std_logic; + vbl_buf_o : out std_logic; + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_video_unit; + +architecture struct of ladybug_video_unit is + + signal h_s, + h_t_s : std_logic_vector(3 downto 0); + signal ha_d_s, + ha_t_rise_s : std_logic; + signal hbl_s : std_logic; + signal hx_s : std_logic; + + signal v_s, + v_t_s : std_logic_vector(3 downto 0); + signal vc_d_s : std_logic; + signal vbl_n_s, + vbl_d_n_s : std_logic; + + signal blank_flont_s : std_logic; + + signal d_from_char_s : std_logic_vector(7 downto 0); + + signal blank_s : std_logic; + signal crg_s : std_logic_vector(5 downto 1); + + signal sig_s : std_logic_vector(4 downto 1); + + signal comp_sync_n : std_logic; + +begin + comp_sync_n_o <= comp_sync_n and vbl_n_s; + vbl_buf_o <= not vbl_n_s; + ----------------------------------------------------------------------------- + -- Horizontal and Vertical Timing Generator + ----------------------------------------------------------------------------- + timing_b : entity work.ladybug_video_timing + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + h_o => h_s, + h_t_o => h_t_s, + hbl_o => hbl_s, + hx_o => hx_s, + ha_d_o => ha_d_s, + ha_t_rise_o => ha_t_rise_s, + v_o => v_s, + v_t_o => v_t_s, + vc_d_o => vc_d_s, + vbl_n_o => vbl_n_s, + vbl_d_n_o => vbl_d_n_s, + vbl_t_n_o => vbl_tick_n_o, + blank_flont_o => blank_flont_s, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n + ); + vc_o <= v_s(2); + + + ----------------------------------------------------------------------------- + -- Character Module + ----------------------------------------------------------------------------- + char_b : entity work.ladybug_char + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_4mhz_i => clk_en_4mhz_i, + cs10_n_i => cs10_n_i, + cs13_n_i => cs13_n_i, + a_i => a_i, + rd_n_i => rd_n_i, + wr_n_i => wr_n_i, + wait_n_o => wait_n_o, + d_from_cpu_i => d_from_cpu_i, + d_from_char_o => d_from_char_s, + h_i => h_s, + h_t_i => h_t_s, + ha_t_rise_i => ha_t_rise_s, + hx_i => hx_s, + v_i => v_s, + v_t_i => v_t_s, + hbl_i => hbl_s, + blank_flont_i => blank_flont_s, + blank_o => blank_s, + vblank_o => vblank_o, + hblank_o => hblank_o, + crg_o => crg_s, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i + ); + + + ----------------------------------------------------------------------------- + -- Sprite Module + ----------------------------------------------------------------------------- + sprite_b : entity work.ladybug_sprite + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_10mhz_i => clk_en_10mhz_i, + clk_en_10mhz_n_i => clk_en_10mhz_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + cs7_n_i => cs7_n_i, + a_i => a_i(9 downto 0), + d_from_cpu_i => d_from_cpu_i, + h_i => h_s, + h_t_i => h_t_s, + hx_i => hx_s, + ha_d_i => ha_d_s, + v_i => v_s, + v_t_i => v_t_s, + vbl_n_i => vbl_n_s, + vbl_d_n_i => vbl_d_n_s, + vc_d_i => vc_d_s, + blank_flont_i => blank_flont_s, + blank_i => blank_s, + sig_o => sig_s, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + + ----------------------------------------------------------------------------- + -- RGB Generator + ----------------------------------------------------------------------------- + rgb_b : entity work.ladybug_rgb + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + crg_i => crg_s, + sig_i => sig_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o + ); + + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_from_video_o <= d_from_char_s + when cs13_n_i = '0' else + (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/mist_io.v b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/osd.v b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/pll.qip b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/pll.v b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/pll.v new file mode 100644 index 00000000..65715540 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 20, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/scandoubler.v b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/ladybug_sound_unit.vhd new file mode 100644 index 00000000..23ad2a6a --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/ladybug_sound_unit.vhd @@ -0,0 +1,143 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sound_unit.vhd,v 1.4 2006/06/16 22:41:37 arnim Exp $ +-- +-- Sound Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_sound_unit is + + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + por_n_i : in std_logic; + cs11_n_i : in std_logic; + cs12_n_i : in std_logic; + wr_n_i : in std_logic; + d_from_cpu_i : in std_logic_vector(7 downto 0); + sound_wait_n_o : out std_logic; + audio_o : out signed(7 downto 0) + ); + +end ladybug_sound_unit; + +architecture struct of ladybug_sound_unit is + + signal ready_b1_s, + ready_c1_s : std_logic; + + signal aout_b1_s, + aout_c1_s : signed(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip B1 + ----------------------------------------------------------------------------- + snd_b1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs11_n_i, + we_n_i => wr_n_i, + ready_o => ready_b1_s, + d_i => d_from_cpu_i, + aout_o => aout_b1_s + ); + + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip C1 + ----------------------------------------------------------------------------- + snd_c1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs12_n_i, + we_n_i => wr_n_i, + ready_o => ready_c1_s, + d_i => d_from_cpu_i, + aout_o => aout_c1_s + ); + + + ----------------------------------------------------------------------------- + -- Process mix + -- + -- Purpose: + -- Mix the digital audio of the two SN76489 instances. + -- Additional care is taken to avoid audio overfow/clipping. + -- + mix: process (aout_b1_s, + aout_c1_s) + variable sum_v : signed(8 downto 0); + begin + sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9); + + if sum_v > 127 then + audio_o <= to_signed(127, 8); + elsif sum_v < -128 then + audio_o <= to_signed(-128, 8); + else + audio_o <= RESIZE(sum_v, 8); + end if; + + end process mix; + -- + ----------------------------------------------------------------------------- + + + sound_wait_n_o <= ready_b1_s and ready_c1_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING new file mode 100644 index 00000000..60549be5 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README new file mode 100644 index 00000000..33630144 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/README @@ -0,0 +1,143 @@ + +An SN76489AN Compatible Implementation in VHDL +============================================== +Version: $Date: 2006/06/18 19:28:40 $ + +Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +See the file COPYING. + + +Integration +----------- + +The sn76489 design exhibits all interface signals as the original chip. It +only differs in the audio data output which is provided as an 8 bit signed +vector instead of an analog output pin. + + generic ( + clock_div_16_g : integer := 1 + -- Set to '1' when operating the design in SN76489 mode. The primary clock + -- input is divided by 16 in this variant. The data sheet mentions the + -- SN76494 which contains a divide-by-2 clock input stage. Set the generic + -- to '0' to enable this mode. + ); + port ( + clock_i : in std_logic; + -- Primary clock input + -- Drive with the target frequency or any integer multiple of it. + + clock_en_i : in std_logic; + -- Clock enable + -- A '1' on this input qualifies a valid rising edge on clock_i. A '0' + -- disables the next rising clock edge, effectivley halting the design + -- until the next enabled rising clock edge. + -- Can be used to run the core at lower frequencies than applied on + -- clock_i. + + res_n_i : in std_logic; + -- Asynchronous low active reset input. + -- Sets all sequential elements to a known state. + + ce_n_i : in std_logic; + -- Chip enable, low active. + + we_n_i : in std_logic; + -- Write enable, low active. + + ready_o : out std_logic; + -- Ready indication to microprocessor. + + d_i : in std_logic_vector(0 to 7); + -- Data input + -- MSB 0 ... 7 LSB + + aout_o : out signed(0 to 7) + -- Audio output, signed vector + -- MSB/SIGN 0 ... 7 LSB + ); + + +Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the +MSB and bit 7 to be the LSB. This has been implemented according to TI's data +sheet, thus all register/data format figures apply 1:1 for this design. +Many systems will flip the system data bus bit wise before it is connected to +this PSG. This is simply achieved with the following VHDL construct: + + signal data_s : std_logic_vector(7 downto 0); + + ... + d_i => data_s, + ... + +d_i and data_s will be assigned from left to right, resulting in the expected +bit assignment: + + d_i data_s + 0 7 + 1 6 + ... + 6 1 + 7 0 + + +As this design is fully synchronous, care has to be taken when the design +replaces an SN76489 in asynchronous mode. No problems are expected when +interfacing the code to other synchronous components. + + +Design Hierarchy +---------------- + + sn76489_top + | + +-- sn76489_latch_ctrl + | + +-- sn76489_clock_div + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + \-- sn76489_noise + | + \-- sn76489_attentuator + +Resulting compilation sequence: + + sn76489_comp_pack-p.vhd + sn76489_top.vhd + sn76489_latch_ctrl.vhd + sn76489_latch_ctrl-c.vhd + sn76489_clock_div.vhd + sn76489_clock_div-c.vhd + sn76489_attenuator.vhd + sn76489_attenuator-c.vhd + sn76489_tone.vhd + sn76489_tone-c.vhd + sn76489_noise.vhd + sn76489_noise-c.vhd + sn76489_top-c.vhd + +Skip the files containing VHDL configurations when analyzing the code for +synthesis. + + +References +---------- + +* TI Data sheet SN76489.pdf + ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf + +* John Kortink's article on the SN76489: + http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ + +* Maxim's "SN76489 notes" in + http://www.smspower.org/maxim/docs/SN76489.txt diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd new file mode 100644 index 00000000..444064e5 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $ +-- +-- Attenuator Module +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_attenuator is + + port ( + attenuation_i : in std_logic_vector(0 to 3); + factor_i : in signed(0 to 1); + product_o : out signed(0 to 7) + ); + +end sn76489_attenuator; + + +architecture rtl of sn76489_attenuator is + +begin + + ----------------------------------------------------------------------------- + -- Process attenuate + -- + -- Purpose: + -- Determine the attenuation and generate the resulting product. + -- + -- The maximum attenuation value is 31 which corresponds to volume off. + -- As described in the data sheet, the maximum "playing" attenuation is + -- 28 = 16 + 8 + 4 + -- + -- The table for the volume constants is derived from the following + -- formula (each step is 2dB voltage): + -- v(0) = 31 + -- v(n+1) = v(n) * 0.79432823 + -- + attenuate: process (attenuation_i, + factor_i) + + type volume_t is array (natural range 0 to 15) of natural; + constant volume_c : volume_t := + (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0); + + variable attenuation_v : unsigned(attenuation_i'range); + variable volume_v : signed(product_o'range); + + begin + + attenuation_v := unsigned(attenuation_i); + + -- volume look-up table + volume_v := to_signed(volume_c(to_integer(attenuation_v)), + product_o'length); + + -- this replaces a multiplier and consumes a bit fewer + -- resources + case to_integer(factor_i) is + when +1 => + product_o <= volume_v; + when -1 => + product_o <= -volume_v; + when others => + product_o <= (others => '0'); + end case; + + end process attenuate; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd new file mode 100644 index 00000000..eab86beb --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $ +-- +-- Clock Divider Circuit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_clock_div is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + clk_en_o : out boolean + ); + +end sn76489_clock_div; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_clock_div is + + signal cnt_s, + cnt_q : unsigned(3 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential counter element. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + cnt_q <= (others => '0'); + elsif clock_i'event and clock_i = '1' then + cnt_q <= cnt_s; + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational counter logic. + -- + comb: process (clock_en_i, + cnt_q) + begin + -- default assignments + cnt_s <= cnt_q; + clk_en_o <= false; + + if clock_en_i = '1' then + + if cnt_q = 0 then + clk_en_o <= true; + + if clock_div_16_g = 1 then + cnt_s <= to_unsigned(15, cnt_q'length); + elsif clock_div_16_g = 0 then + cnt_s <= to_unsigned( 1, cnt_q'length); + else + -- pragma translate_off + assert false + report "Generic clock_div_16_g must be either 0 or 1." + severity failure; + -- pragma translate_on + end if; + + else + cnt_s <= cnt_q - 1; + + end if; + + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd new file mode 100644 index 00000000..789720c2 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd @@ -0,0 +1,138 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Latch Control Unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_latch_ctrl is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector(0 to 7); + ready_o : out std_logic; + tone1_we_o : out boolean; + tone2_we_o : out boolean; + tone3_we_o : out boolean; + noise_we_o : out boolean; + r2_o : out std_logic + ); + +end sn76489_latch_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_latch_ctrl is + + signal reg_q : std_logic_vector(0 to 2); + signal we_q : boolean; + signal ready_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + reg_q <= (others => '0'); + we_q <= false; + ready_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + -- READY Flag Output ---------------------------------------------------- + if ready_q = '0' and we_q then + if clk_en_i then + -- assert READY when write access happened + ready_q <= '1'; + end if; + elsif ce_n_i = '1' then + -- deassert READY when access has finished + ready_q <= '0'; + end if; + + -- Register Selection --------------------------------------------------- + if ce_n_i = '0' and we_n_i = '0' then + if clk_en_i then + if d_i(0) = '1' then + reg_q <= d_i(1 to 3); + end if; + we_q <= true; + end if; + else + we_q <= false; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + tone1_we_o <= reg_q(0 to 1) = "00" and we_q; + tone2_we_o <= reg_q(0 to 1) = "01" and we_q; + tone3_we_o <= reg_q(0 to 1) = "10" and we_q; + noise_we_o <= reg_q(0 to 1) = "11" and we_q; + + r2_o <= reg_q(2); + + ready_o <= ready_q + when ce_n_i = '0' else + '1'; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd new file mode 100644 index 00000000..688bdd56 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_noise.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Noise Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_noise is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + tone3_ff_i : in std_logic; + noise_o : out signed(0 to 7) + ); + +end sn76489_noise; + +architecture rtl of sn76489_noise is + + signal nf_q : std_logic_vector(0 to 1); + signal fb_q : std_logic; + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 6); + signal freq_ff_q : std_logic; + + signal shift_source_s, + shift_source_q : std_logic; + signal shift_rise_edge_s : boolean; + + signal lfsr_q : std_logic_vector(0 to 15); + + signal freq_s : signed(0 to 1); + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + nf_q <= (others => '0'); + fb_q <= '0'; + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to control register + -- both access types can write to the control register! + nf_q <= d_i(6 to 7); + fb_q <= d_i(5); + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- reload frequency counter according to NF setting + case nf_q is + when "00" => + freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length); + when "01" => + freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length); + when "10" => + freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length); + when others => + null; + end case; + + freq_ff_q <= not freq_ff_q; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Multiplex the source of the LFSR's shift enable + ----------------------------------------------------------------------------- + shift_source_s <= tone3_ff_i + when nf_q = "11" else + freq_ff_q; + + ----------------------------------------------------------------------------- + -- Process rise_edge + -- + -- Purpose: + -- Detect the rising edge of the selected LFSR shift source. + -- + rise_edge: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + shift_source_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + shift_source_q <= shift_source_s; + end if; + end if; + end process rise_edge; + -- + ----------------------------------------------------------------------------- + + -- detect rising edge on shift source + shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1'; + + + ----------------------------------------------------------------------------- + -- Process lfsr + -- + -- Purpose: + -- Implements the LFSR that generates noise. + -- Note: This implementation shifts the register right, i.e. from index + -- 15 towards 0 => bit 15 is the input, bit 0 is the output + -- + -- Tapped bits according to MAME's sn76496.c, implemented in function + -- lfsr_tapped_f. + -- + lfsr: process (clock_i, res_n_i) + + function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is + constant tapped_bits_c : std_logic_vector(0 to 15) + -- tapped bits are 0, 2, 15 + := "1010000000000001"; + variable parity_v : std_logic; + begin + parity_v := '0'; + + for idx in lfsr'low to lfsr'high loop + parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx)); + end loop; + + return parity_v; + end; + + begin + if res_n_i = '0' then + -- reset LFSR to "0000000000000001" + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if we_i and r2_i = '0' then + -- write to noise register + -- -> reset LFSR + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif shift_rise_edge_s then + + -- shift LFSR left towards MSB + for idx in lfsr_q'right-1 downto lfsr_q'left loop + lfsr_q(idx) <= lfsr_q(idx+1); + end loop; + + -- determine input bit + if fb_q = '0' then + -- "Periodic" Noise + -- -> input to LFSR is output + lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left); + else + -- "White" Noise + -- -> input to LFSR is parity of tapped bits + lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q); + end if; + + end if; + + end if; + end if; + end process lfsr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map output of LFSR to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when lfsr_q(0) = '1' else + to_signed( 0, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => noise_o + ); + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd new file mode 100644 index 00000000..3658efcc --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_tone.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $ +-- +-- Tone Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_tone is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + ff_o : out std_logic; + tone_o : out signed(0 to 7) + ); + +end sn76489_tone; + +architecture rtl of sn76489_tone is + + signal f_q : std_logic_vector(0 to 9); + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 9); + signal freq_ff_q : std_logic; + + signal freq_s : signed(0 to 1); + + function all_zero(a : in std_logic_vector) return boolean is + variable result_v : boolean; + begin + result_v := true; + + for idx in a'low to a'high loop + if a(idx) /= '0' then + result_v := false; + end if; + end loop; + + return result_v; + end; + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + f_q <= (others => '0'); + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to frequency register + if d_i(0) = '0' then + f_q(0 to 5) <= d_i(2 to 7); + else + f_q(6 to 9) <= d_i(4 to 7); + end if; + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- update counter from frequency register + freq_cnt_q <= unsigned(f_q); + + -- and toggle the frequency flip-flop if enabled + if not all_zero(f_q) then + freq_ff_q <= not freq_ff_q; + else + -- if frequency setting is 0, then keep flip-flop at +1 + freq_ff_q <= '1'; + end if; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map frequency flip-flop to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when freq_ff_q = '1' else + to_signed(-1, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => tone_o + ); + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + ff_o <= freq_ff_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd new file mode 100644 index 00000000..c26d0e1a --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/sound/sn76489/sn76489_top.vhd @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $ +-- +-- Chip Toplevel +-- +-- References: +-- +-- * TI Data sheet SN76489.pdf +-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf +-- +-- * John Kortink's article on the SN76489: +-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ +-- +-- * Maxim's "SN76489 notes" in +-- http://www.smspower.org/maxim/docs/SN76489.txt +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ieee; +use ieee.numeric_std.all; + +entity sn76489_top is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + ready_o : out std_logic; + d_i : in std_logic_vector(0 to 7); + aout_o : out signed(0 to 7) + ); + +end sn76489_top; + +architecture struct of sn76489_top is + + signal clk_en_s : boolean; + + signal tone1_we_s, + tone2_we_s, + tone3_we_s, + noise_we_s : boolean; + signal r2_s : std_logic; + + signal tone1_s, + tone2_s, + tone3_s, + noise_s : signed(0 to 7); + + signal tone3_ff_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock Divider + ----------------------------------------------------------------------------- + clock_div_b : entity work.sn76489_clock_div + generic map ( + clock_div_16_g => clock_div_16_g + ) + port map ( + clock_i => clock_i, + clock_en_i => clock_en_i, + res_n_i => res_n_i, + clk_en_o => clk_en_s + ); + + + ----------------------------------------------------------------------------- + -- Latch Control = CPU Interface + ----------------------------------------------------------------------------- + latch_ctrl_b : entity work.sn76489_latch_ctrl + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + ce_n_i => ce_n_i, + we_n_i => we_n_i, + d_i => d_i, + ready_o => ready_o, + tone1_we_o => tone1_we_s, + tone2_we_o => tone2_we_s, + tone3_we_o => tone3_we_s, + noise_we_o => noise_we_s, + r2_o => r2_s + ); + + + ----------------------------------------------------------------------------- + -- Tone Channel 1 + ----------------------------------------------------------------------------- + tone1_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone1_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone1_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 2 + ----------------------------------------------------------------------------- + tone2_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone2_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone2_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 3 + ----------------------------------------------------------------------------- + tone3_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone3_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => tone3_ff_s, + tone_o => tone3_s + ); + + ----------------------------------------------------------------------------- + -- Noise Channel + ----------------------------------------------------------------------------- + noise_b : entity work.sn76489_noise + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => noise_we_s, + d_i => d_i, + r2_i => r2_s, + tone3_ff_i => tone3_ff_s, + noise_o => noise_s + ); + + + aout_o <= tone1_s + tone2_s + tone3_s + noise_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/spram.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/spram.vhd new file mode 100644 index 00000000..fa4a1fd7 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/spram.vhd @@ -0,0 +1,84 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + widthad_a : natural; + width_a : natural := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ttl_175.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ttl_175.vhd new file mode 100644 index 00000000..b6459332 --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ttl_175.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74175 - Quad D-Type Flip-Flops with Clear +-- +-- $Id: ttl_175.vhd,v 1.5 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_175 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + por_n_i : in std_logic; + cl_n_i : in std_logic; + d_i : in std_logic_vector(4 downto 1); + q_o : out std_logic_vector(4 downto 1); + q_n_o : out std_logic_vector(4 downto 1); + d_o : out std_logic_vector(4 downto 1); + d_n_o : out std_logic_vector(4 downto 1) + ); + +end ttl_175; + + +architecture rtl of ttl_175 is + + signal flops_q, + flops_s : std_logic_vector(4 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process flops + -- + -- Purpose: + -- Implement the sequential elements. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_n_i. + -- + flops: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + flops_q <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + flops_q <= flops_s; + end if; + end process flops; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational logic. + -- + comb: process (flops_q, + cl_n_i, + d_i, + ck_en_i) + begin + -- default assignments + flops_s <= flops_q; + + if cl_n_i = '1' then + if ck_en_i = '1' then + flops_s <= d_i; + end if; + + else + -- pseudo-asynchronous clear + flops_s <= (others => '0'); + end if; + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + q_o <= flops_q; + q_n_o <= not flops_q; + d_o <= flops_s; + d_n_o <= not flops_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ttl_393.vhd b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ttl_393.vhd new file mode 100644 index 00000000..3ef25d4b --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/ttl_393.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74LS393 - Dual 4-Bit Binary Counter +-- +-- $Id: ttl_393.vhd,v 1.3 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_393 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic_vector(2 downto 1); + por_n_i : in std_logic; + cl_i : in std_logic_vector(2 downto 1); + qa_o : out std_logic_vector(2 downto 1); + qb_o : out std_logic_vector(2 downto 1); + qc_o : out std_logic_vector(2 downto 1); + qd_o : out std_logic_vector(2 downto 1); + da_o : out std_logic_vector(2 downto 1); + db_o : out std_logic_vector(2 downto 1); + dc_o : out std_logic_vector(2 downto 1); + dd_o : out std_logic_vector(2 downto 1) + ); + +end ttl_393; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ttl_393 is + + type cnt_q_t is array (natural range 2 downto 1) of unsigned(3 downto 0); + type cnt_d_t is array (natural range 2 downto 1) of unsigned(4 downto 0); + signal cnt_q : cnt_q_t; + signal cnt_s : cnt_d_t; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the flip-flops. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_i. + -- + seq: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + cnt_q(1) <= (others => '0'); + cnt_q(2) <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + cnt_q(1) <= cnt_s(1)(3 downto 0); + cnt_q(2) <= cnt_s(2)(3 downto 0); + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process adder + -- + -- Purpose: + -- Implements the adder. + -- + adder: process (ck_en_i, + cl_i, + cnt_q) + begin + for idx in 2 downto 1 loop + cnt_s(idx) <= '0' & cnt_q(idx); + + if cl_i(idx) = '0' then + if ck_en_i(idx) = '1' then + -- increment upon enable + cnt_s(idx) <= ('0' & cnt_q(idx)) + 1; + end if; + + else + -- pseudo-asynchronous clear + cnt_s(idx) <= (others => '0'); + end if; + end loop; + end process adder; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + qa_o(1) <= cnt_q(1)(0); + qb_o(1) <= cnt_q(1)(1); + qc_o(1) <= cnt_q(1)(2); + qd_o(1) <= cnt_q(1)(3); + qa_o(2) <= cnt_q(2)(0); + qb_o(2) <= cnt_q(2)(1); + qc_o(2) <= cnt_q(2)(2); + qd_o(2) <= cnt_q(2)(3); + da_o(1) <= cnt_s(1)(0); + db_o(1) <= cnt_s(1)(1); + dc_o(1) <= cnt_s(1)(2); + dd_o(1) <= cnt_s(1)(3); + da_o(2) <= cnt_s(2)(0); + db_o(2) <= cnt_s(2)(1); + dc_o(2) <= cnt_s(2)(2); + dd_o(2) <= cnt_s(2)(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/video_mixer.sv b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Ladybug Hardware/LadyBug_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/README.txt b/Arcade/Ladybug Hardware/Snapjack_MiST/README.txt new file mode 100644 index 00000000..dfd6ccd6 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Snapjack port to MiST by Gehstock +-- 14 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Lady Bug hardware +-- Unknown Author on Papilio Plus board. +--------------------------------------------------------------------------------- +-- +-- +-- Only controls are rotated on VGA output. +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + + +ToDo : Sound diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/Release/Snapjack.rbf b/Arcade/Ladybug Hardware/Snapjack_MiST/Release/Snapjack.rbf new file mode 100644 index 00000000..34d39896 Binary files /dev/null and b/Arcade/Ladybug Hardware/Snapjack_MiST/Release/Snapjack.rbf differ diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.qpf b/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.qpf new file mode 100644 index 00000000..4709662f --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Snapjack" diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf b/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf new file mode 100644 index 00000000..55249b70 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.qsf @@ -0,0 +1,206 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:02:22 November 16, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Snapjack_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_top.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_tone.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_noise.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_latch_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_clock_div.vhd +set_global_assignment -name VHDL_FILE rtl/sound/sn76489/sn76489_attenuator.vhd +set_global_assignment -name VHDL_FILE rtl/sound/ladybug_sound_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_sprite_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_cpu1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_u.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/rom_char_l.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_decrypt.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_3.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom_10_1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80a.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_393.vhd +set_global_assignment -name VHDL_FILE rtl/ttl_175.vhd +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_video_timing.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_sprite.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rgb.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_res.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_rams.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_machine.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_gpio.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_dip_pack.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_cpu_unit.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_counter.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_clk.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chutes.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_chute.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_char.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug_addr_dec.vhd +set_global_assignment -name VHDL_FILE rtl/ladybug.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Snapjack.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TOP_LEVEL_ENTITY Snapjack + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(CosmicAvenger) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(CosmicAvenger) +# ------------------- +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.srf b/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/Snapjack.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/clean.bat b/Arcade/Ladybug Hardware/Snapjack_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_1.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_1.vhd new file mode 100644 index 00000000..31cb8a94 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_1.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_1 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"9D",X"11",X"B8",X"00",X"79",X"62",X"18",X"00",X"9E",X"25",X"DA",X"00",X"D7",X"A3",X"79", + X"00",X"DE",X"29",X"74",X"00",X"D4",X"75",X"9D",X"00",X"AD",X"86",X"97",X"00",X"5A",X"4C",X"17"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_2.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_2.vhd new file mode 100644 index 00000000..51862067 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_2.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_2 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F5",X"05",X"54",X"C1",X"C4",X"94",X"84",X"24",X"D0",X"90",X"A1",X"00",X"31",X"50",X"25",X"F5", + X"90",X"31",X"05",X"25",X"05",X"94",X"30",X"41",X"05",X"94",X"61",X"30",X"94",X"50",X"05",X"A5"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_3.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_3.vhd new file mode 100644 index 00000000..a731ff5c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_10_3.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity prom_10_3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of prom_10_3 is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"37",X"3A",X"3A",X"3A",X"3A",X"28",X"28",X"38",X"38", + X"08",X"08",X"38",X"38",X"20",X"20",X"38",X"38",X"20",X"20",X"38",X"38",X"3E",X"3E",X"3E",X"3E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_decrypt.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_decrypt.vhd new file mode 100644 index 00000000..00f98d21 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/prom_decrypt.vhd @@ -0,0 +1,63 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity prom_decrypt is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(7 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of prom_decrypt is + + + type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07", -- 0x0000 + x"08",x"09",x"0A",x"0B",x"0C",x"0D",x"0E",x"0F", -- 0x0008 + x"10",x"11",x"12",x"13",x"14",x"15",x"16",x"17", -- 0x0010 + x"18",x"19",x"1A",x"1B",x"1C",x"1D",x"1E",x"1F", -- 0x0018 + x"20",x"21",x"22",x"23",x"24",x"25",x"26",x"27", -- 0x0020 + x"28",x"29",x"2A",x"2B",x"2C",x"2D",x"2E",x"2F", -- 0x0028 + x"30",x"31",x"32",x"33",x"34",x"35",x"36",x"37", -- 0x0030 + x"38",x"39",x"3A",x"3B",x"3C",x"3D",x"3E",x"3F", -- 0x0038 + x"40",x"41",x"42",x"43",x"44",x"45",x"46",x"47", -- 0x0040 + x"48",x"49",x"4A",x"4B",x"4C",x"4D",x"4E",x"4F", -- 0x0048 + x"50",x"51",x"52",x"53",x"54",x"55",x"56",x"57", -- 0x0050 + x"58",x"59",x"5A",x"5B",x"5C",x"5D",x"5E",x"5F", -- 0x0058 + x"60",x"61",x"62",x"63",x"64",x"65",x"66",x"67", -- 0x0060 + x"68",x"69",x"6A",x"6B",x"6C",x"6D",x"6E",x"6F", -- 0x0068 + x"70",x"71",x"72",x"73",x"74",x"75",x"76",x"77", -- 0x0070 + x"78",x"79",x"7A",x"7B",x"7C",x"7D",x"7E",x"7F", -- 0x0078 + x"80",x"81",x"82",x"83",x"84",x"85",x"86",x"87", -- 0x0080 + x"88",x"89",x"8A",x"8B",x"8C",x"8D",x"8E",x"8F", -- 0x0088 + x"90",x"91",x"92",x"93",x"94",x"95",x"96",x"97", -- 0x0090 + x"98",x"99",x"9A",x"9B",x"9C",x"9D",x"9E",x"9F", -- 0x0098 + x"A0",x"A1",x"A2",x"A3",x"A4",x"A5",x"A6",x"A7", -- 0x00A0 + x"A8",x"A9",x"AA",x"AB",x"AC",x"AD",x"AE",x"AF", -- 0x00A8 + x"B0",x"B1",x"B2",x"B3",x"B4",x"B5",x"B6",x"B7", -- 0x00B0 + x"B8",x"B9",x"BA",x"BB",x"BC",x"BD",x"BE",x"BF", -- 0x00B8 + x"C0",x"C1",x"C2",x"C3",x"C4",x"C5",x"C6",x"C7", -- 0x00C0 + x"C8",x"C9",x"CA",x"CB",x"CC",x"CD",x"CE",x"CF", -- 0x00C8 + x"D0",x"D1",x"D2",x"D3",x"D4",x"D5",x"D6",x"D7", -- 0x00D0 + x"D8",x"D9",x"DA",x"DB",x"DC",x"DD",x"DE",x"DF", -- 0x00D8 + x"E0",x"E1",x"E2",x"E3",x"E4",x"E5",x"E6",x"E7", -- 0x00E0 + x"E8",x"E9",x"EA",x"EB",x"EC",x"ED",x"EE",x"EF", -- 0x00E8 + x"F0",x"F1",x"F2",x"F3",x"F4",x"F5",x"F6",x"F7", -- 0x00F0 + x"F8",x"F9",x"FA",x"FB",x"FC",x"FD",x"FE",x"FF" -- 0x00F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_char_l.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_char_l.vhd new file mode 100644 index 00000000..1780bb2c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_char_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_char_u.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_char_u.vhd new file mode 100644 index 00000000..015e229d --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_char_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_char_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_char_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"7C",X"C6",X"C6",X"C6",X"C6",X"C6",X"7C",X"00",X"18",X"1C",X"18",X"18",X"18",X"18",X"3C", + X"00",X"7C",X"E6",X"C6",X"30",X"0C",X"C6",X"7E",X"00",X"7C",X"C6",X"C0",X"70",X"C6",X"C6",X"7C", + X"00",X"68",X"68",X"6C",X"64",X"FE",X"60",X"F0",X"00",X"7E",X"02",X"7E",X"C2",X"C0",X"C6",X"7C", + X"00",X"7C",X"C6",X"06",X"7E",X"C6",X"C6",X"7C",X"00",X"FE",X"C2",X"C2",X"60",X"30",X"18",X"18", + X"00",X"7C",X"C6",X"C6",X"7C",X"C6",X"C6",X"7C",X"00",X"7C",X"C6",X"C6",X"FC",X"C0",X"C6",X"7C", + X"00",X"70",X"58",X"C8",X"CC",X"FC",X"C6",X"C6",X"00",X"7E",X"CC",X"CC",X"7C",X"CC",X"CC",X"7E", + X"00",X"78",X"CC",X"06",X"06",X"86",X"CC",X"78",X"00",X"3E",X"6C",X"CC",X"CC",X"CC",X"6C",X"3E", + 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if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu1.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu1.vhd new file mode 100644 index 00000000..4f1da5e4 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"00",X"6C",X"C3",X"70",X"02",X"C7",X"C7",X"5E",X"23",X"56",X"23",X"EB",X"C9",X"C7",X"C7", + X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9",X"D1",X"5F",X"CB",X"23",X"16",X"00",X"19",X"5E", + X"23",X"56",X"EB",X"E9",X"C7",X"C7",X"C7",X"C7",X"21",X"01",X"90",X"C3",X"AD",X"01",X"C7",X"C7", + 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if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu2.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu2.vhd new file mode 100644 index 00000000..bc456fab --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu2.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu2 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"74",X"06",X"DD",X"75",X"07",X"DD",X"77",X"08",X"08",X"FD",X"72",X"00",X"FD",X"73",X"01",X"FD", + X"77",X"02",X"C5",X"79",X"87",X"4F",X"87",X"87",X"81",X"5F",X"16",X"00",X"21",X"A3",X"6A",X"19", + X"11",X"89",X"6A",X"06",X"0A",X"1A",X"4E",X"EB",X"12",X"71",X"EB",X"13",X"23",X"10",X"F6",X"C1", + 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if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu3.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu3.vhd new file mode 100644 index 00000000..c72150e9 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_cpu3.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_cpu3 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_cpu3 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"60",X"CB",X"BE",X"CB",X"86",X"CB",X"6E",X"28",X"02",X"3E",X"02",X"DD",X"77",X"02",X"DD",X"36", + X"03",X"0A",X"DD",X"36",X"04",X"00",X"3E",X"00",X"CD",X"A0",X"1B",X"CD",X"21",X"40",X"C3",X"44", + X"40",X"21",X"53",X"41",X"CD",X"39",X"1D",X"CD",X"39",X"1D",X"CD",X"39",X"1D",X"DD",X"7E",X"02", + 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if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_sprite_l.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_sprite_l.vhd new file mode 100644 index 00000000..edab8fcd --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_sprite_l.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_l is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_l is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"3F",X"03",X"F5",X"0F",X"A5",X"3D",X"69",X"E5",X"59",X"DA",X"57",X"D5",X"AB",X"D5",X"57", + X"F0",X"00",X"BF",X"00",X"95",X"C0",X"65",X"70",X"65",X"5C",X"FD",X"5C",X"0D",X"5C",X"33",X"5C", + X"D6",X"81",X"EA",X"80",X"EA",X"80",X"35",X"55",X"0D",X"55",X"03",X"55",X"00",X"FF",X"00",X"00", + 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X"FF",X"C0",X"0D",X"C0",X"0D",X"70",X"FD",X"5C",X"CE",X"57",X"0D",X"97",X"3D",X"67",X"F6",X"5B", + X"D5",X"5F",X"D5",X"50",X"D5",X"50",X"35",X"60",X"0D",X"6A",X"03",X"6A",X"00",X"E9",X"00",X"3F", + X"65",X"9B",X"59",X"9B",X"19",X"97",X"19",X"67",X"59",X"67",X"56",X"6F",X"56",X"70",X"FF",X"C0"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_sprite_u.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_sprite_u.vhd new file mode 100644 index 00000000..5e926cad --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ROM/rom_sprite_u.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity rom_sprite_u is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of rom_sprite_u is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AA",X"AA",X"AA",X"AF",X"2A",X"FF",X"06",X"F5",X"06",X"F1",X"01",X"F5",X"00",X"7C",X"00",X"7F", + X"FF",X"FD",X"FF",X"FD",X"3F",X"FD",X"4F",X"FD",X"43",X"FD",X"03",X"FD",X"0F",X"F7",X"3F",X"F7", + X"00",X"1F",X"00",X"07",X"00",X"07",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"F7",X"FF",X"DF",X"FF",X"5F",X"7D",X"FF",X"17",X"FF",X"01",X"55",X"00",X"15",X"00",X"00", + X"FF",X"7F",X"FF",X"5F",X"FD",X"F7",X"F7",X"F5",X"5F",X"FD",X"DF",X"F5",X"F7",X"F5",X"FD",X"D5", + X"FF",X"C0",X"D5",X"40",X"DA",X"80",X"42",X"A0",X"02",X"A0",X"00",X"A0",X"80",X"A8",X"80",X"28", + X"FD",X"56",X"FD",X"5A",X"F5",X"5A",X"D5",X"A5",X"56",X"6A",X"5A",X"9A",X"0A",X"A5",X"00",X"2A", + X"80",X"0A",X"80",X"02",X"A0",X"00",X"50",X"00",X"A0",X"00",X"A0",X"00",X"54",X"00",X"AA",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"00",X"1F",X"00",X"7F",X"01",X"FF", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv new file mode 100644 index 00000000..29bc7662 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/Snapjack.sv @@ -0,0 +1,192 @@ +//============================================================================ +// Arcade: Snapjack +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Snapjack +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Snapjack;;", + //"O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire signed[7:0] audio_s; +reg [6:0] audio; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(440), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_vid), + .ce_pix_actual(ce_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(blankn ? {r} : "0"), + .G(blankn ? {g&g} : "00"), + .B(blankn ? {b} : "0"), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire blankn = ~(hblank | vblank); + + +ladybugt ladybugt +( + .CLK_IN(clk_sys), + .I_RESET(status[0] | status[6] | buttons[1]), + .O_PIXCE(ce_vid), + + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_VSYNC(vs), + .O_HSYNC(hs), + .O_VBLANK(vblank), + .O_HBLANK(hblank), + + .O_AUDIO(audio_s), + + .but_coin_s(~{1'b0,m_coin}), + .but_fire_s(~{m_fire,m_fire}), + .but_bomb_s(~{m_bomb,m_bomb}), + .but_tilt_s(~{1'b0,1'b0}), + .but_select_s(~{m_start2,m_start1}), + .but_up_s(~{m_up,m_up}), + .but_down_s(~{m_down,m_down}), + .but_left_s(~{m_left,m_left}), + .but_right_s(~{m_right,m_right}) +); + +assign audio = audio_s; + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/build_id.tcl b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/build_id.v b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/build_id.v new file mode 100644 index 00000000..ff95db6c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "182358" diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..c3e13c5c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1094 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..7e8a9995 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,370 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..7d407fb8 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,2027 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..6904b66b --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,220 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..998033ef --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd new file mode 100644 index 00000000..33d61068 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/cpu/T80a.vhd @@ -0,0 +1,280 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, asynchronous top level +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80a is + generic( + Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLK_EN_SYS : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80a; + +architecture rtl of T80a is + + signal CEN : std_logic; + signal Reset_s : std_logic; + signal IntCycle_n : std_logic; + signal IORQ : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal MREQ : std_logic; + signal MReq_Inhibit : std_logic; + signal Req_Inhibit : std_logic; + signal RD : std_logic; + signal MREQ_n_i : std_logic; + signal IORQ_n_i : std_logic; + signal RD_n_i : std_logic; + signal WR_n_i : std_logic; + signal RFSH_n_i : std_logic; + signal BUSAK_n_i : std_logic; + signal A_i : std_logic_vector(15 downto 0); + signal DO_Reg : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser + signal Wait_s : std_logic; + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + -- clock enable supplied from clocking system + CEN <= CLK_EN_SYS; + + BUSAK_n <= BUSAK_n_i; + MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); + RD_n_i <= not RD or Req_Inhibit; + + MREQ_n <= MREQ_n_i; + IORQ_n <= IORQ_n_i; + RD_n <= RD_n_i; + WR_n <= WR_n_i; + RFSH_n <= RFSH_n_i; + A <= A_i; + DO <= DO_Reg; + +-- process (RESET_n, CLK_n) +-- begin +-- if RESET_n = '0' then +-- Reset_s <= '0'; +-- elsif CLK_n'event and CLK_n = '1' then +-- Reset_s <= '1'; +-- end if; +-- end process; + -- T80 reset input has already proper characteristics: + -- * asynchronous assertion + -- * deassertion synchronous to CLK_n (main_clk) + Reset_s <= RESET_n; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 1) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n_i, + HALT_n => HALT_n, + WAIT_n => Wait_s, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => Reset_s, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n_i, + CLK_n => CLK_n, + A => A_i, + DInst => DI, + DI => DI_Reg, + DO => DO_Reg, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (CLK_n) + begin + if CLK_n'event and CLK_n = '0' then + if CEN = '1' then + Wait_s <= WAIT_n; + if TState = "011" and BUSAK_n_i = '1' then + DI_Reg <= to_x01(DI); + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + WR_n_i <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + WR_n_i <= '1'; + if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! + WR_n_i <= not Write; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + Req_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + Req_Inhibit <= '1'; + else + Req_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process (Reset_s,CLK_n) + begin + if Reset_s = '0' then + MReq_Inhibit <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + if MCycle = "001" and TState = "010" then + MReq_Inhibit <= '1'; + else + MReq_Inhibit <= '0'; + end if; + end if; + end if; + end process; + + process(Reset_s,CLK_n) + begin + if Reset_s = '0' then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + elsif CLK_n'event and CLK_n = '0' then + if CEN = '1' then + + if MCycle = "001" then + if TState = "001" then + RD <= IntCycle_n; + MREQ <= IntCycle_n; + IORQ_n_i <= IntCycle_n; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '1'; + end if; + if TState = "100" then + MREQ <= '0'; + end if; + else + if TState = "001" and NoRead = '0' then + RD <= not Write; + IORQ_n_i <= not IORQ; + MREQ <= not IORQ; + end if; + if TState = "011" then + RD <= '0'; + IORQ_n_i <= '1'; + MREQ <= '0'; + end if; + end if; + + end if; + end if; + end process; + +end; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/dac.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/dac.vhd new file mode 100644 index 00000000..c21b306b --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 7 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/dpram.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/hq2x.sv b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/keyboard.v b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd new file mode 100644 index 00000000..a1a186fe --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug.vhd @@ -0,0 +1,243 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- Toplevel port for Papilio Plus board. +-- +------------------------------------------------------------------------------- +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library ieee; + use ieee.numeric_std.all; + +use work.ladybug_dip_pack.all; + +entity ladybugt is +port ( + -- Global Interface ------------------------------------------------------- + CLK_IN : in std_logic; -- 20MHz + I_RESET : in std_logic; + + -- VGA Interface ---------------------------------------------------------- + O_VIDEO_R : out std_logic_vector( 1 downto 0); + O_VIDEO_G : out std_logic_vector( 1 downto 0); + O_VIDEO_B : out std_logic_vector( 1 downto 0); + O_VSYNC : out std_logic; + O_HSYNC : out std_logic; + O_VBLANK : out std_logic; + O_HBLANK : out std_logic; + O_PIXCE : out std_logic; + + -- Audio Interface -------------------------------------------------------- + O_AUDIO : out signed(7 downto 0); + + but_coin_s : in std_logic_vector( 1 downto 0); + but_fire_s : in std_logic_vector( 1 downto 0); + but_bomb_s : in std_logic_vector( 1 downto 0); + but_tilt_s : in std_logic_vector( 1 downto 0); + but_select_s : in std_logic_vector( 1 downto 0); + but_up_s : in std_logic_vector( 1 downto 0); + but_down_s : in std_logic_vector( 1 downto 0); + but_left_s : in std_logic_vector( 1 downto 0); + but_right_s : in std_logic_vector( 1 downto 0) +); +end ladybugt; + +architecture struct of ladybugt is + + signal + ps2_codeready, + clk_20mhz_s, + clk_en_5mhz_s, + ext_res_n_s, + ext_res_s, + audio_s, + vid_hsync, + vid_vsync, + vga_hsync, + vid_comp_sync_n, + vga_vsync : std_logic; + + signal rom_cpu_a_s : std_logic_vector(14 downto 0); + signal rom_cpu_d_s : std_logic_vector( 7 downto 0); + signal rom_cpu_d1 : std_logic_vector( 7 downto 0); + signal rom_cpu_d2 : std_logic_vector( 7 downto 0); + signal rom_cpu_d3 : std_logic_vector( 7 downto 0); + signal rom_cpu_d4 : std_logic_vector( 7 downto 0); + signal rom_cpu_d5 : std_logic_vector( 7 downto 0); + signal rom_cpu_d6 : std_logic_vector( 7 downto 0); + + signal rom_char_a_s : std_logic_vector(11 downto 0); + signal rom_char_d_s : std_logic_vector(15 downto 0); + + signal rom_sprite_a_s : std_logic_vector(11 downto 0); + signal rom_sprite_d_s : std_logic_vector(15 downto 0); + + signal + dac_audio_s, + dip_block_1_s, + dip_block_2_s : std_logic_vector( 7 downto 0) := (others => '0'); + + signal ps2_scancode : std_logic_vector( 9 downto 0) := (others => '0'); + + signal + vid_rgb, + vga_rgb : std_logic_vector(15 downto 0) := (others => '0'); + + signal but_chute_s : std_logic_vector( 1 downto 0) := (others=>'0'); + +begin + + O_PIXCE <= clk_en_5mhz_s; + + but_chute_s <= not but_coin_s(1) & not but_coin_s(0); + + ----------------------------------------------------------------------------- + -- inputs assignments + ----------------------------------------------------------------------------- + ext_res_s <= I_RESET; + ext_res_n_s <= not ext_res_s; + clk_20mhz_s <= CLK_IN; + + ----------------------------------------------------------------------------- + -- Ladybug Machine + ----------------------------------------------------------------------------- + machine_b : entity work.ladybug_machine + port map ( + ext_res_n_i => ext_res_n_s, + clk_20mhz_i => clk_20mhz_s, + clk_en_5mhz_o => clk_en_5mhz_s, + tilt_n_i => but_tilt_s(0), + player_select_n_i => but_select_s, + player_fire_n_i => but_fire_s, + player_up_n_i => but_up_s, + player_right_n_i => but_right_s, + player_down_n_i => but_down_s, + player_left_n_i => but_left_s, + player_bomb_n_i => but_bomb_s, + right_chute_i => but_chute_s(0), + left_chute_i => but_chute_s(1), + dip_block_1_i => dip_block_1_s, + dip_block_2_i => dip_block_2_s, + rgb_r_o => O_VIDEO_R, + rgb_g_o => O_VIDEO_G, + rgb_b_o => O_VIDEO_B, + hsync_n_o => O_HSYNC, + vsync_n_o => O_VSYNC, + vblank_o => O_VBLANK, + hblank_o => O_HBLANK, + audio_o => O_AUDIO, + rom_cpu_a_o => rom_cpu_a_s, + rom_cpu_d_i => rom_cpu_d_s, + rom_char_a_o => rom_char_a_s, + rom_char_d_i => rom_char_d_s, + rom_sprite_a_o => rom_sprite_a_s, + rom_sprite_d_i => rom_sprite_d_s + ); + + ----------------------------------------------------------------------------- + -- Building the DIP Switches - see file ladybug_dip_pack.vhd + ----------------------------------------------------------------------------- +-- dip_block_1_s <= lb_dip_block_1_c; -- Lady Bug +-- dip_block_1_s <= do_dip_block_1_c; -- Dorodon + dip_block_1_s <= ca_dip_block_1_c; -- Cosmic Avenger + dip_block_2_s <= price_dip_block_2_c; -- Common for all games (coins per game pricing) + + ----------------------------------------------------------------------------- + -- Game ROMs + ----------------------------------------------------------------------------- + inst_rom_spritel : entity work.rom_sprite_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s( 7 downto 0) + ); + + inst_rom_spriteu : entity work.rom_sprite_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_sprite_a_s, + DATA => rom_sprite_d_s(15 downto 8) + ); + + inst_rom_charl : entity work.rom_char_l + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s( 7 downto 0) + ); + + inst_rom_charu : entity work.rom_char_u + port map ( + CLK => clk_20mhz_s, + ADDR => rom_char_a_s, + DATA => rom_char_d_s(15 downto 8) + ); + + inst_rom_cpu1 : entity work.rom_cpu1 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d1 + ); + + inst_rom_cpu2 : entity work.rom_cpu2 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d2 + ); + + inst_rom_cpu3 : entity work.rom_cpu3 + port map ( + CLK => clk_20mhz_s, + ADDR => rom_cpu_a_s(12 downto 0), + DATA => rom_cpu_d3 + ); + + ----------------------------------------------------------------------------- + -- Program ROMs data mux + ----------------------------------------------------------------------------- + rom_cpu_d_s <= + rom_cpu_d1 when rom_cpu_a_s(14 downto 13) = "00" else + rom_cpu_d2 when rom_cpu_a_s(14 downto 13) = "01" else + rom_cpu_d3 when rom_cpu_a_s(14 downto 13) = "10" else + (others=>'0'); + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_addr_dec.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_addr_dec.vhd new file mode 100644 index 00000000..6d857f6c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_addr_dec.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_addr_dec.vhd,v 1.10 2005/12/10 14:51:46 arnim Exp $ +-- +-- Address decoder of the CPU Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_addr_dec is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + a_i : in std_logic_vector(15 downto 12); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + mreq_n_i : in std_logic; + rfsh_n_i : in std_logic; + cs_n_o : out std_logic_vector(15 downto 0); + ram_cpu_cs_n_o : out std_logic + ); + +end ladybug_addr_dec; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_addr_dec is + +begin + + ----------------------------------------------------------------------------- + -- Process adec + -- + -- Purpose: + -- Decode the CPU address and generate one-hot chip select signals. + -- Each chip select enables a 4 KByte address segment. + -- + -- The chip select outputs are registered with the 20 MHz clock to + -- break potentially long combinational paths here. + -- + adec: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + cs_n_o <= (others => '1'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- default assignment + cs_n_o <= (others => '1'); + + if a_i(15) = '0' then + if rd_n_i = '0' or wr_n_i = '0' then + cs_n_o(to_integer(unsigned( '0' & a_i(14 downto 12) ))) <= '0'; + end if; + + else + if mreq_n_i = '0' and rfsh_n_i = '1' then + cs_n_o(to_integer(unsigned( '1' & a_i(14 downto 12) ))) <= '0'; + end if; + + end if; + + end if; + end process adec; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cs_ext_ram + -- + -- Purpose: + -- Builds the combinational chip select signal for the external CPU RAM. + -- + cs_ext_ram: process (a_i, + rd_n_i, wr_n_i) + begin + if (rd_n_i = '0' or wr_n_i = '0') and + a_i(15 downto 12) = "0110" then + ram_cpu_cs_n_o <= '0'; + else + ram_cpu_cs_n_o <= '1'; + end if; + end process cs_ext_ram; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_char.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_char.vhd new file mode 100644 index 00000000..1ca149f3 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_char.vhd @@ -0,0 +1,740 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char.vhd,v 1.18 2005/10/10 22:02:14 arnim Exp $ +-- +-- Character Video Module of Lady Bug Machine. +-- +-- This unit contains most of the logic found on schematic page three. +-- Excluded parts are: +-- * the 10 MHz and 5 MHz clock generation +-- moved into separate module on toplevel of Lady Bug machine +-- * the video timing circuitry +-- moved into separate module on toplevel of video unit +-- * the video MUX and RGB conversion unit +-- moved into separate module at toplevel of video unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity ladybug_char is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_char_o : out std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + ha_t_rise_i : in std_logic; + hx_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + hbl_i : in std_logic; + blank_flont_i : in std_logic; + blank_o : out std_logic; + crg_o : out std_logic_vector( 5 downto 1); + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_char; + +architecture rtl of ladybug_char is + + signal flip_screen_q : std_logic; + + signal h0_s, + h1_s, + h2_s : std_logic; + signal h_flip_s, + h_t_flip_s : std_logic_vector(3 downto 0); + signal v_flip_s, + v_t_flip_s : std_logic_vector(3 downto 0); + + signal h_ctrl_d_s, + h_ctrl_s, + h_ctrl_n_s, + h_ctrl_d_out_s, + h_ctrl_d_n_out_s, + h_ctrl_rise_s, + h_ctrl_n_rise_s : std_logic_vector(4 downto 1); + + signal hx_ctrl_q, + hx_ctrl_s, + hx_ctrl_n_rise_s : std_logic; + signal hx_ctrl_clear_q : std_logic; + + signal b1_ff_q, + b1_ff_s, + b1_ff_n_rise_s : std_logic; + + signal wait_q : std_logic; + signal wait_clear_q : std_logic; + + signal cgs_q, + cgs_s, + cgs_rise_s : std_logic; + + signal ram_addr_s : std_logic_vector(9 downto 0); + signal select_a_s : std_logic; + + signal char_ram_cs_n_s, + char_ram_we_n_s : std_logic; + signal col_ram_cs_n_s, + col_ram_we_n_s : std_logic; + signal d_from_char_ram_s : std_logic_vector(7 downto 0); + signal d_from_col_ram_s : std_logic_vector(3 downto 0); + + signal s_q : std_logic_vector( 7 downto 0); + signal d_char_ram_q : std_logic_vector( 7 downto 0); + signal d_col_ram_q : std_logic_vector( 3 downto 0); + + signal d_char_rom_q : std_logic_vector(15 downto 0); + signal crg1_s, + crg2_s, + crg3_q, + crg4_q, + crg5_q : std_logic; + + signal hbl_q,hbl_d : std_logic; + + signal hcnt : integer; + signal vdd_s : std_logic; + +begin + + vdd_s <= '1'; + + ----------------------------------------------------------------------------- + -- Process flip + -- + -- Purpose: + -- Implement the flip_screen flag. + -- + flip: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + -- Actually, this asynchronous reset of the ls259 is not 100% + -- equivalent to the real behavior of this circuit. However, + -- the flip_screen latch is modelled like this for the sake of + -- simplicity. It's sufficient for the purpose here. + flip_screen_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if a_i(2 downto 0) = "000" and cs10_n_i = '0' then + flip_screen_q <= d_from_cpu_i(0); + end if; + + end if; + end process flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process h_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + h_flip: process (flip_screen_q, + h_i, h_t_i, + s_q) + variable a_v, b_v, + sum_v : unsigned(8 downto 0); + begin + -- calculate sum + a_v := '0' & unsigned(s_q); + b_v := '0' & unsigned(h_t_i) & unsigned(h_i); + sum_v := a_v + b_v; + + -- h0,1,2 are taken from directly from sum + h0_s <= sum_v(0); + h1_s <= sum_v(1); + h2_s <= sum_v(2); + + -- now flip + for idx in 3 downto 0 loop + h_flip_s(idx) <= flip_screen_q xor sum_v(idx); + h_t_flip_s(idx) <= flip_screen_q xor sum_v(idx + 4); + end loop; + end process h_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process v_flip + -- + -- Purpose: + -- Build the flipped horizontal timing signals. + -- + v_flip: process (flip_screen_q, + v_i, v_t_i) + begin + for idx in 3 downto 0 loop + v_flip_s(idx) <= flip_screen_q xor v_i(idx); + v_t_flip_s(idx) <= flip_screen_q xor v_t_i(idx); + end loop; + end process v_flip; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The Horizontal Control Signals + -- Detailed purpose/meaning is unknown. + ----------------------------------------------------------------------------- + h_ctrl_d_s(1) <= not (not h2_s and (h1_s xor h0_s)); + h_ctrl_d_s(2) <= hx_i; + h_ctrl_d_s(3) <= not ((h1_s xor h0_s) or (not h2_s xor h1_s)); + h_ctrl_d_s(4) <= '0'; + h_ctrl_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + por_n_i => por_n_i, + cl_n_i => vdd_s, + d_i => h_ctrl_d_s, + q_o => h_ctrl_s, + q_n_o => h_ctrl_n_s, + d_o => h_ctrl_d_out_s, + d_n_o => h_ctrl_d_n_out_s + ); + h_ctrl_rise_s <= not h_ctrl_s and h_ctrl_d_out_s; + h_ctrl_n_rise_s <= h_ctrl_s and not h_ctrl_d_n_out_s; + + + ----------------------------------------------------------------------------- + -- Process ctrl_seq + -- + -- Purpose: + -- Implemente the various sequential elements for horizontal control. + -- + ctrl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_ctrl_q <= '0'; + hx_ctrl_clear_q <= '0'; + b1_ff_q <= '0'; + wait_q <= '0'; + wait_clear_q <= '0'; + cgs_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- the HX control flip-flop + hx_ctrl_q <= hx_ctrl_s; + + -- the clear counterpart of hx_ctrl_q + if h_ctrl_s(2) = '0' then + -- pseudo-asynchronous clear + hx_ctrl_clear_q <= '0'; + elsif hx_ctrl_n_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + hx_ctrl_clear_q <= '1'; + end if; + + -- the mysterious B1 flip-flop + b1_ff_q <= b1_ff_s; + + -- the CGS rising edge indicator support flip-flops + cgs_q <= cgs_s; + + -- the WAIT flip-flop + if wait_clear_q = '1' then + -- pseudo-asynchronous clear + wait_q <= '0'; + elsif cgs_rise_s = '1' then + -- rising edge indicator acts as clock enable instead of clock + wait_q <= '1'; + end if; + + -- the clear counterpart of wait_q + if clk_en_4mhz_i = '1' then + wait_clear_q <= wait_q and (h_ctrl_s(3) and (b1_ff_q or hx_ctrl_q)); + end if; + + end if; + end process ctrl_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ctrl_comp + -- + -- Purpose: + -- Implements the combination logic for the horizontal control + -- elements. + -- + ctrl_comp: process (h_ctrl_rise_s, + hx_i, hx_ctrl_q, + hx_ctrl_clear_q, + h_ctrl_n_rise_s, + b1_ff_q, + cgs_q, cs13_n_i) + begin + -- default assignments + hx_ctrl_s <= hx_ctrl_q; + hx_ctrl_n_rise_s <= '0'; + b1_ff_s <= b1_ff_q; + b1_ff_n_rise_s <= '0'; + cgs_s <= cgs_q; + cgs_rise_s <= '0'; + + -- the HX control flip-flop ----------------------------------------------- + if hx_ctrl_clear_q = '1' then + -- pseudo-asynchronous clear + hx_ctrl_s <= '0'; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + elsif h_ctrl_rise_s(1) = '1' then + -- rising edge indicator acts as clock enable instead of clock + if hx_i = '1' then + -- toggle FF + hx_ctrl_s <= not hx_ctrl_q; + + if (not hx_ctrl_q) = '0' then + -- detct rising edge of inverted ouput + hx_ctrl_n_rise_s <= '1'; + end if; + end if; + end if; + + -- the mysterious B1 flip-flop -------------------------------------------- + if hx_ctrl_q = '1' then + -- pseudo-asynchronous clear + b1_ff_s <= '0'; + + if (not b1_ff_q) = '0' then + -- detct rising edge of inverted ouput + b1_ff_n_rise_s <= '1'; + end if; + elsif h_ctrl_n_rise_s(3) = '1' then + -- rising edge indicator acts as clock enable instead of clock + b1_ff_s <= '1'; + end if; + + -- the CGS rising edge indicator support flip-flop ------------------------ + cgs_s <= not cs13_n_i; + cgs_rise_s <= not cgs_q and not cs13_n_i; + + end process ctrl_comp; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_addr + -- + -- Purpose: + -- Multiplexes the CPU address bus and the h+v timing control signals to + -- form the RAM address bus. + -- + ram_addr: process (h_flip_s, h_t_flip_s, + v_flip_s, v_t_flip_s, + a_i, + h_ctrl_s, h_ctrl_n_s, + hx_ctrl_q, + b1_ff_q) + variable a_v, b_v, g_n_v : std_logic; + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + ram_addr_s <= (others => '0'); + + -- logic that drives A input of IC L4 and K4 + a_v := not (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + -- logic that drives B input of IC L4 and K4 + b_v := hx_ctrl_q; + -- logic that drives /G input of IC J4 + g_n_v := hx_ctrl_q and (h_ctrl_n_s(1) and (b1_ff_q or hx_ctrl_q)); + + -- IC L4 and K4: Dual 4:1 Multiplexer ------------------------------------- + vec_v := b_v & a_v; + case vec_v is + when "00" => + ram_addr_s(0) <= h_flip_s (3); + ram_addr_s(1) <= h_t_flip_s(0); + -- + ram_addr_s(2) <= h_t_flip_s(1); + ram_addr_s(3) <= h_t_flip_s(2); + when "01" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when "10" => + ram_addr_s(0) <= v_t_flip_s(1); + ram_addr_s(1) <= v_t_flip_s(2); + -- + ram_addr_s(2) <= v_t_flip_s(3); + ram_addr_s(3) <= '0'; + when "11" => + ram_addr_s(0) <= a_i (0); + ram_addr_s(1) <= a_i (1); + -- + ram_addr_s(2) <= a_i (2); + ram_addr_s(3) <= a_i (3); + when others => + null; + end case; + + -- IC J4 and H4: Quad 2:1 Multiplexer ------------------------------------- + case a_v is + when '0' => + ram_addr_s(4) <= h_t_flip_s(3) and not g_n_v; + ram_addr_s(7) <= v_t_flip_s(1) and not g_n_v; + ram_addr_s(8) <= v_t_flip_s(2) and not g_n_v; + ram_addr_s(9) <= v_t_flip_s(3) and not g_n_v; + -- + ram_addr_s(5) <= v_flip_s (3); + ram_addr_s(6) <= v_t_flip_s(0); + when '1' => + ram_addr_s(4) <= a_i (4) and not g_n_v; + ram_addr_s(7) <= a_i (7) and not g_n_v; + ram_addr_s(8) <= a_i (8) and not g_n_v; + ram_addr_s(9) <= a_i (9) and not g_n_v; + -- + ram_addr_s(5) <= a_i (5); + ram_addr_s(6) <= a_i (6); + when others => + null; + end case; + + select_a_s <= a_v; + + end process ram_addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ram_ctrl + -- + -- Purpose: + -- Generate the control signals for the character and color RAMs. + -- This comprises: + -- * reading RAMs while the beam sweeps the screen + -- * reading RAMs to the CPU + -- * writing RAMs from the CPU + -- + ram_ctrl: process (cs13_n_i, + wait_q, + select_a_s, + a_i, + wr_n_i, rd_n_i, + d_from_char_ram_s, d_from_col_ram_s, + clk_en_4mhz_i) + variable cpu_read_char_ram_v : boolean; + variable cpu_write_char_ram_v : boolean; + variable cpu_read_col_ram_v : boolean; + variable cpu_write_col_ram_v : boolean; + variable vec_v : std_logic_vector(2 downto 0); + begin + -- default assignments + char_ram_cs_n_s <= '1'; + char_ram_we_n_s <= '1'; + col_ram_cs_n_s <= '1'; + col_ram_we_n_s <= '1'; + d_from_char_o <= (others => '1'); + cpu_read_char_ram_v := false; + cpu_write_char_ram_v := false; + cpu_read_col_ram_v := false; + cpu_write_col_ram_v := false; + + -- detect and decode CPU access + if clk_en_4mhz_i = '1' and -- operate RAMs with CPU clock + (not cs13_n_i and select_a_s and not wait_q) = '1' then + vec_v := a_i(10) & rd_n_i & wr_n_i; + case vec_v is + when "001" => + cpu_read_char_ram_v := true; + when "010" => + cpu_write_char_ram_v := true; + when "101" => + cpu_read_col_ram_v := true; + when "110" => + cpu_write_col_ram_v := true; + when others => + null; + end case; + end if; + + -- now we are prepared to generate the /CS and /WE signals for the RAMs + if select_a_s = '0' or + cpu_read_char_ram_v or cpu_write_char_ram_v then + char_ram_cs_n_s <= '0'; + end if; + if select_a_s = '0' or + cpu_read_col_ram_v or cpu_write_col_ram_v then + col_ram_cs_n_s <= '0'; + end if; + if cpu_write_char_ram_v then + char_ram_we_n_s <= '0'; + end if; + if cpu_write_col_ram_v then + col_ram_we_n_s <= '0'; + end if; + + -- and we can multiplex the data bus towards the CPU + if cpu_read_char_ram_v then + d_from_char_o <= d_from_char_ram_s; + elsif cpu_read_col_ram_v then + d_from_char_o(3 downto 0) <= d_from_col_ram_s; + end if; + + end process ram_ctrl; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The character RAM + ----------------------------------------------------------------------------- + char_ram_b : entity work.ladybug_char_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => char_ram_cs_n_s, + we_n_i => char_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => d_from_char_ram_s + ); + ----------------------------------------------------------------------------- + -- The color RAM + ----------------------------------------------------------------------------- + col_ram_b : entity work.ladybug_char_col_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => ram_addr_s, + cs_n_i => col_ram_cs_n_s, + we_n_i => col_ram_we_n_s, + d_i => d_from_cpu_i(3 downto 0), + d_o => d_from_col_ram_s + ); + + + ----------------------------------------------------------------------------- + -- Process ram_d_seq + -- + -- Purpose: + -- Implements three latch banks that save the output of the character + -- and color RAMs. + -- + ram_d_seq: process (clk_20mhz_i, por_n_i) + variable complex_rising_edge_v : boolean; + begin + if por_n_i = '0' then + s_q <= (others => '0'); + d_char_ram_q <= (others => '0'); + d_col_ram_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- latch data from the character RAM to form input for h_flip ----------- + if hx_ctrl_n_rise_s = '1' then + s_q <= d_from_char_ram_s; + end if; + + -- latch data from the character RAM for ROM address generation --------- + -- there are three sources for a rising edge: + -- 1) falling edge of h_ctrl_n_s(1) + -- => equivalen to rising edge of h_ctrl_s(1) + -- 2) rising edge of hx_ctrl_n_q + -- 3) rising edge of b1_ff_n + -- For each source, the two have to be in a defined state to let + -- the edge propage to the latches. + complex_rising_edge_v := ((h_ctrl_rise_s(1) and + (b1_ff_q or hx_ctrl_q)) or + (hx_ctrl_n_rise_s and + (not b1_ff_q and not h_ctrl_n_s(1))) or + (b1_ff_n_rise_s and + (not hx_ctrl_q and not h_ctrl_s(1)))) = '1'; + if complex_rising_edge_v then + d_char_ram_q <= d_from_char_ram_s; + d_col_ram_q <= d_from_col_ram_s; + end if; + + end if; + end process ram_d_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process latch_rom_d + -- + -- Purpose: + -- Latch the output of the character ROM. + -- + latch_rom_d: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + d_char_rom_q <= (others => '0'); + crg3_q <= '0'; + crg4_q <= '0'; + crg5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if (clk_en_5mhz_i and + h2_s and h1_s and h0_s) = '1' then + d_char_rom_q <= rom_char_d_i; + crg3_q <= d_col_ram_q(0); + crg4_q <= d_col_ram_q(1); + crg5_q <= d_col_ram_q(2); + end if; + + end if; + end process latch_rom_d; + -- + ----------------------------------------------------------------------------- + -- Process hbl_seq + -- + -- Purpose: + -- Implements the flip-flop that latches HBL. + -- + hbl_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hbl_q <= '0'; + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + if hcnt /= 255 then + hcnt <= hcnt + 1; + end if; + end if; + if ha_t_rise_i = '1' then + hbl_q <= hbl_i; + if hbl_q = '1' and hbl_i = '0' then + hcnt <= 0; + end if; + end if; + end if; + end process hbl_seq; + -- + ----------------------------------------------------------------------------- + + process (clk_20mhz_i) + begin + if rising_edge(clk_20mhz_i) then + if clk_en_5mhz_i = '1' then + hbl_d <= hbl_q; + + if hcnt < 240 then + hblank_o <= '0'; + else + hblank_o <= '1'; + end if; + + if hbl_d = '0' and hbl_q = '1' then + vblank_o <= not blank_flont_i; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process crg_mux + -- + -- Purpose: + -- Multiplexes the latched character ROM data to CRG1 and CRG2. + -- + crg_mux: process (d_char_rom_q, + h_flip_s, + blank_flont_i, + hbl_q) + variable blank_v : std_logic; + variable idx_v : unsigned(2 downto 0); + begin + blank_v := not (blank_flont_i and not hbl_q); + idx_v := unsigned(h_flip_s(2 downto 0)); + + if blank_v = '0' then + crg1_s <= d_char_rom_q(to_integer('0' & idx_v)); + crg2_s <= d_char_rom_q(to_integer('1' & idx_v)); + else + crg1_s <= '0'; + crg2_s <= '0'; + end if; + + blank_o <= blank_v; + end process crg_mux; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + wait_n_o <= not wait_q; + crg_o(5) <= crg5_q; + crg_o(4) <= crg4_q; + crg_o(3) <= crg3_q; + crg_o(2) <= crg2_s; + crg_o(1) <= crg1_s; + rom_char_a_o( 2 downto 0) <= v_flip_s(2 downto 0); + rom_char_a_o(10 downto 3) <= d_char_ram_q; + rom_char_a_o(11) <= d_col_ram_q(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_chute.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_chute.vhd new file mode 100644 index 00000000..b3255fe0 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_chute.vhd @@ -0,0 +1,130 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chute.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaper for a chute input. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chute is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + chute_i : in std_logic; + chute_o : out std_logic + ); + +end ladybug_chute; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_chute is + + -- 2.35e-2 s = 1 / 20,000,000 Hz * 470000 + constant chute_delay_c : natural := 470000; + + signal chute_cnt_q : unsigned(18 downto 0); + + signal chute_sync_q : std_logic_vector(1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process sync + -- + -- Purpose: + -- Synchronize the asynchronous chute input. + -- + sync: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_sync_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + chute_sync_q(0) <= chute_i; + chute_sync_q(1) <= chute_sync_q(0); + + end if; + end process sync; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cnt + -- + -- Purpose: + -- Count the required number of 20 MHz clock cycles before emitting + -- chute event. This is a low pass filter for the rising edge of chute_i. + -- + cnt: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if chute_sync_q(1) = '1' then + if chute_cnt_q = chute_delay_c then + chute_o <= '1'; + else + chute_cnt_q <= chute_cnt_q + 1; + end if; + + else + -- reset counter when chute input goes back to 0 + chute_cnt_q <= (others => '0'); + chute_o <= '0'; + + end if; + + end if; + end process cnt; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_chutes.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_chutes.vhd new file mode 100644 index 00000000..7584de89 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_chutes.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_chutes.vhd,v 1.4 2005/10/10 21:21:20 arnim Exp $ +-- +-- Pulse shaping for the two chute inputs. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_chutes is + + port ( + clk_20mhz_i : in std_logic; + res_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + cs8_n_i : in std_logic; + nmi_n_o : out std_logic; + int_n_o : out std_logic + ); + +end ladybug_chutes; + +architecture rtl of ladybug_chutes is + + signal right_chute_s, + left_chute_s : std_logic; + signal left_chute_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Pulse shaper for Right Chute + ----------------------------------------------------------------------------- + right_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => right_chute_i, + chute_o => right_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Pulse shaper for Left Chute + ----------------------------------------------------------------------------- + left_chute_b : entity work.ladybug_chute + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + chute_i => left_chute_i, + chute_o => left_chute_s + ); + + + ----------------------------------------------------------------------------- + -- Process left_edge + -- + -- Purpose: + -- Implement the edge detector for the left chute. + -- Only a rising edge of the filtered chute input can trigger a new + -- interrupt to the CPU. + -- + left_edge: process (clk_20mhz_i, res_n_i) + begin + if res_n_i = '0' then + left_chute_q <= '0'; + int_n_o <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + left_chute_q <= left_chute_s; + + if cs8_n_i = '0' then + -- synchronous set, has priority over data path + int_n_o <= '1'; + + -- edge detector + elsif left_chute_s = '1' and left_chute_q = '0' then + int_n_o <= '0'; + + end if; + + end if; + end process left_edge; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + nmi_n_o <= not right_chute_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_clk.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_clk.vhd new file mode 100644 index 00000000..d3e00484 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_clk.vhd @@ -0,0 +1,158 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_clk.vhd,v 1.5 2005/10/28 21:17:41 arnim Exp $ +-- +-- Clock generator for the Lady Bug machine. +-- +-- This module generates the clock enables which are required to mimic the +-- different clocks of the Lady Bug boards. +-- +-- Theory of Operation: +-- A PLL is used to tune the external clock to 20 MHz. This forms the +-- main clock which is used by all sequential elements. +-- All derived clocks are built with clock enables to allow a synchronous +-- design style (sort of). +-- +-- Note: +-- The counters and enable signals are reset by the power-on reset. +-- Thus, the "derived clocks" run during normal system reset. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_clk is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_10mhz_n_o : out std_logic; + clk_en_5mhz_o : out std_logic; + clk_en_5mhz_n_o : out std_logic; + clk_en_4mhz_o : out std_logic + ); + +end ladybug_clk; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_clk is + + -- counter for 5 MHz and 10 MHz clock enables + signal clk_cnt_5mhz_q : unsigned(1 downto 0); + -- counter for 4 MHz clock enable + signal clk_cnt_4mhz_q : unsigned(2 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process clk_en + -- + -- Purpose: + -- Generates the clock enables for 10 MHz, 5 MHz, 4 MHz. + -- + clk_en: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_cnt_5mhz_q <= (others => '0'); + clk_cnt_4mhz_q <= (others => '0'); + clk_en_10mhz_o <= '0'; + clk_en_10mhz_n_o <= '0'; + clk_en_5mhz_o <= '0'; + clk_en_5mhz_n_o <= '0'; + clk_en_4mhz_o <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + + ------------------------------------------------------------------------- + -- 10 MHz / 5 MHz clock domain + -- + -- counter for 10 MHz and 5 MHz clock enables + clk_cnt_5mhz_q <= clk_cnt_5mhz_q + 1; + + -- generate clock enable for 10 MHz + -- enable on every second clock of clk_20mhz_i + clk_en_10mhz_o <= clk_cnt_5mhz_q(0); + -- enable with 180 deg phase shift + clk_en_10mhz_n_o <= not clk_cnt_5mhz_q(0); + + -- generate clock enables for 5 MHz: + -- enable on every forth clock of clk_20mhz_i + if clk_cnt_5mhz_q = "11" then + clk_en_5mhz_o <= '1'; + else + clk_en_5mhz_o <= '0'; + end if; + -- enable with 180 deg phase shift + if clk_cnt_5mhz_q = "01" then + clk_en_5mhz_n_o <= '1'; + else + clk_en_5mhz_n_o <= '0'; + end if; + -- + ------------------------------------------------------------------------- + + + ------------------------------------------------------------------------- + -- 4 MHz domain + -- + -- counter for 4 MHz clock enable, wrap around after 5 clocks + clk_en_4mhz_o <= clk_cnt_4mhz_q(2); + + if clk_cnt_4mhz_q = "100" then + clk_cnt_4mhz_q <= (others => '0'); + else + clk_cnt_4mhz_q <= clk_cnt_4mhz_q + 1; + end if; + -- + ------------------------------------------------------------------------- + + end if; + end process clk_en; + -- + ----------------------------------------------------------------------------- + + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_counter.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_counter.vhd new file mode 100644 index 00000000..d07256bb --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_counter.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------- +-- +-- Synchronous 8-Bit Binary Counter with preset. +-- +-- $Id: ladybug_counter.vhd,v 1.9 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity counter is +port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + reset_n_i : in std_logic; + load_i : in std_logic; + preset_i : in std_logic_vector(7 downto 0); + q_o : out std_logic_vector(7 downto 0); + rise_q_o : out std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0); + co_o : out std_logic +); +end counter; + +architecture rtl of counter is + signal cnt_q : std_logic_vector(7 downto 0); + signal cnt_s : std_logic_vector(7 downto 0); +begin + + seq: process (ck_i, reset_n_i) + begin + if reset_n_i = '0' then + cnt_q <= (others => '0'); + elsif rising_edge(ck_i) then + cnt_q <= cnt_s; + end if; + end process seq; + + adder: process (ck_en_i, cnt_q, load_i, preset_i) + begin + cnt_s <= cnt_q; + + if ck_en_i = '1' then + if load_i = '1' then + cnt_s <= preset_i; + else + cnt_s <= cnt_q + 1; + end if; + end if; + end process adder; + + co_o <= '1' when cnt_q = x"FF" else '0'; + rise_q_o <= cnt_s and not cnt_q; + q_o <= cnt_q; + d_o <= cnt_s; +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd new file mode 100644 index 00000000..7d41074f --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_cpu_unit.vhd @@ -0,0 +1,260 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_unit.vhd,v 1.19 2005/12/10 14:51:51 arnim Exp $ +-- +-- CPU Main Unit of the Lady Bug Machine. +-- +-- Actually, the PCB where the CPU resides on contains also the sound chips and +-- parts of the video controller. For the sake of simplicity, the CPU and chip +-- select logic has been moved into this separate unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_unit is + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + res_n_i : in std_logic; + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + sound_wait_n_i : in std_logic; + wait_n_i : in std_logic; + right_chute_i : in std_logic; + left_chute_i : in std_logic; + gpio_in0_i : in std_logic_vector( 7 downto 0); + gpio_in1_i : in std_logic_vector( 7 downto 0); + gpio_in2_i : in std_logic_vector( 7 downto 0); + gpio_in3_i : in std_logic_vector( 7 downto 0); + gpio_extra_i : in std_logic_vector( 7 downto 0); + a_o : out std_logic_vector(10 downto 0); + d_to_cpu_i : in std_logic_vector( 7 downto 0); + d_from_cpu_o : out std_logic_vector( 7 downto 0); + rd_n_o : out std_logic; + wr_n_o : out std_logic; + cs7_n_o : out std_logic; + cs10_n_o : out std_logic; + cs11_n_o : out std_logic; + cs12_n_o : out std_logic; + cs13_n_o : out std_logic + ); + +end ladybug_cpu_unit; + +architecture struct of ladybug_cpu_unit is + + signal t80_clk_en_s : std_logic; + + signal wait_n_s : std_logic; + signal int_n_s : std_logic; + signal nmi_n_s : std_logic; + signal mreq_n_s : std_logic; + signal rd_n_s : std_logic; + signal wr_n_s : std_logic; + signal rfsh_n_s : std_logic; + signal m1_n_s : std_logic; + signal a_s : std_logic_vector(15 downto 0); + signal d_to_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_cpu_s : std_logic_vector( 7 downto 0); + signal d_from_rom_s, + d_decrypted_s, + d_rom_mux_s : std_logic_vector( 7 downto 0); + signal d_from_ram_s : std_logic_vector( 7 downto 0); + signal d_from_gpio_s : std_logic_vector( 7 downto 0); + + signal cs_n_s : std_logic_vector(15 downto 0); + + signal ram_cpu_cs_n_s : std_logic; + + signal vcc_s : std_logic; + +begin + vcc_s <= '1'; + + wait_n_s <= sound_wait_n_i and wait_n_i; + + ----------------------------------------------------------------------------- + -- The T80 CPU + ----------------------------------------------------------------------------- + -- "wait" has to be modelled with the clock enable because the T80 is not + -- able to enlarge write accesses properly when they are delayed with "wait" + t80_clk_en_s <= clk_en_4mhz_i and wait_n_s; + T80a_b : entity work.T80a + generic map ( + Mode => 0 + ) + port map ( + RESET_n => res_n_i, + CLK_n => clk_20mhz_i, + CLK_EN_SYS => t80_clk_en_s, + WAIT_n => wait_n_s, + INT_n => int_n_s, + NMI_n => nmi_n_s, + BUSRQ_n => vcc_s, + M1_n => m1_n_s, + MREQ_n => mreq_n_s, + IORQ_n => open, + RD_n => rd_n_s, + WR_n => wr_n_s, + RFSH_n => rfsh_n_s, + HALT_n => open, + BUSAK_n => open, + A => a_s, + DI => d_to_cpu_s, + DO => d_from_cpu_s + ); + d_from_cpu_o <= d_from_cpu_s; + + + ----------------------------------------------------------------------------- + -- The CPU RAM + ----------------------------------------------------------------------------- + cpu_ram_b : entity work.ladybug_cpu_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_4mhz_i, + a_i => a_s(11 downto 0), + cs_n_i => cs_n_s(6), + we_n_i => wr_n_s, + d_i => d_from_cpu_s, + d_o => d_from_ram_s + ); + + ----------------------------------------------------------------------------- + -- The Address Decoder + ----------------------------------------------------------------------------- + addr_dec_b : entity work.ladybug_addr_dec + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + a_i => a_s(15 downto 12), + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + mreq_n_i => mreq_n_s, + rfsh_n_i => rfsh_n_s, + cs_n_o => cs_n_s, + ram_cpu_cs_n_o => ram_cpu_cs_n_s + ); + + + ----------------------------------------------------------------------------- + -- The General Purpose IO + ----------------------------------------------------------------------------- + gpio_b : entity work.ladybug_gpio + port map ( + a_i => a_s(1 downto 0), + cs_in_n_i => cs_n_s(9), + cs_extra_n_i => cs_n_s(14), + in0_i => gpio_in0_i, + in1_i => gpio_in1_i, + in2_i => gpio_in2_i, + in3_i => gpio_in3_i, + extra_i => gpio_extra_i, + d_o => d_from_gpio_s + ); + + + ----------------------------------------------------------------------------- + -- The Coin Chutes + ----------------------------------------------------------------------------- + coin_chutes_b : entity work.ladybug_chutes + port map ( + clk_20mhz_i => clk_20mhz_i, + res_n_i => res_n_i, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + cs8_n_i => cs_n_s(8), + nmi_n_o => nmi_n_s, + int_n_o => int_n_s + ); + + + ----------------------------------------------------------------------------- + -- Decrytion PROMs + ----------------------------------------------------------------------------- + + decrypt_prom : entity work.prom_decrypt + port map ( + CLK => clk_20mhz_i, + ADDR => rom_cpu_d_i, + DATA => d_decrypted_s + ); + + ----------------------------------------------------------------------------- + -- Only opcodes (i.e. instruction fetches) have to be decrypted + ----------------------------------------------------------------------------- + d_rom_mux_s <= d_decrypted_s when m1_n_s = '0' else rom_cpu_d_i; + + ----------------------------------------------------------------------------- + -- Gate Data Bus from ROM + -- The ROM puts data on the data bus within the CPU Main Unit so we do + -- gating here. + ----------------------------------------------------------------------------- + d_from_rom_s <= d_rom_mux_s + when cs_n_s(0) = '0' or cs_n_s(1) = '0' or cs_n_s(2) = '0' or + cs_n_s(3) = '0' or cs_n_s(4) = '0' or cs_n_s(5) = '0' else + (others => '1'); + + + ----------------------------------------------------------------------------- + -- Combine Data Buses + -- Uses an AND of all incoming buses from submodules. Each module has to + -- drive ones when not active so we can save logic complexity here. + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_to_cpu_i and d_from_rom_s and d_from_ram_s and d_from_gpio_s; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + a_o <= a_s(10 downto 0); + rom_cpu_a_o <= a_s(14 downto 0); + rd_n_o <= rd_n_s; + wr_n_o <= wr_n_s; + cs7_n_o <= cs_n_s(7); + cs10_n_o <= cs_n_s(10); + cs11_n_o <= cs_n_s(11); + cs12_n_o <= cs_n_s(12); + cs13_n_o <= cs_n_s(13); + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_dip_pack.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_dip_pack.vhd new file mode 100644 index 00000000..ebff8ec4 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_dip_pack.vhd @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------- +-- +-- $Id: ladybug_dip_pack-p.vhd,v 1.4 2005/10/10 20:52:04 arnim Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package ladybug_dip_pack is + + ----------------------------------------------------------------------------- + -- DIP switch settings for Lady Bug + ----------------------------------------------------------------------------- + constant lb_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- High Score Initials ---------------------------------------------------- + -- 0 = 3-Letter Initials + -- 1 = 10-Letter Initials + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + ----------------------------------------------------------------------------- + -- DIP switch settings for Dorodon + ----------------------------------------------------------------------------- + constant do_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives ------------------------------------------------------------------ + -- 0 = 5 Lives + -- 1 = 3 Lives + '0' & + -- Free Play -------------------------------------------------------------- + -- 0 = Free Play + -- 1 = No Free Play + '1' & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- Screen Freeze ---------------------------------------------------------- + -- 0 = Freeze + -- 1 = No Freeze + '1' & + -- Rack Test (Cheat) ------------------------------------------------------ + -- 0 = On + -- 1 = Off + '1' & + -- Bonus Life ------------------------------------------------------------- + -- 0 = 40000 + -- 1 = 20000 + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + + ----------------------------------------------------------------------------- + -- DIP switch settings for Cosmic Avenger + ----------------------------------------------------------------------------- + constant ca_dip_block_1_c : std_logic_vector(7 downto 0) := + -- Lives per Game --------------------------------------------------------- + -- 00 = 2 Lives + -- 11 = 3 Lives + -- 10 = 4 Lives + -- 01 = 5 Lives + "01" & + -- Initial High Score ----------------------------------------------------- + -- 00 = 0 + -- 11 = 5000 + -- 10 = 8000 + -- 01 = 10000 + "11" & + -- Cabinet ---------------------------------------------------------------- + -- 0 = Upright + -- 1 = Cocktail + '0' & + -- High Score Names ------------------------------------------------------- + -- 0 = 3 Letters + -- 1 = 10 Letters + '1' & + -- Difficulty ------------------------------------------------------------- + -- 11 = Easy + -- 10 = Medium + -- 01 = Hard + -- 00 = Hardest + "10"; + + constant price_dip_block_2_c : std_logic_vector(7 downto 0) := + -- Pricing Options -------------------------------------------------------- + -- 1111 = 1 coin 1 credit + -- 1110 = 1 coin 2 credits + -- 1101 = 1 coin 3 credits + -- 1100 = 1 coin 4 credits + -- 1011 = 1 coin 5 credits + -- 1010 = 2 coins 1 credit + -- 1001 = 2 coins 3 credits + -- 1000 = 3 coins 1 credit + -- 0111 = 3 coins 2 credit + -- 0110 = 4 coins 1 credit + -- 0101 = 1 coin 1 credit + -- 0100 = 1 coin 1 credit + -- 0011 = 1 coin 1 credit + -- 0010 = 1 coin 1 credit + -- 0001 = 1 coin 1 credit + -- 0000 = 1 coin 1 credit + -- + -- Left Chute + "1111" & + -- Right Chute + "1111"; + +end ladybug_dip_pack; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_gpio.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_gpio.vhd new file mode 100644 index 00000000..6ca21711 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_gpio.vhd @@ -0,0 +1,139 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_gpio.vhd,v 1.3 2005/10/10 21:21:20 arnim Exp $ +-- +-- General purpose IO input for CPU Main Unit. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_gpio is + + port ( + a_i : in std_logic_vector(1 downto 0); + cs_in_n_i : in std_logic; + cs_extra_n_i : in std_logic; + in0_i : in std_logic_vector(7 downto 0); + in1_i : in std_logic_vector(7 downto 0); + in2_i : in std_logic_vector(7 downto 0); + in3_i : in std_logic_vector(7 downto 0); + extra_i : in std_logic_vector(7 downto 0); + d_o : out std_logic_vector(7 downto 0) + ); + +end ladybug_gpio; + + +architecture rtl of ladybug_gpio is + +begin + + ----------------------------------------------------------------------------- + -- Process gpio + -- + -- Purpose: + -- Multiplex the IN and EXTRA inputs onto the data bus for CPU. + -- + gpio: process (a_i, + cs_in_n_i, + cs_extra_n_i, + in0_i, + in1_i, + in2_i, + in3_i, + extra_i) + variable cs_n_v : std_logic_vector(1 downto 0); + begin + -- default assignment with inactive bus value + d_o <= (others => '1'); + + cs_n_v := cs_extra_n_i & cs_in_n_i; + case cs_n_v is + -- IN ports and DIP switches selected ----------------------------------- + when "10" => + case a_i is + -- IN 0 addressed + when "00" => + d_o <= in0_i; + -- IN 1 addressed + when "01" => + d_o <= in1_i; + -- DIP 0 addressed + when "10" => + d_o <= in2_i; + -- DIP 1 addressed + when "11" => + d_o <= in3_i; + + when others => + null; + end case; + + -- Extra bank selected -------------------------------------------------- + when "01" => + case a_i is + when "00" => + d_o(1) <= extra_i(7); + d_o(0) <= extra_i(3); + when "01" => + d_o(1) <= extra_i(6); + d_o(0) <= extra_i(2); + when "10" => + d_o(1) <= extra_i(5); + d_o(0) <= extra_i(1); + when "11" => + d_o(1) <= extra_i(4); + d_o(0) <= extra_i(0); + when others => + null; + end case; + + when others => + null; + end case; + + end process gpio; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd new file mode 100644 index 00000000..584b8391 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_machine.vhd @@ -0,0 +1,295 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_machine.vhd,v 1.23 2006/02/07 00:44:21 arnim Exp $ +-- +-- Toplevel of the Lady Bug machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_machine is + port ( + -- Clock and Reset Interface ---------------------------------------------- + ext_res_n_i : in std_logic; + clk_20mhz_i : in std_logic; + clk_en_10mhz_o : out std_logic; + clk_en_5mhz_o : out std_logic; + por_n_o : out std_logic; + -- Control Interface ------------------------------------------------------ + tilt_n_i : in std_logic; + player_select_n_i : in std_logic_vector( 1 downto 0); + player_fire_n_i : in std_logic_vector( 1 downto 0); + player_up_n_i : in std_logic_vector( 1 downto 0); + player_right_n_i : in std_logic_vector( 1 downto 0); + player_down_n_i : in std_logic_vector( 1 downto 0); + player_left_n_i : in std_logic_vector( 1 downto 0); + player_bomb_n_i : in std_logic_vector( 1 downto 0); + right_chute_i : in std_logic; + left_chute_i : in std_logic; + -- DIP Switch Interface --------------------------------------------------- + dip_block_1_i : in std_logic_vector( 7 downto 0); + dip_block_2_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Audio Interface -------------------------------------------------------- + audio_o : out signed( 7 downto 0); + -- CPU ROM Interface ------------------------------------------------------ + rom_cpu_a_o : out std_logic_vector(14 downto 0); + rom_cpu_d_i : in std_logic_vector( 7 downto 0); + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + + +end ladybug_machine; + +architecture struct of ladybug_machine is + + -- Clock System ------------------------------------------------------------- + signal clk_en_10mhz_s, + clk_en_10mhz_n_s : std_logic; + signal clk_en_5mhz_s, + clk_en_5mhz_n_s : std_logic; + signal clk_en_4mhz_s : std_logic; + + -- Reset System ------------------------------------------------------------- + signal por_n_s : std_logic; + signal res_n_s : std_logic; + + signal sound_wait_n_s : std_logic; + signal wait_n_s : std_logic; + signal a_s : std_logic_vector(10 downto 0); + signal d_to_cpu_s, + d_from_cpu_s, + d_from_video_s : std_logic_vector( 7 downto 0); + signal rd_n_s, + wr_n_s : std_logic; + signal cs7_n_s, + cs10_n_s, + cs11_n_s, + cs12_n_s, + cs13_n_s : std_logic; + signal vc_s, + vbl_tick_n_s, + vbl_buf_s : std_logic; + + signal gpio_in0_s, + gpio_in1_s, + gpio_in2_s, + gpio_in3_s, + gpio_extra_s : std_logic_vector( 7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk_b : entity work.ladybug_clk + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + clk_en_10mhz_o => clk_en_10mhz_s, + clk_en_10mhz_n_o => clk_en_10mhz_n_s, + clk_en_5mhz_o => clk_en_5mhz_s, + clk_en_5mhz_n_o => clk_en_5mhz_n_s, + clk_en_4mhz_o => clk_en_4mhz_s + ); + -- + clk_en_5mhz_o <= clk_en_5mhz_s; + clk_en_10mhz_o <= clk_en_10mhz_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + res_b : entity work.ladybug_res + port map ( + clk_20mhz_i => clk_20mhz_i, + ext_res_n_i => ext_res_n_i, + res_n_o => res_n_s, + por_n_o => por_n_s + ); + -- + por_n_o <= por_n_s; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Joystick and DIP Switch Mapping + ----------------------------------------------------------------------------- + gpio_in0_s <= tilt_n_i & + player_select_n_i(1) & + player_select_n_i(0) & + player_fire_n_i(0) & + player_up_n_i(0) & + player_right_n_i(0) & + player_down_n_i(0) & + player_left_n_i(0); + gpio_in1_s <= vbl_buf_s & + vbl_tick_n_s & + vc_s & + player_fire_n_i(1) & + player_up_n_i(1) & + player_right_n_i(1) & + player_down_n_i(1) & + player_left_n_i(1); + gpio_in2_s <= dip_block_1_i; + gpio_in3_s <= dip_block_2_i; + gpio_extra_s <= player_bomb_n_i(1) & + '1' & + '1' & + '1' & + player_bomb_n_i(0) & + '1' & + '1' & + '1'; + + + ----------------------------------------------------------------------------- + -- CPU Unit + ----------------------------------------------------------------------------- + cpu_b : entity work.ladybug_cpu_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + res_n_i => res_n_s, + rom_cpu_a_o => rom_cpu_a_o, + rom_cpu_d_i => rom_cpu_d_i, + + sound_wait_n_i => sound_wait_n_s, + wait_n_i => wait_n_s, + right_chute_i => right_chute_i, + left_chute_i => left_chute_i, + gpio_in0_i => gpio_in0_s, + gpio_in1_i => gpio_in1_s, + gpio_in2_i => gpio_in2_s, + gpio_in3_i => gpio_in3_s, + gpio_extra_i => gpio_extra_s, + a_o => a_s, + d_to_cpu_i => d_to_cpu_s, + d_from_cpu_o => d_from_cpu_s, + rd_n_o => rd_n_s, + wr_n_o => wr_n_s, + cs7_n_o => cs7_n_s, + cs10_n_o => cs10_n_s, + cs11_n_o => cs11_n_s, + cs12_n_o => cs12_n_s, + cs13_n_o => cs13_n_s + ); + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_to_cpu_s <= d_from_video_s when (cs7_n_s and cs13_n_s) = '0' else (others => '1'); + + ----------------------------------------------------------------------------- + -- Video Unit + ----------------------------------------------------------------------------- + video_b : entity work.ladybug_video_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_s, + res_n_i => res_n_s, + clk_en_10mhz_i => clk_en_10mhz_s, + clk_en_10mhz_n_i => clk_en_10mhz_n_s, + clk_en_5mhz_i => clk_en_5mhz_s, + clk_en_5mhz_n_i => clk_en_5mhz_n_s, + clk_en_4mhz_i => clk_en_4mhz_s, + cs7_n_i => cs7_n_s, + cs10_n_i => cs10_n_s, + cs13_n_i => cs13_n_s, + a_i => a_s, + rd_n_i => rd_n_s, + wr_n_i => wr_n_s, + wait_n_o => wait_n_s, + d_from_cpu_i => d_from_cpu_s, + d_from_video_o => d_from_video_s, + vc_o => vc_s, + vbl_tick_n_o => vbl_tick_n_s, + vbl_buf_o => vbl_buf_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n_o, + vblank_o => vblank_o, + hblank_o => hblank_o, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + ----------------------------------------------------------------------------- + -- Sound Unit + ----------------------------------------------------------------------------- + sound_b : entity work.ladybug_sound_unit + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_4mhz_i => clk_en_4mhz_s, + por_n_i => por_n_s, + cs11_n_i => cs11_n_s, + cs12_n_i => cs12_n_s, + wr_n_i => wr_n_s, + d_from_cpu_i => d_from_cpu_s, + sound_wait_n_o => sound_wait_n_s, + audio_o => audio_o + ); + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_rams.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_rams.vhd new file mode 100644 index 00000000..578d08e7 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_rams.vhd @@ -0,0 +1,340 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_char_ram; + +architecture struct of ladybug_char_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_sprite_ram; + +architecture struct of ladybug_sprite_ram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_char_col_ram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video character color RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_char_col_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_char_col_ram; + +architecture struct of ladybug_char_col_ram is + + signal d_s : std_logic_vector(3 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_vram.vhd,v 1.1 2005/11/06 15:42:13 arnim Exp $ +-- +-- Wrapper for technology dependent video sprite VRAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 1 K x 4 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_sprite_vram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(9 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 3 downto 0); + d_o : out std_logic_vector( 3 downto 0) + ); + +end ladybug_sprite_vram; + +architecture struct of ladybug_sprite_vram is + + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram_inst: work.spram generic map(10,4) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_o + ); + +end struct; + +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_cpu_ram.vhd,v 1.1 2005/11/06 15:43:38 arnim Exp $ +-- +-- Wrapper for technology dependent CPU RAM. +-- +-- Xilinx flavor. +-- +-- Instantiate 4 K x 8 synchronous RAM. +-- +-- The clock enable of the controller clock is not attached to the RAM to +-- emulate the asynchronous read behavior of the original RAM. Read data is +-- available within a clock cycle of the controller although it takes two +-- cycles of the main clock to get the data from the RAM macro. +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_cpu_ram is + + port ( + clk_i : in std_logic; + clk_en_i : in std_logic; + a_i : in std_logic_vector(11 downto 0); + cs_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector( 7 downto 0); + d_o : out std_logic_vector( 7 downto 0) + ); + +end ladybug_cpu_ram; + +architecture struct of ladybug_cpu_ram is + + signal d_s : std_logic_vector(7 downto 0); + signal we_s : std_logic; + +begin + + -- generate write enable at same clock edge as controller logic + -- this might suppress intermediate writes when address bus changes + -- during write cycle + we_s <= not cs_n_i and not we_n_i and clk_en_i; + + ram1_inst: work.spram generic map(12,8) + port map + ( + address => a_i, + clock => clk_i, + data => d_i, + wren => we_s, + q => d_s + ); + + -- gate the data output for and'ing on CPU bus + d_o <= d_s when cs_n_i = '0' else (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_res.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_res.vhd new file mode 100644 index 00000000..85998a10 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_res.vhd @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_res.vhd,v 1.8 2005/10/10 20:52:04 arnim Exp $ +-- +-- Reset generator for the Lady Bug machine. +-- +-- This module generates a reset signal for the whole system synchronous to +-- the main clock. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity ladybug_res is + + port ( + clk_20mhz_i : in std_logic; + ext_res_n_i : in std_logic; + res_n_o : out std_logic; + por_n_o : out std_logic + ); + +end ladybug_res; + +architecture rtl of ladybug_res is + + -- 4.7e-2 s = 1 / 20,000,000 Hz * 940000 + constant res_delay_c : natural := 940000; + + signal res_sync_n_q : std_logic_vector(1 downto 0); + + signal res_delay_q : unsigned(19 downto 0); + signal res_n_q : std_logic; + + signal por_cnt_q : unsigned(1 downto 0) := "00"; + signal por_n_q : std_logic := '0'; +begin + + por_n_o <= por_n_q; + res_n_o <= res_n_q; + + ----------------------------------------------------------------------------- + -- Process por_cnt + -- + -- Purpose: + -- Generate a power-on reset for 4 clock cycles. + -- + por_cnt: process (clk_20mhz_i) + begin + if clk_20mhz_i'event and clk_20mhz_i = '1' then + if por_cnt_q = "11" then + por_n_q <= '1'; + else + por_cnt_q <= por_cnt_q + 1; + end if; + end if; + end process por_cnt; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_sync + -- + -- Purpose: + -- Synchronize asynchronous external reset to main 20 MHz clock. + -- + res_sync: process (clk_20mhz_i, ext_res_n_i, por_n_q) + begin + if ext_res_n_i = '0' or por_n_q = '0' then + res_sync_n_q <= (others => '0'); + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + res_sync_n_q(0) <= '1'; + res_sync_n_q(1) <= res_sync_n_q(0); + end if; + end process res_sync; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process res_delay + -- + -- Purpose: + -- Delay reset event (external or power-on) by 4.7e-2 s. + -- Reset delay is taken from Lady Bug reset circuit using NE555. + -- This duration might be too long for the actual requirements of the + -- FPGA circuit. + -- + res_delay: process (clk_20mhz_i, res_sync_n_q) + begin + if res_sync_n_q(1) = '0' then + res_delay_q <= (others => '0'); + res_n_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if res_delay_q = res_delay_c then + res_n_q <= '1'; + else + res_delay_q <= res_delay_q + 1; + end if; + end if; + end process res_delay; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_rgb.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_rgb.vhd new file mode 100644 index 00000000..1bfcd53c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_rgb.vhd @@ -0,0 +1,135 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_rgb.vhd,v 1.4 2005/10/10 22:02:14 arnim Exp $ +-- +-- RGB Generation Module of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_rgb is + + port ( + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + crg_i : in std_logic_vector(5 downto 1); + sig_i : in std_logic_vector(4 downto 1); + rgb_r_o : out std_logic_vector(1 downto 0); + rgb_g_o : out std_logic_vector(1 downto 0); + rgb_b_o : out std_logic_vector(1 downto 0) + ); + +end ladybug_rgb; + +architecture rtl of ladybug_rgb is + + signal a_s : std_logic_vector(5 downto 1); + signal rgb_s : std_logic_vector(8 downto 1); + signal rgb_n_q : std_logic_vector(8 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process addr + -- + -- Purpose: + -- Generates the PROM address. + -- + addr: process (crg_i, + sig_i) + variable sig_and_v : std_logic; + begin + sig_and_v := sig_i(1) and sig_i(2) and sig_i(3) and sig_i(4); + + a_s(5) <= crg_i(1) and sig_and_v; + + if not (sig_and_v and (crg_i(1) or crg_i(2))) = '0' then + a_s(4 downto 1) <= crg_i(2) & crg_i(5) & crg_i(4) & crg_i(3); + else + a_s(4 downto 1) <= sig_i; + end if; + + end process addr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- The RGB Conversion PROM + ----------------------------------------------------------------------------- + rgb_prom_b : entity work.prom_10_2 + port map ( + CLK => clk_20mhz_i, + ADDR => a_s, + DATA => rgb_s + ); + + ----------------------------------------------------------------------------- + -- Process rgb_latch + -- + -- Purpose: + -- Implements the output latch for the RGB values. + -- + rgb_latch: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rgb_n_q <= (others => '1'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_5mhz_i = '1' then + rgb_n_q <= not rgb_s; + end if; + end if; + end process rgb_latch; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rgb_r_o <= rgb_n_q(5+1) & rgb_n_q(0+1); + rgb_g_o <= rgb_n_q(6+1) & rgb_n_q(2+1); + rgb_b_o <= rgb_n_q(7+1) & rgb_n_q(4+1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sprite.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sprite.vhd new file mode 100644 index 00000000..941d997c --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sprite.vhd @@ -0,0 +1,857 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite.vhd,v 1.12 2005/10/10 22:02:14 arnim Exp $ +-- +-- Sprite Video Module of Lady Bug Machine. +-- +-- This unit contains the whole sprite logic which is distributed on the +-- CPU and video boards. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_sprite is +port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + a_i : in std_logic_vector( 9 downto 0); + d_from_cpu_i : in std_logic_vector( 7 downto 0); + -- RGB Video Interface ---------------------------------------------------- + h_i : in std_logic_vector( 3 downto 0); + h_t_i : in std_logic_vector( 3 downto 0); + hx_i : in std_logic; + ha_d_i : in std_logic; + v_i : in std_logic_vector( 3 downto 0); + v_t_i : in std_logic_vector( 3 downto 0); + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_d_i : in std_logic; + blank_flont_i : in std_logic; + blank_i : in std_logic; + sig_o : out std_logic_vector( 4 downto 1); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) +); + +end ladybug_sprite; + +architecture rtl of ladybug_sprite is + + signal sprite_ram_cs_n_s, + sprite_ram_we_n_s, + clk_5mhz_n_q, + clk_en_eck_s, + clk_en_rd_s, + clk_en_5ck_n_s, + clk_en_6ck_n_s, + clk_en_7ck_n_s, + clk_en_b7_p3_s, + clk_en_e7_3_s, + s6ck_n_s, + s7ck_n_s, + e5_p8_s, + a8_p5_n_s, + ct0_s, + ct1_s, + cr_mux_sel_s, + ck_inh_s, + ck_inh_n_q, + qh1_s, + qh2_s : std_logic; + + signal rb_s, + rb_unflip_s, + rc_s : std_logic_vector( 7 downto 0); + + signal c_s : std_logic_vector(10 downto 0); + signal v_cnt_s : std_logic_vector( 4 downto 0); + signal ra_s : std_logic_vector( 9 downto 0); + + signal ma_s : std_logic_vector(11 downto 0); + signal ma_q : std_logic_vector(11 downto 6); + signal mb_q : std_logic_vector( 1 downto 0); + signal mc_q : std_logic_vector( 6 downto 0); + signal cl_q : std_logic_vector( 4 downto 0); + + signal j7_s : std_logic_vector( 2 downto 0); + signal df_muxed_s : std_logic_vector( 7 downto 0); + + signal lu_a_s : std_logic_vector( 4 downto 0); + signal lu_d_s : std_logic_vector( 7 downto 0); + signal lu_d_mux_s : std_logic_vector( 3 downto 0); + + signal rd_shift_s, + rd_shift_int, + rd_vram_s : std_logic_vector(15 downto 0); + signal rs_s, + rs_int, + rs_n_s : std_logic_vector( 3 downto 0); + signal rs_enable_s : std_logic; + signal shift_oc_n_s : std_logic; + + signal j6_shifter : std_logic_vector( 3 downto 0); + signal h6_shifter : std_logic_vector( 3 downto 0); + signal ctrl_lu_a_s : std_logic_vector( 4 downto 0); + signal ctrl_lu_d_s : std_logic_vector( 7 downto 0); + signal v_cnt_a5_a6_s : std_logic_vector( 7 downto 0); + + signal ctrl_lu_q_d_s, + ctrl_lu_q : std_logic_vector( 6 downto 1); + + signal vram_we_n_s : std_logic; + signal vram_a6_in_s, + vram_a6_out_s, + vram_b6_in_s, + vram_b6_out_s, + vram_c6_in_s, + vram_c6_out_s, + vram_d6_in_s, + vram_d6_out_s : std_logic_vector( 3 downto 0); + + signal ca_q : std_logic_vector( 3 downto 1); + signal ca6_s, + ca7_s, + ca8_s : std_logic; + signal x_s : std_logic_vector( 5 downto 0); + + signal cr_s : std_logic_vector( 9 downto 0); + + signal vram_q : std_logic_vector(15 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- The Vertical Counters C5 D5 + ----------------------------------------------------------------------------- + v_cnt_c5_c6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_b7_p3_s = '1' then + if e5_p8_s = '0' then + v_cnt_s <= (v_t_i & "0"); + else + v_cnt_s <= v_cnt_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Counter J7 + ----------------------------------------------------------------------------- + j7_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + j7_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s6ck_n_s = '0' then + j7_s <= not mc_q(6) & mc_q(6) & '0'; + elsif (ct0_s or ct1_s or a8_p5_n_s or ck_inh_s) = '0' then + j7_s <= j7_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Sprite VRAM Counters A5 A6 + ----------------------------------------------------------------------------- + ct0_s <= v_cnt_a5_a6_s(0); + ct1_s <= v_cnt_a5_a6_s(1); + x_s <= v_cnt_a5_a6_s(7 downto 2); + + v_cnt_a5_a6_b : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + v_cnt_a5_a6_s <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if clk_en_10mhz_i = '1' then + if s7ck_n_s = '0' then + v_cnt_a5_a6_s(7 downto 4) <= (rb_s(7 downto 4)); + v_cnt_a5_a6_s(3 downto 0) <= (rb_s(3 downto 2) & not rc_s(7) & not rc_s(6)); + elsif ck_inh_n_q = '1' then + v_cnt_a5_a6_s <=v_cnt_a5_a6_s + 1; + end if; + end if; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Process sprite_ram_ctrl + -- + -- Purpose: + -- Generates the control signals for the sprite RAM. + -- + sprite_ram_ctrl: process ( cs7_n_i, + vbl_n_i, + a_i, + c_s, v_cnt_s) + variable cpu_access_v : std_logic; + begin + cpu_access_v := not cs7_n_i and not vbl_n_i; + + sprite_ram_we_n_s <= not cpu_access_v; + sprite_ram_cs_n_s <= cpu_access_v nor vbl_n_i; + + if vbl_n_i = '0' then + ra_s <= a_i; + else + ra_s <= v_cnt_s(4 downto 0) & c_s(4 downto 0); + end if; + end process sprite_ram_ctrl; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Sprite RAM P5 N5 + ----------------------------------------------------------------------------- + sprite_ram_b : entity work.ladybug_sprite_ram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => clk_en_5mhz_i, + a_i => ra_s, + cs_n_i => sprite_ram_cs_n_s, + we_n_i => sprite_ram_we_n_s, + d_i => d_from_cpu_i, + d_o => rb_s + ); + + ----------------------------------------------------------------------------- + -- Process rc_add + -- + -- Purpose: + -- Implements IC N6 and E6 which add sprite RAM data and Cx signals to + -- form RCx bus. + -- + rc_add: process (rb_s, c_s, v_i) + variable a_v, b_v, + sum_v : std_logic_vector(7 downto 0); + begin + -- prepare the inputs of the adder + a_v(3 downto 0) := rb_s(3 downto 0); + a_v(4) := '1'; + a_v(5) := '0'; + a_v(7 downto 6) := rb_s(1 downto 0); + + b_v(0) := not c_s(6); + b_v(1) := not c_s(7); + b_v(2) := not c_s(8); + b_v(3) := not v_i(3); + b_v(4) := c_s(10); + b_v(5) := '0'; + b_v(7 downto 6) := "11"; + + sum_v := a_v + b_v; + + rc_s <= sum_v; + + end process rc_add; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Sprite Control Logic + ----------------------------------------------------------------------------- + sprite_ctrl_b : entity work.ladybug_sprite_ctrl + port map ( + clk_20mhz_i => clk_20mhz_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + por_n_i => por_n_i, + vbl_n_i => vbl_n_i, + vbl_d_n_i => vbl_d_n_i, + vc_i => v_i(2), + vc_d_i => vc_d_i, + ha_i => h_i(0), + ha_d_i => ha_d_i, + rb6_i => rb_s(6), + rb7_i => rb_s(7), + rc3_i => rc_s(3), + rc4_i => rc_s(4), + rc5_i => rc_s(5), + j7_b_i => j7_s(1), + j7_c_i => j7_s(2), + clk_en_eck_i => clk_en_eck_s, + c_o => c_s, + clk_en_5ck_n_o => clk_en_5ck_n_s, + clk_en_6ck_n_o => clk_en_6ck_n_s, + clk_en_7ck_n_o => clk_en_7ck_n_s, + s6ck_n_o => s6ck_n_s, + s7ck_n_o => s7ck_n_s, + clk_en_b7_p3_o => clk_en_b7_p3_s, + e5_p8_o => e5_p8_s, + clk_en_e7_3_o => clk_en_e7_3_s, + a8_p5_n_o => a8_p5_n_s + ); + + ----------------------------------------------------------------------------- + -- Process misc_seq + -- + -- Purpose: + -- Implements several sequential elements. + -- + misc_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_n_q <= '0'; + ma_q <= (others => '0'); + mb_q <= (others => '0'); + mc_q <= (others => '0'); + cl_q <= (others => '0'); + ck_inh_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz_n into clock waveform ---------------------------------- + if clk_en_5mhz_n_i = '1' then + clk_5mhz_n_q <= '1'; + elsif clk_en_5mhz_i = '1' then + clk_5mhz_n_q <= '0'; + end if; + + -- 8-Bit Register M6 ---------------------------------------------------- + if clk_en_5ck_n_s = '1' then + mb_q <= rb_s(1 downto 0); + ma_q <= rb_s(7 downto 2); + end if; + + -- 8-Bit Register P6 ---------------------------------------------------- + if clk_en_e7_3_s = '1' then + -- these are inverted based on mc_q(4) + mc_q(3 downto 0) <= rc_s(3 downto 0); + -- inverts sprites horizontally + mc_q(4) <= rb_s(4); + -- inverts sprites vertically + mc_q(5) <= rb_s(5); + -- + mc_q(6) <= rb_s(6); + end if; + + -- 6-Bit Register B6 ---------------------------------------------------- + if clk_en_6ck_n_s = '1' then + cl_q <= rb_s(4 downto 0); + end if; + + -- Flip-Flop H8 --------------------------------------------------------- + if clk_en_10mhz_n_i = '1' then + ck_inh_n_q <= not ck_inh_s; + end if; + + end if; + end process misc_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ma_vec + -- + -- Purpose: + -- Build the ma_s vector. + -- + ma_vec: process ( ma_q, + mb_q, + mc_q, + j7_s) + begin + ma_s(11 downto 6) <= ma_q; + + if mc_q(6) = '0' then + ma_s(5) <= mb_q(1); + ma_s(4) <= mb_q(0); + else + ma_s(5) <= mc_q(3) xor mc_q(4); + ma_s(4) <= mc_q(5) xor j7_s(2); + end if; + + ma_s(3) <= mc_q(2) xor mc_q(4); + ma_s(2) <= mc_q(1) xor mc_q(4); + ma_s(1) <= mc_q(0) xor mc_q(4); + ma_s(0) <= mc_q(5) xor j7_s(0); + end process ma_vec; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process df_mux + -- + -- Purpose: + -- Builds the multiplexed data from Sprite ROM. + -- Two-stage multiplexer: + -- 1) ROM data to DFx: 16->8 + -- 2) DF to input for shift register: 8->8 + -- This is actually a scrambler. + -- + df_mux: process ( rom_sprite_d_i, + cl_q, + mc_q) + variable df_v : std_logic_vector(7 downto 0); + begin + if cl_q(4) = '0' then + -- ROM L7 + df_v := rom_sprite_d_i( 7 downto 0); + else + -- ROM M7 + df_v := rom_sprite_d_i(15 downto 8); + end if; + + if mc_q(5) = '0' then + df_muxed_s(0) <= df_v(1); + df_muxed_s(1) <= df_v(3); + df_muxed_s(2) <= df_v(5); + df_muxed_s(3) <= df_v(7); + -- + df_muxed_s(4) <= df_v(0); + df_muxed_s(5) <= df_v(2); + df_muxed_s(6) <= df_v(4); + df_muxed_s(7) <= df_v(6); + else + df_muxed_s(0) <= df_v(7); + df_muxed_s(1) <= df_v(5); + df_muxed_s(2) <= df_v(3); + df_muxed_s(3) <= df_v(1); + -- + df_muxed_s(4) <= df_v(6); + df_muxed_s(5) <= df_v(4); + df_muxed_s(6) <= df_v(2); + df_muxed_s(7) <= df_v(0); + end if; + + end process df_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- The Two 8-Bit Shift Registers H6 J6 + ----------------------------------------------------------------------------- + shifters_h6_j6 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + h6_shifter <= (others=>'0'); + j6_shifter <= (others=>'0'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + if (ct0_s or ct1_s or a8_p5_n_s) = '0' then + h6_shifter <= df_muxed_s(3 downto 0); + j6_shifter <= df_muxed_s(7 downto 4); + else + h6_shifter <= h6_shifter(2 downto 0) & "0"; + j6_shifter <= j6_shifter(2 downto 0) & "0"; + end if; + end if; + end if; + end process; + + qh1_s <= h6_shifter(3); + qh2_s <= j6_shifter(3); + + ----------------------------------------------------------------------------- + -- Sprite Look-up PROM F4 + ----------------------------------------------------------------------------- + lu_a_s(4 downto 2) <= cl_q(2 downto 0); + lu_a_s(1) <= qh2_s; + lu_a_s(0) <= qh1_s; + + prom_F4 : entity work.prom_10_1 + port map ( + CLK => clk_20mhz_i, + ADDR => lu_a_s, + DATA => lu_d_s + ); + + lu_d_mux_s <= lu_d_s(3 downto 0) when cl_q(3) = '0' else lu_d_s(7 downto 4); + + ----------------------------------------------------------------------------- + -- Sprite Control Look-up PROM C4 + ----------------------------------------------------------------------------- + ctrl_lu_a_s(0) <= '1'; + ctrl_lu_a_s(1) <= hx_i; + ctrl_lu_a_s(2) <= clk_5mhz_n_q; + ctrl_lu_a_s(3) <= h_i(0); + ctrl_lu_a_s(4) <= h_i(1); + + prom_C4 : entity work.prom_10_3 + port map ( + CLK => clk_20mhz_i, + ADDR => ctrl_lu_a_s, + DATA => ctrl_lu_d_s + ); + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_seq + -- + -- Purpose: + -- Registers output of Sprite Control Look-up PROM. + -- + ctrl_lu_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ctrl_lu_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + ctrl_lu_q <= ctrl_lu_q_d_s; + end if; + end process ctrl_lu_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ctrl_lu_comb + -- + -- Purpose: + -- Combinational logic for the sprite control registers. + -- + ctrl_lu_comb: process ( clk_en_10mhz_i, + ctrl_lu_d_s, + ctrl_lu_q, + ctrl_lu_q_d_s) + begin + -- default assignments + ctrl_lu_q_d_s <= ctrl_lu_q; + clk_en_eck_s <= '0'; + clk_en_rd_s <= '0'; + + -- register control + if clk_en_10mhz_i = '1' then + ctrl_lu_q_d_s <= ctrl_lu_d_s(5 downto 0); + + if ctrl_lu_q(1) = '0' and ctrl_lu_q_d_s(1) = '1' then + -- detect rising edge on ctrl_lu_q(1) + clk_en_eck_s <= '1'; + end if; + + if ctrl_lu_q(6) = '0' and ctrl_lu_q_d_s(6) = '1' then + -- detect rising edge on ctrl_lu_q(6) + clk_en_rd_s <= '1'; + end if; + end if; + + end process ctrl_lu_comb; + -- + shift_oc_n_s <= ctrl_lu_q(1) nand res_n_i; + ck_inh_s <= ctrl_lu_q(2); + cr_mux_sel_s <= ctrl_lu_q(3); + vram_we_n_s <= ctrl_lu_q(4); + rs_enable_s <= ctrl_lu_q(5); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process ca_seq + -- + -- Purpose: + -- Implements B5, the register that holds the CS flip-flops. + -- + ca_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + ca_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if clk_en_7ck_n_s = '1' then + ca_q <= c_s(8 downto 6); + end if; + end if; + end process ca_seq; + -- + ca6_s <= ca_q(1); + ca7_s <= ca_q(2); + ca8_s <= ca_q(3); + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process vram_mux + -- + -- Purpose: + -- Generates the VRAM address CRx. + -- It implements chips D5, C5 and B5. + -- + vram_mux: process ( h_i, h_t_i, + v_i, + x_s, + ca6_s, ca7_s, ca8_s, + cr_mux_sel_s) + begin + if cr_mux_sel_s = '0' then + -- D5 + cr_s(0) <= h_i(2); + cr_s(1) <= h_i(3); + cr_s(2) <= h_t_i(0); + cr_s(3) <= h_t_i(1); + -- C5 + cr_s(4) <= h_t_i(2); + cr_s(5) <= h_t_i(3); + cr_s(6) <= v_i(0); + cr_s(7) <= v_i(1); + -- B5 + cr_s(8) <= v_i(2); + cr_s(9) <= v_i(3); + + else + -- D5 + cr_s(0) <= x_s(0); + cr_s(1) <= x_s(1); + cr_s(2) <= x_s(2); + cr_s(3) <= x_s(3); + -- C5 + cr_s(4) <= x_s(4); + cr_s(5) <= x_s(5); + cr_s(6) <= ca6_s; + cr_s(7) <= ca7_s; + -- B5 + cr_s(8) <= ca8_s; + cr_s(9) <= not v_i(3); + + end if; + end process vram_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Shift Registers + ----------------------------------------------------------------------------- + shifters_a7_a8_d7_d8_f8 : process(clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + rd_shift_int <= (others=>'1'); + elsif rising_edge(clk_20mhz_i) then + if (clk_en_10mhz_i and not ck_inh_s) = '1' then + rs_int <= (qh1_s nor qh2_s) & rs_int(3 downto 1); + rd_shift_int <= + lu_d_mux_s(0) & rd_shift_int(15 downto 13) & + lu_d_mux_s(1) & rd_shift_int(11 downto 9) & + lu_d_mux_s(2) & rd_shift_int( 7 downto 5) & + lu_d_mux_s(3) & rd_shift_int( 3 downto 1); + end if; + end if; + end process; + + rd_shift_s <= rd_shift_int when shift_oc_n_s = '0' else (others=>'1'); + rs_s <= rs_int when shift_oc_n_s = '0' else (others=>'1'); +-- rs_n_s(3) <= not rs_s(3) or not rs_enable_s; +-- rs_n_s(2) <= not rs_s(2) or not rs_enable_s; +-- rs_n_s(1) <= not rs_s(1) or not rs_enable_s; +-- rs_n_s(0) <= not rs_s(0) or not rs_enable_s; + rs_n_s(3) <= rs_s(3) and rs_enable_s; + rs_n_s(2) <= rs_s(2) and rs_enable_s; + rs_n_s(1) <= rs_s(1) and rs_enable_s; + rs_n_s(0) <= rs_s(0) and rs_enable_s; + + ----------------------------------------------------------------------------- + -- Sprite VRAM + ----------------------------------------------------------------------------- + vram_a6_in_s(0) <= rd_shift_s( 0); + vram_a6_in_s(1) <= rd_shift_s( 4); + vram_a6_in_s(2) <= rd_shift_s( 8); + vram_a6_in_s(3) <= rd_shift_s(12); + vram_a6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(0), + we_n_i => vram_we_n_s, + d_i => vram_a6_in_s, + d_o => vram_a6_out_s + ); + -- + vram_b6_in_s(0) <= rd_shift_s( 1); + vram_b6_in_s(1) <= rd_shift_s( 5); + vram_b6_in_s(2) <= rd_shift_s( 9); + vram_b6_in_s(3) <= rd_shift_s(13); + vram_b6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(1), + we_n_i => vram_we_n_s, + d_i => vram_b6_in_s, + d_o => vram_b6_out_s + ); + -- + vram_c6_in_s(0) <= rd_shift_s( 2); + vram_c6_in_s(1) <= rd_shift_s( 6); + vram_c6_in_s(2) <= rd_shift_s(10); + vram_c6_in_s(3) <= rd_shift_s(14); + vram_c6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(2), + we_n_i => vram_we_n_s, + d_i => vram_c6_in_s, + d_o => vram_c6_out_s + ); + -- + vram_d6_in_s(0) <= rd_shift_s( 3); + vram_d6_in_s(1) <= rd_shift_s( 7); + vram_d6_in_s(2) <= rd_shift_s(11); + vram_d6_in_s(3) <= rd_shift_s(15); + vram_d6_b : entity work.ladybug_sprite_vram + port map ( + clk_i => clk_20mhz_i, + clk_en_i => '1', + a_i => cr_s, + cs_n_i => rs_n_s(3), + we_n_i => vram_we_n_s, + d_i => vram_d6_in_s, + d_o => vram_d6_out_s + ); + -- Remap VRAM data outputs to the complete bus ------------------------------ + rd_vram_s(15) <= vram_d6_out_s(3) or rs_n_s(3); + rd_vram_s(14) <= vram_c6_out_s(3) or rs_n_s(2); + rd_vram_s(13) <= vram_b6_out_s(3) or rs_n_s(1); + rd_vram_s(12) <= vram_a6_out_s(3) or rs_n_s(0); + -- + rd_vram_s(11) <= vram_d6_out_s(2) or rs_n_s(3); + rd_vram_s(10) <= vram_c6_out_s(2) or rs_n_s(2); + rd_vram_s( 9) <= vram_b6_out_s(2) or rs_n_s(1); + rd_vram_s( 8) <= vram_a6_out_s(2) or rs_n_s(0); + -- + rd_vram_s( 7) <= vram_d6_out_s(1) or rs_n_s(3); + rd_vram_s( 6) <= vram_c6_out_s(1) or rs_n_s(2); + rd_vram_s( 5) <= vram_b6_out_s(1) or rs_n_s(1); + rd_vram_s( 4) <= vram_a6_out_s(1) or rs_n_s(0); + -- + rd_vram_s( 3) <= vram_d6_out_s(0) or rs_n_s(3); + rd_vram_s( 2) <= vram_c6_out_s(0) or rs_n_s(2); + rd_vram_s( 1) <= vram_b6_out_s(0) or rs_n_s(1); + rd_vram_s( 0) <= vram_a6_out_s(0) or rs_n_s(0); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process rd_seq + -- + -- Purpose: + -- Implements the registers saving the RDx bus. + -- + rd_seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + vram_q <= (others => '0'); + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + if blank_flont_i = '0' then + -- pseudo-asynchronous clear + vram_q <= (others => '0'); + + elsif clk_en_rd_s = '1' then + if shift_oc_n_s = '0' then + -- take data from shift registers + vram_q <= rd_shift_s; + else + -- take data from VRAM + vram_q <= rd_vram_s; + end if; + end if; + end if; + end process rd_seq; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Process sig_mux + -- + -- Purpose: + -- Multiplexes the saved VRAM data to generate the four SIG outputs. + -- + sig_mux: process (vram_q, + h_i, + blank_i) + variable vec_v : std_logic_vector(1 downto 0); + begin + -- default assignment + sig_o <= (others => '0'); + + vec_v := (h_i(1) & h_i(0)); + + if blank_i = '0' then + case vec_v is + when "00" => + sig_o(1) <= vram_q( 1); + sig_o(2) <= vram_q( 5); + sig_o(3) <= vram_q( 9); + sig_o(4) <= vram_q(13); + when "01" => + sig_o(1) <= vram_q( 2); + sig_o(2) <= vram_q( 6); + sig_o(3) <= vram_q(10); + sig_o(4) <= vram_q(14); + when "10" => + sig_o(1) <= vram_q( 3); + sig_o(2) <= vram_q( 7); + sig_o(3) <= vram_q(11); + sig_o(4) <= vram_q(15); + when "11" => + sig_o(1) <= vram_q( 0); + sig_o(2) <= vram_q( 4); + sig_o(3) <= vram_q( 8); + sig_o(4) <= vram_q(12); + when others => + null; + end case; + end if; + end process sig_mux; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + rom_sprite_a_o <= ma_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sprite_ctrl.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sprite_ctrl.vhd new file mode 100644 index 00000000..f0eaff48 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_sprite_ctrl.vhd @@ -0,0 +1,491 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sprite_ctrl.vhd,v 1.8 2005/10/10 22:02:14 arnim Exp $ +-- +-- Control logic of the Sprite module. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +library ieee; +use ieee.numeric_std.all; + +entity ladybug_sprite_ctrl is + + port ( + clk_20mhz_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + por_n_i : in std_logic; + vbl_n_i : in std_logic; + vbl_d_n_i : in std_logic; + vc_i : in std_logic; + vc_d_i : in std_logic; + ha_i : in std_logic; + ha_d_i : in std_logic; + rb6_i : in std_logic; + rb7_i : in std_logic; + rc3_i : in std_logic; + rc4_i : in std_logic; + rc5_i : in std_logic; + j7_b_i : in std_logic; + j7_c_i : in std_logic; + clk_en_eck_i : in std_logic; + c_o : out std_logic_vector(10 downto 0); + clk_en_5ck_n_o : out std_logic; + clk_en_6ck_n_o : out std_logic; + clk_en_7ck_n_o : out std_logic; + s6ck_n_o : out std_logic; + s7ck_n_o : out std_logic; + clk_en_b7_p3_o : out std_logic; + e5_p8_o : out std_logic; + clk_en_e7_3_o : out std_logic; + a8_p5_n_o : out std_logic + ); + +end ladybug_sprite_ctrl; + + +architecture rtl of ladybug_sprite_ctrl is + + signal clk_5mhz_q : std_logic; + + signal a7_p5_s, + a7_p5_q : std_logic; + signal a7_p9_q : std_logic; + + signal a8_p5_q : std_logic; + + signal n4_p5_s, + n4_p5_q : std_logic; + + signal f7_ck_en_s, + f7_cl_s, + f7_qa_s, f7_qb_s, f7_qc_s, f7_qd_s, + f7_da_s, f7_db_s, f7_dc_s, f7_dd_s : std_logic_vector(2 downto 1); + + signal j5_ck_en_s, + j5_cl_s, + j5_qa_s, j5_qb_s, j5_qc_s, j5_qd_s, + j5_da_s, j5_db_s, j5_dc_s, j5_dd_s : std_logic_vector(2 downto 1); + + signal e7_ck_en_s, + e7_cl_n_s : std_logic; + signal e7_d_s, + e7_q_s, e7_q_n_s, + e7_d_out_s, e7_d_out_n_s : std_logic_vector(4 downto 1); + + signal h5_n_s : std_logic_vector(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements various sequential elements. + -- + seq: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + clk_5mhz_q <= '0'; + a7_p5_q <= '0'; + a7_p9_q <= '0'; + a8_p5_q <= '0'; + n4_p5_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Turn clk_5mhz enable into clock waveform ----------------------------- + if clk_en_5mhz_i = '1' then + clk_5mhz_q <= '1'; + elsif clk_en_5mhz_n_i = '1' then + clk_5mhz_q <= '0'; + end if; + + -- Flip-Flop A7 --------------------------------------------------------- + a7_p5_q <= a7_p5_s; + -- + if clk_en_5mhz_n_i = '1' then + a7_p9_q <= j5_qd_s(2); + end if; + + -- Flip-Flop A8 --------------------------------------------------------- + if clk_en_eck_i = '1' then + a8_p5_q <= j7_b_i nand j7_c_i; + end if; + + -- Flip-Flop N4 --------------------------------------------------------- + n4_p5_q <= n4_p5_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements various combinational signals. + -- + comb: process (a7_p5_q, + vc_i, vc_d_i, + n4_p5_q, + ha_i, ha_d_i, + f7_qd_s) + begin + -- D Input for Flip-Flop N4 ----------------------------------------------- + if a7_p5_q = '0' then + -- pseudo-asynchronous clear + n4_p5_s <= '0'; + elsif (vc_i and not vc_d_i) = '1' then + -- falling edge on VC + n4_p5_s <= '1'; + else + n4_p5_s <= n4_p5_q; + end if; + + -- D-Input for Flip-Flop A7.5 --------------------------------------------- + if (ha_i and not ha_d_i) = '1' then + -- falling edge on HA + a7_p5_s <= f7_qd_s(2); + else + a7_p5_s <= a7_p5_q; + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- F7 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + f7_cl_s(1) <= n4_p5_q and ha_i and vbl_n_i; + f7_cl_s(2) <= f7_cl_s(1); + -- + f7_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => f7_ck_en_s, + por_n_i => por_n_i, + cl_i => f7_cl_s, + qa_o => f7_qa_s, + qb_o => f7_qb_s, + qc_o => f7_qc_s, + qd_o => f7_qd_s, + da_o => f7_da_s, + db_o => f7_db_s, + dc_o => f7_dc_s, + dd_o => f7_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process f7_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in F7. + -- + f7_ck_en: process (j5_qd_s, j5_dd_s, + vbl_n_i, vbl_d_n_i, + ha_i, ha_d_i, + n4_p5_q, n4_p5_s, + f7_qd_s, f7_dd_s, + e7_q_n_s, e7_d_out_n_s, + f7_qb_s, f7_db_s) + + variable ff_q_v, ff_d_v : std_logic; + + begin + + -- combinational result based on flip-flop outputs + ff_q_v := j5_qd_s(2) or ( not ( not ( vbl_n_i and ha_i and n4_p5_q ) ) or not ( not f7_qd_s(2) nand not e7_q_n_s(1) ) ); + + -- combinational result based on flip-flop inputs + ff_d_v := j5_dd_s(2) or ( not ( not ( vbl_d_n_i and ha_d_i and n4_p5_s ) ) or not ( not f7_qd_s(2) nand not e7_d_out_n_s(1) ) ); +-- B7.3 D7.8 D7.8 F6.3 B7.6 + -- rising edge detector on B7.3 + f7_ck_en_s(1) <= not ff_q_v and ff_d_v; + + -- falling edge detector on F7.QB(1) + f7_ck_en_s(2) <= f7_qb_s(1) and not f7_db_s(1); + + end process f7_ck_en; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- J5 - Dual 4-Bit Binary Counter + ----------------------------------------------------------------------------- + j5_cl_s(1) <= not vbl_n_i + or -- D7.6 + not( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) + or -- D7.6 + n4_p5_q; + j5_cl_s(2) <= a7_p9_q + or -- B7.8 + ( + not ( + not ( + n4_p5_q + and -- D7.8 + ha_i + and -- D7.8 + vbl_n_i + ) + ) + or -- F6.3 + not ( + not f7_qd_s(2) + nand -- B7.6 + not e7_q_n_s(1) + ) + ); + -- + j5_b : entity work.ttl_393 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => j5_ck_en_s, + por_n_i => por_n_i, + cl_i => j5_cl_s, + qa_o => j5_qa_s, + qb_o => j5_qb_s, + qc_o => j5_qc_s, + qd_o => j5_qd_s, + da_o => j5_da_s, + db_o => j5_db_s, + dc_o => j5_dc_s, + dd_o => j5_dd_s + ); + + + ----------------------------------------------------------------------------- + -- Process j5_ck_en + -- + -- Purpose: + -- Build the clock enable for the two counters in J5. + -- + j5_ck_en: process (ha_i, ha_d_i, + e7_q_s, e7_d_out_s, + j5_qc_s, j5_dc_s) + begin + -- falling edge detector on F6.11 + j5_ck_en_s(1) <= -- Flip-Flop Outputs + ( + not ha_i + nand + e7_q_s(3) + ) + and not -- Flip-Flop Inputs + ( + not ha_d_i + nand + e7_d_out_s(3) + ); + + -- falling edge detector on C7.10 + j5_ck_en_s(2) <= -- Flip-Flop Outputs + ( + j5_qc_s(1) + nor + e7_q_s(2) + ) + and not -- Flip-Flop Inputs + ( + j5_dc_s(1) + nor + e7_d_out_s(2) + ); + end process j5_ck_en; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- E7 - Quad D-Type Flip-Flops with Clear + ----------------------------------------------------------------------------- + e7_d_s(1) <= not rb7_i; + e7_d_s(2) <= not ( + rb7_i + and -- D7.12 + rc5_i + and -- D7.12 + ( + not rc4_i + and -- C7.1 + not ( + not rc3_i + nor -- C6.3 + rb6_i + ) + ) + ); + e7_d_s(3) <= not e7_d_s(2) + and -- C7.4 + not a8_p5_q; + e7_d_s(4) <= '0'; + + -- This clock enable is not 100% equivalent to the schematics. + -- There, h5_n_s(4) could also generate a rising edge for E7 + -- but this is ignored here. It is believed that h5_n_s(4) acts + -- only as a clock enable/suppress for the 5 MHz clock. + -- This implementation suppresses as well a combinational feedback + -- loop from J5/1. + e7_ck_en_s <= clk_en_5mhz_i and not h5_n_s(4); + + e7_cl_n_s <= f7_qd_s(2) + or -- B7.3?? + ( + not clk_5mhz_q + nand -- F5.8 + not h5_n_s(0) + ) after 20 ns; + + e7_b : entity work.ttl_175 + port map ( + ck_i => clk_20mhz_i, + ck_en_i => e7_ck_en_s, + por_n_i => por_n_i, + cl_n_i => e7_cl_n_s, + d_i => e7_d_s, + q_o => e7_q_s, + q_n_o => e7_q_n_s, + d_o => e7_d_out_s, + d_n_o => e7_d_out_n_s + ); + + clk_en_e7_3_o <= not e7_q_s(3) and e7_d_out_s(3); + + + ----------------------------------------------------------------------------- + -- Process h5 + -- + -- Purpose: + -- Implements all functionality regarding H5. + -- + h5: process (j5_qa_s, j5_da_s, + j5_qb_s, j5_db_s, + ha_i, ha_d_i, + vbl_n_i, vbl_d_n_i, + a7_p5_q, a7_p5_s) + variable ff_q_v, ff_d_v : std_logic_vector(7 downto 0); + variable f5_p3_q_v, f5_p3_d_v : std_logic; + + ----------------------------------------------------------------------------- + -- 7445 - BCD to Decimal Decoder + ----------------------------------------------------------------------------- + function ttl_45_f(a, b, c, d : in std_logic) return + std_logic_vector is + variable idx_v : std_logic_vector( 3 downto 0); + variable vec_v : std_logic_vector(15 downto 0); + begin + vec_v := (others => '1'); + + idx_v := d & c & b & a; + vec_v(to_integer(unsigned(idx_v))) := '0'; + + return vec_v(7 downto 0); + end ttl_45_f; + + begin + -- combinational result based on flip-flop outputs + f5_p3_q_v := not a7_p5_q nand vbl_n_i; + ff_q_v := ttl_45_f(a => j5_qa_s(1), + b => j5_qb_s(1), + c => ha_i, + d => f5_p3_q_v); + -- combinational result based on flip-flop inputs + f5_p3_d_v := not a7_p5_s nand vbl_d_n_i; + ff_d_v := ttl_45_f(a => j5_da_s(1), + b => j5_db_s(1), + c => ha_d_i, + d => f5_p3_d_v); + + -- combinational output of H5 is based on flip-flop outputs + h5_n_s <= ff_q_v; + + -- clock enable for flip-flops on /5CK + clk_en_5ck_n_o <= not ff_q_v(5) and ff_d_v(5); + -- clock enable for flip-flops on /6CK + clk_en_6ck_n_o <= not ff_q_v(6) and ff_d_v(6); + -- clock enable for flip-flops on /7CK + clk_en_7ck_n_o <= not ff_q_v(7) and ff_d_v(7); + + s6ck_n_o <= ff_q_v(6); + s7ck_n_o <= ff_q_v(7); + end process h5; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + clk_en_b7_p3_o <= f7_ck_en_s(1); + e5_p8_o <= n4_p5_q + nor -- E5.8 + not ( + f7_qa_s(1) + nand -- F6.8 + f7_qb_s(1) + ); + a8_p5_n_o <= not a8_p5_q; + + c_o( 0) <= j5_qa_s(1); + c_o( 1) <= j5_qb_s(1); + c_o( 2) <= j5_qa_s(2); + c_o( 3) <= j5_qb_s(2); + c_o( 4) <= j5_qc_s(2); + c_o( 5) <= j5_qd_s(2); + c_o( 6) <= f7_qa_s(2); + c_o( 7) <= f7_qb_s(2); + c_o( 8) <= f7_qc_s(2); + c_o( 9) <= f7_qa_s(1); + c_o(10) <= f7_qb_s(1); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_video_timing.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_video_timing.vhd new file mode 100644 index 00000000..58a3a818 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_video_timing.vhd @@ -0,0 +1,356 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_timing.vhd,v 1.16 2006/02/07 19:27:38 arnim Exp $ +-- +-- The Video Timing Module of Lady Bug Machine. +-- +-- It implements the horizontal and vertical timing signals including composite +-- sync information. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ladybug_video_timing is + + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + -- Horizontal Timing Interface -------------------------------------------- + h_o : out std_logic_vector(3 downto 0); + h_t_o : out std_logic_vector(3 downto 0); + hbl_o : out std_logic; + hx_o : out std_logic; + ha_d_o : out std_logic; + ha_t_rise_o : out std_logic; + -- Vertical Timing Interface ---------------------------------------------- + v_o : out std_logic_vector(3 downto 0); + v_t_o : out std_logic_vector(3 downto 0); + vc_d_o : out std_logic; + vbl_n_o : out std_logic; + vbl_d_n_o : out std_logic; + vbl_t_n_o : out std_logic; + blank_flont_o : out std_logic; + -- RBG Video Interface ---------------------------------------------------- + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic + ); + +end ladybug_video_timing; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ladybug_video_timing is + + -- horizontal timing circuit + signal h_preset : std_logic_vector(7 downto 0); + signal h_rise : std_logic_vector(7 downto 0); + signal h_do : std_logic_vector(7 downto 0); + signal h_j2_h2 : std_logic_vector(7 downto 0); + signal h_s : std_logic_vector(7 downto 0); + signal hx_q, + hx_s, + hx_n_s : std_logic; + signal hx_rise_s : std_logic; + signal hbl_q : std_logic; +-- signal hbl_n_s : std_logic; + signal hsync_n_q : std_logic; + signal h_carry_s : std_logic; + signal hd_rise_s : std_logic; + + -- vertical timing circuit + signal v_preset : std_logic_vector(7 downto 0); + signal v_rise : std_logic_vector(7 downto 0); + signal v_do : std_logic_vector(7 downto 0); + signal v_s : std_logic_vector(7 downto 0); + signal vx_q, + vx_n_s : std_logic; + signal vbl_q, + vbl_s, + vbl_n_s : std_logic; + signal vbl_t_q, + vbl_t_s, + vbl_t_n_s : std_logic; + signal vsync_n_q : std_logic; + signal v_carry_s : std_logic; + signal vc_rise_s, + vd_rise_s : std_logic; + signal vb_t_rise_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Horizontal Timing counters J2 H2 + ----------------------------------------------------------------------------- + hd_rise_s <= h_rise(3); + ha_t_rise_o <= h_rise(4); + ha_d_o <= h_do(0); + h_preset <= hx_n_s & hx_n_s & "00" & hx_n_s & "000"; + + h_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => clk_en_5mhz_i, + reset_n_i => por_n_i, + load_i => h_carry_s, + preset_i => h_preset, + q_o => h_s, + co_o => h_carry_s, + rise_q_o => h_rise, + d_o => h_do + ); + + ----------------------------------------------------------------------------- + -- Process h_timing + -- + -- Purpose: + -- Implement the horizontal timing circuit. + -- + -- The original circuit has no asynchronous reset. To have a stable + -- behavior on silicon, all sequential elements are cleared with the + -- power-on reset. This assumes that the original chips power-up to + -- these values. + -- + -- See also instantiations of ttl_161. + -- + h_timing: process (clk_20mhz_i, por_n_i) + begin + if por_n_i = '0' then + hx_q <= '0'; + hbl_q <= '0'; + hsync_n_q <= '1'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Flip-flops on 5 MHz clock -------------------------------------------- + -- HX + hx_q <= hx_s; + + -- Free running flip-flops ---------------------------------------------- + -- HBL + if (hx_q and not h_s(3)) = '1' then + -- pseudo-asynchronous preset + hbl_q <= '1'; + elsif hd_rise_s = '1' then + -- Rising edge on HD + hbl_q <= hx_q; + end if; + + -- HSYNC + if hx_q = '0' then + -- pseudo-asynchronous preset + hsync_n_q <= '1'; + elsif hd_rise_s = '1' then + -- rising edge on HD + hsync_n_q <= h_s(5); + end if; + + end if; + + end process h_timing; + -- + ----------------------------------------------------------------------------- + + hx_n_s <= not hx_q; +--hbl_n_s <= not hbl_q; + + ----------------------------------------------------------------------------- + -- Process hx_comb + -- + -- Purpose: + -- Implements the combinational logic for hx. Including rising edge + -- detection. + -- + hx_comb: process (clk_en_5mhz_i, h_carry_s, hx_q) + begin + -- default assignments + hx_s <= hx_q; + hx_rise_s <= '0'; + + -- HX + if clk_en_5mhz_i = '1' then + if h_carry_s = '1' then + hx_s <= not hx_q; + + -- flag rising edge of hx_q + if hx_q = '0' then + hx_rise_s <= '1'; + end if; + end if; + end if; + + end process hx_comb; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Vertical Timing counters E5 E2 + ----------------------------------------------------------------------------- + vb_t_rise_s <= v_rise(5); + vd_rise_s <= v_rise(3); + vc_rise_s <= v_rise(2); + vc_d_o <= v_do(2); + v_preset <= vx_n_s & vx_n_s & vx_n_s & vx_q & vx_n_s & '0' & vx_n_s & '0'; + + v_counter : entity work.counter + port map ( + ck_i => clk_20mhz_i, + ck_en_i => hx_rise_s, + reset_n_i => por_n_i, + load_i => v_carry_s, + preset_i => v_preset, + q_o => v_s, + co_o => v_carry_s, + rise_q_o => v_rise, + d_o => v_do + ); + + ----------------------------------------------------------------------------- + -- Process v_timing + -- + -- Purpose: + -- Implement the vertical timing circuit. + -- + -- See process h_timing for reset discussion. + -- + v_timing: process (clk_20mhz_i, por_n_i) + variable preset_v : boolean; + begin + if por_n_i = '0' then + vx_q <= '0'; + vbl_q <= '0'; + vsync_n_q <= '1'; + vbl_t_q <= '0'; + + elsif clk_20mhz_i'event and clk_20mhz_i = '1' then + -- Free running flip-flops ---------------------------------------------- + -- VX + if hx_rise_s = '1' then + if v_carry_s = '1' then + vx_q <= vx_n_s; + end if; + end if; + + -- VSYNC + if vc_rise_s = '1' then + -- rising edge on VC + vsync_n_q <= not (v_s(7) and v_s(6) and v_s(5) and v_s(4) and v_s(3) and vx_n_s); + end if; + + -- VBL + vbl_q <= vbl_s; + + -- VBL' + vbl_t_q <= vbl_t_s; + + end if; + end process v_timing; + -- + ----------------------------------------------------------------------------- + + vx_n_s <= not vx_q; + vbl_n_s <= not vbl_q; + vbl_t_n_s <= not vbl_t_q; + + + ----------------------------------------------------------------------------- + -- Process vbl_comb + -- + -- Purpose: + -- Combinational logic for vbl_q and vbl_t_q. + -- + vbl_comb: process (v_s, vb_t_rise_s, vd_rise_s, vx_q, vbl_q, vbl_t_q) + variable preset_v : boolean; + begin + preset_v := (v_s(5) and v_s(6) and v_s(7)) = '1'; + -- VBL + vbl_s <= vbl_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_s <= '1'; + elsif vb_t_rise_s = '1' then + -- rising edge on VB' + vbl_s <= vx_q; + end if; + + -- VBL' + vbl_t_s <= vbl_t_q; + if preset_v then + -- pseudo-asynchronous preset + vbl_t_s <= '1'; + elsif vd_rise_s = '1' then + -- rising edge on VD + vbl_t_s <= vx_q; + end if; + + end process vbl_comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + h_o <= h_s(3 downto 0); + h_t_o <= h_s(7 downto 4); + hbl_o <= hbl_q; + hx_o <= hx_q; + v_o <= v_s(3 downto 0); + v_t_o <= v_s(7 downto 4); + vbl_n_o <= vbl_n_s; + vbl_t_n_o <= vbl_t_n_s; + vbl_d_n_o <= not vbl_s; + hsync_n_o <= hsync_n_q; + vsync_n_o <= vsync_n_q; + comp_sync_n_o <= not hsync_n_q xor vsync_n_q; + + -- I have no idea why there is an additional wire called BLANK FLONT. + -- From the schematics, it is the same as /VBL (just buffered). + blank_flont_o <= vbl_n_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_video_unit.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_video_unit.vhd new file mode 100644 index 00000000..96d58e5f --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ladybug_video_unit.vhd @@ -0,0 +1,240 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_video_unit.vhd,v 1.22 2006/02/07 00:44:35 arnim Exp $ +-- +-- The Video Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ladybug_video_unit is + port ( + -- Clock and Reset Interface ---------------------------------------------- + clk_20mhz_i : in std_logic; + por_n_i : in std_logic; + res_n_i : in std_logic; + clk_en_10mhz_i : in std_logic; + clk_en_10mhz_n_i : in std_logic; + clk_en_5mhz_i : in std_logic; + clk_en_5mhz_n_i : in std_logic; + clk_en_4mhz_i : in std_logic; + -- CPU Interface ---------------------------------------------------------- + cs7_n_i : in std_logic; + cs10_n_i : in std_logic; + cs13_n_i : in std_logic; + a_i : in std_logic_vector(10 downto 0); + rd_n_i : in std_logic; + wr_n_i : in std_logic; + wait_n_o : out std_logic; + d_from_cpu_i : in std_logic_vector( 7 downto 0); + d_from_video_o : out std_logic_vector( 7 downto 0); + vc_o : out std_logic; + vbl_tick_n_o : out std_logic; + vbl_buf_o : out std_logic; + -- RGB Video Interface ---------------------------------------------------- + rgb_r_o : out std_logic_vector( 1 downto 0); + rgb_g_o : out std_logic_vector( 1 downto 0); + rgb_b_o : out std_logic_vector( 1 downto 0); + hsync_n_o : out std_logic; + vsync_n_o : out std_logic; + comp_sync_n_o : out std_logic; + vblank_o : out std_logic; + hblank_o : out std_logic; + -- Character ROM Interface ------------------------------------------------ + rom_char_a_o : out std_logic_vector(11 downto 0); + rom_char_d_i : in std_logic_vector(15 downto 0); + -- Sprite ROM Interface --------------------------------------------------- + rom_sprite_a_o : out std_logic_vector(11 downto 0); + rom_sprite_d_i : in std_logic_vector(15 downto 0) + ); + +end ladybug_video_unit; + +architecture struct of ladybug_video_unit is + + signal h_s, + h_t_s : std_logic_vector(3 downto 0); + signal ha_d_s, + ha_t_rise_s : std_logic; + signal hbl_s : std_logic; + signal hx_s : std_logic; + + signal v_s, + v_t_s : std_logic_vector(3 downto 0); + signal vc_d_s : std_logic; + signal vbl_n_s, + vbl_d_n_s : std_logic; + + signal blank_flont_s : std_logic; + + signal d_from_char_s : std_logic_vector(7 downto 0); + + signal blank_s : std_logic; + signal crg_s : std_logic_vector(5 downto 1); + + signal sig_s : std_logic_vector(4 downto 1); + + signal comp_sync_n : std_logic; + +begin + comp_sync_n_o <= comp_sync_n and vbl_n_s; + vbl_buf_o <= not vbl_n_s; + ----------------------------------------------------------------------------- + -- Horizontal and Vertical Timing Generator + ----------------------------------------------------------------------------- + timing_b : entity work.ladybug_video_timing + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + h_o => h_s, + h_t_o => h_t_s, + hbl_o => hbl_s, + hx_o => hx_s, + ha_d_o => ha_d_s, + ha_t_rise_o => ha_t_rise_s, + v_o => v_s, + v_t_o => v_t_s, + vc_d_o => vc_d_s, + vbl_n_o => vbl_n_s, + vbl_d_n_o => vbl_d_n_s, + vbl_t_n_o => vbl_tick_n_o, + blank_flont_o => blank_flont_s, + hsync_n_o => hsync_n_o, + vsync_n_o => vsync_n_o, + comp_sync_n_o => comp_sync_n + ); + vc_o <= v_s(2); + + + ----------------------------------------------------------------------------- + -- Character Module + ----------------------------------------------------------------------------- + char_b : entity work.ladybug_char + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_4mhz_i => clk_en_4mhz_i, + cs10_n_i => cs10_n_i, + cs13_n_i => cs13_n_i, + a_i => a_i, + rd_n_i => rd_n_i, + wr_n_i => wr_n_i, + wait_n_o => wait_n_o, + d_from_cpu_i => d_from_cpu_i, + d_from_char_o => d_from_char_s, + h_i => h_s, + h_t_i => h_t_s, + ha_t_rise_i => ha_t_rise_s, + hx_i => hx_s, + v_i => v_s, + v_t_i => v_t_s, + hbl_i => hbl_s, + blank_flont_i => blank_flont_s, + blank_o => blank_s, + vblank_o => vblank_o, + hblank_o => hblank_o, + crg_o => crg_s, + rom_char_a_o => rom_char_a_o, + rom_char_d_i => rom_char_d_i + ); + + + ----------------------------------------------------------------------------- + -- Sprite Module + ----------------------------------------------------------------------------- + sprite_b : entity work.ladybug_sprite + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + res_n_i => res_n_i, + clk_en_10mhz_i => clk_en_10mhz_i, + clk_en_10mhz_n_i => clk_en_10mhz_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + clk_en_5mhz_n_i => clk_en_5mhz_n_i, + cs7_n_i => cs7_n_i, + a_i => a_i(9 downto 0), + d_from_cpu_i => d_from_cpu_i, + h_i => h_s, + h_t_i => h_t_s, + hx_i => hx_s, + ha_d_i => ha_d_s, + v_i => v_s, + v_t_i => v_t_s, + vbl_n_i => vbl_n_s, + vbl_d_n_i => vbl_d_n_s, + vc_d_i => vc_d_s, + blank_flont_i => blank_flont_s, + blank_i => blank_s, + sig_o => sig_s, + rom_sprite_a_o => rom_sprite_a_o, + rom_sprite_d_i => rom_sprite_d_i + ); + + + ----------------------------------------------------------------------------- + -- RGB Generator + ----------------------------------------------------------------------------- + rgb_b : entity work.ladybug_rgb + port map ( + clk_20mhz_i => clk_20mhz_i, + por_n_i => por_n_i, + clk_en_5mhz_i => clk_en_5mhz_i, + crg_i => crg_s, + sig_i => sig_s, + rgb_r_o => rgb_r_o, + rgb_g_o => rgb_g_o, + rgb_b_o => rgb_b_o + ); + + + ----------------------------------------------------------------------------- + -- Bus Multiplexer + ----------------------------------------------------------------------------- + d_from_video_o <= d_from_char_s + when cs13_n_i = '0' else + (others => '1'); + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/mist_io.v b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/osd.v b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/pll.qip b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/pll.v b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/pll.v new file mode 100644 index 00000000..65715540 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 20, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/scandoubler.v b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/ladybug_sound_unit.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/ladybug_sound_unit.vhd new file mode 100644 index 00000000..23ad2a6a --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/ladybug_sound_unit.vhd @@ -0,0 +1,143 @@ +------------------------------------------------------------------------------- +-- +-- FPGA Lady Bug +-- +-- $Id: ladybug_sound_unit.vhd,v 1.4 2006/06/16 22:41:37 arnim Exp $ +-- +-- Sound Unit of the Lady Bug Machine. +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ladybug_sound_unit is + + port ( + clk_20mhz_i : in std_logic; + clk_en_4mhz_i : in std_logic; + por_n_i : in std_logic; + cs11_n_i : in std_logic; + cs12_n_i : in std_logic; + wr_n_i : in std_logic; + d_from_cpu_i : in std_logic_vector(7 downto 0); + sound_wait_n_o : out std_logic; + audio_o : out signed(7 downto 0) + ); + +end ladybug_sound_unit; + +architecture struct of ladybug_sound_unit is + + signal ready_b1_s, + ready_c1_s : std_logic; + + signal aout_b1_s, + aout_c1_s : signed(7 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip B1 + ----------------------------------------------------------------------------- + snd_b1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs11_n_i, + we_n_i => wr_n_i, + ready_o => ready_b1_s, + d_i => d_from_cpu_i, + aout_o => aout_b1_s + ); + + + ----------------------------------------------------------------------------- + -- SN76489 Sound Chip C1 + ----------------------------------------------------------------------------- + snd_c1_b : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk_20mhz_i, + clock_en_i => clk_en_4mhz_i, + res_n_i => por_n_i, + ce_n_i => cs12_n_i, + we_n_i => wr_n_i, + ready_o => ready_c1_s, + d_i => d_from_cpu_i, + aout_o => aout_c1_s + ); + + + ----------------------------------------------------------------------------- + -- Process mix + -- + -- Purpose: + -- Mix the digital audio of the two SN76489 instances. + -- Additional care is taken to avoid audio overfow/clipping. + -- + mix: process (aout_b1_s, + aout_c1_s) + variable sum_v : signed(8 downto 0); + begin + sum_v := RESIZE(aout_b1_s, 9) + RESIZE(aout_c1_s, 9); + + if sum_v > 127 then + audio_o <= to_signed(127, 8); + elsif sum_v < -128 then + audio_o <= to_signed(-128, 8); + else + audio_o <= RESIZE(sum_v, 8); + end if; + + end process mix; + -- + ----------------------------------------------------------------------------- + + + sound_wait_n_o <= ready_b1_s and ready_c1_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING new file mode 100644 index 00000000..60549be5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) 19yy + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README new file mode 100644 index 00000000..33630144 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/README @@ -0,0 +1,143 @@ + +An SN76489AN Compatible Implementation in VHDL +============================================== +Version: $Date: 2006/06/18 19:28:40 $ + +Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +See the file COPYING. + + +Integration +----------- + +The sn76489 design exhibits all interface signals as the original chip. It +only differs in the audio data output which is provided as an 8 bit signed +vector instead of an analog output pin. + + generic ( + clock_div_16_g : integer := 1 + -- Set to '1' when operating the design in SN76489 mode. The primary clock + -- input is divided by 16 in this variant. The data sheet mentions the + -- SN76494 which contains a divide-by-2 clock input stage. Set the generic + -- to '0' to enable this mode. + ); + port ( + clock_i : in std_logic; + -- Primary clock input + -- Drive with the target frequency or any integer multiple of it. + + clock_en_i : in std_logic; + -- Clock enable + -- A '1' on this input qualifies a valid rising edge on clock_i. A '0' + -- disables the next rising clock edge, effectivley halting the design + -- until the next enabled rising clock edge. + -- Can be used to run the core at lower frequencies than applied on + -- clock_i. + + res_n_i : in std_logic; + -- Asynchronous low active reset input. + -- Sets all sequential elements to a known state. + + ce_n_i : in std_logic; + -- Chip enable, low active. + + we_n_i : in std_logic; + -- Write enable, low active. + + ready_o : out std_logic; + -- Ready indication to microprocessor. + + d_i : in std_logic_vector(0 to 7); + -- Data input + -- MSB 0 ... 7 LSB + + aout_o : out signed(0 to 7) + -- Audio output, signed vector + -- MSB/SIGN 0 ... 7 LSB + ); + + +Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the +MSB and bit 7 to be the LSB. This has been implemented according to TI's data +sheet, thus all register/data format figures apply 1:1 for this design. +Many systems will flip the system data bus bit wise before it is connected to +this PSG. This is simply achieved with the following VHDL construct: + + signal data_s : std_logic_vector(7 downto 0); + + ... + d_i => data_s, + ... + +d_i and data_s will be assigned from left to right, resulting in the expected +bit assignment: + + d_i data_s + 0 7 + 1 6 + ... + 6 1 + 7 0 + + +As this design is fully synchronous, care has to be taken when the design +replaces an SN76489 in asynchronous mode. No problems are expected when +interfacing the code to other synchronous components. + + +Design Hierarchy +---------------- + + sn76489_top + | + +-- sn76489_latch_ctrl + | + +-- sn76489_clock_div + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + \-- sn76489_noise + | + \-- sn76489_attentuator + +Resulting compilation sequence: + + sn76489_comp_pack-p.vhd + sn76489_top.vhd + sn76489_latch_ctrl.vhd + sn76489_latch_ctrl-c.vhd + sn76489_clock_div.vhd + sn76489_clock_div-c.vhd + sn76489_attenuator.vhd + sn76489_attenuator-c.vhd + sn76489_tone.vhd + sn76489_tone-c.vhd + sn76489_noise.vhd + sn76489_noise-c.vhd + sn76489_top-c.vhd + +Skip the files containing VHDL configurations when analyzing the code for +synthesis. + + +References +---------- + +* TI Data sheet SN76489.pdf + ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf + +* John Kortink's article on the SN76489: + http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ + +* Maxim's "SN76489 notes" in + http://www.smspower.org/maxim/docs/SN76489.txt diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd new file mode 100644 index 00000000..444064e5 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_attenuator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $ +-- +-- Attenuator Module +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_attenuator is + + port ( + attenuation_i : in std_logic_vector(0 to 3); + factor_i : in signed(0 to 1); + product_o : out signed(0 to 7) + ); + +end sn76489_attenuator; + + +architecture rtl of sn76489_attenuator is + +begin + + ----------------------------------------------------------------------------- + -- Process attenuate + -- + -- Purpose: + -- Determine the attenuation and generate the resulting product. + -- + -- The maximum attenuation value is 31 which corresponds to volume off. + -- As described in the data sheet, the maximum "playing" attenuation is + -- 28 = 16 + 8 + 4 + -- + -- The table for the volume constants is derived from the following + -- formula (each step is 2dB voltage): + -- v(0) = 31 + -- v(n+1) = v(n) * 0.79432823 + -- + attenuate: process (attenuation_i, + factor_i) + + type volume_t is array (natural range 0 to 15) of natural; + constant volume_c : volume_t := + (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0); + + variable attenuation_v : unsigned(attenuation_i'range); + variable volume_v : signed(product_o'range); + + begin + + attenuation_v := unsigned(attenuation_i); + + -- volume look-up table + volume_v := to_signed(volume_c(to_integer(attenuation_v)), + product_o'length); + + -- this replaces a multiplier and consumes a bit fewer + -- resources + case to_integer(factor_i) is + when +1 => + product_o <= volume_v; + when -1 => + product_o <= -volume_v; + when others => + product_o <= (others => '0'); + end case; + + end process attenuate; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd new file mode 100644 index 00000000..eab86beb --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_clock_div.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $ +-- +-- Clock Divider Circuit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_clock_div is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + clk_en_o : out boolean + ); + +end sn76489_clock_div; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_clock_div is + + signal cnt_s, + cnt_q : unsigned(3 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential counter element. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + cnt_q <= (others => '0'); + elsif clock_i'event and clock_i = '1' then + cnt_q <= cnt_s; + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational counter logic. + -- + comb: process (clock_en_i, + cnt_q) + begin + -- default assignments + cnt_s <= cnt_q; + clk_en_o <= false; + + if clock_en_i = '1' then + + if cnt_q = 0 then + clk_en_o <= true; + + if clock_div_16_g = 1 then + cnt_s <= to_unsigned(15, cnt_q'length); + elsif clock_div_16_g = 0 then + cnt_s <= to_unsigned( 1, cnt_q'length); + else + -- pragma translate_off + assert false + report "Generic clock_div_16_g must be either 0 or 1." + severity failure; + -- pragma translate_on + end if; + + else + cnt_s <= cnt_q - 1; + + end if; + + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd new file mode 100644 index 00000000..789720c2 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_latch_ctrl.vhd @@ -0,0 +1,138 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Latch Control Unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_latch_ctrl is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector(0 to 7); + ready_o : out std_logic; + tone1_we_o : out boolean; + tone2_we_o : out boolean; + tone3_we_o : out boolean; + noise_we_o : out boolean; + r2_o : out std_logic + ); + +end sn76489_latch_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_latch_ctrl is + + signal reg_q : std_logic_vector(0 to 2); + signal we_q : boolean; + signal ready_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + reg_q <= (others => '0'); + we_q <= false; + ready_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + -- READY Flag Output ---------------------------------------------------- + if ready_q = '0' and we_q then + if clk_en_i then + -- assert READY when write access happened + ready_q <= '1'; + end if; + elsif ce_n_i = '1' then + -- deassert READY when access has finished + ready_q <= '0'; + end if; + + -- Register Selection --------------------------------------------------- + if ce_n_i = '0' and we_n_i = '0' then + if clk_en_i then + if d_i(0) = '1' then + reg_q <= d_i(1 to 3); + end if; + we_q <= true; + end if; + else + we_q <= false; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + tone1_we_o <= reg_q(0 to 1) = "00" and we_q; + tone2_we_o <= reg_q(0 to 1) = "01" and we_q; + tone3_we_o <= reg_q(0 to 1) = "10" and we_q; + noise_we_o <= reg_q(0 to 1) = "11" and we_q; + + r2_o <= reg_q(2); + + ready_o <= ready_q + when ce_n_i = '0' else + '1'; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd new file mode 100644 index 00000000..688bdd56 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_noise.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Noise Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_noise is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + tone3_ff_i : in std_logic; + noise_o : out signed(0 to 7) + ); + +end sn76489_noise; + +architecture rtl of sn76489_noise is + + signal nf_q : std_logic_vector(0 to 1); + signal fb_q : std_logic; + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 6); + signal freq_ff_q : std_logic; + + signal shift_source_s, + shift_source_q : std_logic; + signal shift_rise_edge_s : boolean; + + signal lfsr_q : std_logic_vector(0 to 15); + + signal freq_s : signed(0 to 1); + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + nf_q <= (others => '0'); + fb_q <= '0'; + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to control register + -- both access types can write to the control register! + nf_q <= d_i(6 to 7); + fb_q <= d_i(5); + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- reload frequency counter according to NF setting + case nf_q is + when "00" => + freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length); + when "01" => + freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length); + when "10" => + freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length); + when others => + null; + end case; + + freq_ff_q <= not freq_ff_q; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Multiplex the source of the LFSR's shift enable + ----------------------------------------------------------------------------- + shift_source_s <= tone3_ff_i + when nf_q = "11" else + freq_ff_q; + + ----------------------------------------------------------------------------- + -- Process rise_edge + -- + -- Purpose: + -- Detect the rising edge of the selected LFSR shift source. + -- + rise_edge: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + shift_source_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + shift_source_q <= shift_source_s; + end if; + end if; + end process rise_edge; + -- + ----------------------------------------------------------------------------- + + -- detect rising edge on shift source + shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1'; + + + ----------------------------------------------------------------------------- + -- Process lfsr + -- + -- Purpose: + -- Implements the LFSR that generates noise. + -- Note: This implementation shifts the register right, i.e. from index + -- 15 towards 0 => bit 15 is the input, bit 0 is the output + -- + -- Tapped bits according to MAME's sn76496.c, implemented in function + -- lfsr_tapped_f. + -- + lfsr: process (clock_i, res_n_i) + + function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is + constant tapped_bits_c : std_logic_vector(0 to 15) + -- tapped bits are 0, 2, 15 + := "1010000000000001"; + variable parity_v : std_logic; + begin + parity_v := '0'; + + for idx in lfsr'low to lfsr'high loop + parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx)); + end loop; + + return parity_v; + end; + + begin + if res_n_i = '0' then + -- reset LFSR to "0000000000000001" + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if we_i and r2_i = '0' then + -- write to noise register + -- -> reset LFSR + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif shift_rise_edge_s then + + -- shift LFSR left towards MSB + for idx in lfsr_q'right-1 downto lfsr_q'left loop + lfsr_q(idx) <= lfsr_q(idx+1); + end loop; + + -- determine input bit + if fb_q = '0' then + -- "Periodic" Noise + -- -> input to LFSR is output + lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left); + else + -- "White" Noise + -- -> input to LFSR is parity of tapped bits + lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q); + end if; + + end if; + + end if; + end if; + end process lfsr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map output of LFSR to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when lfsr_q(0) = '1' else + to_signed( 0, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => noise_o + ); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd new file mode 100644 index 00000000..3658efcc --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_tone.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $ +-- +-- Tone Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_tone is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + ff_o : out std_logic; + tone_o : out signed(0 to 7) + ); + +end sn76489_tone; + +architecture rtl of sn76489_tone is + + signal f_q : std_logic_vector(0 to 9); + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 9); + signal freq_ff_q : std_logic; + + signal freq_s : signed(0 to 1); + + function all_zero(a : in std_logic_vector) return boolean is + variable result_v : boolean; + begin + result_v := true; + + for idx in a'low to a'high loop + if a(idx) /= '0' then + result_v := false; + end if; + end loop; + + return result_v; + end; + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + f_q <= (others => '0'); + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to frequency register + if d_i(0) = '0' then + f_q(0 to 5) <= d_i(2 to 7); + else + f_q(6 to 9) <= d_i(4 to 7); + end if; + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- update counter from frequency register + freq_cnt_q <= unsigned(f_q); + + -- and toggle the frequency flip-flop if enabled + if not all_zero(f_q) then + freq_ff_q <= not freq_ff_q; + else + -- if frequency setting is 0, then keep flip-flop at +1 + freq_ff_q <= '1'; + end if; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map frequency flip-flop to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when freq_ff_q = '1' else + to_signed(-1, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => tone_o + ); + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + ff_o <= freq_ff_q; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd new file mode 100644 index 00000000..c26d0e1a --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/sound/sn76489/sn76489_top.vhd @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $ +-- +-- Chip Toplevel +-- +-- References: +-- +-- * TI Data sheet SN76489.pdf +-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf +-- +-- * John Kortink's article on the SN76489: +-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ +-- +-- * Maxim's "SN76489 notes" in +-- http://www.smspower.org/maxim/docs/SN76489.txt +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ieee; +use ieee.numeric_std.all; + +entity sn76489_top is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + ready_o : out std_logic; + d_i : in std_logic_vector(0 to 7); + aout_o : out signed(0 to 7) + ); + +end sn76489_top; + +architecture struct of sn76489_top is + + signal clk_en_s : boolean; + + signal tone1_we_s, + tone2_we_s, + tone3_we_s, + noise_we_s : boolean; + signal r2_s : std_logic; + + signal tone1_s, + tone2_s, + tone3_s, + noise_s : signed(0 to 7); + + signal tone3_ff_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock Divider + ----------------------------------------------------------------------------- + clock_div_b : entity work.sn76489_clock_div + generic map ( + clock_div_16_g => clock_div_16_g + ) + port map ( + clock_i => clock_i, + clock_en_i => clock_en_i, + res_n_i => res_n_i, + clk_en_o => clk_en_s + ); + + + ----------------------------------------------------------------------------- + -- Latch Control = CPU Interface + ----------------------------------------------------------------------------- + latch_ctrl_b : entity work.sn76489_latch_ctrl + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + ce_n_i => ce_n_i, + we_n_i => we_n_i, + d_i => d_i, + ready_o => ready_o, + tone1_we_o => tone1_we_s, + tone2_we_o => tone2_we_s, + tone3_we_o => tone3_we_s, + noise_we_o => noise_we_s, + r2_o => r2_s + ); + + + ----------------------------------------------------------------------------- + -- Tone Channel 1 + ----------------------------------------------------------------------------- + tone1_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone1_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone1_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 2 + ----------------------------------------------------------------------------- + tone2_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone2_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone2_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 3 + ----------------------------------------------------------------------------- + tone3_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone3_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => tone3_ff_s, + tone_o => tone3_s + ); + + ----------------------------------------------------------------------------- + -- Noise Channel + ----------------------------------------------------------------------------- + noise_b : entity work.sn76489_noise + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => noise_we_s, + d_i => d_i, + r2_i => r2_s, + tone3_ff_i => tone3_ff_s, + noise_o => noise_s + ); + + + aout_o <= tone1_s + tone2_s + tone3_s + noise_s; + +end struct; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/spram.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/spram.vhd new file mode 100644 index 00000000..fa4a1fd7 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/spram.vhd @@ -0,0 +1,84 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + widthad_a : natural; + width_a : natural := 8 + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ttl_175.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ttl_175.vhd new file mode 100644 index 00000000..b6459332 --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ttl_175.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74175 - Quad D-Type Flip-Flops with Clear +-- +-- $Id: ttl_175.vhd,v 1.5 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_175 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic; + por_n_i : in std_logic; + cl_n_i : in std_logic; + d_i : in std_logic_vector(4 downto 1); + q_o : out std_logic_vector(4 downto 1); + q_n_o : out std_logic_vector(4 downto 1); + d_o : out std_logic_vector(4 downto 1); + d_n_o : out std_logic_vector(4 downto 1) + ); + +end ttl_175; + + +architecture rtl of ttl_175 is + + signal flops_q, + flops_s : std_logic_vector(4 downto 1); + +begin + + ----------------------------------------------------------------------------- + -- Process flops + -- + -- Purpose: + -- Implement the sequential elements. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_n_i. + -- + flops: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + flops_q <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + flops_q <= flops_s; + end if; + end process flops; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational logic. + -- + comb: process (flops_q, + cl_n_i, + d_i, + ck_en_i) + begin + -- default assignments + flops_s <= flops_q; + + if cl_n_i = '1' then + if ck_en_i = '1' then + flops_s <= d_i; + end if; + + else + -- pseudo-asynchronous clear + flops_s <= (others => '0'); + end if; + end process comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + q_o <= flops_q; + q_n_o <= not flops_q; + d_o <= flops_s; + d_n_o <= not flops_s; + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ttl_393.vhd b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ttl_393.vhd new file mode 100644 index 00000000..3ef25d4b --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/ttl_393.vhd @@ -0,0 +1,152 @@ +------------------------------------------------------------------------------- +-- +-- TTL 74LS393 - Dual 4-Bit Binary Counter +-- +-- $Id: ttl_393.vhd,v 1.3 2005/10/10 21:59:13 arnim Exp $ +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ttl_393 is + + port ( + ck_i : in std_logic; + ck_en_i : in std_logic_vector(2 downto 1); + por_n_i : in std_logic; + cl_i : in std_logic_vector(2 downto 1); + qa_o : out std_logic_vector(2 downto 1); + qb_o : out std_logic_vector(2 downto 1); + qc_o : out std_logic_vector(2 downto 1); + qd_o : out std_logic_vector(2 downto 1); + da_o : out std_logic_vector(2 downto 1); + db_o : out std_logic_vector(2 downto 1); + dc_o : out std_logic_vector(2 downto 1); + dd_o : out std_logic_vector(2 downto 1) + ); + +end ttl_393; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ttl_393 is + + type cnt_q_t is array (natural range 2 downto 1) of unsigned(3 downto 0); + type cnt_d_t is array (natural range 2 downto 1) of unsigned(4 downto 0); + signal cnt_q : cnt_q_t; + signal cnt_s : cnt_d_t; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the flip-flops. + -- + -- Note: We assume that the sequential elements power-up to the same state + -- as forced into by cl_i. + -- + seq: process (ck_i, por_n_i) + begin + if por_n_i = '0' then + cnt_q(1) <= (others => '0'); + cnt_q(2) <= (others => '0'); + elsif ck_i'event and ck_i = '1' then + cnt_q(1) <= cnt_s(1)(3 downto 0); + cnt_q(2) <= cnt_s(2)(3 downto 0); + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process adder + -- + -- Purpose: + -- Implements the adder. + -- + adder: process (ck_en_i, + cl_i, + cnt_q) + begin + for idx in 2 downto 1 loop + cnt_s(idx) <= '0' & cnt_q(idx); + + if cl_i(idx) = '0' then + if ck_en_i(idx) = '1' then + -- increment upon enable + cnt_s(idx) <= ('0' & cnt_q(idx)) + 1; + end if; + + else + -- pseudo-asynchronous clear + cnt_s(idx) <= (others => '0'); + end if; + end loop; + end process adder; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + qa_o(1) <= cnt_q(1)(0); + qb_o(1) <= cnt_q(1)(1); + qc_o(1) <= cnt_q(1)(2); + qd_o(1) <= cnt_q(1)(3); + qa_o(2) <= cnt_q(2)(0); + qb_o(2) <= cnt_q(2)(1); + qc_o(2) <= cnt_q(2)(2); + qd_o(2) <= cnt_q(2)(3); + da_o(1) <= cnt_s(1)(0); + db_o(1) <= cnt_s(1)(1); + dc_o(1) <= cnt_s(1)(2); + dd_o(1) <= cnt_s(1)(3); + da_o(2) <= cnt_s(2)(0); + db_o(2) <= cnt_s(2)(1); + dc_o(2) <= cnt_s(2)(2); + dd_o(2) <= cnt_s(2)(3); + +end rtl; diff --git a/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/video_mixer.sv b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Ladybug Hardware/Snapjack_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Midway8080.qpf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Midway8080.qpf new file mode 100644 index 00000000..9d9324d0 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/Midway8080.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:56:36 February 09, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "10:56:36 February 09, 2017" + +# Revisions + +PROJECT_REVISION = "Midway8080" +PROJECT_REVISION = "invaders" diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf new file mode 100644 index 00000000..bbfbb296 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf @@ -0,0 +1,164 @@ +# copyright (c) 1991-2005 altera corporation +# your use of altera corporation's design tools, logic functions +# and other software and tools, and its ampp partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the altera program license +# subscription agreement, altera megacore function license +# agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by altera and sold by +# altera or its authorized distributors. please refer to the +# applicable agreement for further details. + + +# the default values for assignments are stored in the file +# invaders_assignment_defaults.qdf +# if this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# altera recommends that you do not modify this file. this +# file is updated automatically by the quartus ii software +# and any changes you make may be lost or overwritten. + + +# project-wide assignments +# ======================== +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +# pin & location assignments +# ========================== + +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 + + +# analysis & synthesis assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY target_top + +# fitter assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name SEARCH_PATH device/cycloneii/ -tag from_archive +set_global_assignment -name SEARCH_PATH pacman/openep3c16/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/cpu/t80/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/io/gamecube/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/io/maple/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/ps2/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/sound/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/component/toys/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/pace/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/pace/stubs/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/pace/video/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/platform/midway8080/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/platform/midway8080/invaders/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/platform/midway8080/invaders/roms/ -tag from_archive +set_global_assignment -name SEARCH_PATH src/target/mist/ -tag from_archive +set_global_assignment -name VERILOG_FILE src/mist/ps2_intf.v +set_global_assignment -name VERILOG_FILE src/mist/osd.v +set_global_assignment -name VERILOG_FILE src/mist/keyboard.v +set_global_assignment -name VHDL_FILE src/Z80.vhd +set_global_assignment -name VERILOG_FILE src/mist/user_io.v +set_global_assignment -name VHDL_FILE src/mist/target_top.vhd +set_global_assignment -name VHDL_FILE src/mist/target_pkg.vhd +set_global_assignment -name VHDL_FILE src/mist/sigma_delta_dac.vhd +set_global_assignment -name VHDL_FILE src/mist/custom_io.vhd +set_global_assignment -name VHDL_FILE src/video_mixer.vhd +set_global_assignment -name VHDL_FILE src/video_controller_pkg_body.vhd +set_global_assignment -name VHDL_FILE src/video_controller_pkg.vhd +set_global_assignment -name VHDL_FILE src/video_controller.vhd +set_global_assignment -name VHDL_FILE src/tilemapctl_e.vhd +set_global_assignment -name VHDL_FILE src/sprom.vhd +set_global_assignment -name VHDL_FILE src/sprite_pkg_body.vhd +set_global_assignment -name VHDL_FILE src/sprite_pkg.vhd +set_global_assignment -name VHDL_FILE src/spram.vhd +set_global_assignment -name VHDL_FILE src/Sound.vhd +set_global_assignment -name VHDL_FILE src/project_pkg.vhd +set_global_assignment -name QIP_FILE src/pllclk_ez.qip +set_global_assignment -name VHDL_FILE src/platform_variant_pkg.vhd +set_global_assignment -name VHDL_FILE src/platform_pkg.vhd +set_global_assignment -name VHDL_FILE src/platform.vhd +set_global_assignment -name VHDL_FILE src/pace_pkg_body.vhd +set_global_assignment -name VHDL_FILE src/pace_pkg.vhd +set_global_assignment -name VHDL_FILE src/pace.vhd +set_global_assignment -name VHDL_FILE src/invaders_audio.vhd +set_global_assignment -name VHDL_FILE src/Inputs.VHD +set_global_assignment -name VHDL_FILE src/InputMapper.VHDL +set_global_assignment -name VHDL_FILE src/Graphics.VHD +set_global_assignment -name VHDL_FILE src/dpram_1r1w.vhd +set_global_assignment -name VHDL_FILE src/dpram.vhd +set_global_assignment -name VHDL_FILE src/clk_div.vhd +set_global_assignment -name VHDL_FILE src/bitmapctl_e.vhd +set_global_assignment -name VHDL_FILE src/bitmapctl.vhd +set_global_assignment -name VHDL_FILE src/altera_mem.vhd +set_global_assignment -name VHDL_FILE src/ps2kbd.vhd +set_global_assignment -name VHDL_FILE src/ps2kbd_pkg.vhd +set_global_assignment -name VHDL_FILE src/T80_Pack.vhd +set_global_assignment -name VHDL_FILE src/T80se.vhd +set_global_assignment -name VHDL_FILE src/T80.vhd +set_global_assignment -name VHDL_FILE src/T80_ALU.vhd +set_global_assignment -name VHDL_FILE src/T80_Reg.vhd +set_global_assignment -name VHDL_FILE src/T80_MCode.vhd +set_global_assignment -name QIP_FILE src/mist/pll27.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/README.txt b/Arcade/Midway8080 Hardware/Midway8080_MiST/README.txt new file mode 100644 index 00000000..59855f77 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/README.txt @@ -0,0 +1,22 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Space Invaders port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of MIDWAY8080 hardware +--------------------------------------------------------------------------------- +-- +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Galaxy_Wars(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Galaxy_Wars(Midway8080).rbf new file mode 100644 index 00000000..a77e6f8d Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Galaxy_Wars(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Lunar_Rescue(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Lunar_Rescue(Midway8080).rbf new file mode 100644 index 00000000..195e9533 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Lunar_Rescue(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Attack_II(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Attack_II(Midway8080).rbf new file mode 100644 index 00000000..ed1a4415 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Attack_II(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Invaders(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Invaders(Midway8080).rbf new file mode 100644 index 00000000..ab3fee8e Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Invaders(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Invaders_Deluxe(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Invaders_Deluxe(Midway8080).rbf new file mode 100644 index 00000000..37be9127 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Invaders_Deluxe(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Laser(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Laser(Midway8080).rbf new file mode 100644 index 00000000..5c3f030d Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Space_Laser(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Super_Earth_Invasion(Midway8080).rbf b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Super_Earth_Invasion(Midway8080).rbf new file mode 100644 index 00000000..30420d93 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/Release/Super_Earth_Invasion(Midway8080).rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/clean.bat b/Arcade/Midway8080 Hardware/Midway8080_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/readme.md b/Arcade/Midway8080 Hardware/Midway8080_MiST/readme.md new file mode 100644 index 00000000..dd48826a --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/readme.md @@ -0,0 +1,19 @@ +Midway 8080 Arcade Platform for Mist FPGA + +- with OSD +- Keyboard/Joystick Support +- only VGA Supported + + + +Following Games currently working: + +Space Invaders +Space Invaders 2 +Super Earth Invasion +Lunar Rescue +Space Laser +Galaxy Wars +Space Attack II + +See File platform_variant_pkg.vhd diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/280zzzap.hex b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/280zzzap.hex new file mode 100644 index 00000000..65555ea7 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/280zzzap.hex @@ -0,0 +1,194 @@ +:020000040000FA +:200000000000AFD305C36400F5C5D50E00C39E06F5C5D50E01C39E06E3D5C5F5E925302059 +:20002000E1F1C1D1E1C93500C3160F05B4041404E37E23E3CD910F77DF215E207E23B6E6BA +:200040001FCA5D0001FF1DCD6201215E207ECD5E0F237ECD5E0FE701FF1DC3620101001D93 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new file mode 100644 index 00000000..6ed65a9c Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609f.bin differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609g.bin b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609g.bin new file mode 100644 index 00000000..93a4839f Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609g.bin differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609h.bin b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609h.bin new file mode 100644 index 00000000..e7268c49 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Gunfight/7609h.bin differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Midway8080.txt b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Midway8080.txt new file mode 100644 index 00000000..13c51004 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/Midway8080.txt @@ -0,0 +1,1639 @@ + +ROM_START( searthin ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "earthinv.h", 0x0000, 0x0800, CRC(58a750c8) SHA1(90bfa4ea06f38e67fe4286d37d151632439249d2) ) + ROM_LOAD( "earthinv.g", 0x0800, 0x0800, CRC(b91742f1) SHA1(8d9ca92405fbaf1d5a7138d400986616378d061e) ) + ROM_LOAD( "earthinv.f", 0x1000, 0x0800, CRC(4acbbc60) SHA1(b8c1efb4251a1e690ff6936ec956d6f66136a085) ) + ROM_LOAD( "earthinv.e", 0x1800, 0x0800, CRC(df397b12) SHA1(e7e8c080cb6baf342ec637532e05d38129ae73cf) ) +ROM_END + +ROM_START( searthina ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "unkh.h1", 0x0000, 0x0400, CRC(272b9bf3) SHA1(dd57d6a88d42024a39640931114107b547b4c520) ) + ROM_LOAD( "unkg.g1", 0x0400, 0x0400, CRC(61bb6101) SHA1(8fc8bbd8ac93d239e0cf0e4881f709860ec2c973) ) + ROM_LOAD( "unkf.f1", 0x0800, 0x0400, CRC(2a8d9cd5) SHA1(7948d79b326e729bcb629607c8797156ff9fb0e8) ) + ROM_LOAD( "unke.e1", 0x0c00, 0x0400, CRC(1938d349) SHA1(3bd2a0deb126cf2e22bc3cb53e9a59c3875be260) ) + ROM_LOAD( "unkd.d1", 0x1000, 0x0400, CRC(9bc2ab88) SHA1(1e9f3b780135827d16ba25978382b097a8110828) ) + ROM_LOAD( "unkc.c1", 0x1400, 0x0400, CRC(d4e2dada) SHA1(e98271212fc89e240fdf97d292edd17dc8dd4191) ) + ROM_LOAD( "unkb.b1", 0x1800, 0x0400, CRC(ab645a9c) SHA1(9c286f8a031a8babfb8e9b594e05e133c338b342) ) + ROM_LOAD( "unka.a1", 0x1c00, 0x0400, CRC(4b65bd7c) SHA1(3931f9f5b0e3339ab484eee14473d3a474935fd9) ) +ROM_END + +ROM_START( searthie ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "searthie.h", 0x0000, 0x0800, CRC(92b08b91) SHA1(4cebb70735e5231717619c7b8e5d3080694338b7) ) + ROM_LOAD( "searthie.g", 0x0800, 0x0800, CRC(23e24bcc) SHA1(a62e8422554f7db34796d4fb1c01e8ddebc7e978) ) + ROM_LOAD( "searthie.f", 0x1000, 0x0800, CRC(8700286a) SHA1(e0a3c099bc60e70bc9a6c0325944454d9d26428f) ) + ROM_LOAD( "searthie.e", 0x1800, 0x0800, CRC(baf949b0) SHA1(bfda97a3ef59fcdf87814afc6918507190c3e315) ) +ROM_END + +ROM_START( invadrmr ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "11.1t", 0x0000, 0x0400, CRC(389d44b6) SHA1(5d2581b8bc0da918ce57cf319e06b5b31989c681) ) + ROM_LOAD( "sv02.1p", 0x0400, 0x0400, CRC(0e159534) SHA1(94b2015a9d38ca738705b8d024a79fd2f9855b98) ) + ROM_LOAD( "20.1n", 0x0800, 0x0400, CRC(805b04f0) SHA1(209f42dfde1593699ccf3755e9267d425416d910) ) + ROM_LOAD( "sv04.1j", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) + ROM_LOAD( "13.1h", 0x1800, 0x0400, CRC(76b4a6ea) SHA1(076f8d12ba7ebe66b83a40d9a848075627776554) ) + ROM_LOAD( "sv06.1g", 0x1c00, 0x0400, CRC(2c68e0b4) SHA1(a5e5357120102ad32792bf3ef6362f45b7ba7070) ) +ROM_END + +ROM_START( claybust ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "0.a1", 0x0000, 0x0400, CRC(90810582) SHA1(a5c3655bae6f92a3cd0eae3a5a3c25e414d4fdf0) ) + ROM_LOAD( "1.a2", 0x0400, 0x0400, CRC(5ce6fb0e) SHA1(19fa3fbc0dd7e0fa4fffc005ded5a814c3b48f2d) ) + ROM_LOAD( "2.a4", 0x0800, 0x0400, CRC(d4c1d523) SHA1(1a4785095caa8200d7e1d8d53a93c8e298f52c65) ) + ROM_LOAD( "3.a5", 0x0c00, 0x0400, CRC(1ca00825) SHA1(74633a4903a51f1eebdd09679597dbe86db2e001) ) + ROM_LOAD( "4.a6", 0x1000, 0x0400, CRC(09a21120) SHA1(e976d2c173c649e51b032bc5dad54f006864155c) ) + ROM_LOAD( "5.a8", 0x1400, 0x0400, CRC(92cd4da8) SHA1(217e00012a52c479bf0b0cf37ce556387755740d) ) +ROM_END + +ROM_START( gunchamp ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "251.a1", 0x0000, 0x0400, CRC(f27a8c1e) SHA1(510debd1ac2c0986f99c217e3078208a39d7837c) ) + ROM_LOAD( "252.a2", 0x0400, 0x0400, CRC(d53b8f91) SHA1(56919f4c88fb3b5c23b5365f0866698bfceb2762) ) + ROM_LOAD( "253.a4", 0x0800, 0x0400, CRC(9ef35c6c) SHA1(95bda3e2cdd50f7ac989c581481bad5f1ef2992f) ) + ROM_LOAD( "254.a5", 0x0c00, 0x0400, CRC(ba5b562d) SHA1(47819d7e5ef3700e700a5f2faa9537bc2199561c) ) + ROM_LOAD( "255.a6", 0x1000, 0x0400, CRC(00ea8293) SHA1(9c921fa4bafc36fc16a3f5f8588887342936d433) ) + ROM_LOAD( "256.a8", 0x1400, 0x0400, CRC(e271150c) SHA1(36d0c0c1335036b4a994e8a38904adcf74161c59) ) + ROM_LOAD( "257.a9", 0x1800, 0x0400, CRC(0da5d9ad) SHA1(c87c6ab248bfd2b75f070343a8f7fcbaed13f4e3) ) + ROM_LOAD( "258.a10", 0x1c00, 0x0400, CRC(471d4052) SHA1(c8ccda2eba44c2ab49f5fc2874fe70c2bdae35d3) ) +ROM_END + +ROM_START( spaceatt ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "h", 0x0000, 0x0400, CRC(d0c32d72) SHA1(b3bd950b1ba940fbeb5d95e55113ed8f4c311434) ) // == SV01 + ROM_LOAD( "sv02.bin", 0x0400, 0x0400, CRC(0e159534) SHA1(94b2015a9d38ca738705b8d024a79fd2f9855b98) ) // == SV02 + ROM_LOAD( "f", 0x0800, 0x0400, CRC(483e651e) SHA1(ae795ee3bc53ac3936f6cf2c72cca7a890783513) ) // == SV10 + ROM_LOAD( "c", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) // == SV04 + ROM_LOAD( "b", 0x1800, 0x0400, CRC(6fc782aa) SHA1(0275adbeec455e146f4443b0b836b1171436b79b) ) + ROM_LOAD( "a", 0x1c00, 0x0400, CRC(211ac4a3) SHA1(e08e90a4e77cfa30400626a484c9f37c87ea13f9) ) +ROM_END + +/* SPACE ATTACK set is from Video Game GmbH - 1010 A / Top board shows Video-Games - 6302 LICH - 1034 + Roms are set up as 1k bproms (82S137) and data is 1 rom top 4 bits, another bottom 4. This data once assembled matches original spaceatt set */ +ROM_START( spaceattbp ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROMX_LOAD( "06e.bin", 0x0000, 0x0400, CRC(68301d05) SHA1(b0c33a982b42378da828281e74356d58fbea1d86), ROM_NIBBLE | ROM_SHIFT_NIBBLE_HI ) + ROMX_LOAD( "12l.bin", 0x0000, 0x0400, CRC(c5a5228f) SHA1(7861b5567d44e972d728551d47aab9b92d71ffc7), ROM_NIBBLE | ROM_SHIFT_NIBBLE_LO ) + ROMX_LOAD( "05de.bin", 0x0400, 0x0400, CRC(42032c14) SHA1(753948e7f52b88655c894b48d419b76de07c14f2), ROM_NIBBLE | ROM_SHIFT_NIBBLE_HI ) + ROMX_LOAD( "11hl.bin", 0x0400, 0x0400, CRC(d5d3811a) SHA1(7d2d983fa88b0349a90a6331ca3e18583125d21e), ROM_NIBBLE | ROM_SHIFT_NIBBLE_LO ) + ROMX_LOAD( "04d.bin", 0x0800, 0x0400, CRC(5f5e540c) SHA1(9092794a878494dbe34c2f05a212ff7b9d00fc55), ROM_NIBBLE | ROM_SHIFT_NIBBLE_HI ) + ROMX_LOAD( "10h.bin", 0x0800, 0x0400, CRC(9d5ef6f1) SHA1(ef584678373375a7f13307d7c4597639a5f6010e), ROM_NIBBLE | ROM_SHIFT_NIBBLE_LO ) + ROMX_LOAD( "03b.bin", 0x1400, 0x0400, CRC(89e13008) SHA1(1ad82ae0607af27925b42758f8c86a0e89079620), ROM_NIBBLE | ROM_SHIFT_NIBBLE_HI ) + ROMX_LOAD( "09g.bin", 0x1400, 0x0400, CRC(c16f5503) SHA1(cf36beac472c5c405342193b7ef434d32b37a4a8), ROM_NIBBLE | ROM_SHIFT_NIBBLE_LO ) + ROMX_LOAD( "02ab.bin", 0x1800, 0x0400, CRC(ffa166c2) SHA1(10496fcbb272130cc200dfb1886808559be8d6ea), ROM_NIBBLE | ROM_SHIFT_NIBBLE_HI ) + ROMX_LOAD( "08f.bin", 0x1800, 0x0400, CRC(b5fa1a2b) SHA1(7eab1cb9a9f95520a37ee4fb2b246ef072dedcbd), ROM_NIBBLE | ROM_SHIFT_NIBBLE_LO ) + ROMX_LOAD( "01a.bin", 0x1c00, 0x0400, CRC(44f8e99c) SHA1(9adecdadb16edaebde02892e30f9f87fb98f4ae1), ROM_NIBBLE | ROM_SHIFT_NIBBLE_HI ) + ROMX_LOAD( "07ef.bin", 0x1c00, 0x0400, CRC(9560880d) SHA1(866d6c3714b939814ce48707be53a69ef8355b34), ROM_NIBBLE | ROM_SHIFT_NIBBLE_LO ) +ROM_END + +/* SPACE ATTACK set is from Video Games GmbH - Board Typ 1010 C / Top board shows Video-Games - 6302 LICH - 1034B + Contains same data as spaceatt but with added 00 fill to make larger roms (b+a=E1, 00fill+c=F1, f+00fill=G1, h+sv02=H1) */ +ROM_START( spaceatt2k ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "H1.bin", 0x0000, 0x0800, CRC(734f5ad8) SHA1(ff6200af4c9110d8181249cbcef1a8a40fa40b7f) ) + ROM_LOAD( "G1.bin", 0x0800, 0x0800, CRC(6bfaca4a) SHA1(16f48649b531bdef8c2d1446c429b5f414524350) ) + ROM_LOAD( "F1.bin", 0x1000, 0x0800, CRC(0ccead96) SHA1(537aef03468f63c5b9e11dd61e253f7ae17d9743) ) + ROM_LOAD( "E1.bin", 0x1800, 0x0800, CRC(19971ca7) SHA1(373900e6796aa681f35158e2c4c7665574990906) ) +ROM_END + +ROM_START( spaceat2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "spaceatt.h", 0x0000, 0x0800, CRC(a31d0756) SHA1(2b76929654ed0b180091348546dac29fc6e5438e) ) + ROM_LOAD( "spaceatt.g", 0x0800, 0x0800, CRC(f41241f7) SHA1(d93cead75922510075433849c4f7099279eafc18) ) + ROM_LOAD( "spaceatt.f", 0x1000, 0x0800, CRC(4c060223) SHA1(957e75a978aa600627399061cae0a6525e92ad11) ) + ROM_LOAD( "spaceatt.e", 0x1800, 0x0800, CRC(7cf6f604) SHA1(469557de15178c4b2d686e5724e1006f7c20d7a4) ) +ROM_END + +ROM_START( cosmicin ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "CN7472N-7921.bin", 0x0000, 0x0800, CRC(734f5ad8) SHA1(ff6200af4c9110d8181249cbcef1a8a40fa40b7f) ) + ROM_LOAD( "CN7471N-7918.bin", 0x0800, 0x0800, CRC(6bfaca4a) SHA1(16f48649b531bdef8c2d1446c429b5f414524350) ) + ROM_LOAD( "CN7470N-7918.bin", 0x1000, 0x0800, CRC(0ccead96) SHA1(537aef03468f63c5b9e11dd61e253f7ae17d9743) ) + ROM_LOAD( "CN7469N-7921.bin", 0x1800, 0x0800, CRC(5733048c) SHA1(e9197925396b723f5dda4653238e6e1ea287fdae) ) +ROM_END + +ROM_START( galmonst ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "h.5m", 0x0000, 0x0400, CRC(8a0395e9) SHA1(f456aaa0301a1d0f3f9f45cbe39c5ff14909ecd3) ) + ROM_LOAD( "g.5n", 0x0400, 0x0400, CRC(6183ed16) SHA1(8e0bc13cafa237daa5fdeda9a5d6df8f491eabc2) ) + ROM_LOAD( "f.5p", 0x0800, 0x0400, CRC(b6047fdd) SHA1(bc324a9bf7829a2c2bb2bbf965d64272b0d07223) ) + ROM_LOAD( "c.5t", 0x1400, 0x0400, CRC(e88e8c96) SHA1(43108ddb328914c68977c7c49b4c1f71073ca36b) ) + ROM_LOAD( "b.5u", 0x1800, 0x0400, CRC(34678b80) SHA1(17f01facb3272c963a8bca290c4ca36411b8de31) ) + ROM_LOAD( "a.5v", 0x1c00, 0x0400, CRC(05a6806b) SHA1(ea884110d0ea6463801cbc2f87ce9c4921b49e33) ) +ROM_END + +ROM_START( spacecom ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1f.ic67", 0x0000, 0x0400, BAD_DUMP CRC(703f2cbe) SHA1(b183f9fbedd8658399555c0ba21ecab6370e86cb) ) + ROM_LOAD( "2g.ic82", 0x0400, 0x0400, CRC(7269b719) SHA1(6fd5879a6f2a5b1d38c7f00996037418df9491d3) ) + ROM_LOAD( "3f.ic68", 0x0800, 0x0400, CRC(6badac4f) SHA1(7b998d8fb21d143f26d605fe2a7dbbe1cf65210f) ) + ROM_LOAD( "4g.ic83", 0x0c00, 0x0400, CRC(75b59ea7) SHA1(e00eb4a9cf662c84e18fc9efc29cedebf0c5af67) ) + ROM_LOAD( "5f.ic69", 0x1000, 0x0400, CRC(84b61117) SHA1(3e41ff74ad02a7da4bbc22f3b84917eec067bbca) ) + ROM_LOAD( "6g.ic84", 0x1400, 0x0400, CRC(de383625) SHA1(7ec0d7171e771c4b43e026f3f50a88d8ab2236bb) ) + ROM_LOAD( "7f.ic70", 0x1800, 0x0400, CRC(5a23dbc8) SHA1(4d193bb7b38fb7ccd57d2c72463a3fe123dbca58) ) + ROM_LOAD( "8g.ic85", 0x1c00, 0x0400, CRC(a5a467e3) SHA1(ef591059e55d21f14baa8af1f1324a9bc2ada8c4) ) +ROM_END + +ROM_START( sinvzen ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.bin", 0x0000, 0x0400, CRC(9b0da779) SHA1(a52ccdb252eb69c497aa5eafb35d7f25a311b44e) ) + ROM_LOAD( "2.bin", 0x0400, 0x0400, CRC(9858ccab) SHA1(5ad8e5ef0d95779f0e513634b97bc330c9269ce4) ) + ROM_LOAD( "3.bin", 0x0800, 0x0400, CRC(a1cc38b5) SHA1(45fc9466b548d511b8174f6f3a4783164dd59489) ) + ROM_LOAD( "4.bin", 0x0c00, 0x0400, CRC(1f2db7a8) SHA1(354ad155743f724f2bebcab422f1ef96cb57c683) ) + ROM_LOAD( "5.bin", 0x1000, 0x0400, CRC(9b505fcd) SHA1(7461b7087d31dbe09f7b3078584ccaa2c9122c95) ) + ROM_LOAD( "6.bin", 0x1400, 0x0400, CRC(de0ca0ae) SHA1(a15d1218361839a2a2bf8da3f78d81621251fe1c) ) + ROM_LOAD( "7.bin", 0x1800, 0x0400, CRC(25a296f6) SHA1(37df98384c1513f0e33a350dfcaa99655f91c9ba) ) + ROM_LOAD( "8.bin", 0x1c00, 0x0400, CRC(f4bc4a98) SHA1(bff3806750a3695a136f398c7dbb69a0b7daa88a) ) +ROM_END + +ROM_START( sinvemag ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sv01.36", 0x0000, 0x0400, CRC(86bb8cb6) SHA1(a75648e7f2446c756d86624b15d387d25ce47b66) ) // sldh - == SV0H + ROM_LOAD( "emag_si.b", 0x0400, 0x0400, CRC(febe6d1a) SHA1(e1c3a24b4fa5862107ada1f9d7249466e8c3f06a) ) + ROM_LOAD( "emag_si.c", 0x0800, 0x0400, CRC(aafb24f7) SHA1(6718cdfae09f77d735be5145b9d202a73d8ed9db) ) + ROM_LOAD( "emag_si.d", 0x1400, 0x0400, CRC(68c4b9da) SHA1(8953dc0427b09b71bd763e65caa7deaca09a15da) ) + ROM_LOAD( "emag_si.e", 0x1800, 0x0400, CRC(c4e80586) SHA1(3d427d5a2eea3c911ec7bd055e06e6747ce5e84d) ) + ROM_LOAD( "emag_si.f", 0x1c00, 0x0400, CRC(077f5ef2) SHA1(625de6839073ac4c904f949efc1b2e0afea5d676) ) +ROM_END + +ROM_START( tst_invd ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "test.h", 0x0000, 0x0800, CRC(f86a2eea) SHA1(4a72ff01f3e6d16bbe9bf7f123cd98895bfbed9a) ) /* The Test ROM */ + ROM_LOAD( "invaders.g", 0x0800, 0x0800, CRC(6bfaca4a) SHA1(16f48649b531bdef8c2d1446c429b5f414524350) ) + ROM_LOAD( "invaders.f", 0x1000, 0x0800, CRC(0ccead96) SHA1(537aef03468f63c5b9e11dd61e253f7ae17d9743) ) + ROM_LOAD( "invaders.e", 0x1800, 0x0800, CRC(14e538b0) SHA1(1d6ca0c99f9df71e2990b610deb9d7da0125e2d8) ) +ROM_END + +ROM_START( alieninv ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "alieninv.h", 0x0000, 0x0800, CRC(6ad601c3) SHA1(9fc88698f98ce43992a5044d28d3e19751f82772) ) + ROM_LOAD( "alieninv.g", 0x0800, 0x0800, CRC(c6bb6fb3) SHA1(01a12163309f967dcffce19890b1e0d079021fc2) ) + ROM_LOAD( "alieninv.f", 0x1000, 0x0800, CRC(1d2ff324) SHA1(209766a981fdd3a68e36da3d8122a244c883cae7) ) + ROM_LOAD( "alieninv.e", 0x1800, 0x0800, CRC(2f2e6791) SHA1(08a1f17bcfec598182386f1c43e4fc7b476212de) ) +ROM_END + +ROM_START( alieninvp2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1h.bin", 0x0000, 0x0800, CRC(c46df7f4) SHA1(eec34b3d5585bae03c7b80585daaa05ddfcc2164) ) + ROM_LOAD( "1g.bin", 0x0800, 0x0800, CRC(4b1112d6) SHA1(b693667656e5d8f44eeb2ea730f4d4db436da579) ) + ROM_LOAD( "1f.bin", 0x1000, 0x0800, CRC(adca18a5) SHA1(7e02651692113db31fd469868ae5ffdb0f941ecf) ) + ROM_LOAD( "1e.bin", 0x1800, 0x0800, CRC(0449cb52) SHA1(8adcb7cd4492fa6649d9ee81172d8dff56621d64) ) +ROM_END + +ROM_START( sitv1 ) // rev 1 + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "tv01.s1", 0x0000, 0x0800, CRC(9f37b146) SHA1(0b7ef79dbc3de3beeae3bf222d086b60249d429f) ) + ROM_LOAD( "tv02.rp1", 0x0800, 0x0800, CRC(3c759a90) SHA1(d847d592dee592b1d3a575c21d89eaf3f7f6ae1b) ) + ROM_LOAD( "tv03.n1", 0x1000, 0x0800, CRC(0ad3657f) SHA1(a501f316535c50f7d7a20ef8e6dede1526a3f2a8) ) + ROM_LOAD( "tv04.m1", 0x1800, 0x0800, CRC(cd2c67f6) SHA1(60f9d8fe2d36ff589277b607f07c1edc917c755c) ) +ROM_END + +ROM_START( sitv ) // rev 2, minor bug fixes of sitv1; delay when writing to sound latch 0x05, and another unknown change + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "tv0h.s1", 0x0000, 0x0800, CRC(fef18aad) SHA1(043edeefe6a6d4934bd384eafea19326de1dbeec) ) + ROM_LOAD( "tv02.rp1", 0x0800, 0x0800, CRC(3c759a90) SHA1(d847d592dee592b1d3a575c21d89eaf3f7f6ae1b) ) + ROM_LOAD( "tv03.n1", 0x1000, 0x0800, CRC(0ad3657f) SHA1(a501f316535c50f7d7a20ef8e6dede1526a3f2a8) ) + ROM_LOAD( "tv04.m1", 0x1800, 0x0800, CRC(cd2c67f6) SHA1(60f9d8fe2d36ff589277b607f07c1edc917c755c) ) +ROM_END + +ROM_START( sicv ) // likely not the first sicv version... + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "cv17.36", 0x0000, 0x0800, CRC(3dfbe9e6) SHA1(26487df7fa0bbd0b9b7f74347c4b9318b0a73b89) ) + ROM_LOAD( "cv18.35", 0x0800, 0x0800, CRC(bc3c82bf) SHA1(33e39fc97bd46699be1f9b9741a86f433efdc911) ) + ROM_LOAD( "cv19.34", 0x1000, 0x0800, CRC(d202b41c) SHA1(868fe938ef768655c894ec95b7d9a81bf21f69ca) ) + ROM_LOAD( "cv20.33", 0x1800, 0x0800, CRC(c74ee7b6) SHA1(4f52db274a2d4433ab67c099ee805e8eb8516c0f) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "cv01.1", 0x0000, 0x0400, CRC(037e16ac) SHA1(d585030aaff428330c91ae94d7cd5c96ebdd67dd) ) + ROM_LOAD( "cv02.2", 0x0400, 0x0400, CRC(8263da38) SHA1(2e7c769d129e6f8a1a31eba1e02777bb94ac32b2) ) +ROM_END + +ROM_START( sicv1 ) // Original Taito board AA017742B - data match for sicv, just smaller program roms (2708s vs. 2716s) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "cv11.s1", 0x0000, 0x0400, CRC(309d4582) SHA1(e60a1a696111502c115ee00d84cd418c85aba9af) ) + ROM_LOAD( "cv12.r1", 0x0400, 0x0400, CRC(70153e09) SHA1(b75068b7738aa232f75272c539fca04b3d0c2c4a) ) + ROM_LOAD( "cv13.np1", 0x0800, 0x0400, CRC(2ca24fee) SHA1(4b516ebd5a777b001443159233d89fc0a331f756) ) + ROM_FILL( 0x0c00, 0x0400, 0xff ) /* rom socket at M1 is unpopulated */ + ROM_FILL( 0x1000, 0x0400, 0xff ) /* rom socket at L1 is unpopulated */ + ROM_LOAD( "cv14.jk1", 0x1400, 0x0400, CRC(556d9a97) SHA1(fb792e981658d79d1c801b01f06345c237e9e803) ) + ROM_LOAD( "cv15.i1", 0x1800, 0x0400, CRC(ac520cf5) SHA1(47281256083d64a2754b2045c252e74fe5b71153) ) + ROM_LOAD( "cv16.g1", 0x1c00, 0x0400, CRC(285cfb59) SHA1(53eab8ed07dc9ca107e2e91b4556b9424a073530) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "cv01.1", 0x0000, 0x0400, CRC(037e16ac) SHA1(d585030aaff428330c91ae94d7cd5c96ebdd67dd) ) + ROM_LOAD( "cv02.2", 0x0400, 0x0400, CRC(8263da38) SHA1(2e7c769d129e6f8a1a31eba1e02777bb94ac32b2) ) +ROM_END + +ROM_START( sisv1 ) // rev 1, this version may or may not really exist (may have been test/prototype only?) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sv01.36", 0x0000, 0x0400, CRC(d0c32d72) SHA1(b3bd950b1ba940fbeb5d95e55113ed8f4c311434) ) + ROM_LOAD( "sv02.35", 0x0400, 0x0400, CRC(0e159534) SHA1(94b2015a9d38ca738705b8d024a79fd2f9855b98) ) + ROM_LOAD( "sv03.34", 0x0800, 0x0400, NO_DUMP ) + ROM_LOAD( "sv04.31", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) + ROM_LOAD( "sv05.42", 0x1800, 0x0400, NO_DUMP ) + ROM_LOAD( "sv06.41", 0x1c00, 0x0400, CRC(2c68e0b4) SHA1(a5e5357120102ad32792bf3ef6362f45b7ba7070) ) +ROM_END + +ROM_START( sisv2 ) // rev 2 + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sv01.36", 0x0000, 0x0400, CRC(d0c32d72) SHA1(b3bd950b1ba940fbeb5d95e55113ed8f4c311434) ) + ROM_LOAD( "sv02.35", 0x0400, 0x0400, CRC(0e159534) SHA1(94b2015a9d38ca738705b8d024a79fd2f9855b98) ) + ROM_LOAD( "sv10.34", 0x0800, 0x0400, CRC(483e651e) SHA1(ae795ee3bc53ac3936f6cf2c72cca7a890783513) ) + ROM_LOAD( "sv04.31", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) + ROM_LOAD( "sv09.42", 0x1800, 0x0400, CRC(cd80b13f) SHA1(0f4b9537b99fe3cdeebe525efb1869a1be0bc704) ) + ROM_LOAD( "sv06.41", 0x1c00, 0x0400, CRC(2c68e0b4) SHA1(a5e5357120102ad32792bf3ef6362f45b7ba7070) ) +ROM_END + +ROM_START( sisv3 ) // rev 3 + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sv0h.36", 0x0000, 0x0400, CRC(86bb8cb6) SHA1(a75648e7f2446c756d86624b15d387d25ce47b66) ) + ROM_LOAD( "sv02.35", 0x0400, 0x0400, CRC(0e159534) SHA1(94b2015a9d38ca738705b8d024a79fd2f9855b98) ) + ROM_LOAD( "sv10.34", 0x0800, 0x0400, CRC(483e651e) SHA1(ae795ee3bc53ac3936f6cf2c72cca7a890783513) ) + ROM_LOAD( "sv04.31", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) + ROM_LOAD( "sv09.42", 0x1800, 0x0400, CRC(cd80b13f) SHA1(0f4b9537b99fe3cdeebe525efb1869a1be0bc704) ) + ROM_LOAD( "sv06.41", 0x1c00, 0x0400, CRC(2c68e0b4) SHA1(a5e5357120102ad32792bf3ef6362f45b7ba7070) ) +ROM_END + +ROM_START( sisv ) // rev 4, with 5-digit scoring + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sv0h.36", 0x0000, 0x0400, CRC(86bb8cb6) SHA1(a75648e7f2446c756d86624b15d387d25ce47b66) ) + ROM_LOAD( "sv11.35", 0x0400, 0x0400, CRC(febe6d1a) SHA1(e1c3a24b4fa5862107ada1f9d7249466e8c3f06a) ) + ROM_LOAD( "sv12.34", 0x0800, 0x0400, CRC(a08e7202) SHA1(de9f7c851d1b894915e720cfc5d794cdb31752f6) ) + ROM_LOAD( "sv04.31", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) + ROM_LOAD( "sv13.42", 0x1800, 0x0400, CRC(a9011634) SHA1(1f1369ecb02078042cfdf17a497b8dda6dd23793) ) + ROM_LOAD( "sv14.41", 0x1c00, 0x0400, CRC(58730370) SHA1(13dc806bcecd2d6089a85dd710ac2869413f7475) ) +ROM_END + +ROM_START( spacerng ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sr1.u36", 0x0000, 0x0800, CRC(b984f52d) SHA1(fdc8b249c0b65339977f91b674bdcb435aa99474) ) + ROM_LOAD( "sr2.u35", 0x0800, 0x0800, CRC(4b4f07e6) SHA1(408dcdae3e80a09584d8ebd6491bc90c4def1fcf) ) + ROM_LOAD( "sr3.u34", 0x1000, 0x0800, CRC(edc28ba9) SHA1(c96668f709d3fa0b97a6b118614e9c139f8f54cc) ) + ROM_LOAD( "sr4.u33", 0x1800, 0x0800, CRC(a95f559f) SHA1(f597c7af96a9d039fd8e54d976d68a065f6bf0c8) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv */ + // NOTE: SISV (L-shaped boardset) was not supposed to HAVE color proms and hence they are removed. Maybe this is the correct set for these? + ROM_LOAD( "cv01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) // sldh + ROM_LOAD( "cv02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) // sldh +ROM_END + +ROM_START( spceking ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "invaders.h", 0x0000, 0x0800, CRC(734f5ad8) SHA1(ff6200af4c9110d8181249cbcef1a8a40fa40b7f) ) + ROM_LOAD( "spcekng2", 0x0800, 0x0800, CRC(96dcdd42) SHA1(e18d7ffca92e863ef40e235b2be973d8c5879fdb) ) + ROM_LOAD( "spcekng3", 0x1000, 0x0800, CRC(95fc96ad) SHA1(38175edad0e538a1561cec8f7613f15ae274dd14) ) + ROM_LOAD( "spcekng4", 0x1800, 0x0800, CRC(54170ada) SHA1(1e8b3774355ec0d448f04805a917f4c1fe64bceb) ) +ROM_END + +ROM_START( spcewars ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sanritsu.1", 0x0000, 0x0400, CRC(ca331679) SHA1(5c362c3d1c721d293bcddbef4033533769c8f0e0) ) + ROM_LOAD( "sanritsu.2", 0x0400, 0x0400, CRC(48dc791c) SHA1(91a98205c83ca38961e6ba2ac43a41e6e8bc2675) ) + ROM_LOAD( "ic35.bin", 0x0800, 0x0800, CRC(40c2d55b) SHA1(b641b63046d242ad23911143ed840011fc98eaff) ) + ROM_LOAD( "sanritsu.5", 0x1000, 0x0400, CRC(77475431) SHA1(15a04a2655847ee462be65d1065d643c872bb47c) ) + ROM_LOAD( "sanritsu.6", 0x1400, 0x0400, CRC(392ef82c) SHA1(77c98c11ee727ed3ed6e118f13d97aabdb555540) ) + ROM_LOAD( "sanritsu.7", 0x1800, 0x0400, CRC(b3a93df8) SHA1(3afc96814149d4d5343fe06eac09f808384d02c4) ) + ROM_LOAD( "sanritsu.8", 0x1c00, 0x0400, CRC(64fdc3e1) SHA1(c3c278bc236ced7fc85e1a9b018e80be6ab33402) ) + ROM_LOAD( "sanritsu.9", 0x4000, 0x0400, CRC(b2f29601) SHA1(ce855e312f50df7a74682974803cb4f9b2d184f3) ) +ROM_END + +ROM_START( spacewr3 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ic36.bin", 0x0000, 0x0800, CRC(9e30f88a) SHA1(314dfb2920d9b43b977cc19e40ac315e6933c3b9) ) + ROM_LOAD( "ic35.bin", 0x0800, 0x0800, CRC(40c2d55b) SHA1(b641b63046d242ad23911143ed840011fc98eaff) ) + ROM_LOAD( "ic34.bin", 0x1000, 0x0800, CRC(b435f021) SHA1(2d0d813b99d571b53770fa878a1f82ca67827caa) ) + ROM_LOAD( "ic33.bin", 0x1800, 0x0800, CRC(cbdc6fe8) SHA1(63038ea09d320c54e3d1cf7f043c17bba71bf13c) ) + ROM_LOAD( "ic32.bin", 0x4000, 0x0800, CRC(1e5a753c) SHA1(5b7cd7b347203f4edf816f02c366bd3b1b9517c4) ) +ROM_END + +ROM_START( invaderl ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "c01", 0x0000, 0x0400, CRC(499f253a) SHA1(e13353194277f5d35e92db9b11912b5f392f51b7) ) + ROM_LOAD( "c02", 0x0400, 0x0400, CRC(2d0b2e1f) SHA1(2e0262d9dba607824fcd720d2995531649bdd03d) ) + ROM_LOAD( "c03", 0x0800, 0x0400, CRC(03033dc2) SHA1(87d7838e6a6542c2c5510af593df45137cb397c6) ) + ROM_LOAD( "c07", 0x1000, 0x0400, CRC(5a7bbf1f) SHA1(659f2a8c646660d316d6e70f1d9548375f1da63f) ) + ROM_LOAD( "c04", 0x1400, 0x0400, CRC(455b1fa7) SHA1(668800a0a3ba18d8b54c2aa4dfd4bd01a667d679) ) + ROM_LOAD( "c05", 0x1800, 0x0400, CRC(40cbef75) SHA1(15994ed8bb8ab8faed6198926873851062c9d95f) ) + ROM_LOAD( "sv06.bin", 0x1c00, 0x0400, CRC(2c68e0b4) SHA1(a5e5357120102ad32792bf3ef6362f45b7ba7070) ) +ROM_END + +ROM_START( invader4 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "spin4.a", 0x0000, 0x0800, CRC(bb386dfe) SHA1(cc00f3e4f6ca4c05bae038a24ccdb213fb951cfc) ) + ROM_LOAD( "spin4.b", 0x0800, 0x0800, CRC(63afa11d) SHA1(d8cedfa010a49237e31f6ebaed35134cb1c3ce68) ) + ROM_LOAD( "spin4.c", 0x1000, 0x0800, CRC(22b0317c) SHA1(8fd037bf5f89a7bcb06042697410566d5180912a) ) + ROM_LOAD( "spin4.d", 0x1800, 0x0800, CRC(9102fd68) SHA1(3523e69314844fcd1863b1e9a9d7fcebe9ee174b) ) +ROM_END + +ROM_START( jspecter ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "3305.u6", 0x0000, 0x1000, CRC(ab211a4f) SHA1(d675ed29c3479d7318f8559bd56dd619cf631b6a) ) + ROM_LOAD( "3306.u7", 0x1400, 0x1000, CRC(0df142a7) SHA1(2f1c32d6fe7eafb7808fef0bdeb69b4909427417) ) +ROM_END + +ROM_START( jspecter2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "unksi.b2", 0x0000, 0x1000, CRC(0584b6c4) SHA1(c130021b878bde2beda4a189f71bbfed61088535) ) + ROM_LOAD( "unksi.a2", 0x1400, 0x1000, CRC(58095955) SHA1(545df3bb9ee4ff09f491d7a4b704e31aa311a8d7) ) +ROM_END + +ROM_START( invadpt2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "pv01", 0x0000, 0x0800, CRC(7288a511) SHA1(ff617872784c28ed03591aefa9f0519e5651701f) ) + ROM_LOAD( "pv02", 0x0800, 0x0800, CRC(097dd8d5) SHA1(8d68654d54d075c0f0d7f63c87ff4551ce8b7fbf) ) + ROM_LOAD( "pv03", 0x1000, 0x0800, CRC(1766337e) SHA1(ea959bf06c9930d83a07559e191a28641efb07ac) ) + ROM_LOAD( "pv04", 0x1800, 0x0800, CRC(8f0e62e0) SHA1(a967b155f15f8432222fcc78b23121b00c405c5c) ) + ROM_LOAD( "pv05", 0x4000, 0x0800, CRC(19b505e9) SHA1(6a31a37586782ce421a7d2cffd8f958c00b7b415) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "pv06.1", 0x0000, 0x0400, CRC(a732810b) SHA1(a5fabffa73ca740909e23b9530936f9274dff356) ) + ROM_LOAD( "pv07.2", 0x0400, 0x0400, CRC(2c5b91cb) SHA1(7fa4d4aef85473b1b4f18734230c164e72be44e7) ) +ROM_END + +ROM_START( invadpt2br ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "pv01", 0x0000, 0x0800, CRC(7288a511) SHA1(ff617872784c28ed03591aefa9f0519e5651701f) ) + /* pv01 had weird encryption applied to it, very likely to have been done post-dump. */ +// for (offs = 0x4fc; offs < 0x5fc; offs++) +// rom[offs] ^= 0x6c; + + // 0x4fc + 1 * 0x56 +// for (offs = 0x54e; offs < 0x552; offs++) +// rom[offs] ^= 0x03; + + // 0x4fc + 2 * 0x56 +// for (offs = 0x5a4; offs < 0x5a8; offs++) +// rom[offs] ^= 0x01; + + // 0x4fc + 3 * 0x56 +// for (offs = 0x5fa; offs < 0x5fc; offs++) +// rom[offs] ^= 0x02; + + ROM_LOAD( "br_pv02", 0x0800, 0x0800, CRC(420c7c35) SHA1(b51265f4d9e5a8cf9d53099a97cadd25ea0b34ce) ) + ROM_LOAD( "br_pv03", 0x1000, 0x0800, CRC(dffd04b9) SHA1(d51a0f27e90b0a49cf2d57ec82a863dcae9f3ea4) ) + ROM_LOAD( "br_pv04", 0x1800, 0x0800, CRC(b0626aff) SHA1(b7de6c21030732bd0479228f057ca4c87b913b0a) ) + ROM_LOAD( "br_pv05", 0x4000, 0x0800, CRC(84c70bb8) SHA1(75fef3ee6da3e7e01a257629016bc10a23691d62) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 (taken from parent set) */ + ROM_LOAD( "pv06.1", 0x0000, 0x0400, CRC(a732810b) SHA1(a5fabffa73ca740909e23b9530936f9274dff356) ) + ROM_LOAD( "pv07.2", 0x0400, 0x0400, CRC(2c5b91cb) SHA1(7fa4d4aef85473b1b4f18734230c164e72be44e7) ) +ROM_END + +ROM_START( invaddlx ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "invdelux.h", 0x0000, 0x0800, CRC(e690818f) SHA1(0860fb03a64d34a9704a1459a5e96929eafd39c7) ) + ROM_LOAD( "invdelux.g", 0x0800, 0x0800, CRC(4268c12d) SHA1(df02419f01cf0874afd1f1aa16276751acd0604a) ) + ROM_LOAD( "invdelux.f", 0x1000, 0x0800, CRC(f4aa1880) SHA1(995d77b67cb4f2f3781c2c8747cb058b7c1b3412) ) + ROM_LOAD( "invdelux.e", 0x1800, 0x0800, CRC(408849c1) SHA1(f717e81017047497a2e9f33f0aafecfec5a2ed7d) ) + ROM_LOAD( "invdelux.d", 0x4000, 0x0800, CRC(e8d5afcd) SHA1(91fde9a9e7c3dd53aac4770bd169721a79b41ed1) ) +ROM_END + +/* Runs on a Space Invaders Part II boardset with an epoxy module in place of the 8080 CPU */ +ROM_START( vortex ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.t36", 0x0000, 0x0800, CRC(577417a6) SHA1(13ed1b989b8ea27cea88be7872921ff9283b5dd6) ) + ROM_LOAD( "2.t35", 0x0800, 0x0800, CRC(126d0049) SHA1(4c189a2364bca8682543d605e84d458bf81ee489) ) + ROM_LOAD( "3.t34", 0x1000, 0x0800, CRC(4a2510b3) SHA1(1c62583b7baf8ee2b6014a6e5dfc7e2d516886d1) ) + ROM_LOAD( "4.t33", 0x1800, 0x0800, CRC(da0274fe) SHA1(b8ab1b16d66700f9ca6a2380a5b6796eaef6e1bd) ) + ROM_LOAD( "5.t32", 0x4000, 0x0800, CRC(a3de49d6) SHA1(e302c6fd2705c6e7f9125b52b2dcb034cc88a90e) ) + ROM_LOAD( "6.t31", 0x4800, 0x0800, CRC(271085d0) SHA1(a772cec8135bc746f6c56aa294eb22c0604e16f9) ) +ROM_END + + +ROM_START( moonbase ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ze3-1.a4", 0x0000, 0x0400, CRC(82dbf2c7) SHA1(c767d8b866db4a5059bd79f962a90ce3a962e1e6) ) + ROM_LOAD( "ze3-2.c4", 0x0400, 0x0400, CRC(c867f5b4) SHA1(686318fda6edde297aecaf33f480bfa075fa6eca) ) + ROM_LOAD( "ze3-3.e4", 0x0800, 0x0400, CRC(cb23ccc1) SHA1(86be2d14d52b3404e1a25c573bd25b97729d82a1) ) + ROM_LOAD( "ze3-4.f4", 0x0c00, 0x0400, CRC(9a11abe2) SHA1(f5337183c7f279d75ddeeab24f4f132aa2ee103b) ) // 'Taito Corp' string hidden in ROM + ROM_LOAD( "ze3-5.h4", 0x1000, 0x0400, CRC(2b105ed3) SHA1(fa0767089b3aaec25be39e950e7163ecbdc2f39f) ) + ROM_LOAD( "ze3-6.l4", 0x1400, 0x0400, CRC(cb3d6dcb) SHA1(b4923b12a141c76b7d50274f19a3224db26a5669) ) + ROM_LOAD( "ze3-7.a5", 0x1800, 0x0400, CRC(774b52c9) SHA1(ddbbba874ac069fb930b364a890c45675ec389f7) ) + ROM_LOAD( "ze3-8.c5", 0x1c00, 0x0400, CRC(e88ea83b) SHA1(ef05be4783c860369ee5ecd4844837207e99ad9f) ) + ROM_LOAD( "ze3-9.e5", 0x4000, 0x0400, CRC(2dd5adfa) SHA1(62cb98cad1e48de0e0cbf30392d35834b38dadbd) ) + ROM_LOAD( "ze3-10.f5", 0x4400, 0x0400, CRC(1e7c22a4) SHA1(b34173375494ffbf5400dd4014a683a9807f4f08) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "cv02.h7", 0x0400, 0x0400, CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) /* NEC B406 or compatible BPROM, like the 82S137 */ + ROM_LOAD( "cv01.g7", 0x0000, 0x0400, CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) /* NEC B406 or compatible BPROM, like the 82S137 */ +ROM_END + +ROM_START( moonbasea ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ze3-1.a4", 0x0000, 0x0400, CRC(82dbf2c7) SHA1(c767d8b866db4a5059bd79f962a90ce3a962e1e6) ) + ROM_LOAD( "ze3-2.c4", 0x0400, 0x0400, CRC(c867f5b4) SHA1(686318fda6edde297aecaf33f480bfa075fa6eca) ) + ROM_LOAD( "ze3-3.e4", 0x0800, 0x0400, CRC(cb23ccc1) SHA1(86be2d14d52b3404e1a25c573bd25b97729d82a1) ) + ROM_LOAD( "ze3-4_alt.f4", 0x0c00, 0x0400, CRC(86a00411) SHA1(f518f5098512d6d23a8887605707844c1b32e54f) ) // 'Nichibutsu' string hidden in ROM + ROM_LOAD( "ze3-5.h4", 0x1000, 0x0400, CRC(2b105ed3) SHA1(fa0767089b3aaec25be39e950e7163ecbdc2f39f) ) + ROM_LOAD( "ze3-6.l4", 0x1400, 0x0400, CRC(cb3d6dcb) SHA1(b4923b12a141c76b7d50274f19a3224db26a5669) ) + ROM_LOAD( "ze3-7.a5", 0x1800, 0x0400, CRC(774b52c9) SHA1(ddbbba874ac069fb930b364a890c45675ec389f7) ) + ROM_LOAD( "ze3-8.c5", 0x1c00, 0x0400, CRC(e88ea83b) SHA1(ef05be4783c860369ee5ecd4844837207e99ad9f) ) + ROM_LOAD( "ze3-9.e5", 0x4000, 0x0400, CRC(2dd5adfa) SHA1(62cb98cad1e48de0e0cbf30392d35834b38dadbd) ) + ROM_LOAD( "ze3-10.f5", 0x4400, 0x0400, CRC(1e7c22a4) SHA1(b34173375494ffbf5400dd4014a683a9807f4f08) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "cv02.h7", 0x0400, 0x0400, CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) /* NEC B406 or compatible BPROM, like the 82S137 */ + ROM_LOAD( "cv01.g7", 0x0000, 0x0400, CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) /* NEC B406 or compatible BPROM, like the 82S137 */ +ROM_END + + +ROM_START( invrvnge ) // Space Invaders hw + sound daughterboard + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "h.ic36", 0x0000, 0x0800, CRC(0e229b9f) SHA1(617197bf94e9700cbbb2f32487dc47b318d4f2af) ) + ROM_LOAD( "g.ic35", 0x0800, 0x0800, CRC(26b38aa4) SHA1(f281c7ec47ce6ab61bfda2e7aa6a5b8a01f2c11e) ) + ROM_LOAD( "f.ic34", 0x1000, 0x0800, CRC(b3b2749e) SHA1(4f854f981396e2d6a959dd48cff12234074fb69b) ) + ROM_LOAD( "e.ic33", 0x1800, 0x0800, CRC(d8e75102) SHA1(86d5618944265947e3ce60fdf048d8fff4a55744) ) + + ROM_REGION( 0x10000, "audiocpu", 0 ) // encrypted + ROM_LOAD( "snd.2c", 0xf000, 0x0800, CRC(135f3b16) SHA1(d472a6ca32c4a16cc1faf09f4a4876d75cd4ba24) ) + ROM_LOAD( "snd.1c", 0xf800, 0x0800, CRC(152fc85e) SHA1(df207d6e690287a56e4e330deaa5ee40a179f1fc) ) + + ROM_REGION( 0x0800, "proms", 0 ) + ROM_LOAD( "colour.bin", 0x0000, 0x0800, CRC(7de74988) SHA1(0b8c94b2bfdbc3921d60aad765df8af611f3fdd7) ) +ROM_END + +ROM_START( invrvngea ) // Space Invaders hw + sound daughterboard + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "h.ic36", 0x0000, 0x0800, CRC(0914b279) SHA1(91e465f56ed0dc8c68e109e33ec9d2bda2616a21) ) // sldh + ROM_LOAD( "g.ic35", 0x0800, 0x0800, CRC(84d9497c) SHA1(fb1b5fc49365fbf89e5418789e64efd186cdeecf) ) // sldh + ROM_LOAD( "f.ic34", 0x1000, 0x0800, CRC(78d34d97) SHA1(a50c19df12e75c644b014d74a463094e249db207) ) // sldh + ROM_LOAD( "e.ic33", 0x1800, 0x0800, CRC(30c71887) SHA1(17c9e905eb327435d52b6d51842f7f42a5e6ab7d) ) // sldh + + ROM_REGION( 0x10000, "audiocpu", 0 ) // encrypted + ROM_LOAD( "snd.2c", 0xf000, 0x0800, CRC(135f3b16) SHA1(d472a6ca32c4a16cc1faf09f4a4876d75cd4ba24) ) + ROM_LOAD( "snd.1c", 0xf800, 0x0800, CRC(152fc85e) SHA1(df207d6e690287a56e4e330deaa5ee40a179f1fc) ) + + ROM_REGION( 0x0800, "proms", 0 ) + ROM_LOAD( "colour.bin", 0x0000, 0x0800, CRC(7de74988) SHA1(0b8c94b2bfdbc3921d60aad765df8af611f3fdd7) ) +ROM_END + +ROM_START( invrvngeb ) // source unknown + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "invrvnge.h", 0x0000, 0x0800, CRC(aca41bbb) SHA1(ca71f792abd6d9a44d15b19d2ccf678e82ccba4f) ) + ROM_LOAD( "invrvnge.g", 0x0800, 0x0800, CRC(cfe89dad) SHA1(218b6a0b636c49c4cdc3667e8b1387ef0e257115) ) + ROM_LOAD( "invrvnge.f", 0x1000, 0x0800, CRC(e350de2c) SHA1(e845565e2f96f9dec3242ec5ab75910a515428c9) ) + ROM_LOAD( "invrvnge.e", 0x1800, 0x0800, CRC(1ec8dfc8) SHA1(fc8fbe1161958f57c9f4ccbcab8a769184b1c562) ) + + ROM_REGION( 0x10000, "audiocpu", 0 ) // encrypted + ROM_LOAD( "snd.2c", 0xf000, 0x0800, BAD_DUMP CRC(135f3b16) SHA1(d472a6ca32c4a16cc1faf09f4a4876d75cd4ba24) ) // not dumped, taken from parent + ROM_LOAD( "snd.1c", 0xf800, 0x0800, BAD_DUMP CRC(152fc85e) SHA1(df207d6e690287a56e4e330deaa5ee40a179f1fc) ) // not dumped, taken from parent + + ROM_REGION( 0x0800, "proms", 0 ) + ROM_LOAD( "colour.bin", 0x0000, 0x0800, BAD_DUMP CRC(7de74988) SHA1(0b8c94b2bfdbc3921d60aad765df8af611f3fdd7) ) // not dumped, taken from parent +ROM_END + +ROM_START( invrvngedu ) // single PCB + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ir.5m", 0x0000, 0x0800, CRC(b145cb71) SHA1(127eb11de7ab9835f06510fb12838c0b728c0d42) ) + ROM_LOAD( "ir.5n", 0x0800, 0x0800, CRC(660e8af3) SHA1(bd52eadf4ee3d717fd5bd7206e1e87d729250c92) ) + ROM_LOAD( "ir.5p", 0x1000, 0x0800, CRC(6ec5a9ad) SHA1(d1e84d2d60c6128c092f2cd20a2b87216df3034b) ) + ROM_LOAD( "ir.5r", 0x1800, 0x0800, CRC(74516811) SHA1(0f595c7b0fae5f3f83fdd1ffed5a408ee77c9438) ) + + ROM_REGION( 0x10000, "audiocpu", 0 ) // encrypted + ROM_LOAD( "ir.1t", 0xf000, 0x0800, BAD_DUMP CRC(135f3b16) SHA1(d472a6ca32c4a16cc1faf09f4a4876d75cd4ba24) ) // not dumped, taken from parent + ROM_LOAD( "ir.1u", 0xf800, 0x0800, BAD_DUMP CRC(152fc85e) SHA1(df207d6e690287a56e4e330deaa5ee40a179f1fc) ) // not dumped, taken from parent + + ROM_REGION( 0x0800, "proms", 0 ) + ROM_LOAD( "ir.3r", 0x0000, 0x0800, CRC(57da51a9) SHA1(a8cb0b45c52eef353b83fe75b61e4990e27eb124) ) +ROM_END + +ROM_START( invrvngegw ) // single PCB + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ir.5m", 0x0000, 0x0800, CRC(4fe35d1f) SHA1(469d563f88229cf163f8b21dce9e68f75d3d214e) ) // sldh + ROM_LOAD( "ir.5n", 0x0800, 0x0800, CRC(92d0442c) SHA1(1d104fbb225ce1a3a72e47af396a641030d990c2) ) // sldh + ROM_LOAD( "ir.5p", 0x1000, 0x0800, CRC(18d2372d) SHA1(d19b7bd315226ef0a565b296964b221fa4714413) ) // sldh + ROM_LOAD( "ir.5r", 0x1800, 0x0800, CRC(657ddf27) SHA1(957c6bbdb2133d4697d3302b2358979d1451b6d5) ) // sldh + + ROM_REGION( 0x10000, "audiocpu", 0 ) // encrypted + ROM_LOAD( "ir.1t", 0xf000, 0x0800, CRC(64e9e81e) SHA1(3390f8bab219cf134b33ae21c473da0873e01929) ) // sldh - bad? + ROM_LOAD( "ir.1u", 0xf800, 0x0800, CRC(152fc85e) SHA1(df207d6e690287a56e4e330deaa5ee40a179f1fc) ) + + ROM_REGION( 0x0800, "proms", 0 ) + ROM_LOAD( "ir.3r", 0x0000, 0x0800, CRC(6ce639bf) SHA1(73752f5886dcf8729d9853ddc258770f5c724ca3) ) // sldh +ROM_END + + +ROM_START( spclaser ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "la01", 0x0000, 0x0800, CRC(bedc0078) SHA1(a5bb0cbbb8e3f27d03beb8101b2be1111d73689d) ) + ROM_LOAD( "la02", 0x0800, 0x0800, CRC(43bc65c5) SHA1(5f9827c02c2d221e1607359c840374ff7fb92fbf) ) + ROM_LOAD( "la03", 0x1000, 0x0800, CRC(1083e9cc) SHA1(7ad45c6230c9e02fcf51e3414c15e2237eebbd7a) ) + ROM_LOAD( "la04", 0x1800, 0x0800, CRC(5116b234) SHA1(b165b2574cbcb26a5bb43f91df5f8be5f111f486) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv/intruder */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( intruder ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "la01-1.36", 0x0000, 0x0800, CRC(bedc0078) SHA1(a5bb0cbbb8e3f27d03beb8101b2be1111d73689d) ) + ROM_LOAD( "la02-1.35", 0x0800, 0x0800, CRC(43bc65c5) SHA1(5f9827c02c2d221e1607359c840374ff7fb92fbf) ) + ROM_LOAD( "la03-1.34", 0x1000, 0x0800, CRC(278ef9cf) SHA1(74a9c1d3500ea28e50d07363a547c381999c84fa) ) + ROM_LOAD( "la04-1.33", 0x1800, 0x0800, CRC(5116b234) SHA1(b165b2574cbcb26a5bb43f91df5f8be5f111f486) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "01.1", 0x0000, 0x0400, CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( laser ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.u36", 0x0000, 0x0800, CRC(b44e2c41) SHA1(00e0b2e088495d6f3bc175e8a53dcb3686ea8484) ) + ROM_LOAD( "2.u35", 0x0800, 0x0800, CRC(9876f331) SHA1(14e36b26d186d9a195492834ef989ed5664d7b65) ) + ROM_LOAD( "3.u34", 0x1000, 0x0800, CRC(ed79000b) SHA1(bfe0407e833ce61aa909f5f1f93c3fc1d46605e9) ) + ROM_LOAD( "4.u33", 0x1800, 0x0800, CRC(10a160a1) SHA1(e2d4208af11b65fc42d2856e57ee3c196f89d360) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from intruder */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( spcewarl ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "spcewarl.1", 0x0000, 0x0800, CRC(1fcd34d2) SHA1(674139944e0d842a85bd21b326bd735e15453038) ) + ROM_LOAD( "spcewarl.2", 0x0800, 0x0800, CRC(43bc65c5) SHA1(5f9827c02c2d221e1607359c840374ff7fb92fbf) ) + ROM_LOAD( "spcewarl.3", 0x1000, 0x0800, CRC(7820df3a) SHA1(53315857f4282c68624b338b068d80ee6828af4c) ) + ROM_LOAD( "spcewarl.4", 0x1800, 0x0800, CRC(adc05b8d) SHA1(c4acf75537c0662a4785d5d6a90643239a54bf43) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from intruder */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( galxwars ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "univgw3.0", 0x0000, 0x0400, CRC(937796f4) SHA1(88e9494cc532498e51e3a68fa1122c40f22b27dd) ) + ROM_LOAD( "univgw4.1", 0x0400, 0x0400, CRC(4b86e7a6) SHA1(167f9f7491a2de39d08e3e6f7057cc75b36c9340) ) + ROM_LOAD( "univgw5.2", 0x0800, 0x0400, CRC(47a187cd) SHA1(640c896ba25f34d323624005bd676257ad17b687) ) + ROM_LOAD( "univgw6.3", 0x0c00, 0x0400, CRC(7b7d22ff) SHA1(74364cf2b04dcfbbc8e0131fa12c0e574f693d34) ) + ROM_LOAD( "univgw1.4", 0x4000, 0x0400, CRC(0871156e) SHA1(3726d0bfe153a0afc62ea56737662074986064b0) ) + ROM_LOAD( "univgw2.5", 0x4400, 0x0400, CRC(6036d7bf) SHA1(36c2ad2ffdb47bbecc40fd67ced6ab51a5cd2f3e) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv/intruder */ + /* Or are colormaps generated by a group of TTLs, similar to dai3wksi? */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( galxwars2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "3192.h6", 0x0000, 0x1000, CRC(bde6860b) SHA1(e04b8add32d8f7ea588fae6d6a387f1d40495f1b) ) + ROM_LOAD( "3193.h7", 0x4000, 0x1000, CRC(a17cd507) SHA1(554ab0e8bdc0e7af4a30b0ddc8aa053c8e70255c) ) /* 2nd half unused */ + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv/intruder */ + /* Or are colormaps generated by a group of TTLs, similar to dai3wksi? */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( galxwarst ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "galxwars.0", 0x0000, 0x0400, CRC(608bfe7f) SHA1(a41a40a2f0a1bb61a70b9ff8a7da925ab1db7f74) ) + ROM_LOAD( "galxwars.1", 0x0400, 0x0400, CRC(a810b258) SHA1(030a72fffcf240f643bc3006028cb4883cf58bbc) ) + ROM_LOAD( "galxwars.2", 0x0800, 0x0400, CRC(74f31781) SHA1(1de70e8ebbb26eea20ffedb7bd0ca051a67f45e7) ) + ROM_LOAD( "galxwars.3", 0x0c00, 0x0400, CRC(c88f886c) SHA1(4d705fbb97e3868c3f6c90c5e5753ad17cfbf5d6) ) + ROM_LOAD( "galxwars.4", 0x4000, 0x0400, CRC(ae4fe8fb) SHA1(494f44167dc84e4515b769c12f6e24419461dce4) ) + ROM_LOAD( "galxwars.5", 0x4400, 0x0400, CRC(37708a35) SHA1(df6fd521ddfa146ef93e390e47741bdbfda1e7ba) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv/intruder */ + /* Or are colormaps generated by a group of TTLs, similar to dai3wksi? */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( starw ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "roma", 0x0000, 0x0400, CRC(60e8993c) SHA1(0bdf163ff0f2e6a8771987d4e7ac604c45af21b8) ) + ROM_LOAD( "romb", 0x0400, 0x0400, CRC(b8060773) SHA1(92aa358c338ef8f5773bccada8988d068764e7ea) ) + ROM_LOAD( "romc", 0x0800, 0x0400, CRC(307ce6b8) SHA1(f4b6f54db3d2377ec27d62d33fa1c4946559a092) ) + ROM_LOAD( "romd", 0x1400, 0x0400, CRC(2b0d0a88) SHA1(d079d12b6d4136519ded32415d668a02147b7601) ) + ROM_LOAD( "rome", 0x1800, 0x0400, CRC(5b1c3ad0) SHA1(edb42eec59c3dd7e274e2ea08fed0f3e8fc72e9e) ) + ROM_LOAD( "romf", 0x1c00, 0x0400, CRC(c8e42d3d) SHA1(841b27af251b9c3a964972e864fb7c88acc742e0) ) +ROM_END + +ROM_START( starw1 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "gc.75", 0x0000, 0x0400, CRC(ad10c128) SHA1(c30ff9ff5cf8dedf7654c8e2799a4bb79a30104a) ) + ROM_LOAD( "gc.77", 0x0400, 0x0400, CRC(ab77c474) SHA1(eb07dcad1f265834b93a8108298d4441d6a74b2e) ) + ROM_LOAD( "gc.76", 0x0800, 0x0400, CRC(3638aed4) SHA1(1426c9270f248fd2ab134dc35526599c02051ccd) ) + ROM_LOAD( "gc.80", 0x1400, 0x0400, CRC(4c67957b) SHA1(dda7bbd54e7395dea80d224e487318fb4429f027) ) + ROM_LOAD( "gc.81", 0x1800, 0x0400, CRC(246621ef) SHA1(bddc5253f735fa81266d725a24b1c14faabe0c6a) ) + ROM_LOAD( "gc.82", 0x1c00, 0x0400, CRC(19bd32ee) SHA1(a1718a6a6300c3d7df469793cb0d590c4a966aff) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "cv01", 0x0000, 0x0400, CRC(8d892ef3) SHA1(c471dd6197a3c779d89c33fcb425cf3bbdf4fc15) ) + ROM_IGNORE( 0x0400 ) + ROM_LOAD( "cv02", 0x0400, 0x0400, CRC(b44ddde8) SHA1(8793f370526c072e645d8d0b9794b1b64a7701ef) ) + ROM_IGNORE( 0x0400 ) +ROM_END + +ROM_START( lrescue ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "lrescue.1", 0x0000, 0x0800, CRC(2bbc4778) SHA1(0167f1ac1501ab0b4c4e555023fa5efed59d56ae) ) + ROM_LOAD( "lrescue.2", 0x0800, 0x0800, CRC(49e79706) SHA1(bed675bb97d59ae0132c007ccead0d096ed2ddf1) ) + ROM_LOAD( "lrescue.3", 0x1000, 0x0800, CRC(1ac969be) SHA1(67ac47f45b9fa5c530bf6047bb7d5776b52847be) ) + ROM_LOAD( "lrescue.4", 0x1800, 0x0800, CRC(782fee3c) SHA1(668295e9d6d99084bb4e7c5491f00fe75f4f5a88) ) + ROM_LOAD( "lrescue.5", 0x4000, 0x0800, CRC(58fde8bc) SHA1(663665ac5254204c1eba18357d9867034eae55eb) ) + ROM_LOAD( "lrescue.6", 0x4800, 0x0800, CRC(bfb0f65d) SHA1(ea0943d764a16094b6e2289f62ef117c9f838c98) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color map */ + ROM_LOAD( "7643-1.cpu", 0x0000, 0x0400, CRC(8b2e38de) SHA1(d6a757be31c3a179d31bd3709e71f9e38ec632e9) ) + ROM_RELOAD( 0x0400, 0x0400 ) +ROM_END + +/* +MOON LANDER +Manufacturer: Leisure Time Electronics +Year: 1980 +Orientation: Vertical B/W +Cabinet: Cocktail +Leisure Time Electronics produced three games: Astro Laser, Moon Lander, and Space Ranger. +The games were designed to be interchangeable with a universal cocktail cabinet which they designed and named "Star Series". The cocktail cabinets share the same artwork with all three games and has a different instruction card for each game. +There were no upright or cabaret cabinets. The game ROMs operate on Taito pc boards. +Moon Lander is a clone/ripoff of Lunar Rescue/Destination Earth. I do not have a manual or schematics for this pcb although +I was able to confirm 5 out of 8 dipswitch settings. I was surprised to hear the sounds effects are almost exactly like when Lunar Rescue used the "invaders" external samples in MAME. The pcb does not play the invader "hit" sound for some reason. +I couldn't find anything obviously wrong in the sound section so it must be that it's just not hooked up as-is from the factory. There does not appear to be a sound-in-attract option. +CPU - Mitsubishi M5L8080AP +X-tal - 19968 mhz (decimal not shown, device stamped very lightly) +Sound - discrete, SN76477N +I/O board - Taito # CV070001A/CVN00001A label= serial# 172190 +CPU board - Taito # AA017757 label= CVN00004 serial# 802868 +ROM board - Taito # AA017756A label= CVN00006 serial# 046120 +EPROMs - 6x 2716 +ML1.u36 checksum 0002CA52 +ML2.u35 checksum 0002C999 +ML3.u34 checksum 0002BD5C +ML4.u33 checksum 000252EE +ML5.u32 checksum 00029365 +ML6.u31 checksum 0002C624 +Dipswitch sw1, 8-bank +sw1 - # ships +sw2 - # ships +sw3 - not used/unknown +sw4 - not used/unknown +sw5 - ON= enable player2 move right OFF= disabled +sw6 - ON= enable player2 move left OFF= disabled +sw7 - ON= enable player2 fire/shoot OFF= disabled +sw8 - not used/unknown +-------------------------------------------------------------------------- + 1 2 3 4 5 6 7 8 +-------------------------------------------------------------------------- +# of player ships +- 3 ships on on +- 4 ships off on +- 5 ships on off +- 6 ships off off +Maximum Credits= 9 +Sound Pots: +VR1 = engine sound +VR2 = beam gun +VR3 = ship explosion sound +VR4 = enemy explosion sound (not connected?) +VR5 = bonus ship sound +VR6 = bonus music, footsteps, and docking sound +VR7 = shooting star/ship descending sound +VR8 = pot for adjusting total sounds +*/ + +ROM_START( mlander ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ml1.u36", 0x0000, 0x0800, CRC(69df529a) SHA1(ded3b4a04e28dc341b1fc5a8880bc48aa332bdb5) ) + ROM_LOAD( "ml2.u35", 0x0800, 0x0800, CRC(3b503337) SHA1(d1056c0161d481202996811503e9970d0a0c9147) ) + ROM_LOAD( "ml3.u34", 0x1000, 0x0800, CRC(64e53458) SHA1(629f2434eea4d31dc9db0ee7bc8364cd2bf08a04) ) + ROM_LOAD( "ml4.u33", 0x1800, 0x0800, CRC(c9a74571) SHA1(b1671d19eff17f7adb274013c8f11eb044ebdd28) ) + ROM_LOAD( "ml5.u32", 0x4000, 0x0800, CRC(88291fa2) SHA1(40c4eb51f75b5ca81a62121231d22b9f48d0f628) ) + ROM_LOAD( "ml6.u31", 0x4800, 0x0800, CRC(bfb0f65d) SHA1(ea0943d764a16094b6e2289f62ef117c9f838c98) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color map */ + ROM_LOAD( "01.bin", 0x0000, 0x0400, CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.bin", 0x0400, 0x0400, CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( grescue ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "lrescue.1", 0x0000, 0x0800, CRC(2bbc4778) SHA1(0167f1ac1501ab0b4c4e555023fa5efed59d56ae) ) + ROM_LOAD( "lrescue.2", 0x0800, 0x0800, CRC(49e79706) SHA1(bed675bb97d59ae0132c007ccead0d096ed2ddf1) ) + ROM_LOAD( "lrescue.3", 0x1000, 0x0800, CRC(1ac969be) SHA1(67ac47f45b9fa5c530bf6047bb7d5776b52847be) ) + ROM_LOAD( "grescue.4", 0x1800, 0x0800, CRC(ca412991) SHA1(41b59f338a6c246e0942a8bfa3c0bca2c24c7f81) ) + ROM_LOAD( "grescue.5", 0x4000, 0x0800, CRC(a419a4d6) SHA1(8eeeb31cbebffc98d2c6c5b964f9b320fcf303d2) ) + ROM_LOAD( "lrescue.6", 0x4800, 0x0800, CRC(bfb0f65d) SHA1(ea0943d764a16094b6e2289f62ef117c9f838c98) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color map */ + ROM_LOAD( "7643-1.cpu", 0x0000, 0x0400, CRC(8b2e38de) SHA1(d6a757be31c3a179d31bd3709e71f9e38ec632e9) ) + ROM_RELOAD( 0x0400, 0x0400 ) +ROM_END + +ROM_START( desterth ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "36_h.bin", 0x0000, 0x0800, CRC(f86923e5) SHA1(d19935ba3d2c1c2553b3779f1a7ad8856c003dae) ) + ROM_LOAD( "35_g.bin", 0x0800, 0x0800, CRC(797f440d) SHA1(a96917f2296ae467acc795eacc1533a2a2d2f401) ) + ROM_LOAD( "34_f.bin", 0x1000, 0x0800, CRC(993d0846) SHA1(6be0c45add41fa7e43cac96c776cd0ebb45ade7b) ) + ROM_LOAD( "33_e.bin", 0x1800, 0x0800, CRC(8d155fc5) SHA1(1ef5e62d71abbf870c027fa1e477121ff124b8da) ) + ROM_LOAD( "32_d.bin", 0x4000, 0x0800, CRC(3f531b6f) SHA1(2fc1f4912688986650e20a050a5d63ddecd4267e) ) + ROM_LOAD( "31_c.bin", 0x4800, 0x0800, CRC(ab019c30) SHA1(33931510a722168bcf7c30d22eac9345576b6631) ) + ROM_LOAD( "42_b.bin", 0x5000, 0x0800, CRC(ed9dbac6) SHA1(4553f445ac32ebb1be490b02df4924f76557e8f9) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color map */ + ROM_LOAD( "7643-1.cpu", 0x0000, 0x0400, CRC(8b2e38de) SHA1(d6a757be31c3a179d31bd3709e71f9e38ec632e9) ) + ROM_RELOAD( 0x0400, 0x0400 ) +ROM_END + +ROM_START( escmars ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "2516_em.m5", 0x0000, 0x0800, CRC(6580f1c3) SHA1(fd44d4bab799e02b2d7c20fe6bf14ade9c8d4f1d) ) + ROM_LOAD( "2716_em.n5", 0x0800, 0x0800, CRC(49e79706) SHA1(bed675bb97d59ae0132c007ccead0d096ed2ddf1) ) + ROM_LOAD( "2516_em.p5", 0x1000, 0x0800, CRC(1ac969be) SHA1(67ac47f45b9fa5c530bf6047bb7d5776b52847be) ) + ROM_LOAD( "2516_em.r5", 0x1800, 0x0800, CRC(c1bd5949) SHA1(df390dd159766ed6489abfae8bb258115dc643e6) ) + ROM_LOAD( "2716_em.s5", 0x4000, 0x0800, CRC(1ec21a31) SHA1(5db61f00d8987662ccae1132fb25da318ac177dd) ) + ROM_LOAD( "2716_em.t5", 0x4800, 0x0800, CRC(bfb0f65d) SHA1(ea0943d764a16094b6e2289f62ef117c9f838c98) ) + + /* No proms, only colour overlay */ +ROM_END + +ROM_START( lrescuem ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "48.ic36", 0x0000, 0x0400, CRC(bad5ba48) SHA1(6d8a2df172e058d16f196ad7f29430e9fd1fdaa8) ) + ROM_LOAD( "49.ic35", 0x0400, 0x0400, CRC(a6dc23d6) SHA1(76b9105935bf239ae90b47900f64dac3032ceecd) ) + ROM_LOAD( "50.ic34", 0x0800, 0x0400, CRC(90179fee) SHA1(35059f7399229b8d9588d34f79073fa4d3301614) ) + ROM_LOAD( "51.ic33", 0x0c00, 0x0400, CRC(1d197d87) SHA1(21e049f9c2a0fe1c0403d9d1a2dc695c4ee764f9) ) + ROM_LOAD( "52.ic32", 0x1000, 0x0400, CRC(4326d338) SHA1(ac31645bdf292f28dfcfcb9d5e158e5df7a6f95d) ) + ROM_LOAD( "53.ic31", 0x1400, 0x0400, CRC(3b272372) SHA1(39b807c810d093d7a34b102eec16f3d9baeb21f1) ) + ROM_LOAD( "54.ic42", 0x1800, 0x0400, CRC(a877c5b6) SHA1(862871c3dd18221d5713fe1fd2dc4f5b7cb913c1) ) + ROM_LOAD( "55.ic41", 0x1c00, 0x0400, CRC(c9a93407) SHA1(604bcace8e3bec07db6ca8a8918b306b77643e14) ) + ROM_LOAD( "56.ic40", 0x4000, 0x0400, CRC(3398798f) SHA1(d7dd9e65a1048df8edd217f4206b19cd01f143f4) ) + ROM_LOAD( "57.ic39", 0x4400, 0x0400, CRC(37c5bfc6) SHA1(b0aec85e6f979cdf7a3a985830c8530302804837) ) + ROM_LOAD( "58.ic38", 0x4800, 0x0400, CRC(1b7a5644) SHA1(d26530ea11ada86f7c99b11d6faf4416a8f5a9eb) ) + ROM_LOAD( "59.ic37", 0x4c00, 0x0400, CRC(c342b907) SHA1(327da029420c4eedabc2a0534199a008a3f341b8) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 - these don't really fit this game, but were on the PCB */ + ROM_LOAD( "cv01-7643.2c", 0x0000, 0x0400, CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "cv02-7643.1c", 0x0400, 0x0400, CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( lrescuem2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "0.bin", 0x0000, 0x0800, CRC(27d37ad6) SHA1(18b2de9f9c022a31187b2a4049573e7f204e84c9) ) + ROM_LOAD( "1.bin", 0x0800, 0x0800, CRC(d8ed56f0) SHA1(d3f02d43f59d8ee83b4ed94f58f1bd25dca1a8de) ) + ROM_LOAD( "2.bin", 0x1000, 0x0800, CRC(3aed9788) SHA1(1be3c2f9f3a0f7d187a6faa2b020979027fa60e9) ) + ROM_LOAD( "3.bin", 0x1800, 0x0800, CRC(fa121b92) SHA1(2753b8b93d69d49e85075765630958038aa21ce3) ) + ROM_LOAD( "4.bin", 0x4000, 0x0800, CRC(535b4a78) SHA1(dd5613f47a3c7e15701c5d1dbac4a2228b9c28f2) ) + ROM_LOAD( "5.bin", 0x4800, 0x0800, CRC(0613a977) SHA1(47b85efdc436b39f8fb12355f9b87cb791f2d3b1) ) + ROM_LOAD( "6.bin", 0x5000, 0x0800, CRC(8fe51cc0) SHA1(1a98044ab95a1559362813a3961c1436267dcf63) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 - these don't really fit this game, but were on the PCB */ + ROM_LOAD( "cv01-7643.2c", 0x0000, 0x0400, CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "cv02-7643.1c", 0x0400, 0x0400, CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + + +/* +Cosmo +TDS & Mints, 1979/80? +Notes: +This game runs on modified "original" Taito (3 board) Space Invaders hardware. +There are approx. 70 (or more) wires tied to various parts of the boards, plus +there is an extra board on top of the sound board with a *HUGE* amount of wires +running to it from the main boards. There are 2 EPROMs on the top board that appear +to be for use with colour generation or extra sounds(?) The PROMs on the middle board +have been removed and in their place are a pile of wires that join to the top board. +The remainder of the hardware is just standard Taito Space Invaders..... including +a SN76477 and the discrete components for sound generation. +Note that the sounds and gameplay of Cosmo are VERY different from Space Invaders. +*/ + +ROM_START( cosmo ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.36", 0x0000, 0x0800, CRC(445c9a98) SHA1(89bce80a061e9c12544231f970d9dec801eb1b94) ) + ROM_LOAD( "2.35", 0x0800, 0x0800, CRC(df3eb731) SHA1(fb90c1d0f2518195dd49062c9f0fd890536d89f4) ) + ROM_LOAD( "3.34", 0x1000, 0x0800, CRC(772c813f) SHA1(a1c0d857c660fb0b838dd0466af7bf5d73bcd55d) ) + ROM_LOAD( "4.33", 0x1800, 0x0800, CRC(279f66e6) SHA1(8ce71c08cca0bdde2f2e0ef21622731c4610c030) ) + ROM_LOAD( "5.32", 0x4000, 0x0800, CRC(cefb18df) SHA1(bb500cf3f7d1a54045a165d3613a92ab3f11d3e8) ) + ROM_LOAD( "6.31", 0x4800, 0x0800, CRC(b037f6c4) SHA1(b9a42948052b8cda8d2e4575e59909589f4e7a8d) ) + ROM_LOAD( "7.42", 0x5000, 0x0800, CRC(c3831ea2) SHA1(8c67ef0312656ef0eeff34b8463376c736bd8ea1) ) + + ROM_REGION( 0x1000, "proms", 0 ) /* color map */ + ROM_LOAD( "n-1.7d", 0x0800, 0x0800, CRC(bd8576f1) SHA1(aa5fe0a4d024f21a3bca7a6b3f5022779af6f3f4) ) + ROM_LOAD( "n-2.6e", 0x0000, 0x0800, CRC(48f1ade5) SHA1(a1b45f82f3649cde8ae6a2ef494a3a6cdb5e65d0) ) +ROM_END + + +ROM_START( cosmicmo ) /* Roms stamped with "II", denoting version II */ + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ii-1.h1", 0x0000, 0x0400, CRC(d6e4e5da) SHA1(8b4275a3c71ac3fa80d17237dc04de5f586645f4) ) + ROM_LOAD( "ii-2.h2", 0x0400, 0x0400, CRC(8f7988e6) SHA1(b6a01d5dcab013350f8f7f3e3ebfc986bb939fe0) ) + ROM_LOAD( "ii-3.h3", 0x0800, 0x0400, CRC(2d2e9dc8) SHA1(dd3da4fc752e003e5e7c64bf189288133aed545b) ) + ROM_LOAD( "ii-4.h4", 0x0c00, 0x0400, CRC(26cae456) SHA1(2f2262340c10e5c29d71317f6eb8072c26655563) ) + ROM_LOAD( "ii-5.h5", 0x4000, 0x0400, CRC(b13f228e) SHA1(a0de05aa36435e72c77f5333f3ad964ec448a8f0) ) + ROM_LOAD( "ii-6.h6", 0x4400, 0x0400, CRC(4ae1b9c4) SHA1(8eed87eebe68caa775fa679363b0fe3728d98c34) ) + ROM_LOAD( "ii-7.h7", 0x4800, 0x0400, CRC(6a13b15b) SHA1(dc03a6c3e938cfd08d16bd1660899f951ba72ea2) ) + + /* There is no colour circuits or tracking on the game pcb, its a black and white composite video signal only */ + /* The PCB is etched with Universal 7814A-3 */ +ROM_END + +ROM_START( cosmicm2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "3907.bin", 0x0000, 0x1000, CRC(bbffede6) SHA1(e7505ee8e3f19557ebbfd0145dc2ae0d1c529eba) ) + ROM_LOAD( "3906.bin", 0x4000, 0x1000, CRC(b841f894) SHA1(b1f9e1800969baab14da2fd8873b58d4707b7236) ) +ROM_END + +ROM_START( superinv ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "00", 0x0000, 0x0400, CRC(7a9b4485) SHA1(dde918ec106971972bf7c7e5085c1262522f7e35) ) + ROM_LOAD( "01", 0x0400, 0x0400, CRC(7c86620d) SHA1(9e92ec0aa4eee96a7fa115a14a611c488d13b9dd) ) + ROM_LOAD( "02", 0x0800, 0x0400, CRC(ccaf38f6) SHA1(8eb0456e8abdba0d1dda20a335a9ecbe7c38f9ed) ) + ROM_LOAD( "03", 0x1400, 0x0400, CRC(8ec9eae2) SHA1(48d7a7dc61e0417ca4093e5c2a36efd96e359233) ) + ROM_LOAD( "04", 0x1800, 0x0400, CRC(68719b30) SHA1(2084bd63cd61ef1d2497c32112cdb42b7b582da4) ) + ROM_LOAD( "05", 0x1c00, 0x0400, CRC(8abe2466) SHA1(17494b1e5db207e37a7d28d7c89cbc5f36b7aefc) ) +ROM_END + +ROM_START( invasion ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "10136-0.0k", 0x0000, 0x0400, CRC(7a9b4485) SHA1(dde918ec106971972bf7c7e5085c1262522f7e35) ) + ROM_LOAD( "10136-1.1k", 0x0400, 0x0400, CRC(7c86620d) SHA1(9e92ec0aa4eee96a7fa115a14a611c488d13b9dd) ) + ROM_LOAD( "10136-2.2k", 0x0800, 0x0400, CRC(ccaf38f6) SHA1(8eb0456e8abdba0d1dda20a335a9ecbe7c38f9ed) ) + ROM_LOAD( "10136-5.5k", 0x1400, 0x0400, CRC(8ec9eae2) SHA1(48d7a7dc61e0417ca4093e5c2a36efd96e359233) ) + ROM_LOAD( "10136-6.6k", 0x1800, 0x0400, CRC(ff0b0690) SHA1(8547c4b2a228f1690287217a916613c8f0caccf6) ) + ROM_LOAD( "10136-7.7k", 0x1c00, 0x0400, CRC(75d7acaf) SHA1(977d146d7df555cea1bb2156d29d88bec9731f98) ) +ROM_END + +ROM_START( invasiona ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "invasiona_0.bin", 0x0000, 0x0400, CRC(c2fe6197) SHA1(823d02c2790711f40c167544a55e1669a97d93b4) ) + ROM_LOAD( "invasiona_1.bin", 0x0400, 0x0400, CRC(7c86620d) SHA1(9e92ec0aa4eee96a7fa115a14a611c488d13b9dd) ) + ROM_LOAD( "invasiona_2.bin", 0x0800, 0x0400, CRC(ccaf38f6) SHA1(8eb0456e8abdba0d1dda20a335a9ecbe7c38f9ed) ) + ROM_LOAD( "invasiona_3.bin", 0x1400, 0x0400, CRC(8ec9eae2) SHA1(48d7a7dc61e0417ca4093e5c2a36efd96e359233) ) + ROM_LOAD( "invasiona_4.bin", 0x1800, 0x0400, CRC(24b39879) SHA1(c93530ac20c412b516fbcba8220d85a9bd4fa804) ) + ROM_LOAD( "invasiona_5.bin", 0x1c00, 0x0400, CRC(59134ff8) SHA1(2e6a040066b35b10f867a3e500e3b13922c0eb7a) ) +ROM_END + +ROM_START( invasionb ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "invasionb_0.bin", 0x0000, 0x0400, CRC(7a9b4485) SHA1(dde918ec106971972bf7c7e5085c1262522f7e35) ) + ROM_LOAD( "invasionb_1.bin", 0x0400, 0x0400, CRC(7c86620d) SHA1(9e92ec0aa4eee96a7fa115a14a611c488d13b9dd) ) + ROM_LOAD( "invasionb_2.bin", 0x0800, 0x0400, CRC(ccaf38f6) SHA1(8eb0456e8abdba0d1dda20a335a9ecbe7c38f9ed) ) + ROM_LOAD( "invasionb_5.bin", 0x1400, 0x0400, CRC(8ec9eae2) SHA1(48d7a7dc61e0417ca4093e5c2a36efd96e359233) ) + ROM_LOAD( "invasionb_6.bin", 0x1800, 0x0400, CRC(ec0edb4a) SHA1(8c6946b50ba5c319fe03c55b43c4e714387719b8) ) + ROM_LOAD( "invasionb_7.bin", 0x1c00, 0x0400, CRC(6aac1281) SHA1(f071a21de72d2c9f7851195592c828fa501197ce) ) +ROM_END + +ROM_START( invasionrz ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rz0.0k", 0x0000, 0x0400, CRC(7a9b4485) SHA1(dde918ec106971972bf7c7e5085c1262522f7e35) ) + ROM_LOAD( "rz1.1k", 0x0400, 0x0400, CRC(7c86620d) SHA1(9e92ec0aa4eee96a7fa115a14a611c488d13b9dd) ) + ROM_LOAD( "rz2.2k", 0x0800, 0x0400, CRC(ccaf38f6) SHA1(8eb0456e8abdba0d1dda20a335a9ecbe7c38f9ed) ) + ROM_LOAD( "rz5.5k", 0x1400, 0x0400, CRC(8ec9eae2) SHA1(48d7a7dc61e0417ca4093e5c2a36efd96e359233) ) + ROM_LOAD( "rz6.6k", 0x1800, 0x0400, CRC(ec0edb4a) SHA1(8c6946b50ba5c319fe03c55b43c4e714387719b8) ) + ROM_LOAD( "rz7.7k", 0x1c00, 0x0400, CRC(e4ab9012) SHA1(4f54e3fd3e3835a7b7d3b8d77929f4d9e42a4917) ) +ROM_END + +ROM_START( invasionrza ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rz0-0.9k", 0x0000, 0x0400, CRC(3044806f) SHA1(7eaedd7fd7fcfd421432d5f6970ede12f586f644) ) + ROM_LOAD( "rz1-1.8k", 0x0400, 0x0400, CRC(7c86620d) SHA1(9e92ec0aa4eee96a7fa115a14a611c488d13b9dd) ) + ROM_LOAD( "rz2-2.7k", 0x0800, 0x0400, CRC(c808e941) SHA1(c17f2171d82df1984c4b048f2664dea5bd9c136b) ) + ROM_LOAD( "rz5-5.4k", 0x1400, 0x0400, CRC(8ec9eae2) SHA1(48d7a7dc61e0417ca4093e5c2a36efd96e359233) ) + // 2 reads of the bad rom + ROM_LOAD( "rz6-6.3k", 0x1800, 0x0400, BAD_DUMP CRC(c48df3ca) SHA1(d92064d171e099a45821c944324b993e39d894f7) ) + ROM_LOAD( "rz6-6.3ka", 0x1800, 0x0400, BAD_DUMP CRC(aa51b2c3) SHA1(bb30f3827a66ec3cb8436566f6b865995d702f76) ) + ROM_LOAD( "rz7-7.2k", 0x1c00, 0x0400, CRC(27dbea48) SHA1(f0bf5d31424dc72ac2e6fa01c528365efff838d2) ) +ROM_END + +/* +Space Invaders (Electromar, Madrid) 1980 +Board by Roselson +Dumped by Ricky2001 from Aumap +This game runs in a clone of a Midway L-Shape Space Invaders pcb with different connectors, but identical. +The board is updated with a litthe daughter board for the reset, instead of being generated in the Power supply. +Most of the Texts are in Spanish but keeps the original name "Space Invaders", also in the psb is writen a Patent number, I think this means it was a licensed version. +Boards Electromar 1007-A / 1007B +Patente N MU221718 +*/ + +ROM_START( invadersem ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "h.bin", 0x0000, 0x0400, CRC(7fc672a5) SHA1(93c8dd27769e9c1ab812fd68031c67a5dc79d0da) ) + ROM_LOAD( "g.bin", 0x0400, 0x0400, CRC(ad518883) SHA1(8f7f1f520287b738ebb6f2c70b7da2cae5db2be8) ) + ROM_LOAD( "f.bin", 0x0800, 0x0400, CRC(f4a6c480) SHA1(eb179a46345d652ffd74f77956d361cebfbb1112)) + ROM_LOAD( "c.bin", 0x1400, 0x0400, CRC(8f62c513) SHA1(87570241d4ab7df3ef380d57d27055af3cca7845) ) + ROM_LOAD( "b.bin", 0x1800, 0x0400, CRC(2808e5c0) SHA1(aef4821d6d6e7f062e3ebecb878e6370b604224e) ) + ROM_LOAD( "a.bin", 0x1c00, 0x0400, CRC(04c9b084) SHA1(d267438589de2d8332410e9641164fe68f337f73) ) +ROM_END + +ROM_START( ultrainv ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "in-01.bin", 0x0000, 0x0400, CRC(db9de599) SHA1(ccee1116ca924b520a126b63088a76d2ce8c396f) ) + ROM_LOAD( "in-02.bin", 0x0400, 0x0400, CRC(febe6d1a) SHA1(e1c3a24b4fa5862107ada1f9d7249466e8c3f06a) ) + ROM_LOAD( "in-03.bin", 0x0800, 0x0400, CRC(3d5c9820) SHA1(f3c83c660edf56a04148e2aa1c8e00427b86ca07) ) + ROM_LOAD( "in-04.bin", 0x1400, 0x0400, CRC(1293b826) SHA1(165cd5d08a19eadbe954145b12807f10df9e691a) ) + ROM_LOAD( "in-05.bin", 0x1800, 0x0400, CRC(e315a8c4) SHA1(dffec9e8bd7014fa34500b4bdac7feadac090482) ) + ROM_LOAD( "in-06.bin", 0x1c00, 0x0400, CRC(d958478c) SHA1(9df38c400c500b45d306d52fe74cd4d5ca92c0f0) ) +ROM_END + + +ROM_START( invmulti ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) // decrypted rom goes here + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("m803d.bin", 0x00000, 0x20000, CRC(6a62cb3c) SHA1(eb7b567098ad596859f417dd5c59c2cf1ebf1154) ) +ROM_END + +ROM_START( invmultim3a ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("m803a.bin", 0x00000, 0x20000, CRC(6d538828) SHA1(9a80c67abd32c4c8cd04320501a2aa4e2a308fc9) ) +ROM_END + +ROM_START( invmultim2c ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("m802c.bin", 0x00000, 0x20000, CRC(5b537de5) SHA1(4d8a6b622b818e88383d011c25f8f34b7372db6d) ) +ROM_END + +ROM_START( invmultim2a ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("m802a.bin", 0x00000, 0x20000, CRC(8079b1d0) SHA1(b13d910f314550eef468ee819b92788d2a002d82) ) +ROM_END + +ROM_START( invmultim1a ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("m801a.bin", 0x00000, 0x20000, CRC(f28536d2) SHA1(08ef3ea3fac38c7a478f094bfa7c369ac39515c4) ) +ROM_END + +ROM_START( invmultit3d ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("t803d.bin", 0x00000, 0x20000, CRC(4d53173c) SHA1(a9caf7fd8e2fea86ca1cf7edc104bdacf09203f8) ) +ROM_END + +ROM_START( invmultis3a ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("s083a.bin", 0x00000, 0x20000, CRC(f426d43b) SHA1(a299472f1d65f356ec01ca7cc8d3039abac20019) ) +ROM_END + +ROM_START( invmultis2a ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("s082a.bin", 0x00000, 0x20000, CRC(25f0f17e) SHA1(a3ccf823399e23dd9fdb38fd58c0acfe80b57fe3) ) +ROM_END + +ROM_START( invmultis1a ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("s081a.bin", 0x00000, 0x20000, CRC(daa77345) SHA1(0fdc9c2a6d9c0aa3233c5d31433adb1ea4e5b250) ) +ROM_END + +ROM_START( invmultip ) + ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) + + ROM_REGION( 0x20000, "user1", 0 ) + ROM_LOAD("s10.bin", 0x00000, 0x20000, CRC(1b43e4d3) SHA1(c50decd9caaec7f2d8b3ba74f718372d31bc1c3b) ) +ROM_END + + +ROM_START( rollingc ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rc01.bin", 0x0000, 0x0400, CRC(66fa50bf) SHA1(7451d4ff8d3b351a324aaecdbdc5b46672f5fdd0) ) + ROM_LOAD( "rc02.bin", 0x0400, 0x0400, CRC(61c06ae4) SHA1(7685c806e20e4a4a0508a547ac08ca8f6d75bb79) ) + ROM_LOAD( "rc03.bin", 0x0800, 0x0400, CRC(77e39fa0) SHA1(16bf88af1b97c5a2a81e105af08b8d9d1f10dcc8) ) + ROM_LOAD( "rc04.bin", 0x0c00, 0x0400, CRC(3fdfd0f3) SHA1(4c5e7136a766f3f16399e61eaaa0e00ef6b619f7) ) + ROM_LOAD( "rc05.bin", 0x1000, 0x0400, CRC(c26a8f5b) SHA1(f7a541999cfe04c6d6927d285484f0f81857e04a) ) + ROM_LOAD( "rc06.bin", 0x1400, 0x0400, CRC(0b98dbe5) SHA1(33cedab82ddccb4caaf681fce553b5230a8d6f92) ) + ROM_LOAD( "rc07.bin", 0x1800, 0x0400, CRC(6242145c) SHA1(b01bb02835dda89dc02604ec52e423167183e8c9) ) + ROM_LOAD( "rc08.bin", 0x1c00, 0x0400, CRC(d23c2ef1) SHA1(909e3d53291dbd219f4f9e0047c65317b9f6d5bd) ) + + ROM_LOAD( "rc09.bin", 0x4000, 0x0800, CRC(2e2c5b95) SHA1(33f4e2789d67e355ccd99d2c0d07301ec2bd3bc1) ) + ROM_LOAD( "rc10.bin", 0x4800, 0x0800, CRC(ef94c502) SHA1(07c0504b2ebce0fa6e53e6957e7b6c0e9caab430) ) + ROM_LOAD( "rc11.bin", 0x5000, 0x0800, CRC(a3164b18) SHA1(7270af25fa4171f86476f5dc409e658da7fba7fc) ) + ROM_LOAD( "rc12.bin", 0x5800, 0x0800, CRC(2052f6d9) SHA1(036702fc40cf133eb374ed674695d7c6c79e8311) ) +ROM_END + +ROM_START( schaser ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rt13.bin", 0x0000, 0x0400, CRC(0dfbde68) SHA1(7367b138ad8448aba9222fed632a892df65cecbd) ) + ROM_LOAD( "rt14.bin", 0x0400, 0x0400, CRC(5a508a25) SHA1(c681d0bbf49317e79b596fb094e66b8912f0e409) ) + ROM_LOAD( "rt15.bin", 0x0800, 0x0400, CRC(2ac43a93) SHA1(d364f0940681a888c0147e06bcb01f8a0d4a24c8) ) + ROM_LOAD( "rt16.bin", 0x0c00, 0x0400, CRC(f5583afc) SHA1(5e8edb43ccb138fd47ac8f3da1af79b4444a4a82) ) + ROM_LOAD( "rt17.bin", 0x1000, 0x0400, CRC(51cf1155) SHA1(fd8c82d951602fd7e0ada65fc7cdee9f277c70db) ) + ROM_LOAD( "rt18.bin", 0x1400, 0x0400, CRC(3f0fc73a) SHA1(b801c3f1e8e6e41c564432db7c5891f6b27293b2) ) + ROM_LOAD( "rt19.bin", 0x1800, 0x0400, CRC(b66ea369) SHA1(d277f572f9c7c4301518546cf60671a6539326ee) ) + ROM_LOAD( "rt20.bin", 0x1c00, 0x0400, CRC(e3a7466a) SHA1(2378970f38b0cec066ef853a6540500e468e4ab4) ) + ROM_LOAD( "rt21.bin", 0x4000, 0x0400, CRC(b368ac98) SHA1(6860efe0496955db67611183be0efecda92c9c98) ) + ROM_LOAD( "rt22.bin", 0x4400, 0x0400, CRC(6e060dfb) SHA1(614e2ecf676c3ea2f9ea869125cfffef2f713684) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "rt06.ic2", 0x0000, 0x0400, CRC(950cf973) SHA1(d22df09b325835a0057ccd0d54f827b374254ac6) ) +ROM_END + +ROM_START( schasera ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rt13.bin", 0x0000, 0x0800, CRC(7b0bfeed) SHA1(832fe90430653d03cd0e7ea1b046524a2ca292ea) ) // sldh + ROM_LOAD( "rt15.bin", 0x0800, 0x0800, CRC(825fc8ac) SHA1(176ff0f4d0cd55be30efb184bd5bef62b92d0333) ) // sldh + ROM_LOAD( "rt17.bin", 0x1000, 0x0800, CRC(de9d3f85) SHA1(13a71fdd889023cfc65ed2c0a65236884b79b1f0) ) // sldh + ROM_LOAD( "rt19.bin", 0x1800, 0x0800, CRC(c0adab87) SHA1(4bb8e4ccfb5eaa052584555bfa03fecf19ab8a29) ) // sldh + ROM_LOAD( "rt21.bin", 0x4000, 0x0800, CRC(a3b31070) SHA1(af0108e1446a2be66cfc00d0b837fa91ab882441) ) // sldh + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "rt06.ic2", 0x0000, 0x0400, CRC(950cf973) SHA1(d22df09b325835a0057ccd0d54f827b374254ac6) ) +ROM_END + +ROM_START( schaserb ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rt33.bin", 0x0000, 0x0800, CRC(eec6b032) SHA1(da14fcd862d6b80531cd3b858034bc5a120ed8ae) ) + ROM_LOAD( "rt34.bin", 0x0800, 0x0800, CRC(13a73701) SHA1(48ddbc10dec458070274c9fabbb0c420e2a07c96) ) + ROM_LOAD( "rt35.bin", 0x1000, 0x0800, CRC(de9d3f85) SHA1(13a71fdd889023cfc65ed2c0a65236884b79b1f0) ) + ROM_LOAD( "rt36.bin", 0x1800, 0x0800, CRC(521ec25e) SHA1(ce53e882c11a4c36f3edc3b389d3f5ad0e0ec151) ) + ROM_LOAD( "rt37.bin", 0x4000, 0x0800, CRC(44f65f19) SHA1(ee97d7987f54c9c26f5a20c72bdae04c46f94dc4) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "rt06.ic2", 0x0000, 0x0400, CRC(950cf973) SHA1(d22df09b325835a0057ccd0d54f827b374254ac6) ) +ROM_END + +ROM_START( schaserm ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "MR26.71", 0x0000, 0x0800, CRC(4e547879) SHA1(464fab35373d6bd6218474e7f5109425376f1db2) ) + ROM_LOAD( "RT08.70", 0x0800, 0x0800, CRC(825fc8ac) SHA1(176ff0f4d0cd55be30efb184bd5bef62b92d0333) ) + ROM_LOAD( "RT09.69", 0x1000, 0x0800, CRC(de9d3f85) SHA1(13a71fdd889023cfc65ed2c0a65236884b79b1f0) ) + ROM_LOAD( "MR27.62", 0x1800, 0x0800, CRC(069ec108) SHA1(b12cd288d7e42002d01290f0572f9074adf2cdca) ) + ROM_LOAD( "RT11.61", 0x4000, 0x0800, CRC(17a7ef7a) SHA1(1a7b3f9393dceddcd1e220cadbff7e619594f884) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "rt06.ic2", 0x0000, 0x0400, CRC(950cf973) SHA1(d22df09b325835a0057ccd0d54f827b374254ac6) ) +ROM_END + +ROM_START( sflush ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "fr05.sc2", 0xd800, 0x800, CRC(c4f08f9f) SHA1(997f216f5244942fc1a19f5c1988adbfadc301fc) ) + ROM_LOAD( "fr04.sc3", 0xe000, 0x800, CRC(87a754a5) SHA1(07c0e2c3cb7aa0086d8f4dd202a452bc6c20d4ee) ) + ROM_LOAD( "fr03.sc4", 0xe800, 0x800, CRC(5b12847f) SHA1(4b62342723dd49a387fae6637c331d7c853712a3) ) + ROM_LOAD( "fr02.sc5", 0xf000, 0x800, CRC(291c9b1f) SHA1(7e5b3e1605581abf3d8165f4de9d4e32a5ee3bb0) ) + ROM_LOAD( "fr01.sc6", 0xf800, 0x800, CRC(55d688c6) SHA1(574a3a2ca73cabb4b8f3444aa4464e6d64daa3ad) ) +ROM_END + +ROM_START( schasercv ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1", 0x0000, 0x0400, CRC(bec2b16b) SHA1(c62210ecb64d7c38e5b63481d7fe04eb59bb1068) ) + ROM_LOAD( "2", 0x0400, 0x0400, CRC(9d25e608) SHA1(4cc52a93a3ab96a0ec1d07593e17832fa59b30a1) ) + ROM_LOAD( "3", 0x0800, 0x0400, CRC(113d0635) SHA1(ab5e98d0b5fc37d7d69bb5c541681a0f66460440) ) + ROM_LOAD( "4", 0x0c00, 0x0400, CRC(f3a43c8d) SHA1(29a7a8b7d1de763a255cfec79157fd95e7bff551) ) + ROM_LOAD( "5", 0x1000, 0x0400, CRC(47c84f23) SHA1(61b475fa92b8335f8edd3a128d8ac8561658e464) ) + ROM_LOAD( "6", 0x1400, 0x0400, CRC(02ff2199) SHA1(e12c235b2064cb4bb426145172e523256e3c6358) ) + ROM_LOAD( "7", 0x1800, 0x0400, CRC(87d06b88) SHA1(2d743161f85e47cb8ee2a600cbee790b1ad7ad99) ) + ROM_LOAD( "8", 0x1c00, 0x0400, CRC(6dfaad08) SHA1(2184c4e2f4b6bffdc4fe13e178134331fcd43253) ) + ROM_LOAD( "9", 0x4000, 0x0400, CRC(3d1a2ae3) SHA1(672ad6590aebdfebc2748455fa638107f3934c41) ) + ROM_LOAD( "10", 0x4400, 0x0400, CRC(037edb99) SHA1(f2fc5e61f962666e7f6bb81753ac24ea0b97e581) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 (not used, but they were on the board) */ + ROM_LOAD( "cv01", 0x0000, 0x0400, CRC(037e16ac) SHA1(d585030aaff428330c91ae94d7cd5c96ebdd67dd) ) + ROM_LOAD( "cv02", 0x0400, 0x0400, CRC(8263da38) SHA1(2e7c769d129e6f8a1a31eba1e02777bb94ac32b2) ) +ROM_END + +ROM_START( schaserc ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "45.ic30", 0x0000, 0x0400, CRC(ca90619c) SHA1(d2f9b29290d720c57f867d1dc193e877248e6afd) ) + ROM_LOAD( "46.ic36", 0x0400, 0x0400, CRC(6a016895) SHA1(6984d9d002e5d8fa14bdaf16f6ba9ca02136372c) ) + ROM_LOAD( "rt15.bin", 0x0800, 0x0400, CRC(2ac43a93) SHA1(d364f0940681a888c0147e06bcb01f8a0d4a24c8) ) + ROM_LOAD( "rt16.bin", 0x0c00, 0x0400, CRC(f5583afc) SHA1(5e8edb43ccb138fd47ac8f3da1af79b4444a4a82) ) + ROM_LOAD( "rt17.bin", 0x1000, 0x0400, CRC(51cf1155) SHA1(fd8c82d951602fd7e0ada65fc7cdee9f277c70db) ) + ROM_LOAD( "rt18.bin", 0x1400, 0x0400, CRC(3f0fc73a) SHA1(b801c3f1e8e6e41c564432db7c5891f6b27293b2) ) + ROM_LOAD( "rt19.bin", 0x1800, 0x0400, CRC(b66ea369) SHA1(d277f572f9c7c4301518546cf60671a6539326ee) ) + ROM_LOAD( "47.ic39", 0x1c00, 0x0400, CRC(d476e182) SHA1(87428bf0131f8bf39d506b8df424af94cd944d82) ) + ROM_LOAD( "rt21.bin", 0x4000, 0x0400, CRC(b368ac98) SHA1(6860efe0496955db67611183be0efecda92c9c98) ) + ROM_LOAD( "rt22.bin", 0x4400, 0x0400, CRC(6e060dfb) SHA1(614e2ecf676c3ea2f9ea869125cfffef2f713684) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "rt06.ic2", 0x0000, 0x0400, CRC(950cf973) SHA1(d22df09b325835a0057ccd0d54f827b374254ac6) ) +ROM_END + +ROM_START( lupin3 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "lp01.36", 0x0000, 0x0800, CRC(fd506ee8) SHA1(67ce62f24892f0eddf3e47913dff541f41493a17) ) + ROM_LOAD( "lp02.35", 0x0800, 0x0800, CRC(ec4225f8) SHA1(cd7360b3b339e5050075b498226070914fb7a031) ) + ROM_LOAD( "lp03.34", 0x1000, 0x0800, CRC(9307d377) SHA1(081f6c63ff2dcc549e44ab5ff5f5ddf99d544640) ) + ROM_LOAD( "lp04.33", 0x1800, 0x0800, CRC(e41e8b2b) SHA1(e67eaa8aeaf13f706afc17074fbbde3ad2cc9548) ) + ROM_LOAD( "lp05.32", 0x4000, 0x0800, CRC(f5c2faf4) SHA1(8d056f8c630e4659c02dd5da759dd497e4734292) ) + ROM_LOAD( "lp06.31", 0x4800, 0x0800, CRC(66289ab2) SHA1(fc9b4a7b7a08d43f34beaf1a8e68ed0ff6148534) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color map */ + ROM_LOAD( "lp08.1", 0x0000, 0x0400, CRC(33dbd03a) SHA1(1e0ae1cad1e9a90642886ae2ef726d3f383dd6cf) ) + ROM_LOAD( "lp09.2", 0x0400, 0x0400, CRC(9eaee652) SHA1(a4d2d8282ba825f3a8c0cc9bca16e1d36a0d0796) ) +ROM_END + +ROM_START( lupin3a ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "lp12.bin", 0x0000, 0x0800, CRC(68a7f47a) SHA1(dce99b3810331d7603fa468f1dea984e571f709b) ) + ROM_LOAD( "lp13.bin", 0x0800, 0x0800, CRC(cae9a17b) SHA1(a333ba7db45325996e3254ab36162bb7577e8a38) ) + ROM_LOAD( "lp14.bin", 0x1000, 0x0800, CRC(3553b9e4) SHA1(6affb5b6caf08f365c0dce669e44046295c3df91) ) + ROM_LOAD( "lp15.bin", 0x1800, 0x0800, CRC(acbeef64) SHA1(50d78cdc9938285b6bf9fa81fa0f6c30b23e0756) ) + ROM_LOAD( "lp16.bin", 0x4000, 0x0800, CRC(19fcdc54) SHA1(2f18ee8158321fff68886ffe793724001e8b18c2) ) + ROM_LOAD( "lp17.bin", 0x4800, 0x0800, CRC(66289ab2) SHA1(fc9b4a7b7a08d43f34beaf1a8e68ed0ff6148534) ) + ROM_LOAD( "lp18.bin", 0x5000, 0x0800, CRC(2f07b4ba) SHA1(982e4c437b39b45e23d15af1b2fc8c7aa3034559) ) +ROM_END + +ROM_START( polaris ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ps01-1.30", 0x0000, 0x0800, CRC(7d41007c) SHA1(168f002fe997aac6e4141292de826d389859bb04) ) + ROM_LOAD( "ps09.36", 0x0800, 0x0800, CRC(9a5c8cb2) SHA1(7a8c5d74f8b431072d9476d3ef65a3fe1d639813) ) + ROM_LOAD( "ps03-1.31", 0x1000, 0x0800, CRC(21f32415) SHA1(6ac9ae9b55e342729fe260147021ed3911a24dc2) ) + ROM_LOAD( "ps04.37", 0x1800, 0x0800, CRC(65694948) SHA1(de92a7f3e3ef732b573254baa60df60f8e068a5d) ) + ROM_LOAD( "ps05.32", 0x4000, 0x0800, CRC(772e31f3) SHA1(fa0b866b6df1a9217e286ca880b3bb3fb0644bf3) ) + ROM_LOAD( "ps10.38", 0x4800, 0x0800, CRC(3df77bac) SHA1(b3275c34b8d42df83df2c404c5b7d220aae651fa) ) + ROM_LOAD( "ps26", 0x5000, 0x0800, CRC(9d5c3d50) SHA1(a6acf9ca6e807625156cb1759269014d5830a44f) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "ps08.1b", 0x0000, 0x0400, CRC(164aa05d) SHA1(41c699ce45c76a60c71294f25d8df6c6e6c1280a) ) /* NEC B406 or compatible BPROM (82S137) */ + + ROM_REGION( 0x0100, "user1", 0 ) /* cloud graphics */ + ROM_LOAD( "ps07.2c", 0x0000, 0x0100, CRC(2953253b) SHA1(2fb851bc9652ca4e51d473b484ede6dab05f1b51) ) /* MB7052 or compatible BPROM (82S129) */ +ROM_END + +ROM_START( polarisa ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ps01.30", 0x0000, 0x0800, CRC(c04ce5a9) SHA1(62cc9b3b682ebecfb7600393862c65e26ff5263f) ) + ROM_LOAD( "ps09.36", 0x0800, 0x0800, CRC(9a5c8cb2) SHA1(7a8c5d74f8b431072d9476d3ef65a3fe1d639813) ) + ROM_LOAD( "ps03.31", 0x1000, 0x0800, CRC(8680d7ea) SHA1(7fd4b8a415666c36842fed80d2798b48f8b29d0d) ) + ROM_LOAD( "ps04.37", 0x1800, 0x0800, CRC(65694948) SHA1(de92a7f3e3ef732b573254baa60df60f8e068a5d) ) + ROM_LOAD( "ps05.32", 0x4000, 0x0800, CRC(772e31f3) SHA1(fa0b866b6df1a9217e286ca880b3bb3fb0644bf3) ) + ROM_LOAD( "ps10.38", 0x4800, 0x0800, CRC(3df77bac) SHA1(b3275c34b8d42df83df2c404c5b7d220aae651fa) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "ps08.1b", 0x0000, 0x0400, CRC(164aa05d) SHA1(41c699ce45c76a60c71294f25d8df6c6e6c1280a) ) /* NEC B406 or compatible BPROM (82S137) */ + + ROM_REGION( 0x0100, "user1", 0 ) /* cloud graphics */ + ROM_LOAD( "ps07.2c", 0x0000, 0x0100, CRC(2953253b) SHA1(2fb851bc9652ca4e51d473b484ede6dab05f1b51) ) /* MB7052 or compatible BPROM (82S129) */ +ROM_END + + +ROM_START( polariso ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "ps01.30", 0x0000, 0x0800, CRC(c04ce5a9) SHA1(62cc9b3b682ebecfb7600393862c65e26ff5263f) ) + ROM_LOAD( "ps02.36", 0x0800, 0x0800, CRC(18648e4f) SHA1(9f672e108177d5d9bc004b41eec00dc4d19269ff) ) + ROM_LOAD( "ps03.31", 0x1000, 0x0800, CRC(8680d7ea) SHA1(7fd4b8a415666c36842fed80d2798b48f8b29d0d) ) + ROM_LOAD( "ps04.37", 0x1800, 0x0800, CRC(65694948) SHA1(de92a7f3e3ef732b573254baa60df60f8e068a5d) ) + ROM_LOAD( "ps05.32", 0x4000, 0x0800, CRC(772e31f3) SHA1(fa0b866b6df1a9217e286ca880b3bb3fb0644bf3) ) + ROM_LOAD( "ps06.38", 0x4800, 0x0800, CRC(f577cb72) SHA1(7a931b5ebaf0d6941191f21afb9ed670d0251e07) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "ps08.1b", 0x0000, 0x0400, CRC(164aa05d) SHA1(41c699ce45c76a60c71294f25d8df6c6e6c1280a) ) /* NEC B406 or compatible BPROM (82S137) */ + + ROM_REGION( 0x0100, "user1", 0 ) /* cloud graphics */ + ROM_LOAD( "ps07.2c", 0x0000, 0x0100, CRC(2953253b) SHA1(2fb851bc9652ca4e51d473b484ede6dab05f1b51) ) /* MB7052 or compatible BPROM (82S129) */ +ROM_END + +ROM_START( polarisbr ) /* aka Polaris II on flyers? */ + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1", 0x0000, 0x0800, CRC(17015f52) SHA1(8beb4d927c08420f9990fac787a81d4bd6dd419c) ) + ROM_LOAD( "2", 0x0800, 0x0800, CRC(9a5c8cb2) SHA1(7a8c5d74f8b431072d9476d3ef65a3fe1d639813) ) + ROM_LOAD( "3", 0x1000, 0x0800, CRC(60118368) SHA1(e1189fd88b943fcf77a5c41c519cccdb8196910c) ) + ROM_LOAD( "4", 0x1800, 0x0800, CRC(65694948) SHA1(de92a7f3e3ef732b573254baa60df60f8e068a5d) ) + ROM_LOAD( "5", 0x4000, 0x0800, CRC(6cb21b31) SHA1(f9d435a3aa905f124cb87c139b047e1585d0997b) ) + ROM_LOAD( "6", 0x4800, 0x0800, CRC(3df77bac) SHA1(b3275c34b8d42df83df2c404c5b7d220aae651fa) ) + ROM_LOAD( "7", 0x5000, 0x0800, CRC(0d811b92) SHA1(09af62997e1e0da0525ab4f6ced775d3673d8f35) ) + + ROM_REGION( 0x0400, "proms", 0 ) /* background color map */ + ROM_LOAD( "ps08.1b", 0x0000, 0x0400, CRC(164aa05d) SHA1(41c699ce45c76a60c71294f25d8df6c6e6c1280a) ) /* NEC B406 or compatible BPROM (82S137) */ + + ROM_REGION( 0x0100, "user1", 0 ) /* cloud graphics */ + ROM_LOAD( "ps07.2c", 0x0000, 0x0100, CRC(2953253b) SHA1(2fb851bc9652ca4e51d473b484ede6dab05f1b51) ) /* MB7052 or compatible BPROM (82S129) */ +ROM_END + +ROM_START( ozmawars ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "mw01", 0x0000, 0x0800, CRC(31f4397d) SHA1(bba9765aadd608d19e2515a5edf8e0eceb70916a) ) + ROM_LOAD( "mw02", 0x0800, 0x0800, CRC(d8e77c62) SHA1(84fc81cf9a924ecbb13a008cd7435b7d465bddf6) ) + ROM_LOAD( "mw03", 0x1000, 0x0800, CRC(3bfa418f) SHA1(7318878202322a2263551ca463e4c70943401f68) ) + ROM_LOAD( "mw04", 0x1800, 0x0800, CRC(e190ce6c) SHA1(120898e9a683f5ce874c6fde761570a26de2fa8c) ) + ROM_LOAD( "mw05", 0x4000, 0x0800, CRC(3bc7d4c7) SHA1(b084f8cd2ce0f502c2e915da3eceffcbb448e9c0) ) + ROM_LOAD( "mw06", 0x4800, 0x0800, CRC(99ca2eae) SHA1(8d0f220f68043eff0c85d2de7bee7fd4365fb51c) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv/intruder */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +/* +------------------------------ +Ozma Wars by SHIN NIHON KIKAKU +------------------------------ +Location Type File ID Checksum +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +ROM IC36 2708 OZ1 8707 +ROM IC35 2708 OZ2 60A7 +ROM IC34 2708 OZ3 7504 +ROM IC33 2708 OZ4 55A1 +ROM IC32 2708 OZ5 6BC3 +ROM IC31 2708 OZ6 2808 +ROM IC42 2708 OZ7 FE8A +ROM IC41 2708 OZ8 C03B +ROM IC40 2708 OZ9 7515 +ROM IC39 2708 OZ10 4BD4 +ROM IC38 2708 OZ11 50BA +ROM IC37 2708 OZ12 3411 +Note: CPU - CPU board (AA017757) + AUD - Audio/IO board (CV070005) + ROM - ROM board (AA017756A) + - Uses Taito's three board colour version + of Space Invaders PCB +*/ + +ROM_START( ozmawars2 ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "oz1", 0x0000, 0x0400, CRC(9300830e) SHA1(7ed349f7ad01b30aefb41dcaf97e209d00f5af6c) ) + ROM_LOAD( "oz2", 0x0400, 0x0400, CRC(957fc661) SHA1(ac0edc901d8033619f62967f8eaf53a02947e109) ) + ROM_LOAD( "oz3", 0x0800, 0x0400, CRC(cf8f4d6c) SHA1(effb4dc48594e1b7164b37f683a5a78b1a9bdd4f) ) + ROM_LOAD( "oz4", 0x0c00, 0x0400, CRC(f51544a5) SHA1(368411a2dadaebcbb4d5b6cf6c2beec036ce817f) ) + ROM_LOAD( "oz5", 0x1000, 0x0400, CRC(5597bf52) SHA1(626c7348365ed974d416485d94d057745b5d9b96) ) + ROM_LOAD( "oz6", 0x1400, 0x0400, CRC(19b43578) SHA1(3609b7c77f5ee6f10f302892f56fcc8375577f20) ) + ROM_LOAD( "oz7", 0x1800, 0x0400, CRC(a285bfde) SHA1(ed7a9fce4d887d3b5d596645893ea87c0bafda02) ) + ROM_LOAD( "oz8", 0x1c00, 0x0400, CRC(ae59a629) SHA1(0c9ea67dc35f93ec65ec91e1dab2e4b6212428bf) ) + ROM_LOAD( "oz9", 0x4000, 0x0400, CRC(df0cc633) SHA1(3725af2e5a6e9ab08dd9ada345630de19c88ce73) ) + ROM_LOAD( "oz10", 0x4400, 0x0400, CRC(31b7692e) SHA1(043880750d134d04311eab55e30ee223977d3d17) ) + ROM_LOAD( "oz11", 0x4800, 0x0400, CRC(660e934c) SHA1(1d50ae3a9de041b908e256892203ce1738d588f6) ) + ROM_LOAD( "oz12", 0x4c00, 0x0400, CRC(8b969f61) SHA1(6d12cacc73c31a897812ccd8de24725ee56dd975) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + /* !! not dumped yet, these were taken from sisv/intruder */ + ROM_LOAD( "01.1", 0x0000, 0x0400, BAD_DUMP CRC(aac24f34) SHA1(ad110e776547fb48baac568bb50d61854537ca34) ) + ROM_LOAD( "02.2", 0x0400, 0x0400, BAD_DUMP CRC(2bdf83a0) SHA1(01ffbd43964c41987e7d44816271308f9a70802b) ) +ROM_END + +ROM_START( ozmawarsmr ) // single PCB marked CS 210. No PROMS. + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "73.1s", 0x0000, 0x0400, CRC(9300830e) SHA1(7ed349f7ad01b30aefb41dcaf97e209d00f5af6c) ) + ROM_LOAD( "74.1pr", 0x0400, 0x0400, CRC(957fc661) SHA1(ac0edc901d8033619f62967f8eaf53a02947e109) ) + ROM_LOAD( "75.1n", 0x0800, 0x0400, CRC(cf8f4d6c) SHA1(effb4dc48594e1b7164b37f683a5a78b1a9bdd4f) ) + ROM_LOAD( "76.1m", 0x0c00, 0x0400, CRC(f51544a5) SHA1(368411a2dadaebcbb4d5b6cf6c2beec036ce817f) ) + ROM_LOAD( "77.1l", 0x1000, 0x0400, CRC(4a653fe6) SHA1(22aee4c6cc3bd474d7159a552c4fb666b78fc4fb) ) + ROM_LOAD( "78.1kj", 0x1400, 0x0400, CRC(fb3db187) SHA1(bbf3e316215cefe2237115d766332ce185c8ca01) ) + ROM_LOAD( "79.1h", 0x1800, 0x0400, CRC(ed2d7c34) SHA1(f468b422e9f06522b034d213cebc914afb21dda1) ) + ROM_LOAD( "80.1g", 0x1c00, 0x0400, CRC(85728971) SHA1(400968f5c99b50416cdeefb4405989aa8012a3d1) ) + ROM_LOAD( "81.1ef", 0x4000, 0x0400, CRC(df0cc633) SHA1(3725af2e5a6e9ab08dd9ada345630de19c88ce73) ) + ROM_LOAD( "82.1d", 0x4400, 0x0400, CRC(31b7692e) SHA1(043880750d134d04311eab55e30ee223977d3d17) ) + ROM_LOAD( "83.1c", 0x4800, 0x0400, CRC(50257351) SHA1(5c3eb29f36f04b7fb8f0351ccf9c8cfc7587f927) ) + ROM_LOAD( "84.1b", 0x4c00, 0x0400, CRC(293303c9) SHA1(bd3770ff7cf6fa38b17cdfd0e0633d84c015dea7) ) +ROM_END + +ROM_START( solfight ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "solfight.m", 0x0000, 0x0800, CRC(a4f2814e) SHA1(e2437e3543dcc97eeaea32babcd4aec6455581ac) ) + ROM_LOAD( "solfight.n", 0x0800, 0x0800, CRC(5657ec07) SHA1(9a2fb398841160f59483bb70060caba37addb8a4) ) + ROM_LOAD( "solfight.p", 0x1000, 0x0800, CRC(ef9ce96d) SHA1(96867b4f2d72f3a8827b1eb3a0748922eaa8d608) ) + ROM_LOAD( "solfight.r", 0x1800, 0x0800, CRC(4f1ef540) SHA1(a798e57959e72bfb554dd2fed0e37027312f9ed3) ) + ROM_LOAD( "mw05", 0x4000, 0x0800, CRC(3bc7d4c7) SHA1(b084f8cd2ce0f502c2e915da3eceffcbb448e9c0) ) + ROM_LOAD( "solfight.t", 0x4800, 0x0800, CRC(3b6fb206) SHA1(db631f4a0bd5344d130ff8d723d949e9914b6f92) ) +ROM_END + +ROM_START( spaceph ) /* Also seen in a 6-rom version which matches contents exactly (sv01+sv02, sv03+sv04, etc)*/ + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "sv01.bin", 0x0000, 0x0400, CRC(de84771d) SHA1(13a7e5eedb826cca4d59634d38db9fcf5e65b732) ) + ROM_LOAD( "sv02.bin", 0x0400, 0x0400, CRC(957fc661) SHA1(ac0edc901d8033619f62967f8eaf53a02947e109) ) + ROM_LOAD( "sv03.bin", 0x0800, 0x0400, CRC(dbda38b9) SHA1(73a277616a0c236b07c9ffa66f16a27a78c12d70) ) + ROM_LOAD( "sv04.bin", 0x0c00, 0x0400, CRC(f51544a5) SHA1(368411a2dadaebcbb4d5b6cf6c2beec036ce817f) ) + ROM_LOAD( "sv05.bin", 0x1000, 0x0400, CRC(98d02683) SHA1(f13958df8d385f532e993e4c34569d992904a4ed) ) + ROM_LOAD( "sv06.bin", 0x1400, 0x0400, CRC(4ec390fd) SHA1(ade23efde5d55d282fbb28a5f8a1346601501b79) ) + ROM_LOAD( "sv07.bin", 0x1800, 0x0400, CRC(170862fd) SHA1(ac64a97b1510ca81d4ef3a5fcf45b7e6c7414914) ) + ROM_LOAD( "sv08.bin", 0x1c00, 0x0400, CRC(511b12cf) SHA1(08ba43024c8574ded11aa457eca24b72984f5ea9) ) + ROM_LOAD( "sv09.bin", 0x4000, 0x0400, CRC(af1cd1af) SHA1(286d77e8556e475b291a3b1a53acaca8b7dc3678) ) + ROM_LOAD( "sv10.bin", 0x4400, 0x0400, CRC(31b7692e) SHA1(043880750d134d04311eab55e30ee223977d3d17) ) + ROM_LOAD( "sv11.bin", 0x4800, 0x0400, CRC(50257351) SHA1(5c3eb29f36f04b7fb8f0351ccf9c8cfc7587f927) ) + ROM_LOAD( "sv12.bin", 0x4c00, 0x0400, CRC(a2a3366a) SHA1(87032787450216d378406122effa95ea01145bf7) ) +ROM_END + +ROM_START( ballbomb ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "tn01", 0x0000, 0x0800, CRC(551585b5) SHA1(7c17b046bdfca6ab107b7e68ba9bde6ca590c3d4) ) + ROM_LOAD( "tn02", 0x0800, 0x0800, CRC(7e1f734f) SHA1(a15656818cd730d9bc98d00ff1e7fe3f860bd624) ) + ROM_LOAD( "tn03", 0x1000, 0x0800, CRC(d93e20bc) SHA1(2bf72f813750cef8fad572a18fb8e9fd5bf38804) ) + ROM_LOAD( "tn04", 0x1800, 0x0800, CRC(d0689a22) SHA1(1f6b258431b7eb878853ff979e4d97a05fb6b797) ) + ROM_LOAD( "tn05-1", 0x4000, 0x0800, CRC(5d5e94f1) SHA1(b9f8ba38161ef4f0940c274e9d93fed4bb7db017) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "tn06", 0x0000, 0x0400, CRC(7ec554c4) SHA1(b638605ba2043fdca4c5e18755fa5fa81ed3db07) ) + ROM_LOAD( "tn07", 0x0400, 0x0400, CRC(deb0ac82) SHA1(839581c4e58cb7b0c2c14cf4f239220017cc26eb) ) + + ROM_REGION( 0x0100, "user1", 0 ) /* cloud graphics (missing) */ + ROM_LOAD( "mb7052.2c", 0x0000, 0x0100, NO_DUMP ) +ROM_END + +ROM_START( yosakdon ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "yd1.bin", 0x0000, 0x0400, CRC(607899c9) SHA1(219c0c99894715818606fba49cc75517f6f43e0c) ) + ROM_LOAD( "yd2.bin", 0x0400, 0x0400, CRC(78336df4) SHA1(b0b6254568d191d2d0b9c9280a3ccf2417ef3f38) ) + ROM_LOAD( "yd3.bin", 0x0800, 0x0400, CRC(c5af6d52) SHA1(c40af79fe060562c64fc316881b7d0348e11ee3f) ) + ROM_LOAD( "yd4.bin", 0x0c00, 0x0400, CRC(dca8064f) SHA1(77a58137cc7f0b5fbe0e9e8deb9c5be88b1ebbcf) ) + ROM_LOAD( "yd5.bin", 0x1400, 0x0400, CRC(38804ff1) SHA1(9b7527b9d2b106355f0c8df46666b1e3f286b2e3) ) + ROM_LOAD( "yd6.bin", 0x1800, 0x0400, CRC(988d2362) SHA1(deaf864b4e287cbc2585c2a11343b1ae82e15463) ) + ROM_LOAD( "yd7.bin", 0x1c00, 0x0400, CRC(2744e68b) SHA1(5ad5a7a615d36f57b6d560425e035c15e25e9005) ) +ROM_END + +ROM_START( yosakdona ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "yosaku1", 0x0000, 0x0400, CRC(d132f4f0) SHA1(373c7ea1bd6debcb3dad5881793b8c31dc7a01e6) ) + ROM_LOAD( "yd2.bin", 0x0400, 0x0400, CRC(78336df4) SHA1(b0b6254568d191d2d0b9c9280a3ccf2417ef3f38) ) + ROM_LOAD( "yosaku3", 0x0800, 0x0400, CRC(b1a0b3eb) SHA1(4eb80668920b45dc6216424f8ca53d753a35f4f1) ) + ROM_LOAD( "yosaku4", 0x0c00, 0x0400, CRC(c06c225e) SHA1(2699e3c13b09b6de16bd3ca3ca2e9d7a91b7e268) ) + ROM_LOAD( "yosaku5", 0x1400, 0x0400, CRC(ae422a43) SHA1(5219680f9d6c5d984b29167f85106fa375856121) ) + ROM_LOAD( "yosaku6", 0x1800, 0x0400, CRC(26b24a12) SHA1(387589fa4027d41b6fb06555661d4f92fe2f990c) ) + ROM_LOAD( "yosaku7", 0x1c00, 0x0400, CRC(878d5a18) SHA1(6adc8763d5644602eed7fe6d9186a48be105aace) ) +ROM_END + +ROM_START( indianbt ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.36", 0x0000, 0x0800, CRC(ddc2b25d) SHA1(120ae17492b79d7d2ad515de9f1e3be7f8b9d4eb) ) + ROM_LOAD( "2.35", 0x0800, 0x0800, CRC(6499b062) SHA1(62a301d532b9fc4e7a17cbe8d2061eb0e842bdfa) ) + ROM_LOAD( "3.34", 0x1000, 0x0800, CRC(5c51675d) SHA1(1313e8794ee6cd0252452b96d42cff7907eeaa21) ) + ROM_LOAD( "4.33", 0x1800, 0x0800, CRC(70ebec95) SHA1(f6e1e7a28033d89e49b88c559ea8926b1b4ff21b) ) + ROM_LOAD( "5.32", 0x4000, 0x0800, CRC(7b4022f4) SHA1(10dec8110e8f4bc79764d3183bdfb3c135e27faf) ) + ROM_LOAD( "6.31", 0x4800, 0x0800, CRC(89bd6f73) SHA1(5dc63871252c530ef0aae4f4cd02fee44b397815) ) + ROM_LOAD( "7.42", 0x5000, 0x0800, CRC(7060ba0b) SHA1(366ce02b7b0a3391afef23b8b41cd98a91034830) ) + ROM_LOAD( "8.41", 0x5800, 0x0800, CRC(eaccfc0a) SHA1(c6c2d702243bdd1d2ad5fbaaceadb5a5798577bc) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "mb7054.1", 0x0000, 0x0400, CRC(4acf4db3) SHA1(842a6c9f91806b424b7cc437670b4fe0bd57dff1) ) + ROM_LOAD( "mb7054.2", 0x0400, 0x0400, CRC(62cb3419) SHA1(3df65062945589f1df37359dbd3e30ae4b23f469) ) +ROM_END + +ROM_START( indianbtbr ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.36", 0x0000, 0x0800, CRC(5cf6316b) SHA1(9812fbb7139d6f33a832a2485f9cd6422146d1ae) ) // sldh + ROM_LOAD( "2.35", 0x0800, 0x0800, CRC(882c7421) SHA1(b2cc15c8693bd1fc74dddfcf52bf08984423f4bf) ) // sldh + ROM_LOAD( "3.34", 0x1000, 0x0800, CRC(5c51675d) SHA1(1313e8794ee6cd0252452b96d42cff7907eeaa21) ) + ROM_LOAD( "4.33", 0x1800, 0x0800, CRC(70ebec95) SHA1(f6e1e7a28033d89e49b88c559ea8926b1b4ff21b) ) + ROM_LOAD( "5.32", 0x4000, 0x0800, CRC(aa12dbae) SHA1(083425b82cfdc0f037afcf293ad03b98fc6af3e5) ) // sldh + ROM_LOAD( "6.31", 0x4800, 0x0800, CRC(d9cb1691) SHA1(c13cd8479914ba6719427b408ed589c9892f832c) ) // sldh + ROM_LOAD( "7.42", 0x5000, 0x0800, CRC(7060ba0b) SHA1(366ce02b7b0a3391afef23b8b41cd98a91034830) ) + ROM_LOAD( "8.41", 0x5800, 0x0800, CRC(e96699d6) SHA1(701d370ae28608221fb4d00e12877d30122c848e) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 */ + ROM_LOAD( "mb7054.1", 0x0000, 0x0400, CRC(4acf4db3) SHA1(842a6c9f91806b424b7cc437670b4fe0bd57dff1) ) + ROM_LOAD( "mb7054.2", 0x0400, 0x0400, CRC(62cb3419) SHA1(3df65062945589f1df37359dbd3e30ae4b23f469) ) +ROM_END + +ROM_START( shuttlei ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.13c", 0x0000, 0x0400, CRC(b6d4f0cd) SHA1(f855a793e78ff6283288c815b59e6942513ab4f8) ) + ROM_LOAD( "2.11c", 0x0400, 0x0400, CRC(168d6138) SHA1(e0e5ba58eb5a3a00802504c48a96d63522f9865f) ) + ROM_LOAD( "3.13d", 0x0800, 0x0400, CRC(804bd7fb) SHA1(f019bcc2894f9b819a14c069de8f1a7d228b79eb) ) + ROM_LOAD( "4.11d", 0x0c00, 0x0400, CRC(8205b369) SHA1(685dd244881f5762d0f53cbfa935da2b857e3fba) ) + ROM_LOAD( "5.13e", 0x1000, 0x0400, CRC(b50df820) SHA1(27a846ac3da4c0890a80f60483ed5750cb0b2476) ) + ROM_LOAD( "8.11f", 0x1c00, 0x0400, CRC(4978552b) SHA1(5a6b6e39f57a353580ed9281d7da24950f058426) ) + + ROM_REGION( 0x0100, "proms", 0 ) + ROM_LOAD( "82s129.2b", 0x0000, 0x0100, CRC(f108d00d) SHA1(de0cb9d18e4c9920495011f962c4497a789f651f) ) +ROM_END + +ROM_START( skylove ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "01", 0x0000, 0x0400, CRC(391ad7d0) SHA1(73358fff44da5fffd4e08fbb615ccc0245e3365b) ) + ROM_LOAD( "02", 0x0400, 0x0400, CRC(365ba070) SHA1(8493bde493ea0d04b3563f9bc752a6ec57022524) ) + ROM_LOAD( "03", 0x0800, 0x0400, CRC(47364dad) SHA1(b49704f8d49a0866cb9cd8bb867f30246e3dabc9) ) + ROM_LOAD( "04", 0x0c00, 0x0400, CRC(9d76f33d) SHA1(5aa6a081a3609e6c036843049d58cc763a86fedb) ) + ROM_LOAD( "05", 0x1000, 0x0400, CRC(09084954) SHA1(f5c826188ffb7a572c45aad94e794f31bebfebe5) ) + ROM_LOAD( "06", 0x1400, 0x0400, CRC(6d494e82) SHA1(8e5ee1b842621cd088e80124b92b8a517e8dfbb9) ) + ROM_LOAD( "07", 0x1800, 0x0400, CRC(1a9aa4b8) SHA1(0da553c6343a2740312ebafc2b936ffbbf24af04) ) + ROM_LOAD( "08", 0x1c00, 0x0400, CRC(ecaacacc) SHA1(b815366d3aaa8ef311cd54a5be9fb4d60324e5a7) ) +ROM_END + + +ROM_START( darthvdr ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "rom0", 0x0000, 0x0400, CRC(b15785b6) SHA1(f453a006019dc83bd746f3a26736e913186332e6) ) + ROM_LOAD( "rom1", 0x0400, 0x0400, CRC(95947743) SHA1(59f414de21f680e0d68ca8c4b6b538c8006cfdd6) ) + ROM_LOAD( "rom2", 0x0800, 0x0400, CRC(19b1731f) SHA1(2383c241de8a1ed57f03ecc7ded97585a6c10c91) ) + ROM_LOAD( "rom3", 0x0c00, 0x0400, CRC(ca1b5e3c) SHA1(e54ca4a3f36b2ed5e4e42c1e8bbbde43c92796e9) ) + ROM_LOAD( "rom4", 0x1000, 0x0400, CRC(eede5f41) SHA1(cd9f023057eb9598bad01b9e9d91bb4866b9bd3b) ) + ROM_LOAD( "rom5", 0x1400, 0x0400, CRC(cc52a4bb) SHA1(857b75a8b01fc707db940197d6bf3b0466c4a7b5) ) +ROM_END + +ROM_START( astropal ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "2708.0a", 0x0000, 0x0400, CRC(e6883322) SHA1(05b0ab0dc6297209dcfdd173e762bfae3a720e8d) ) + ROM_LOAD( "2708.1a", 0x0400, 0x0400, CRC(4401df1d) SHA1(16f3b957278aa67cb37bcd5defb6e4dd8ccf7d1f) ) + ROM_LOAD( "2708.2a", 0x0800, 0x0400, CRC(5bac1ee4) SHA1(8c3e5f882f4798f8ed0523b60a216c989324a7c2) ) + ROM_LOAD( "2708.3a", 0x0c00, 0x0400, CRC(a870afad) SHA1(1a256db2bc6baa238ee1df4eff2fdce0888f812c) ) + ROM_LOAD( "2708.4a", 0x1000, 0x0400, CRC(8bd2d985) SHA1(3ff9110c1bad7d4562664da772d14750d738c2d6) ) + ROM_LOAD( "2708.5a", 0x1400, 0x0400, CRC(5e97a86b) SHA1(f3500d48ecb3969b8aaea9c4e812fbf6cf4170af) ) + ROM_LOAD( "2708.6a", 0x1800, 0x0400, CRC(22c354d0) SHA1(c465ca5787ad8de3be97deac1214d3abd0b27e6b) ) + ROM_LOAD( "2708.7a", 0x1c00, 0x0400, CRC(aeca51c1) SHA1(767bca1e6bca41327b9ff6c3570edcabe46dec21) ) +ROM_END + +ROM_START( steelwkr ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1.36", 0x0000, 0x0400, CRC(5d78873a) SHA1(293cbc067937668148181453877239cb5ed57600) ) + ROM_LOAD( "2.35", 0x0400, 0x0400, CRC(99cd70c6) SHA1(a08bf4db6b39d22dfcf052cc6603aab041db0208) ) + ROM_LOAD( "3.34", 0x0800, 0x0400, CRC(18103b67) SHA1(45929ea56ab15769fc68873570aab3d403e8e913) ) + ROM_LOAD( "4.33", 0x0c00, 0x0400, CRC(c413ae82) SHA1(302b933b45b2aaa515434b5268fd74aec4160e3f) ) + ROM_LOAD( "5.32", 0x1000, 0x0400, CRC(ca7b07b5) SHA1(cbea221c4daf84825f99bbef6d731fc2ef88feeb) ) + ROM_LOAD( "6.31", 0x1400, 0x0400, CRC(f8181fa0) SHA1(a907611529a1500a2ae118e834c2d4b6d11974f1) ) + ROM_LOAD( "7.42", 0x1800, 0x0400, CRC(a35f113e) SHA1(53073037db55c14055810c0bee7b85eb75bbaa72) ) + ROM_LOAD( "8.41", 0x1c00, 0x0400, CRC(af208370) SHA1(ccbd002accda26cc0a02987d9801a47e5f49921a) ) + + ROM_REGION( 0x0800, "proms", 0 ) /* color maps player 1/player 2 (not used, but they were on the board) */ + ROM_LOAD( "la05.1", 0x0000, 0x0400, CRC(98f31392) SHA1(ccdd1bd2ddd24bd6b1f8255a87e138f937eaf5b4) ) + ROM_LOAD( "la06.2", 0x0400, 0x0400, CRC(98f31392) SHA1(ccdd1bd2ddd24bd6b1f8255a87e138f937eaf5b4) ) +ROM_END + +ROM_START( galactic ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1", 0x0000, 0x0800, CRC(b5098f1e) SHA1(9d1d045d8abeafd4716d3052fe93e52c6b347049) ) // sldh + ROM_LOAD( "2", 0x0800, 0x0800, CRC(f97410ee) SHA1(47f1f296c905fa13f6c521edc12c10f1f0e42400) ) + ROM_LOAD( "3", 0x1000, 0x0800, CRC(c1175feb) SHA1(83bf955ed3a52e1ce8c688d89725d8dee1bcc866) ) + ROM_LOAD( "4", 0x1800, 0x0800, CRC(b4451d7c) SHA1(62a18e8e927ef00a7f6cb933cdc5aeae9f074dc0) ) + ROM_LOAD( "5", 0x4000, 0x0800, CRC(74c9da61) SHA1(cb98105729f0fa4343b71af3c658b378ade1ed46) ) + ROM_LOAD( "6", 0x4800, 0x0800, CRC(5e7c6c44) SHA1(be7eeef10462377909018cf40503766f38466022) ) + ROM_LOAD( "7", 0x5000, 0x0800, CRC(02619e18) SHA1(4c59f17fbc96ca08090f08c41ca9fc72c074e9c0) ) +ROM_END + +ROM_START( spacmiss ) + ROM_REGION( 0x10000, "maincpu", 0 ) + ROM_LOAD( "1", 0x0000, 0x0800, CRC(e212dc88) SHA1(bc56052bf43d18081f777b936b2be792e91ba842) ) // sldh + ROM_LOAD( "2", 0x0800, 0x0800, CRC(f97410ee) SHA1(47f1f296c905fa13f6c521edc12c10f1f0e42400) ) + ROM_LOAD( "3", 0x1000, 0x0800, CRC(c1175feb) SHA1(83bf955ed3a52e1ce8c688d89725d8dee1bcc866) ) + ROM_LOAD( "4", 0x1800, 0x0800, CRC(b4451d7c) SHA1(62a18e8e927ef00a7f6cb933cdc5aeae9f074dc0) ) + ROM_LOAD( "5", 0x4000, 0x0800, CRC(74c9da61) SHA1(cb98105729f0fa4343b71af3c658b378ade1ed46) ) + ROM_LOAD( "6", 0x4800, 0x0800, CRC(5e7c6c44) SHA1(be7eeef10462377909018cf40503766f38466022) ) + ROM_LOAD( "7", 0x5000, 0x0800, CRC(02619e18) SHA1(4c59f17fbc96ca08090f08c41ca9fc72c074e9c0) ) + + ROM_REGION( 0x0800, "user1", 0 ) + ROM_LOAD( "8", 0x0000, 0x0800, CRC(942e5261) SHA1(e8af51d644eab4e7b31c14dc66bb036ad8940c42) ) // ? +ROM_END + +ROM_START( attackfc ) + ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 ) + ROM_LOAD( "30a.bin", 0x0000, 0x0400, CRC(c12e3386) SHA1(72b1d3d67a83edf0be0b0c37ef6dcffba450f16f) ) + ROM_LOAD( "36a.bin", 0x0400, 0x0400, CRC(6738dcb9) SHA1(e4c68553fc3f2d3db3d251b9cb325e2409d9c02a) ) + ROM_LOAD( "31a.bin", 0x0800, 0x0400, CRC(787a4658) SHA1(5be3143bdba6a32256603be94400034a8ea1fda6) ) + ROM_LOAD( "37a.bin", 0x0c00, 0x0400, CRC(ad6bfbbe) SHA1(5f5437b6c8e7dfe9649b25040862f8a51d8c43ed) ) + ROM_LOAD( "32a.bin", 0x1000, 0x0400, CRC(cbe0a711) SHA1(6e5f4214a4b48b70464005f4263c9b1ec3cbbeb1) ) + ROM_LOAD( "33a.bin", 0x1800, 0x0400, CRC(53147393) SHA1(57e078f1734e382e8a46be09c133daab30c75681) ) + ROM_LOAD( "39a.bin", 0x1c00, 0x0400, CRC(f538cf08) SHA1(4a375a41ab5d9f0d9f9a2ebef4c448038c139204) ) +ROM_END + + +/* board # rom parent machine inp init monitor, .. */ + +// Taito games (+clones), starting with Space Invaders +GAME( 1978, sisv1, invaders, invaders, sitv, driver_device, 0, ROT270, "Taito", "Space Invaders (SV Version rev 1)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 1978, sisv2, invaders, invaders, sitv, driver_device, 0, ROT270, "Taito", "Space Invaders (SV Version rev 2)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 1978, sisv3, invaders, invaders, sitv, driver_device, 0, ROT270, "Taito", "Space Invaders (SV Version rev 3)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 1978, sisv, invaders, invaders, sitv, driver_device, 0, ROT270, "Taito", "Space Invaders (SV Version rev 4)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAMEL(1978, sitv1, invaders, invaders, sitv, driver_device, 0, ROT270, "Taito", "Space Invaders (TV Version rev 1)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1978, sitv, invaders, invaders, sitv, driver_device, 0, ROT270, "Taito", "Space Invaders (TV Version rev 2)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAME( 1979, sicv, invaders, invadpt2, sicv, driver_device, 0, ROT270, "Taito", "Space Invaders (CV Version, larger roms)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 1979, sicv1, invaders, invadpt2, sicv, driver_device, 0, ROT270, "Taito", "Space Invaders (CV Version, smaller roms)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAMEL(1978, invadrmr, invaders, invaders, invadrmr, driver_device, 0, ROT270, "Taito / Model Racing", "Space Invaders (Model Racing)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // unclassified, licensed or bootleg? +GAMEL(1978, invaderl, invaders, invaders, sicv, driver_device, 0, ROT270, "Taito / Logitec", "Space Invaders (Logitec)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // unclassified, licensed or bootleg? +GAMEL(1978, spcewars, invaders, spcewars, spcewars, driver_device, 0, ROT270, "Taito / Sanritsu", "Space War (Sanritsu)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE, layout_invaders ) // unclassified, licensed or bootleg? +GAMEL(1978, spceking, invaders, invaders, sicv, driver_device, 0, ROT270, "Taito / Leijac Corporation", "Space King", MACHINE_SUPPORTS_SAVE, layout_invaders ) // unclassified, licensed or bootleg? +GAMEL(1979, cosmicmo, invaders, cosmicmo, cosmicmo, driver_device, 0, ROT270, "Taito / Universal", "Cosmic Monsters (version II)", MACHINE_SUPPORTS_SAVE, layout_cosmicm ) // unclassified, licensed or bootleg? +GAMEL(1979, cosmicm2, invaders, cosmicmo, cosmicmo, driver_device, 0, ROT270, "Taito / Universal", "Cosmic Monsters 2", MACHINE_SUPPORTS_SAVE, layout_cosmicm ) // unclassified, licensed or bootleg? +GAMEL(1980?,sinvzen, invaders, invaders, sinvzen, driver_device, 0, ROT270, "Taito / Zenitone-Microsec Ltd.", "Super Invaders (Zenitone-Microsec)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // unclassified, licensed or bootleg? +GAMEL(1980, ultrainv, invaders, invaders, sicv, driver_device, 0, ROT270, "Taito / Konami", "Ultra Invaders", MACHINE_SUPPORTS_SAVE, layout_invaders ) // unclassified, licensed or bootleg? +GAMEL(1978, spaceatt, invaders, invaders, sicv, driver_device, 0, ROT270, "bootleg (Video Games GmbH)", "Space Attack (bootleg of Space Invaders)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1978, spaceattbp, invaders, invaders, sicv, driver_device, 0, ROT270, "bootleg (Video Games GmbH)", "Space Attack (bproms)(bootleg of Space Invaders)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1978, spaceatt2k, invaders, invaders, sicv, driver_device, 0, ROT270, "bootleg (Video Games GmbH)", "Space Attack (2k roms)(bootleg of Space Invaders)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1978, cosmicin, invaders, invaders, sicv, driver_device, 0, ROT270, "bootleg", "Cosmic Invaders (bootleg of Space Invaders)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1978, galmonst, invaders, invaders, sicv, driver_device, 0, ROT270, "bootleg (Laguna S.A.)", "Galaxy Monsters (Laguna S.A. Spanish bootleg of Space Invaders)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1980, spaceat2, invaders, invaders, spaceat2, driver_device, 0, ROT270, "bootleg (Video Games UK)", "Space Attack II (bootleg of Super Invaders)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // bootleg of Zenitone-Microsec Super Invaders +GAMEL(1979, spacecom, invaders, spacecom, spacecom, _8080bw_state, spacecom, ROT270, "bootleg", "Space Combat (bootleg of Space Invaders)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE, layout_spacecom ) +GAME( 1978, spacerng, invaders, spacerng, sitv, driver_device, 0, ROT90, "bootleg (Leisure Time Electronics)", "Space Ranger (bootleg of Space Invaders)", MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) // many modifications +GAMEL(19??, invasion, invaders, invaders, invasion, driver_device, 0, ROT270, "bootleg (Sidam)", "Invasion (Sidam)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(19??, invasiona, invaders, invaders, invasion, driver_device, 0, ROT270, "bootleg", "Invasion (bootleg set 1, normal graphics)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // has Sidam replaced with 'Ufo Monster Attack' and standard GFX +GAMEL(19??, invasionb, invaders, invaders, invasion, driver_device, 0, ROT270, "bootleg", "Invasion (bootleg set 2, no copyright)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(19??, invasionrz, invaders, invaders, invasion, driver_device, 0, ROT270, "bootleg (R Z SRL Bologna)", "Invasion (bootleg set 3, R Z SRL Bologna)", MACHINE_SUPPORTS_SAVE | MACHINE_NOT_WORKING, layout_invaders ) +GAMEL(19??, invasionrza,invaders, invaders, invasion, driver_device, 0, ROT270, "bootleg (R Z SRL Bologna)", "Invasion (bootleg set 4, R Z SRL Bologna)", MACHINE_SUPPORTS_SAVE | MACHINE_NOT_WORKING, layout_invaders ) +GAMEL(19??, invadersem, invaders, invaders, sitv, driver_device, 0, ROT270, "Electromar", "Space Invaders (Electromar, Spanish)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // possibly licensed +GAMEL(1978, superinv, invaders, invaders, superinv, driver_device, 0, ROT270, "bootleg", "Super Invaders (bootleg set 1)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // not related to Zenitone-Microsec version +GAMEL(1978, sinvemag, invaders, invaders, sinvemag, driver_device, 0, ROT270, "bootleg (Emag)", "Super Invaders (bootleg set 2)", MACHINE_SUPPORTS_SAVE, layout_invaders ) // not related to Zenitone-Microsec version +GAMEL(1980, searthin, invaders, invaders, searthin, driver_device, 0, ROT270, "bootleg (Competitive Video)", "Super Earth Invasion (set 1)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1980, searthina, invaders, invaders, searthin, driver_device, 0, ROT270, "bootleg (Competitive Video)", "Super Earth Invasion (set 2)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1980, searthie, invaders, invaders, searthin, driver_device, 0, ROT270, "bootleg (Electrocoin)", "Super Earth Invasion (set 3)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(19??, alieninv, invaders, invaders, alieninv, driver_device, 0, ROT270, "bootleg (Margamatics)", "Alien Invasion", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(19??, alieninvp2, invaders, invaders, searthin, driver_device, 0, ROT270, "bootleg", "Alien Invasion Part II", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1979, jspecter, invaders, invaders, jspecter, driver_device, 0, ROT270, "bootleg (Jatre)", "Jatre Specter (set 1)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1979, jspecter2, invaders, invaders, jspecter, driver_device, 0, ROT270, "bootleg (Jatre)", "Jatre Specter (set 2)", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAMEL(1978, spacewr3, invaders, spcewars, sicv, driver_device, 0, ROT270, "bootleg", "Space War Part 3", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE, layout_invaders ) // unrelated to Sanritsu's version? +GAMEL(1978, invader4, invaders, invaders, sicv, driver_device, 0, ROT270, "bootleg", "Space Invaders Part Four", MACHINE_SUPPORTS_SAVE, layout_invaders ) +GAME( 1978, darthvdr, invaders, darthvdr, darthvdr, driver_device, 0, ROT270, "bootleg", "Darth Vader (bootleg of Space Invaders)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAMEL(19??, tst_invd, invaders, invaders, sicv, driver_device, 0, ROT0, "", "Space Invaders Test ROM", MACHINE_SUPPORTS_SAVE, layout_invaders ) + +// other Taito +GAME( 1979, invadpt2, 0, invadpt2, invadpt2, driver_device, 0, ROT270, "Taito", "Space Invaders Part II (Taito)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1979, invadpt2br, invadpt2, invadpt2, invadpt2, driver_device, 0, ROT270, "Taito do Brasil", "Space Invaders Part II (Brazil)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1980, invaddlx, invadpt2, invaders, invadpt2, driver_device, 0, ROT270, "Taito (Midway license)", "Space Invaders Deluxe", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, moonbase, invadpt2, invadpt2, invadpt2, driver_device, 0, ROT270, "Taito / Nichibutsu", "Moon Base (set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) // this has a 'Taito Corp' string hidden away in the rom - how do you get it to display? +GAME( 1979, moonbasea, invadpt2, invadpt2, invadpt2, driver_device, 0, ROT270, "Taito / Nichibutsu", "Moon Base (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) // this has the same string replaced with Nichibutsu, no other differences + +GAME( 1980, spclaser, 0, invadpt2, spclaser, driver_device, 0, ROT270, "Taito", "Space Laser", MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE ) +GAME( 1980, intruder, spclaser, invadpt2, spclaser, driver_device, 0, ROT270, "Taito (Game Plan license)", "Intruder", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1980, laser, spclaser, invadpt2, spclaser, driver_device, 0, ROT270, "bootleg (Leisure Time Electronics)", "Astro Laser (bootleg of Space Laser)", MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE ) +GAME( 1979, spcewarl, spclaser, invadpt2, spclaser, driver_device, 0, ROT270, "Leijac Corporation", "Space War (Leijac Corporation)", MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE ) // Taito's version is actually a spin-off of this? + +GAME( 1979, lrescue, 0, lrescue, lrescue, driver_device, 0, ROT270, "Taito", "Lunar Rescue", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1979, grescue, lrescue, lrescue, lrescue, driver_device, 0, ROT270, "Taito (Universal license?)", "Galaxy Rescue", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1980, mlander, lrescue, lrescue, lrescue, driver_device, 0, ROT270, "bootleg (Leisure Time Electronics)", "Moon Lander (bootleg of Lunar Rescue)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, lrescuem, lrescue, lrescue, lrescue, driver_device, 0, ROT270, "bootleg (Model Racing)", "Lunar Rescue (Model Racing bootleg, set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1979, lrescuem2, lrescue, lrescue, lrescue, driver_device, 0, ROT270, "bootleg (Model Racing)", "Lunar Rescue (Model Racing bootleg, set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1979, desterth, lrescue, lrescue, lrescue, driver_device, 0, ROT270, "bootleg", "Destination Earth (bootleg of Lunar Rescue)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAMEL( 1980,escmars, lrescue, escmars, lrescue, driver_device, 0, ROT270, "bootleg", "Escape from Mars (bootleg of Lunar Rescue)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND, layout_escmars ) + +GAME( 1979, schaser, 0, schaser, schaser, driver_device, 0, ROT270, "Taito", "Space Chaser (set 1)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, schasera, schaser, schaser, schaser, driver_device, 0, ROT270, "Taito", "Space Chaser (set 2)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, schaserb, schaser, schaser, schaser, driver_device, 0, ROT270, "Taito", "Space Chaser (set 3)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, schaserc, schaser, schaser, schaser, driver_device, 0, ROT270, "Taito", "Space Chaser (set 4)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_COLORS ) +GAME( 1979, schasercv, schaser, schasercv, schasercv, driver_device, 0, ROT270, "Taito", "Space Chaser (CV version - set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_COLORS ) +GAME( 1979, schaserm, schaser, schaser, schaserm, driver_device, 0, ROT270, "bootleg (Model Racing)", "Space Chaser (Model Racing bootleg)", MACHINE_SUPPORTS_SAVE ) // on original Taito PCB, hacked to be harder? + +GAME( 1979, sflush, 0, sflush, sflush, driver_device, 0, ROT270, "Taito", "Straight Flush", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND | MACHINE_IMPERFECT_COLORS | MACHINE_NO_COCKTAIL) + +GAME( 1980, lupin3, 0, lupin3, lupin3, driver_device, 0, ROT270, "Taito", "Lupin III (set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1980, lupin3a, lupin3, lupin3a, lupin3a, driver_device, 0, ROT270, "Taito", "Lupin III (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) + +GAME( 1980, polaris, 0, polaris, polaris, driver_device, 0, ROT270, "Taito", "Polaris (Latest version)", MACHINE_SUPPORTS_SAVE ) +GAME( 1980, polarisa, polaris, polaris, polaris, driver_device, 0, ROT270, "Taito", "Polaris (First revision)", MACHINE_SUPPORTS_SAVE ) +GAME( 1980, polariso, polaris, polaris, polaris, driver_device, 0, ROT270, "Taito", "Polaris (Original version)", MACHINE_SUPPORTS_SAVE ) +GAME( 1981, polarisbr, polaris, polaris, polaris, driver_device, 0, ROT270, "Taito do Brasil", "Polaris (Brazil)", MACHINE_SUPPORTS_SAVE ) + +GAME( 1980, ballbomb, 0, ballbomb, ballbomb, driver_device, 0, ROT270, "Taito", "Balloon Bomber", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS ) /* missing clouds */ + +GAME( 1980, indianbt, 0, indianbt, indianbt, driver_device, 0, ROT270, "Taito", "Indian Battle", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1983, indianbtbr, indianbt, indianbtbr,indianbtbr,driver_device, 0, ROT270, "Taito do Brasil", "Indian Battle (Brazil)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) + +GAME( 1980, steelwkr, 0, steelwkr, steelwkr, driver_device, 0, ROT0 , "Taito", "Steel Worker", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) + +GAMEL(1980?,galactic, 0, invaders, galactic, driver_device, 0, ROT270, "Taito do Brasil", "Galactica - Batalha Espacial", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND, layout_galactic ) +GAMEL(1980?,spacmiss, galactic, invaders, galactic, driver_device, 0, ROT270, "bootleg?", "Space Missile - Space Fighting Game", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND, layout_galactic ) + +// Misc. manufacturers +GAME( 1979, galxwars, 0, invadpt2, galxwars, driver_device, 0, ROT270, "Universal", "Galaxy Wars (Universal set 1)", MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE ) +GAME( 1979, galxwars2, galxwars, invadpt2, galxwars, driver_device, 0, ROT270, "Universal", "Galaxy Wars (Universal set 2)", MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE ) +GAME( 1979, galxwarst, galxwars, invadpt2, galxwars, driver_device, 0, ROT270, "Universal (Taito license?)", "Galaxy Wars (Taito?)" , MACHINE_WRONG_COLORS | MACHINE_SUPPORTS_SAVE ) // Copyright not displayed +GAME( 1979, starw, galxwars, invaders, galxwars, driver_device, 0, ROT270, "bootleg", "Star Wars (bootleg of Galaxy Wars, set 1)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, starw1, galxwars, starw1, galxwars, driver_device, 0, ROT270, "bootleg (Yamashita)", "Star Wars (bootleg of Galaxy Wars, set 2)", MACHINE_SUPPORTS_SAVE ) + +GAME( 1979, cosmo, 0, cosmo, cosmo, driver_device, 0, ROT90, "TDS & MINTS", "Cosmo", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) + +GAME( 1980?,invrvnge, 0, invrvnge, invrvnge, driver_device, 0, ROT270, "Zenitone-Microsec Ltd.", "Invader's Revenge (set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND ) // copyright is either late-1980, or early-1981 +GAME( 1980?,invrvngea, invrvnge, invrvnge, invrvnge, driver_device, 0, ROT270, "Zenitone-Microsec Ltd.", "Invader's Revenge (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND ) +GAME( 1980?,invrvngeb, invrvnge, invrvnge, invrvnge, driver_device, 0, ROT270, "Zenitone-Microsec Ltd.", "Invader's Revenge (set 3)", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND ) +GAME( 1980?,invrvngedu, invrvnge, invrvnge, invrvnge, driver_device, 0, ROT270, "Zenitone-Microsec Ltd. (Dutchford license)", "Invader's Revenge (Dutchford, single PCB)", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND ) +GAME( 1980?,invrvngegw, invrvnge, invrvnge, invrvnge, driver_device, 0, ROT270, "Zenitone-Microsec Ltd. (Game World license)", "Invader's Revenge (Game World, single PCB)", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND ) + +GAME( 1980, vortex, 0, vortex, vortex, _8080bw_state, vortex, ROT270, "Zilec Electronics", "Vortex", MACHINE_IMPERFECT_COLORS | MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) /* Encrypted 8080/IO */ + +GAME( 1979, rollingc, 0, rollingc, rollingc, driver_device, 0, ROT270, "Nichibutsu", "Rolling Crash / Moon Base", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_COLORS | MACHINE_SUPPORTS_SAVE ) + +GAME( 1979, ozmawars, 0, invadpt2, ozmawars, driver_device, 0, ROT270, "SNK", "Ozma Wars (set 1)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, ozmawars2, ozmawars, invadpt2, ozmawars, driver_device, 0, ROT270, "SNK", "Ozma Wars (set 2)", MACHINE_SUPPORTS_SAVE ) /* Uses Taito's three board color version of Space Invaders PCB */ +GAME( 1979, ozmawarsmr, ozmawars, invaders, ozmawars, driver_device, 0, ROT270, "bootleg (Model Racing)", "Ozma Wars (Model Racing bootleg)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, spaceph, ozmawars, invaders, spaceph, driver_device, 0, ROT270, "bootleg? (Zilec Games)", "Space Phantoms (bootleg of Ozma Wars)", MACHINE_SUPPORTS_SAVE ) +GAME( 1979, solfight, ozmawars, invaders, ozmawars, driver_device, 0, ROT270, "bootleg", "Solar Fight (bootleg of Ozma Wars)", MACHINE_SUPPORTS_SAVE ) + +GAME( 1979, yosakdon, 0, yosakdon, yosakdon, driver_device, 0, ROT270, "Wing", "Yosaku To Donbei (set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) +GAME( 1979, yosakdona, yosakdon, yosakdon, yosakdon, driver_device, 0, ROT270, "Wing", "Yosaku To Donbei (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) + +GAMEL(1979, shuttlei, 0, shuttlei, shuttlei, driver_device, 0, ROT270, "Omori Electric Co., Ltd.", "Shuttle Invader", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND, layout_shuttlei ) + +GAMEL(1979, skylove, 0, shuttlei, skylove, driver_device, 0, ROT270, "Omori Electric Co., Ltd.", "Sky Love", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND, layout_shuttlei ) + +GAME (1978, claybust, 0, claybust, claybust, driver_device, 0, ROT0, "Model Racing", "Claybuster", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND ) // no titlescreen, Claybuster according to flyers + +GAMEL(1980, gunchamp, 0, claybust, gunchamp, driver_device, 0, ROT0, "Model Racing", "Gun Champ", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND, layout_gunchamp ) // no titlescreen, Gun Champ according to original cab + +GAME( 1980?,astropal, 0, astropal, astropal, driver_device, 0, ROT0, "Sidam?", "Astropal", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_SOUND ) + +GAMEL(1979?,attackfc, 0, attackfc, attackfc, _8080bw_state, attackfc, ROT0, "Electronic Games Systems", "Attack Force", MACHINE_SUPPORTS_SAVE | MACHINE_NO_SOUND, layout_attackfc ) + +GAME( 2002, invmulti, 0, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (M8.03D)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultim3a,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (M8.03A)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultim2c,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (M8.02C)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultim2a,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (M8.02A)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultim1a,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (M8.01A)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultit3d,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (T8.03D)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultis3a,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (S0.83A)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultis2a,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (S0.82A)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultis1a,invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (S0.81A)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +GAME( 2002, invmultip, invmulti, invmulti, invmulti, _8080bw_state, invmulti, ROT270, "hack (Braze Technologies)", "Space Invaders Multigame (prototype)", MACHINE_IMPERFECT_SOUND | MACHINE_SUPPORTS_SAVE ) +Contact GitHub API Training Shop Blog About +© 2017 GitHub, Inc. Terms Privacy Security Status Help \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/ballbomb.zip b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/ballbomb.zip new file mode 100644 index 00000000..74f170d9 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/ballbomb.zip differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/bin2hex.exe b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/bin2hex.exe new file mode 100644 index 00000000..443395a5 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/bin2hex.exe differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/bomb1.hex b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/bomb1.hex new file mode 100644 index 00000000..46f817dd --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/bomb1.hex @@ -0,0 +1,322 @@ +:020000040000FA +:20000000000000C318000000FBC9000000000000E5D5C5F5C3D804FF310024CD7601060090 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Hardware/Midway8080_MiST/roms/zzzapd b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapd new file mode 100644 index 00000000..800211bd Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapd differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzape b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzape new file mode 100644 index 00000000..051c824f Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzape differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapf b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapf new file mode 100644 index 00000000..8152873a Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapg b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapg new file mode 100644 index 00000000..d925be84 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzapg differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzaph b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzaph new file mode 100644 index 00000000..54e86ff9 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080_MiST/roms/zzzaph differ diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Graphics.VHD b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Graphics.VHD new file mode 100644 index 00000000..2bc251ad --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Graphics.VHD @@ -0,0 +1,272 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; + +entity Graphics is + port + ( + bitmap_ctl_i : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + bitmap_ctl_o : out from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + tilemap_ctl_i : in to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + tilemap_ctl_o : out from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + + sprite_reg_i : in to_SPRITE_REG_t; + sprite_ctl_i : in to_SPRITE_CTL_t; + sprite_ctl_o : out from_SPRITE_CTL_t; + spr0_hit : out std_logic; + + graphics_i : in to_GRAPHICS_t; + graphics_o : out from_GRAPHICS_t; + + video_i : in from_VIDEO_t; + video_o : out to_VIDEO_t + ); + +end Graphics; + +architecture SYN of Graphics is + + alias clk : std_logic is video_i.clk; + + signal from_video_ctl : from_VIDEO_CTL_t; + signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + signal tilemap_ctl_o_s : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + signal sprite_ctl_o_s : from_SPRITE_CTL_t; + signal sprite_pri : std_logic; + + signal rgb_data : RGB_t; + + signal video_o_s : to_VIDEO_t; + +begin + + -- dodgy OSD transparency... + video_o.clk <= video_o_s.clk; + video_o.rgb.r <= video_o_s.rgb.r; + video_o.rgb.g <= video_o_s.rgb.g; + video_o.rgb.b <= video_o_s.rgb.b; + video_o.hsync <= video_o_s.hsync; + video_o.vsync <= video_o_s.vsync; + video_o.hblank <= video_o_s.hblank; + video_o.vblank <= video_o_s.vblank; + + graphics_o.y <= from_video_ctl.y; + -- should this be the 'real' vblank or the 'active' vblank? + -- - use the real for now + graphics_o.hblank <= video_o_s.hblank; + graphics_o.vblank <= video_o_s.vblank; + --graphics_o.vblank <= from_video_ctl.vblank; + + pace_video_controller_inst : entity work.pace_video_controller + generic map + ( + CONFIG => PACE_VIDEO_CONTROLLER_TYPE, + DELAY => PACE_VIDEO_PIPELINE_DELAY, + H_SIZE => PACE_VIDEO_H_SIZE, + V_SIZE => PACE_VIDEO_V_SIZE, + L_CROP => PACE_VIDEO_L_CROP, + R_CROP => PACE_VIDEO_R_CROP, + H_SCALE => PACE_VIDEO_H_SCALE, + V_SCALE => PACE_VIDEO_V_SCALE, + H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY, + V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY, + BORDER_RGB => PACE_VIDEO_BORDER_RGB + ) + port map + ( + -- clocking etc + video_i => video_i, + + -- register interface + reg_i.h_scale => "000", + reg_i.v_scale => "000", + -- video data signals (in) + rgb_i => rgb_data, + + -- video control signals (out) + video_ctl_o => from_video_ctl, + + -- VGA signals (out) + video_o => video_o_s + ); + + pace_video_mixer_inst : entity work.pace_video_mixer + port map + ( + bitmap_ctl_o => bitmap_ctl_o_s, + tilemap_ctl_o => tilemap_ctl_o_s, + sprite_rgb => sprite_ctl_o_s.rgb, + sprite_set => sprite_ctl_o_s.set, + sprite_pri => sprite_pri, + + video_ctl_i => from_video_ctl, + graphics_i => graphics_i, + rgb_o => rgb_data + ); + + GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate + --bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0'); + end generate GEN_NO_BITMAPS; + + GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => bitmap_ctl_i(1), + ctl_o => bitmap_ctl_o_s(1), + + graphics_i => graphics_i + ); + end generate GEN_BITMAP_1; + + GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => bitmap_ctl_i(2), + ctl_o => bitmap_ctl_o_s(2), + + graphics_i => graphics_i + ); + + end generate GEN_BITMAP_2; + + GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate + + forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => bitmap_ctl_i(3), + ctl_o => bitmap_ctl_o_s(3), + + graphics_i => graphics_i + ); + + end generate GEN_BITMAP_3; + + bitmap_ctl_o <= bitmap_ctl_o_s; + + GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate + --tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'), + -- (others => (others => '0')), '0'); + end generate GEN_NO_TILEMAPS; + + GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate + + foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => tilemap_ctl_i(1), + ctl_o => tilemap_ctl_o_s(1), + + graphics_i => graphics_i + ); + + end generate GEN_TILEMAP_1; + + GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate + + background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2) + generic map + ( + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + video_ctl => from_video_ctl, + + ctl_i => tilemap_ctl_i(2), + ctl_o => tilemap_ctl_o_s(2), + + graphics_i => graphics_i + ); + + end generate GEN_TILEMAP_2; + + tilemap_ctl_o <= tilemap_ctl_o_s; + + GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate + sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0'); + sprite_pri <= '0'; + spr0_hit <= '0'; + end generate GEN_NO_SPRITES; + + GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate + + sprites_inst : sprite_array + generic map + ( + N_SPRITES => PACE_VIDEO_NUM_SPRITES, + DELAY => PACE_VIDEO_PIPELINE_DELAY + ) + port map + ( + reset => video_i.reset, + + -- register interface + reg_i => sprite_reg_i, + + -- video control signals + video_ctl => from_video_ctl, + + graphics_i => graphics_i, + + row_a => sprite_ctl_o_s.a, + row_d => sprite_ctl_i.d, + + rgb => sprite_ctl_o_s.rgb, + set => sprite_ctl_o_s.set, + pri => sprite_pri, + spr0_set => spr0_hit + ); + + end generate GEN_SPRITES; + + sprite_ctl_o <= sprite_ctl_o_s; + + +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/InputMapper.VHDL b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/InputMapper.VHDL new file mode 100644 index 00000000..5024c699 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/InputMapper.VHDL @@ -0,0 +1,119 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; +use work.kbd_pkg.all; + +entity inputmapper is + generic + ( + NUM_DIPS : integer := 8; + NUM_INPUTS : integer := 2 + ); + port + ( + clk : in std_logic; + rst_n : in std_logic; + + -- inputs from keyboard controller + reset : in std_logic; + key_down : in std_logic; + key_up : in std_logic; + data : in std_logic_vector(7 downto 0); + -- JAMMA interface + jamma : in from_JAMMA_t; + + -- user outputs + dips : in std_logic_vector(NUM_DIPS-1 downto 0); + inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1) + ); + end inputmapper; + +architecture SYN of inputmapper is + +begin + + latchInputs: process (clk, rst_n) + variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1); + variable keybd_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1); + begin + + -- note: all inputs are active HIGH + + if rst_n = '0' then + for i in 0 to NUM_INPUTS-1 loop + jamma_v(i).d := (others => '1'); + keybd_v(i).d := (others => '0'); + end loop; + + elsif rising_edge (clk) then + + -- handle JAMMA inputs + -- enable button 3 to insert coin + jamma_v(0).d(0) := jamma.coin(1) and jamma.p(1).button(3); + jamma_v(0).d(1) := jamma.p(2).start; + jamma_v(0).d(2) := jamma.p(1).start; + jamma_v(0).d(4) := jamma.p(1).button(1); + jamma_v(1).d(4) := jamma.p(1).button(1); + jamma_v(0).d(5) := jamma.p(1).left; + jamma_v(1).d(5) := jamma.p(1).left; + jamma_v(0).d(6) := jamma.p(1).right; + jamma_v(1).d(6) := jamma.p(1).right; + + -- map the dipswitches + keybd_v(1).d(3 downto 0) := dips(3 downto 0); + keybd_v(1).d(7) := dips(7); + if (key_down or key_up) = '1' then + case data(7 downto 0) is + -- IN0 + when SCANCODE_5 => + keybd_v(0).d(0) := key_down; + when SCANCODE_2 => + keybd_v(0).d(1) := key_down; + when SCANCODE_1 => + keybd_v(0).d(2) := key_down; + when SCANCODE_LCTRL | SCANCODE_SPACE => + keybd_v(0).d(4) := key_down; + keybd_v(1).d(4) := key_down; + when SCANCODE_LEFT => + keybd_v(0).d(5) := key_down; + keybd_v(1).d(5) := key_down; + when SCANCODE_RIGHT => + keybd_v(0).d(6) := key_down; + keybd_v(1).d(6) := key_down; + -- IN1 + --when "01110101" => -- $75 = UP + --when "01110010" => -- $72 = DOWN + --when "00110111" => -- $37 = '6' + --when "00011011" => -- $1B = 'S' + -- Special keys + when SCANCODE_F3 => + keybd_v(2).d(0) := key_down; -- CPU RESET + when SCANCODE_TAB => + keybd_v(2).d(1) := key_down; -- OSD TOGGLE + when SCANCODE_F4 => + keybd_v(2).d(2) := key_down; -- video rotate + when others => + end case; + end if; -- key_down or key_up + + -- this is PS/2 reset only + if (reset = '1') then + for i in 0 to NUM_INPUTS-1 loop + keybd_v(i).d := (others =>'0'); + end loop; + end if; + end if; -- rising_edge (clk) + + -- assign outputs + for i in 0 to NUM_INPUTS-1 loop + inputs(i).d <= not jamma_v(i).d or keybd_v(i).d; + end loop; + + end process latchInputs; + +end SYN; + + diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Inputs.VHD b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Inputs.VHD new file mode 100644 index 00000000..4337db25 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Inputs.VHD @@ -0,0 +1,112 @@ +Library IEEE; +Use IEEE.std_logic_1164.all; + +library work; +use work.pace_pkg.all; +use work.kbd_pkg.all; + +entity inputs is + generic + ( + NUM_DIPS : integer := 8; + NUM_INPUTS : integer := 2; + CLK_1US_DIV : natural := 30 + ); + port + ( + clk : in std_logic; + reset : in std_logic; + ps2clk : in std_logic; + ps2data : in std_logic; + jamma : in from_JAMMA_t; + + dips : in std_logic_vector(NUM_DIPS-1 downto 0); + inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1) + ); +end entity inputs; + +architecture SYN of inputs is + + component ps2kbd + port + ( + clk : in std_logic; + rst_n : in std_logic; + tick1us : in std_logic; + ps2_clk : in std_logic; + ps2_data : in std_logic; + + reset : out std_logic; + keydown : out std_logic; + keyup : out std_logic; + scancode : out std_logic_vector(7 downto 0) + ); + end component; + + signal reset_n : std_logic; + signal tick_1us : std_logic; + signal ps2_reset : std_logic; + signal ps2_press : std_logic; + signal ps2_release : std_logic; + signal ps2_scancode : std_logic_vector(7 downto 0); + +begin + + reset_n <= not reset; + +-- ps2clk <= 'Z'; +-- ps2data <= 'Z'; + + ps2kbd_inst : ps2kbd + port map + ( + clk => clk, + rst_n => reset_n, + tick1us => tick_1us, + ps2_clk => ps2clk, + ps2_data => ps2data, + + reset => ps2_reset, + keydown => ps2_press, + keyup => ps2_release, + scancode => ps2_scancode + ); + + inputmapper_inst : entity work.inputmapper + generic map + ( + NUM_DIPS => NUM_DIPS, + NUM_INPUTS => NUM_INPUTS + ) + port map + ( + clk => clk, + rst_n => reset_n, + + reset => ps2_reset, + key_down => ps2_press, + key_up => ps2_release, + data => ps2_scancode, + jamma => jamma, + + dips => dips, + inputs => inputs + ); + + process (clk, reset) + variable count : integer range 0 to CLK_1US_DIV := 0; + begin + if reset = '1' then + count := 0; + tick_1us <= '0'; + elsif rising_edge(clk) then + tick_1us <= '0'; + count := count + 1; + if count = CLK_1US_DIV then + count := 0; + tick_1us <= '1'; + end if; + end if; + end process; + +end architecture SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Sound.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Sound.vhd new file mode 100644 index 00000000..6c6d9a42 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Sound.vhd @@ -0,0 +1,116 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sound is + generic + ( + CLK_MHz : natural + ); + port + ( + sysClk : in std_logic; + reset : in std_logic; + + sndif_rd : in std_logic; + sndif_wr : in std_logic; + sndif_datai : in std_logic_vector(7 downto 0); + sndif_addr : in std_logic_vector(15 downto 0); + + snd_clk : out std_logic; + snd_data_l : out std_logic_vector(7 downto 0); + snd_data_r : out std_logic_vector(7 downto 0); + sndif_datao : out std_logic_vector(7 downto 0) + ); +end entity sound; + +architecture SYN of Sound is + + component invaders_audio + Port + ( + Clk : in std_logic; + S1 : in std_logic_vector(5 downto 0); + S2 : in std_logic_vector(5 downto 0); + Aud : out std_logic_vector(7 downto 0) + ); + end component; + +-- Signal Declarations + + -- audio module clock + signal clk_5M : std_logic; + signal clk_10M : std_logic; + + -- port latches + signal s1_r : std_logic_vector(5 downto 0); + signal s2_r : std_logic_vector(5 downto 0); + + signal snd_data_s : std_logic_vector(7 downto 0); + +begin + + sndif_datao <= X"00"; + + -- latches + process (sysClk, reset) + variable wr_r : std_logic := '0'; + begin + if reset = '1' then + wr_r := '0'; + elsif rising_edge(sysClk) then + -- latch port data on rising edge of WRITE + if sndif_wr = '1' and wr_r = '0' then + case sndif_addr(2 downto 0) is + when "011" => + s1_r <= sndif_datai(5 downto 0); + when "101" => + s2_r <= sndif_datai(5 downto 0); + when others => + end case; + end if; + wr_r := sndif_wr; + end if; + end process; + + -- apparently the audio module wants a 10MHz clock + process (sysClk, reset) + subtype count_t is integer range 0 to CLK_MHz/5; + variable count : count_t := 0; + begin + if reset = '1' then + count := 0; + clk_10M <= '0'; + clk_5M <= '0'; + elsif rising_edge(sysClk) then + clk_10M <= '0'; + clk_5M <= '0'; + if count = count_t'high/2 then + clk_10M <= '1'; + count := count + 1; + elsif count = count_t'high then + clk_10M <= '1'; + clk_5M <= '1'; + count := 0; + else + count := count + 1; + end if; + end if; + end process; + + -- can use anything suitable + snd_clk <= clk_5M; + + audio_inst : invaders_audio + port map + ( + Clk => clk_10M, + S1 => s1_r, + S2 => s2_r, + Aud => snd_data_s + ); + + snd_data_l <= snd_data_s; + snd_data_r <= snd_data_s; + +end architecture SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80.vhd new file mode 100644 index 00000000..1ea66542 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80.vhd @@ -0,0 +1,1088 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if Mode = 3 then + IStatus <= "10"; + elsif IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusA <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_ALU.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_MCode.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_MCode.vhd new file mode 100644 index 00000000..a8f5fbf5 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_MCode.vhd @@ -0,0 +1,2024 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + --I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + if mode = 3 then + MCycles <= "011"; + else + MCycles <= "101"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_Pack.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_Pack.vhd new file mode 100644 index 00000000..907db408 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_Pack.vhd @@ -0,0 +1,228 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_Reg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_Reg.vhd new file mode 100644 index 00000000..1c0f2638 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80se.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80se.vhd new file mode 100644 index 00000000..1b0cb9b5 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/T80se.vhd @@ -0,0 +1,192 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0240 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Z80.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Z80.vhd new file mode 100644 index 00000000..db1ad947 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/Z80.vhd @@ -0,0 +1,135 @@ +library IEEE; +use IEEE.std_logic_1164.all; +library work; +use work.T80_Pack.all; + +entity Z80 is port + ( + clk : in std_logic; + clk_en : in std_logic; + reset : in std_logic; + + addr : out std_logic_vector(15 downto 0); + datai : in std_logic_vector(7 downto 0); + datao : out std_logic_vector(7 downto 0); + + m1 : out std_logic; + mem_rd : out std_logic; + mem_wr : out std_logic; + io_rd : out std_logic; + io_wr : out std_logic; + + wait_n : in std_logic := '1'; + busrq_n : in std_logic := '1'; + intreq : in std_logic := '0'; + intvec : in std_logic_vector(7 downto 0); + intack : out std_logic; + nmi : in std_logic := '0' + ); +end Z80; + +architecture SYN of Z80 is + + component T80se is + generic + ( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port + ( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); + end component T80se; + + -- Signal Declarations + + signal reset_n : std_logic; + signal int_n : std_logic; + signal nmi_n : std_logic; + + signal z80_m1 : std_logic; + signal z80_memreq : std_logic; + signal z80_ioreq : std_logic; + signal z80_rd : std_logic; + signal z80_wr : std_logic; + signal z80_datai : std_logic_vector(7 downto 0); + + -- derived signals (outputs we need to read) + signal z80_memrd : std_logic; + signal z80_iord : std_logic; + signal fetch : std_logic; + + begin + + -- simple inversions + reset_n <= not reset; + int_n <= not intreq; + nmi_n <= not nmi; + + -- direct-connect (outputs we need to read) + m1 <= z80_m1; + mem_rd <= z80_memrd; + io_rd <= z80_iord; + + -- memory signals + z80_memrd <= z80_memreq nor z80_rd; + mem_wr <= z80_memreq nor z80_wr; + + -- io signals + z80_iord <= z80_ioreq nor z80_rd; + io_wr <= z80_ioreq nor z80_wr; + + -- other signals + fetch <= z80_m1 nor z80_memreq; + intack <= z80_m1 nor z80_ioreq; + + -- data in mux + z80_datai <= intvec when ((z80_memrd or z80_iord) = '0') else + datai; + + Z80_uP : T80se + generic map + ( + Mode => 0 -- Z80 + ) + port map + ( + RESET_n => reset_n, + CLK_n => clk, + CLKEN => clk_en, + WAIT_n => wait_n, + INT_n => int_n, + NMI_n => nmi_n, + BUSRQ_n => busrq_n, + M1_n => z80_m1, + MREQ_n => z80_memreq, + IORQ_n => z80_ioreq, + RD_n => z80_rd, + WR_n => z80_wr, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => addr, + DI => z80_datai, + DO => datao + ); + +end architecture SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/altera_mem.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/altera_mem.vhd new file mode 100644 index 00000000..ba68be99 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/altera_mem.vhd @@ -0,0 +1,144 @@ +library IEEE; +use ieee.std_logic_1164.all; +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; + +ENTITY invaders_rom_0 IS + PORT + ( + address : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END invaders_rom_0; + +architecture SYN of invaders_rom_0 is +begin + sprom_inst : entity work.sprom + generic map + ( + init_file => ROM_0_NAME, + --numwords_a => 8192, + widthad_a => 13 + ) + port map + ( + clock => clock, + address => address, + q => q + ); +end SYN; + +library IEEE; +use ieee.std_logic_1164.all; +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; + +ENTITY invaders_rom_1 IS + PORT + ( + address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END invaders_rom_1; + +architecture SYN of invaders_rom_1 is +begin + sprom_inst : entity work.sprom + generic map + ( + init_file => ROM_1_NAME, + --numwords_a => 4096, + widthad_a => 12 + ) + port map + ( + clock => clock, + address => address, + q => q + ); +end SYN; + +library IEEE; +use ieee.std_logic_1164.all; +library work; +use work.pace_pkg.all; +use work.platform_variant_pkg.all; + +ENTITY vram IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END vram; + +architecture SYN of vram is +begin + dpam_inst : entity work.dpram + generic map + ( + init_file => VRAM_NAME, + --numwords_a => 8192, + widthad_a => 13 + ) + port map + ( + clock_b => clock_b, + address_b => address_b, + data_b => data_b, + q_b => q_b, + wren_b => wren_b, + + clock_a => clock_a, + address_a => address_a, + data_a => data_a, + q_a => q_a, + wren_a => wren_a + ); +end SYN; + +library IEEE; +use ieee.std_logic_1164.all; +library work; +use work.pace_pkg.all; + +ENTITY wram IS + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END wram; + +architecture SYN of wram is +begin + spram_inst : entity work.spram + generic map + ( + --numwords_a => 1024, + widthad_a => 10 + ) + port map + ( + clock => clock, + address => address, + data => data, + wren => wren, + q => q + ); +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/bitmapctl.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/bitmapctl.vhd new file mode 100644 index 00000000..ea55e6dc --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/bitmapctl.vhd @@ -0,0 +1,121 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.platform_pkg.all; + +-- +-- Midway 8080 Bitmap Controller +-- + +architecture BITMAP_1 of bitmapCtl is + + alias clk : std_logic is video_ctl.clk; + alias clk_ena : std_logic is video_ctl.clk_ena; + alias stb : std_logic is video_ctl.stb; + alias hblank : std_logic is video_ctl.hblank; + alias vblank : std_logic is video_ctl.vblank; + --alias x : std_logic_vector(video_ctl.x'range) is video_ctl.x; + --alias y : std_logic_vector(video_ctl.y'range) is video_ctl.y; + + alias rgb : RGB_t is ctl_o.rgb; + + signal x : std_logic_vector(video_ctl.x'range); + signal y : std_logic_vector(video_ctl.y'range); + + signal chr_x : std_logic_vector(4 downto 0); + signal chr_y : std_logic_vector(4 downto 0); + + alias rot_en : std_logic is graphics_i.bit8(0)(0); + +begin + + -- flip X,Y to rotate the screen in the opposite direction for my cabinet + x <= not video_ctl.x when rot_en = '0' else not video_ctl.y; + y <= not video_ctl.y when rot_en = '0' else 32 + video_ctl.x; + + -- cellophane coordinate system independent of video for now + chr_x <= video_ctl.x(7 downto 3) when rot_en = '0' else 1 + video_ctl.y(7 downto 3); + -- bottom line green still not right... fix it later + chr_y <= video_ctl.y(7 downto 3) when rot_en = '0' else not video_ctl.x(7 downto 3); + + -- generate pixel + process (clk) + variable bitmap_d_r : std_logic_vector(7 downto 0); + variable i : integer range 0 to 7; + variable pel : std_logic; + begin + + if rising_edge(clk) and clk_ena = '1' then + + -- 1st stage of pipeline + -- - read tile from tilemap + if stb = '1' then + ctl_o.a(12 downto 5) <= y(7 downto 0); + ctl_o.a(4 downto 0) <= x(7 downto 3); + end if; + + if rot_en = '0' then + if x(2 downto 0) = 0 then + bitmap_d_r := ctl_i.d(7 downto 0); + else + bitmap_d_r := bitmap_d_r(bitmap_d_r'left-1 downto 0) & '0'; + end if; + pel := bitmap_d_r(bitmap_d_r'left); + else + i := to_integer(unsigned(x(2 downto 0))); + pel := ctl_i.d(i); + end if; + + -- emulate the coloured cellophane overlays + rgb.r <= (others => '0'); + rgb.g <= (others => '0'); + rgb.b <= (others => '0'); + if pel = '1' then + if chr_x < 5 then + -- white + rgb.r(9 downto 0) <= (others => '1'); + rgb.g(9 downto 0) <= (others => '1'); + rgb.b(9 downto 0) <= (others => '1'); + elsif chr_x < 9 then + rgb.r(9 downto 0) <= (others => '1'); -- red + elsif chr_x < 24 then + -- white + rgb.r(9 downto 0) <= (others => '1'); + rgb.g(9 downto 0) <= (others => '1'); + rgb.b(9 downto 0) <= (others => '1'); + elsif chr_x < 31 then + rgb.g(9 downto 0) <= (others => '1'); -- green + else + if chr_y < 11 then + -- white ("CREDIT 00") + rgb.r(9 downto 0) <= (others => '1'); + rgb.g(9 downto 0) <= (others => '1'); + rgb.b(9 downto 0) <= (others => '1'); + elsif chr_y < 29 then + -- green (bases) + rgb.g(9 downto 0) <= (others => '1'); + else + -- white (ships left) + rgb.r(9 downto 0) <= (others => '1'); + rgb.g(9 downto 0) <= (others => '1'); + rgb.b(9 downto 0) <= (others => '1'); + end if; + end if; + else + null; -- black + end if; + + end if; -- rising_edge(clk) + + end process; + + -- not used/constant + ctl_o.a(15 downto 13) <= (others => '0'); + ctl_o.set <= '1'; + +end architecture BITMAP_1; + diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/bitmapctl_e.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/bitmapctl_e.vhd new file mode 100644 index 00000000..508109c8 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/bitmapctl_e.vhd @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.platform_pkg.all; +use work.project_pkg.all; + +entity bitmapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity bitmapCtl; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/clk_div.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/clk_div.vhd new file mode 100644 index 00000000..020d6ae6 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/clk_div.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity clk_div is + generic + ( + DIVISOR : natural + ); + port + ( + clk : in std_logic; + reset : in std_logic; + + clk_en : out std_logic + ); +end clk_div; + +architecture SYN of clk_div is + +begin + + process (clk, reset) + variable count : integer range 0 to DIVISOR-1; + begin + if reset = '1' then + count := 0; + clk_en <= '0'; + elsif rising_edge(clk) then + clk_en <= '0'; + if count = DIVISOR-1 then + clk_en <= '1'; + count := 0; + else + count := count + 1; + end if; + end if; + end process; + +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/dpram.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/dpram.vhd new file mode 100644 index 00000000..91233996 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/dpram.vhd @@ -0,0 +1,123 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED"; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(width_a-1 DOWNTO 0); + q_b <= sub_wire1(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => init_file, + intended_device_family => "Cyclone II", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + numwords_b => 2**widthad_a, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => outdata_reg_a, + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + +END SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/dpram_1r1w.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/dpram_1r1w.vhd new file mode 100644 index 00000000..6e9193cd --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/dpram_1r1w.vhd @@ -0,0 +1,102 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dpram_1r1w IS + GENERIC + ( + numwords_a : natural; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_b : string := "UNREGISTERED" + ); + PORT + ( + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + rdclock : IN STD_LOGIC ; + rdclocken : IN STD_LOGIC := '1'; + wraddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + wrclock : IN STD_LOGIC ; + wrclocken : IN STD_LOGIC := '1'; + wren : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END dpram_1r1w; + + +ARCHITECTURE SYN OF dpram_1r1w IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_b : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clocken0 : IN STD_LOGIC ; + clocken1 : IN STD_LOGIC ; + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone II", + lpm_type => "altsyncram", + numwords_a => numwords_a, + numwords_b => numwords_a, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => outdata_reg_b, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + widthad_b => widthad_a, + width_a => width_a, + width_b => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + clocken0 => wrclocken, + clocken1 => rdclocken, + wren_a => wren, + clock0 => wrclock, + clock1 => rdclock, + address_a => wraddress, + address_b => rdaddress, + data_a => data, + q_b => sub_wire0 + ); + +END SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/invaders_audio.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/invaders_audio.vhd new file mode 100644 index 00000000..f16cf379 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/invaders_audio.vhd @@ -0,0 +1,496 @@ + +-- Version : 0300 +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- minor tidy up by MikeJ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: PaulWalsh +-- +-- Create Date: 08:45:29 11/04/05 +-- Design Name: +-- Module Name: Invaders Audio +-- Project Name: Space Invaders +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity invaders_audio is + Port ( + Clk : in std_logic; + S1 : in std_logic_vector(5 downto 0); + S2 : in std_logic_vector(5 downto 0); + Aud : out std_logic_vector(7 downto 0) + ); +end; + --* Port 3: (S1) + --* bit 0=UFO (repeats) + --* bit 1=Shot + --* bit 2=Base hit + --* bit 3=Invader hit + --* bit 4=Bonus base + --* + --* Port 5: (S2) + --* bit 0=Fleet movement 1 + --* bit 1=Fleet movement 2 + --* bit 2=Fleet movement 3 + --* bit 3=Fleet movement 4 + --* bit 4=UFO 2 + +architecture Behavioral of invaders_audio is + + signal ClkDiv : unsigned(10 downto 0) := (others => '0'); + signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); + signal Clk7680_ena : std_logic; + signal Clk480_ena : std_logic; + signal Clk240_ena : std_logic; + signal Clk60_ena : std_logic; + + signal s1_t1 : std_logic_vector(5 downto 0); + signal s2_t1 : std_logic_vector(5 downto 0); + signal tempsum : std_logic_vector(7 downto 0); + + signal vco_cnt : std_logic_vector(3 downto 0); + + signal TriDir1 : std_logic; + signal Fnum : std_logic_vector(3 downto 0); + signal comp : std_logic; + + signal SS : std_logic; + + signal TrigSH : std_logic; + signal SHCnt : std_logic_vector(8 downto 0); + signal SH : std_logic_vector(7 downto 0); + signal SauHit : std_logic_vector(8 downto 0); + signal SHitTri : std_logic_vector(5 downto 0); + + signal TrigIH : std_logic; + signal IHDir : std_logic; + signal IHDir1 : std_logic; + signal IHCnt : std_logic_vector(8 downto 0); + signal IH : std_logic_vector(7 downto 0); + signal InHit : std_logic_vector(8 downto 0); + signal IHitTri : std_logic_vector(5 downto 0); + + signal TrigEx : std_logic; + signal Excnt : std_logic_vector(9 downto 0); + signal ExShift : std_logic_vector(15 downto 0); + signal Ex : std_logic_vector(2 downto 0); + signal Explo : std_logic; + + signal TrigMis : std_logic; + signal MisShift : std_logic_vector(15 downto 0); + signal MisCnt : std_logic_vector(8 downto 0); + signal miscnt1 : unsigned(7 downto 0); + signal Mis : std_logic_vector(2 downto 0); + signal Missile : std_logic; + + signal EnBG : std_logic; + signal BGFnum : std_logic_vector(7 downto 0); + signal BGCnum : std_logic_vector(7 downto 0); + signal bg_cnt : unsigned(7 downto 0); + signal BG : std_logic; + +begin + + -- do a crude addition of all sound samples + p_audio_mix : process + variable IHVol : std_logic_vector(6 downto 0); + variable SHVol : std_logic_vector(6 downto 0); + begin + wait until rising_edge(Clk); + + IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); + SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); + + tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); + + Aud(7) <= tempsum (7); + Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; + Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; + Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); + Aud(3 downto 0) <= tempsum (3 downto 0); + + end process; + + p_clkdiv : process + begin + wait until rising_edge(Clk); + Clk7680_ena <= '0'; + if ClkDiv = 1277 then + Clk7680_ena <= '1'; + ClkDiv <= (others => '0'); + else + ClkDiv <= ClkDiv + 1; + end if; + end process; + + p_clkdiv2 : process + begin + wait until rising_edge(Clk); + Clk480_ena <= '0'; + Clk240_ena <= '0'; + Clk60_ena <= '0'; + + if (Clk7680_ena = '1') then + ClkDiv2 <= ClkDiv2 + 1; + + if (ClkDiv2(3 downto 0) = "0000") then + Clk480_ena <= '1'; + end if; + + if (ClkDiv2(4 downto 0) = "00000") then + Clk240_ena <= '1'; + end if; + + if (ClkDiv2(7 downto 0) = "00000000") then + Clk60_ena <= '1'; + end if; + + end if; + end process; + + p_delay : process + begin + wait until rising_edge(Clk); + s1_t1 <= S1; + s2_t1 <= S2; + end process; +--*************************Saucer Sound*************************************** + +-- Implement a VCOscilator: frequency is set using counter end point(Fnum) + p_saucer_vco : process + variable term : std_logic_vector(3 downto 0); + begin + wait until rising_edge(Clk); + term := 8 + Fnum; + if (S1(0) = '1') and (Clk7680_ena = '1') then + if vco_cnt = term then + + vco_cnt <= (others => '0'); + SS <= not SS; + else + vco_cnt <= vco_cnt + 1; + end if; + end if; + end process; + +-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator + -- this is 6Hz ?? 0123454321 + p_saucer_lfo : process + begin + wait until rising_edge(Clk); + if (Clk60_ena = '1') then + if Fnum = 4 then -- 5 -1 + Comp <= '1'; + elsif Fnum = 1 then -- 0 +1 + Comp <= '0'; + end if; + + if comp = '1' then + Fnum <= Fnum - 1 ; + else + Fnum <= Fnum + 1 ; + end if; + end if; + end process; + +--**********************SAUCER HIT Sound************************** + +-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO + p_saucer_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if SHitTri = 48 then + SHitTri <= "000000"; + else + SHitTri <= SHitTri+1; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx + p_saucer_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if TriDir1 = '1' then + if (SauHit +58 - SHitTri) < 190 + 256 then + SauHit <= SauHit +58 - SHitTri; + else + SauHit <= "110111110"; + TriDir1 <= '0'; + end if; + else + if (SauHit -58 + SHitTri) > 256 then + SauHit <= SauHit -58 + SHitTri; + else + SauHit <= "100000000"; + TriDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Saucer Hit Sound + p_saucer_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigSH = '1') then + SHCnt <= "100000000"; + SH <= "11111111"; + elsif (SHCnt(8) = '1') then + SHCnt <= SHCnt + "1"; + if SHCnt(7 downto 0) = x"60" then -- 96 + SH <= "01111111"; + elsif SHCnt(7 downto 0) = x"90" then -- 144 + SH <= "00111111"; + elsif SHCnt(7 downto 0) = x"C0" then -- 192 + SH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Saucer Hit Sound + p_saucer_hit : process + begin + wait until rising_edge(Clk); + if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge + TrigSH <= '1'; + elsif (Clk480_ena = '1') then + TrigSH <= '0'; + end if; + end process; + +--***********************Invader Hit Sound***************************** +-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO + p_invader_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if IHitTri = 48-2 then + IHDir <= '0'; + elsif IHitTri =0+2 then + IHDir <= '1'; + end if; + + if IHDir ='1' then + IHitTri <= IHitTri + 2; + else + IHitTri <= IHitTri - 2; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx + p_invader_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if IHDir1 = '1' then + if (InHit +10 + IHitTri) < 110 + 256 then + InHit <= InHit +10 + IHitTri; + else + InHit <= "101101110"; + IHDir1 <= '0'; + end if; + else + if (InHit -10 - IHitTri) > 256 then + InHit <= InHit -10 - IHitTri; + else + InHit <= "100000000"; + IHDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Invader Hit Sound + p_invader_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigIH = '1') then + IHCnt <= "100000000"; + IH <= "11111111"; + elsif (IHCnt(8) = '1') then + IHCnt <= IHCnt + "1"; + if IHCnt(7 downto 0) = x"14" then -- 20 + IH <= "01111111"; + elsif IHCnt(7 downto 0) = x"1C" then -- 28 + IH <= "11111111"; + elsif IHCnt(7 downto 0) = x"30" then -- 48 + IH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Invader Hit Sound + p_invader_hit : process + begin + wait until rising_edge(Clk); + if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge + TrigIH <= '1'; + elsif (Clk480_ena = '1') then + TrigIH <= '0'; + end if; + end process; + +--***********************Explosion***************************** +-- Implement a Pseudo Random Noise Generator + p_explosion_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (ExShift = x"0000") then + ExShift <= "0000000010101001"; + else + ExShift(0) <= Exshift(14) xor ExShift(15); + ExShift(15 downto 1) <= ExShift (14 downto 0); + end if; + end if; + end process; + Explo <= ExShift(0); + + p_explosion_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigEx = '1') then + ExCnt <= "1000000000"; + Ex <= "100"; + elsif (ExCnt(9) = '1') then + ExCnt <= ExCnt + "1"; + if ExCnt(8 downto 0) = '0' & x"64" then -- 100 + Ex <= "010"; + elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 + Ex <= "001"; + elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 + Ex <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Explosion Sound + p_explosion_trig : process + begin + wait until rising_edge(Clk); + if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge + TrigEx <= '1'; + elsif (Clk480_ena = '1') then + TrigEx <= '0'; + end if; + end process; + +--***********************Missile***************************** +-- Implement a Pseudo Random Noise Generator + p_missile_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if (MisShift = x"0000") then + MisShift <= "0000000010101001"; + else + MisShift(0) <= MisShift(14) xor MisShift(15); + MisShift(15 downto 1) <= MisShift (14 downto 0); + end if; + + miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); + if miscnt1 > 60 then + miscnt1 <= "00000000"; + Missile <= not Missile; + end if; + + end if; + end process; + +-- Implement the ADSR for The Missile Sound + p_missile_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigMis = '1') then + MisCnt <= "100000000"; + Mis <= "100"; + elsif (MisCnt(8) = '1') then + MisCnt <= MisCnt + "1"; + if MisCnt(7 downto 0) = x"4b" then -- 75 + Mis <= "010"; + elsif MisCnt(7 downto 0) = x"70" then -- 112 + Mis <= "001"; + elsif MisCnt(7 downto 0) = x"96" then -- 150 + Mis <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Missile Sound + p_missile_trig : process + begin + wait until rising_edge(Clk); + if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge + TrigMis <= '1'; + elsif (Clk480_ena = '1') then + TrigMis <= '0'; + end if; + end process; + +-- ******************************** Background invader moving tones ************************** + EnBG <= S2(0) or S2(1) or S2(2) or S2(3); + + with S2(3 downto 0) select + BGFnum <= x"66" when "0001", + x"74" when "0010", + x"7C" when "0100", + x"87" when "1000", + x"87" when others; + + with S2(3 downto 0) select + BGCnum <= x"33" when "0001", + x"3A" when "0010", + x"3E" when "0100", + x"43" when "1000", + x"43" when others; + +-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) + + p_background : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if EnBG = '0' then + bg_cnt <= x"00"; + BG <= '0'; + else + bg_cnt <= bg_cnt + 1; + + if bg_cnt = unsigned(BGfnum) then + bg_cnt <= x"00"; + BG <= '0'; + elsif bg_cnt=unsigned(BGCnum) then + BG <='1'; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/custom_io.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/custom_io.vhd new file mode 100644 index 00000000..7fe8da50 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/custom_io.vhd @@ -0,0 +1,25 @@ +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.target_pkg.all; +use work.platform_pkg.all; +use work.project_pkg.all; + +entity custom_io is + port + ( + project_i : out from_PROJECT_IO_t; + project_o : in to_PROJECT_IO_t; + platform_i : out from_PLATFORM_IO_t; + platform_o : in to_PLATFORM_IO_t; + target_i : out from_TARGET_IO_t; + target_o : in to_TARGET_IO_t + ); +end entity custom_io; + +architecture SYN of custom_io is + +begin +end architecture SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/keyboard.v b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/keyboard.v new file mode 100644 index 00000000..50a0376e --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/keyboard.v @@ -0,0 +1,72 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg pressed; +reg e0; +wire [7:0] keyb_data; +wire keyb_valid; + +// PS/2 interface +ps2_intf ps2( + clk, + !reset, + + ps2_kbd_clk, + ps2_kbd_data, + + // Byte-wide data interface - only valid for one clock + // so must be latched externally if required + keyb_data, + keyb_valid +); + + + + +always @(posedge reset or posedge clk) begin + + if(reset) begin + pressed <= 1'b0; + e0 <= 1'b0; + + joystick <= 8'd0; + end else begin + if (keyb_valid) begin + if (keyb_data == 8'HE0) + e0 <=1'b1; + else if (keyb_data == 8'HF0) + pressed <= 1'b0; + else begin + case({e0, keyb_data}) + 9'H016: joystick[1] <= pressed; // 1 + 9'H01E: joystick[2] <= pressed; // 2 + + 9'H175: joystick[4] <= pressed; // arrow up + 9'H172: joystick[5] <= pressed; // arrow down + 9'H16B: joystick[6] <= pressed; // arrow left + 9'H174: joystick[7] <= pressed; // arrow right + + 9'H029: joystick[0] <= pressed; // Space +// 9'H011: joystick[1] <= pressed; // Left Alt +// 9'H00d: joystick[2] <= pressed; // Tab + 9'H076: joystick[3] <= pressed; // Escape + + endcase; + + pressed <= 1'b1; + e0 <= 1'b0; + end + end + end +end + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/osd.v b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/osd.v new file mode 100644 index 00000000..58cd8291 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/osd.v @@ -0,0 +1,191 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input pclk, + + // SPI interface + input sck, + input ss, + input sdi, + + // VGA signals coming from core + input [5:0] red_in, + input [5:0] green_in, + input [5:0] blue_in, + input hs_in, + input vs_in, + + // enable scanlines + input scanline_ena_h, + + // VGA signals going to video connector + output [5:0] red_out, + output [5:0] green_out, + output [5:0] blue_out, + output hs_out, + output vs_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd1; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg [7:0] sbuf; +reg [7:0] cmd; +reg [4:0] cnt; +reg [10:0] bcnt; +reg osd_enable; + +reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge sck, posedge ss) begin + if(ss == 1'b1) begin + cnt <= 5'd0; + bcnt <= 11'd0; + end else begin + sbuf <= { sbuf[6:0], sdi}; + + // 0:7 is command, rest payload + if(cnt < 15) + cnt <= cnt + 4'd1; + else + cnt <= 4'd8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], sdi}; + + // lower three command bits are line address + bcnt <= { sbuf[1:0], sdi, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) + osd_enable <= sdi; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], sdi}; + bcnt <= bcnt + 11'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg hsD, hsD2; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high; +wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] }; +reg scanline = 0; + +always @(posedge pclk) begin + // bring hsync into local clock domain + hsD <= hs_in; + hsD2 <= hsD; + + // falling edge of hs_in + if(!hsD && hsD2) begin + h_cnt <= 10'd0; + hs_high <= h_cnt; + scanline <= ~scanline; + end + + // rising edge of hs_in + else if(hsD && !hsD2) begin + h_cnt <= 10'd0; + hs_low <= h_cnt; + end + + else + h_cnt <= h_cnt + 10'd1; +end + +// vertical counter +reg [9:0] v_cnt; +reg vsD, vsD2; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high; +wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] }; + +always @(posedge hs_in) begin + // bring vsync into local clock domain + vsD <= vs_in; + vsD2 <= vsD; + + // falling edge of vs_in + if(!vsD && vsD2) begin + v_cnt <= 10'd0; + vs_high <= v_cnt; + end + + // rising edge of vs_in + else if(vsD && !vsD2) begin + v_cnt <= 10'd0; + vs_low <= v_cnt; + end + + else + v_cnt <= v_cnt + 10'd1; +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1); +wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1; +wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1); +wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1; + +reg h_osd_active, v_osd_active; +always @(posedge pclk) begin + if(hs_in != hs_pol) begin + if(h_cnt == h_osd_start) h_osd_active <= 1'b1; + if(h_cnt == h_osd_end) h_osd_active <= 1'b0; + end + if(vs_in != vs_pol) begin + if(v_cnt == v_osd_start) v_osd_active <= 1'b1; + if(v_cnt == v_osd_end) v_osd_active <= 1'b0; + end +end + +wire osd_de = osd_enable && h_osd_active && v_osd_active; + +wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register +wire [6:0] osd_vcnt = v_cnt - v_osd_start; + +wire osd_pixel = osd_byte[osd_vcnt[3:1]]; + +reg [7:0] osd_byte; +always @(posedge pclk) + osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}]; + +wire [2:0] osd_color = OSD_COLOR; +wire [5:0] red_t = (scanline && scanline_ena_h)?{1'b0, red_in[5:1]}: red_in; +wire [5:0] green_t = (scanline && scanline_ena_h)?{1'b0, green_in[5:1]}: green_in; +wire [5:0] blue_t = (scanline && scanline_ena_h)?{1'b0, blue_in[5:1]}: blue_in; + +assign red_out = !osd_de?red_t: {osd_pixel, osd_pixel, osd_color[2], red_t[5:3] }; +assign green_out = !osd_de?green_t:{osd_pixel, osd_pixel, osd_color[1], green_t[5:3]}; +assign blue_out = !osd_de?blue_t: {osd_pixel, osd_pixel, osd_color[0], blue_t[5:3] }; + +assign hs_out = hs_in; +assign vs_out = vs_in; + +endmodule \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.qip b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.qip new file mode 100644 index 00000000..cd28ff9e --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll27.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll27_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll27.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll27.ppf"] diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.vhd new file mode 100644 index 00000000..c882cf03 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.vhd @@ -0,0 +1,414 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll27.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.0 Build 156 04/24/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll27 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC + ); +END pll27; + + +ARCHITECTURE SYN OF pll27 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c0 <= sub_wire2; + c2 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 13500, + clk0_duty_cycle => 50, + clk0_multiply_by => 7, + clk0_phase_shift => "0", + clk1_divide_by => 27, + clk1_duty_cycle => 50, + clk1_multiply_by => 20, + clk1_phase_shift => "0", + clk2_divide_by => 27, + clk2_duty_cycle => 50, + clk2_multiply_by => 40, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll27", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire5, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "13500" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.014000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "16" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.01400000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll27.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "13500" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27_inst.vhd TRUE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27_inst.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27_inst.vhd new file mode 100644 index 00000000..fe2f2bfa --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27_inst.vhd @@ -0,0 +1,6 @@ +pll27_inst : pll27 PORT MAP ( + inclk0 => inclk0_sig, + c0 => c0_sig, + c1 => c1_sig, + c2 => c2_sig + ); diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/ps2_intf.v b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/ps2_intf.v new file mode 100644 index 00000000..f128cda9 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/ps2_intf.v @@ -0,0 +1,141 @@ +// ZX Spectrum for Altera DE1 +// +// Copyright (c) 2009-2011 Mike Stirling +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// * Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// * Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written agreement from the author. +// +// * License is granted for non-commercial use only. A fee may not be charged +// for redistributions as source code or in synthesized/hardware form without +// specific prior written agreement from the author. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// PS/2 interface (input only) +// Based loosely on ps2_ctrl.vhd (c) ALSE. http://www.alse-fr.com + +// This is input-only for the time being +module ps2_intf #(parameter filter_length=8)( + input CLK, + input nRESET, + + // PS/2 interface (could be bi-dir) + input PS2_CLK, + input PS2_DATA, + + // Byte-wide data interface - only valid for one clock + // so must be latched externally if required + output reg [7:0] DATA, + output reg VALID, + output reg ERROR +); + + reg [filter_length-1:0] clk_filter; + + reg ps2_clk_in; + reg ps2_dat_in; + // Goes high when a clock falling edge is detected + reg clk_edge; + reg [3:0] bit_count; + reg [8:0] shiftreg; + reg parity; + // Register input signals + + always @(negedge nRESET or posedge CLK) + if (!nRESET) begin + ps2_clk_in <= 1'b1; + ps2_dat_in <= 1'b1; + clk_filter <= 8'b11111111; + clk_edge <= 1'b0; + end else begin + // Register inputs (and filter clock) + ps2_dat_in <= PS2_DATA; + clk_filter <= {PS2_CLK, clk_filter[filter_length-1:1]}; + clk_edge <= 1'b0; + + if (clk_filter) + // Filtered clock is high + ps2_clk_in <= 1'b1; + else begin + // Filter clock is low, check for edge + if (ps2_clk_in) clk_edge <= 1'b1; + ps2_clk_in <= 1'b0; + end + end + + // Shift in keyboard data + always @(negedge nRESET or posedge CLK) begin + if (!nRESET) begin + bit_count <= 4'd0; + shiftreg <= 9'd0; + parity <= 1'b0; + DATA <= 8'd0; + VALID <= 1'b0; + ERROR <= 1'b0; + end else begin + // Clear flags + VALID <= 1'b0; + ERROR <= 1'b0; + + if (clk_edge) begin + // We have a new bit from the keyboard for processing + if (bit_count == 4'd0) begin + // Idle state, check for start bit (0) only and don't + // start counting bits until we get it + parity <= 1'b0; + if (!ps2_dat_in) bit_count <= bit_count + 4'd1; // This is a start bit + end else begin + // Running. 8-bit data comes in LSb first followed by + // a single stop bit (1) + if (bit_count < 4'd10) begin + // Shift in data and parity (9 bits) + bit_count <= bit_count + 4'd1; + shiftreg <= {ps2_dat_in, shiftreg[8:1]}; + parity <= parity ^ ps2_dat_in; // Calculate parity + end else if (ps2_dat_in) begin + // Valid stop bit received + bit_count <= 4'd0; // back to idle + if (parity) begin + // Parity correct, submit data to host + DATA <= shiftreg[7:0]; + VALID <= 1'b1; + end else begin + // Error + ERROR <= 1'b1; + end + end + else begin + // Invalid stop bit + bit_count <= 4'd0; // back to idle + ERROR <= 1'b1; + end + end + end + end + end + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/sigma_delta_dac.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/sigma_delta_dac.vhd new file mode 100644 index 00000000..fdec465f --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/sigma_delta_dac.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sigma_delta_dac is + port + ( + clk : in std_logic; + din : in std_logic_vector(7 downto 0); + + dout : out std_logic + ); +end entity sigma_delta_dac; + +architecture SYN of sigma_delta_dac is + + signal si : unsigned(15 downto 0) := (others => '0'); + signal so : unsigned(15 downto 0) := (others => '0'); + +begin + + si(15 downto 10) <= "000000"; + si(9 downto 0) <= unsigned(so(9) & so(9) & din); + + process (clk) + begin + if rising_edge(clk) then + so <= si + so; + dout <= so(9); + end if; + end process; + +end architecture SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/target_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/target_pkg.vhd new file mode 100644 index 00000000..f66ee0a1 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/target_pkg.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; + +package target_pkg is + + -- + -- PACE constants which *MUST* be defined + -- +constant PACE_TARGET : PACETargetType := PACE_TARGET_MIST; +constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA; +constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3; + +constant PACE_CLKIN0 : natural := 27; + + -- + -- DE1-specific constants + -- + type from_TARGET_IO_t is record + not_used : std_logic; + end record; + + type to_TARGET_IO_t is record + not_used : std_logic; + end record; + + end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/target_top.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/target_top.vhd new file mode 100644 index 00000000..f37dbf11 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/target_top.vhd @@ -0,0 +1,362 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; +use work.target_pkg.all; + +entity target_top is + port + ( + + CLOCK_27 : in std_logic; + SPI_SCK : in std_logic; + SPI_DI : in std_logic; + SPI_SS2 : in std_logic; + SPI_SS3 : in std_logic; + SPI_SS4 : in std_logic; + SPI_DO : out std_logic; + LED : out std_logic; + CONF_DATA0 : in std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + VGA_VS : out std_logic; -- VGA H_SYNC + VGA_HS : out std_logic; -- VGA V_SYNC + VGA_R : out std_logic_vector(5 downto 0); -- VGA Red[3:0] + VGA_G : out std_logic_vector(5 downto 0); -- VGA Green[3:0] + VGA_B : out std_logic_vector(5 downto 0) -- VGA Blue[3:0] + + ); + +end target_top; + +architecture SYN of target_top is + + signal init : std_logic := '1'; + signal clock_50 : std_logic; + signal clkrst_i : from_CLKRST_t; + signal buttons_i : from_BUTTONS_t; + signal switches_i : from_SWITCHES_t; + signal leds_o : to_LEDS_t; + signal inputs_i : from_INPUTS_t; + signal video_i : from_VIDEO_t; + signal video_o : to_VIDEO_t; + signal audio_i : from_AUDIO_t; + signal audio_o : to_AUDIO_t; + signal project_i : from_PROJECT_IO_t; + signal project_o : to_PROJECT_IO_t; + signal platform_i : from_PLATFORM_IO_t; + signal platform_o : to_PLATFORM_IO_t; + signal target_i : from_TARGET_IO_t; + signal target_o : to_TARGET_IO_t; + + signal clk_kb : std_logic; + signal joystick1 : std_logic_vector(7 downto 0); + signal joystick2 : std_logic_vector(7 downto 0); + signal switches : std_logic_vector(1 downto 0); + signal buttons : std_logic_vector(1 downto 0); + signal ps2Clk : std_logic; + signal ps2Data : std_logic; + signal kbd_joy0 : std_logic_vector(7 downto 0); + signal osd_pclk : std_logic; + signal clk8m : std_logic; + signal clk16m : std_logic; + signal scandoubler_disable : std_logic; + signal hsync_out : std_logic; + signal vsync_out : std_logic; + signal csync_out : std_logic; + signal VGA_R_O : std_logic_vector(5 downto 0); + signal VGA_G_O : std_logic_vector(5 downto 0); + signal VGA_B_O : std_logic_vector(5 downto 0); + signal VGA_HS_O : std_logic; + signal VGA_VS_O : std_logic; + signal status : std_logic_vector(7 downto 0); + signal reset : std_logic; + + + constant CONF_STR : string := "Midw.8080;;O4,Scanlines,OFF,ON;T5,Reset;V,v1.0 by Gehstock;"; + + function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; + + begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; + + end function; + + component user_io + generic ( STRLEN : integer := 0 ); + port ( + SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic; + SPI_MISO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + switches : out std_logic_vector(1 downto 0); + buttons : out std_logic_vector(1 downto 0); + scandoubler_disable : out std_logic; + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + status : out std_logic_vector(7 downto 0); + ps2_clk : in std_logic; + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); + end component user_io; + + component osd + port ( + pclk, sck, ss, sdi, hs_in, vs_in, scanline_ena_h : in std_logic; + red_in, blue_in, green_in : in std_logic_vector(5 downto 0); + red_out, blue_out, green_out : out std_logic_vector(5 downto 0); + hs_out, vs_out : out std_logic + ); + end component osd; + + component keyboard + PORT( + clk : in std_logic; + reset : in std_logic; + ps2_kbd_clk : in std_logic; + ps2_kbd_data : in std_logic; + joystick : out std_logic_vector (7 downto 0) + ); + end component; + + + component pll27 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC; + c1 : OUT STD_LOGIC; + c2 : OUT STD_LOGIC + ); + end component; + + + +begin + +LED <= '1'; + +-- OSD + osd_pclk <= clk16m when scandoubler_disable='0' else clk8m; + + -- a minimig vga->scart cable expects a composite sync signal on the VGA_HS output + -- and VCC on VGA_VS (to switch into rgb mode) + csync_out <= '1' when (hsync_out = vsync_out) else '0'; + VGA_HS <= hsync_out when scandoubler_disable='0' else csync_out; + VGA_VS <= vsync_out when scandoubler_disable='0' else '1'; + + osd_inst : osd + port map ( + pclk => osd_pclk, + sdi => SPI_DI, + sck => SPI_SCK, + ss => SPI_SS3, + red_in => VGA_R_O, + green_in => VGA_G_O, + blue_in => VGA_B_O, + hs_in => VGA_HS_O, + vs_in => VGA_VS_O, + scanline_ena_h => status(4), + red_out => VGA_R, + green_out => VGA_G, + blue_out => VGA_B, + hs_out => hsync_out, + vs_out => vsync_out + ); + + user_io_inst : user_io + generic map (STRLEN => CONF_STR'length) + port map ( + SPI_CLK => SPI_SCK, + SPI_SS_IO => CONF_DATA0, + SPI_MOSI => SPI_DI, + SPI_MISO => SPI_DO, + conf_str => to_slv(CONF_STR), + switches => switches, + buttons => buttons, + scandoubler_disable => scandoubler_disable, + joystick_1 => joystick2, + joystick_0 => joystick1, + status => status, + ps2_clk => clk_kb, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data + ); + + u_keyboard : keyboard + port map( + clk => clock_50, + reset => reset, + ps2_kbd_clk => ps2Clk, + ps2_kbd_data => ps2Data, + joystick => kbd_joy0 +); + + +kbclk : pll27 + port map + ( + inclk0 => CLOCK_27, + c0 => clk_kb, + c1 => clk8m, + c2 => clk16m + ); + clkrst_i.clk_ref <= CLOCK_27; + + pll_27_inst : entity work.pllclk_ez + port map + ( + inclk0 => CLOCK_27, + c0 => clock_50, -- master clock + c1 => clkrst_i.clk(1) -- video clock + ); + clkrst_i.clk(0)<=clock_50; + + + -- FPGA STARTUP + -- should extend power-on reset if registers init to '0' + process (clock_50) + variable count : std_logic_vector (11 downto 0) := (others => '0'); + begin + if rising_edge(clock_50) then + if count = X"FFF" then + init <= '0'; + else + count := count + 1; + init <= '1'; + end if; + end if; + end process; + + clkrst_i.arst <= init or status(5) or buttons(1); + clkrst_i.arst_n <= not clkrst_i.arst; + + GEN_RESETS : for i in 0 to 3 generate + + process (clkrst_i.clk(i), clkrst_i.arst) + variable rst_r : std_logic_vector(2 downto 0) := (others => '0'); + begin + if clkrst_i.arst = '1' then + rst_r := (others => '1'); + elsif rising_edge(clkrst_i.clk(i)) then + rst_r := rst_r(rst_r'left-1 downto 0) & '0'; + end if; + clkrst_i.rst(i) <= rst_r(rst_r'left); + end process; + + end generate GEN_RESETS; + + + inputs_i.jamma_n.coin(1) <= not (kbd_joy0(3)) or status(2);--ESC + inputs_i.jamma_n.p(1).start <= not (kbd_joy0(3)) or status(2);--ESC + + inputs_i.jamma_n.p(1).up <= not (joystick1(3) or joystick2(3) or kbd_joy0(4)); + inputs_i.jamma_n.p(1).down <= not (joystick1(2) or joystick2(2) or kbd_joy0(5)); + inputs_i.jamma_n.p(1).left <= not (joystick1(1) or joystick2(1) or kbd_joy0(6)); + inputs_i.jamma_n.p(1).right <= not (joystick1(0) or joystick2(0) or kbd_joy0(7)); + + inputs_i.jamma_n.p(1).button(1) <= not (joystick1(4) or joystick2(4) or kbd_joy0(0)); + inputs_i.jamma_n.p(1).button(2) <= '1'; + inputs_i.jamma_n.p(1).button(3) <= '1'; + inputs_i.jamma_n.p(1).button(4) <= '1'; + inputs_i.jamma_n.p(1).button(5) <= '1'; + + inputs_i.jamma_n.p(2).up <= not (joystick1(3) or joystick2(3) or kbd_joy0(4)); + inputs_i.jamma_n.p(2).down <= not (joystick1(2) or joystick2(2) or kbd_joy0(5)); + inputs_i.jamma_n.p(2).left <= not (joystick1(1) or joystick2(1) or kbd_joy0(6)); + inputs_i.jamma_n.p(2).right <= not (joystick1(0) or joystick2(0) or kbd_joy0(7)); + + inputs_i.jamma_n.p(2).button(1) <= not (joystick1(4) or joystick2(4) or kbd_joy0(0)); + inputs_i.jamma_n.p(2).button(2) <= '1'; + inputs_i.jamma_n.p(2).button(3) <= '1'; + inputs_i.jamma_n.p(2).button(4) <= '1'; + inputs_i.jamma_n.p(2).button(5) <= '1'; + + + -- not currently wired to any inputs + inputs_i.jamma_n.coin_cnt <= (others => '1'); + inputs_i.jamma_n.coin(2) <= '1'; + inputs_i.jamma_n.service <= '1'; + inputs_i.jamma_n.tilt <= '1'; + inputs_i.jamma_n.test <= '1'; + + BLK_VIDEO : block + begin + + video_i.clk <= clkrst_i.clk(1); -- by convention + video_i.clk_ena <= '1'; + video_i.reset <= clkrst_i.rst(1); + + VGA_R_O <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-5); + VGA_G_O <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-5); + VGA_B_O <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-5); + VGA_HS_O <= video_o.hsync; + VGA_VS_O <= video_o.vsync; + + end block BLK_VIDEO; + + BLK_AUDIO : block + begin + + dacl : entity work.sigma_delta_dac + port map ( + clk => CLOCK_27, + din => audio_o.ldata(15 downto 8), + dout => AUDIO_L + ); + + dacr : entity work.sigma_delta_dac + port map ( + clk => CLOCK_27, + din => audio_o.rdata(15 downto 8), + dout => AUDIO_R + ); + + end block BLK_AUDIO; + + pace_inst : entity work.pace + port map + ( + -- clocks and resets + clkrst_i => clkrst_i, + + -- misc inputs and outputs + buttons_i => buttons_i, + switches_i => switches_i, + leds_o => open, + + -- controller inputs + inputs_i => inputs_i, + + -- VGA video + video_i => video_i, + video_o => video_o, + + -- sound + audio_i => audio_i, + audio_o => audio_o, + + -- custom i/o + project_i => project_i, + project_o => project_o, + platform_i => platform_i, + platform_o => platform_o, + target_i => target_i, + target_o => target_o + ); +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/user_io.v b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/user_io.v new file mode 100644 index 00000000..c66c515f --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/mist/user_io.v @@ -0,0 +1,411 @@ +// +// user_io.v +// +// user_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +// parameter STRLEN and the actual length of conf_str have to match + +module user_io #(parameter STRLEN=0) ( + input [(8*STRLEN)-1:0] conf_str, + + input SPI_CLK, + input SPI_SS_IO, + output reg SPI_MISO, + input SPI_MOSI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + + output reg [7:0] status, + + // connection to sd card emulation + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + input sd_conf, + input sd_sdhc, + output reg [7:0] sd_dout, + output reg sd_dout_strobe, + input [7:0] sd_din, + output reg sd_din_strobe, + + + // ps2 keyboard emulation + input ps2_clk, // 12-16khz provided by core + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // serial com port + input [7:0] serial_data, + input serial_strobe +); + +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [7:0] joystick0; +reg [7:0] joystick1; +reg [4:0] but_sw; +reg [2:0] stick_idx; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +// filter spi clock. the 8 bit gate delay is ~2.5ns in total +wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */; +wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff); + +// drive MISO only when transmitting core id +always@(negedge spi_sck or posedge SPI_SS_IO) begin + if(SPI_SS_IO == 1) begin + SPI_MISO <= 1'bZ; + end else begin + + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + SPI_MISO <= core_type[~bit_cnt]; + + end else begin + // reading serial fifo + if(cmd == 8'h1b) begin + // send alternating flag byte and data + if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt]; + else SPI_MISO <= serial_out_byte[~bit_cnt]; + end + + // reading config string + else if(cmd == 8'h14) begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) + SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else + SPI_MISO <= 1'b0; + end + + // reading sd card status + else if(cmd == 8'h16) begin + if(byte_cnt == 1) + SPI_MISO <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) + SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else + SPI_MISO <= 1'b0; + end + + // reading sd card write data + else if(cmd == 8'h18) + SPI_MISO <= sd_din[~bit_cnt]; + + else + SPI_MISO <= 1'b0; + end + end +end + +// ---------------- PS2 --------------------- + +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +// keyboard +reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_kbd_tx_state; +reg [7:0] ps2_kbd_tx_byte; +reg ps2_kbd_parity; + +assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_kbd_r_inc; +always@(posedge ps2_clk) begin + ps2_kbd_r_inc <= 1'b0; + + if(ps2_kbd_r_inc) + ps2_kbd_rptr <= ps2_kbd_rptr + 1; + + // transmitter is idle? + if(ps2_kbd_tx_state == 0) begin + // data in fifo present? + if(ps2_kbd_wptr != ps2_kbd_rptr) begin + // load tx register from fifo + ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; + ps2_kbd_r_inc <= 1'b1; + + // reset parity + ps2_kbd_parity <= 1'b1; + + // start transmitter + ps2_kbd_tx_state <= 4'd1; + + // put start bit on data line + ps2_kbd_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) + ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) + ps2_kbd_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) + ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; + else + ps2_kbd_tx_state <= 4'd0; + + end +end + +// mouse +reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_mouse_tx_state; +reg [7:0] ps2_mouse_tx_byte; +reg ps2_mouse_parity; + +assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_mouse_r_inc; +always@(posedge ps2_clk) begin + ps2_mouse_r_inc <= 1'b0; + + if(ps2_mouse_r_inc) + ps2_mouse_rptr <= ps2_mouse_rptr + 1; + + // transmitter is idle? + if(ps2_mouse_tx_state == 0) begin + // data in fifo present? + if(ps2_mouse_wptr != ps2_mouse_rptr) begin + // load tx register from fifo + ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; + ps2_mouse_r_inc <= 1'b1; + + // reset parity + ps2_mouse_parity <= 1'b1; + + // start transmitter + ps2_mouse_tx_state <= 4'd1; + + // put start bit on data line + ps2_mouse_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) + ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) + ps2_mouse_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) + ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; + else + ps2_mouse_tx_state <= 4'd0; + + end +end + +// fifo to receive serial data from core to be forwarded to io controller + +// 16 byte fifo to store serial bytes +localparam SERIAL_OUT_FIFO_BITS = 6; +reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0]; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr; + +wire serial_out_data_available = serial_out_wptr != serial_out_rptr; +wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */; +wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available}; + +// status[0] is reset signal from io controller and is thus used to flush +// the fifo +always @(posedge serial_strobe or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_wptr <= 0; + end else begin + serial_out_fifo[serial_out_wptr] <= serial_data; + serial_out_wptr <= serial_out_wptr + 1; + end +end + +always@(negedge spi_sck or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_rptr <= 0; + end else begin + if((byte_cnt != 0) && (cmd == 8'h1b)) begin + // read last bit -> advance read pointer + if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) + serial_out_rptr <= serial_out_rptr + 1; + end + end +end + +// SPI receiver +always@(posedge spi_sck or posedge SPI_SS_IO) begin + + if(SPI_SS_IO == 1) begin + bit_cnt <= 3'd0; + byte_cnt <= 8'd0; + sd_ack <= 1'b0; + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + end else begin + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + + sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; + bit_cnt <= bit_cnt + 3'd1; + if((bit_cnt == 7)&&(byte_cnt != 8'd255)) + byte_cnt <= byte_cnt + 8'd1; + + // finished reading command byte + if(bit_cnt == 7) begin + if(byte_cnt == 0) begin + cmd <= { sbuf, SPI_MOSI}; + + // fetch first byte when sectore FPGA->IO command has been seen + if({ sbuf, SPI_MOSI} == 8'h18) + sd_din_strobe <= 1'b1; + + if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18)) + sd_ack <= 1'b1; + + end else begin + + // buttons and switches + if(cmd == 8'h01) + but_sw <= { sbuf[3:0], SPI_MOSI }; + + if(cmd == 8'h02) + joystick_0 <= { sbuf, SPI_MOSI }; + + if(cmd == 8'h03) + joystick_1 <= { sbuf, SPI_MOSI }; + + if(cmd == 8'h04) begin + // store incoming ps2 mouse bytes + ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; + ps2_mouse_wptr <= ps2_mouse_wptr + 1; + end + + if(cmd == 8'h05) begin + // store incoming ps2 keyboard bytes + ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; + ps2_kbd_wptr <= ps2_kbd_wptr + 1; + end + + if(cmd == 8'h15) + status <= { sbuf[6:0], SPI_MOSI }; + + // send sector IO -> FPGA + if(cmd == 8'h17) begin + // flag that download begins + sd_dout <= { sbuf, SPI_MOSI}; + sd_dout_strobe <= 1'b1; + end + + // send sector FPGA -> IO + if(cmd == 8'h18) + sd_din_strobe <= 1'b1; + + // send SD config IO -> FPGA + if(cmd == 8'h19) begin + // flag that download begins + sd_dout <= { sbuf, SPI_MOSI}; + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + sd_dout_strobe <= 1'b1; + end + + // joystick analog + if(cmd == 8'h1a) begin + // first byte is joystick indes + if(byte_cnt == 1) + stick_idx <= { sbuf[1:0], SPI_MOSI }; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) + joystick_analog_0[15:8] <= { sbuf, SPI_MOSI }; + else if(stick_idx == 1) + joystick_analog_1[15:8] <= { sbuf, SPI_MOSI }; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) + joystick_analog_0[7:0] <= { sbuf, SPI_MOSI }; + else if(stick_idx == 1) + joystick_analog_1[7:0] <= { sbuf, SPI_MOSI }; + end + end + + end + end + end +end + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace.vhd new file mode 100644 index 00000000..997095eb --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace.vhd @@ -0,0 +1,199 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.platform_pkg.all; +use work.project_pkg.all; +use work.target_pkg.all; + +entity PACE is + port + ( + -- clocks and resets + clkrst_i : in from_CLKRST_t; + + -- misc I/O + buttons_i : in from_BUTTONS_t; + switches_i : in from_SWITCHES_t; + leds_o : out to_LEDS_t; + + -- controller inputs + inputs_i : in from_INPUTS_t; + + -- video + video_i : in from_VIDEO_t; + video_o : out to_VIDEO_t; + + -- audio + audio_i : in from_AUDIO_t; + audio_o : out to_AUDIO_t; + + -- custom i/o + project_i : in from_PROJECT_IO_t; + project_o : out to_PROJECT_IO_t; + platform_i : in from_PLATFORM_IO_t; + platform_o : out to_PLATFORM_IO_t; + target_i : in from_TARGET_IO_t; + target_o : out to_TARGET_IO_t + ); +end entity PACE; + +architecture SYN of PACE is + + constant CLK_1US_COUNTS : integer := + integer(PACE_CLKIN0 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY); + + signal mapped_inputs : from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1); + + signal to_tilemap_ctl : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + + signal to_bitmap_ctl : to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + signal from_bitmap_ctl : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + + signal to_sprite_reg : to_SPRITE_REG_t; + signal to_sprite_ctl : to_SPRITE_CTL_t; + signal from_sprite_ctl : from_SPRITE_CTL_t; + signal spr0_hit : std_logic; + + signal to_graphics : to_GRAPHICS_t; + signal from_graphics : from_GRAPHICS_t; + + signal to_sound : to_SOUND_t; + signal from_sound : from_sound_t; + + +begin + + assert false + report "CLK0_FREQ_MHz=" & integer'image(CLK0_FREQ_MHz) & + " CLK_1US_COUNTS=" & integer'image(CLK_1US_COUNTS) + severity note; + + inputs_inst : entity work.inputs + generic map + ( + NUM_DIPS => PACE_NUM_SWITCHES, + NUM_INPUTS => PACE_INPUTS_NUM_BYTES, + CLK_1US_DIV => CLK_1US_COUNTS + ) + port map + ( + clk => clkrst_i.clk(0), + reset => clkrst_i.rst(0), + ps2clk => inputs_i.ps2_kclk, + ps2data => inputs_i.ps2_kdat, + jamma => inputs_i.jamma_n, + + dips => switches_i, + inputs => mapped_inputs + ); + + platform_inst : entity work.platform + generic map + ( + NUM_INPUT_BYTES => PACE_INPUTS_NUM_BYTES + ) + port map + ( + -- clocking and reset + clkrst_i => clkrst_i, + + -- misc inputs and outputs + buttons_i => buttons_i, + switches_i => switches_i, + leds_o => leds_o, + + -- controller inputs + inputs_i => mapped_inputs, + + -- graphics + bitmap_i => from_bitmap_ctl, + bitmap_o => to_bitmap_ctl, + + tilemap_i => from_tilemap_ctl, + tilemap_o => to_tilemap_ctl, + + sprite_reg_o => to_sprite_reg, + sprite_i => from_sprite_ctl, + sprite_o => to_sprite_ctl, + spr0_hit => spr0_hit, + + graphics_i => from_graphics, + graphics_o => to_graphics, + + -- sound + snd_i => from_sound, + snd_o => to_sound, + + -- custom i/o + project_i => project_i, + project_o => project_o, + platform_i => platform_i, + platform_o => platform_o, + target_i => target_i, + target_o => target_o + ); + + graphics_inst : entity work.Graphics + Port Map + ( + bitmap_ctl_i => to_bitmap_ctl, + bitmap_ctl_o => from_bitmap_ctl, + + tilemap_ctl_i => to_tilemap_ctl, + tilemap_ctl_o => from_tilemap_ctl, + + sprite_reg_i => to_sprite_reg, + sprite_ctl_i => to_sprite_ctl, + sprite_ctl_o => from_sprite_ctl, + spr0_hit => spr0_hit, + + graphics_i => to_graphics, + graphics_o => from_graphics, + + -- video (incl. clk) + video_i => video_i, + video_o => video_o + ); + + SOUND_BLOCK : block + signal snd_data_l : std_logic_vector(7 downto 0); + signal snd_data_r : std_logic_vector(7 downto 0); + signal snd_a : std_logic_vector(15 downto 0); + begin + + snd_a <= std_logic_vector(resize(unsigned(to_sound.a), snd_a'length)); + + sound_inst : entity work.Sound + generic map + ( + CLK_MHz => CLK0_FREQ_MHz + ) + port map + ( + sysclk => clkrst_i.clk(0), -- fudge for now + reset => clkrst_i.rst(0), + + sndif_rd => to_sound.rd, + sndif_wr => to_sound.wr, + sndif_addr => snd_a, + sndif_datai => to_sound.d, + + snd_clk => audio_o.clk, + snd_data_l => snd_data_l, + snd_data_r => snd_data_r, + sndif_datao => from_sound.d + ); + + -- route audio to both channels + audio_o.ldata <= snd_data_l & "00000000"; + audio_o.rdata <= snd_data_r & "00000000"; + + end block SOUND_BLOCK; + +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace_pkg.vhd new file mode 100644 index 00000000..4f659cd8 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace_pkg.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +package pace_pkg is + + -- + -- PACE constants which *MUST* be defined + -- + + type PACETargetType is + ( + PACE_TARGET_NANOBOARD_NB1, + PACE_TARGET_DE0, + PACE_TARGET_DE0_CV, -- 5CEBA4 + PACE_TARGET_DE0_NANO, -- EP4CE22 + PACE_TARGET_DE1, + PACE_TARGET_DE2, + PACE_TARGET_DE2_70, -- EP2C70 + PACE_TARGET_DE2_115, -- EP4CE115 + PACE_TARGET_P2, -- A02 build + PACE_TARGET_P2A, -- A04/A build (SRAM byte selects) + PACE_TARGET_P3M, + PACE_TARGET_S3A_700, -- Spartan 3A/N Starter Kit + PACE_TARGET_RC10, + PACE_TARGET_NX2_12, + PACE_TARGET_NEXYS_3, -- Digilent S6 board + PACE_TARGET_CYC3DEV, + PACE_TARGET_CYC5GXDEV, + PACE_TARGET_COCO3PLUS, + PACE_TARGET_S5A, + PACE_TARGET_CARTEBLANCHE_250, + PACE_TARGET_CARTEBLANCHE_500, + PACE_TARGET_BEMICRO, + PACE_TARGET_OPENEP3C16, + PACE_TARGET_MIST, + PACE_TARGET_CHAMELEON64, + PACE_TARGET_RETRORAMBLINGS_CYC3, -- Generic EP3C25 board with custom io boards + PACE_TARGET_S5A_R2_EP4C, + PACE_TARGET_S5A_R2_EP3SL, + PACE_TARGET_S5A_R2B0_EP4C, + PACE_TARGET_S5A_R2B0_EP3SL, + PACE_TARGET_S5A_R2C0_EP4C, + PACE_TARGET_S5A_R2C0_EP3SL, + PACE_TARGET_S5L_A0_EP4C, + PACE_TARGET_S5L_A0_EP3SL, + PACE_TARGET_NAVICO_ROCKY, + PACE_TARGET_NGPACE, + PACE_TARGET_S6M_A0 + ); + + type PACEFpgaVendor_t is + ( + PACE_FPGA_VENDOR_ALTERA, + PACE_FPGA_VENDOR_XILINX, + PACE_FPGA_VENDOR_LATTICE + ); + + type PACEFpgaFamily_t is + ( + PACE_FPGA_FAMILY_CYCLONE1, + PACE_FPGA_FAMILY_CYCLONE2, + PACE_FPGA_FAMILY_CYCLONE3, + PACE_FPGA_FAMILY_CYCLONE4, + PACE_FPGA_FAMILY_CYCLONE5, + PACE_FPGA_FAMILY_CYCLONE6, + PACE_FPGA_FAMILY_STRATIX_III, + PACE_FPGA_FAMILY_SPARTAN3, + PACE_FPGA_FAMILY_SPARTAN3A, + PACE_FPGA_FAMILY_SPARTAN3E + ); + + type PACEJamma_t is + ( + PACE_JAMMA_NONE, + PACE_JAMMA_MAPLE, + PACE_JAMMA_NGC, + PACE_JAMMA_PS2 + ); + + -- Types + + type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0); + + type from_CLKRST_t is record + arst : std_logic; + arst_n : std_logic; + rst : std_logic_vector(0 to 3); + clk_ref : std_logic; --reference clock + clk : std_logic_vector(0 to 3); + end record; + + -- maximums from the DE2 target + + constant PACE_NUM_SWITCHES : natural := 18; + subtype from_SWITCHES_t is std_logic_vector(PACE_NUM_SWITCHES-1 downto 0); + + constant PACE_NUM_BUTTONS : natural := 4; + subtype from_BUTTONS_t is std_logic_vector(PACE_NUM_BUTTONS-1 downto 0); + + constant PACE_NUM_LEDS : natural := 18; + subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0); + + -- + -- JAMMA interface data structures + -- - note: all signals are active LOW + -- + + type from_JAMMA_player_t is record + start : std_logic; + up : std_logic; + down : std_logic; + left : std_logic; + right : std_logic; + button : std_logic_vector(1 to 5); + end record; + + type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t; + + type from_JAMMA_t is record + coin_cnt : std_logic_vector(1 to 2); + service : std_logic; + tilt : std_logic; + test : std_logic; + coin : std_logic_vector(1 to 2); + p : from_JAMMA_player_a(1 to 2); + end record; + + -- + -- INPUTS + -- + subtype analogue_in_t is std_logic_vector(9 downto 0); + type analogue_in_a is array (natural range <>) of analogue_in_t; + + type from_INPUTS_t is record + ps2_kclk : std_logic; + ps2_kdat : std_logic; + ps2_mclk : std_logic; + ps2_mdat : std_logic; + jamma_n : from_JAMMA_t; + -- up to 4 10-bit analgue inputs + analogue : analogue_in_a(1 to 4); + end record; + + type in8_t is record + d : std_logic_vector(7 downto 0); + end record; + + type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t; + + -- + -- SRAM interface data structure + -- + type from_SRAM_t is record + d : std_logic_vector(31 downto 0); + end record; + + type to_SRAM_t is record + a : std_logic_vector(23 downto 0); + d : std_logic_vector(31 downto 0); + be : std_logic_vector(3 downto 0); + cs : std_logic; + oe : std_logic; + we : std_logic; + end record; + + + + -- + -- FLASH interface data structure + -- + type from_FLASH_t is record + d : std_logic_vector(15 downto 0); + end record; + + type to_FLASH_t is record + a : std_logic_vector(21 downto 0); + d : std_logic_vector(15 downto 0); + we : std_logic; + cs : std_logic; + oe : std_logic; + end record; + + + type from_AUDIO_t is record + clk : std_logic; + end record; + + type to_AUDIO_t is record + clk : std_logic; + ldata : std_logic_vector(15 downto 0); + rdata : std_logic_vector(15 downto 0); + end record; + + function NULL_TO_AUDIO return to_AUDIO_t; + + type from_SPI_t is record + din : std_logic; + end record; + + type to_SPI_t is record + clk : std_logic; + mode : std_logic; + sel : std_logic; + ena : std_logic; + dout : std_logic; + end record; + + + + type to_SERIAL_t is record + txd : std_logic; + rts : std_logic; + end record; + + + + type from_SERIAL_t is record + dcd : std_logic; + rxd : std_logic; + cts : std_logic; + end record; + + constant PACE_NUM_GPI : natural := 72; + subtype from_GP_t is std_logic_vector(PACE_NUM_GPI-1 downto 0); + constant PACE_NUM_GPO : natural := PACE_NUM_GPI; + type to_GP_t is record + d : std_logic_vector(PACE_NUM_GPO-1 downto 0); + oe : std_logic_vector(PACE_NUM_GPO-1 downto 0); + end record; + + function NULL_TO_GP return to_GP_t; + + subtype SND_A_t is std_logic_vector(7 downto 0); + subtype SND_D_t is std_logic_vector(7 downto 0); + + type to_SOUND_t is record + a : SND_A_t; + d : SND_D_t; + rd : std_logic; + wr : std_logic; + end record; + + type from_SOUND_t is record + d : SND_D_t; + end record; + + function NULL_TO_SOUND return to_SOUND_t; + + -- + -- OSD interface data structure + -- + type from_OSD_t is record + d : std_logic_vector(7 downto 0); + end record; + + + + type to_OSD_t is record + en : std_logic; + a : std_logic_vector(7 downto 0); + d : std_logic_vector(7 downto 0); + we : std_logic; + end record; + + + -- create a constant that automatically determines + -- whether this is simulation or synthesis + constant IN_SIMULATION : BOOLEAN := false + -- synthesis translate_off + or true + -- synthesis translate_on + ; + constant IN_SYNTHESIS : boolean := not IN_SIMULATION; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace_pkg_body.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace_pkg_body.vhd new file mode 100644 index 00000000..8cc99869 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pace_pkg_body.vhd @@ -0,0 +1,20 @@ +library work; + +package body pace_pkg is + + function NULL_TO_AUDIO return to_AUDIO_t is + begin + return ('0', (others => '0'), (others => '0')); + end NULL_TO_AUDIO; + + function NULL_TO_SOUND return to_SOUND_t is + begin + return ((others => '0'), (others => '0'), '0', '0'); + end NULL_TO_SOUND; + + function NULL_TO_GP return to_GP_t is + begin + return ((others => '0'), (others => '0')); + end NULL_TO_GP; + +end package body pace_pkg; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform.vhd new file mode 100644 index 00000000..f598f001 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform.vhd @@ -0,0 +1,385 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_europa_support_lib.to_std_logic; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.target_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; +use work.platform_variant_pkg.all; + +entity platform is + generic + ( + NUM_INPUT_BYTES : integer + ); + port + ( + -- clocking and reset + clkrst_i : in from_CLKRST_t; + + -- misc I/O + buttons_i : in from_BUTTONS_t; + switches_i : in from_SWITCHES_t; + leds_o : out to_LEDS_t; + + -- controller inputs + inputs_i : in from_MAPPED_INPUTS_t(0 to NUM_INPUT_BYTES-1); + + -- graphics + + bitmap_i : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + bitmap_o : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + + tilemap_i : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + tilemap_o : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + + sprite_reg_o : out to_SPRITE_REG_t; + sprite_i : in from_SPRITE_CTL_t; + sprite_o : out to_SPRITE_CTL_t; + spr0_hit : in std_logic; + + -- various graphics information + graphics_i : in from_GRAPHICS_t; + graphics_o : out to_GRAPHICS_t; + + -- sound + snd_i : in from_SOUND_t; + snd_o : out to_SOUND_t; + + -- custom i/o + project_i : in from_PROJECT_IO_t; + project_o : out to_PROJECT_IO_t; + platform_i : in from_PLATFORM_IO_t; + platform_o : out to_PLATFORM_IO_t; + target_i : in from_TARGET_IO_t; + target_o : out to_TARGET_IO_t + ); +end entity platform; + +architecture SYN of platform is + + alias clk_sys : std_logic is clkrst_i.clk(0); + alias clk_video : std_logic is clkrst_i.clk(1); + + -- uP signals + signal clk_2M_en : std_logic; + signal cpu_a : std_logic_vector(15 downto 0); + signal cpu_d_i : std_logic_vector(7 downto 0); + signal cpu_d_o : std_logic_vector(7 downto 0); + signal cpu_mem_rd : std_logic; + signal cpu_mem_wr : std_logic; + signal cpu_io_rd : std_logic; + signal cpu_io_wr : std_logic; + signal cpu_irq : std_logic; + signal cpu_intvec : std_logic_vector(7 downto 0); + signal cpu_intack : std_logic; + alias io_addr : std_logic_vector(7 downto 0) is cpu_a(7 downto 0); + + -- ROM signals + signal rom0_cs : std_logic; + signal rom0_datao : std_logic_vector(7 downto 0); + signal rom1_cs : std_logic; + signal rom1_datao : std_logic_vector(7 downto 0); + + -- VRAM signals + signal vram_cs : std_logic; + signal vram_wr : std_logic; + signal vram_datao : std_logic_vector(7 downto 0); + + -- RAM signals + signal wram_cs : std_logic; + signal wram_wr : std_logic; + signal wram_datao : std_logic_vector(7 downto 0); + + -- IO signals + signal port_cs : std_logic_vector(5 downto 0); + signal port_wr : std_logic_vector(5 downto 2); + alias game_reset : std_logic is inputs_i(2).d(0); + signal shift_dout : std_logic_vector(7 downto 0); + + -- other signals + signal cpu_reset : std_logic; + signal cpu_mem_d_i : std_logic_vector(7 downto 0); + signal cpu_io_d_i : std_logic_vector(7 downto 0); + + signal spec_key_en : std_logic_vector(7 downto 0); + alias osd_key_en : std_logic is spec_key_en(1); + alias rot_key_en : std_logic is spec_key_en(2); + +begin + + assert false + report "CLK0_FREQ_MHz=" & integer'image(CLK0_FREQ_MHz) & + " CPU_FREQ_MHz=" & integer'image(CPU_FREQ_MHz) & + " CPU_CLK_ENA_DIV=" & integer'image(INVADERS_CPU_CLK_ENA_DIVIDE_BY) + severity note; + + cpu_reset <= clkrst_i.arst or game_reset; + + -- read mux + cpu_d_i <= cpu_mem_d_i when (cpu_mem_rd = '1') else cpu_io_d_i; + + -- memory chip selects + -- ROM0 $0000-$1FFF + rom0_cs <= '1' when cpu_a(14 downto 13) = "00" else '0'; + -- WRAM $2000-$23FF + wram_cs <= '1' when cpu_a(14 downto 10) = "01000" else '0'; + -- VRAM $2400-$3FFF + vram_cs <= '1' when cpu_a(14 downto 13) = "01" and cpu_a(12 downto 10) /= "000" else '0'; + -- ROM1 $4000-$5FFF + rom1_cs <= '1' when cpu_a(14 downto 13) = "10" else '0'; + + -- memory write enables + vram_wr <= vram_cs and cpu_mem_wr; + wram_wr <= wram_cs and cpu_mem_wr; + + -- I/O chip selects + -- inputs port 0 + port_cs(0) <= '1' when cpu_a(2 downto 0) = "000" else '0'; + -- inputs port 1 + port_cs(1) <= '1' when cpu_a(2 downto 0) = "001" else '0'; + -- number of bits to shift ($2) + port_cs(2) <= '1' when cpu_a(2 downto 0) = "010" else '0'; + -- sound reg #1 ($3) + port_cs(3) <= '1' when cpu_a(2 downto 0) = "011" else '0'; + -- shifter data ($4) + port_cs(4) <= '1' when cpu_a(2 downto 0) = "100" else '0'; + -- sound reg #2 ($5) + port_cs(5) <= '1' when cpu_a(2 downto 0) = "101" else '0'; + + -- io write enables + port_wr(2) <= port_cs(2) and cpu_io_wr; + port_wr(3) <= port_cs(3) and cpu_io_wr; + port_wr(4) <= port_cs(4) and cpu_io_wr; + port_wr(5) <= port_cs(5) and cpu_io_wr; + + -- sound interface + snd_o.rd <= (port_cs(3) or port_cs(5)) and cpu_io_rd; -- not used + snd_o.wr <= (port_cs(3) or port_cs(5)) and cpu_io_wr; + snd_o.d <= cpu_d_o; + snd_o.a <= cpu_a(snd_o.a'range); + + -- memory read mux + cpu_mem_d_i <= rom0_datao when rom0_cs = '1' else + wram_datao when wram_cs = '1' else + vram_datao when vram_cs = '1' else + rom1_datao when rom1_cs = '1' else + (others => '1'); + + -- io read mux + cpu_io_d_i <= X"40" when port_cs(0) = '1' else + inputs_i(0).d when port_cs(1) = '1' else + inputs_i(1).d when port_cs(2) = '1' else + shift_dout when port_cs(3) = '1' else + X"00"; + + -- shifter block + process (clk_sys, clkrst_i.arst) + variable shift_din : std_logic_vector(15 downto 0); + variable shift_amt : std_logic_vector(2 downto 0); + variable wr2_r : std_logic := '0'; + variable wr4_r : std_logic := '0'; + begin + if clkrst_i.arst = '1' then + wr2_r := '0'; + wr4_r := '0'; + elsif rising_edge(clk_sys) then + -- latch on rising edge of WR to port 2 (shift_amt) + if port_wr(2) = '1' and wr2_r = '0' then + shift_amt := cpu_d_o(2 downto 0); + -- latch on rising edge of WR to port 4 (shift_din) + elsif port_wr(4) = '1' and wr4_r = '0' then + shift_din := cpu_d_o & shift_din(15 downto 8); + end if; + wr2_r := port_wr(2); + wr4_r := port_wr(4); + end if; + + -- combinatorial logic + case shift_amt(2 downto 0) is + when "000" => + shift_dout <= shift_din(15 downto 8); + when "001" => + shift_dout <= shift_din(14 downto 7); + when "010" => + shift_dout <= shift_din(13 downto 6); + when "011" => + shift_dout <= shift_din(12 downto 5); + when "100" => + shift_dout <= shift_din(11 downto 4); + when "101" => + shift_dout <= shift_din(10 downto 3); + when "110" => + shift_dout <= shift_din(9 downto 2); + when "111" => + shift_dout <= shift_din(8 downto 1); + when others => + end case; + + end process; + + INT_BLOCK : block + + constant RST08 : std_logic_vector(7 downto 0) := X"CF"; + constant RST10 : std_logic_vector(7 downto 0) := X"D7"; + + begin + + process (clk_sys, cpu_reset) + subtype count_60Hz_t is integer range 0 to CLK0_FREQ_MHz * 1000000 / 60 - 1; + variable count : count_60Hz_t; + begin + if cpu_reset = '1' then + cpu_irq <= '0'; + count := 0; + elsif rising_edge(clk_sys) then + -- generate interrupt + count := count + 1; + if count = count_60Hz_t'high/2 then + cpu_irq <= '1'; + cpu_intvec <= RST08; + elsif count = count_60Hz_t'high then + count := 0; + cpu_irq <= '1'; + cpu_intvec <= RST10; + -- clear interrupt + elsif cpu_intack = '1' then + cpu_irq <= '0'; + end if; + end if; + end process; + + end block INT_BLOCK; + + -- special keys + process (clk_sys, clkrst_i.arst) + variable spec_key_r : std_logic_vector(7 downto 0); + begin + if clkrst_i.arst = '1' then + spec_key_r := (others => '0'); + osd_key_en <= '0'; + rot_key_en <= to_std_logic(INVADERS_ROTATE_VIDEO); + elsif rising_edge(clk_sys) then + for i in 0 to 7 loop + if inputs_i(2).d(i) = '1' and spec_key_r(i) = '0' then + spec_key_en <= not spec_key_en; + end if; + end loop; + spec_key_r := inputs_i(2).d; + end if; + end process; + + -- video rotate key + graphics_o.bit8(0)(0) <= rot_key_en; + + -- generate CPU clock (2MHz from 20MHz) + clk_en_inst : entity work.clk_div + generic map + ( + DIVISOR => integer(INVADERS_CPU_CLK_ENA_DIVIDE_BY) + ) + port map + ( + clk => clk_sys, + reset => clkrst_i.arst, + clk_en => clk_2M_en + ); + + U_uP : entity work.Z80 + port map + ( + clk => clk_sys, + clk_en => clk_2M_en, + reset => cpu_reset, + + addr => cpu_a, + datai => cpu_d_i, + datao => cpu_d_o, + + mem_rd => cpu_mem_rd, + mem_wr => cpu_mem_wr, + io_rd => cpu_io_rd, + io_wr => cpu_io_wr, + + intreq => cpu_irq, + intvec => cpu_intvec, + intack => cpu_intack, + nmi => '0' + ); + + + + rom0_inst : entity work.invaders_rom_0 + port map + ( + clock => clk_sys, + address => cpu_a(12 downto 0), + q => rom0_datao + ); + + + -- this should be inside the above generate + -- but this crashes Quartus v10.1SP1 + GEN_ROM1 : if ROM_1_NAME /= "" generate + rom1_inst : entity work.invaders_rom_1 + port map + ( + clock => clk_sys, + address => cpu_a(11 downto 0), + q => rom1_datao + ); + else generate + rom1_datao <= (others => '0'); + end generate GEN_ROM1; + + -- + -- *** WARNING - the contents of the VRAM are offset!!! + -- - the video won't look right!!!! + -- + + -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE + vram_inst : entity work.vram + port map + ( + clock_b => clk_sys, + address_b => cpu_a(12 downto 0), + data_b => cpu_d_o, + q_b => vram_datao, + wren_b => vram_wr, + + clock_a => clk_video, + address_a => bitmap_i(1).a(12 downto 0), + data_a => (others => '0'), + q_a => bitmap_o(1).d(7 downto 0), + wren_a => '0' + ); + + + wram_inst : entity work.wram + port map + ( + clock => clk_sys, + address => cpu_a(9 downto 0), + data => cpu_d_o, + wren => wram_wr, + q => wram_datao + ); + + + -- unused outputs + + --graphics_o <= NULL_TO_GRAPHICS; + --tilemap_o <= NULL_TO_TILEMAP_CTL; + sprite_reg_o <= NULL_TO_SPRITE_REG; + sprite_o <= NULL_TO_SPRITE_CTL; + leds_o <= (others => '0'); + +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform_pkg.vhd new file mode 100644 index 00000000..6fddf103 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform_pkg.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.project_pkg.all; +use work.target_pkg.all; + +package platform_pkg is + + + constant PACE_VIDEO_NUM_BITMAPS : natural := 1; + constant PACE_VIDEO_NUM_TILEMAPS : natural := 0; + constant PACE_VIDEO_NUM_SPRITES : natural := 0; + constant PACE_VIDEO_H_SIZE : integer := 224; + constant PACE_VIDEO_V_SIZE : integer := 256; + constant PACE_VIDEO_L_CROP : integer := 0; + constant PACE_VIDEO_R_CROP : integer := 0; + constant PACE_VIDEO_PIPELINE_DELAY : integer := 3; + constant PACE_INPUTS_NUM_BYTES : integer := 3; + + -- + -- Platform-specific constants (optional) + -- + + constant CLK0_FREQ_MHz : natural := 20; + constant CPU_FREQ_MHz : natural := 2; + + constant INVADERS_CPU_CLK_ENA_DIVIDE_BY : natural := 20 / 2; + + type from_PLATFORM_IO_t is record + not_used : std_logic; + end record; + + type to_PLATFORM_IO_t is record + not_used : std_logic; + end record; + +end package; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd new file mode 100644 index 00000000..3525ece3 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/platform_variant_pkg.vhd @@ -0,0 +1,116 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package platform_variant_pkg is + + -- + -- Platform-variant-specific constants (optional) + -- + +--Test Area + --$0000 + constant ROM_0_NAME : string := "../roms/jatrespecter.hex"; + --$4000 + constant ROM_1_NAME : string := ""; + constant VRAM_NAME : string := "../roms/sivram.hex"; + + +--**************************WORKING******************************************************** + +-- Space Invaders +-- constant ROM_0_NAME : string := "../roms/invaders0.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +-- Space Invaders 2 +-- constant ROM_0_NAME : string := "../roms/invadpt20.hex"; +-- constant ROM_1_NAME : string := "../roms/invadpt21.hex"; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +-- Super Earth Invasion +---constant ROM_0_NAME : string := "../roms/searthin.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := ""; + +-- Lunar Rescue +-- constant ROM_0_NAME : string := "../roms/lrescue0.hex"; +-- constant ROM_1_NAME : string := "../roms/lrescue1.hex"; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +-- Space Laser +-- constant ROM_0_NAME : string := "../roms/laser1.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/laser2.hex"; + +-- Galaxy Wars +-- constant ROM_0_NAME : string := "../roms/galxwars0.hex"; +-- constant ROM_1_NAME : string := "../roms/galxwars1.hex"; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +-- Space Attack II +-- constant ROM_0_NAME : string := "../roms/spaceatt.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := ""; + + + +--**************************NOT WORKING******************************************************** +--Yosaku To Donbei (set1) +-- constant ROM_0_NAME : string := "../roms/yosakdon.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := ""; + +--Yosaku To Donbei (set2) +-- constant ROM_0_NAME : string := "../roms/yosakdona.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := ""; + + +-- Ball Bomb +-- constant ROM_0_NAME : string := "../roms/bomb1.hex"; +-- constant ROM_1_NAME : string := "../roms/bomb2.hex"; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + + +--4 Player Bowling Alley +-- constant ROM_0_NAME : string := "../roms/bowler1.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/bowler2.hex"; + +-- Gunfight(todo Controls) +-- constant ROM_0_NAME : string := "../roms/gunfight.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := ""; + +-- Boot Hill(todo Controls) +-- constant ROM_0_NAME : string := "../roms/boothill.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +--Check Mate +-- constant ROM_0_NAME : string := "../roms/checkmate.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +--Datsun 280 zzz +-- constant ROM_0_NAME : string := "../roms/280zzzap.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +--PhantomII +-- constant ROM_0_NAME : string := "../roms/phantomII.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/phantomIIprom.hex"; + +-- Space Encounter +-- constant ROM_0_NAME : string := "../roms/spaceenc1.hex"; +-- constant ROM_1_NAME : string := "../roms/spaceenc1.hex"; +-- constant VRAM_NAME : string := ""; + +--Jatre Spectre +-- constant ROM_0_NAME : string := "../roms/jatrespecter.hex"; +-- constant ROM_1_NAME : string := ""; +-- constant VRAM_NAME : string := "../roms/sivram.hex"; + +end; \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pll.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pll.vhd new file mode 100644 index 00000000..366ea101 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pll.vhd @@ -0,0 +1,186 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +entity pll is + generic + ( + -- INCLK + INCLK0_INPUT_FREQUENCY : natural; + + -- CLK0 + CLK0_DIVIDE_BY : natural := 1; + CLK0_DUTY_CYCLE : natural := 50; + CLK0_MULTIPLY_BY : natural := 1; + CLK0_PHASE_SHIFT : string := "0"; + + -- CLK1 + CLK1_DIVIDE_BY : natural := 1; + CLK1_DUTY_CYCLE : natural := 50; + CLK1_MULTIPLY_BY : natural := 1; + CLK1_PHASE_SHIFT : string := "0" + ); + port + ( + inclk0 : in std_logic := '0'; + c0 : out std_logic ; + c1 : out std_logic + ); +END pll; + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_enable0 : STRING; + port_enable1 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + port_extclkena0 : STRING; + port_extclkena1 : STRING; + port_extclkena2 : STRING; + port_extclkena3 : STRING; + port_sclkout0 : STRING; + port_sclkout1 : STRING + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => CLK0_DIVIDE_BY, + clk0_duty_cycle => CLK0_DUTY_CYCLE, + clk0_multiply_by => CLK0_MULTIPLY_BY, + clk0_phase_shift => CLK0_PHASE_SHIFT, + clk1_divide_by => CLK1_DIVIDE_BY, + clk1_duty_cycle => CLK1_DUTY_CYCLE, + clk1_multiply_by => CLK1_MULTIPLY_BY, + clk1_phase_shift => CLK1_PHASE_SHIFT, + compensate_clock => "CLK0", + inclk0_input_frequency => INCLK0_INPUT_FREQUENCY, + intended_device_family => "Cyclone II", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "FAST", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_enable0 => "PORT_UNUSED", + port_enable1 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + port_extclkena0 => "PORT_UNUSED", + port_extclkena1 => "PORT_UNUSED", + port_extclkena2 => "PORT_UNUSED", + port_extclkena3 => "PORT_UNUSED", + port_sclkout0 => "PORT_UNUSED", + port_sclkout1 => "PORT_UNUSED" + ) + PORT MAP ( + inclk => sub_wire4, + clk => sub_wire0 + ); + + + +END SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.qip b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.qip new file mode 100644 index 00000000..26d620d6 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllclk_ez.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.ppf"] diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.vhd new file mode 100644 index 00000000..78d02f52 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.vhd @@ -0,0 +1,399 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pllclk_ez.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pllclk_ez IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pllclk_ez; + + +ARCHITECTURE SYN OF pllclk_ez IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 20, + clk0_phase_shift => "0", + clk1_divide_by => 27, + clk1_duty_cycle => 50, + clk1_multiply_by => 40, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pllclk_ez", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllclk_ez.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/project_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/project_pkg.vhd new file mode 100644 index 00000000..f1c5289f --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/project_pkg.vhd @@ -0,0 +1,52 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; + +package project_pkg is + + -- + -- PACE constants which *MUST* be defined + -- + + constant PACE_HAS_PLL : boolean := true; + constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz; + constant PACE_CLK0_DIVIDE_BY : natural := 27; + constant PACE_CLK0_MULTIPLY_BY : natural := 20; -- 50*2/5 = 20MHz + constant PACE_CLK1_DIVIDE_BY : natural := 27; + constant PACE_CLK1_MULTIPLY_BY : natural := 40; -- 50*4/5 = 40MHz + constant PACE_VIDEO_H_SCALE : integer := 2; + constant PACE_VIDEO_V_SCALE : integer := 2; + constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1'; -- Not currently used? + constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1'; + constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK; + + constant PACE_HAS_OSD : boolean := false; + constant PACE_OSD_XPOS : natural := 0; + constant PACE_OSD_YPOS : natural := 0; + + -- Invaders-specific constants + + -- rotate native video (for VGA monitor) + -- - need to change H,V size in platform_pkg.vhd +-- constant INVADERS_ROTATE_VIDEO : boolean := true; + + constant INVADERS_ROM_IN_FLASH : boolean := false; + constant PACE_HAS_FLASH : boolean := false; + + constant INVADERS_USE_INTERNAL_WRAM : boolean := true; + constant PACE_HAS_SRAM : boolean := false; + constant USE_VIDEO_VBLANK_INTERRUPT : boolean := false; + + type from_PROJECT_IO_t is record + not_used : std_logic; + end record; + + type to_PROJECT_IO_t is record + not_used : std_logic; + end record; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/ps2kbd.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/ps2kbd.vhd new file mode 100644 index 00000000..6bd6983c --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/ps2kbd.vhd @@ -0,0 +1,202 @@ +-- PS/2 serial port, input only +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXKeyDown OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : First KeyUp +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ps2kbd is + port( + Rst_n : in std_logic; + Clk : in std_logic; + Tick1us : in std_logic; + PS2_Clk : in std_logic; + PS2_Data : in std_logic; + KeyDown : out std_logic; + KeyUp : out std_logic; + Reset : out std_logic; + ScanCode : out std_logic_vector(7 downto 0)); +end ps2kbd; + +architecture rtl of ps2kbd is + + signal PS2_Sample : std_logic; + signal PS2_Data_s : std_logic; + + signal RX_Bit_Cnt : unsigned(3 downto 0); + signal RX_Byte : unsigned(2 downto 0); + signal RX_ShiftReg : std_logic_vector(7 downto 0); + signal RX_KeyUp : std_logic; + signal RX_Received : std_logic; + +begin + + ScanCode <= RX_ShiftReg; + + process (Clk, Rst_n) + variable PS2_Data_r : std_logic_vector(1 downto 0); + variable PS2_Clk_r : std_logic_vector(1 downto 0); + variable PS2_Clk_State : std_logic; + begin + if Rst_n = '0' then + PS2_Sample <= '0'; + PS2_Data_s <= '0'; + PS2_Data_r := "11"; + PS2_Clk_r := "11"; + PS2_Clk_State := '1'; + elsif Clk'event and Clk = '1' then + if Tick1us = '1' then + PS2_Sample <= '0'; + + -- Deglitch + if PS2_Data_r = "00" then + PS2_Data_s <= '0'; + end if; + if PS2_Data_r = "11" then + PS2_Data_s <= '1'; + end if; + if PS2_Clk_r = "00" then + if PS2_Clk_State = '1' then + PS2_Sample <= '1'; + end if; + PS2_Clk_State := '0'; + end if; + if PS2_Clk_r = "11" then + PS2_Clk_State := '1'; + end if; + + -- Double synchronise + PS2_Data_r(1) := PS2_Data_r(0); + PS2_Clk_r(1) := PS2_Clk_r(0); + PS2_Data_r(0) := PS2_Data; + PS2_Clk_r(0) := PS2_Clk; + end if; + end if; + end process; + + process (Clk, Rst_n) + variable Cnt : integer; + begin + if Rst_n = '0' then + RX_Bit_Cnt <= (others => '0'); + RX_ShiftReg <= (others => '0'); + RX_Received <= '0'; + Cnt := 0; + elsif Clk'event and Clk = '1' then + RX_Received <= '0'; + if Tick1us = '1' then + + if PS2_Sample = '1' then + if RX_Bit_Cnt = "0000" then + if PS2_Data_s = '0' then -- Start bit + RX_Bit_Cnt <= RX_Bit_Cnt + 1; + end if; + elsif RX_Bit_Cnt = "1001" then -- Parity bit + RX_Bit_Cnt <= RX_Bit_Cnt + 1; + -- Ignoring parity + elsif RX_Bit_Cnt = "1010" then -- Stop bit + if PS2_Data_s = '1' then + RX_Received <= '1'; + end if; + RX_Bit_Cnt <= "0000"; + else + RX_Bit_Cnt <= RX_Bit_Cnt + 1; + RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1); + RX_ShiftReg(7) <= PS2_Data_s; + end if; + end if; + + -- TimeOut + if PS2_Sample = '1' then + Cnt := 0; + elsif Cnt = 127 then + RX_Bit_Cnt <= "0000"; + Cnt := 0; + else + Cnt := Cnt + 1; + end if; + end if; + end if; + end process; + + process (Clk, Rst_n) + begin + if Rst_n = '0' then + KeyDown <= '0'; + KeyUp <= '0'; + Reset <= '0'; + RX_Byte <= (others => '0'); + RX_KeyUp <= '0'; + elsif Clk'event and Clk = '1' then + KeyDown <= '0'; + KeyUp <= '0'; + Reset <= '0'; + if RX_Received = '1' then + RX_Byte <= RX_Byte + 1; + if RX_ShiftReg = x"F0" then + RX_KeyUp <= '1'; + elsif RX_ShiftReg = x"E0" then + else + RX_KeyUp <= '0'; + -- Normal key KeyDown + if RX_KeyUp = '0' then + KeyDown <= '1'; + end if; + -- Normal key KeyUp + if RX_KeyUp = '1' then + KeyUp <= '1'; + end if; + end if; + if RX_ShiftReg = x"aa" then + Reset <= '1'; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/ps2kbd_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/ps2kbd_pkg.vhd new file mode 100644 index 00000000..0fc93379 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/ps2kbd_pkg.vhd @@ -0,0 +1,111 @@ +library ieee; +use ieee.std_logic_1164.all; + +package kbd_pkg is + + constant SCANCODE_BACKQUOTE : std_logic_vector(7 downto 0) := X"0E"; + constant SCANCODE_A : std_logic_vector(7 downto 0) := X"1C"; + constant SCANCODE_B : std_logic_vector(7 downto 0) := X"32"; + constant SCANCODE_C : std_logic_vector(7 downto 0) := X"21"; + constant SCANCODE_D : std_logic_vector(7 downto 0) := X"23"; + constant SCANCODE_E : std_logic_vector(7 downto 0) := X"24"; + constant SCANCODE_F : std_logic_vector(7 downto 0) := X"2B"; + constant SCANCODE_G : std_logic_vector(7 downto 0) := X"34"; + constant SCANCODE_H : std_logic_vector(7 downto 0) := X"33"; + constant SCANCODE_I : std_logic_vector(7 downto 0) := X"43"; + constant SCANCODE_J : std_logic_vector(7 downto 0) := X"3B"; + constant SCANCODE_K : std_logic_vector(7 downto 0) := X"42"; + constant SCANCODE_L : std_logic_vector(7 downto 0) := X"4B"; + constant SCANCODE_M : std_logic_vector(7 downto 0) := X"3A"; + constant SCANCODE_N : std_logic_vector(7 downto 0) := X"31"; + constant SCANCODE_O : std_logic_vector(7 downto 0) := X"44"; + constant SCANCODE_P : std_logic_vector(7 downto 0) := X"4D"; + constant SCANCODE_Q : std_logic_vector(7 downto 0) := X"15"; + constant SCANCODE_R : std_logic_vector(7 downto 0) := X"2D"; + constant SCANCODE_S : std_logic_vector(7 downto 0) := X"1B"; + constant SCANCODE_T : std_logic_vector(7 downto 0) := X"2C"; + constant SCANCODE_U : std_logic_vector(7 downto 0) := X"3C"; + constant SCANCODE_V : std_logic_vector(7 downto 0) := X"2A"; + constant SCANCODE_W : std_logic_vector(7 downto 0) := X"1D"; + constant SCANCODE_X : std_logic_vector(7 downto 0) := X"22"; + constant SCANCODE_Y : std_logic_vector(7 downto 0) := X"35"; + constant SCANCODE_Z : std_logic_vector(7 downto 0) := X"1A"; + constant SCANCODE_0 : std_logic_vector(7 downto 0) := X"45"; + constant SCANCODE_1 : std_logic_vector(7 downto 0) := X"16"; + constant SCANCODE_2 : std_logic_vector(7 downto 0) := X"1E"; + constant SCANCODE_3 : std_logic_vector(7 downto 0) := X"26"; + constant SCANCODE_4 : std_logic_vector(7 downto 0) := X"25"; + constant SCANCODE_5 : std_logic_vector(7 downto 0) := X"2E"; + constant SCANCODE_6 : std_logic_vector(7 downto 0) := X"36"; + constant SCANCODE_7 : std_logic_vector(7 downto 0) := X"3D"; + constant SCANCODE_8 : std_logic_vector(7 downto 0) := X"3E"; + constant SCANCODE_9 : std_logic_vector(7 downto 0) := X"46"; + constant SCANCODE_QUOTE : std_logic_vector(7 downto 0) := X"52"; + constant SCANCODE_SEMICOLON : std_logic_vector(7 downto 0) := X"4C"; + constant SCANCODE_COMMA : std_logic_vector(7 downto 0) := X"41"; + constant SCANCODE_MINUS : std_logic_vector(7 downto 0) := X"4E"; + constant SCANCODE_PERIOD : std_logic_vector(7 downto 0) := X"49"; + constant SCANCODE_SLASH : std_logic_vector(7 downto 0) := X"4A"; + constant SCANCODE_ENTER : std_logic_vector(7 downto 0) := X"5A"; + constant SCANCODE_HOME : std_logic_vector(7 downto 0) := X"6C"; + constant SCANCODE_INS : std_logic_vector(7 downto 0) := X"70"; -- E0 + constant SCANCODE_PGUP : std_logic_vector(7 downto 0) := X"7D"; -- E0 + constant SCANCODE_DELETE : std_logic_vector(7 downto 0) := X"71"; -- E0 + constant SCANCODE_PGDN : std_logic_vector(7 downto 0) := X"7A"; -- E0 + constant SCANCODE_UP : std_logic_vector(7 downto 0) := X"75"; -- E0 + constant SCANCODE_DOWN : std_logic_vector(7 downto 0) := X"72"; -- E0 + constant SCANCODE_LEFT : std_logic_vector(7 downto 0) := X"6B"; -- E0 + constant SCANCODE_BACKSPACE : std_logic_vector(7 downto 0) := X"66"; + constant SCANCODE_RIGHT : std_logic_vector(7 downto 0) := X"74"; -- E0 + constant SCANCODE_SPACE : std_logic_vector(7 downto 0) := X"29"; + constant SCANCODE_LSHIFT : std_logic_vector(7 downto 0) := X"12"; + constant SCANCODE_RSHIFT : std_logic_vector(7 downto 0) := X"59"; + constant SCANCODE_TAB : std_logic_vector(7 downto 0) := X"0D"; + constant SCANCODE_ESC : std_logic_vector(7 downto 0) := X"76"; + constant SCANCODE_EQUALS : std_logic_vector(7 downto 0) := X"55"; + constant SCANCODE_F1 : std_logic_vector(7 downto 0) := X"05"; + constant SCANCODE_F2 : std_logic_vector(7 downto 0) := X"06"; + constant SCANCODE_F3 : std_logic_vector(7 downto 0) := X"04"; + constant SCANCODE_F4 : std_logic_vector(7 downto 0) := X"0C"; + constant SCANCODE_F5 : std_logic_vector(7 downto 0) := X"03"; + constant SCANCODE_F6 : std_logic_vector(7 downto 0) := X"0B"; + constant SCANCODE_F7 : std_logic_vector(7 downto 0) := X"83"; + constant SCANCODE_F8 : std_logic_vector(7 downto 0) := X"0A"; + constant SCANCODE_F9 : std_logic_vector(7 downto 0) := X"01"; + constant SCANCODE_F10 : std_logic_vector(7 downto 0) := X"09"; + constant SCANCODE_F11 : std_logic_vector(7 downto 0) := X"78"; + constant SCANCODE_F12 : std_logic_vector(7 downto 0) := X"07"; + constant SCANCODE_SCROLL : std_logic_vector(7 downto 0) := X"7E"; + constant SCANCODE_CAPSLOCK : std_logic_vector(7 downto 0) := X"58"; + constant SCANCODE_BACKSLASH : std_logic_vector(7 downto 0) := X"5D"; + constant SCANCODE_NUMLOCK : std_logic_vector(7 downto 0) := X"77"; + constant SCANCODE_LCTRL : std_logic_vector(7 downto 0) := X"14"; + constant SCANCODE_LGUI : std_logic_vector(7 downto 0) := X"1F"; -- E0 + constant SCANCODE_LALT : std_logic_vector(7 downto 0) := X"11"; + constant SCANCODE_RGUI : std_logic_vector(7 downto 0) := X"27"; -- E0 + --constant SCANCODE_RALT : std_logic_vector(7 downto 0) := X"11"; + alias SCANCODE_TILDE : std_logic_vector(7 downto 0) is SCANCODE_BACKQUOTE; + constant SCANCODE_OPENBRKT : std_logic_vector(7 downto 0) := X"54"; + alias SCANCODE_OPENBRACE : std_logic_vector(7 downto 0) is SCANCODE_OPENBRKT; + constant SCANCODE_CLOSEBRKT : std_logic_vector(7 downto 0) := X"5B"; + alias SCANCODE_CLOSEBRACE : std_logic_vector(7 downto 0) is SCANCODE_CLOSEBRKT; + constant SCANCODE_END : std_logic_vector(7 downto 0) := X"69"; -- E0 + alias SCANCODE_PAD0 : std_logic_vector(7 downto 0) is SCANCODE_INS; + alias SCANCODE_PAD1 : std_logic_vector(7 downto 0) is SCANCODE_END; + alias SCANCODE_PAD2 : std_logic_vector(7 downto 0) is SCANCODE_DOWN; + alias SCANCODE_PAD3 : std_logic_vector(7 downto 0) is SCANCODE_PGDN; + alias SCANCODE_PAD4 : std_logic_vector(7 downto 0) is SCANCODE_LEFT; + constant SCANCODE_PAD5 : std_logic_vector(7 downto 0) := X"73"; + alias SCANCODE_PAD6 : std_logic_vector(7 downto 0) is SCANCODE_RIGHT; + alias SCANCODE_PAD7 : std_logic_vector(7 downto 0) is SCANCODE_HOME; + alias SCANCODE_PAD8 : std_logic_vector(7 downto 0) is SCANCODE_UP; + alias SCANCODE_PAD9 : std_logic_vector(7 downto 0) is SCANCODE_PGUP; + constant SCANCODE_PADPLUS : std_logic_vector(7 downto 0) := X"79"; + constant SCANCODE_PADMINUS : std_logic_vector(7 downto 0) := X"7B"; + constant SCANCODE_PADTIMES : std_logic_vector(7 downto 0) := X"7C"; + constant SCANCODE_PADEQUALS : std_logic_vector(7 downto 0) := X"0F"; + + type kbd_row is array (natural range <>) of std_logic_vector(7 downto 0); + type kbd_col is array (natural range <>) of std_logic_vector(7 downto 0); + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/spram.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/spram.vhd new file mode 100644 index 00000000..64bfc2b8 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/spram.vhd @@ -0,0 +1,84 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + power_up_uninitialized => "FALSE", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + +END SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprite_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprite_pkg.vhd new file mode 100644 index 00000000..ee5cf179 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprite_pkg.vhd @@ -0,0 +1,97 @@ +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.numeric_std.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +use work.video_controller_pkg.all; + +package sprite_pkg is + + subtype SPRITE_N_t is std_logic_vector(11 downto 0); + subtype SPRITE_A_t is std_logic_vector(7 downto 0); + subtype SPRITE_D_t is std_logic_vector(7 downto 0); + + type from_SPRITE_REG_t is record + n : SPRITE_N_t; + x : std_logic_vector(10 downto 0); + y : std_logic_vector(10 downto 0); + xflip : std_logic; + yflip : std_logic; + colour : std_logic_vector(7 downto 0); + pri : std_logic; + end record; + + type to_SPRITE_REG_t is record + clk : std_logic; + clk_ena : std_logic; + wr : std_logic; + a : SPRITE_A_t; + d : SPRITE_D_t; + end record; + + function NULL_TO_SPRITE_REG return to_SPRITE_REG_t; + + subtype SPRITE_ROW_D_t is std_logic_vector(63 downto 0); + subtype SPRITE_ROW_A_t is std_logic_vector(15 downto 0); + + type to_SPRITE_CTL_t is record + ld : std_logic; + d : SPRITE_ROW_D_t; + end record; + + type from_SPRITE_CTL_t is record + a : SPRITE_ROW_A_t; + rgb : RGB_t; + set : std_logic; + end record; + + function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t; + + component sprite_array is + generic + ( + N_SPRITES : integer; + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- register interface + reg_i : in to_SPRITE_REG_t; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- extra data + graphics_i : in to_GRAPHICS_t; + + -- sprite data + row_a : out SPRITE_ROW_A_t; + row_d : in SPRITE_ROW_D_t; + + -- video data + rgb : out RGB_t; + set : out std_logic; + pri : out std_logic; + spr0_set : out std_logic + ); + end component sprite_array; + + function flip_row + ( + row_in : std_logic_vector; + flip : std_logic + ) + return SPRITE_ROW_D_t; + + function flip_1 + ( + d_i : std_logic_vector; + flip : std_logic + ) + return std_logic_vector; + +end package sprite_pkg; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprite_pkg_body.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprite_pkg_body.vhd new file mode 100644 index 00000000..551261b2 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprite_pkg_body.vhd @@ -0,0 +1,62 @@ +library work; +use work.pace_pkg.all; +--use work.sprite_pkg.all; + +package body sprite_pkg is + + function NULL_TO_SPRITE_REG return to_SPRITE_REG_t is + begin + return ('0', '0', '0', (others => '0'), (others => '0')); + end function NULL_TO_SPRITE_REG; + + function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t is + begin + return ('0', (others => '0')); + end function NULL_TO_SPRITE_CTL; + + function flip_row + ( + row_in : std_logic_vector; + flip : std_logic + ) + return std_logic_vector is + + constant HALF : natural := (row_in'length / 2) - 1; + + alias row_in_0 : std_logic_vector(row_in'length-1 downto 0) + is row_in; + variable row_out : std_logic_vector(row_in_0'range); + + begin + + if flip = '0' then + return row_in; + else + for i in 0 to HALF loop + row_out ((HALF-i)*2+1 downto (HALF-i)*2) := row_in_0(i*2+1 downto i*2); + end loop; + return row_out; + end if; + + end flip_row; + + function flip_1 + ( + d_i : std_logic_vector; + flip : std_logic + ) + return std_logic_vector is + alias d_i_0 : std_logic_vector(d_i'length-1 downto 0) is d_i; + variable d_o : std_logic_vector(d_i_0'range); + begin + if flip = '0' then + return d_i; + else + for i in d_i_0'range loop + d_o(i) := d_i_0(d_i_0'high-i); + end loop; + return d_o; + end if; + end function flip_1; + +end package body sprite_pkg; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprom.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprom.vhd new file mode 100644 index 00000000..3ec3beb7 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/sprom.vhd @@ -0,0 +1,77 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY sprom IS + GENERIC + ( + init_file : string := ""; + numwords_a : natural := 0; -- not used any more + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END sprom; + + +ARCHITECTURE SYN OF sprom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2**widthad_a, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + +END SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/tilemapctl_e.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/tilemapctl_e.vhd new file mode 100644 index 00000000..68d3fd1a --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/tilemapctl_e.vhd @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.project_pkg.all; +use work.platform_pkg.all; +use work.video_controller_pkg.all; + +entity tilemapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- tilemap controller signals + ctl_i : in to_TILEMAP_CTL_t; + ctl_o : out from_TILEMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); +end entity tilemapCtl; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller.vhd new file mode 100644 index 00000000..14da0c20 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller.vhd @@ -0,0 +1,455 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.video_controller_pkg.all; + +entity pace_video_controller is + generic + ( + CONFIG : PACEVideoController_t := PACE_VIDEO_NONE; + DELAY : integer := 1; + H_SIZE : integer; + V_SIZE : integer; + L_CROP : integer range 0 to 255; + R_CROP : integer range 0 to 255; + H_SCALE : integer; + V_SCALE : integer; + H_SYNC_POL : std_logic := '1'; + V_SYNC_POL : std_logic := '1'; + BORDER_RGB : RGB_t := RGB_BLACK + ); + port + ( + -- clocking etc + video_i : in from_VIDEO_t; + + -- register interface + reg_i : in VIDEO_REG_t; + + -- video input data + rgb_i : in RGB_t; + + -- control signals (out) + video_ctl_o : out from_VIDEO_CTL_t; + + -- video output control & data + video_o : out to_VIDEO_t + ); +end pace_video_controller; + +architecture SYN of pace_video_controller is + + constant SIM_DELAY : time := 2 ns; + + constant VIDEO_H_SIZE : integer := H_SIZE * H_SCALE; + constant VIDEO_V_SIZE : integer := V_SIZE * V_SCALE; + + subtype reg_t is integer range 0 to 2047; + + alias clk : std_logic is video_i.clk; + alias clk_ena : std_logic is video_i.clk_ena; + alias reset : std_logic is video_i.reset; + + -- registers + signal h_front_porch_r : reg_t := 0; + signal h_sync_r : reg_t := 0; + signal h_back_porch_r : reg_t := 0; + signal h_border_r : reg_t := 0; + signal h_video_r : reg_t := 0; + signal v_front_porch_r : reg_t := 0; + signal v_sync_r : reg_t := 0; + signal v_back_porch_r : reg_t := 0; + signal v_border_r : reg_t := 0; + signal v_video_r : reg_t := 0; + + signal border_rgb_r : RGB_t := ((others=>'0'), (others=>'0'), (others=>'0')); + + -- derived values + signal h_sync_start : reg_t := 0; + signal h_back_porch_start : reg_t := 0; + signal h_left_border_start : reg_t := 0; + signal h_video_start : reg_t := 0; + signal h_right_border_start : reg_t := 0; + signal h_line_end : reg_t := 0; + signal v_sync_start : reg_t := 0; + signal v_back_porch_start : reg_t := 0; + signal v_top_border_start : reg_t := 0; + signal v_video_start : reg_t := 0; + signal v_bottom_border_start : reg_t := 0; + signal v_screen_end : reg_t := 0; + + signal hsync_s : std_logic := '0'; + signal vsync_s : std_logic := '0'; + signal hactive_s : std_logic := '0'; + signal vactive_s : std_logic := '0'; + signal hblank_s : std_logic := '0'; + signal vblank_s : std_logic := '0'; + + subtype count_t is integer range 0 to 2047; + signal x_count : count_t := 0; + signal y_count : count_t := 0; + + signal x_s : unsigned(10 downto 0) := (others => '0'); + signal y_s : unsigned(10 downto 0) := (others => '0'); + + --signal extended_reset : std_logic := '1'; + alias extended_reset : std_logic is video_i.reset; + +begin + + -- registers + reg_proc: process (reset, clk) + + begin + --if reset = '1' then + case CONFIG is + + when PACE_VIDEO_VGA_240x320_60Hz => + -- P3M, clk=11.136MHz, clk_ena=5.568MHz + h_front_porch_r <= 272-240; + h_sync_r <= 5; + h_back_porch_r <= 22; + h_border_r <= (240-VIDEO_H_SIZE)/2; + v_front_porch_r <= 326-320; + v_sync_r <= 1; + v_back_porch_r <= 5; + v_border_r <= (320-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_320x480_60Hz => + -- VGA, clk=12.588MHz + --# 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio + --Modeline "320x240" 12.588 320 336 384 400 240 245 246 262 Doublescan + h_front_porch_r <= 16; + h_sync_r <= 48; + h_back_porch_r <= 16; + h_border_r <= (320-VIDEO_H_SIZE)/2; + v_front_porch_r <= (5*2); + v_sync_r <= (1*2); + v_back_porch_r <= (16*2); + v_border_r <= (480-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_640x480_60Hz => + -- VGA, clk=25.175MHz + h_front_porch_r <= 16; + h_sync_r <= 96; + h_back_porch_r <= 48; + h_border_r <= (640-VIDEO_H_SIZE)/2; + v_front_porch_r <= 10; + v_sync_r <= 2; + v_back_porch_r <= 33; + v_border_r <= (480-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_800x600_60Hz => + -- SVGA, clk=40MHz + h_front_porch_r <= 40; + h_sync_r <= 128; + h_back_porch_r <= 88; + h_border_r <= (800-VIDEO_H_SIZE)/2; + v_front_porch_r <= 1; + v_sync_r <= 4; + v_back_porch_r <= 23; + v_border_r <= (600-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1024x768_60Hz => + -- XVGA, clk=65MHz + h_front_porch_r <= 24; + h_sync_r <= 136; + h_back_porch_r <= 160; + h_border_r <= (1024-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 6; + v_back_porch_r <= 29; + v_border_r <= (768-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1366x768_60Hz => + -- XVGA(NAVICO ROCKY), clk=72MHz + h_front_porch_r <= 88; --64; + h_sync_r <= 44; --112; + h_back_porch_r <= 148; --248; + h_border_r <= (1366-VIDEO_H_SIZE)/2; + v_front_porch_r <= 4; --3; + v_sync_r <= 5; --6; + v_back_porch_r <= 36; --18; + v_border_r <= (768-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1280x800_60Hz => + -- Sentinel Mode 36, clk=103.2MHz + h_front_porch_r <= 64; + h_sync_r <= 32; + h_back_porch_r <= 362-32-64; + h_border_r <= (1280-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 4; + v_back_porch_r <= 38-4-3; + v_border_r <= (800-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1280x1024_60Hz => + -- SXGA, clk=108MHz + h_front_porch_r <= 48; + h_sync_r <= 112; + h_back_porch_r <= 248; + h_border_r <= (1280-VIDEO_H_SIZE)/2; + v_front_porch_r <= 1; + v_sync_r <= 3; + v_back_porch_r <= 38; + v_border_r <= (1024-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_VGA_1680x1050_60Hz => + -- WSXGA+, clk=147.14MHz + h_front_porch_r <= 104; + h_sync_r <= 184; + h_back_porch_r <= 288; + v_front_porch_r <= 1; + v_sync_r <= 3; + v_back_porch_r <= 33; + -- WSXGA+, clk=118MHz + --h_front_porch_r <= 48; + --h_sync_r <= 32; + --h_back_porch_r <= 80; + --v_front_porch_r <= 3; + --v_sync_r <= 6; + --v_back_porch_r <= 21; + h_border_r <= (1680-VIDEO_H_SIZE)/2; + v_border_r <= (1050-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_ARCADE_STD_336x240_60Hz => + -- arcade standard resolution, clk=7.16MHz + h_front_porch_r <= 34; + h_sync_r <= 34; + h_back_porch_r <= 51; + h_border_r <= (336-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 3; + v_back_porch_r <= 16; + v_border_r <= (240-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64 => + -- arcade standard resolution, clk=28.64MHz + h_front_porch_r <= 4*34; + h_sync_r <= 4*34; + h_back_porch_r <= 4*51; + h_border_r <= 4*(336-VIDEO_H_SIZE)/2; + v_front_porch_r <= 3; + v_sync_r <= 3; + v_back_porch_r <= 16; + v_border_r <= (240-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_CVBS_720x288p_50Hz => + -- generic composite, clk=13.5MHz + h_front_porch_r <= (8+12); + h_sync_r <= 64; + h_back_porch_r <= (144-64-(8+12)); + h_border_r <= (720-VIDEO_H_SIZE)/2; + v_front_porch_r <= 1; + v_sync_r <= 3; + v_back_porch_r <= 20; + v_border_r <= (288-VIDEO_V_SIZE)/2; + + when PACE_VIDEO_LCM_320x240_60Hz => + -- DE1/2, clk=18MHz + h_front_porch_r <= 59; + h_sync_r <= 1; + h_back_porch_r <= 151; + h_border_r <= (320-VIDEO_H_SIZE)*3/2; + v_front_porch_r <= 8; + v_sync_r <= 1; + v_back_porch_r <= 13; + v_border_r <= (240-VIDEO_V_SIZE)/2; + + when others => + null; + end case; + + h_video_r <= VIDEO_H_SIZE; + v_video_r <= VIDEO_V_SIZE; + border_rgb_r <= BORDER_RGB; + + --end if; + end process reg_proc; + + -- register some arithmetic + init_proc: process (reset, clk, clk_ena) + begin + if reset = '1' then + null; + elsif rising_edge(clk) then + h_sync_start <= h_front_porch_r - 1; + h_back_porch_start <= h_sync_start + h_sync_r; + h_left_border_start <= h_back_porch_start + h_back_porch_r; + h_video_start <= h_left_border_start + h_border_r; + h_right_border_start <= h_video_start + h_video_r; + h_line_end <= h_right_border_start + h_border_r; + v_sync_start <= v_front_porch_r - 1; + v_back_porch_start <= v_sync_start + v_sync_r; + v_top_border_start <= v_back_porch_start + v_back_porch_r; + v_video_start <= v_top_border_start + v_border_r; + v_bottom_border_start <= v_video_start + v_video_r; + v_screen_end <= v_bottom_border_start + v_border_r; + end if; + end process init_proc; + + reset_proc: process (reset, clk) + variable count_v : integer; + begin + if reset = '1' then + --extended_reset <= '1'; + count_v := 7; + elsif rising_edge(clk) then + if count_v = 0 then + --extended_reset <= '0'; + else + count_v := count_v - 1; + end if; + end if; + end process reset_proc; + + -- video control outputs + timer_proc: process (extended_reset, clk, clk_ena) + begin + if extended_reset = '1' then + hblank_s <= '1'; + vblank_s <= '1'; + hactive_s <= '0'; + vactive_s <= '0'; + hsync_s <= not H_SYNC_POL; + x_count <= 0; + y_count <= 0; + elsif rising_edge(clk) and clk_ena = '1' then + if x_count = h_line_end then + hblank_s <= '1'; + hactive_s <= '0'; -- for 0 borders + if y_count = v_screen_end then + vblank_s <= '1'; + vactive_s <= '0'; -- for 0 borders + y_count <= 0; + else + y_s <= y_s + 1; + if y_count = v_sync_start then + vsync_s <= V_SYNC_POL; + elsif y_count = v_back_porch_start then + vsync_s <= not V_SYNC_POL; + elsif y_count = v_video_start then + vblank_s <= '0'; -- for 0 borders + vactive_s <= '1'; + y_s <= (others => '0'); + -- check the borders last in case they're 0 + elsif y_count = v_top_border_start then + vblank_s <= '0'; + elsif y_count = v_bottom_border_start then + vactive_s <= '0'; + end if; + y_count <= y_count + 1; + end if; + x_count <= 0; + else + x_s <= x_s + 1; + if x_count = h_sync_start then + hsync_s <= H_SYNC_POL; + elsif x_count = h_back_porch_start then + hsync_s <= not H_SYNC_POL; + elsif x_count = h_video_start then + hblank_s <= '0'; -- for 0 borders + hactive_s <= '1'; + x_s <= (others => '0'); + -- check the borders last in case they're 0 + elsif x_count = h_left_border_start then + hblank_s <= '0'; + elsif x_count = h_right_border_start then + hactive_s <= '0'; + end if; + x_count <= x_count + 1; + end if; + end if; -- rising_edge(clk) and clk_ena = '1' + end process timer_proc; + + -- pass-through for tile/bitmap & sprite controllers + video_ctl_o.clk <= clk; + video_ctl_o.clk_ena <= clk_ena; + + -- for video DACs and TFT output + video_o.clk <= clk; + + BLK_VIDEO_O : block + + constant PIPELINE_DELAY : natural := DELAY+1; + + -- won't synthesize correctly under ISE if these are variables + signal hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + signal vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + + begin + + video_o_proc: process (extended_reset, clk, clk_ena) + variable hsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + variable vsync_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + --variable hactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + --variable vactive_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + variable hblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + variable vblank_v_r : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0'); + alias hsync_v : std_logic is hsync_v_r(hsync_v_r'left); + alias vsync_v : std_logic is vsync_v_r(vsync_v_r'left); + alias hactive_v : std_logic is hactive_v_r(hactive_v_r'left); + alias vactive_v : std_logic is vactive_v_r(vactive_v_r'left); + alias hblank_v : std_logic is hblank_v_r(hblank_v_r'left); + alias vblank_v : std_logic is vblank_v_r(vblank_v_r'left); + variable stb_cnt_v : unsigned(3 downto 0); -- up to 16x scaling + begin + if extended_reset = '1' then + hsync_v_r := (others => not H_SYNC_POL); + vsync_v_r := (others => not V_SYNC_POL); + hactive_v_r <= (others => '0'); + vactive_v_r <= (others => '0'); + hblank_v_r := (others => '0'); + vblank_v_r := (others => '0'); + stb_cnt_v := (others => '1'); + elsif rising_edge(clk) and clk_ena = '1' then + + -- register control signals and handle scaling + video_ctl_o.hblank <= not hactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers + video_ctl_o.vblank <= not vactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers + -- handle scaling + video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY; + if hactive_s = '1' and vactive_s = '1' then + stb_cnt_v := stb_cnt_v + 2; + elsif hblank_s = '0' and vblank_s = '0' then + stb_cnt_v := (others => '1'); + end if; + video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY; + video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY; + + -- register video outputs + if hactive_v = '1' and vactive_v = '1' then + -- active video + if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or + x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then + video_o.rgb <= RGB_BLACK after SIM_DELAY; + else + video_o.rgb <= rgb_i after SIM_DELAY; + end if; + elsif hblank_v = '0' and vblank_v = '0' then + -- border + video_o.rgb <= border_rgb_r after SIM_DELAY; + else + video_o.rgb.r <= (others => '0') after SIM_DELAY; + video_o.rgb.g <= (others => '0') after SIM_DELAY; + video_o.rgb.b <= (others => '0') after SIM_DELAY; + end if; + video_o.hsync <= hsync_v after SIM_DELAY; + video_o.vsync <= vsync_v after SIM_DELAY; + video_o.hblank <= hblank_v after SIM_DELAY; + video_o.vblank <= vblank_v after SIM_DELAY; + -- pipelined signals + hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s; + vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s; + hactive_v_r <= hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s; + vactive_v_r <= vactive_v_r(vactive_v_r'left-1 downto 0) & vactive_s; + hblank_v_r := hblank_v_r(hblank_v_r'left-1 downto 0) & hblank_s; + vblank_v_r := vblank_v_r(vblank_v_r'left-1 downto 0) & vblank_s; + end if; + end process video_o_proc; + + end block BLK_VIDEO_O; + +end SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg.vhd new file mode 100644 index 00000000..183bfe23 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg.vhd @@ -0,0 +1,229 @@ +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.numeric_std.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +package video_controller_pkg is + + type PACEVideoController_t is + ( + PACE_VIDEO_NONE, -- PACE video controller not used + PACE_VIDEO_VGA_240x320_60Hz, -- P3M video + PACE_VIDEO_VGA_320x480_60Hz, -- for 320x200 (12.588MHz) + PACE_VIDEO_VGA_640x480_60Hz, -- generic VGA (25.175MHz) + PACE_VIDEO_VGA_800x600_60Hz, -- generic VGA (40MHz) + PACE_VIDEO_VGA_1024x768_60Hz, -- XVGA (65MHz) + PACE_VIDEO_VGA_1366x768_60Hz, -- (NAVICO ROCKY) (72MHz) + PACE_VIDEO_VGA_1280x800_60Hz, -- Sentinel Mode 36 + PACE_VIDEO_VGA_1280x1024_60Hz, -- SXGA (108MHz) + PACE_VIDEO_VGA_1680x1050_60Hz, -- WSXGA+ (147MHz) + PACE_VIDEO_ARCADE_STD_336x240_60Hz, -- arcade std resolution (7.16MHz) + PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64, -- arcade std resolution (28.64MHz) + PACE_VIDEO_CVBS_720x288p_50Hz, -- generic composite + PACE_VIDEO_LCM_320x240_60Hz -- DE2 LCD + ); + + type PACEVideoDisplay_t is + ( + PACE_DISPLAY_NONE, + PACE_DISPLAY_VGA, + PACE_DISPLAY_CVBS, + PACE_DISPLAY_TFT + ); + + type RGB_t is record + r : std_logic_vector(9 downto 0); + g : std_logic_vector(9 downto 0); + b : std_logic_vector(9 downto 0); + end record; + + type RGB_a is array (natural range <>) of RGB_t; + + function NULL_RGB return RGB_t; + + constant RGB_BLACK : RGB_t := ((others=>'0'),(others=>'0'),(others=>'0')); + constant RGB_RED : RGB_t := ((others=>'1'),(others=>'0'),(others=>'0')); + constant RGB_GREEN : RGB_t := ((others=>'0'),(others=>'1'),(others=>'0')); + constant RGB_YELLOW : RGB_t := ((others=>'1'),(others=>'1'),(others=>'0')); + constant RGB_BLUE : RGB_t := ((others=>'0'),(others=>'0'),(others=>'1')); + constant RGB_MAGENTA : RGB_t := ((others=>'1'),(others=>'0'),(others=>'1')); + constant RGB_CYAN : RGB_t := ((others=>'0'),(others=>'1'),(others=>'1')); + constant RGB_WHITE : RGB_t := ((others=>'1'),(others=>'1'),(others=>'1')); + + type VIDEO_REG_t is record + h_scale : std_logic_vector(2 downto 0); + v_scale : std_logic_vector(2 downto 0); + end record; + + type from_VIDEO_t is record + clk : std_logic; + clk_ena : std_logic; + reset : std_logic; + end record; + + type to_VIDEO_t is record + clk : std_logic; + rgb : rgb_t; + hsync : std_logic; + vsync : std_logic; + hblank : std_logic; + vblank : std_logic; + de : std_logic; + end record; + + type from_VIDEO_CTL_t is record + clk : std_logic; + clk_ena : std_logic; + stb : std_logic; + hblank : std_logic; + vblank : std_logic; + x : std_logic_vector(10 downto 0); + y : std_logic_vector(10 downto 0); + end record; + + subtype BITMAP_D_t is std_logic_vector(23 downto 0); + subtype BITMAP_A_t is std_logic_vector(15 downto 0); + + type to_BITMAP_CTL_t is record + d : BITMAP_D_t; + end record; + + type to_BITMAP_CTL_a is array (natural range <>) of to_BITMAP_CTL_t; + + function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t; + + type from_BITMAP_CTL_t is record + a : BITMAP_A_t; + rgb : RGB_t; + set : std_logic; + end record; + + type from_BITMAP_CTL_a is array (natural range <>) of from_BITMAP_CTL_t; + + subtype TILEMAP_D_t is std_logic_vector(15 downto 0); + subtype TILEMAP_A_t is std_logic_vector(15 downto 0); + subtype TILE_A_t is std_logic_vector(16 downto 0); + subtype TILE_D_t is std_logic_vector(23 downto 0); + subtype ATTR_A_t is std_logic_vector(15 downto 0); + subtype ATTR_D_t is std_logic_vector(15 downto 0); + + type to_TILEMAP_CTL_t is record + map_d : TILEMAP_D_t; + tile_d : TILE_D_t; + attr_d : ATTR_D_t; + end record; + + type to_TILEMAP_CTL_a is array (natural range <>) of to_TILEMAP_CTL_t; + + function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t; + + type from_TILEMAP_CTL_t is record + map_a : TILEMAP_A_t; + tile_a : TILE_A_t; + attr_a : ATTR_A_t; + rgb : RGB_t; + set : std_logic; + end record; + + type from_TILEMAP_CTL_a is array (natural range <>) of from_TILEMAP_CTL_t; + + subtype PAL_ENTRY_t is std_logic_vector(15 downto 0); + type PAL_A_t is array (natural range <>) of PAL_ENTRY_t; + + subtype BYTE_t is std_logic_vector(7 downto 0); + type BYTE_A_t is array (natural range <>) of BYTE_t; + + subtype WORD_t is std_logic_vector(15 downto 0); + type WORD_A_t is array (natural range <>) of WORD_t; + + type to_GRAPHICS_t is record + pal : PAL_A_t(0 to 15); + -- for various uses + bit8 : BYTE_A_t(0 to 7); + bit16 : WORD_A_t(0 to 3); + -- 'native' graphics stream + hsync : std_logic; + vsync : std_logic; + rgb : RGB_t; + end record; + + function NULL_TO_GRAPHICS return to_GRAPHICS_t; + + type from_GRAPHICS_t is record + y : std_logic_vector(10 downto 0); + hblank : std_logic; + vblank : std_logic; + end record; + + component pace_video_controller is + generic + ( + CONFIG : PACEVideoController_t := PACE_VIDEO_NONE; + DELAY : integer := 1; + H_SIZE : integer; + V_SIZE : integer; + --H_SCALE : integer; + --V_SCALE : integer; + BORDER_RGB : RGB_t := RGB_BLACK + ); + port + ( + -- clocking etc + video_i : in from_VIDEO_t; + + -- register interface + reg_i : in VIDEO_REG_t; + + -- video input data + rgb_i : in RGB_t; + + -- control signals (out) + video_ctl_o : from_VIDEO_CTL_t; + + -- Outputs to video + video_o : out to_VIDEO_t + ); + end component pace_video_controller; + + component tilemapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- tilemap controller signals + ctl_i : in to_TILEMAP_CTL_t; + ctl_o : out from_TILEMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); + end component tilemapCtl; + + component bitmapCtl is + generic + ( + DELAY : integer + ); + port + ( + reset : in std_logic; + + -- video control signals + video_ctl : in from_VIDEO_CTL_t; + + -- bitmap controller signals + ctl_i : in to_BITMAP_CTL_t; + ctl_o : out from_BITMAP_CTL_t; + + graphics_i : in to_GRAPHICS_t + ); + end component bitmapCtl; + +end package video_controller_pkg; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg_body.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg_body.vhd new file mode 100644 index 00000000..996e5867 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg_body.vhd @@ -0,0 +1,29 @@ +library work; +--use work.pace_pkg.all; + +package body video_controller_pkg is + + function NULL_RGB return RGB_t is + begin + return (others => (others => '0')); + end NULL_RGB; + + function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t is + begin + return (others => (others => '0')); + end NULL_TO_BITMAP_CTL; + + function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t is + begin + return ((others => '0'), (others => '0'), (others => '0')); + end NULL_TO_TILEMAP_CTL; + + function NULL_TO_GRAPHICS return to_GRAPHICS_t is + begin + return ((others => (others => '0')), + (others => (others => '0')), + (others => (others => '0')), + '0', '0', NULL_RGB); + end NULL_TO_GRAPHICS; + +end package body video_controller_pkg; diff --git a/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_mixer.vhd b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_mixer.vhd new file mode 100644 index 00000000..fb4b4aa4 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080_MiST/src/video_mixer.vhd @@ -0,0 +1,66 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.pace_pkg.all; +use work.video_controller_pkg.all; +use work.sprite_pkg.all; +use work.platform_pkg.all; + +entity pace_video_mixer is + port + ( + --bitmap_rgb : in RGB_t; + --bitmap_set : in std_logic; + bitmap_ctl_o : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS); + tilemap_ctl_o : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS); + sprite_rgb : in RGB_t; + sprite_set : in std_logic; + sprite_pri : in std_logic; + + video_ctl_i : in from_VIDEO_CTL_t; + graphics_i : in to_GRAPHICS_t; + rgb_o : out RGB_t + ); +end entity pace_video_mixer; + +architecture SYN of pace_video_mixer is + signal bg_rgb : RGB_t; +begin + + GEN_BITMAPS : + if PACE_VIDEO_NUM_BITMAPS = 1 generate + bg_rgb <= bitmap_ctl_o(1).rgb; + elsif PACE_VIDEO_NUM_BITMAPS = 2 generate + bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else + bitmap_ctl_o(2).rgb; + elsif PACE_VIDEO_NUM_BITMAPS = 3 generate + bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else + bitmap_ctl_o(2).rgb when bitmap_ctl_o(2).set = '1' else + bitmap_ctl_o(3).rgb when bitmap_ctl_o(3).set = '1' else + (others => (others => '0')); + else generate + bg_rgb <= (others => (others => '0')); + end generate GEN_BITMAPS; + + GEN_TILEMAPS : + if PACE_VIDEO_NUM_TILEMAPS = 1 generate + rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else + tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else + sprite_rgb when sprite_set = '1' else + bg_rgb; + elsif PACE_VIDEO_NUM_TILEMAPS = 2 generate + rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else + tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else + tilemap_ctl_o(2).rgb when tilemap_ctl_o(2).set = '1' else + sprite_rgb when sprite_set = '1' else + bg_rgb; + else generate + rgb_o <= sprite_rgb when sprite_set = '1' and sprite_pri = '1' else + sprite_rgb when sprite_set = '1' else + bg_rgb; + end generate GEN_TILEMAPS; + +end architecture SYN; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qpf b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qpf new file mode 100644 index 00000000..c69f402a --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 21:27:39 November 20, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "21:27:39 November 20, 2017" + +# Revisions + +PROJECT_REVISION = "Invaders" diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf new file mode 100644 index 00000000..0f690d41 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf @@ -0,0 +1,134 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 21:27:39 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Invaders_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY Invaders_mist +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd +set_global_assignment -name VHDL_FILE rtl/invaders.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_rom_h.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_rom_e.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_rom_f.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_rom_g.vhd +set_global_assignment -name QIP_FILE rtl/WRAM.qip +set_global_assignment -name VHDL_FILE rtl/mw8080.vhd +set_global_assignment -name VHDL_FILE rtl/T8080se.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T80.vhd +set_global_assignment -name VHDL_FILE rtl/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T80_Reg.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders_mist.sv +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VHDL_FILE rtl/Invaders_memory.vhd +set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/README.txt b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/README.txt new file mode 100644 index 00000000..a610b39a --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Space Invaders port to MiST by Gehstock +-- 09 Januar 2018 +-- +--------------------------------------------------------------------------------- +-- +-- Midway 8080 Hardware +-- Audio based on work by Paul Walsh. +-- Audio and scan converter by MikeJ. +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- F1 : Start +-- SPACE : Fire +-- RIGHT/LEFT : Movement +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +Work in Progress + diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf new file mode 100644 index 00000000..a5835782 Binary files /dev/null and b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/Release/Invaders.rbf differ diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/clean.bat b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_memory.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_memory.vhd new file mode 100644 index 00000000..665b8e96 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_memory.vhd @@ -0,0 +1,81 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity invaders_memory is + port( + CLK : in std_logic;--10mhz + RWE_n : in std_logic; + AD : in std_logic_vector(15 downto 0); + RAB : in std_logic_vector(12 downto 0); + RDB : out std_logic_vector(7 downto 0); + RWD : in std_logic_vector(7 downto 0); + IB : out std_logic_vector(7 downto 0) + ); +end invaders_memory; + +architecture rtl of invaders_memory is + signal rom_data_0 : std_logic_vector(7 downto 0); + signal rom_data_1 : std_logic_vector(7 downto 0); + signal rom_data_2 : std_logic_vector(7 downto 0); + signal rom_data_3 : std_logic_vector(7 downto 0); + +begin + u_rom_h : entity work.INVADERS_ROM_H + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_0 + ); + -- + u_rom_g : entity work.INVADERS_ROM_G + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_1 + ); + -- + u_rom_f : entity work.INVADERS_ROM_F + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_2 + ); + -- + u_rom_e : entity work.INVADERS_ROM_E + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_3 + ); + -- + p_rom_data : process(AD, rom_data_0, rom_data_1, rom_data_2, rom_data_3) + begin + IB <= (others => '0'); + case AD(12 downto 11) is + when "00" => IB <= rom_data_0; + when "01" => IB <= rom_data_1; + when "10" => IB <= rom_data_2; + when "11" => IB <= rom_data_3; + when others => null; + end case; + end process; + + + rams : for i in 0 to 3 generate + u_ram : entity work.WRAM + port map ( + q => RDB((i*2)+1 downto (i*2)), + address => RAB, + clock => Clk, + data => RWD((i*2)+1 downto (i*2)), + rden => '1', + wren => not RWE_n + ); + end generate; + +end; \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv new file mode 100644 index 00000000..30306b63 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv @@ -0,0 +1,207 @@ +module Invaders_mist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Space Inv.;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys, clk_mist; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .c1(clk_mist) +); + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid; +wire hs, vs; +wire r,g,b; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_mist), + .ce_pix(clk_sys), + .ce_pix_actual(clk_sys), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r,r}), + .G({g,g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_mist ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_mist), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +//wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +//wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +wire [12:0]RAB; +wire [15:0]AD; +wire [7:0]RDB; +wire [7:0]RWD; +wire [7:0]IB; +wire [5:0]SoundCtrl3; +wire [5:0]SoundCtrl5; +wire Rst_n_s; +wire RWE_n; +wire Video; +wire HSync; +wire VSync; + +invaderst invaderst( + .Rst_n(~(status[0] | status[6] | buttons[1])), + .Clk(clk_sys), + .ENA(), + .Coin(m_coin), + .Sel1Player(~m_start1), + .Sel2Player(~m_start2), + .Fire(~m_fire), + .MoveLeft(~m_left), + .MoveRight(~m_right), + .DIP(8'b0), + .RDB(RDB), + .IB(IB), + .RWD(RWD), + .RAB(RAB), + .AD(AD), + .SoundCtrl3(SoundCtrl3), + .SoundCtrl5(SoundCtrl5), + .Rst_n_s(Rst_n_s), + .RWE_n(RWE_n), + .Video(Video), + .HSync(HSync), + .VSync(VSync) + ); + +Invaders_memory Invaders_memory ( + .CLK(clk_sys), + .RWE_n(RWE_n), + .AD(AD), + .RAB(RAB), + .RDB(RDB), + .RWD(RWD), + .IB(IB) + ); + +invaders_audio invaders_audio ( + .Clk(clk_sys), + .S1(SoundCtrl3), + .S2(SoundCtrl5), + .Aud(audio) + ); + +invaders_video invaders_video ( + .Video(Video), + .CLK(clk_sys), + .Rst_n_s(Rst_n_s), + .HSync(HSync), + .VSync(VSync), + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs) + ); + +dac dac +( + .clk_i(clk_mist), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T8080se.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T8080se.vhd new file mode 100644 index 00000000..b18b47a4 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T8080se.vhd @@ -0,0 +1,194 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- 8080 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original 8080 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- STACK status output not supported +-- +-- File history : +-- +-- 0237 : First version +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T8080se is + generic( + Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + ); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T8080se; + +architecture rtl of T8080se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal INT_n : std_logic; + signal HALT_n : std_logic; + signal BUSRQ_n : std_logic; + signal BUSAK_n : std_logic; + signal DO_i : std_logic_vector(7 downto 0); + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + signal One : std_logic; + +begin + + INT_n <= not INT; + BUSRQ_n <= HOLD; + HLDA <= not BUSAK_n; + SYNC <= '1' when TState = "001" else '0'; + VAIT <= '1' when TState = "010" else '0'; + One <= '1'; + + DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA + DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n + DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!! + DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA + DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT + DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1 + DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP + DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR + + u0 : T80 + generic map( + Mode => Mode, + IOWait => 0) + port map( + CEN => CLKEN, + M1_n => open, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => open, + HALT_n => HALT_n, + WAIT_n => READY, + INT_n => INT_n, + NMI_n => One, + RESET_n => RESET_n, + BUSRQ_n => One, + BUSAK_n => BUSAK_n, + CLK_n => CLK, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO_i, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n, + IntE => INTE); + + process (RESET_n, CLK) + begin + if RESET_n = '0' then + DBIN <= '0'; + WR_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK'event and CLK = '1' then + if CLKEN = '1' then + DBIN <= '0'; + WR_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and READY = '0') then + DBIN <= IntCycle_n; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then + DBIN <= '1'; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then + WR_n <= '0'; + end if; + end if; + end if; + if TState = "010" and READY = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_ALU.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_ALU.vhd new file mode 100644 index 00000000..e09def1e --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_ALU.vhd @@ -0,0 +1,361 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_MCode.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_Pack.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_Reg.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_Reg.vhd new file mode 100644 index 00000000..1c0f2638 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_RegX.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_RegX.vhd new file mode 100644 index 00000000..ebeee095 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/T80_RegX.vhd @@ -0,0 +1,176 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers for Xilinx Select RAM +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Removed UNISIM library and added componet declaration +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + component RAM16X1D + port( + DPO : out std_ulogic; + SPO : out std_ulogic; + A0 : in std_ulogic; + A1 : in std_ulogic; + A2 : in std_ulogic; + A3 : in std_ulogic; + D : in std_ulogic; + DPRA0 : in std_ulogic; + DPRA1 : in std_ulogic; + DPRA2 : in std_ulogic; + DPRA3 : in std_ulogic; + WCLK : in std_ulogic; + WE : in std_ulogic); + end component; + + signal ENH : std_logic; + signal ENL : std_logic; + +begin + + ENH <= CEN and WEH; + ENL <= CEN and WEL; + + bG1: for I in 0 to 7 generate + begin + Reg1H : RAM16X1D + port map( + DPO => DOBH(i), + SPO => DOAH(i), + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIH(i), + DPRA0 => AddrB(0), + DPRA1 => AddrB(1), + DPRA2 => AddrB(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENH); + Reg1L : RAM16X1D + port map( + DPO => DOBL(i), + SPO => DOAL(i), + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIL(i), + DPRA0 => AddrB(0), + DPRA1 => AddrB(1), + DPRA2 => AddrB(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENL); + Reg2H : RAM16X1D + port map( + DPO => DOCH(i), + SPO => open, + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIH(i), + DPRA0 => AddrC(0), + DPRA1 => AddrC(1), + DPRA2 => AddrC(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENH); + Reg2L : RAM16X1D + port map( + DPO => DOCL(i), + SPO => open, + A0 => AddrA(0), + A1 => AddrA(1), + A2 => AddrA(2), + A3 => '0', + D => DIL(i), + DPRA0 => AddrC(0), + DPRA1 => AddrC(1), + DPRA2 => AddrC(2), + DPRA3 => '0', + WCLK => Clk, + WE => ENL); + end generate; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/WRAM.qip b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/WRAM.qip new file mode 100644 index 00000000..ba1d4355 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/WRAM.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "WRAM.vhd"] diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/WRAM.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/WRAM.vhd new file mode 100644 index 00000000..cce6b51b --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/WRAM.vhd @@ -0,0 +1,160 @@ +-- megafunction wizard: %RAM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: WRAM.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY WRAM IS + PORT + ( + address : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + rden : IN STD_LOGIC := '1'; + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END WRAM; + + +ARCHITECTURE SYN OF wram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + +BEGIN + q <= sub_wire0(1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 8192, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "CLOCK0", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => 13, + width_a => 2, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + data_a => data, + wren_a => wren, + rden_a => rden, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrData NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegData NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +-- Retrieval info: PRIVATE: WidthData NUMERIC "2" +-- Retrieval info: PRIVATE: rden NUMERIC "1" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "2" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]" +-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]" +-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 2 0 data 0 0 2 0 +-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 2 0 @q_a 0 0 2 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL WRAM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WRAM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WRAM.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WRAM.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL WRAM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.tcl b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v new file mode 100644 index 00000000..4d429cb5 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171118" +`define BUILD_TIME "195221" diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/dac.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/hq2x.sv b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd new file mode 100644 index 00000000..2bf98881 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd @@ -0,0 +1,271 @@ +-- Space Invaders core logic +-- 9.984MHz clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Cleaned up reset logic +-- +-- 0300 : MikeJ tidyup for audio release + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity invaderst is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + Coin : in std_logic; + Sel1Player : in std_logic; + Sel2Player : in std_logic; + Fire : in std_logic; + MoveLeft : in std_logic; + MoveRight : in std_logic; + DIP : in std_logic_vector(8 downto 1); + RDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + RWD : out std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + AD : out std_logic_vector(15 downto 0); + SoundCtrl3 : out std_logic_vector(5 downto 0); + SoundCtrl5 : out std_logic_vector(5 downto 0); + Rst_n_s : out std_logic; + RWE_n : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic + ); +end invaderst; + +architecture rtl of invaderst is + + component mw8080 + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic); + end component; + + signal GDB0 : std_logic_vector(7 downto 0); + signal GDB1 : std_logic_vector(7 downto 0); + signal GDB2 : std_logic_vector(7 downto 0); + signal S : std_logic_vector(7 downto 0); + signal GDB : std_logic_vector(7 downto 0); + signal DB : std_logic_vector(7 downto 0); + signal Sounds : std_logic_vector(7 downto 0); + signal AD_i : std_logic_vector(15 downto 0); + signal PortWr : std_logic_vector(6 downto 2); + signal EA : std_logic_vector(2 downto 0); + signal D5 : std_logic_vector(15 downto 0); + signal WD_Cnt : unsigned(7 downto 0); + signal Sample : std_logic; + signal Rst_n_s_i : std_logic; +begin + + Rst_n_s <= Rst_n_s_i; + RWD <= DB; + AD <= AD_i; + + process (Rst_n, Clk) + variable Rst_n_r : std_logic; + begin + if Rst_n = '0' then + Rst_n_r := '0'; + Rst_n_s_i <= '0'; + elsif Clk'event and Clk = '1' then + Rst_n_s_i <= Rst_n_r; + if WD_Cnt = 255 then + Rst_n_s_i <= '0'; + end if; + Rst_n_r := '1'; + end if; + end process; + + process (Rst_n_s_i, Clk) + variable Old_S0 : std_logic; + begin + if Rst_n_s_i = '0' then + WD_Cnt <= (others => '0'); + Old_S0 := '1'; + elsif Clk'event and Clk = '1' then + if Sounds(0) = '1' and Old_S0 = '0' then + WD_Cnt <= WD_Cnt + 1; + end if; + if PortWr(6) = '1' then + WD_Cnt <= (others => '0'); + end if; + Old_S0 := Sounds(0); + end if; + end process; + + u_mw8080: mw8080 + port map( + Rst_n => Rst_n_s_i, + Clk => Clk, + ENA => ENA, + RWE_n => RWE_n, + RDB => RDB, + IB => IB, + RAB => RAB, + Sounds => Sounds, + Ready => open, + GDB => GDB, + DB => DB, + AD => AD_i, + Status => open, + Systb => open, + Int => open, + Hold_n => '1', + IntE => open, + DBin_n => open, + Vait => open, + HldA => open, + Sample => Sample, + Wr => open, + Video => Video, + HSync => HSync, + VSync => VSync); + + with AD_i(9 downto 8) select + GDB <= GDB0 when "00", + GDB1 when "01", + GDB2 when "10", + S when others; + + GDB0(0) <= DIP(8); -- Unused ? + GDB0(1) <= DIP(7); + GDB0(2) <= DIP(6); -- Unused ? + GDB0(3) <= '1'; -- Unused ? + GDB0(4) <= not Fire; + GDB0(5) <= not MoveLeft; + GDB0(6) <= not MoveRight; + GDB0(7) <= DIP(5); -- Unused ? + + GDB1(0) <= not Coin;-- Active High ! + GDB1(1) <= not Sel2Player; + GDB1(2) <= not Sel1Player; + GDB1(3) <= '1'; -- Unused ? + GDB1(4) <= not Fire; + GDB1(5) <= not MoveLeft; + GDB1(6) <= not MoveRight; + GDB1(7) <= '1'; -- Unused ? + + GDB2(0) <= DIP(4); -- LSB Lives 3-6 + GDB2(1) <= DIP(3); -- MSB Lives 3-6 + GDB2(2) <= '0'; -- Tilt ? + GDB2(3) <= DIP(2); -- Bonus life at 1000 or 1500 + GDB2(4) <= not Fire; + GDB2(5) <= not MoveLeft; + GDB2(6) <= not MoveRight; + GDB2(7) <= DIP(1); -- Coin info + + PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0'; + PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0'; + PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0'; + PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0'; + PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0'; + + process (Rst_n_s_i, Clk) + variable OldSample : std_logic; + begin + if Rst_n_s_i = '0' then + D5 <= (others => '0'); + EA <= (others => '0'); + SoundCtrl3 <= (others => '0'); + SoundCtrl5 <= (others => '0'); + OldSample := '0'; + elsif Clk'event and Clk = '1' then + if PortWr(2) = '1' then + EA <= DB(2 downto 0); + end if; + if PortWr(3) = '1' then + SoundCtrl3 <= DB(5 downto 0); + end if; + if PortWr(4) = '1' and OldSample = '0' then + D5(15 downto 8) <= DB; + D5(7 downto 0) <= D5(15 downto 8); + end if; + if PortWr(5) = '1' then + SoundCtrl5 <= DB(5 downto 0); + end if; + OldSample := Sample; + end if; + end process; + + with EA select + S <= D5(15 downto 8) when "000", + D5(14 downto 7) when "001", + D5(13 downto 6) when "010", + D5(12 downto 5) when "011", + D5(11 downto 4) when "100", + D5(10 downto 3) when "101", + D5( 9 downto 2) when "110", + D5( 8 downto 1) when others; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_audio.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_audio.vhd new file mode 100644 index 00000000..f16cf379 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_audio.vhd @@ -0,0 +1,496 @@ + +-- Version : 0300 +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- minor tidy up by MikeJ +------------------------------------------------------------------------------- +-- Company: +-- Engineer: PaulWalsh +-- +-- Create Date: 08:45:29 11/04/05 +-- Design Name: +-- Module Name: Invaders Audio +-- Project Name: Space Invaders +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity invaders_audio is + Port ( + Clk : in std_logic; + S1 : in std_logic_vector(5 downto 0); + S2 : in std_logic_vector(5 downto 0); + Aud : out std_logic_vector(7 downto 0) + ); +end; + --* Port 3: (S1) + --* bit 0=UFO (repeats) + --* bit 1=Shot + --* bit 2=Base hit + --* bit 3=Invader hit + --* bit 4=Bonus base + --* + --* Port 5: (S2) + --* bit 0=Fleet movement 1 + --* bit 1=Fleet movement 2 + --* bit 2=Fleet movement 3 + --* bit 3=Fleet movement 4 + --* bit 4=UFO 2 + +architecture Behavioral of invaders_audio is + + signal ClkDiv : unsigned(10 downto 0) := (others => '0'); + signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0'); + signal Clk7680_ena : std_logic; + signal Clk480_ena : std_logic; + signal Clk240_ena : std_logic; + signal Clk60_ena : std_logic; + + signal s1_t1 : std_logic_vector(5 downto 0); + signal s2_t1 : std_logic_vector(5 downto 0); + signal tempsum : std_logic_vector(7 downto 0); + + signal vco_cnt : std_logic_vector(3 downto 0); + + signal TriDir1 : std_logic; + signal Fnum : std_logic_vector(3 downto 0); + signal comp : std_logic; + + signal SS : std_logic; + + signal TrigSH : std_logic; + signal SHCnt : std_logic_vector(8 downto 0); + signal SH : std_logic_vector(7 downto 0); + signal SauHit : std_logic_vector(8 downto 0); + signal SHitTri : std_logic_vector(5 downto 0); + + signal TrigIH : std_logic; + signal IHDir : std_logic; + signal IHDir1 : std_logic; + signal IHCnt : std_logic_vector(8 downto 0); + signal IH : std_logic_vector(7 downto 0); + signal InHit : std_logic_vector(8 downto 0); + signal IHitTri : std_logic_vector(5 downto 0); + + signal TrigEx : std_logic; + signal Excnt : std_logic_vector(9 downto 0); + signal ExShift : std_logic_vector(15 downto 0); + signal Ex : std_logic_vector(2 downto 0); + signal Explo : std_logic; + + signal TrigMis : std_logic; + signal MisShift : std_logic_vector(15 downto 0); + signal MisCnt : std_logic_vector(8 downto 0); + signal miscnt1 : unsigned(7 downto 0); + signal Mis : std_logic_vector(2 downto 0); + signal Missile : std_logic; + + signal EnBG : std_logic; + signal BGFnum : std_logic_vector(7 downto 0); + signal BGCnum : std_logic_vector(7 downto 0); + signal bg_cnt : unsigned(7 downto 0); + signal BG : std_logic; + +begin + + -- do a crude addition of all sound samples + p_audio_mix : process + variable IHVol : std_logic_vector(6 downto 0); + variable SHVol : std_logic_vector(6 downto 0); + begin + wait until rising_edge(Clk); + + IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0); + SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0); + + tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol); + + Aud(7) <= tempsum (7); + Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG; + Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS; + Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo); + Aud(3 downto 0) <= tempsum (3 downto 0); + + end process; + + p_clkdiv : process + begin + wait until rising_edge(Clk); + Clk7680_ena <= '0'; + if ClkDiv = 1277 then + Clk7680_ena <= '1'; + ClkDiv <= (others => '0'); + else + ClkDiv <= ClkDiv + 1; + end if; + end process; + + p_clkdiv2 : process + begin + wait until rising_edge(Clk); + Clk480_ena <= '0'; + Clk240_ena <= '0'; + Clk60_ena <= '0'; + + if (Clk7680_ena = '1') then + ClkDiv2 <= ClkDiv2 + 1; + + if (ClkDiv2(3 downto 0) = "0000") then + Clk480_ena <= '1'; + end if; + + if (ClkDiv2(4 downto 0) = "00000") then + Clk240_ena <= '1'; + end if; + + if (ClkDiv2(7 downto 0) = "00000000") then + Clk60_ena <= '1'; + end if; + + end if; + end process; + + p_delay : process + begin + wait until rising_edge(Clk); + s1_t1 <= S1; + s2_t1 <= S2; + end process; +--*************************Saucer Sound*************************************** + +-- Implement a VCOscilator: frequency is set using counter end point(Fnum) + p_saucer_vco : process + variable term : std_logic_vector(3 downto 0); + begin + wait until rising_edge(Clk); + term := 8 + Fnum; + if (S1(0) = '1') and (Clk7680_ena = '1') then + if vco_cnt = term then + + vco_cnt <= (others => '0'); + SS <= not SS; + else + vco_cnt <= vco_cnt + 1; + end if; + end if; + end process; + +-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator + -- this is 6Hz ?? 0123454321 + p_saucer_lfo : process + begin + wait until rising_edge(Clk); + if (Clk60_ena = '1') then + if Fnum = 4 then -- 5 -1 + Comp <= '1'; + elsif Fnum = 1 then -- 0 +1 + Comp <= '0'; + end if; + + if comp = '1' then + Fnum <= Fnum - 1 ; + else + Fnum <= Fnum + 1 ; + end if; + end if; + end process; + +--**********************SAUCER HIT Sound************************** + +-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO + p_saucer_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if SHitTri = 48 then + SHitTri <= "000000"; + else + SHitTri <= SHitTri+1; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx + p_saucer_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if TriDir1 = '1' then + if (SauHit +58 - SHitTri) < 190 + 256 then + SauHit <= SauHit +58 - SHitTri; + else + SauHit <= "110111110"; + TriDir1 <= '0'; + end if; + else + if (SauHit -58 + SHitTri) > 256 then + SauHit <= SauHit -58 + SHitTri; + else + SauHit <= "100000000"; + TriDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Saucer Hit Sound + p_saucer_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigSH = '1') then + SHCnt <= "100000000"; + SH <= "11111111"; + elsif (SHCnt(8) = '1') then + SHCnt <= SHCnt + "1"; + if SHCnt(7 downto 0) = x"60" then -- 96 + SH <= "01111111"; + elsif SHCnt(7 downto 0) = x"90" then -- 144 + SH <= "00111111"; + elsif SHCnt(7 downto 0) = x"C0" then -- 192 + SH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Saucer Hit Sound + p_saucer_hit : process + begin + wait until rising_edge(Clk); + if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge + TrigSH <= '1'; + elsif (Clk480_ena = '1') then + TrigSH <= '0'; + end if; + end process; + +--***********************Invader Hit Sound***************************** +-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO + p_invader_hit_lfo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if IHitTri = 48-2 then + IHDir <= '0'; + elsif IHitTri =0+2 then + IHDir <= '1'; + end if; + + if IHDir ='1' then + IHitTri <= IHitTri + 2; + else + IHitTri <= IHitTri - 2; + end if; + end if; + end process; + +-- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx + p_invader_hit_vco : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if IHDir1 = '1' then + if (InHit +10 + IHitTri) < 110 + 256 then + InHit <= InHit +10 + IHitTri; + else + InHit <= "101101110"; + IHDir1 <= '0'; + end if; + else + if (InHit -10 - IHitTri) > 256 then + InHit <= InHit -10 - IHitTri; + else + InHit <= "100000000"; + IHDir1 <= '1'; + end if; + end if; + end if; + end process; + +-- Implement the ADSR for Invader Hit Sound + p_invader_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigIH = '1') then + IHCnt <= "100000000"; + IH <= "11111111"; + elsif (IHCnt(8) = '1') then + IHCnt <= IHCnt + "1"; + if IHCnt(7 downto 0) = x"14" then -- 20 + IH <= "01111111"; + elsif IHCnt(7 downto 0) = x"1C" then -- 28 + IH <= "11111111"; + elsif IHCnt(7 downto 0) = x"30" then -- 48 + IH <= "00000000"; + end if; + end if; + end if; + end process; + + -- Implement the trigger for The Invader Hit Sound + p_invader_hit : process + begin + wait until rising_edge(Clk); + if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge + TrigIH <= '1'; + elsif (Clk480_ena = '1') then + TrigIH <= '0'; + end if; + end process; + +--***********************Explosion***************************** +-- Implement a Pseudo Random Noise Generator + p_explosion_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (ExShift = x"0000") then + ExShift <= "0000000010101001"; + else + ExShift(0) <= Exshift(14) xor ExShift(15); + ExShift(15 downto 1) <= ExShift (14 downto 0); + end if; + end if; + end process; + Explo <= ExShift(0); + + p_explosion_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigEx = '1') then + ExCnt <= "1000000000"; + Ex <= "100"; + elsif (ExCnt(9) = '1') then + ExCnt <= ExCnt + "1"; + if ExCnt(8 downto 0) = '0' & x"64" then -- 100 + Ex <= "010"; + elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200 + Ex <= "001"; + elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300 + Ex <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Explosion Sound + p_explosion_trig : process + begin + wait until rising_edge(Clk); + if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge + TrigEx <= '1'; + elsif (Clk480_ena = '1') then + TrigEx <= '0'; + end if; + end process; + +--***********************Missile***************************** +-- Implement a Pseudo Random Noise Generator + p_missile_pseudo : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if (MisShift = x"0000") then + MisShift <= "0000000010101001"; + else + MisShift(0) <= MisShift(14) xor MisShift(15); + MisShift(15 downto 1) <= MisShift (14 downto 0); + end if; + + miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0)); + if miscnt1 > 60 then + miscnt1 <= "00000000"; + Missile <= not Missile; + end if; + + end if; + end process; + +-- Implement the ADSR for The Missile Sound + p_missile_adsr : process + begin + wait until rising_edge(Clk); + if (Clk480_ena = '1') then + if (TrigMis = '1') then + MisCnt <= "100000000"; + Mis <= "100"; + elsif (MisCnt(8) = '1') then + MisCnt <= MisCnt + "1"; + if MisCnt(7 downto 0) = x"4b" then -- 75 + Mis <= "010"; + elsif MisCnt(7 downto 0) = x"70" then -- 112 + Mis <= "001"; + elsif MisCnt(7 downto 0) = x"96" then -- 150 + Mis <= "000"; + end if; + end if; + end if; + end process; + +-- Implement the trigger for The Missile Sound + p_missile_trig : process + begin + wait until rising_edge(Clk); + if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge + TrigMis <= '1'; + elsif (Clk480_ena = '1') then + TrigMis <= '0'; + end if; + end process; + +-- ******************************** Background invader moving tones ************************** + EnBG <= S2(0) or S2(1) or S2(2) or S2(3); + + with S2(3 downto 0) select + BGFnum <= x"66" when "0001", + x"74" when "0010", + x"7C" when "0100", + x"87" when "1000", + x"87" when others; + + with S2(3 downto 0) select + BGCnum <= x"33" when "0001", + x"3A" when "0010", + x"3E" when "0100", + x"43" when "1000", + x"43" when others; + +-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum) + + p_background : process + begin + wait until rising_edge(Clk); + if (Clk7680_ena = '1') then + if EnBG = '0' then + bg_cnt <= x"00"; + BG <= '0'; + else + bg_cnt <= bg_cnt + 1; + + if bg_cnt = unsigned(BGfnum) then + bg_cnt <= x"00"; + BG <= '0'; + elsif bg_cnt=unsigned(BGCnum) then + BG <='1'; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_e.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_e.vhd new file mode 100644 index 00000000..b19c4624 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_e.vhd @@ -0,0 +1,288 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity INVADERS_ROM_E is + port ( + CLK : in std_logic; + ENA : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of INVADERS_ROM_E is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"20",x"C3",x"C9",x"16",x"21",x"84",x"20",x"7E", -- 0x0000 + x"A7",x"CA",x"07",x"07",x"23",x"7E",x"A7",x"C0", -- 0x0008 + x"06",x"01",x"C3",x"FA",x"18",x"21",x"10",x"28", -- 0x0010 + x"11",x"A3",x"1C",x"0E",x"15",x"CD",x"F3",x"08", -- 0x0018 + x"3E",x"0A",x"32",x"6C",x"20",x"01",x"BE",x"1D", -- 0x0020 + x"CD",x"56",x"18",x"DA",x"37",x"18",x"CD",x"44", -- 0x0028 + x"18",x"C3",x"28",x"18",x"CD",x"B1",x"0A",x"01", -- 0x0030 + x"CF",x"1D",x"CD",x"56",x"18",x"D8",x"CD",x"4C", -- 0x0038 + x"18",x"C3",x"3A",x"18",x"C5",x"06",x"10",x"CD", -- 0x0040 + x"39",x"14",x"C1",x"C9",x"C5",x"3A",x"6C",x"20", -- 0x0048 + x"4F",x"CD",x"93",x"0A",x"C1",x"C9",x"0A",x"FE", -- 0x0050 + x"FF",x"37",x"C8",x"6F",x"03",x"0A",x"67",x"03", -- 0x0058 + x"0A",x"5F",x"03",x"0A",x"57",x"03",x"A7",x"C9", -- 0x0060 + x"21",x"C2",x"20",x"34",x"23",x"4E",x"CD",x"D9", -- 0x0068 + x"01",x"47",x"3A",x"CA",x"20",x"B8",x"CA",x"98", -- 0x0070 + x"18",x"3A",x"C2",x"20",x"E6",x"04",x"2A",x"CC", -- 0x0078 + x"20",x"C2",x"88",x"18",x"11",x"30",x"00",x"19", -- 0x0080 + x"22",x"C7",x"20",x"21",x"C5",x"20",x"CD",x"3B", -- 0x0088 + x"1A",x"EB",x"C3",x"D3",x"15",x"00",x"00",x"00", -- 0x0090 + x"3E",x"01",x"32",x"CB",x"20",x"C9",x"21",x"50", -- 0x0098 + x"20",x"11",x"C0",x"1B",x"06",x"10",x"CD",x"32", -- 0x00A0 + x"1A",x"3E",x"02",x"32",x"80",x"20",x"3E",x"FF", -- 0x00A8 + x"32",x"7E",x"20",x"3E",x"04",x"32",x"C1",x"20", -- 0x00B0 + x"3A",x"55",x"20",x"E6",x"01",x"CA",x"B8",x"18", -- 0x00B8 + x"3A",x"55",x"20",x"E6",x"01",x"C2",x"C0",x"18", -- 0x00C0 + x"21",x"11",x"33",x"3E",x"26",x"00",x"CD",x"FF", -- 0x00C8 + x"08",x"C3",x"B6",x"0A",x"31",x"00",x"24",x"06", -- 0x00D0 + x"00",x"CD",x"E6",x"01",x"CD",x"56",x"19",x"3E", -- 0x00D8 + x"08",x"32",x"CF",x"20",x"C3",x"EA",x"0A",x"3A", -- 0x00E0 + x"67",x"20",x"21",x"E7",x"20",x"0F",x"D0",x"23", -- 0x00E8 + x"C9",x"06",x"02",x"3A",x"82",x"20",x"3D",x"C0", -- 0x00F0 + x"04",x"C9",x"3A",x"94",x"20",x"B0",x"32",x"94", -- 0x00F8 + x"20",x"D3",x"03",x"C9",x"21",x"00",x"22",x"C3", -- 0x0100 + x"C3",x"01",x"CD",x"D8",x"14",x"C3",x"97",x"15", -- 0x0108 + x"21",x"E7",x"20",x"3A",x"67",x"20",x"0F",x"D8", -- 0x0110 + x"23",x"C9",x"0E",x"1C",x"21",x"1E",x"24",x"11", -- 0x0118 + x"E4",x"1A",x"C3",x"F3",x"08",x"21",x"F8",x"20", -- 0x0120 + x"C3",x"31",x"19",x"21",x"FC",x"20",x"C3",x"31", -- 0x0128 + x"19",x"5E",x"23",x"56",x"23",x"7E",x"23",x"66", -- 0x0130 + x"6F",x"C3",x"AD",x"09",x"0E",x"07",x"21",x"01", -- 0x0138 + x"35",x"11",x"A9",x"1F",x"C3",x"F3",x"08",x"3A", -- 0x0140 + x"EB",x"20",x"21",x"01",x"3C",x"C3",x"B2",x"09", -- 0x0148 + x"21",x"F4",x"20",x"C3",x"31",x"19",x"CD",x"5C", -- 0x0150 + x"1A",x"CD",x"1A",x"19",x"CD",x"25",x"19",x"CD", -- 0x0158 + x"2B",x"19",x"CD",x"50",x"19",x"CD",x"3C",x"19", -- 0x0160 + x"C3",x"47",x"19",x"CD",x"DC",x"19",x"C3",x"71", -- 0x0168 + x"16",x"3E",x"01",x"32",x"6D",x"20",x"C3",x"E6", -- 0x0170 + x"16",x"CD",x"D7",x"19",x"CD",x"47",x"19",x"C3", -- 0x0178 + x"3C",x"19",x"32",x"C1",x"20",x"C9",x"8B",x"19", -- 0x0180 + x"C3",x"D6",x"09",x"21",x"03",x"28",x"11",x"BE", -- 0x0188 + x"19",x"0E",x"13",x"C3",x"F3",x"08",x"00",x"00", -- 0x0190 + x"00",x"00",x"3A",x"1E",x"20",x"A7",x"C2",x"AC", -- 0x0198 + x"19",x"DB",x"01",x"E6",x"76",x"D6",x"72",x"C0", -- 0x01A0 + x"3C",x"32",x"1E",x"20",x"DB",x"01",x"E6",x"76", -- 0x01A8 + x"FE",x"34",x"C0",x"21",x"1B",x"2E",x"11",x"F7", -- 0x01B0 + x"0B",x"0E",x"09",x"C3",x"F3",x"08",x"28",x"13", -- 0x01B8 + x"00",x"08",x"13",x"0E",x"26",x"02",x"0E",x"11", -- 0x01C0 + x"0F",x"0E",x"11",x"00",x"13",x"08",x"0E",x"0D", -- 0x01C8 + x"28",x"3E",x"01",x"32",x"E9",x"20",x"C9",x"AF", -- 0x01D0 + x"C3",x"D3",x"19",x"00",x"3A",x"94",x"20",x"A0", -- 0x01D8 + x"32",x"94",x"20",x"D3",x"03",x"C9",x"21",x"01", -- 0x01E0 + x"27",x"CA",x"FA",x"19",x"11",x"60",x"1C",x"06", -- 0x01E8 + x"10",x"4F",x"CD",x"39",x"14",x"79",x"3D",x"C2", -- 0x01F0 + x"EC",x"19",x"06",x"10",x"CD",x"CB",x"14",x"7C", -- 0x01F8 + x"FE",x"35",x"C2",x"FA",x"19",x"C9",x"21",x"72", -- 0x0200 + x"20",x"46",x"1A",x"E6",x"80",x"A8",x"C0",x"37", -- 0x0208 + x"C9",x"32",x"2B",x"24",x"1C",x"16",x"11",x"0D", -- 0x0210 + x"0A",x"08",x"07",x"06",x"05",x"04",x"03",x"02", -- 0x0218 + x"01",x"34",x"2E",x"27",x"22",x"1C",x"18",x"15", -- 0x0220 + x"13",x"10",x"0E",x"0D",x"0C",x"0B",x"09",x"07", -- 0x0228 + x"05",x"FF",x"1A",x"77",x"23",x"13",x"05",x"C2", -- 0x0230 + x"32",x"1A",x"C9",x"5E",x"23",x"56",x"23",x"7E", -- 0x0238 + x"23",x"4E",x"23",x"46",x"61",x"6F",x"C9",x"C5", -- 0x0240 + x"06",x"03",x"7C",x"1F",x"67",x"7D",x"1F",x"6F", -- 0x0248 + x"05",x"C2",x"4A",x"1A",x"7C",x"E6",x"3F",x"F6", -- 0x0250 + x"20",x"67",x"C1",x"C9",x"21",x"00",x"24",x"36", -- 0x0258 + x"00",x"23",x"7C",x"FE",x"40",x"C2",x"5F",x"1A", -- 0x0260 + x"C9",x"C5",x"E5",x"1A",x"B6",x"77",x"13",x"23", -- 0x0268 + x"0D",x"C2",x"6B",x"1A",x"E1",x"01",x"20",x"00", -- 0x0270 + x"09",x"C1",x"05",x"C2",x"69",x"1A",x"C9",x"CD", -- 0x0278 + x"2E",x"09",x"A7",x"C8",x"F5",x"3D",x"77",x"CD", -- 0x0280 + x"E6",x"19",x"F1",x"21",x"01",x"25",x"E6",x"0F", -- 0x0288 + x"C3",x"C5",x"09",x"00",x"00",x"00",x"00",x"FF", -- 0x0290 + x"B8",x"FE",x"20",x"1C",x"10",x"9E",x"00",x"20", -- 0x0298 + x"1C",x"30",x"10",x"0B",x"08",x"07",x"06",x"00", -- 0x02A0 + x"0C",x"04",x"26",x"0E",x"15",x"04",x"11",x"26", -- 0x02A8 + x"26",x"0F",x"0B",x"00",x"18",x"04",x"11",x"24", -- 0x02B0 + x"26",x"25",x"1B",x"26",x"0E",x"11",x"26",x"1C", -- 0x02B8 + x"0F",x"0B",x"00",x"18",x"04",x"11",x"12",x"26", -- 0x02C0 + x"01",x"14",x"13",x"13",x"0E",x"0D",x"26",x"0E", -- 0x02C8 + x"0D",x"0B",x"18",x"26",x"1B",x"0F",x"0B",x"00", -- 0x02D0 + x"18",x"04",x"11",x"26",x"26",x"01",x"14",x"13", -- 0x02D8 + x"13",x"0E",x"0D",x"26",x"26",x"12",x"02",x"0E", -- 0x02E0 + x"11",x"04",x"24",x"1B",x"25",x"26",x"07",x"08", -- 0x02E8 + x"3F",x"12",x"02",x"0E",x"11",x"04",x"26",x"12", -- 0x02F0 + x"02",x"0E",x"11",x"04",x"24",x"1C",x"25",x"26", -- 0x02F8 + x"01",x"00",x"00",x"10",x"00",x"00",x"00",x"00", -- 0x0300 + x"02",x"78",x"38",x"78",x"38",x"00",x"F8",x"00", -- 0x0308 + x"00",x"80",x"00",x"8E",x"02",x"FF",x"05",x"0C", -- 0x0310 + x"60",x"1C",x"20",x"30",x"10",x"01",x"00",x"00", -- 0x0318 + x"00",x"00",x"00",x"BB",x"03",x"00",x"10",x"90", -- 0x0320 + x"1C",x"28",x"30",x"01",x"04",x"00",x"FF",x"FF", -- 0x0328 + x"00",x"00",x"02",x"76",x"04",x"00",x"00",x"00", -- 0x0330 + x"00",x"00",x"04",x"EE",x"1C",x"00",x"00",x"03", -- 0x0338 + x"00",x"00",x"00",x"B6",x"04",x"00",x"00",x"01", -- 0x0340 + x"00",x"1D",x"04",x"E2",x"1C",x"00",x"00",x"03", -- 0x0348 + x"00",x"00",x"00",x"82",x"06",x"00",x"00",x"01", -- 0x0350 + x"06",x"1D",x"04",x"D0",x"1C",x"00",x"00",x"03", -- 0x0358 + x"FF",x"00",x"C0",x"1C",x"00",x"00",x"10",x"21", -- 0x0360 + x"01",x"00",x"30",x"00",x"12",x"00",x"00",x"00", -- 0x0368 + x"0F",x"0B",x"00",x"18",x"26",x"0F",x"0B",x"00", -- 0x0370 + x"18",x"04",x"11",x"24",x"1B",x"25",x"FC",x"00", -- 0x0378 + x"01",x"FF",x"FF",x"00",x"00",x"00",x"20",x"64", -- 0x0380 + x"1D",x"D0",x"29",x"18",x"02",x"54",x"1D",x"00", -- 0x0388 + x"08",x"00",x"06",x"00",x"00",x"01",x"40",x"00", -- 0x0390 + x"01",x"00",x"00",x"10",x"9E",x"00",x"20",x"1C", -- 0x0398 + x"00",x"03",x"04",x"78",x"14",x"13",x"08",x"1A", -- 0x03A0 + x"3D",x"68",x"FC",x"FC",x"68",x"3D",x"1A",x"00", -- 0x03A8 + x"00",x"00",x"01",x"B8",x"98",x"A0",x"1B",x"10", -- 0x03B0 + x"FF",x"00",x"A0",x"1B",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"10",x"00",x"0E",x"05",x"00",x"00",x"00", -- 0x03C0 + x"00",x"00",x"07",x"D0",x"1C",x"C8",x"9B",x"03", -- 0x03C8 + x"00",x"00",x"03",x"04",x"78",x"14",x"0B",x"19", -- 0x03D0 + x"3A",x"6D",x"FA",x"FA",x"6D",x"3A",x"19",x"00", -- 0x03D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 + x"00",x"01",x"00",x"00",x"01",x"74",x"1F",x"00", -- 0x03E8 + x"80",x"00",x"00",x"00",x"00",x"00",x"1C",x"2F", -- 0x03F0 + x"00",x"00",x"1C",x"27",x"00",x"00",x"1C",x"39", -- 0x03F8 + x"00",x"00",x"39",x"79",x"7A",x"6E",x"EC",x"FA", -- 0x0400 + x"FA",x"EC",x"6E",x"7A",x"79",x"39",x"00",x"00", -- 0x0408 + x"00",x"00",x"00",x"78",x"1D",x"BE",x"6C",x"3C", -- 0x0410 + x"3C",x"3C",x"6C",x"BE",x"1D",x"78",x"00",x"00", -- 0x0418 + x"00",x"00",x"00",x"00",x"19",x"3A",x"6D",x"FA", -- 0x0420 + x"FA",x"6D",x"3A",x"19",x"00",x"00",x"00",x"00", -- 0x0428 + x"00",x"00",x"38",x"7A",x"7F",x"6D",x"EC",x"FA", -- 0x0430 + x"FA",x"EC",x"6D",x"7F",x"7A",x"38",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"0E",x"18",x"BE",x"6D",x"3D", -- 0x0440 + x"3C",x"3D",x"6D",x"BE",x"18",x"0E",x"00",x"00", -- 0x0448 + x"00",x"00",x"00",x"00",x"1A",x"3D",x"68",x"FC", -- 0x0450 + x"FC",x"68",x"3D",x"1A",x"00",x"00",x"00",x"00", -- 0x0458 + x"00",x"00",x"0F",x"1F",x"1F",x"1F",x"1F",x"7F", -- 0x0460 + x"FF",x"7F",x"1F",x"1F",x"1F",x"1F",x"0F",x"00", -- 0x0468 + x"00",x"04",x"01",x"13",x"03",x"07",x"B3",x"0F", -- 0x0470 + x"2F",x"03",x"2F",x"49",x"04",x"03",x"00",x"01", -- 0x0478 + x"40",x"08",x"05",x"A3",x"0A",x"03",x"5B",x"0F", -- 0x0480 + x"27",x"27",x"0B",x"4B",x"40",x"84",x"11",x"48", -- 0x0488 + x"0F",x"99",x"3C",x"7E",x"3D",x"BC",x"3E",x"7C", -- 0x0490 + x"99",x"27",x"1B",x"1A",x"26",x"0F",x"0E",x"08", -- 0x0498 + x"0D",x"13",x"12",x"28",x"12",x"02",x"0E",x"11", -- 0x04A0 + x"04",x"26",x"00",x"03",x"15",x"00",x"0D",x"02", -- 0x04A8 + x"04",x"26",x"13",x"00",x"01",x"0B",x"04",x"28", -- 0x04B0 + x"02",x"10",x"20",x"30",x"13",x"08",x"0B",x"13", -- 0x04B8 + x"00",x"08",x"49",x"22",x"14",x"81",x"42",x"00", -- 0x04C0 + x"42",x"81",x"14",x"22",x"49",x"08",x"00",x"00", -- 0x04C8 + x"44",x"AA",x"10",x"88",x"54",x"22",x"10",x"AA", -- 0x04D0 + x"44",x"22",x"54",x"88",x"4A",x"15",x"BE",x"3F", -- 0x04D8 + x"5E",x"25",x"04",x"FC",x"04",x"10",x"FC",x"10", -- 0x04E0 + x"20",x"FC",x"20",x"80",x"FC",x"80",x"00",x"FE", -- 0x04E8 + x"00",x"24",x"FE",x"12",x"00",x"FE",x"00",x"48", -- 0x04F0 + x"FE",x"90",x"0F",x"0B",x"00",x"29",x"00",x"00", -- 0x04F8 + x"01",x"07",x"01",x"01",x"01",x"04",x"0B",x"01", -- 0x0500 + x"06",x"03",x"01",x"01",x"0B",x"09",x"02",x"08", -- 0x0508 + x"02",x"0B",x"04",x"07",x"0A",x"05",x"02",x"05", -- 0x0510 + x"04",x"06",x"07",x"08",x"0A",x"06",x"0A",x"03", -- 0x0518 + x"FF",x"0F",x"FF",x"1F",x"FF",x"3F",x"FF",x"7F", -- 0x0520 + x"FF",x"FF",x"FC",x"FF",x"F8",x"FF",x"F0",x"FF", -- 0x0528 + x"F0",x"FF",x"F0",x"FF",x"F0",x"FF",x"F0",x"FF", -- 0x0530 + x"F0",x"FF",x"F0",x"FF",x"F8",x"FF",x"FC",x"FF", -- 0x0538 + x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"FF",x"3F", -- 0x0540 + x"FF",x"1F",x"FF",x"0F",x"05",x"10",x"15",x"30", -- 0x0548 + x"94",x"97",x"9A",x"9D",x"10",x"05",x"05",x"10", -- 0x0550 + x"15",x"10",x"10",x"05",x"30",x"10",x"10",x"10", -- 0x0558 + x"05",x"15",x"10",x"05",x"00",x"00",x"00",x"00", -- 0x0560 + x"04",x"0C",x"1E",x"37",x"3E",x"7C",x"74",x"7E", -- 0x0568 + x"7E",x"74",x"7C",x"3E",x"37",x"1E",x"0C",x"04", -- 0x0570 + x"00",x"00",x"00",x"00",x"00",x"22",x"00",x"A5", -- 0x0578 + x"40",x"08",x"98",x"3D",x"B6",x"3C",x"36",x"1D", -- 0x0580 + x"10",x"48",x"62",x"B6",x"1D",x"98",x"08",x"42", -- 0x0588 + x"90",x"08",x"00",x"00",x"26",x"1F",x"1A",x"1B", -- 0x0590 + x"1A",x"1A",x"1B",x"1F",x"1A",x"1D",x"1A",x"1A", -- 0x0598 + x"10",x"20",x"30",x"60",x"50",x"48",x"48",x"48", -- 0x05A0 + x"40",x"40",x"40",x"0F",x"0B",x"00",x"18",x"12", -- 0x05A8 + x"0F",x"00",x"02",x"04",x"26",x"26",x"08",x"0D", -- 0x05B0 + x"15",x"00",x"03",x"04",x"11",x"12",x"0E",x"2C", -- 0x05B8 + x"68",x"1D",x"0C",x"2C",x"20",x"1C",x"0A",x"2C", -- 0x05C0 + x"40",x"1C",x"08",x"2C",x"00",x"1C",x"FF",x"0E", -- 0x05C8 + x"2E",x"E0",x"1D",x"0C",x"2E",x"EA",x"1D",x"0A", -- 0x05D0 + x"2E",x"F4",x"1D",x"08",x"2E",x"99",x"1C",x"FF", -- 0x05D8 + x"27",x"38",x"26",x"0C",x"18",x"12",x"13",x"04", -- 0x05E0 + x"11",x"18",x"27",x"1D",x"1A",x"26",x"0F",x"0E", -- 0x05E8 + x"08",x"0D",x"13",x"12",x"27",x"1C",x"1A",x"26", -- 0x05F0 + x"0F",x"0E",x"08",x"0D",x"13",x"12",x"00",x"00", -- 0x05F8 + x"00",x"1F",x"24",x"44",x"24",x"1F",x"00",x"00", -- 0x0600 + x"00",x"7F",x"49",x"49",x"49",x"36",x"00",x"00", -- 0x0608 + x"00",x"3E",x"41",x"41",x"41",x"22",x"00",x"00", -- 0x0610 + x"00",x"7F",x"41",x"41",x"41",x"3E",x"00",x"00", -- 0x0618 + x"00",x"7F",x"49",x"49",x"49",x"41",x"00",x"00", -- 0x0620 + x"00",x"7F",x"48",x"48",x"48",x"40",x"00",x"00", -- 0x0628 + x"00",x"3E",x"41",x"41",x"45",x"47",x"00",x"00", -- 0x0630 + x"00",x"7F",x"08",x"08",x"08",x"7F",x"00",x"00", -- 0x0638 + x"00",x"00",x"41",x"7F",x"41",x"00",x"00",x"00", -- 0x0640 + x"00",x"02",x"01",x"01",x"01",x"7E",x"00",x"00", -- 0x0648 + x"00",x"7F",x"08",x"14",x"22",x"41",x"00",x"00", -- 0x0650 + x"00",x"7F",x"01",x"01",x"01",x"01",x"00",x"00", -- 0x0658 + x"00",x"7F",x"20",x"18",x"20",x"7F",x"00",x"00", -- 0x0660 + x"00",x"7F",x"10",x"08",x"04",x"7F",x"00",x"00", -- 0x0668 + x"00",x"3E",x"41",x"41",x"41",x"3E",x"00",x"00", -- 0x0670 + x"00",x"7F",x"48",x"48",x"48",x"30",x"00",x"00", -- 0x0678 + x"00",x"3E",x"41",x"45",x"42",x"3D",x"00",x"00", -- 0x0680 + x"00",x"7F",x"48",x"4C",x"4A",x"31",x"00",x"00", -- 0x0688 + x"00",x"32",x"49",x"49",x"49",x"26",x"00",x"00", -- 0x0690 + x"00",x"40",x"40",x"7F",x"40",x"40",x"00",x"00", -- 0x0698 + x"00",x"7E",x"01",x"01",x"01",x"7E",x"00",x"00", -- 0x06A0 + x"00",x"7C",x"02",x"01",x"02",x"7C",x"00",x"00", -- 0x06A8 + x"00",x"7F",x"02",x"0C",x"02",x"7F",x"00",x"00", -- 0x06B0 + x"00",x"63",x"14",x"08",x"14",x"63",x"00",x"00", -- 0x06B8 + x"00",x"60",x"10",x"0F",x"10",x"60",x"00",x"00", -- 0x06C0 + x"00",x"43",x"45",x"49",x"51",x"61",x"00",x"00", -- 0x06C8 + x"00",x"3E",x"45",x"49",x"51",x"3E",x"00",x"00", -- 0x06D0 + x"00",x"00",x"21",x"7F",x"01",x"00",x"00",x"00", -- 0x06D8 + x"00",x"23",x"45",x"49",x"49",x"31",x"00",x"00", -- 0x06E0 + x"00",x"42",x"41",x"49",x"59",x"66",x"00",x"00", -- 0x06E8 + x"00",x"0C",x"14",x"24",x"7F",x"04",x"00",x"00", -- 0x06F0 + x"00",x"72",x"51",x"51",x"51",x"4E",x"00",x"00", -- 0x06F8 + x"00",x"1E",x"29",x"49",x"49",x"46",x"00",x"00", -- 0x0700 + x"00",x"40",x"47",x"48",x"50",x"60",x"00",x"00", -- 0x0708 + x"00",x"36",x"49",x"49",x"49",x"36",x"00",x"00", -- 0x0710 + x"00",x"31",x"49",x"49",x"4A",x"3C",x"00",x"00", -- 0x0718 + x"00",x"08",x"14",x"22",x"41",x"00",x"00",x"00", -- 0x0720 + x"00",x"00",x"41",x"22",x"14",x"08",x"00",x"00", -- 0x0728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 + x"00",x"14",x"14",x"14",x"14",x"14",x"00",x"00", -- 0x0738 + x"00",x"22",x"14",x"7F",x"14",x"22",x"00",x"00", -- 0x0740 + x"00",x"03",x"04",x"78",x"04",x"03",x"00",x"00", -- 0x0748 + x"24",x"1B",x"26",x"0E",x"11",x"26",x"1C",x"26", -- 0x0750 + x"0F",x"0B",x"00",x"18",x"04",x"11",x"12",x"25", -- 0x0758 + x"26",x"26",x"28",x"1B",x"26",x"0F",x"0B",x"00", -- 0x0760 + x"18",x"04",x"11",x"26",x"26",x"1B",x"26",x"02", -- 0x0768 + x"0E",x"08",x"0D",x"26",x"01",x"01",x"00",x"00", -- 0x0770 + x"01",x"00",x"02",x"01",x"00",x"02",x"01",x"00", -- 0x0778 + x"60",x"10",x"0F",x"10",x"60",x"30",x"18",x"1A", -- 0x0780 + x"3D",x"68",x"FC",x"FC",x"68",x"3D",x"1A",x"00", -- 0x0788 + x"08",x"0D",x"12",x"04",x"11",x"13",x"26",x"26", -- 0x0790 + x"02",x"0E",x"08",x"0D",x"0D",x"2A",x"50",x"1F", -- 0x0798 + x"0A",x"2A",x"62",x"1F",x"07",x"2A",x"E1",x"1F", -- 0x07A0 + x"FF",x"02",x"11",x"04",x"03",x"08",x"13",x"26", -- 0x07A8 + x"00",x"60",x"10",x"0F",x"10",x"60",x"38",x"19", -- 0x07B0 + x"3A",x"6D",x"FA",x"FA",x"6D",x"3A",x"19",x"00", -- 0x07B8 + x"00",x"20",x"40",x"4D",x"50",x"20",x"00",x"00", -- 0x07C0 + x"00",x"00",x"00",x"FF",x"B8",x"FF",x"80",x"1F", -- 0x07C8 + x"10",x"97",x"00",x"80",x"1F",x"00",x"00",x"01", -- 0x07D0 + x"D0",x"22",x"20",x"1C",x"10",x"94",x"00",x"20", -- 0x07D8 + x"1C",x"28",x"1C",x"26",x"0F",x"0B",x"00",x"18", -- 0x07E0 + x"04",x"11",x"12",x"26",x"1C",x"26",x"02",x"0E", -- 0x07E8 + x"08",x"0D",x"12",x"0F",x"14",x"12",x"07",x"26", -- 0x07F0 + x"00",x"08",x"08",x"08",x"08",x"08",x"00",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + DATA <= ROM(to_integer(unsigned(ADDR))); + end if; + end process; +end RTL; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_f.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_f.vhd new file mode 100644 index 00000000..01bf33e4 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_f.vhd @@ -0,0 +1,288 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity INVADERS_ROM_F is + port ( + CLK : in std_logic; + ENA : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of INVADERS_ROM_F is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"00",x"CD",x"74",x"14",x"00",x"C5",x"E5",x"1A", -- 0x0400 + x"D3",x"04",x"DB",x"03",x"B6",x"77",x"23",x"13", -- 0x0408 + x"AF",x"D3",x"04",x"DB",x"03",x"B6",x"77",x"E1", -- 0x0410 + x"01",x"20",x"00",x"09",x"C1",x"05",x"C2",x"05", -- 0x0418 + x"14",x"C9",x"00",x"00",x"CD",x"74",x"14",x"C5", -- 0x0420 + x"E5",x"AF",x"77",x"23",x"77",x"23",x"E1",x"01", -- 0x0428 + x"20",x"00",x"09",x"C1",x"05",x"C2",x"27",x"14", -- 0x0430 + x"C9",x"C5",x"1A",x"77",x"13",x"01",x"20",x"00", -- 0x0438 + x"09",x"C1",x"05",x"C2",x"39",x"14",x"C9",x"00", -- 0x0440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 + x"00",x"00",x"CD",x"74",x"14",x"C5",x"E5",x"1A", -- 0x0450 + x"D3",x"04",x"DB",x"03",x"2F",x"A6",x"77",x"23", -- 0x0458 + x"13",x"AF",x"D3",x"04",x"DB",x"03",x"2F",x"A6", -- 0x0460 + x"77",x"E1",x"01",x"20",x"00",x"09",x"C1",x"05", -- 0x0468 + x"C2",x"55",x"14",x"C9",x"7D",x"E6",x"07",x"D3", -- 0x0470 + x"02",x"C3",x"47",x"1A",x"C5",x"E5",x"7E",x"12", -- 0x0478 + x"13",x"23",x"0D",x"C2",x"7E",x"14",x"E1",x"01", -- 0x0480 + x"20",x"00",x"09",x"C1",x"05",x"C2",x"7C",x"14", -- 0x0488 + x"C9",x"CD",x"74",x"14",x"AF",x"32",x"61",x"20", -- 0x0490 + x"C5",x"E5",x"1A",x"D3",x"04",x"DB",x"03",x"F5", -- 0x0498 + x"A6",x"CA",x"A9",x"14",x"3E",x"01",x"32",x"61", -- 0x04A0 + x"20",x"F1",x"B6",x"77",x"23",x"13",x"AF",x"D3", -- 0x04A8 + x"04",x"DB",x"03",x"F5",x"A6",x"CA",x"BD",x"14", -- 0x04B0 + x"3E",x"01",x"32",x"61",x"20",x"F1",x"B6",x"77", -- 0x04B8 + x"E1",x"01",x"20",x"00",x"09",x"C1",x"05",x"C2", -- 0x04C0 + x"98",x"14",x"C9",x"AF",x"C5",x"77",x"01",x"20", -- 0x04C8 + x"00",x"09",x"C1",x"05",x"C2",x"CC",x"14",x"C9", -- 0x04D0 + x"3A",x"25",x"20",x"FE",x"05",x"C8",x"FE",x"02", -- 0x04D8 + x"C0",x"3A",x"29",x"20",x"FE",x"D8",x"47",x"D2", -- 0x04E0 + x"30",x"15",x"3A",x"02",x"20",x"A7",x"C8",x"78", -- 0x04E8 + x"FE",x"CE",x"D2",x"79",x"15",x"C6",x"06",x"47", -- 0x04F0 + x"3A",x"09",x"20",x"FE",x"90",x"D2",x"04",x"15", -- 0x04F8 + x"B8",x"D2",x"30",x"15",x"68",x"CD",x"62",x"15", -- 0x0500 + x"3A",x"2A",x"20",x"67",x"CD",x"6F",x"15",x"22", -- 0x0508 + x"64",x"20",x"3E",x"05",x"32",x"25",x"20",x"CD", -- 0x0510 + x"81",x"15",x"7E",x"A7",x"CA",x"30",x"15",x"36", -- 0x0518 + x"00",x"CD",x"5F",x"0A",x"CD",x"3B",x"1A",x"CD", -- 0x0520 + x"D3",x"15",x"3E",x"10",x"32",x"03",x"20",x"C9", -- 0x0528 + x"3E",x"03",x"32",x"25",x"20",x"C3",x"4A",x"15", -- 0x0530 + x"21",x"03",x"20",x"35",x"C0",x"2A",x"64",x"20", -- 0x0538 + x"06",x"10",x"CD",x"24",x"14",x"3E",x"04",x"32", -- 0x0540 + x"25",x"20",x"AF",x"32",x"02",x"20",x"06",x"F7", -- 0x0548 + x"C3",x"DC",x"19",x"00",x"0E",x"00",x"BC",x"D4", -- 0x0550 + x"90",x"15",x"BC",x"D0",x"C6",x"10",x"0C",x"C3", -- 0x0558 + x"5A",x"15",x"3A",x"09",x"20",x"65",x"CD",x"54", -- 0x0560 + x"15",x"41",x"05",x"DE",x"10",x"6F",x"C9",x"3A", -- 0x0568 + x"0A",x"20",x"CD",x"54",x"15",x"DE",x"10",x"67", -- 0x0570 + x"C9",x"3E",x"01",x"32",x"85",x"20",x"C3",x"45", -- 0x0578 + x"15",x"78",x"07",x"07",x"07",x"80",x"80",x"80", -- 0x0580 + x"81",x"3D",x"6F",x"3A",x"67",x"20",x"67",x"C9", -- 0x0588 + x"0C",x"C6",x"10",x"FA",x"90",x"15",x"C9",x"3A", -- 0x0590 + x"0D",x"20",x"A7",x"C2",x"B7",x"15",x"21",x"A4", -- 0x0598 + x"3E",x"CD",x"C5",x"15",x"D0",x"06",x"FE",x"3E", -- 0x05A0 + x"01",x"32",x"0D",x"20",x"78",x"32",x"08",x"20", -- 0x05A8 + x"3A",x"0E",x"20",x"32",x"07",x"20",x"C9",x"21", -- 0x05B0 + x"24",x"25",x"CD",x"C5",x"15",x"D0",x"CD",x"F1", -- 0x05B8 + x"18",x"AF",x"C3",x"A9",x"15",x"06",x"17",x"7E", -- 0x05C0 + x"A7",x"C2",x"6B",x"16",x"23",x"05",x"C2",x"C7", -- 0x05C8 + x"15",x"C9",x"00",x"CD",x"74",x"14",x"E5",x"C5", -- 0x05D0 + x"E5",x"1A",x"D3",x"04",x"DB",x"03",x"77",x"23", -- 0x05D8 + x"13",x"AF",x"D3",x"04",x"DB",x"03",x"77",x"E1", -- 0x05E0 + x"01",x"20",x"00",x"09",x"C1",x"05",x"C2",x"D7", -- 0x05E8 + x"15",x"E1",x"C9",x"CD",x"11",x"16",x"01",x"00", -- 0x05F0 + x"37",x"7E",x"A7",x"CA",x"FF",x"15",x"0C",x"23", -- 0x05F8 + x"05",x"C2",x"F9",x"15",x"79",x"32",x"82",x"20", -- 0x0600 + x"FE",x"01",x"C0",x"21",x"6B",x"20",x"36",x"01", -- 0x0608 + x"C9",x"2E",x"00",x"3A",x"67",x"20",x"67",x"C9", -- 0x0610 + x"3A",x"15",x"20",x"FE",x"FF",x"C0",x"21",x"10", -- 0x0618 + x"20",x"7E",x"23",x"46",x"B0",x"C0",x"3A",x"25", -- 0x0620 + x"20",x"A7",x"C0",x"3A",x"EF",x"20",x"A7",x"CA", -- 0x0628 + x"52",x"16",x"3A",x"2D",x"20",x"A7",x"C2",x"48", -- 0x0630 + x"16",x"CD",x"C0",x"17",x"E6",x"10",x"C8",x"3E", -- 0x0638 + x"01",x"32",x"25",x"20",x"32",x"2D",x"20",x"C9", -- 0x0640 + x"CD",x"C0",x"17",x"E6",x"10",x"C0",x"32",x"2D", -- 0x0648 + x"20",x"C9",x"21",x"25",x"20",x"36",x"01",x"2A", -- 0x0650 + x"ED",x"20",x"23",x"7D",x"FE",x"7E",x"DA",x"63", -- 0x0658 + x"16",x"2E",x"74",x"22",x"ED",x"20",x"7E",x"32", -- 0x0660 + x"1D",x"20",x"C9",x"37",x"C9",x"AF",x"CD",x"8B", -- 0x0668 + x"1A",x"CD",x"10",x"19",x"36",x"00",x"CD",x"CA", -- 0x0670 + x"09",x"23",x"11",x"F5",x"20",x"1A",x"BE",x"1B", -- 0x0678 + x"2B",x"1A",x"CA",x"8B",x"16",x"D2",x"98",x"16", -- 0x0680 + x"C3",x"8F",x"16",x"BE",x"D2",x"98",x"16",x"7E", -- 0x0688 + x"12",x"13",x"23",x"7E",x"12",x"CD",x"50",x"19", -- 0x0690 + x"3A",x"CE",x"20",x"A7",x"CA",x"C9",x"16",x"21", -- 0x0698 + x"03",x"28",x"11",x"A6",x"1A",x"0E",x"14",x"CD", -- 0x06A0 + x"93",x"0A",x"25",x"25",x"06",x"1B",x"3A",x"67", -- 0x06A8 + x"20",x"0F",x"DA",x"B7",x"16",x"06",x"1C",x"78", -- 0x06B0 + x"CD",x"FF",x"08",x"CD",x"B1",x"0A",x"CD",x"E7", -- 0x06B8 + x"18",x"7E",x"A7",x"CA",x"C9",x"16",x"C3",x"ED", -- 0x06C0 + x"02",x"21",x"18",x"2D",x"11",x"A6",x"1A",x"0E", -- 0x06C8 + x"0A",x"CD",x"93",x"0A",x"CD",x"B6",x"0A",x"CD", -- 0x06D0 + x"D6",x"09",x"AF",x"32",x"EF",x"20",x"D3",x"05", -- 0x06D8 + x"CD",x"D1",x"19",x"C3",x"89",x"0B",x"31",x"00", -- 0x06E0 + x"24",x"FB",x"AF",x"32",x"15",x"20",x"CD",x"D8", -- 0x06E8 + x"14",x"06",x"04",x"CD",x"FA",x"18",x"CD",x"59", -- 0x06F0 + x"0A",x"C2",x"EE",x"16",x"CD",x"D7",x"19",x"21", -- 0x06F8 + x"01",x"27",x"CD",x"FA",x"19",x"AF",x"CD",x"8B", -- 0x0700 + x"1A",x"06",x"FB",x"C3",x"6B",x"19",x"CD",x"CA", -- 0x0708 + x"09",x"23",x"7E",x"11",x"B8",x"1C",x"21",x"A1", -- 0x0710 + x"1A",x"0E",x"04",x"47",x"1A",x"B8",x"D2",x"27", -- 0x0718 + x"17",x"23",x"13",x"0D",x"C2",x"1C",x"17",x"7E", -- 0x0720 + x"32",x"CF",x"20",x"C9",x"3A",x"25",x"20",x"FE", -- 0x0728 + x"00",x"C2",x"39",x"17",x"06",x"FD",x"C3",x"DC", -- 0x0730 + x"19",x"06",x"02",x"C3",x"FA",x"18",x"00",x"00", -- 0x0738 + x"21",x"9B",x"20",x"35",x"CC",x"6D",x"17",x"3A", -- 0x0740 + x"68",x"20",x"A7",x"CA",x"6D",x"17",x"21",x"96", -- 0x0748 + x"20",x"35",x"C0",x"21",x"98",x"20",x"7E",x"D3", -- 0x0750 + x"05",x"3A",x"82",x"20",x"A7",x"CA",x"6D",x"17", -- 0x0758 + x"2B",x"7E",x"2B",x"77",x"2B",x"36",x"01",x"3E", -- 0x0760 + x"04",x"32",x"9B",x"20",x"C9",x"3A",x"98",x"20", -- 0x0768 + x"E6",x"30",x"D3",x"05",x"C9",x"3A",x"95",x"20", -- 0x0770 + x"A7",x"CA",x"AA",x"17",x"21",x"11",x"1A",x"11", -- 0x0778 + x"21",x"1A",x"3A",x"82",x"20",x"BE",x"D2",x"8E", -- 0x0780 + x"17",x"23",x"13",x"C3",x"85",x"17",x"1A",x"32", -- 0x0788 + x"97",x"20",x"21",x"98",x"20",x"7E",x"E6",x"30", -- 0x0790 + x"47",x"7E",x"E6",x"0F",x"07",x"FE",x"10",x"C2", -- 0x0798 + x"A4",x"17",x"3E",x"01",x"B0",x"77",x"AF",x"32", -- 0x07A0 + x"95",x"20",x"21",x"99",x"20",x"35",x"C0",x"06", -- 0x07A8 + x"EF",x"C3",x"DC",x"19",x"06",x"EF",x"21",x"98", -- 0x07B0 + x"20",x"7E",x"A0",x"77",x"D3",x"05",x"C9",x"00", -- 0x07B8 + x"3A",x"67",x"20",x"0F",x"D2",x"CA",x"17",x"DB", -- 0x07C0 + x"01",x"C9",x"DB",x"02",x"C9",x"DB",x"02",x"E6", -- 0x07C8 + x"04",x"C8",x"3A",x"9A",x"20",x"A7",x"C0",x"31", -- 0x07D0 + x"00",x"24",x"06",x"04",x"CD",x"D6",x"09",x"05", -- 0x07D8 + x"C2",x"DC",x"17",x"3E",x"01",x"32",x"9A",x"20", -- 0x07E0 + x"CD",x"D7",x"19",x"FB",x"11",x"BC",x"1C",x"21", -- 0x07E8 + x"16",x"30",x"0E",x"04",x"CD",x"93",x"0A",x"CD", -- 0x07F0 + x"B1",x"0A",x"AF",x"32",x"9A",x"20",x"32",x"93" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + DATA <= ROM(to_integer(unsigned(ADDR))); + end if; + end process; +end RTL; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_g.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_g.vhd new file mode 100644 index 00000000..2cdc5141 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_g.vhd @@ -0,0 +1,288 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity INVADERS_ROM_G is + port ( + CLK : in std_logic; + ENA : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of INVADERS_ROM_G is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"AF",x"32",x"C1",x"20",x"CD",x"CF",x"01",x"3A", -- 0x0000 + x"67",x"20",x"0F",x"DA",x"72",x"08",x"CD",x"13", -- 0x0008 + x"02",x"CD",x"CF",x"01",x"CD",x"B1",x"00",x"CD", -- 0x0010 + x"D1",x"19",x"06",x"20",x"CD",x"FA",x"18",x"CD", -- 0x0018 + x"18",x"16",x"CD",x"0A",x"19",x"CD",x"F3",x"15", -- 0x0020 + x"CD",x"88",x"09",x"3A",x"82",x"20",x"A7",x"CA", -- 0x0028 + x"EF",x"09",x"CD",x"0E",x"17",x"CD",x"35",x"09", -- 0x0030 + x"CD",x"D8",x"08",x"CD",x"2C",x"17",x"CD",x"59", -- 0x0038 + x"0A",x"CA",x"49",x"08",x"06",x"04",x"CD",x"FA", -- 0x0040 + x"18",x"CD",x"75",x"17",x"D3",x"06",x"CD",x"04", -- 0x0048 + x"18",x"C3",x"1F",x"08",x"00",x"00",x"00",x"11", -- 0x0050 + x"BA",x"1A",x"CD",x"F3",x"08",x"06",x"98",x"DB", -- 0x0058 + x"01",x"0F",x"0F",x"DA",x"6D",x"08",x"0F",x"DA", -- 0x0060 + x"98",x"07",x"C3",x"7F",x"07",x"3E",x"01",x"C3", -- 0x0068 + x"9B",x"07",x"CD",x"1A",x"02",x"C3",x"14",x"08", -- 0x0070 + x"3A",x"08",x"20",x"47",x"2A",x"09",x"20",x"EB", -- 0x0078 + x"C3",x"86",x"08",x"00",x"00",x"00",x"3A",x"67", -- 0x0080 + x"20",x"67",x"2E",x"FC",x"C9",x"21",x"11",x"2B", -- 0x0088 + x"11",x"70",x"1B",x"0E",x"0E",x"CD",x"F3",x"08", -- 0x0090 + x"3A",x"67",x"20",x"0F",x"3E",x"1C",x"21",x"11", -- 0x0098 + x"37",x"D4",x"FF",x"08",x"3E",x"B0",x"32",x"C0", -- 0x00A0 + x"20",x"3A",x"C0",x"20",x"A7",x"C8",x"E6",x"04", -- 0x00A8 + x"C2",x"BC",x"08",x"CD",x"CA",x"09",x"CD",x"31", -- 0x00B0 + x"19",x"C3",x"A9",x"08",x"06",x"20",x"21",x"1C", -- 0x00B8 + x"27",x"3A",x"67",x"20",x"0F",x"DA",x"CB",x"08", -- 0x00C0 + x"21",x"1C",x"39",x"CD",x"CB",x"14",x"C3",x"A9", -- 0x00C8 + x"08",x"DB",x"02",x"E6",x"03",x"C6",x"03",x"C9", -- 0x00D0 + x"3A",x"82",x"20",x"FE",x"09",x"D0",x"3E",x"FB", -- 0x00D8 + x"32",x"7E",x"20",x"C9",x"3A",x"CE",x"20",x"A7", -- 0x00E0 + x"C0",x"21",x"1C",x"39",x"06",x"20",x"C3",x"CB", -- 0x00E8 + x"14",x"0E",x"03",x"1A",x"D5",x"CD",x"FF",x"08", -- 0x00F0 + x"D1",x"13",x"0D",x"C2",x"F3",x"08",x"C9",x"11", -- 0x00F8 + x"00",x"1E",x"E5",x"26",x"00",x"6F",x"29",x"29", -- 0x0100 + x"29",x"19",x"EB",x"E1",x"06",x"08",x"D3",x"06", -- 0x0108 + x"C3",x"39",x"14",x"3A",x"09",x"20",x"FE",x"78", -- 0x0110 + x"D0",x"2A",x"91",x"20",x"7D",x"B4",x"C2",x"29", -- 0x0118 + x"09",x"21",x"00",x"06",x"3E",x"01",x"32",x"83", -- 0x0120 + x"20",x"2B",x"22",x"91",x"20",x"C9",x"CD",x"11", -- 0x0128 + x"16",x"2E",x"FF",x"7E",x"C9",x"CD",x"10",x"19", -- 0x0130 + x"2B",x"2B",x"7E",x"A7",x"C8",x"06",x"15",x"DB", -- 0x0138 + x"02",x"E6",x"08",x"CA",x"48",x"09",x"06",x"10", -- 0x0140 + x"CD",x"CA",x"09",x"23",x"7E",x"B8",x"D8",x"CD", -- 0x0148 + x"2E",x"09",x"34",x"7E",x"F5",x"21",x"01",x"25", -- 0x0150 + x"24",x"24",x"3D",x"C2",x"58",x"09",x"06",x"10", -- 0x0158 + x"11",x"60",x"1C",x"CD",x"39",x"14",x"F1",x"3C", -- 0x0160 + x"CD",x"8B",x"1A",x"CD",x"10",x"19",x"2B",x"2B", -- 0x0168 + x"36",x"00",x"3E",x"FF",x"32",x"99",x"20",x"06", -- 0x0170 + x"10",x"C3",x"FA",x"18",x"21",x"A0",x"1D",x"FE", -- 0x0178 + x"02",x"D8",x"23",x"FE",x"04",x"D8",x"23",x"C9", -- 0x0180 + x"CD",x"CA",x"09",x"3A",x"F1",x"20",x"A7",x"C8", -- 0x0188 + x"AF",x"32",x"F1",x"20",x"E5",x"2A",x"F2",x"20", -- 0x0190 + x"EB",x"E1",x"7E",x"83",x"27",x"77",x"5F",x"23", -- 0x0198 + x"7E",x"8A",x"27",x"77",x"57",x"23",x"7E",x"23", -- 0x01A0 + x"66",x"6F",x"C3",x"AD",x"09",x"7A",x"CD",x"B2", -- 0x01A8 + x"09",x"7B",x"D5",x"F5",x"0F",x"0F",x"0F",x"0F", -- 0x01B0 + x"E6",x"0F",x"CD",x"C5",x"09",x"F1",x"E6",x"0F", -- 0x01B8 + x"CD",x"C5",x"09",x"D1",x"C9",x"C6",x"1A",x"C3", -- 0x01C0 + x"FF",x"08",x"3A",x"67",x"20",x"0F",x"21",x"F8", -- 0x01C8 + x"20",x"D8",x"21",x"FC",x"20",x"C9",x"21",x"02", -- 0x01D0 + x"24",x"36",x"00",x"23",x"7D",x"E6",x"1F",x"FE", -- 0x01D8 + x"1C",x"DA",x"E8",x"09",x"11",x"06",x"00",x"19", -- 0x01E0 + x"7C",x"FE",x"40",x"DA",x"D9",x"09",x"C9",x"CD", -- 0x01E8 + x"3C",x"0A",x"AF",x"32",x"E9",x"20",x"CD",x"D6", -- 0x01F0 + x"09",x"3A",x"67",x"20",x"F5",x"CD",x"E4",x"01", -- 0x01F8 + x"F1",x"32",x"67",x"20",x"3A",x"67",x"20",x"67", -- 0x0200 + x"E5",x"2E",x"FE",x"7E",x"E6",x"07",x"3C",x"77", -- 0x0208 + x"21",x"A2",x"1D",x"23",x"3D",x"C2",x"13",x"0A", -- 0x0210 + x"7E",x"E1",x"2E",x"FC",x"77",x"23",x"36",x"38", -- 0x0218 + x"7C",x"0F",x"DA",x"33",x"0A",x"3E",x"21",x"32", -- 0x0220 + x"98",x"20",x"CD",x"F5",x"01",x"CD",x"04",x"19", -- 0x0228 + x"C3",x"04",x"08",x"CD",x"EF",x"01",x"CD",x"C0", -- 0x0230 + x"01",x"C3",x"04",x"08",x"CD",x"59",x"0A",x"C2", -- 0x0238 + x"52",x"0A",x"3E",x"30",x"32",x"C0",x"20",x"3A", -- 0x0240 + x"C0",x"20",x"A7",x"C8",x"CD",x"59",x"0A",x"CA", -- 0x0248 + x"47",x"0A",x"CD",x"59",x"0A",x"C2",x"52",x"0A", -- 0x0250 + x"C9",x"3A",x"15",x"20",x"FE",x"FF",x"C9",x"3A", -- 0x0258 + x"EF",x"20",x"A7",x"CA",x"7C",x"0A",x"48",x"06", -- 0x0260 + x"08",x"CD",x"FA",x"18",x"41",x"78",x"CD",x"7C", -- 0x0268 + x"09",x"7E",x"21",x"F3",x"20",x"36",x"00",x"2B", -- 0x0270 + x"77",x"2B",x"36",x"01",x"21",x"62",x"20",x"C9", -- 0x0278 + x"3E",x"02",x"32",x"C1",x"20",x"D3",x"06",x"3A", -- 0x0280 + x"CB",x"20",x"A7",x"CA",x"85",x"0A",x"AF",x"32", -- 0x0288 + x"C1",x"20",x"C9",x"D5",x"1A",x"CD",x"FF",x"08", -- 0x0290 + x"D1",x"3E",x"07",x"32",x"C0",x"20",x"3A",x"C0", -- 0x0298 + x"20",x"3D",x"C2",x"9E",x"0A",x"13",x"0D",x"C2", -- 0x02A0 + x"93",x"0A",x"C9",x"21",x"50",x"20",x"C3",x"4B", -- 0x02A8 + x"02",x"3E",x"40",x"C3",x"D7",x"0A",x"3E",x"80", -- 0x02B0 + x"C3",x"D7",x"0A",x"E1",x"C3",x"72",x"00",x"3A", -- 0x02B8 + x"C1",x"20",x"0F",x"DA",x"BB",x"0A",x"0F",x"DA", -- 0x02C0 + x"68",x"18",x"0F",x"DA",x"AB",x"0A",x"C9",x"21", -- 0x02C8 + x"14",x"2B",x"0E",x"0F",x"C3",x"93",x"0A",x"32", -- 0x02D0 + x"C0",x"20",x"3A",x"C0",x"20",x"A7",x"C2",x"DA", -- 0x02D8 + x"0A",x"C9",x"21",x"C2",x"20",x"06",x"0C",x"C3", -- 0x02E0 + x"32",x"1A",x"AF",x"D3",x"03",x"D3",x"05",x"CD", -- 0x02E8 + x"82",x"19",x"FB",x"CD",x"B1",x"0A",x"3A",x"EC", -- 0x02F0 + x"20",x"A7",x"21",x"17",x"30",x"0E",x"04",x"C2", -- 0x02F8 + x"E8",x"0B",x"11",x"FA",x"1C",x"CD",x"93",x"0A", -- 0x0300 + x"11",x"AF",x"1D",x"CD",x"CF",x"0A",x"CD",x"B1", -- 0x0308 + x"0A",x"CD",x"15",x"18",x"CD",x"B6",x"0A",x"3A", -- 0x0310 + x"EC",x"20",x"A7",x"C2",x"4A",x"0B",x"11",x"95", -- 0x0318 + x"1A",x"CD",x"E2",x"0A",x"CD",x"80",x"0A",x"11", -- 0x0320 + x"B0",x"1B",x"CD",x"E2",x"0A",x"CD",x"80",x"0A", -- 0x0328 + x"CD",x"B1",x"0A",x"11",x"C9",x"1F",x"CD",x"E2", -- 0x0330 + x"0A",x"CD",x"80",x"0A",x"CD",x"B1",x"0A",x"21", -- 0x0338 + x"B7",x"33",x"06",x"0A",x"CD",x"CB",x"14",x"CD", -- 0x0340 + x"B6",x"0A",x"CD",x"D6",x"09",x"3A",x"FF",x"21", -- 0x0348 + x"A7",x"C2",x"5D",x"0B",x"CD",x"D1",x"08",x"32", -- 0x0350 + x"FF",x"21",x"CD",x"7F",x"1A",x"CD",x"E4",x"01", -- 0x0358 + x"CD",x"C0",x"01",x"CD",x"EF",x"01",x"CD",x"1A", -- 0x0360 + x"02",x"3E",x"01",x"32",x"C1",x"20",x"CD",x"CF", -- 0x0368 + x"01",x"CD",x"18",x"16",x"CD",x"F1",x"0B",x"D3", -- 0x0370 + x"06",x"CD",x"59",x"0A",x"CA",x"71",x"0B",x"AF", -- 0x0378 + x"32",x"25",x"20",x"CD",x"59",x"0A",x"C2",x"83", -- 0x0380 + x"0B",x"AF",x"32",x"C1",x"20",x"CD",x"B1",x"0A", -- 0x0388 + x"CD",x"88",x"19",x"0E",x"0C",x"21",x"11",x"2C", -- 0x0390 + x"11",x"90",x"1F",x"CD",x"F3",x"08",x"3A",x"EC", -- 0x0398 + x"20",x"FE",x"00",x"C2",x"AE",x"0B",x"21",x"11", -- 0x03A0 + x"33",x"3E",x"02",x"CD",x"FF",x"08",x"01",x"9C", -- 0x03A8 + x"1F",x"CD",x"56",x"18",x"CD",x"4C",x"18",x"DB", -- 0x03B0 + x"02",x"07",x"DA",x"C3",x"0B",x"01",x"A0",x"1F", -- 0x03B8 + x"CD",x"3A",x"18",x"CD",x"B6",x"0A",x"3A",x"EC", -- 0x03C0 + x"20",x"FE",x"00",x"C2",x"DA",x"0B",x"11",x"D5", -- 0x03C8 + x"1F",x"CD",x"E2",x"0A",x"CD",x"80",x"0A",x"CD", -- 0x03D0 + x"9E",x"18",x"21",x"EC",x"20",x"7E",x"3C",x"E6", -- 0x03D8 + x"01",x"77",x"CD",x"D6",x"09",x"C3",x"DF",x"18", -- 0x03E0 + x"11",x"AB",x"1D",x"CD",x"93",x"0A",x"C3",x"0B", -- 0x03E8 + x"0B",x"CD",x"0A",x"19",x"C3",x"9A",x"19",x"13", -- 0x03F0 + x"00",x"08",x"13",x"0E",x"26",x"02",x"0E",x"0F", -- 0x03F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + DATA <= ROM(to_integer(unsigned(ADDR))); + end if; + end process; +end RTL; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_h.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_h.vhd new file mode 100644 index 00000000..f2f27278 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_rom_h.vhd @@ -0,0 +1,288 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity INVADERS_ROM_H is + port ( + CLK : in std_logic; + ENA : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of INVADERS_ROM_H is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"00",x"00",x"C3",x"D4",x"18",x"00",x"00", -- 0x0000 + x"F5",x"C5",x"D5",x"E5",x"C3",x"8C",x"00",x"00", -- 0x0008 + x"F5",x"C5",x"D5",x"E5",x"3E",x"80",x"32",x"72", -- 0x0010 + x"20",x"21",x"C0",x"20",x"35",x"CD",x"CD",x"17", -- 0x0018 + x"DB",x"01",x"0F",x"DA",x"67",x"00",x"3A",x"EA", -- 0x0020 + x"20",x"A7",x"CA",x"42",x"00",x"3A",x"EB",x"20", -- 0x0028 + x"FE",x"99",x"CA",x"3E",x"00",x"C6",x"01",x"27", -- 0x0030 + x"32",x"EB",x"20",x"CD",x"47",x"19",x"AF",x"32", -- 0x0038 + x"EA",x"20",x"3A",x"E9",x"20",x"A7",x"CA",x"82", -- 0x0040 + x"00",x"3A",x"EF",x"20",x"A7",x"C2",x"6F",x"00", -- 0x0048 + x"3A",x"EB",x"20",x"A7",x"C2",x"5D",x"00",x"CD", -- 0x0050 + x"BF",x"0A",x"C3",x"82",x"00",x"3A",x"93",x"20", -- 0x0058 + x"A7",x"C2",x"82",x"00",x"C3",x"65",x"07",x"3E", -- 0x0060 + x"01",x"32",x"EA",x"20",x"C3",x"3F",x"00",x"CD", -- 0x0068 + x"40",x"17",x"3A",x"32",x"20",x"32",x"80",x"20", -- 0x0070 + x"CD",x"00",x"01",x"CD",x"48",x"02",x"CD",x"13", -- 0x0078 + x"09",x"00",x"E1",x"D1",x"C1",x"F1",x"FB",x"C9", -- 0x0080 + x"00",x"00",x"00",x"00",x"AF",x"32",x"72",x"20", -- 0x0088 + x"3A",x"E9",x"20",x"A7",x"CA",x"82",x"00",x"3A", -- 0x0090 + x"EF",x"20",x"A7",x"C2",x"A5",x"00",x"3A",x"C1", -- 0x0098 + x"20",x"0F",x"D2",x"82",x"00",x"21",x"20",x"20", -- 0x00A0 + x"CD",x"4B",x"02",x"CD",x"41",x"01",x"C3",x"82", -- 0x00A8 + x"00",x"CD",x"86",x"08",x"E5",x"7E",x"23",x"66", -- 0x00B0 + x"6F",x"22",x"09",x"20",x"22",x"0B",x"20",x"E1", -- 0x00B8 + x"2B",x"7E",x"FE",x"03",x"C2",x"C8",x"00",x"3D", -- 0x00C0 + x"32",x"08",x"20",x"FE",x"FE",x"3E",x"00",x"C2", -- 0x00C8 + x"D3",x"00",x"3C",x"32",x"0D",x"20",x"C9",x"3E", -- 0x00D0 + x"02",x"32",x"FB",x"21",x"32",x"FB",x"22",x"C3", -- 0x00D8 + x"E4",x"08",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 + x"21",x"02",x"20",x"7E",x"A7",x"C2",x"38",x"15", -- 0x0100 + x"E5",x"3A",x"06",x"20",x"6F",x"3A",x"67",x"20", -- 0x0108 + x"67",x"7E",x"A7",x"E1",x"CA",x"36",x"01",x"23", -- 0x0110 + x"23",x"7E",x"23",x"46",x"E6",x"FE",x"07",x"07", -- 0x0118 + x"07",x"5F",x"16",x"00",x"21",x"00",x"1C",x"19", -- 0x0120 + x"EB",x"78",x"A7",x"C4",x"3B",x"01",x"2A",x"0B", -- 0x0128 + x"20",x"06",x"10",x"CD",x"D3",x"15",x"AF",x"32", -- 0x0130 + x"00",x"20",x"C9",x"21",x"30",x"00",x"19",x"EB", -- 0x0138 + x"C9",x"3A",x"68",x"20",x"A7",x"C8",x"3A",x"00", -- 0x0140 + x"20",x"A7",x"C0",x"3A",x"67",x"20",x"67",x"3A", -- 0x0148 + x"06",x"20",x"16",x"02",x"3C",x"FE",x"37",x"CC", -- 0x0150 + x"A1",x"01",x"6F",x"46",x"05",x"C2",x"54",x"01", -- 0x0158 + x"32",x"06",x"20",x"CD",x"7A",x"01",x"61",x"22", -- 0x0160 + x"0B",x"20",x"7D",x"FE",x"28",x"DA",x"71",x"19", -- 0x0168 + x"7A",x"32",x"04",x"20",x"3E",x"01",x"32",x"00", -- 0x0170 + x"20",x"C9",x"16",x"00",x"7D",x"21",x"09",x"20", -- 0x0178 + x"46",x"23",x"4E",x"FE",x"0B",x"FA",x"94",x"01", -- 0x0180 + x"DE",x"0B",x"5F",x"78",x"C6",x"10",x"47",x"7B", -- 0x0188 + x"14",x"C3",x"83",x"01",x"68",x"A7",x"C8",x"5F", -- 0x0190 + x"79",x"C6",x"10",x"4F",x"7B",x"3D",x"C3",x"95", -- 0x0198 + x"01",x"15",x"CA",x"CD",x"01",x"21",x"06",x"20", -- 0x01A0 + x"36",x"00",x"23",x"4E",x"36",x"00",x"CD",x"D9", -- 0x01A8 + x"01",x"21",x"05",x"20",x"7E",x"3C",x"E6",x"01", -- 0x01B0 + x"77",x"AF",x"21",x"67",x"20",x"66",x"C9",x"00", -- 0x01B8 + x"21",x"00",x"21",x"06",x"37",x"36",x"01",x"23", -- 0x01C0 + x"05",x"C2",x"C5",x"01",x"C9",x"E1",x"C9",x"3E", -- 0x01C8 + x"01",x"06",x"E0",x"21",x"02",x"24",x"C3",x"CC", -- 0x01D0 + x"14",x"23",x"46",x"23",x"79",x"86",x"77",x"23", -- 0x01D8 + x"78",x"86",x"77",x"C9",x"06",x"C0",x"11",x"00", -- 0x01E0 + x"1B",x"21",x"00",x"20",x"C3",x"32",x"1A",x"21", -- 0x01E8 + x"42",x"21",x"C3",x"F8",x"01",x"21",x"42",x"22", -- 0x01F0 + x"0E",x"04",x"11",x"20",x"1D",x"D5",x"06",x"2C", -- 0x01F8 + x"CD",x"32",x"1A",x"D1",x"0D",x"C2",x"FD",x"01", -- 0x0200 + x"C9",x"3E",x"01",x"C3",x"1B",x"02",x"3E",x"01", -- 0x0208 + x"C3",x"14",x"02",x"AF",x"11",x"42",x"22",x"C3", -- 0x0210 + x"1E",x"02",x"AF",x"11",x"42",x"21",x"32",x"81", -- 0x0218 + x"20",x"01",x"02",x"16",x"21",x"06",x"28",x"3E", -- 0x0220 + x"04",x"F5",x"C5",x"3A",x"81",x"20",x"A7",x"C2", -- 0x0228 + x"42",x"02",x"CD",x"69",x"1A",x"C1",x"F1",x"3D", -- 0x0230 + x"C8",x"D5",x"11",x"E0",x"02",x"19",x"D1",x"C3", -- 0x0238 + x"29",x"02",x"CD",x"7C",x"14",x"C3",x"35",x"02", -- 0x0240 + x"21",x"10",x"20",x"7E",x"FE",x"FF",x"C8",x"FE", -- 0x0248 + x"FE",x"CA",x"81",x"02",x"23",x"46",x"4F",x"B0", -- 0x0250 + x"79",x"C2",x"77",x"02",x"23",x"7E",x"A7",x"C2", -- 0x0258 + x"88",x"02",x"23",x"5E",x"23",x"56",x"E5",x"EB", -- 0x0260 + x"E5",x"21",x"6F",x"02",x"E3",x"D5",x"E9",x"E1", -- 0x0268 + x"11",x"0C",x"00",x"19",x"C3",x"4B",x"02",x"05", -- 0x0270 + x"04",x"C2",x"7D",x"02",x"3D",x"05",x"70",x"2B", -- 0x0278 + x"77",x"11",x"10",x"00",x"19",x"C3",x"4B",x"02", -- 0x0280 + x"35",x"2B",x"2B",x"C3",x"81",x"02",x"E1",x"23", -- 0x0288 + x"7E",x"FE",x"FF",x"CA",x"3B",x"03",x"23",x"35", -- 0x0290 + x"C0",x"47",x"AF",x"32",x"68",x"20",x"32",x"69", -- 0x0298 + x"20",x"3E",x"30",x"32",x"6A",x"20",x"78",x"36", -- 0x02A0 + x"05",x"23",x"35",x"C2",x"9B",x"03",x"2A",x"1A", -- 0x02A8 + x"20",x"06",x"10",x"CD",x"24",x"14",x"21",x"10", -- 0x02B0 + x"20",x"11",x"10",x"1B",x"06",x"10",x"CD",x"32", -- 0x02B8 + x"1A",x"06",x"00",x"CD",x"DC",x"19",x"3A",x"6D", -- 0x02C0 + x"20",x"A7",x"C0",x"3A",x"EF",x"20",x"A7",x"C8", -- 0x02C8 + x"31",x"00",x"24",x"FB",x"CD",x"D7",x"19",x"CD", -- 0x02D0 + x"2E",x"09",x"A7",x"CA",x"6D",x"16",x"CD",x"E7", -- 0x02D8 + x"18",x"7E",x"A7",x"CA",x"2C",x"03",x"3A",x"CE", -- 0x02E0 + x"20",x"A7",x"CA",x"2C",x"03",x"3A",x"67",x"20", -- 0x02E8 + x"F5",x"0F",x"DA",x"32",x"03",x"CD",x"0E",x"02", -- 0x02F0 + x"CD",x"78",x"08",x"73",x"23",x"72",x"2B",x"2B", -- 0x02F8 + x"70",x"00",x"CD",x"E4",x"01",x"F1",x"0F",x"3E", -- 0x0300 + x"21",x"06",x"00",x"D2",x"12",x"03",x"06",x"20", -- 0x0308 + x"3E",x"22",x"32",x"67",x"20",x"CD",x"B6",x"0A", -- 0x0310 + x"AF",x"32",x"11",x"20",x"78",x"D3",x"05",x"3C", -- 0x0318 + x"32",x"98",x"20",x"CD",x"D6",x"09",x"CD",x"7F", -- 0x0320 + x"1A",x"C3",x"F9",x"07",x"CD",x"7F",x"1A",x"C3", -- 0x0328 + x"17",x"08",x"CD",x"09",x"02",x"C3",x"F8",x"02", -- 0x0330 + x"00",x"00",x"00",x"21",x"68",x"20",x"36",x"01", -- 0x0338 + x"23",x"7E",x"A7",x"C3",x"B0",x"03",x"00",x"2B", -- 0x0340 + x"36",x"01",x"3A",x"1B",x"20",x"47",x"3A",x"EF", -- 0x0348 + x"20",x"A7",x"C2",x"63",x"03",x"3A",x"1D",x"20", -- 0x0350 + x"0F",x"DA",x"81",x"03",x"0F",x"DA",x"8E",x"03", -- 0x0358 + x"C3",x"6F",x"03",x"CD",x"C0",x"17",x"07",x"07", -- 0x0360 + x"DA",x"81",x"03",x"07",x"DA",x"8E",x"03",x"21", -- 0x0368 + x"18",x"20",x"CD",x"3B",x"1A",x"CD",x"47",x"1A", -- 0x0370 + x"CD",x"39",x"14",x"3E",x"00",x"32",x"12",x"20", -- 0x0378 + x"C9",x"78",x"FE",x"D9",x"CA",x"6F",x"03",x"3C", -- 0x0380 + x"32",x"1B",x"20",x"C3",x"6F",x"03",x"78",x"FE", -- 0x0388 + x"30",x"CA",x"6F",x"03",x"3D",x"32",x"1B",x"20", -- 0x0390 + x"C3",x"6F",x"03",x"3C",x"E6",x"01",x"32",x"15", -- 0x0398 + x"20",x"07",x"07",x"07",x"07",x"21",x"70",x"1C", -- 0x03A0 + x"85",x"6F",x"22",x"18",x"20",x"C3",x"6F",x"03", -- 0x03A8 + x"C2",x"4A",x"03",x"23",x"35",x"C2",x"4A",x"03", -- 0x03B0 + x"C3",x"46",x"03",x"11",x"2A",x"20",x"CD",x"06", -- 0x03B8 + x"1A",x"E1",x"D0",x"23",x"7E",x"A7",x"C8",x"FE", -- 0x03C0 + x"01",x"CA",x"FA",x"03",x"FE",x"02",x"CA",x"0A", -- 0x03C8 + x"04",x"23",x"FE",x"03",x"C2",x"2A",x"04",x"35", -- 0x03D0 + x"CA",x"36",x"04",x"7E",x"FE",x"0F",x"C0",x"E5", -- 0x03D8 + x"CD",x"30",x"04",x"CD",x"52",x"14",x"E1",x"23", -- 0x03E0 + x"34",x"23",x"23",x"35",x"35",x"23",x"35",x"35", -- 0x03E8 + x"35",x"23",x"36",x"08",x"CD",x"30",x"04",x"C3", -- 0x03F0 + x"00",x"14",x"3C",x"77",x"3A",x"1B",x"20",x"C6", -- 0x03F8 + x"08",x"32",x"2A",x"20",x"CD",x"30",x"04",x"C3", -- 0x0400 + x"00",x"14",x"CD",x"30",x"04",x"D5",x"E5",x"C5", -- 0x0408 + x"CD",x"52",x"14",x"C1",x"E1",x"D1",x"3A",x"2C", -- 0x0410 + x"20",x"85",x"6F",x"32",x"29",x"20",x"CD",x"91", -- 0x0418 + x"14",x"3A",x"61",x"20",x"A7",x"C8",x"32",x"02", -- 0x0420 + x"20",x"C9",x"FE",x"05",x"C8",x"C3",x"36",x"04", -- 0x0428 + x"21",x"27",x"20",x"C3",x"3B",x"1A",x"CD",x"30", -- 0x0430 + x"04",x"CD",x"52",x"14",x"21",x"25",x"20",x"11", -- 0x0438 + x"25",x"1B",x"06",x"07",x"CD",x"32",x"1A",x"2A", -- 0x0440 + x"8D",x"20",x"2C",x"7D",x"FE",x"63",x"DA",x"53", -- 0x0448 + x"04",x"2E",x"54",x"22",x"8D",x"20",x"2A",x"8F", -- 0x0450 + x"20",x"2C",x"22",x"8F",x"20",x"3A",x"84",x"20", -- 0x0458 + x"A7",x"C0",x"7E",x"E6",x"01",x"01",x"29",x"02", -- 0x0460 + x"C2",x"6E",x"04",x"01",x"E0",x"FE",x"21",x"8A", -- 0x0468 + x"20",x"71",x"23",x"23",x"70",x"C9",x"E1",x"3A", -- 0x0470 + x"32",x"1B",x"32",x"32",x"20",x"2A",x"38",x"20", -- 0x0478 + x"7D",x"B4",x"C2",x"8A",x"04",x"2B",x"22",x"38", -- 0x0480 + x"20",x"C9",x"11",x"35",x"20",x"3E",x"F9",x"CD", -- 0x0488 + x"50",x"05",x"3A",x"46",x"20",x"32",x"70",x"20", -- 0x0490 + x"3A",x"56",x"20",x"32",x"71",x"20",x"CD",x"63", -- 0x0498 + x"05",x"3A",x"78",x"20",x"A7",x"21",x"35",x"20", -- 0x04A0 + x"C2",x"5B",x"05",x"11",x"30",x"1B",x"21",x"30", -- 0x04A8 + x"20",x"06",x"10",x"C3",x"32",x"1A",x"E1",x"3A", -- 0x04B0 + x"6E",x"20",x"A7",x"C0",x"3A",x"80",x"20",x"FE", -- 0x04B8 + x"01",x"C0",x"11",x"45",x"20",x"3E",x"ED",x"CD", -- 0x04C0 + x"50",x"05",x"3A",x"36",x"20",x"32",x"70",x"20", -- 0x04C8 + x"3A",x"56",x"20",x"32",x"71",x"20",x"CD",x"63", -- 0x04D0 + x"05",x"3A",x"76",x"20",x"FE",x"10",x"DA",x"E7", -- 0x04D8 + x"04",x"3A",x"48",x"1B",x"32",x"76",x"20",x"3A", -- 0x04E0 + x"78",x"20",x"A7",x"21",x"45",x"20",x"C2",x"5B", -- 0x04E8 + x"05",x"11",x"40",x"1B",x"21",x"40",x"20",x"06", -- 0x04F0 + x"10",x"CD",x"32",x"1A",x"3A",x"82",x"20",x"3D", -- 0x04F8 + x"C2",x"08",x"05",x"3E",x"01",x"32",x"6E",x"20", -- 0x0500 + x"2A",x"76",x"20",x"C3",x"7E",x"06",x"E1",x"11", -- 0x0508 + x"55",x"20",x"3E",x"DB",x"CD",x"50",x"05",x"3A", -- 0x0510 + x"46",x"20",x"32",x"70",x"20",x"3A",x"36",x"20", -- 0x0518 + x"32",x"71",x"20",x"CD",x"63",x"05",x"3A",x"76", -- 0x0520 + x"20",x"FE",x"15",x"DA",x"34",x"05",x"3A",x"58", -- 0x0528 + x"1B",x"32",x"76",x"20",x"3A",x"78",x"20",x"A7", -- 0x0530 + x"21",x"55",x"20",x"C2",x"5B",x"05",x"11",x"50", -- 0x0538 + x"1B",x"21",x"50",x"20",x"06",x"10",x"CD",x"32", -- 0x0540 + x"1A",x"2A",x"76",x"20",x"22",x"58",x"20",x"C9", -- 0x0548 + x"32",x"7F",x"20",x"21",x"73",x"20",x"06",x"0B", -- 0x0550 + x"C3",x"32",x"1A",x"11",x"73",x"20",x"06",x"0B", -- 0x0558 + x"C3",x"32",x"1A",x"21",x"73",x"20",x"7E",x"E6", -- 0x0560 + x"80",x"C2",x"C1",x"05",x"3A",x"C1",x"20",x"FE", -- 0x0568 + x"04",x"3A",x"69",x"20",x"CA",x"B7",x"05",x"A7", -- 0x0570 + x"C8",x"23",x"36",x"00",x"3A",x"70",x"20",x"A7", -- 0x0578 + x"CA",x"89",x"05",x"47",x"3A",x"CF",x"20",x"B8", -- 0x0580 + x"D0",x"3A",x"71",x"20",x"A7",x"CA",x"96",x"05", -- 0x0588 + x"47",x"3A",x"CF",x"20",x"B8",x"D0",x"23",x"7E", -- 0x0590 + x"A7",x"CA",x"1B",x"06",x"2A",x"76",x"20",x"4E", -- 0x0598 + x"23",x"00",x"22",x"76",x"20",x"CD",x"2F",x"06", -- 0x05A0 + x"D0",x"CD",x"7A",x"01",x"79",x"C6",x"07",x"67", -- 0x05A8 + x"7D",x"D6",x"0A",x"6F",x"22",x"7B",x"20",x"21", -- 0x05B0 + x"73",x"20",x"7E",x"F6",x"80",x"77",x"23",x"34", -- 0x05B8 + x"C9",x"11",x"7C",x"20",x"CD",x"06",x"1A",x"D0", -- 0x05C0 + x"23",x"7E",x"E6",x"01",x"C2",x"44",x"06",x"23", -- 0x05C8 + x"34",x"CD",x"75",x"06",x"3A",x"79",x"20",x"C6", -- 0x05D0 + x"03",x"21",x"7F",x"20",x"BE",x"DA",x"E2",x"05", -- 0x05D8 + x"D6",x"0C",x"32",x"79",x"20",x"3A",x"7B",x"20", -- 0x05E0 + x"47",x"3A",x"7E",x"20",x"80",x"32",x"7B",x"20", -- 0x05E8 + x"CD",x"6C",x"06",x"3A",x"7B",x"20",x"FE",x"15", -- 0x05F0 + x"DA",x"12",x"06",x"3A",x"61",x"20",x"A7",x"C8", -- 0x05F8 + x"3A",x"7B",x"20",x"FE",x"1E",x"DA",x"12",x"06", -- 0x0600 + x"FE",x"27",x"00",x"D2",x"12",x"06",x"97",x"32", -- 0x0608 + x"15",x"20",x"3A",x"73",x"20",x"F6",x"01",x"32", -- 0x0610 + x"73",x"20",x"C9",x"3A",x"1B",x"20",x"C6",x"08", -- 0x0618 + x"67",x"CD",x"6F",x"15",x"79",x"FE",x"0C",x"DA", -- 0x0620 + x"A5",x"05",x"0E",x"0B",x"C3",x"A5",x"05",x"0D", -- 0x0628 + x"3A",x"67",x"20",x"67",x"69",x"16",x"05",x"7E", -- 0x0630 + x"A7",x"37",x"C0",x"7D",x"C6",x"0B",x"6F",x"15", -- 0x0638 + x"C2",x"37",x"06",x"C9",x"21",x"78",x"20",x"35", -- 0x0640 + x"7E",x"FE",x"03",x"C2",x"67",x"06",x"CD",x"75", -- 0x0648 + x"06",x"21",x"DC",x"1C",x"22",x"79",x"20",x"21", -- 0x0650 + x"7C",x"20",x"35",x"35",x"2B",x"35",x"35",x"3E", -- 0x0658 + x"06",x"32",x"7D",x"20",x"C3",x"6C",x"06",x"A7", -- 0x0660 + x"C0",x"C3",x"75",x"06",x"21",x"79",x"20",x"CD", -- 0x0668 + x"3B",x"1A",x"C3",x"91",x"14",x"21",x"79",x"20", -- 0x0670 + x"CD",x"3B",x"1A",x"C3",x"52",x"14",x"22",x"48", -- 0x0678 + x"20",x"C9",x"E1",x"3A",x"80",x"20",x"FE",x"02", -- 0x0680 + x"C0",x"21",x"83",x"20",x"7E",x"A7",x"CA",x"0F", -- 0x0688 + x"05",x"3A",x"56",x"20",x"A7",x"C2",x"0F",x"05", -- 0x0690 + x"23",x"7E",x"A7",x"C2",x"AB",x"06",x"3A",x"82", -- 0x0698 + x"20",x"FE",x"08",x"DA",x"0F",x"05",x"36",x"01", -- 0x06A0 + x"CD",x"3C",x"07",x"11",x"8A",x"20",x"CD",x"06", -- 0x06A8 + x"1A",x"D0",x"21",x"85",x"20",x"7E",x"A7",x"C2", -- 0x06B0 + x"D6",x"06",x"21",x"8A",x"20",x"7E",x"23",x"23", -- 0x06B8 + x"86",x"32",x"8A",x"20",x"CD",x"3C",x"07",x"21", -- 0x06C0 + x"8A",x"20",x"7E",x"FE",x"28",x"DA",x"F9",x"06", -- 0x06C8 + x"FE",x"E1",x"D2",x"F9",x"06",x"C9",x"06",x"FE", -- 0x06D0 + x"CD",x"DC",x"19",x"23",x"35",x"7E",x"FE",x"1F", -- 0x06D8 + x"CA",x"4B",x"07",x"FE",x"18",x"CA",x"0C",x"07", -- 0x06E0 + x"A7",x"C0",x"06",x"EF",x"21",x"98",x"20",x"7E", -- 0x06E8 + x"A0",x"77",x"E6",x"20",x"D3",x"05",x"00",x"00", -- 0x06F0 + x"00",x"CD",x"42",x"07",x"CD",x"CB",x"14",x"21", -- 0x06F8 + x"83",x"20",x"06",x"0A",x"CD",x"5F",x"07",x"06", -- 0x0700 + x"FE",x"C3",x"DC",x"19",x"3E",x"01",x"32",x"F1", -- 0x0708 + x"20",x"2A",x"8D",x"20",x"46",x"0E",x"04",x"21", -- 0x0710 + x"50",x"1D",x"11",x"4C",x"1D",x"1A",x"B8",x"CA", -- 0x0718 + x"28",x"07",x"23",x"13",x"0D",x"C2",x"1D",x"07", -- 0x0720 + x"7E",x"32",x"87",x"20",x"26",x"00",x"68",x"29", -- 0x0728 + x"29",x"29",x"29",x"22",x"F2",x"20",x"CD",x"42", -- 0x0730 + x"07",x"C3",x"F1",x"08",x"CD",x"42",x"07",x"C3", -- 0x0738 + x"39",x"14",x"21",x"87",x"20",x"CD",x"3B",x"1A", -- 0x0740 + x"C3",x"47",x"1A",x"06",x"10",x"21",x"98",x"20", -- 0x0748 + x"7E",x"B0",x"77",x"CD",x"70",x"17",x"21",x"7C", -- 0x0750 + x"1D",x"22",x"87",x"20",x"C3",x"3C",x"07",x"11", -- 0x0758 + x"83",x"1B",x"C3",x"32",x"1A",x"3E",x"01",x"32", -- 0x0760 + x"93",x"20",x"31",x"00",x"24",x"FB",x"CD",x"79", -- 0x0768 + x"19",x"CD",x"D6",x"09",x"21",x"13",x"30",x"11", -- 0x0770 + x"F3",x"1F",x"0E",x"04",x"CD",x"F3",x"08",x"3A", -- 0x0778 + x"EB",x"20",x"3D",x"21",x"10",x"28",x"0E",x"14", -- 0x0780 + x"C2",x"57",x"08",x"11",x"CF",x"1A",x"CD",x"F3", -- 0x0788 + x"08",x"DB",x"01",x"E6",x"04",x"CA",x"7F",x"07", -- 0x0790 + x"06",x"99",x"AF",x"32",x"CE",x"20",x"3A",x"EB", -- 0x0798 + x"20",x"80",x"27",x"32",x"EB",x"20",x"CD",x"47", -- 0x07A0 + x"19",x"21",x"00",x"00",x"22",x"F8",x"20",x"22", -- 0x07A8 + x"FC",x"20",x"CD",x"25",x"19",x"CD",x"2B",x"19", -- 0x07B0 + x"CD",x"D7",x"19",x"21",x"01",x"01",x"7C",x"32", -- 0x07B8 + x"EF",x"20",x"22",x"E7",x"20",x"22",x"E5",x"20", -- 0x07C0 + x"CD",x"56",x"19",x"CD",x"EF",x"01",x"CD",x"F5", -- 0x07C8 + x"01",x"CD",x"D1",x"08",x"32",x"FF",x"21",x"32", -- 0x07D0 + x"FF",x"22",x"CD",x"D7",x"00",x"AF",x"32",x"FE", -- 0x07D8 + x"21",x"32",x"FE",x"22",x"CD",x"C0",x"01",x"CD", -- 0x07E0 + x"04",x"19",x"21",x"78",x"38",x"22",x"FC",x"21", -- 0x07E8 + x"22",x"FC",x"22",x"CD",x"E4",x"01",x"CD",x"7F", -- 0x07F0 + x"1A",x"CD",x"8D",x"08",x"CD",x"D6",x"09",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + DATA <= ROM(to_integer(unsigned(ADDR))); + end if; + end process; +end RTL; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_top.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_top.vhd new file mode 100644 index 00000000..c5e11d4a --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_top.vhd @@ -0,0 +1,319 @@ +-- Space Invaders top level for +-- ps/2 keyboard interface with sound and scan doubler MikeJ +-- +-- Version : 0300 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Moved the PS/2 interface to ps2kbd.vhd, added the ROM from mw8080.vhd +-- +-- 0300 : MikeJ tidy up for audio release + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity invaders_top is + port( + Buttons : in std_logic_vector(5 downto 0); + O_VIDEO_R : out std_logic; + O_VIDEO_G : out std_logic; + O_VIDEO_B : out std_logic; + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + -- + Audio : out std_logic_vector(7 downto 0); + -- + I_RESET : in std_logic; + CLK : in std_logic--10mhz + ); +end invaders_top; + +architecture rtl of invaders_top is + + signal I_RESET_L : std_logic; + signal Rst_n_s : std_logic; + + signal DIP : std_logic_vector(8 downto 1); + signal RWE_n : std_logic; + signal Video : std_logic; + signal VideoRGB : std_logic_vector(2 downto 0); + signal HSync : std_logic; + signal VSync : std_logic; + + signal AD : std_logic_vector(15 downto 0); + signal RAB : std_logic_vector(12 downto 0); + signal RDB : std_logic_vector(7 downto 0); + signal RWD : std_logic_vector(7 downto 0); + signal IB : std_logic_vector(7 downto 0); + signal SoundCtrl3 : std_logic_vector(5 downto 0); + signal SoundCtrl5 : std_logic_vector(5 downto 0); + + signal Buttons_n : std_logic_vector(5 downto 1); + signal Tick1us : std_logic; + + signal PS2_Sample : std_logic; + signal PS2_Data_s : std_logic; + signal ScanCode : std_logic_vector(7 downto 0); + signal Press : std_logic; + signal Release : std_logic; + signal Reset : std_logic; + + signal rom_data_0 : std_logic_vector(7 downto 0); + signal rom_data_1 : std_logic_vector(7 downto 0); + signal rom_data_2 : std_logic_vector(7 downto 0); + signal rom_data_3 : std_logic_vector(7 downto 0); + signal ram_we : std_logic; + -- + signal HCnt : std_logic_vector(11 downto 0); + signal VCnt : std_logic_vector(11 downto 0); + signal HSync_t1 : std_logic; + signal Overlay_G1 : boolean; + signal Overlay_G2 : boolean; + signal Overlay_R1 : boolean; + signal Overlay_G1_VCnt : boolean; + +begin + + + I_RESET_L <= not I_RESET; + + DIP <= "00000000"; + + core : entity work.invaderst + port map( + Rst_n => I_RESET_L, + Clk => Clk, + Coin => Buttons(0), + Sel1Player => not Buttons(1), + Sel2Player => not Buttons(2), + Fire => not Buttons(3), + MoveLeft => not Buttons(4), + MoveRight => not Buttons(5), + DIP => DIP, + RDB => RDB, + IB => IB, + RWD => RWD, + RAB => RAB, + AD => AD, + SoundCtrl3 => SoundCtrl3, + SoundCtrl5 => SoundCtrl5, + Rst_n_s => Rst_n_s, + RWE_n => RWE_n, + Video => Video, + HSync => HSync, + VSync => VSync + ); + -- + -- ROM + -- + u_rom_h : entity work.INVADERS_ROM_H + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_0 + ); + -- + u_rom_g : entity work.INVADERS_ROM_G + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_1 + ); + -- + u_rom_f : entity work.INVADERS_ROM_F + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_2 + ); + -- + u_rom_e : entity work.INVADERS_ROM_E + port map ( + CLK => Clk, + ENA => '1', + ADDR => AD(10 downto 0), + DATA => rom_data_3 + ); + -- + p_rom_data : process(AD, rom_data_0, rom_data_1, rom_data_2, rom_data_3) + begin + IB <= (others => '0'); + case AD(12 downto 11) is + when "00" => IB <= rom_data_0; + when "01" => IB <= rom_data_1; + when "10" => IB <= rom_data_2; + when "11" => IB <= rom_data_3; + when others => null; + end case; + end process; + -- + -- SRAM + -- + ram_we <= not RWE_n; + + rams : for i in 0 to 3 generate + u_ram : entity work.WRAM + port map ( + q => RDB((i*2)+1 downto (i*2)), + address => RAB, + clock => Clk, + data => RWD((i*2)+1 downto (i*2)), + rden => '1', + wren => ram_we + ); + end generate; + -- + -- Glue + -- + process (Rst_n_s, Clk) + variable cnt : unsigned(3 downto 0); + begin + if Rst_n_s = '0' then + cnt := "0000"; + Tick1us <= '0'; + elsif Clk'event and Clk = '1' then + Tick1us <= '0'; + if cnt = 9 then + Tick1us <= '1'; + cnt := "0000"; + else + cnt := cnt + 1; + end if; + end if; + end process; + + p_overlay : process(Rst_n_s, Clk) + variable HStart : boolean; + begin + if Rst_n_s = '0' then + HCnt <= (others => '0'); + VCnt <= (others => '0'); + HSync_t1 <= '0'; + Overlay_G1_VCnt <= false; + Overlay_G1 <= false; + Overlay_G2 <= false; + Overlay_R1 <= false; + elsif Clk'event and Clk = '1' then + HSync_t1 <= HSync; + HStart := (HSync_t1 = '0') and (HSync = '1');-- rising + + if HStart then + HCnt <= (others => '0'); + else + HCnt <= HCnt + "1"; + end if; + + if (VSync = '0') then + VCnt <= (others => '0'); + elsif HStart then + VCnt <= VCnt + "1"; + end if; + + if HStart then + if (Vcnt = x"1F") then + Overlay_G1_VCnt <= true; + elsif (Vcnt = x"95") then + Overlay_G1_VCnt <= false; + end if; + end if; + + if (HCnt = x"027") and Overlay_G1_VCnt then + Overlay_G1 <= true; + elsif (HCnt = x"046") then + Overlay_G1 <= false; + end if; + + if (HCnt = x"046") then + Overlay_G2 <= true; + elsif (HCnt = x"0B6") then + Overlay_G2 <= false; + end if; + + if (HCnt = x"1A6") then + Overlay_R1 <= true; + elsif (HCnt = x"1E6") then + Overlay_R1 <= false; + end if; + + end if; + end process; + + p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) + begin + if (Video = '0') then + VideoRGB <= "000"; + else + if Overlay_G1 or Overlay_G2 then + VideoRGB <= "010"; + elsif Overlay_R1 then + VideoRGB <= "100"; + else + VideoRGB <= "111"; + end if; + end if; + end process; + + + O_VIDEO_R <= VideoRGB(2); + O_VIDEO_G <= VideoRGB(1); + O_VIDEO_B <= VideoRGB(0); + O_HSYNC <= not HSync; + O_VSYNC <= not VSync; + -- + -- Audio + -- + u_audio : entity work.invaders_audio + port map ( + Clk => Clk, + S1 => SoundCtrl3, + S2 => SoundCtrl5, + Aud => Audio + ); + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd new file mode 100644 index 00000000..ed3007f7 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd @@ -0,0 +1,126 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + + +entity invaders_video is + port( + Video : in std_logic; + CLK : in std_logic; + Rst_n_s : in std_logic; + HSync : in std_logic; + VSync : in std_logic; + O_VIDEO_R : out std_logic; + O_VIDEO_G : out std_logic; + O_VIDEO_B : out std_logic; + O_HSYNC : out std_logic; + O_VSYNC : out std_logic + ); +end invaders_video; + +architecture rtl of invaders_video is + + signal HCnt : std_logic_vector(11 downto 0); + signal VCnt : std_logic_vector(11 downto 0); + signal HSync_t1 : std_logic; + signal Overlay_G1 : boolean; + signal Overlay_G2 : boolean; + signal Overlay_R1 : boolean; + signal Overlay_G1_VCnt : boolean; + signal VideoRGB : std_logic_vector(2 downto 0); +begin + process (Rst_n_s, Clk) + variable cnt : unsigned(3 downto 0); + begin + if Rst_n_s = '0' then + cnt := "0000"; + elsif Clk'event and Clk = '1' then + if cnt = 9 then + cnt := "0000"; + else + cnt := cnt + 1; + end if; + end if; + end process; + + p_overlay : process(Rst_n_s, Clk) + variable HStart : boolean; + begin + if Rst_n_s = '0' then + HCnt <= (others => '0'); + VCnt <= (others => '0'); + HSync_t1 <= '0'; + Overlay_G1_VCnt <= false; + Overlay_G1 <= false; + Overlay_G2 <= false; + Overlay_R1 <= false; + elsif Clk'event and Clk = '1' then + HSync_t1 <= HSync; + HStart := (HSync_t1 = '0') and (HSync = '1'); + + if HStart then + HCnt <= (others => '0'); + else + HCnt <= HCnt + "1"; + end if; + + if (VSync = '0') then + VCnt <= (others => '0'); + elsif HStart then + VCnt <= VCnt + "1"; + end if; + + if HStart then + if (Vcnt = x"1F") then + Overlay_G1_VCnt <= true; + elsif (Vcnt = x"95") then + Overlay_G1_VCnt <= false; + end if; + end if; + + if (HCnt = x"027") and Overlay_G1_VCnt then + Overlay_G1 <= true; + elsif (HCnt = x"046") then + Overlay_G1 <= false; + end if; + + if (HCnt = x"046") then + Overlay_G2 <= true; + elsif (HCnt = x"0B6") then + Overlay_G2 <= false; + end if; + + if (HCnt = x"1A6") then + Overlay_R1 <= true; + elsif (HCnt = x"1E6") then + Overlay_R1 <= false; + end if; + + end if; + end process; + + p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1) + begin + if (Video = '0') then + VideoRGB <= "000"; + else + if Overlay_G1 or Overlay_G2 then + VideoRGB <= "010"; + elsif Overlay_R1 then + VideoRGB <= "100"; + else + VideoRGB <= "111"; + end if; + end if; + end process; + + + O_VIDEO_R <= VideoRGB(2); + O_VIDEO_G <= VideoRGB(1); + O_VIDEO_B <= VideoRGB(0); + O_HSYNC <= not HSync; + O_VSYNC <= not VSync; + + +end; \ No newline at end of file diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/keyboard.v b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/keyboard.v new file mode 100644 index 00000000..ba7038b6 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space +// 'h11: joystick[1] <= ~release_btn; // Left Alt +// 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/mist_io.v b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/mw8080.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/mw8080.vhd new file mode 100644 index 00000000..51d495a6 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/mw8080.vhd @@ -0,0 +1,336 @@ +-- Midway 8080 main board +-- 9.984MHz Clock +-- +-- Version : 0242 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.fpgaarcade.com +-- +-- Limitations : +-- +-- File history : +-- +-- 0241 : First release +-- +-- 0242 : Removed the ROM +-- +-- 0300 : MikeJ tidyup for audio release +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity mw8080 is + port( + Rst_n : in std_logic; + Clk : in std_logic; + ENA : out std_logic; + RWE_n : out std_logic; + RDB : in std_logic_vector(7 downto 0); + RAB : out std_logic_vector(12 downto 0); + Sounds : out std_logic_vector(7 downto 0); + Ready : out std_logic; + GDB : in std_logic_vector(7 downto 0); + IB : in std_logic_vector(7 downto 0); + DB : out std_logic_vector(7 downto 0); + AD : out std_logic_vector(15 downto 0); + Status : out std_logic_vector(7 downto 0); + Systb : out std_logic; + Int : out std_logic; + Hold_n : in std_logic; + IntE : out std_logic; + DBin_n : out std_logic; + Vait : out std_logic; + HldA : out std_logic; + Sample : out std_logic; + Wr : out std_logic; + Video : out std_logic; + HSync : out std_logic; + VSync : out std_logic); +end mw8080; + +architecture struct of mw8080 is + + component T8080se + generic( + Mode : integer := 2; + T2Write : integer := 0); + port( + RESET_n : in std_logic; + CLK : in std_logic; + CLKEN : in std_logic; + READY : in std_logic; + HOLD : in std_logic; + INT : in std_logic; + INTE : out std_logic; + DBIN : out std_logic; + SYNC : out std_logic; + VAIT : out std_logic; + HLDA : out std_logic; + WR_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0)); + end component; + + signal Ready_i : std_logic; + signal Hold : std_logic; + signal IntTrig : std_logic; + signal IntTrigOld : std_logic; + signal Int_i : std_logic; + signal IntE_i : std_logic; + signal DBin : std_logic; + signal Sync : std_logic; + signal Wr_n : std_logic; + signal ClkEnCnt : unsigned(2 downto 0); + signal Status_i : std_logic_vector(7 downto 0); + signal A : std_logic_vector(15 downto 0); + signal ISel : std_logic_vector(1 downto 0); + signal DI : std_logic_vector(7 downto 0); + signal DO : std_logic_vector(7 downto 0); + signal RR : std_logic_vector(9 downto 0); + + signal VidEn : std_logic; + signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320 + signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2 + signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262 + signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2 + signal Shift : std_logic_vector(7 downto 0); + +begin + ENA <= ClkEnCnt(2); + Status <= Status_i; + Ready <= Ready_i; + DB <= DO; + Systb <= Sync; + Int <= Int_i; + Hold <= not Hold_n; + IntE <= IntE_i; + DBin_n <= not DBin; + Sample <= not Wr_n and Status_i(4); + Wr <= not Wr_n; + AD <= A; + Sounds(0) <= CntE7(3); + Sounds(1) <= CntE7(2); + Sounds(2) <= CntE7(1); + Sounds(3) <= CntE7(0); + Sounds(4) <= CntE6(3); + Sounds(5) <= CntE6(2); + Sounds(6) <= CntE6(1); + Sounds(7) <= CntE6(0); + + IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4); + + ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13)); + ISel(1) <= Status_i(0) nor Status_i(6); + + with ISel select + DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00", + GDB when "01", + IB when "10", + RR(7 downto 0) when others; + + RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2); + RAB <= A(12 downto 0) when CntD5(2) = '1' else + std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3)); + + u_8080: T8080se + generic map ( + Mode => 2, + T2Write => 1) + port map ( + RESET_n => Rst_n, + CLK => Clk, + CLKEN => ClkEnCnt(2), + READY => Ready_i, + HOLD => Hold, + INT => Int_i, + INTE => IntE_i, + DBIN => DBin, + SYNC => Sync, + VAIT => Vait, + HLDA => HLDA, + WR_n => Wr_n, + A => A, + DI => DI, + DO => DO); + + -- Clock enables + process (Rst_n, Clk) + begin + if Rst_n = '0' then + ClkEnCnt <= "000"; + VidEn <= '0'; + elsif Clk'event and Clk = '1' then + VidEn <= not VidEn; + if ClkEnCnt = 4 then + ClkEnCnt <= "000"; + else + ClkEnCnt <= ClkEnCnt + 1; + end if; + end if; + end process; + + -- Glue + process (Rst_n, Clk) + variable OldASEL : std_logic; + begin + if Rst_n = '0' then + Status_i <= (others => '0'); + IntTrigOld <= '0'; + Int_i <= '0'; + OldASEL := '0'; + Ready_i <= '0'; + RR <= (others => '0'); + elsif Clk'event and Clk = '1' then + -- E3 + -- Interrupt + IntTrigOld <= IntTrig; + if Status_i(0) = '1' then + Int_i <= '0'; + elsif IntTrigOld = '0' and IntTrig = '1' then + Int_i <= IntE_i; + end if; + + -- D7 + -- Status register + if Sync = '1' then + Status_i <= DO; + end if; + + -- A3, C3, E3 + -- RAM register/ready logic + if Sync = '1' and A(13) = '1' then + Ready_i <= '0'; + elsif Ready_i = '1' then + Ready_i <= '1'; + else + Ready_i <= RR(9); + end if; + if Sync = '1' and A(13) = '1' then + RR <= (others => '0'); + elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge + (CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge + RR(7 downto 0) <= RDB; + RR(8) <= '1'; + RR(9) <= RR(8); + end if; + OldASEL := CntD5(2); + end if; + end process; + + -- Video counters + process (Rst_n, Clk) + begin + if Rst_n = '0' then + CntD5 <= (others => '0'); + CntE5 <= (others => '0'); + CntE6 <= (others => '0'); + CntE7 <= (others => '0'); + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + CntD5 <= CntD5 + 1; + if CntD5 = 15 then + + CntE5 <= CntE5 + 1; + if CntE5(3 downto 0) = 15 then + if CntE5(4) = '0' then + CntE5 <= "11100"; + + CntE6 <= CntE6 + 1; + if CntE6 = 15 then + + CntE7 <= CntE7 + 1; + if CntE7(3 downto 0) = 15 then + if CntE7(4) = '0' then + CntE6 <= "1010"; + CntE7 <= "11101"; + else + CntE7 <= "00010"; + end if; + end if; + end if; + end if; + else + end if; + end if; + end if; + end if; + end process; + + -- Video shift register + process (Rst_n, Clk) + begin + if Rst_n = '0' then + Shift <= (others => '0'); + Video <= '0'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then + Shift(7 downto 0) <= RDB(7 downto 0); + else + Shift(6 downto 0) <= Shift(7 downto 1); + Shift(7) <= '0'; + end if; + Video <= Shift(0); + end if; + end if; + end process; + + -- Sync + process (Rst_n, Clk) + begin + if Rst_n = '0' then + HSync <= '1'; + VSync <= '1'; + elsif Clk'event and Clk = '1' then + if VidEn = '1' then + if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then + HSync <= '0'; + else + HSync <= '1'; + end if; + if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then + VSync <= '0'; + else + VSync <= '1'; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/osd.v b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.qip b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd new file mode 100644 index 00000000..b1553aeb --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/pll.vhd @@ -0,0 +1,382 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 10, + clk0_phase_shift => "0", + clk1_divide_by => 27, + clk1_duty_cycle => 50, + clk1_multiply_by => 40, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire4, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/scandoubler.v b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/video_mixer.sv b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Midway8080 Hardware/Midway8080v2_Mist/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.qpf b/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.qpf new file mode 100644 index 00000000..351dc40a --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Alibaba" diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.qsf b/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.qsf new file mode 100644 index 00000000..c56bc3c2 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Alibaba_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/alibaba.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Alibaba.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Alibaba +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.srf b/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/Alibaba.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/README.txt b/Arcade/Pacman Hardware/Alibaba_MiST/README.txt new file mode 100644 index 00000000..6dda9d12 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Alibaba and 40 thieves for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Alibaba and 40 thieves hardware +-- Copyright (c) Sorgelig +-- Based on Pacman core: Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- TAB : Skip the level +-- SPACE,CTRL : Action +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/Release/Alibaba.rbf b/Arcade/Pacman Hardware/Alibaba_MiST/Release/Alibaba.rbf new file mode 100644 index 00000000..7716df6d Binary files /dev/null and b/Arcade/Pacman Hardware/Alibaba_MiST/Release/Alibaba.rbf differ diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/clean.bat b/Arcade/Pacman Hardware/Alibaba_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv new file mode 100644 index 00000000..2d38460a --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/Alibaba.sv @@ -0,0 +1,196 @@ +//============================================================================ +// Arcade: Alibaba +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Alibaba +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Alibaba;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +wire m_skip = kbjoy[9]; + + +alibabat alibabat +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{1'b0, m_fire, m_coin, m_skip, m_down,m_right,m_left,m_up}), + .in1(~{1'b0, m_start2, m_start1, 5'b00000}), + + .dipsw1(8'b1_1_00_11_01), + .dipsw2(8'b11111111), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..2c141e86 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"33",X"33",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"11",X"11",X"33",X"33",X"77",X"77",X"77",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"77",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"66",X"77",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"77",X"77",X"77",X"66",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"66",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"66",X"66",X"66",X"77",X"77",X"77",X"77",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"33",X"33",X"77",X"77",X"66",X"66",X"66",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"77",X"77",X"33",X"33",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"11",X"11",X"33",X"33",X"77",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"77",X"77",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"11",X"33",X"33",X"77",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"33",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"33",X"33",X"77",X"77",X"77",X"77",X"77",X"33",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"0C",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0C",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"07",X"03", + X"0C",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0C",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"07",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"11",X"11",X"11",X"11",X"FF",X"FF",X"FF",X"FF",X"88",X"88",X"CC",X"EE",X"FF",X"FF",X"77",X"11", + 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Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..17522bd2 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..641f10b9 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"C3",X"72",X"06",X"89",X"CD",X"45",X"AB",X"C3",X"B3",X"03",X"66",X"C3",X"FD",X"A6",X"11", + X"C3",X"86",X"06",X"AB",X"27",X"65",X"22",X"A7",X"C3",X"10",X"1A",X"01",X"22",X"A9",X"32",X"66", + X"C3",X"CF",X"24",X"9A",X"26",X"95",X"00",X"21",X"C3",X"2D",X"2D",X"99",X"67",X"ED",X"C9",X"6A", + X"C3",X"68",X"00",X"56",X"21",X"B7",X"23",X"10",X"C3",X"1C",X"8E",X"56",X"5E",X"DB",X"12",X"00", + X"36",X"02",X"C3",X"33",X"2D",X"03",X"01",X"01",X"00",X"02",X"00",X"04",X"01",X"02",X"01",X"03", + X"00",X"04",X"01",X"03",X"02",X"04",X"01",X"04",X"02",X"03",X"02",X"05",X"01",X"05",X"00",X"03", + X"02",X"06",X"02",X"05",X"01",X"C3",X"2D",X"20",X"11",X"90",X"4C",X"06",X"10",X"1A",X"A7",X"20", + X"0A",X"E1",X"06",X"03",X"7E",X"12",X"23",X"1C",X"10",X"FA",X"E9",X"1C",X"1C",X"1C",X"10",X"ED", + X"C9",X"CA",X"C3",X"1D",X"3A",X"00",X"4E",X"FE",X"03",X"CA",X"25",X"1E",X"C3",X"C3",X"1D",X"03", + X"03",X"03",X"02",X"05",X"02",X"03",X"03",X"06",X"02",X"05",X"02",X"03",X"03",X"06",X"02",X"05", + X"00",X"03",X"04",X"07",X"02",X"05",X"01",X"03",X"04",X"03",X"02",X"05",X"02",X"03",X"04",X"06", + X"02",X"05",X"02",X"03",X"05",X"07",X"02",X"05",X"00",X"03",X"05",X"07",X"02",X"05",X"02",X"03", + X"05",X"05",X"02",X"05",X"01",X"03",X"06",X"07",X"02",X"05",X"02",X"03",X"06",X"07",X"02",X"05", + X"02",X"03",X"06",X"08",X"02",X"05",X"02",X"03",X"06",X"A7",X"66",X"12",X"99",X"6E",X"4C",X"19", + X"4A",X"89",X"CE",X"6E",X"AA",X"9A",X"A6",X"06",X"04",X"11",X"FC",X"4D",X"21",X"22",X"4C",X"1A", + X"A7",X"CA",X"13",X"01",X"D5",X"5F",X"16",X"00",X"19",X"3A",X"C0",X"4D",X"A7",X"3E",X"00",X"20", + X"02",X"3E",X"04",X"4F",X"CD",X"25",X"01",X"79",X"0E",X"03",X"28",X"01",X"81",X"77",X"23",X"3E", + X"01",X"77",X"D1",X"13",X"05",X"C2",X"EC",X"00",X"C3",X"AD",X"8E",X"21",X"50",X"1D",X"3E",X"01", + X"32",X"1F",X"4E",X"C9",X"00",X"C5",X"3A",X"72",X"4E",X"4F",X"3A",X"09",X"4E",X"A1",X"C1",X"C9", + X"20",X"04",X"3E",X"00",X"18",X"02",X"3E",X"04",X"77",X"23",X"3E",X"01",X"77",X"D1",X"13",X"05", + X"20",X"DE",X"3A",X"E4",X"4D",X"FE",X"01",X"28",X"03",X"CD",X"9E",X"84",X"C3",X"76",X"01",X"4C", + X"32",X"29",X"4C",X"C3",X"76",X"01",X"07",X"02",X"05",X"02",X"03",X"07",X"08",X"02",X"05",X"02", + X"03",X"07",X"08",X"02",X"06",X"02",X"03",X"07",X"08",X"02",X"95",X"69",X"48",X"01",X"89",X"06", + X"84",X"05",X"C9",X"45",X"49",X"0D",X"21",X"22",X"4C",X"11",X"F2",X"4E",X"01",X"0C",X"00",X"ED", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..407b9403 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,662 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 10239) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"03",X"04",X"02",X"01",X"03",X"02",X"04",X"02",X"03",X"04",X"01",X"01",X"02",X"04",X"03", + X"02",X"03",X"01",X"04",X"03",X"02",X"04",X"01",X"01",X"01",X"03",X"04",X"02",X"01",X"04",X"03", + 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X"2A",X"82",X"4C",X"7E",X"A7",X"FA",X"80",X"A7",X"36",X"FF",X"2C",X"46",X"36",X"FF",X"2C",X"20", + X"02",X"2E",X"C0",X"22",X"82",X"4C",X"21",X"80",X"A7",X"E5",X"E7",X"ED",X"23",X"D7",X"24",X"19", + X"24",X"48",X"24",X"64",X"25",X"8B",X"26",X"0D",X"24",X"98",X"26",X"30",X"27",X"6C",X"27",X"A9", + X"27",X"F1",X"27",X"3B",X"28",X"65",X"28",X"8F",X"28",X"B9",X"28",X"30",X"02",X"A2",X"26",X"C9", + X"24",X"35",X"2A",X"D0",X"26",X"87",X"24",X"E8",X"23",X"E0",X"A4",X"E0",X"2A",X"5A",X"2A",X"6A", + X"2B",X"EA",X"2B",X"5E",X"2C",X"A1",X"2B",X"75",X"26",X"B2",X"26",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd new file mode 100644 index 00000000..eeabd401 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/alibaba.vhd @@ -0,0 +1,506 @@ +-- +-- A simulation model of Alibaba and 40 thieves hardware +-- Copyright (c) Sorgelig - 2017 +-- +-- Based on Pacman core +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ALIBABAt is + generic( + eight_sprites : boolean := false + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of ALIBABAt is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal mcnt : std_logic_vector(7 downto 0); + signal mcnt2 : std_logic_vector(10 downto 0); + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + signal control2_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_we : std_logic; + signal ram2_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal ram2_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_out2_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + signal iodec_myst1_l : std_logic; + signal iodec_myst2_l : std_logic; + + signal old_rd_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control2_reg(2) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 0) = X"5000" else '1'; +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 3) = X"500"&'0' else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"504" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"505" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"506" else '1'; +iodec_out2_l<= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 3) = X"50C"&'0' else '1'; + +-- READ +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '1'; +iodec_myst1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 0) = X"50C0" else '1'; +iodec_myst2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 0) = X"50C1" else '1'; + + +p_mcnt : process +begin + wait until rising_edge(clk); + mcnt <= (mcnt + "1") + ("0000000" & (in0(3) xor in0(2) xor in0(1) xor in0(0))); +end process; + +p_mcnt2 : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + old_rd_l <= cpu_rd_l; + if iodec_myst2_l = '0' and old_rd_l = '1' and cpu_rd_l = '0' then + mcnt2 <= mcnt2 + "1"; + end if; + end if; +end process; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +p2_control_reg : process +begin + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control2_reg <= (others => '0'); + elsif (iodec_out2_l = '0') then + control2_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + ram_data when ram_cs = '1' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + ram2_data when ram2_cs = '1' else -- RAM at 9000 - 9fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - Bfff + "0000" & mcnt(3 downto 0) when iodec_myst1_l = '0' else + "0000000" & mcnt2(10) when iodec_myst2_l = '0' else + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + X"BF"; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; +ram2_cs <= '1' when cpu_addr(15 downto 12) = X"9" else '0'; +ram_we <= '1' when cpu_wr_l = '0' and cpu_mreq_l = '0' and cpu_rfsh_l = '1' else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => ram_we and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +u_ram2 : work.dpram generic map (10,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => ram_we and ram2_cs, + address_a => cpu_addr(9 downto 0), + data_a => cpu_data_out, + q_a => ram2_data, + + clock_b => clk, + address_b => cpu_addr(9 downto 0) +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control2_reg(1) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control2_reg(1) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"EF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control2_reg(1), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(3 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control2_reg(0), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/build_id.v new file mode 100644 index 00000000..4238f6e6 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "204319" diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..d74e70a3 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector( 3 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB; + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pll.v b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Alibaba_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Alibaba_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf b/Arcade/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf new file mode 100644 index 00000000..6afe5bca --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "CrushRoller" diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf b/Arcade/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf new file mode 100644 index 00000000..3fa9c38c --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/CrushRoller.qsf @@ -0,0 +1,165 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:14:41 November 10, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CrushRoller_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY CrushRoller +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------- +# start ENTITY(MrTNT) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(MrTNT) +# ----------------- +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/CrushRoller.sv +set_global_assignment -name VERILOG_FILE rtl/build_id.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/README.txt b/Arcade/Pacman Hardware/Crush_Roller_MiST/README.txt new file mode 100644 index 00000000..c94994e5 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Crush Roller port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/Release/CrushRoller.rbf b/Arcade/Pacman Hardware/Crush_Roller_MiST/Release/CrushRoller.rbf new file mode 100644 index 00000000..ca2cea70 Binary files /dev/null and b/Arcade/Pacman Hardware/Crush_Roller_MiST/Release/CrushRoller.rbf differ diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/clean.bat b/Arcade/Pacman Hardware/Crush_Roller_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv new file mode 100644 index 00000000..9a9d0e7d --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/CrushRoller.sv @@ -0,0 +1,192 @@ +//============================================================================ +// Arcade: CrushRoller +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module CrushRoller +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Cr. Roller;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(reset), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [15:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire rde, rhs, rvs; +wire [2:0] r,g,rr,rg; +wire [1:0] b,rb; +wire reset = status[0] | status[6] | buttons[1]; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(~reset), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +pacman CrushRoller +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + .dipsw_reg(8'b00_0_1_11_01), + + .RESET(reset), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(~reset), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..d42caf3a --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"CC",X"22",X"22",X"66",X"CC",X"88",X"00",X"33",X"77",X"CC",X"88",X"88",X"77",X"33",X"00", + X"22",X"22",X"EE",X"EE",X"22",X"22",X"00",X"00",X"00",X"00",X"FF",X"FF",X"44",X"00",X"00",X"00", + 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X"C8",X"C8",X"80",X"80",X"00",X"00",X"00",X"00",X"31",X"31",X"10",X"10",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"F7",X"73",X"F6",X"E0",X"FF",X"FF",X"FF",X"FF",X"FC",X"C8",X"80",X"00", + X"00",X"00",X"00",X"00",X"80",X"80",X"C8",X"EC",X"00",X"00",X"00",X"10",X"10",X"21",X"21",X"73", + X"00",X"70",X"F7",X"FF",X"FF",X"3F",X"B7",X"FF",X"00",X"00",X"C0",X"FC",X"FF",X"FF",X"FF",X"FF", + X"EC",X"FE",X"FA",X"B0",X"10",X"00",X"00",X"00",X"73",X"21",X"21",X"10",X"10",X"00",X"00",X"00", + X"FF",X"B7",X"3F",X"FF",X"FF",X"F7",X"70",X"00",X"FF",X"FF",X"FF",X"FF",X"FC",X"C0",X"00",X"00", + X"F0",X"F0",X"F0",X"78",X"3C",X"1E",X"1E",X"1E",X"F0",X"F0",X"F0",X"E1",X"C3",X"87",X"87",X"87", + X"F0",X"E1",X"87",X"0F",X"0F",X"2D",X"0F",X"0F",X"F0",X"78",X"1E",X"0F",X"0F",X"B4",X"0F",X"0F", + X"3C",X"3C",X"78",X"78",X"F0",X"F0",X"F0",X"F0",X"C3",X"C3",X"E1",X"E1",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"C3",X"87",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"3C",X"78",X"F0", + X"F0",X"F0",X"F0",X"F0",X"78",X"78",X"3C",X"1E",X"F0",X"F0",X"F0",X"E1",X"E1",X"C3",X"C3",X"87", + X"F0",X"87",X"0F",X"0F",X"0F",X"0F",X"4B",X"0F",X"F0",X"F0",X"3C",X"0F",X"0F",X"0F",X"0F",X"0F", + X"1E",X"1E",X"5A",X"78",X"F0",X"F0",X"F0",X"F0",X"87",X"C3",X"C3",X"E1",X"E1",X"F0",X"F0",X"F0", + X"0F",X"4B",X"0F",X"0F",X"0F",X"0F",X"87",X"F0",X"0F",X"0F",X"0F",X"0F",X"0F",X"3C",X"F0",X"F0", + X"80",X"48",X"2C",X"1E",X"1E",X"1E",X"E5",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"10",X"21",X"43",X"43",X"63",X"F7",X"F7",X"F0",X"0F",X"0F",X"0F",X"0F",X"8F",X"AF",X"EF", + X"FE",X"EC",X"EC",X"C8",X"80",X"00",X"00",X"00",X"10",X"31",X"F3",X"72",X"F1",X"10",X"30",X"10", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FD",X"F9",X"A0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"E8",X"80", + X"00",X"00",X"80",X"48",X"48",X"48",X"EC",X"EC",X"00",X"00",X"00",X"10",X"10",X"10",X"00",X"00", + X"30",X"43",X"87",X"0F",X"0F",X"2F",X"F7",X"F7",X"E0",X"1E",X"0F",X"0F",X"0F",X"9F",X"AF",X"FF", + X"FE",X"EC",X"EC",X"C8",X"80",X"C8",X"80",X"40",X"10",X"31",X"73",X"72",X"B1",X"10",X"31",X"10", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FD",X"F9",X"90",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F5",X"50", + X"00",X"00",X"00",X"80",X"C8",X"EC",X"EC",X"FE",X"10",X"21",X"43",X"87",X"87",X"87",X"87",X"87", + X"F0",X"1F",X"3F",X"1F",X"0F",X"3F",X"1F",X"7F",X"80",X"E8",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FE",X"F9",X"FD",X"FE",X"FA",X"F5",X"C8",X"C8",X"43",X"21",X"10",X"00",X"00",X"00",X"00",X"00", + X"3F",X"7F",X"F3",X"30",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"F6",X"73",X"30",X"31", + X"00",X"00",X"50",X"E4",X"FE",X"EC",X"FE",X"EC",X"00",X"00",X"10",X"21",X"43",X"87",X"87",X"87", + X"00",X"30",X"F3",X"3F",X"5F",X"3F",X"1F",X"7F",X"80",X"E8",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FE",X"E8",X"EC",X"FE",X"FA",X"A0",X"00",X"80",X"87",X"87",X"43",X"21",X"10",X"00",X"00",X"00", + X"3F",X"7F",X"3F",X"3C",X"C0",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"F6",X"73",X"30",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..dd5ebf26 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"0F",X"0B",X"03",X"00",X"0F",X"0B",X"0F", + X"00",X"0F",X"0B",X"07",X"00",X"0F",X"0B",X"05",X"00",X"0F",X"0B",X"0C",X"00",X"0F",X"0B",X"09", + X"00",X"05",X"0B",X"07",X"00",X"0B",X"01",X"09",X"00",X"05",X"0B",X"01",X"00",X"02",X"05",X"01", + X"00",X"02",X"0B",X"01",X"00",X"05",X"0B",X"09",X"00",X"0C",X"01",X"07",X"00",X"01",X"0C",X"0F", + X"00",X"0F",X"00",X"0B",X"00",X"0C",X"05",X"0F",X"00",X"0F",X"0B",X"0E",X"00",X"0F",X"0B",X"0D", + X"00",X"01",X"09",X"0F",X"00",X"09",X"0C",X"09",X"00",X"09",X"05",X"0F",X"00",X"05",X"0C",X"0F", + X"00",X"01",X"07",X"0B",X"00",X"0F",X"0B",X"00",X"00",X"0F",X"00",X"0B",X"00",X"0B",X"05",X"09", + X"00",X"0B",X"0C",X"02",X"00",X"0B",X"07",X"09",X"00",X"02",X"0B",X"00",X"00",X"02",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"0F",X"0B",X"03",X"00",X"0F",X"0B",X"0F", + X"00",X"0F",X"0B",X"07",X"00",X"0F",X"0B",X"05",X"00",X"0F",X"0B",X"0C",X"00",X"0F",X"0B",X"09", + X"00",X"05",X"0B",X"07",X"00",X"0B",X"01",X"09",X"00",X"05",X"0B",X"01",X"00",X"02",X"05",X"01", + X"00",X"02",X"0B",X"01",X"00",X"05",X"0B",X"09",X"00",X"0C",X"01",X"07",X"00",X"01",X"0C",X"0F", + X"00",X"0F",X"00",X"0B",X"00",X"0C",X"05",X"0F",X"00",X"0F",X"0B",X"0E",X"00",X"0F",X"0B",X"0D", + X"00",X"01",X"09",X"0F",X"00",X"09",X"0C",X"09",X"00",X"09",X"05",X"0F",X"00",X"05",X"0C",X"0F", + X"00",X"01",X"07",X"0B",X"00",X"0F",X"0B",X"00",X"00",X"0F",X"00",X"0B",X"00",X"0B",X"05",X"09", + X"00",X"0B",X"0C",X"0F",X"00",X"0B",X"07",X"09",X"00",X"02",X"0B",X"00",X"00",X"02",X"0B",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..75dfdaa1 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"23",X"31",X"B0",X"4F",X"ED",X"56",X"18",X"79",X"A0",X"C3",X"06",X"A0",X"C3",X"09",X"A0",X"C3", + X"0F",X"0F",X"0F",X"0F",X"C9",X"C3",X"12",X"A0",X"E1",X"D1",X"C1",X"00",X"00",X"C7",X"C3",X"1E", + X"A0",X"00",X"00",X"00",X"00",X"32",X"3C",X"00",X"00",X"10",X"48",X"00",X"00",X"00",X"00",X"03", + X"E1",X"22",X"5A",X"4C",X"C9",X"00",X"00",X"18",X"F5",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5", + X"D9",X"C5",X"D5",X"E5",X"08",X"F5",X"21",X"00",X"50",X"36",X"00",X"32",X"C0",X"50",X"2E",X"07", + X"36",X"01",X"CD",X"D2",X"0B",X"CD",X"DD",X"2B",X"CD",X"D6",X"13",X"CD",X"F7",X"2D",X"CD",X"00", + X"28",X"CD",X"0D",X"32",X"CD",X"50",X"10",X"3E",X"FF",X"32",X"22",X"4C",X"21",X"00",X"50",X"36", + X"01",X"F1",X"08",X"E1",X"D1",X"C1",X"D9",X"FD",X"E1",X"DD",X"E1",X"E1",X"D1",X"C1",X"F1",X"FB", + X"C9",X"21",X"07",X"50",X"36",X"00",X"2B",X"7C",X"FE",X"3F",X"32",X"C0",X"50",X"20",X"F5",X"16", + X"00",X"D9",X"21",X"00",X"40",X"36",X"00",X"23",X"7C",X"32",X"C0",X"50",X"FE",X"51",X"20",X"F5", + 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X"C9",X"3C",X"8A",X"20",X"B6",X"3F",X"11",X"00",X"CD",X"80",X"3F",X"F5",X"F3",X"3A",X"00",X"50", + X"CB",X"67",X"32",X"C0",X"50",X"28",X"F6",X"3A",X"00",X"50",X"CB",X"67",X"32",X"C0",X"50",X"20", + X"F6",X"E5",X"21",X"00",X"50",X"36",X"00",X"36",X"01",X"E1",X"F1",X"FB",X"C9",X"3F",X"11",X"00", + X"D2",X"1A",X"F9",X"DA",X"00",X"00",X"11",X"00",X"DC",X"1A",X"B8",X"29",X"BF",X"03",X"DE",X"A4"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..a715bc70 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"23",X"31",X"B0",X"4F",X"ED",X"56",X"18",X"79",X"A0",X"C3",X"06",X"A0",X"C3",X"09",X"A0",X"C3", + X"0F",X"0F",X"0F",X"0F",X"C9",X"C3",X"12",X"A0",X"E1",X"D1",X"C1",X"00",X"00",X"C7",X"C3",X"1E", + X"A0",X"00",X"00",X"00",X"00",X"32",X"3C",X"00",X"00",X"10",X"48",X"00",X"00",X"00",X"00",X"03", + X"E1",X"22",X"5A",X"4C",X"C9",X"00",X"00",X"18",X"F5",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5", + X"D9",X"C5",X"D5",X"E5",X"08",X"F5",X"21",X"00",X"50",X"36",X"00",X"32",X"C0",X"50",X"2E",X"07", + X"36",X"01",X"CD",X"D2",X"0B",X"CD",X"DD",X"2B",X"CD",X"D6",X"13",X"CD",X"F7",X"2D",X"CD",X"00", + X"28",X"CD",X"0D",X"32",X"CD",X"50",X"10",X"3E",X"FF",X"32",X"22",X"4C",X"21",X"00",X"50",X"36", + X"01",X"F1",X"08",X"E1",X"D1",X"C1",X"D9",X"FD",X"E1",X"DD",X"E1",X"E1",X"D1",X"C1",X"F1",X"FB", + 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-0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/build_id.v new file mode 100644 index 00000000..2f3e03f0 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "062742" diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..70300d20 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman.vhd @@ -0,0 +1,629 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data_out : std_logic_vector(7 downto 0); + signal rom_data : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + rom_data <= program_rom_dinl when cpu_addr(15) = '0' else program_rom_dinh; + rom_data_out <= rom_data(7 downto 6) & rom_data(3) & rom_data(4) & rom_data(5) & rom_data(2 downto 0) when MRTNT = '1' else rom_data; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data_out, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data_out; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data_out; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..895304e9 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_video.vhd @@ -0,0 +1,366 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Crush_Roller_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf b/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf new file mode 100644 index 00000000..23aa7cc2 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "DreamShopper" diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf b/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf new file mode 100644 index 00000000..e9246feb --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.qsf @@ -0,0 +1,128 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY DreamShopper +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dreamshp_video.vhd +set_global_assignment -name VHDL_FILE rtl/dreamshp.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/DreamShopper.sv +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.srf b/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/DreamShopper.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/README.txt b/Arcade/Pacman Hardware/DreamShopper_MiST/README.txt new file mode 100644 index 00000000..208f5ec6 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Dream Shopper for MiST by Gehstock +-- 20 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Dream Shopper hardware +-- Copyright (c) Sorgelig +-- Based on Pacman core: Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE,CTRL : Action +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/Release/DreamShopper.rbf b/Arcade/Pacman Hardware/DreamShopper_MiST/Release/DreamShopper.rbf new file mode 100644 index 00000000..da38814d Binary files /dev/null and b/Arcade/Pacman Hardware/DreamShopper_MiST/Release/DreamShopper.rbf differ diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/clean.bat b/Arcade/Pacman Hardware/DreamShopper_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv new file mode 100644 index 00000000..fc7b983f --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/DreamShopper.sv @@ -0,0 +1,204 @@ +//============================================================================ +// Arcade: Dream Shopper +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module DreamShopper +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "DreamShopper;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +reg ce_1m79; +always @(posedge clk_sys) begin + reg [3:0] div; + + div <= div + 1'd1; + if(div == 12) div <= 0; + ce_1m79 <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire m_Serv = kbjoy[9]; + +dreamshp dreamshp +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{2'b00, m_coin, m_fire, m_down,m_right,m_left,m_up}), + .in1(~{1'b0, m_start2, m_start1, 5'b00000}), + + .dipsw1(8'b11_00_10_0_1), + .dipsw2(8'b00000000), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m), + .ENA_1M79(ce_1m79) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..86fc9730 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"F0",X"F0",X"87",X"3C",X"4B",X"0F",X"0F",X"00",X"70",X"70",X"70",X"70",X"61",X"61",X"61", + X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"F0",X"F0",X"78",X"3C",X"1E",X"1E",X"1E", + X"0F",X"0F",X"0F",X"0F",X"87",X"F0",X"F0",X"00",X"61",X"61",X"61",X"70",X"70",X"70",X"70",X"00", + X"68",X"2C",X"A4",X"E4",X"E8",X"E0",X"E0",X"00",X"0F",X"1E",X"1E",X"3C",X"78",X"F2",X"F0",X"00", + X"00",X"F0",X"F0",X"87",X"3C",X"4B",X"0F",X"0F",X"00",X"70",X"70",X"70",X"70",X"61",X"61",X"61", + X"00",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"F0",X"F0",X"78",X"3C",X"1E",X"1E",X"1E", + X"0F",X"0F",X"0F",X"0F",X"87",X"F0",X"F0",X"00",X"61",X"61",X"61",X"70",X"70",X"70",X"70",X"00", + X"68",X"2C",X"A4",X"E4",X"E0",X"E4",X"E0",X"00",X"0F",X"1E",X"1E",X"3C",X"79",X"F0",X"F0",X"00", + X"00",X"20",X"11",X"00",X"99",X"CB",X"BC",X"71",X"00",X"00",X"00",X"11",X"00",X"10",X"00",X"00", + X"00",X"00",X"00",X"00",X"44",X"88",X"00",X"00",X"00",X"00",X"00",X"88",X"58",X"87",X"79",X"2C", + X"BC",X"0F",X"5B",X"20",X"00",X"00",X"00",X"00",X"00",X"10",X"11",X"22",X"00",X"10",X"00",X"00", + X"00",X"80",X"44",X"00",X"00",X"00",X"00",X"00",X"E9",X"96",X"E2",X"0C",X"80",X"40",X"00",X"00", + X"00",X"01",X"32",X"91",X"4B",X"CC",X"ED",X"4C",X"00",X"00",X"12",X"10",X"33",X"01",X"00",X"01", + X"00",X"00",X"A8",X"4C",X"08",X"00",X"00",X"00",X"00",X"00",X"80",X"0D",X"69",X"F2",X"CF",X"8E", + X"C1",X"DC",X"AD",X"0F",X"B2",X"01",X"00",X"00",X"01",X"12",X"11",X"32",X"01",X"50",X"00",X"00", + X"00",X"08",X"48",X"08",X"88",X"04",X"00",X"00",X"52",X"FC",X"67",X"96",X"3A",X"11",X"00",X"00", + X"11",X"20",X"C0",X"A6",X"6E",X"7B",X"2C",X"9C",X"80",X"40",X"02",X"21",X"10",X"25",X"21",X"30", + X"20",X"60",X"0E",X"C0",X"40",X"00",X"00",X"10",X"00",X"00",X"14",X"C3",X"A1",X"67",X"62",X"21", + X"0F",X"85",X"5E",X"9D",X"0E",X"C0",X"00",X"80",X"10",X"21",X"71",X"53",X"30",X"81",X"32",X"00", + X"28",X"48",X"C0",X"08",X"40",X"80",X"20",X"10",X"D2",X"07",X"E7",X"ED",X"43",X"C2",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"44",X"CC", + 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X"00",X"00",X"80",X"C8",X"C0",X"86",X"C2",X"E0",X"00",X"00",X"00",X"00",X"10",X"34",X"38",X"78", + X"00",X"00",X"00",X"1E",X"96",X"C3",X"C3",X"C3",X"00",X"01",X"50",X"F0",X"F0",X"F0",X"F0",X"F0", + X"E0",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"78",X"78",X"78",X"30",X"30",X"10",X"10",X"00", + X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"F8",X"F0",X"F0",X"F0",X"F0",X"B0",X"07",X"04", + X"08",X"C0",X"E4",X"E0",X"C3",X"E1",X"F0",X"F0",X"00",X"00",X"00",X"00",X"04",X"09",X"38",X"78", + X"00",X"00",X"00",X"10",X"1E",X"0F",X"87",X"87",X"00",X"20",X"70",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"78",X"78",X"70",X"70",X"30",X"30",X"10",X"00", + X"D2",X"F0",X"F0",X"F0",X"F0",X"F0",X"E0",X"00",X"F8",X"78",X"78",X"34",X"B4",X"30",X"00",X"00", + X"00",X"08",X"C0",X"E4",X"E0",X"C3",X"E1",X"F0",X"00",X"00",X"00",X"01",X"10",X"30",X"30",X"30", + X"00",X"00",X"07",X"3C",X"F0",X"F0",X"F0",X"E1",X"00",X"00",X"20",X"70",X"78",X"78",X"3C",X"3C", + X"78",X"F8",X"E0",X"E0",X"E0",X"40",X"00",X"00",X"30",X"30",X"30",X"30",X"30",X"10",X"00",X"00", + X"F1",X"F1",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"7C",X"E9",X"E1",X"F0",X"F0",X"F0",X"E0",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"77",X"44",X"77",X"00",X"77",X"44",X"00",X"00",X"EE",X"AA",X"EE",X"00",X"EE",X"22", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"77",X"00",X"77",X"44",X"77",X"00",X"00",X"00",X"EE",X"00",X"EE",X"22",X"EE",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..2ec6484a --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0D",X"00",X"00",X"07",X"0D",X"0B",X"0E",X"03",X"0D",X"06",X"00",X"03",X"0D",X"08",X"0D",X"01", + X"0D",X"05",X"03",X"02",X"0D",X"05",X"03",X"05",X"0B",X"07",X"02",X"03",X"0B",X"07",X"05",X"01", + X"0B",X"07",X"05",X"02",X"0B",X"07",X"03",X"05",X"00",X"0D",X"07",X"03",X"0D",X"08",X"03",X"05", + X"07",X"0F",X"07",X"01",X"00",X"03",X"0F",X"07",X"00",X"01",X"03",X"07",X"00",X"0F",X"03",X"07", + X"00",X"05",X"03",X"07",X"00",X"03",X"0F",X"07",X"00",X"05",X"09",X"03",X"00",X"01",X"09",X"03", + X"00",X"0D",X"0A",X"04",X"07",X"0F",X"05",X"08",X"00",X"0C",X"00",X"00",X"0D",X"00",X"00",X"06", + X"00",X"03",X"02",X"07",X"00",X"01",X"0A",X"03",X"00",X"07",X"02",X"0A",X"00",X"08",X"0E",X"03", + X"00",X"0E",X"05",X"01",X"00",X"0E",X"07",X"02",X"00",X"01",X"03",X"07",X"0D",X"01",X"03",X"02", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..622997bc --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"C0",X"38",X"07",X"87",X"3F",X"F0",X"FF",X"27",X"14",X"1C",X"80",X"A4",X"00",X"AE",X"28"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..1a2053b0 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 12287) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"E0",X"4E",X"3A",X"AA",X"49",X"FE",X"03",X"30",X"03",X"3E",X"60",X"FF",X"21",X"45",X"48", + X"06",X"0A",X"CF",X"21",X"00",X"4A",X"06",X"20",X"CF",X"FD",X"21",X"00",X"4A",X"CD",X"A6",X"82", + X"FD",X"21",X"10",X"4A",X"CD",X"A6",X"82",X"29",X"FD",X"75",X"0E",X"FD",X"74",X"0F",X"3E",X"23", + X"06",X"01",X"FF",X"FD",X"21",X"00",X"4A",X"DD",X"21",X"45",X"48",X"CD",X"AB",X"85",X"3A",X"01", + X"48",X"CB",X"47",X"28",X"2E",X"DD",X"E5",X"E1",X"06",X"0A",X"CF",X"3E",X"23",X"06",X"01",X"FF", + X"3A",X"01",X"48",X"CB",X"47",X"20",X"F4",X"11",X"46",X"48",X"21",X"03",X"4A",X"01",X"04",X"00", + X"ED",X"B0",X"11",X"4B",X"48",X"21",X"13",X"4A",X"01",X"04",X"00",X"ED",X"B0",X"DD",X"36",X"00", + X"01",X"18",X"BB",X"C5",X"FD",X"7E",X"00",X"E6",X"0F",X"21",X"8C",X"80",X"E5",X"DF",X"B1",X"80", + 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X"10",X"01",X"05",X"05",X"C5",X"E5",X"C5",X"E5",X"3E",X"88",X"01",X"02",X"02",X"CD",X"5C",X"90", + X"E1",X"23",X"23",X"C1",X"10",X"F0",X"E1",X"01",X"40",X"00",X"09",X"C1",X"0D",X"C2",X"84",X"AD", + X"C3",X"BF",X"AD",X"FD",X"7E",X"06",X"CB",X"BF",X"B7",X"28",X"04",X"FD",X"35",X"06",X"C9",X"3E", + X"04",X"FD",X"B6",X"06",X"CB",X"7F",X"CB",X"FF",X"28",X"02",X"CB",X"BF",X"FD",X"77",X"06",X"FD", + X"66",X"01",X"FD",X"6E",X"02",X"CD",X"1E",X"92",X"3E",X"01",X"FD",X"CB",X"06",X"7E",X"28",X"02", + X"3E",X"05",X"01",X"02",X"02",X"1E",X"0A",X"CD",X"5C",X"90",X"C9",X"3A",X"02",X"48",X"CB",X"77", + X"CB",X"F7",X"20",X"0C",X"32",X"02",X"48",X"CB",X"6F",X"20",X"05",X"3E",X"1F",X"CD",X"40",X"03", + X"FD",X"7E",X"06",X"B7",X"28",X"06",X"FD",X"35",X"06",X"C3",X"1A",X"AE",X"FD",X"36",X"06",X"03", + X"FD",X"66",X"01",X"FD",X"6E",X"02",X"CD",X"1E",X"92",X"7E",X"FE",X"11",X"20",X"02",X"3E",X"05", + X"C6",X"04",X"1E",X"0B",X"01",X"02",X"02",X"CD",X"5C",X"90",X"FD",X"7E",X"07",X"B7",X"28",X"04", + X"FD",X"35",X"07",X"C9",X"FD",X"36",X"07",X"03",X"FD",X"66",X"01",X"FD",X"6E",X"02",X"CD",X"1E", + X"92",X"E5",X"E5",X"FD",X"7E",X"08",X"3D",X"CB",X"7F",X"28",X"02",X"3E",X"03",X"CD",X"56",X"AF", + X"E1",X"19",X"3E",X"05",X"CD",X"BC",X"AF",X"FD",X"7E",X"08",X"CD",X"56",X"AF",X"E1",X"19",X"3E", + X"02",X"CD",X"BC",X"AF",X"FD",X"7E",X"08",X"3C",X"FD",X"77",X"08",X"FE",X"04",X"D8",X"FD",X"36", + X"08",X"00",X"FD",X"34",X"09",X"3E",X"04",X"FD",X"BE",X"09",X"C0",X"FD",X"E5",X"FD",X"66",X"01", + X"FD",X"6E",X"02",X"CD",X"AC",X"91",X"36",X"20",X"FD",X"66",X"03",X"FD",X"6E",X"04",X"E5",X"CD", + X"AC",X"91",X"E5",X"FD",X"E1",X"E1",X"CD",X"1E",X"92",X"E5",X"DD",X"E1",X"01",X"05",X"05",X"C5", + X"FD",X"E5",X"DD",X"E5",X"C5",X"DD",X"E5",X"E1",X"CD",X"83",X"26",X"30",X"0C",X"3E",X"88",X"1E", + X"03",X"01",X"02",X"02",X"CD",X"5C",X"90",X"18",X"24",X"FD",X"CB",X"00",X"9E",X"21",X"0C",X"AF", + X"FD",X"7E",X"00",X"CB",X"7F",X"28",X"03",X"21",X"16",X"AF",X"E6",X"70",X"CB",X"3F",X"CB",X"3F", + X"CB",X"3F",X"CB",X"3F",X"CD",X"1D",X"94",X"EB",X"11",X"CD",X"AE",X"D5",X"E9",X"FD",X"23",X"DD", + X"23",X"DD",X"23",X"C1",X"10",X"BE",X"DD",X"E1",X"11",X"40",X"00",X"DD",X"19",X"FD",X"E1",X"11", + X"0C",X"00",X"FD",X"19",X"C1",X"0D",X"20",X"A7",X"FD",X"E1",X"FD",X"E5",X"E1",X"06",X"0A",X"CF", + X"FD",X"E5",X"FD",X"21",X"A0",X"4A",X"06",X"03",X"FD",X"7E",X"00",X"B7",X"20",X"0B",X"FD",X"23", + X"10",X"F6",X"21",X"02",X"48",X"CB",X"76",X"CB",X"B6",X"FD",X"E1",X"C9",X"20",X"AF",X"20",X"AF", + X"34",X"AF",X"B6",X"2D",X"27",X"AF",X"44",X"AF",X"44",X"AF",X"34",X"AF",X"44",X"AF",X"34",X"AF", + X"3A",X"01",X"48",X"CB",X"57",X"20",X"13",X"DD",X"E5",X"E1",X"AF",X"1E",X"16",X"01",X"02",X"02", + X"CD",X"4A",X"90",X"C9",X"1E",X"14",X"3E",X"88",X"18",X"12",X"FD",X"7E",X"00",X"E6",X"07",X"CD", + X"76",X"95",X"18",X"08",X"FD",X"7E",X"00",X"E6",X"07",X"CD",X"87",X"95",X"DD",X"E5",X"E1",X"01", + X"02",X"02",X"CD",X"5C",X"90",X"C9",X"21",X"62",X"AF",X"CD",X"0B",X"94",X"46",X"23",X"5E",X"23", + X"56",X"C9",X"04",X"DF",X"FF",X"06",X"BE",X"FF",X"08",X"9D",X"FF",X"0A",X"7C",X"FF",X"3E",X"18", + X"CD",X"40",X"03",X"FD",X"21",X"A0",X"4A",X"06",X"03",X"C5",X"FD",X"7E",X"00",X"B7",X"20",X"33", + X"FD",X"34",X"00",X"FD",X"74",X"01",X"FD",X"75",X"02",X"3E",X"40",X"FD",X"77",X"05",X"01",X"E0", + X"20",X"CD",X"A5",X"91",X"FD",X"74",X"03",X"FD",X"75",X"04",X"CD",X"AC",X"91",X"01",X"05",X"05", + X"C5",X"E5",X"CB",X"DE",X"23",X"10",X"FB",X"E1",X"01",X"0C",X"00",X"09",X"C1",X"0D",X"C2",X"A0", + X"AF",X"C1",X"C9",X"01",X"0A",X"00",X"FD",X"09",X"C1",X"10",X"BE",X"C9",X"C5",X"CD",X"E6",X"AF", + X"23",X"10",X"FA",X"2B",X"C1",X"C5",X"11",X"20",X"00",X"CD",X"E6",X"AF",X"19",X"10",X"FA",X"C1", + X"C5",X"B7",X"ED",X"52",X"CD",X"E6",X"AF",X"2B",X"10",X"FA",X"C1",X"23",X"11",X"E0",X"FF",X"CD", + X"E6",X"AF",X"19",X"10",X"FA",X"C9",X"36",X"1F",X"CB",X"D4",X"77",X"CB",X"94",X"C9",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/build_id.v new file mode 100644 index 00000000..6953fec4 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "164851" diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd new file mode 100644 index 00000000..31e82bb2 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp.vhd @@ -0,0 +1,477 @@ +-- +-- A simulation model of Dream Shopper hardware +-- Copyright (c) Sorgelig - 2017 +-- +-- Based on Pacman core +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity DREAMSHP is + generic( + eight_sprites : boolean := true + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(9 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic; + ENA_1M79 : in std_logic + ); +end; + +architecture RTL of DREAMSHP is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_nmi_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_nmi_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_nmi_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => '1', + NMI_n => cpu_nmi_l, + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- spr_l 0x5040 - 0x507F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - bfff + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.DREAMSHP_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +sn_we <= '1' when cpu_wr_l = '0' and cpu_iorq_l = '0' and cpu_addr(7 downto 1) = "0000011" else '0'; + +sn : ym2149 +port map +( + CLK => clk, + CE => ENA_1M79, + RESET => reset, + BDIR => sn_we, + BC => cpu_addr(0), + DI => cpu_data_out, + DO => open, + CHANNEL_A=> wav1, + CHANNEL_B=> wav2, + CHANNEL_C=> wav3, + + SEL => '0', + MODE => '0', + IOA_in => (others => '0'), + IOA_out => open, + + IOB_in => (others => '0'), + IOB_out => open +); + +O_AUDIO <= ("00" & wav1) + ("00" & wav2) + ("00" & wav3); + +end RTL; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd new file mode 100644 index 00000000..b03047bf --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/dreamshp_video.vhd @@ -0,0 +1,278 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity DREAMSHP_VIDEO is + generic( + alt_transp : boolean := true + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of DREAMSHP_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/osd.v b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/pll.v b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv new file mode 100644 index 00000000..a8b47c46 --- /dev/null +++ b/Arcade/Pacman Hardware/DreamShopper_MiST/rtl/ym2149.sv @@ -0,0 +1,295 @@ + + +module ym2149 +( + input CLK, // Global clock + input CE, // PSG Clock enable + input RESET, // Chip RESET (set all Registers to '0', active hi) + input BDIR, // Bus Direction (0 - read , 1 - write) + input BC, // Bus control + input [7:0] DI, // Data In + output [7:0] DO, // Data Out + output [7:0] CHANNEL_A, // PSG Output channel A + output [7:0] CHANNEL_B, // PSG Output channel B + output [7:0] CHANNEL_C, // PSG Output channel C + + input SEL, + input MODE, + + input [7:0] IOA_in, + output [7:0] IOA_out, + + input [7:0] IOB_in, + output [7:0] IOB_out +); + +assign IOA_out = ymreg[14]; +assign IOB_out = ymreg[15]; + +reg ena_div; +reg ena_div_noise; +reg [3:0] addr; +reg [7:0] ymreg[16]; +reg env_ena; +reg [4:0] env_vol; + +wire [7:0] volTableAy[16] = + '{8'h00, 8'h03, 8'h04, 8'h06, + 8'h0a, 8'h0f, 8'h15, 8'h22, + 8'h28, 8'h41, 8'h5b, 8'h72, + 8'h90, 8'hb5, 8'hd7, 8'hff + }; + +wire [7:0] volTableYm[32] = + '{8'h00, 8'h01, 8'h01, 8'h02, + 8'h02, 8'h03, 8'h03, 8'h04, + 8'h06, 8'h07, 8'h09, 8'h0a, + 8'h0c, 8'h0e, 8'h11, 8'h13, + 8'h17, 8'h1b, 8'h20, 8'h25, + 8'h2c, 8'h35, 8'h3e, 8'h47, + 8'h54, 8'h66, 8'h77, 8'h88, + 8'ha1, 8'hc0, 8'he0, 8'hff + }; + +// Read from AY +assign DO = dout; +reg [7:0] dout; +always_comb begin + case(addr) + 0: dout = ymreg[0]; + 1: dout = {4'b0000, ymreg[1][3:0]}; + 2: dout = ymreg[2]; + 3: dout = {4'b0000, ymreg[3][3:0]}; + 4: dout = ymreg[4]; + 5: dout = {4'b0000, ymreg[5][3:0]}; + 6: dout = {3'b000, ymreg[6][4:0]}; + 7: dout = ymreg[7]; + 8: dout = {3'b000, ymreg[8][4:0]}; + 9: dout = {3'b000, ymreg[9][4:0]}; + 10: dout = {3'b000, ymreg[10][4:0]}; + 11: dout = ymreg[11]; + 12: dout = ymreg[12]; + 13: dout = {4'b0000, ymreg[13][3:0]}; + 14: dout = (ymreg[7][6] ? ymreg[14] : IOA_in); + 15: dout = (ymreg[7][7] ? ymreg[15] : IOB_in); + endcase +end + +// p_divider +always @(posedge CLK) begin + reg [3:0] cnt_div; + reg noise_div; + + if(CE) begin + ena_div <= 0; + ena_div_noise <= 0; + if(!cnt_div) begin + cnt_div <= {SEL, 3'b111}; + ena_div <= 1; + + noise_div <= (~noise_div); + if (noise_div) ena_div_noise <= 1; + end else begin + cnt_div <= cnt_div - 1'b1; + end + end +end + + +reg [16:0] poly17; +wire [4:0] noise_gen_comp = ymreg[6][4:0] ? ymreg[6][4:0] - 1'd1 : 5'd0; + +// p_noise_gen +always @(posedge CLK) begin + reg [4:0] noise_gen_cnt; + + if(CE) begin + if (ena_div_noise) begin + if (noise_gen_cnt >= noise_gen_comp) begin + noise_gen_cnt <= 0; + poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; + end else begin + noise_gen_cnt <= noise_gen_cnt + 1'd1; + end + end + end +end + +wire [11:0] tone_gen_freq[1:3]; +assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; +assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; +assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; + +wire [11:0] tone_gen_comp[1:3]; +assign tone_gen_comp[1] = tone_gen_freq[1] ? tone_gen_freq[1] - 1'd1 : 12'd0; +assign tone_gen_comp[2] = tone_gen_freq[2] ? tone_gen_freq[2] - 1'd1 : 12'd0; +assign tone_gen_comp[3] = tone_gen_freq[3] ? tone_gen_freq[3] - 1'd1 : 12'd0; + +reg [3:1] tone_gen_op; + +//p_tone_gens +always @(posedge CLK) begin + integer i; + reg [11:0] tone_gen_cnt[1:3]; + + if(CE) begin + // looks like real chips count up - we need to get the Exact behaviour .. + + for (i = 1; i <= 3; i = i + 1) begin + if(ena_div) begin + if (tone_gen_cnt[i] >= tone_gen_comp[i]) begin + tone_gen_cnt[i] <= 0; + tone_gen_op[i] <= (~tone_gen_op[i]); + end else begin + tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; + end + end + end + end +end + +wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; + +//p_envelope_freq +always @(posedge CLK) begin + reg [15:0] env_gen_cnt; + + if(CE) begin + env_ena <= 0; + if(ena_div) begin + if (env_gen_cnt >= env_gen_comp) begin + env_gen_cnt <= 0; + env_ena <= 1; + end else begin + env_gen_cnt <= (env_gen_cnt + 1'd1); + end + end + end +end + +wire is_bot = (env_vol == 5'b00000); +wire is_bot_p1 = (env_vol == 5'b00001); +wire is_top_m1 = (env_vol == 5'b11110); +wire is_top = (env_vol == 5'b11111); + +always @(posedge CLK) begin + reg old_BDIR; + reg env_reset; + reg env_hold; + reg env_inc; + + // envelope shapes + // C AtAlH + // 0 0 x x \___ + // + // 0 1 x x /___ + // + // 1 0 0 0 \\\\ + // + // 1 0 0 1 \___ + // + // 1 0 1 0 \/\/ + // ___ + // 1 0 1 1 \ + // + // 1 1 0 0 //// + // ___ + // 1 1 0 1 / + // + // 1 1 1 0 /\/\ + // + // 1 1 1 1 /___ + + if(RESET) begin + ymreg[0] <= 0; + ymreg[1] <= 0; + ymreg[2] <= 0; + ymreg[3] <= 0; + ymreg[4] <= 0; + ymreg[5] <= 0; + ymreg[6] <= 0; + ymreg[7] <= 255; + ymreg[8] <= 0; + ymreg[9] <= 0; + ymreg[10] <= 0; + ymreg[11] <= 0; + ymreg[12] <= 0; + ymreg[13] <= 0; + ymreg[14] <= 0; + ymreg[15] <= 0; + addr <= 0; + env_vol <= 0; + end else begin + old_BDIR <= BDIR; + if(~old_BDIR & BDIR) begin + if(BC) addr <= DI[3:0]; + else begin + ymreg[addr] <= DI; + env_reset <= (addr == 13); + end + end + end + + if(CE) begin + if(env_reset) begin + env_reset <= 0; + // load initial state + if(!ymreg[13][2]) begin // attack + env_vol <= 5'b11111; + env_inc <= 0; // -1 + end else begin + env_vol <= 5'b00000; + env_inc <= 1; // +1 + end + env_hold <= 0; + end else begin + + if (env_ena) begin + if (!env_hold) begin + if (env_inc) env_vol <= (env_vol + 5'b00001); + else env_vol <= (env_vol + 5'b11111); + end + + // envelope shape control. + if(!ymreg[13][3]) begin + if(!env_inc) begin // down + if(is_bot_p1) env_hold <= 1; + end else if (is_top) env_hold <= 1; + end else if(ymreg[13][0]) begin // hold = 1 + if(!env_inc) begin // down + if(ymreg[13][1]) begin // alt + if(is_bot) env_hold <= 1; + end else if(is_bot_p1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alt + if(is_top) env_hold <= 1; + end else if(is_top_m1) env_hold <= 1; + end else if(ymreg[13][1]) begin // alternate + if(env_inc == 1'b0) begin // down + if(is_bot_p1) env_hold <= 1; + if(is_bot) begin + env_hold <= 0; + env_inc <= 1; + end + end else begin + if(is_top_m1) env_hold <= 1; + if(is_top) begin + env_hold <= 0; + env_inc <= 0; + end + end + end + end + end + end +end + +wire [4:0] A = ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | poly17[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}; +wire [4:0] B = ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | poly17[0])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}; +wire [4:0] C = ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | poly17[0])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}; + +assign CHANNEL_A = MODE ? volTableAy[A[4:1]] : volTableYm[A]; +assign CHANNEL_B = MODE ? volTableAy[B[4:1]] : volTableYm[B]; +assign CHANNEL_C = MODE ? volTableAy[C[4:1]] : volTableYm[C]; + + +endmodule diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.qpf b/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.qpf new file mode 100644 index 00000000..0d807731 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Eeekk" diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.qsf b/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.qsf new file mode 100644 index 00000000..9d756332 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Eeekk_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/eeekk.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Eeekk.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Eeekk +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.srf b/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/Eeekk.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/README.txt b/Arcade/Pacman Hardware/Eeekk_MiST/README.txt new file mode 100644 index 00000000..9c4f1cac --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Eeekk! for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE,CTRL : Punch (also starts 2 player mode!) +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/Release/Eeekk.rbf b/Arcade/Pacman Hardware/Eeekk_MiST/Release/Eeekk.rbf new file mode 100644 index 00000000..41ea328a Binary files /dev/null and b/Arcade/Pacman Hardware/Eeekk_MiST/Release/Eeekk.rbf differ diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/clean.bat b/Arcade/Pacman Hardware/Eeekk_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv new file mode 100644 index 00000000..4d1149a1 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/Eeekk.sv @@ -0,0 +1,196 @@ +//============================================================================ +// Arcade: Eeekk! +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Eeekk +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Eeekk;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +assign LED = 1; +//wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +//wire m_skip = kbjoy[9]; + + +eeekkt eeekkt +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1(~{1'b0, m_start2|m_fire, m_start1, 5'b00000}), + + .dipsw1(8'b1_1_1_100_00), + .dipsw2(8'b11111111), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..72d0990f --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"0F",X"0B",X"0E",X"0B",X"0F",X"01",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F", + X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"88",X"88",X"CC",X"FF",X"FF",X"F3",X"F0",X"F0",X"F3",X"F3",X"F1",X"F1",X"F0",X"F0",X"F0",X"F0", + X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"F3",X"F3",X"F3",X"F3",X"F3",X"F3",X"F3",X"F3", + X"00",X"00",X"00",X"FF",X"FF",X"FF",X"F0",X"F0",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"F0",X"F0", + X"F0",X"F0",X"F3",X"FF",X"FF",X"CC",X"88",X"88",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"F3",X"F3", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C", + X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"0C",X"00",X"0E",X"0F",X"0F",X"00",X"0C",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0F", + X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C", + X"FC",X"FC",X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"11",X"11",X"33",X"FF",X"FF",X"FC",X"F0",X"F0", + X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11", + 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X"70",X"50",X"50",X"D0",X"00",X"F0",X"10",X"F0",X"08",X"0F",X"0F",X"08",X"08",X"00",X"00",X"0F", + X"00",X"0E",X"0E",X"02",X"02",X"0E",X"00",X"0C",X"54",X"54",X"54",X"54",X"CC",X"DC",X"DC",X"DC", + X"00",X"C0",X"40",X"F0",X"00",X"50",X"50",X"F0",X"09",X"09",X"0D",X"03",X"08",X"0F",X"0F",X"08", + X"19",X"19",X"19",X"1D",X"33",X"3B",X"3B",X"33",X"CC",X"DC",X"DC",X"DC",X"CC",X"DC",X"DC",X"DC", + X"EF",X"13",X"15",X"19",X"99",X"99",X"99",X"99",X"F7",X"C8",X"A8",X"98",X"99",X"99",X"99",X"99", + X"FF",X"00",X"00",X"FF",X"80",X"40",X"31",X"32",X"FF",X"00",X"00",X"FF",X"01",X"02",X"8C",X"4C", + X"99",X"99",X"99",X"99",X"91",X"51",X"31",X"FE",X"99",X"99",X"99",X"99",X"89",X"8A",X"8C",X"7F", + X"23",X"13",X"04",X"08",X"FF",X"00",X"00",X"FF",X"C4",X"C8",X"20",X"10",X"FF",X"00",X"00",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..8001b50d --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"02",X"02",X"02",X"00",X"0D",X"0D",X"0D", + X"00",X"09",X"0C",X"03",X"00",X"05",X"02",X"0B",X"00",X"02",X"06",X"04",X"00",X"0F",X"0D",X"05", + X"00",X"0D",X"0C",X"06",X"00",X"02",X"0C",X"07",X"00",X"07",X"0F",X"09",X"00",X"01",X"0A",X"0C", + X"00",X"01",X"0A",X"08",X"00",X"08",X"07",X"0E",X"00",X"07",X"0C",X"0A",X"00",X"07",X"0F",X"01", + X"00",X"07",X"03",X"06",X"00",X"05",X"0C",X"0A",X"00",X"0D",X"0E",X"01",X"00",X"02",X"08",X"01", + X"00",X"02",X"06",X"01",X"00",X"05",X"01",X"0A",X"00",X"08",X"06",X"0A",X"00",X"06",X"07",X"04", + X"00",X"06",X"0F",X"01",X"00",X"07",X"0A",X"0F",X"00",X"05",X"07",X"09",X"00",X"0F",X"08",X"05", + X"00",X"02",X"0F",X"01",X"00",X"0F",X"0C",X"08",X"00",X"02",X"0C",X"08",X"00",X"0D",X"0C",X"08", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..9c147a6a --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"AC",X"47",X"38",X"1F",X"37",X"3F",X"FF",X"B6",X"E8",X"1D",X"9F",X"27",X"86",X"F8",X"C8"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..84a48830 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"01",X"53",X"A3",X"BF",X"B5",X"A3",X"3D",X"B5",X"10",X"9F",X"0E",X"A1",X"D7",X"37",X"88",X"E9", + X"AF",X"10",X"F9",X"5C",X"64",X"BB",X"10",X"FF",X"98",X"7D",X"D2",X"07",X"37",X"7D",X"17",X"77", + X"37",X"40",X"03",X"36",X"EC",X"22",X"B5",X"34",X"5F",X"27",X"E0",X"98",X"13",X"98",X"5D",X"53", + X"A3",X"9B",X"B5",X"E6",X"19",X"03",X"9F",X"F8",X"45",X"5D",X"55",X"4D",X"A2",X"C2",X"FC",X"4B", + X"38",X"08",X"BF",X"10",X"FB",X"54",X"B2",X"09",X"55",X"33",X"34",X"57",X"E1",X"29",X"98",X"41", + X"A2",X"41",X"C7",X"DB",X"DB",X"45",X"A2",X"0A",X"FC",X"4B",X"AE",X"AB",X"A2",X"6E",X"FC",X"4B", + X"AE",X"F6",X"E0",X"C6",X"18",X"F8",X"AF",X"BB",X"79",X"FF",X"5C",X"44",X"BF",X"E2",X"69",X"73", + X"79",X"EB",X"BB",X"9B",X"8B",X"E0",X"71",X"B6",X"71",X"24",X"4C",X"FD",X"B6",X"9E",X"E0",X"5C", + X"44",X"BF",X"E0",X"BB",X"9B",X"8B",X"E0",X"BB",X"9B",X"8B",X"05",X"C6",X"AF",X"59",X"A2",X"2A", + X"FC",X"4B",X"AF",X"87",X"A2",X"0F",X"F8",X"4B",X"AE",X"8A",X"D9",X"8F",X"BA",X"D8",X"8B",X"8B", + X"F0",X"8B",X"F1",X"8B",X"E0",X"69",X"DA",X"8B",X"5D",X"4D",X"55",X"C6",X"D0",X"DB",X"DB",X"1B", + X"DB",X"DB",X"F3",X"BF",X"D0",X"8F",X"BA",X"8A",X"96",X"15",X"08",X"9F",X"BB",X"DF",X"5C",X"52", + X"FF",X"0D",X"1D",X"B7",X"14",X"8F",X"DB",X"FC",X"C7",X"8B",X"E3",X"BF",X"8B",X"C7",X"AF",X"9B", + X"5C",X"80",X"C2",X"5C",X"F7",X"BE",X"5C",X"E3",X"9F",X"10",X"9F",X"1F",X"15",X"1D",X"41",X"F3", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..f3b27c53 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"05",X"02",X"00",X"01",X"03",X"06",X"04",X"07",X"08",X"09",X"0B",X"0A",X"0C",X"0E",X"0D",X"08", + X"0B",X"0F",X"0A",X"10",X"3C",X"80",X"5C",X"81",X"A6",X"82",X"8C",X"83",X"B2",X"84",X"F6",X"85", + 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X"F9",X"99",X"D5",X"79",X"F0",X"79",X"E8",X"B3",X"97",X"6B",X"39",X"FF",X"FF",X"F9",X"B9",X"3A", + X"F1",X"79",X"B3",X"A9",X"A0",X"E9",X"7A",X"B1",X"95",X"30",X"A9",X"9D",X"F9",X"30",X"FD",X"72", + X"5C",X"FC",X"B1",X"F2",X"B9",X"F9",X"59",X"C9",X"73",X"BB",X"3A",X"FA",X"DB",X"98",X"F2",X"D5", + X"51",X"E8",X"7D",X"FB",X"F9",X"5D",X"F9",X"FF",X"32",X"75",X"FE",X"71",X"B1",X"68",X"F4",X"B9", + X"FF",X"F9",X"FD",X"B9",X"B1",X"BA",X"59",X"B9",X"BE",X"E8",X"B8",X"F1",X"F7",X"B8",X"F1",X"49", + X"6D",X"F1",X"9E",X"35",X"E1",X"78",X"E0",X"F9",X"B9",X"F9",X"B0",X"BC",X"D4",X"61",X"63",X"59", + X"F0",X"87",X"D9",X"B9",X"58",X"72",X"D8",X"EB",X"8A",X"F1",X"35",X"33",X"B5",X"79",X"79",X"FD", + X"D0",X"6D",X"39",X"F9",X"FF",X"F9",X"54",X"F9",X"7B",X"F9",X"FB",X"E9",X"AD",X"F8",X"79",X"F0", + X"77",X"07",X"30",X"5D",X"8F",X"C7",X"A5",X"07",X"04",X"A7",X"8D",X"44",X"86",X"C6",X"A0",X"45", + X"18",X"07",X"D4",X"7F",X"1F",X"03",X"04",X"05",X"07",X"4E",X"66",X"05",X"6E",X"06",X"06",X"4E", + X"07",X"2E",X"47",X"46",X"06",X"26",X"06",X"46",X"76",X"06",X"02",X"01",X"97",X"D3",X"C6",X"87", + X"A2",X"87",X"00",X"2A",X"37",X"32",X"A4",X"87",X"66",X"76",X"41",X"1E",X"7E",X"63",X"14",X"89", + X"BE",X"06",X"0F",X"53",X"CA",X"8E",X"06",X"02",X"46",X"26",X"07",X"87",X"4F",X"44",X"04",X"0A", + X"96",X"EC",X"10",X"4E",X"0A",X"0C",X"A6",X"A6",X"0E",X"4F",X"C7",X"86",X"02",X"8E",X"06",X"AC", + X"D6",X"00",X"9B",X"23",X"45",X"2E",X"0C",X"67",X"07",X"22",X"83",X"43",X"62",X"C7",X"0C",X"0E", + X"87",X"06",X"14",X"66",X"BD",X"16",X"E7",X"0E",X"8F",X"06",X"64",X"0F",X"86",X"0F",X"06",X"86", + X"FF",X"D1",X"99",X"78",X"5D",X"69",X"F9",X"71",X"DB",X"71",X"3B",X"9B",X"ED",X"7D",X"F8",X"79", + X"9C",X"F9",X"DB",X"F6",X"EB",X"41",X"77",X"43",X"D9",X"59",X"FB",X"33",X"FF",X"F5",X"B9",X"39", + X"A8",X"C9",X"31",X"A3",X"5D",X"B4",X"71",X"69",X"78",X"7B",X"BE",X"FD",X"78",X"BD",X"73",X"39", + X"F4",X"F9",X"BC",X"B1",X"F9",X"64",X"22",X"3C",X"9B",X"5A",X"B9",X"74",X"5C",X"99",X"6B",X"F9", + X"7F",X"90",X"F9",X"78",X"F8",X"B9",X"3B",X"B1",X"39",X"F9",X"6F",X"F8",X"DE",X"FF",X"B1",X"D8", + X"A9",X"96",X"E8",X"DA",X"F5",X"7A",X"A4",X"39",X"B9",X"F9",X"DD",X"4B",X"DB",X"FA",X"D8",X"7B", + X"F5",X"C1",X"B9",X"FC",X"D8",X"79",X"9E",X"90",X"E9",X"50",X"34",X"99",X"A1",X"59",X"FD",X"69", + X"A1",X"FB",X"1B",X"B8",X"77",X"B9",X"14",X"1B",X"27",X"48",X"FF",X"08",X"F8",X"EB",X"B0",X"F8", + X"B9",X"66",X"03",X"46",X"0F",X"47",X"75",X"C6",X"47",X"02",X"07",X"02",X"0C",X"24",X"2F",X"02", + X"8C",X"43",X"82",X"D5",X"2A",X"0F",X"9C",X"02",X"28",X"0C",X"03",X"8D",X"36",X"04",X"23",X"86", + X"42",X"D2",X"A4",X"46",X"CF",X"8C",X"76",X"96",X"C7",X"05",X"86",X"80",X"5B",X"66",X"46",X"0E", + X"16",X"4C",X"4E",X"46",X"52",X"07",X"A7",X"C5",X"03",X"0F",X"44",X"A3",X"0E",X"46",X"46",X"64", + X"0E",X"27",X"26",X"0B",X"07",X"4E",X"82",X"C6",X"07",X"06",X"D6",X"46",X"4E",X"C2",X"A4",X"06", + X"07",X"47",X"17",X"87",X"58",X"15",X"57",X"07",X"44",X"97",X"0C",X"42",X"04",X"86",X"06",X"57", + X"03",X"44",X"06",X"46",X"D2",X"0E",X"0F",X"43",X"47",X"56",X"AC",X"4C",X"06",X"06",X"37",X"86", + X"06",X"56",X"B4",X"07",X"6E",X"28",X"54",X"07",X"C6",X"86",X"07",X"83",X"1E",X"88",X"46",X"AD"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/build_id.v new file mode 100644 index 00000000..f6567fae --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171122" +`define BUILD_TIME "114527" diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd new file mode 100644 index 00000000..677f5d5a --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/eeekk.vhd @@ -0,0 +1,488 @@ +-- +-- A simulation model of Eeekk! hardware +-- Copyright (c) Sorgelig - 2017 +-- +-- Based on Pacman core +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity EEEKKt is + generic( + eight_sprites : boolean := false + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of EEEKKt is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal rom_x,rom_d : std_logic_vector(7 downto 0); + signal dcnt : std_logic_vector(1 downto 0); + signal old_rd_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- sn1_l 0x5040 - 0x504F sound +-- sn2_l 0x5050 - 0x505F sound +-- spr_l 0x5060 - 0x506F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"4" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"5" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"6" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +p_decrypt : process +begin + wait until rising_edge(clk); + if watchdog_reset_l = '0' then + dcnt <= "01"; + else + old_rd_l <= cpu_rd_l; + if old_rd_l = '1' and cpu_rd_l = '0' and cpu_iorq_l = '0' and cpu_m1_l = '1' then + if cpu_addr(0) = '1' then + dcnt <= dcnt - "1"; + else + dcnt <= dcnt + "1"; + end if; + end if; + end if; +end process; + +rom_d <= not rom_x(7) & not rom_x(6) & rom_x(1) & not rom_x(3) & not rom_x(0) & not rom_x(4) & not rom_x(2) & not rom_x(5) when dcnt = "00" else + not rom_x(7) & not rom_x(1) & not rom_x(4) & not rom_x(3) & not rom_x(0) & rom_x(6) & not rom_x(2) & not rom_x(5) when dcnt = "01" else + rom_x(7) & not rom_x(6) & rom_x(1) & not rom_x(0) & rom_x(3) & not rom_x(4) & not rom_x(2) & not rom_x(5) when dcnt = "10" else + rom_x(7) & not rom_x(1) & not rom_x(4) & not rom_x(0) & rom_x(3) & rom_x(6) & not rom_x(2) & not rom_x(5); + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + rom_d when cpu_addr(14) = '0' else + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => rom_x +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(11 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..91313469 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pll.v b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Eeekk_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Eeekk_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Eyes_MiST/Eyes.qpf b/Arcade/Pacman Hardware/Eyes_MiST/Eyes.qpf new file mode 100644 index 00000000..7e8e0030 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/Eyes.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Eyes" diff --git a/Arcade/Pacman Hardware/Eyes_MiST/Eyes.qsf b/Arcade/Pacman Hardware/Eyes_MiST/Eyes.qsf new file mode 100644 index 00000000..0a241769 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/Eyes.qsf @@ -0,0 +1,169 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:14:41 November 10, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Eyes_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Eyes +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------- +# start ENTITY(MrTNT) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(MrTNT) +# ----------------- +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Eyes.sv +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_rom_descrambler.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/sega_decode.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Eyes_MiST/README.txt b/Arcade/Pacman Hardware/Eyes_MiST/README.txt new file mode 100644 index 00000000..e5ec503a --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Eyes port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Eyes_MiST/Release/Eyes.rbf b/Arcade/Pacman Hardware/Eyes_MiST/Release/Eyes.rbf new file mode 100644 index 00000000..29cb8547 Binary files /dev/null and b/Arcade/Pacman Hardware/Eyes_MiST/Release/Eyes.rbf differ diff --git a/Arcade/Pacman Hardware/Eyes_MiST/clean.bat b/Arcade/Pacman Hardware/Eyes_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/Eyes.sv b/Arcade/Pacman Hardware/Eyes_MiST/rtl/Eyes.sv new file mode 100644 index 00000000..8c1ac366 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/Eyes.sv @@ -0,0 +1,192 @@ +//============================================================================ +// Arcade: Pengo +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Eyes +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Eyes;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +pacman eyes +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + + .dipsw_reg(8'b0_1_11_00_11), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..7822e810 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"9C",X"63",X"41",X"9C",X"BE",X"BE",X"41",X"00",X"41",X"14",X"36",X"41",X"63",X"63",X"14",X"00", + X"41",X"41",X"FF",X"00",X"41",X"41",X"FF",X"00",X"00",X"22",X"77",X"00",X"00",X"00",X"77",X"00", + X"41",X"FF",X"DD",X"63",X"C9",X"77",X"DD",X"00",X"63",X"14",X"55",X"22",X"77",X"36",X"14",X"00", + X"36",X"C9",X"C9",X"22",X"FF",X"63",X"C9",X"00",X"14",X"14",X"77",X"00",X"36",X"14",X"55",X"00", + X"14",X"14",X"FF",X"9C",X"FF",X"9C",X"14",X"00",X"00",X"63",X"77",X"00",X"77",X"41",X"36",X"00", + X"BE",X"41",X"41",X"22",X"FF",X"63",X"41",X"00",X"00",X"55",X"55",X"77",X"55",X"77",X"55",X"00", + X"36",X"C9",X"C9",X"BE",X"FF",X"FF",X"C9",X"00",X"00",X"36",X"14",X"41",X"14",X"63",X"14",X"00", + X"00",X"77",X"88",X"00",X"00",X"00",X"FF",X"00",X"36",X"14",X"55",X"36",X"77",X"36",X"14",X"00", + X"36",X"C9",X"DD",X"36",X"77",X"C9",X"DD",X"00",X"00",X"55",X"14",X"63",X"63",X"77",X"14",X"00", + X"9C",X"C9",X"EB",X"00",X"BE",X"C9",X"C9",X"00",X"63",X"14",X"14",X"63",X"77",X"77",X"14",X"00", + X"62",X"00",X"00",X"00",X"41",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"41",X"00",X"00",X"00",X"62",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"94",X"00",X"00",X"00",X"88",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"00",X"00",X"00",X"94", + X"62",X"62",X"63",X"63",X"63",X"63",X"62",X"62",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"94",X"94",X"9C",X"9C",X"9C",X"9C",X"94",X"94", + X"F6",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"F6",X"00",X"00",X"00",X"FF",X"00",X"00",X"00", + X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"F6",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"F6", + X"08",X"01",X"02",X"0C",X"0C",X"02",X"01",X"08",X"01",X"08",X"04",X"03",X"03",X"04",X"08",X"01", + X"08",X"81",X"02",X"0C",X"0C",X"02",X"81",X"08",X"01",X"48",X"04",X"03",X"03",X"04",X"48",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"08",X"31",X"9A",X"84",X"84",X"9A",X"31",X"08",X"01",X"38",X"65",X"42",X"42",X"65",X"38",X"01", + X"9C",X"4F",X"B1",X"2E",X"B2",X"4F",X"4F",X"9C",X"63",X"8F",X"F8",X"17",X"74",X"8F",X"8F",X"63", + X"9C",X"F1",X"4F",X"2E",X"2E",X"4F",X"F1",X"9C",X"63",X"F8",X"8F",X"17",X"17",X"8F",X"F8",X"63", + X"9C",X"4F",X"4F",X"B2",X"2E",X"F1",X"4F",X"9C",X"63",X"8F",X"8F",X"74",X"17",X"F8",X"8F",X"63", + X"00",X"84",X"08",X"00",X"00",X"08",X"84",X"00",X"00",X"42",X"01",X"00",X"00",X"01",X"42",X"00", + X"00",X"86",X"08",X"08",X"08",X"08",X"86",X"00",X"00",X"46",X"01",X"01",X"01",X"01",X"46",X"00", + X"08",X"87",X"08",X"08",X"08",X"08",X"87",X"08",X"01",X"4E",X"01",X"01",X"01",X"01",X"4E",X"01", + X"02",X"C8",X"04",X"22",X"02",X"14",X"78",X"22",X"14",X"B1",X"22",X"04",X"14",X"02",X"C1",X"04", + X"20",X"49",X"10",X"02",X"20",X"04",X"F7",X"02",X"04",X"FE",X"02",X"10",X"04",X"20",X"89",X"10", + X"22",X"81",X"14",X"20",X"22",X"10",X"8F",X"20",X"10",X"4F",X"20",X"14",X"10",X"22",X"48",X"14", + X"08",X"B1",X"92",X"84",X"84",X"92",X"B1",X"08",X"01",X"78",X"64",X"42",X"42",X"64",X"78",X"01", + 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X"BA",X"17",X"3E",X"03",X"E5",X"1C",X"17",X"C3",X"9C",X"25",X"E5",X"FA",X"0B",X"C3",X"A9",X"25", + X"E5",X"DA",X"0B",X"C3",X"A9",X"25",X"2A",X"D7",X"64",X"EB",X"F5",X"09",X"00",X"00",X"F5",X"31", + X"F5",X"7E",X"01",X"F5",X"86",X"02",X"47",X"CE",X"27",X"F5",X"5F",X"02",X"E3",X"38",X"E3",X"38", + X"E3",X"38",X"E3",X"38",X"F5",X"7E",X"00",X"09",X"1C",X"27",X"E3",X"0F",X"E5",X"95",X"17",X"76", + X"0B",X"56",X"EB",X"E9",X"40",X"27",X"40",X"27",X"41",X"27",X"61",X"27",X"51",X"27",X"71",X"27", + X"E1",X"F5",X"7E",X"04",X"90",X"F5",X"5F",X"04",X"E1",X"F5",X"7E",X"04",X"80",X"F5",X"5F",X"04", + X"E1",X"F5",X"7E",X"03",X"80",X"F5",X"5F",X"03",X"E1",X"F5",X"7E",X"03",X"90",X"F5",X"5F",X"03", + X"E1",X"2A",X"8C",X"64",X"EB",X"F5",X"09",X"00",X"00",X"F5",X"31",X"EB",X"01",X"00",X"64",X"1F", + X"3F",X"ED",X"42",X"CD",X"F5",X"7E",X"00",X"09",X"84",X"27",X"E3",X"0F",X"E5",X"95",X"17",X"76", + X"0B",X"56",X"EB",X"E9",X"54",X"10",X"90",X"27",X"D3",X"27",X"4B",X"10",X"6D",X"10",X"80",X"10", + X"F5",X"7E",X"03",X"1A",X"8A",X"64",X"F5",X"7E",X"04",X"1A",X"8B",X"64",X"E5",X"EA",X"10",X"F5", + X"7E",X"06",X"12",X"3A",X"50",X"64",X"FE",X"00",X"08",X"17",X"3A",X"51",X"64",X"FE",X"00",X"08", + X"17",X"C1",X"09",X"52",X"64",X"21",X"CD",X"D1",X"13",X"01",X"05",X"00",X"1E",X"FF",X"ED",X"98", + X"E1",X"F5",X"7E",X"06",X"13",X"12",X"30",X"E9",X"F5",X"7E",X"06",X"09",X"08",X"00",X"31",X"EB", + X"12",X"30",X"F6",X"E5",X"12",X"11",X"F5",X"7E",X"03",X"90",X"1A",X"8A",X"64",X"F5",X"7E",X"04", + X"1A",X"8B",X"64",X"E5",X"EA",X"10",X"3A",X"50",X"64",X"FE",X"00",X"28",X"1A",X"3A",X"50",X"64", + X"E3",X"0F",X"F5",X"46",X"05",X"80",X"3D",X"C1",X"FD",X"09",X"52",X"64",X"FD",X"21",X"FD",X"5B"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..11fc466e --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"05",X"0C",X"01",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"05",X"0C",X"0B",X"00",X"05",X"0C",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..1e48b947 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"DB",X"AF",X"06",X"20",X"09",X"00",X"50",X"5F",X"0B",X"10",X"FC",X"ED",X"56",X"19",X"D9",X"67", + X"C3",X"C7",X"02",X"3A",X"EC",X"64",X"FE",X"00",X"E0",X"47",X"3E",X"30",X"09",X"35",X"40",X"5F", + X"2B",X"10",X"FC",X"E1",X"3A",X"ED",X"64",X"FE",X"00",X"E0",X"47",X"3E",X"30",X"09",X"02",X"40", + X"5F",X"0B",X"10",X"FC",X"E1",X"B6",X"25",X"66",X"20",X"F1",X"F5",X"CD",X"FD",X"CD",X"AF",X"1A", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..9c1d550f --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"DB",X"AF",X"06",X"20",X"09",X"00",X"50",X"5F",X"0B",X"10",X"FC",X"ED",X"56",X"19",X"D9",X"67", + X"C3",X"C7",X"02",X"3A",X"EC",X"64",X"FE",X"00",X"E0",X"47",X"3E",X"30",X"09",X"35",X"40",X"5F", + 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X"44",X"65",X"09",X"00",X"00",X"3E",X"10",X"DD",X"29",X"EB",X"97",X"29",X"EB",X"A5",X"91",X"6F", + X"7C",X"B0",X"4F",X"13",X"D2",X"F1",X"3C",X"21",X"33",X"D9",X"3D",X"C2",X"C7",X"3C",X"E1",X"76", + X"0B",X"56",X"EB",X"29",X"CD",X"29",X"29",X"C1",X"21",X"E1",X"44",X"65",X"09",X"00",X"00",X"3E", + X"10",X"29",X"EB",X"29",X"EB",X"D2",X"F9",X"3C",X"21",X"3D",X"C2",X"D9",X"3C",X"E1",X"71",X"50", + X"EB",X"97",X"95",X"6F",X"3E",X"00",X"B4",X"4F",X"E1",X"EB",X"77",X"16",X"00",X"EB",X"32",X"9D", + X"6F",X"13",X"32",X"9C",X"4F",X"E1",X"77",X"16",X"00",X"7B",X"95",X"6F",X"7A",X"B4",X"4F",X"E1", + X"67",X"06",X"00",X"7B",X"91",X"6F",X"7A",X"B0",X"4F",X"E1",X"69",X"48",X"66",X"0B",X"46",X"32", + X"91",X"6F",X"13",X"32",X"B0",X"4F",X"E1",X"6F",X"0E",X"00",X"32",X"95",X"6F",X"13",X"32",X"B4", + X"4F",X"E1",X"77",X"16",X"00",X"7B",X"96",X"77",X"7A",X"0B",X"B6",X"57",X"EB",X"E1",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"93",X"1B",X"93",X"1B",X"F1",X"13",X"9D",X"0C",X"93",X"1B",X"EC",X"2E",X"48",X"2F", + X"00",X"00",X"F1",X"13",X"9D",X"0C",X"65",X"0E",X"FF",X"7F",X"2F",X"03",X"BA",X"06",X"00",X"04", + X"FC",X"03",X"76",X"03",X"8F",X"03",X"D5",X"03",X"A0",X"27",X"AD",X"03",X"EA",X"03",X"DF",X"03", + X"A2",X"03",X"1C",X"03",X"E7",X"03",X"4D",X"03",X"92",X"03",X"CA",X"03",X"56",X"03",X"06",X"03", + X"F2",X"92",X"03",X"DA",X"20",X"D2",X"67",X"70",X"A2",X"03",X"F2",X"A8",X"C4",X"52",X"67",X"57", + X"AD",X"03",X"85",X"C7",X"66",X"61",X"66",X"52",X"41",X"57",X"1C",X"03",X"97",X"E5",X"52",X"54", + X"A0",X"27",X"96",X"10",X"C5",X"64",X"54",X"61",X"54",X"CE",X"27",X"A3",X"E5",X"71",X"53",X"0B", + X"00",X"96",X"40",X"C2",X"55",X"53",X"4D",X"03",X"F2",X"90",X"C7",X"66",X"61",X"52",X"54",X"53", + X"D5",X"03",X"95",X"C5",X"64",X"54",X"61",X"54",X"53",X"06",X"03",X"A4",X"E4",X"52",X"53",X"8F", + X"03",X"F1",X"38",X"C1",X"52",X"53",X"1A",X"00",X"F1",X"28",X"C5",X"43",X"41",X"50",X"53",X"F1", + X"27",X"A1",X"D0",X"53",X"78",X"00",X"F8",X"18",X"C1",X"64",X"53",X"4A",X"00",X"F1",X"08",X"D2", + X"60",X"53",X"81",X"00",X"B7",X"E4",X"60",X"53",X"51",X"00",X"B6",X"D4",X"45",X"53",X"76",X"03", + X"F0",X"C0",X"C7",X"45",X"53",X"94",X"00",X"B2",X"E6",X"67",X"61",X"54",X"43",X"45",X"53",X"2A", + X"00",X"8A",X"00",X"C6",X"43",X"53",X"8F",X"27",X"D1",X"1F",X"D2",X"41",X"64",X"41",X"43",X"53", + X"EA",X"03",X"8F",X"C3",X"42",X"53",X"A5",X"00",X"F4",X"B0",X"42",X"D4",X"53",X"52",X"B2",X"00", + X"F7",X"C4",X"52",X"52",X"70",X"00",X"D2",X"4F",X"C1",X"43",X"52",X"52",X"B8",X"00",X"D1",X"27", + X"C3",X"52",X"52",X"42",X"00",X"F1",X"20",X"C1",X"52",X"52",X"C2",X"00",X"D1",X"37",X"D2",X"52", + X"CD",X"00",X"F1",X"30",X"C4",X"64",X"52",X"F6",X"00",X"D2",X"6F",X"C1",X"43",X"64",X"52",X"B3", + X"27",X"D1",X"07",X"C3",X"64",X"52",X"59",X"00",X"F1",X"00",X"C1",X"64",X"52",X"DA",X"00",X"D1", + X"17",X"E4",X"52",X"20",X"01",X"F1",X"10",X"E6",X"54",X"45",X"52",X"D0",X"00",X"D2",X"45",X"E1", + X"54",X"45",X"52",X"6B",X"00",X"D2",X"65",X"D4",X"45",X"52",X"15",X"01",X"D7",X"E1",X"C5",X"65", + X"55",X"53",X"45",X"52",X"01",X"01",X"8D",X"C5",X"56",X"52",X"45",X"53",X"45",X"52",X"86",X"00", + X"8C",X"01",X"D3",X"45",X"52",X"D6",X"00",X"F0",X"80",X"D4",X"41",X"45",X"50",X"45",X"52",X"40", + X"01",X"A7",X"D2",X"27",X"01",X"DB",X"E0",X"53",X"55",X"50",X"51",X"01",X"F6",X"C5",X"D0",X"67", + X"50",X"2C",X"01",X"F6",X"C1",X"E7",X"50",X"0D",X"01",X"DA",X"08",X"C5",X"50",X"F9",X"00",X"DA", + X"28",X"C5",X"47",X"41",X"50",X"E7",X"03",X"A0",X"30",X"D0",X"4B",X"01",X"DA",X"18",X"E1",X"54", + X"55",X"67",X"5F",X"01",X"D2",X"8B",X"C4",X"54",X"55",X"67",X"CA",X"03",X"D2",X"AB",X"D4",X"55", + X"67",X"A4",X"01",X"C9",X"41",X"D2",X"61",X"54",X"67",X"74",X"01",X"D2",X"9B",X"D2",X"44",X"54", + X"67",X"7C",X"01",X"D2",X"BB",X"C7",X"52",X"67",X"E0",X"00",X"81",X"D2",X"67",X"69",X"01",X"F2", + X"98",X"F2",X"66",X"99",X"00",X"DA",X"00",X"D0",X"67",X"66",X"63",X"00",X"D1",X"00",X"D4",X"53", + X"61",X"64",X"67",X"66",X"88",X"00",X"87",X"C7",X"45",X"66",X"47",X"01",X"D2",X"44",X"D2",X"60", + X"43",X"66",X"8B",X"01",X"B4",X"C3",X"66",X"C6",X"01",X"DA",X"10",X"C5",X"65",X"41",X"66",X"D4", + X"01",X"AB",X"C4",X"67",X"65",X"F1",X"01",X"B5",X"C7",X"45",X"65",X"9D",X"01",X"96",X"D8",X"C5", + X"65",X"55",X"01",X"96",X"FF",X"E7",X"52",X"43",X"41",X"65",X"BC",X"01",X"91",X"E5",X"93",X"01", + X"DA",X"38",X"E7",X"64",X"E4",X"01",X"B1",X"D4",X"53",X"61",X"64",X"6F",X"01",X"86",X"D2",X"61", + X"44",X"64",X"DB",X"01",X"D2",X"98",X"E1",X"44",X"64",X"8F",X"00",X"D2",X"88",X"D2",X"44",X"44", + X"64",X"CF",X"01",X"D2",X"B8",X"C4",X"44",X"64",X"06",X"02",X"D2",X"A8",X"C4",X"64",X"14",X"02", + X"D0",X"E4",X"33",X"02",X"DD",X"05",X"D2",X"62",X"35",X"01",X"D3",X"30",X"D0",X"62",X"1C",X"02", + X"D5",X"C3",X"F1",X"61",X"18",X"02",X"FC",X"08",X"F0",X"61",X"AA",X"01",X"FD",X"08",X"C5",X"47"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Eyes_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Eyes_MiST/rtl/build_id.v new file mode 100644 index 00000000..81e50658 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "221924" diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Eyes_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Eyes_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Eyes_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Eyes_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..9b976d32 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman.vhd @@ -0,0 +1,629 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN is +generic ( + MRTNT : std_logic := '1' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data_out : std_logic_vector(7 downto 0); + signal rom_data : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + rom_data <= program_rom_dinl when cpu_addr(15) = '0' else program_rom_dinh; + rom_data_out <= rom_data(7 downto 6) & rom_data(3) & rom_data(4) & rom_data(5) & rom_data(2 downto 0) when MRTNT = '1' else rom_data; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data_out, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data_out; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data_out; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd new file mode 100644 index 00000000..d5e5f484 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_rom_descrambler.vhd @@ -0,0 +1,479 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) d18c7db (gmail) - May 2013 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- + + +-- The following comments and source code in the comments are from MAME source code and are +-- included here to help make sense of the logic used in the VHDL address mapper and descrambler +-- +--/************************************ +-- * +-- * Ms. Pac-Man +-- * +-- ************************************/ +-- +--/* +-- Ms. Pac-Man has an auxiliary PCB with ribbon cable that plugs into the Z-80 CPU socket of a Pac-Man main PCB. Also the +-- graphics ROMs at 5E, 5F on the main board are replaced. +-- +-- The aux board contains three ROMs (two 2532 at U6, U7 and one 2716 at U5), a Z-80, and four PAL/HAL logic chips. +-- +-- The aux board logic decodes the Z-80 address and determines whether to enable the main board ROMs (containing Pac-Man +-- code) or the aux board ROMs (containing Ms. Pac-Man code). Normally the Pac-Man ROMs reside at address 0x0000-0x3fff +-- and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). The aux board logic modifies the address map and +-- enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. Furthermore there are forty 8-byte "patch" +-- regions which reside in the 0x0000-0x2fff address range. Any access to these patch addresses will disable the Pac-Man +-- ROMs and enable the aux board ROM. Aux board ROM addresses 0x8000-0x81ef are mapped onto the patch regions. These +-- patches typically insert jumps to new code above 0x8000. +-- +-- The aux board logic also acts as a software protection circuit which inhibits dumping of the ROMs (e.g., using a +-- microprocessor emulator system). There are several "trap" address regions which enable and disable the decode +-- functions. In order to properly operate as Ms. Pac-Man you must access one of the "latch set" trap addresses. This +-- enables the decode. If a "latch clear" address is accessed then decode is disabled and all you get is Pac-Man. For +-- more info see U.S. Patent 4,525,599 "Software protection methods and apparatus". +-- +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 +-- +-- Any memory access will trigger the trap behavior: instruction fetch, data read, data write. The latch clear addresses +-- should never be accessed during normal Ms. Pac-Man operation, so when the circuitry detects an access it clears the +-- latch and prevents any further dumping of the aux board ROMs. +-- +-- The Pac-Man self-test code does a checksum of the ROM 0x0000-0x2fff. This works because the checksum routine walks the +-- ROM starting from the low address and hits the latch clear trap at 0x0038 prior to encountering any of the patch +-- regions. The decode stays disabled for the rest of the checksum routine, and thus the checksum is calculated for the +-- Pac-Man ROMs with no patches applied. +-- +-- During normal operation every VBLANK (60.6Hz) interrupt will fetch its interrupt vector from the 0x3ff8 trap region, so +-- the latch is continually being enabled. +-- +-- In a further attempt to thwart copying, the aux board ROMs have a simple encryption scheme: their address and data +-- lines are bit flipped (i.e., wired in a nonstandard fashion). The specific bit flips were selected to minimize the +-- vias required to lay out the aux PCB. +--*/ + +-- +--static void mspacman_install_patches(UINT8 *ROM) +--{ +-- int i; +-- +-- /* copy forty 8-byte patches into Pac-Man code */ +-- for (i = 0; i < 8; i++) +-- { +-- ROM[0x0410+i] = ROM[0x8008+i]; +-- ROM[0x08E0+i] = ROM[0x81D8+i]; +-- ROM[0x0A30+i] = ROM[0x8118+i]; +-- ROM[0x0BD0+i] = ROM[0x80D8+i]; +-- ROM[0x0C20+i] = ROM[0x8120+i]; +-- ROM[0x0E58+i] = ROM[0x8168+i]; +-- ROM[0x0EA8+i] = ROM[0x8198+i]; +-- +-- ROM[0x1000+i] = ROM[0x8020+i]; +-- ROM[0x1008+i] = ROM[0x8010+i]; +-- ROM[0x1288+i] = ROM[0x8098+i]; +-- ROM[0x1348+i] = ROM[0x8048+i]; +-- ROM[0x1688+i] = ROM[0x8088+i]; +-- ROM[0x16B0+i] = ROM[0x8188+i]; +-- ROM[0x16D8+i] = ROM[0x80C8+i]; +-- ROM[0x16F8+i] = ROM[0x81C8+i]; +-- ROM[0x19A8+i] = ROM[0x80A8+i]; +-- ROM[0x19B8+i] = ROM[0x81A8+i]; +-- +-- ROM[0x2060+i] = ROM[0x8148+i]; +-- ROM[0x2108+i] = ROM[0x8018+i]; +-- ROM[0x21A0+i] = ROM[0x81A0+i]; +-- ROM[0x2298+i] = ROM[0x80A0+i]; +-- ROM[0x23E0+i] = ROM[0x80E8+i]; +-- ROM[0x2418+i] = ROM[0x8000+i]; +-- ROM[0x2448+i] = ROM[0x8058+i]; +-- ROM[0x2470+i] = ROM[0x8140+i]; +-- ROM[0x2488+i] = ROM[0x8080+i]; +-- ROM[0x24B0+i] = ROM[0x8180+i]; +-- ROM[0x24D8+i] = ROM[0x80C0+i]; +-- ROM[0x24F8+i] = ROM[0x81C0+i]; +-- ROM[0x2748+i] = ROM[0x8050+i]; +-- ROM[0x2780+i] = ROM[0x8090+i]; +-- ROM[0x27B8+i] = ROM[0x8190+i]; +-- ROM[0x2800+i] = ROM[0x8028+i]; +-- ROM[0x2B20+i] = ROM[0x8100+i]; +-- ROM[0x2B30+i] = ROM[0x8110+i]; +-- ROM[0x2BF0+i] = ROM[0x81D0+i]; +-- ROM[0x2CC0+i] = ROM[0x80D0+i]; +-- ROM[0x2CD8+i] = ROM[0x80E0+i]; +-- ROM[0x2CF0+i] = ROM[0x81E0+i]; +-- ROM[0x2D60+i] = ROM[0x8160+i]; +-- } +--} +-- +--DRIVER_INIT_MEMBER(pacman_state,mspacman) +--{ +-- int i; +-- UINT8 *ROM, *DROM; +-- +-- /* CPU ROMs */ +-- +-- /* Pac-Man code is in low bank */ +-- ROM = machine().root_device().memregion("maincpu")->base(); +-- +-- /* decrypted Ms. Pac-Man code is in high bank */ +-- DROM = &machine().root_device().memregion("maincpu")->base()[0x10000]; +-- +-- /* copy ROMs into decrypted bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0x0000+i] = ROM[0x0000+i]; /* pacman.6e */ +-- DROM[0x1000+i] = ROM[0x1000+i]; /* pacman.6f */ +-- DROM[0x2000+i] = ROM[0x2000+i]; /* pacman.6h */ +-- DROM[0x3000+i] = BITSWAP8(ROM[0xb000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u7 */ +-- } +-- for (i = 0; i < 0x800; i++) +-- { +-- DROM[0x8000+i] = BITSWAP8(ROM[0x8000+BITSWAP16(i,15,14,13,12,11,8,7,5,9,10,6,3,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u5 */ +-- DROM[0x8800+i] = BITSWAP8(ROM[0x9800+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +-- DROM[0x9000+i] = BITSWAP8(ROM[0x9000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +--// 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 +-- DROM[0x9800+i] = ROM[0x1800+i]; /* mirror of pacman.6f high */ +-- } +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0xa000+i] = ROM[0x2000+i]; /* mirror of pacman.6h */ +-- DROM[0xb000+i] = ROM[0x3000+i]; /* mirror of pacman.6j */ +-- } +-- /* install patches into decrypted bank */ +-- mspacman_install_patches(DROM); +-- +-- /* mirror Pac-Man ROMs into upper addresses of normal bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- ROM[0x8000+i] = ROM[0x0000+i]; +-- ROM[0x9000+i] = ROM[0x1000+i]; +-- ROM[0xa000+i] = ROM[0x2000+i]; +-- ROM[0xb000+i] = ROM[0x3000+i]; +-- } +-- +-- /* initialize the banks */ +-- machine().root_device().membank("bank1")->configure_entries(0, 2, &ROM[0x00000], 0x10000); +-- machine().root_device().membank("bank1")->set_entry(1); +--} +-- +--ROM_START( puckmana ) +-- ROM_REGION( 0x10000, "maincpu", 0 ) +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "prg7", 0x3000, 0x0800, CRC(b6289b26) SHA1(d249fa9cdde774d5fee7258147cd25fa3f4dc2b3) ) +-- ROM_LOAD( "prg8", 0x3800, 0x0800, CRC(17a88c13) SHA1(eb462de79f49b7aa8adb0cc6d31535b10550c0ce) ) +-- +--ROM_START( mspacman ) +-- ROM_REGION( 0x20000, "maincpu", 0 ) /* 64k for code+64k for decrypted code */ +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "pacman.6j", 0x3000, 0x1000, CRC(817d94e3) SHA1(d4a70d56bb01d27d094d73db8667ffb00ca69cb9) ) +-- +-- ROM_LOAD( "u5", 0x8000, 0x0800, CRC(f45fbbcd) SHA1(b26cc1c8ee18e9b1daa97956d2159b954703a0ec) ) +-- ROM_LOAD( "u6", 0x9000, 0x1000, CRC(a90e7000) SHA1(e4df96f1db753533f7d770aa62ae1973349ea4cf) ) +-- ROM_LOAD( "u7", 0xb000, 0x1000, CRC(c82cd714) SHA1(1d8ac7ad03db2dc4c8c18ade466e12032673f874) ) +-- +-- +--Normally the Pac-Man ROMs reside at address 0x0000-0x3fff and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). +--The aux board logic modifies the address map and enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity rom_descrambler is + generic ( + -- only set one of these + PENGO : std_logic := '0'; -- set to 1 when using Pengo ROMs, 0 otherwise + PACMAN : std_logic := '1'; -- set to 1 for all other Pacman hardware games + -- only set one of these when PACMAN is set + MRTNT : std_logic := '0'; -- set to 1 when using Mr TNT ROMs, 0 otherwise + LIZWIZ : std_logic := '0'; -- set to 1 when using Lizard Wizard ROMs, 0 otherwise + MSPACMAN : std_logic := '0' -- set to 1 when using Ms Pacman ROMs, 0 otherwise + ); + port ( + CLK : in std_logic; + ENA : in std_logic; + -- + cpu_m1_l : in std_logic; + addr : in std_logic_vector(15 downto 0); + data : out std_logic_vector( 7 downto 0) + ); + +end rom_descrambler; + +architecture rtl of rom_descrambler is + signal overlay_on : std_logic := '0'; + signal sega_dec_ena : std_logic; + signal rom_patched : std_logic_vector(15 downto 0); + signal rom_addr : std_logic_vector(15 downto 0); + signal rom_lo : std_logic_vector( 7 downto 0); + signal rom_hi : std_logic_vector( 7 downto 0); + signal rom_data_in : std_logic_vector( 7 downto 0); + signal rom_data_out : std_logic_vector( 7 downto 0); + signal sega_dec : std_logic_vector( 7 downto 0); +begin + -- ROM at 0000 - 3FFF + u_program_rom0 : entity work.ROM_PGM_0 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_lo + ); + + -- ROM at 8000 - BFFF (Liz Wiz) + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_hi + ); + + -- Sega ROM descrambler adapted from MAME segacrpt.c source code + u_sega_decode : entity work.sega_decode + port map ( + I_CK => clk, + I_DEC => sega_dec_ena, -- passthrough when low + I_A(6) => cpu_m1_l, + I_A(5) => rom_addr(12), + I_A(4) => rom_addr(8), + I_A(3) => rom_addr(4), + I_A(2) => rom_addr(0), + I_A(1) => rom_data_in(5), + I_A(0) => rom_data_in(3), + I_D => rom_data_in, + O_D => sega_dec + ); + + sega_dec_ena <= PENGO and (not rom_addr(15)); + +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 + p_overlay : process + variable trap_addr : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + trap_addr := addr(15 downto 3) & "000"; + if trap_addr = x"3ff8" then + overlay_on <= '1'; + elsif + trap_addr = x"0038" or + trap_addr = x"03b0" or + trap_addr = x"1600" or + trap_addr = x"2120" or + trap_addr = x"3ff0" or + trap_addr = x"8000" or + trap_addr = x"97f0" + then + overlay_on <= '0'; + end if; + end process; + + p_decoder_comb : process(clk, rom_addr, addr, rom_data_in, rom_data_out, rom_patched, rom_hi, rom_lo, overlay_on, sega_dec) + variable patch_addr : std_logic_vector(15 downto 0); + begin + rom_addr <= addr; + rom_patched <= addr; + data <= rom_data_out; + + -- default is unscrambled data + rom_data_out <= rom_data_in ; + + -- mux ROMs to same data bus + -- ignore A15 so that Pacman ROMs 0000-3FFF mirror in high mem at 8000-BFFF + if rom_addr(14) = '0' then + rom_data_in <= rom_lo; + else + rom_data_in <= rom_hi; + end if; + + -- Mr TNT program ROMs have data lines D3 and D5 swapped + -- Mr TNT video ROMs have data lines D4 and D6 and address lines A0 and A2 swapped + if MRTNT = '1' then + rom_data_out <= rom_data_in(7 downto 6) & rom_data_in(3) & rom_data_in(4) & rom_data_in(5) & rom_data_in(2 downto 0); + end if; + + if PENGO = '1' then + -- ROM at 0000 - 7fff (Pengo) + if rom_addr(15) = '0' then + rom_data_out <= sega_dec; + end if; + end if; + + if MSPACMAN = '1' and overlay_on = '1' then + -- forty 8-byte patches into Pac-Man code + -- If the CPU address presented falls in a patch range, substitute it with patched address + -- OH THE HUMANITY!!! + patch_addr := addr(15 downto 3) & "000"; + case patch_addr is + when x"0410" => rom_patched <= x"800" & '1' & addr(2 downto 0); -- ROM[0x0410+i] = ROM[0x8008+i] + when x"08E0" => rom_patched <= x"81D" & '1' & addr(2 downto 0); -- ROM[0x08E0+i] = ROM[0x81D8+i] + when x"0A30" => rom_patched <= x"811" & '1' & addr(2 downto 0); -- ROM[0x0A30+i] = ROM[0x8118+i] + when x"0BD0" => rom_patched <= x"80D" & '1' & addr(2 downto 0); -- ROM[0x0BD0+i] = ROM[0x80D8+i] + when x"0C20" => rom_patched <= x"812" & '0' & addr(2 downto 0); -- ROM[0x0C20+i] = ROM[0x8120+i] + when x"0E58" => rom_patched <= x"816" & '1' & addr(2 downto 0); -- ROM[0x0E58+i] = ROM[0x8168+i] + when x"0EA8" => rom_patched <= x"819" & '1' & addr(2 downto 0); -- ROM[0x0EA8+i] = ROM[0x8198+i] + + when x"1000" => rom_patched <= x"802" & '0' & addr(2 downto 0); -- ROM[0x1000+i] = ROM[0x8020+i] + when x"1008" => rom_patched <= x"801" & '0' & addr(2 downto 0); -- ROM[0x1008+i] = ROM[0x8010+i] + when x"1288" => rom_patched <= x"809" & '1' & addr(2 downto 0); -- ROM[0x1288+i] = ROM[0x8098+i] + when x"1348" => rom_patched <= x"804" & '1' & addr(2 downto 0); -- ROM[0x1348+i] = ROM[0x8048+i] + when x"1688" => rom_patched <= x"808" & '1' & addr(2 downto 0); -- ROM[0x1688+i] = ROM[0x8088+i] + when x"16B0" => rom_patched <= x"818" & '1' & addr(2 downto 0); -- ROM[0x16B0+i] = ROM[0x8188+i] + when x"16D8" => rom_patched <= x"80C" & '1' & addr(2 downto 0); -- ROM[0x16D8+i] = ROM[0x80C8+i] + when x"16F8" => rom_patched <= x"81C" & '1' & addr(2 downto 0); -- ROM[0x16F8+i] = ROM[0x81C8+i] + when x"19A8" => rom_patched <= x"80A" & '1' & addr(2 downto 0); -- ROM[0x19A8+i] = ROM[0x80A8+i] + when x"19B8" => rom_patched <= x"81A" & '1' & addr(2 downto 0); -- ROM[0x19B8+i] = ROM[0x81A8+i] + + when x"2060" => rom_patched <= x"814" & '1' & addr(2 downto 0); -- ROM[0x2060+i] = ROM[0x8148+i] + when x"2108" => rom_patched <= x"801" & '1' & addr(2 downto 0); -- ROM[0x2108+i] = ROM[0x8018+i] + when x"21A0" => rom_patched <= x"81A" & '0' & addr(2 downto 0); -- ROM[0x21A0+i] = ROM[0x81A0+i] + when x"2298" => rom_patched <= x"80A" & '0' & addr(2 downto 0); -- ROM[0x2298+i] = ROM[0x80A0+i] + when x"23E0" => rom_patched <= x"80E" & '1' & addr(2 downto 0); -- ROM[0x23E0+i] = ROM[0x80E8+i] + when x"2418" => rom_patched <= x"800" & '0' & addr(2 downto 0); -- ROM[0x2418+i] = ROM[0x8000+i] + when x"2448" => rom_patched <= x"805" & '1' & addr(2 downto 0); -- ROM[0x2448+i] = ROM[0x8058+i] + when x"2470" => rom_patched <= x"814" & '0' & addr(2 downto 0); -- ROM[0x2470+i] = ROM[0x8140+i] + when x"2488" => rom_patched <= x"808" & '0' & addr(2 downto 0); -- ROM[0x2488+i] = ROM[0x8080+i] + when x"24B0" => rom_patched <= x"818" & '0' & addr(2 downto 0); -- ROM[0x24B0+i] = ROM[0x8180+i] + when x"24D8" => rom_patched <= x"80C" & '0' & addr(2 downto 0); -- ROM[0x24D8+i] = ROM[0x80C0+i] + when x"24F8" => rom_patched <= x"81C" & '0' & addr(2 downto 0); -- ROM[0x24F8+i] = ROM[0x81C0+i] + when x"2748" => rom_patched <= x"805" & '0' & addr(2 downto 0); -- ROM[0x2748+i] = ROM[0x8050+i] + when x"2780" => rom_patched <= x"809" & '0' & addr(2 downto 0); -- ROM[0x2780+i] = ROM[0x8090+i] + when x"27B8" => rom_patched <= x"819" & '0' & addr(2 downto 0); -- ROM[0x27B8+i] = ROM[0x8190+i] + when x"2800" => rom_patched <= x"802" & '1' & addr(2 downto 0); -- ROM[0x2800+i] = ROM[0x8028+i] + when x"2B20" => rom_patched <= x"810" & '0' & addr(2 downto 0); -- ROM[0x2B20+i] = ROM[0x8100+i] + when x"2B30" => rom_patched <= x"811" & '0' & addr(2 downto 0); -- ROM[0x2B30+i] = ROM[0x8110+i] + when x"2BF0" => rom_patched <= x"81D" & '0' & addr(2 downto 0); -- ROM[0x2BF0+i] = ROM[0x81D0+i] + when x"2CC0" => rom_patched <= x"80D" & '0' & addr(2 downto 0); -- ROM[0x2CC0+i] = ROM[0x80D0+i] + when x"2CD8" => rom_patched <= x"80E" & '0' & addr(2 downto 0); -- ROM[0x2CD8+i] = ROM[0x80E0+i] + when x"2CF0" => rom_patched <= x"81E" & '0' & addr(2 downto 0); -- ROM[0x2CF0+i] = ROM[0x81E0+i] + when x"2D60" => rom_patched <= x"816" & '0' & addr(2 downto 0); -- ROM[0x2D60+i] = ROM[0x8160+i] + when others => rom_patched <= addr; + end case; + +-- Pacman ROMs +-- 0x0000-0x0FFF = 0x0000-0x0FFF; /* pacman.6e */ +-- 0x1000-0x1FFF = 0x1000-0x1FFF; /* pacman.6f */ +-- 0x2000-0x2FFF = 0x2000-0x2FFF; /* pacman.6h */ +-- 0x3000-0x3FFF = 0x3000-0x3FFF; /* pacman.6j */ + +-- ROM mirror (easy just ignore A15) +-- 0x8000-0x8FFF = 0x0000-0x0FFF; /* mirror of pacman.6e */ +-- 0x9000-0x9FFF = 0x1000-0x1FFF; /* mirror of pacman.6f */ +-- 0xA000-0xAFFF = 0x2000-0x2FFF; /* mirror of pacman.6h */ +-- 0xB000-0xBFFF = 0x3000-0x3FFF; /* mirror of pacman.6j */ + +-- Ms Pacman overlays + +-- no xlate +-- 0x8000-0x87FF = 0x8000-0x87FF (physical ROM hi 0000-07FF); /* decrypt u5 */ +-- 0x9000-0x97FF = 0x9000-0x97FF (physical ROM hi 1000-17FF); /* decrypt half of u6 */ + +-- xlate addr +-- 0x3000-0x3FFF = 0xB000-0xBFFF (physical ROM hi 2000-2FFF); /* decrypt u7 */ + +-- xlate addr +-- 0x8800-0x8FFF = 0x9800-0x9FFF (physical ROM hi 1800-1FFF); /* decrypt half of u6 */ + +-- ROM hi mem map +-- u5 2K 0000-07FF (0x8000-0x87FF) +-- u5 2K 0800-0FFF N/A +-- u6b 2K 1000-17FF (0x9000-0x97FF) +-- u6t 2K 1800-1FFF (0x8800-0x8FFF) +-- u7 4K 2000-2FFF (0x3000-0x3FFF) + + -- If the new patched address falls in certain Ms Pacman ranges, swap in ROM overlays and descramble address and data + -- high address bits are not scrambled so we know for sure this only accesses ROM hi after address translation + case rom_patched(15 downto 11) is + + -- addr = 0x3000-0x37FF, xlate to 0xB000-0xB7FF (physical ROM hi 2000-27FF), decrypt half of u7 + when "00110" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x3800-0x3FFF, xlate to 0xB800-0xBFFF (physical ROM hi 2800-2FFF), decrypt half of u7 + when "00111" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8000-0x87FF, no xlate (physical ROM hi 0000-07FF), decrypt u5 + when "10000" => + rom_addr <= x"0" & rom_patched(11) & rom_patched(8) & rom_patched(7) & rom_patched(5) & rom_patched(9) & rom_patched(10) & rom_patched(6) & rom_patched(3) & rom_patched(4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8800-0x8FFF, xlate to 0x9800-0x9FFF (physical ROM hi 1800-1FFF), decrypt half of u6 + when "10001" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x9000-0x97FF, no xlate (physical ROM hi 1000-17FF), decrypt half of u6 + when "10010" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- catch all default action + when others => null; + rom_addr <= rom_patched; + rom_data_out <= rom_data_in; + end case; + end if; + end process; + +end rtl; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..895304e9 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_video.vhd @@ -0,0 +1,366 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Eyes_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd b/Arcade/Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd new file mode 100644 index 00000000..8ae8141d --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/sega_decode.vhd @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------- +-- Pengo decode table +-- /* opcode (M1=0) data (M1=1) address */ +-- /* 0 1 2 3 0 1 2 3 A12 A8 A4 A0 */ +-- { 0xa0,0x80,0xa8,0x88 }, { 0x28,0xa8,0x08,0x88 }, /* ...0...0...0...0 */ +-- { 0x28,0xa8,0x08,0x88 }, { 0xa0,0x80,0xa8,0x88 }, /* ...0...0...0...1 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...0...0...1...0 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0xa0,0x80,0xa8,0x88 }, /* ...0...0...1...1 */ +-- { 0x08,0x00,0x88,0x80 }, { 0x28,0xa8,0x08,0x88 }, /* ...0...1...0...0 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0x08,0x00,0x88,0x80 }, /* ...0...1...0...1 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...0...1...1...0 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0x00,0x08,0x20,0x28 }, /* ...0...1...1...1 */ +-- { 0x88,0x80,0x08,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...1...0...0...0 */ +-- { 0x88,0x80,0x08,0x00 }, { 0x00,0x08,0x20,0x28 }, /* ...1...0...0...1 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0x08,0x28,0x88,0xa8 }, /* ...1...0...1...0 */ +-- { 0xa0,0x80,0xa8,0x88 }, { 0xa0,0x80,0x20,0x00 }, /* ...1...0...1...1 */ +-- { 0x08,0x00,0x88,0x80 }, { 0x88,0x80,0x08,0x00 }, /* ...1...1...0...0 */ +-- { 0x00,0x08,0x20,0x28 }, { 0x88,0x80,0x08,0x00 }, /* ...1...1...0...1 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0x08,0x28,0x88,0xa8 }, /* ...1...1...1...0 */ +-- { 0x08,0x00,0x88,0x80 }, { 0xa0,0x80,0x20,0x00 } /* ...1...1...1...1 */ +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity sega_decode is + port ( + I_DEC : in std_logic; + I_CK : in std_logic; + -- + I_A : in std_logic_vector(6 downto 0); + I_D : in std_logic_vector(7 downto 0); + O_D : out std_logic_vector(7 downto 0) + ); + +end sega_decode; + +architecture rtl of sega_decode is + signal sel : std_logic_vector(6 downto 0); + signal val : std_logic_vector(2 downto 0); +begin + p_decoder : process + begin + wait until rising_edge(I_CK); + if (I_DEC = '0') then + O_D <= I_D; -- passthough + else + sel <= I_A xor ("00000" & I_D(7) & I_D(7)); + O_D(7) <= I_D(7) xor val(2); + O_D(6) <= I_D(6); + O_D(5) <= I_D(7) xor val(1); + O_D(4) <= I_D(4); + O_D(3) <= I_D(7) xor val(0); + O_D(2) <= I_D(2); + O_D(1) <= I_D(1); + O_D(0) <= I_D(0); + case sel is -- M1 A12 A8 A4 A0 D5 D3 + when "0000000" => val <= "110"; + when "0000001" => val <= "100"; + when "0000010" => val <= "111"; + when "0000011" => val <= "101"; + when "0000100" => val <= "011"; + when "0000101" => val <= "111"; + when "0000110" => val <= "001"; + when "0000111" => val <= "101"; + when "0001000" => val <= "110"; + when "0001001" => val <= "100"; + when "0001010" => val <= "010"; + when "0001011" => val <= "000"; + when "0001100" => val <= "001"; + when "0001101" => val <= "011"; + when "0001110" => val <= "101"; + when "0001111" => val <= "111"; + when "0010000" => val <= "001"; + when "0010001" => val <= "000"; + when "0010010" => val <= "101"; + when "0010011" => val <= "100"; + when "0010100" => val <= "110"; + when "0010101" => val <= "100"; + when "0010110" => val <= "010"; + when "0010111" => val <= "000"; + when "0011000" => val <= "110"; + when "0011001" => val <= "100"; + when "0011010" => val <= "010"; + when "0011011" => val <= "000"; + when "0011100" => val <= "110"; + when "0011101" => val <= "100"; + when "0011110" => val <= "010"; + when "0011111" => val <= "000"; + when "0100000" => val <= "101"; + when "0100001" => val <= "100"; + when "0100010" => val <= "001"; + when "0100011" => val <= "000"; + when "0100100" => val <= "101"; + when "0100101" => val <= "100"; + when "0100110" => val <= "001"; + when "0100111" => val <= "000"; + when "0101000" => val <= "001"; + when "0101001" => val <= "011"; + when "0101010" => val <= "101"; + when "0101011" => val <= "111"; + when "0101100" => val <= "110"; + when "0101101" => val <= "100"; + when "0101110" => val <= "111"; + when "0101111" => val <= "101"; + when "0110000" => val <= "001"; + when "0110001" => val <= "000"; + when "0110010" => val <= "101"; + when "0110011" => val <= "100"; + when "0110100" => val <= "000"; + when "0110101" => val <= "001"; + when "0110110" => val <= "010"; + when "0110111" => val <= "011"; + when "0111000" => val <= "001"; + when "0111001" => val <= "011"; + when "0111010" => val <= "101"; + when "0111011" => val <= "111"; + when "0111100" => val <= "001"; + when "0111101" => val <= "000"; + when "0111110" => val <= "101"; + when "0111111" => val <= "100"; + when "1000000" => val <= "011"; + when "1000001" => val <= "111"; + when "1000010" => val <= "001"; + when "1000011" => val <= "101"; + when "1000100" => val <= "110"; + when "1000101" => val <= "100"; + when "1000110" => val <= "111"; + when "1000111" => val <= "101"; + when "1001000" => val <= "110"; + when "1001001" => val <= "100"; + when "1001010" => val <= "010"; + when "1001011" => val <= "000"; + when "1001100" => val <= "110"; + when "1001101" => val <= "100"; + when "1001110" => val <= "111"; + when "1001111" => val <= "101"; + when "1010000" => val <= "011"; + when "1010001" => val <= "111"; + when "1010010" => val <= "001"; + when "1010011" => val <= "101"; + when "1010100" => val <= "001"; + when "1010101" => val <= "000"; + when "1010110" => val <= "101"; + when "1010111" => val <= "100"; + when "1011000" => val <= "110"; + when "1011001" => val <= "100"; + when "1011010" => val <= "010"; + when "1011011" => val <= "000"; + when "1011100" => val <= "000"; + when "1011101" => val <= "001"; + when "1011110" => val <= "010"; + when "1011111" => val <= "011"; + when "1100000" => val <= "110"; + when "1100001" => val <= "100"; + when "1100010" => val <= "010"; + when "1100011" => val <= "000"; + when "1100100" => val <= "000"; + when "1100101" => val <= "001"; + when "1100110" => val <= "010"; + when "1100111" => val <= "011"; + when "1101000" => val <= "001"; + when "1101001" => val <= "011"; + when "1101010" => val <= "101"; + when "1101011" => val <= "111"; + when "1101100" => val <= "110"; + when "1101101" => val <= "100"; + when "1101110" => val <= "010"; + when "1101111" => val <= "000"; + when "1110000" => val <= "101"; + when "1110001" => val <= "100"; + when "1110010" => val <= "001"; + when "1110011" => val <= "000"; + when "1110100" => val <= "101"; + when "1110101" => val <= "100"; + when "1110110" => val <= "001"; + when "1110111" => val <= "000"; + when "1111000" => val <= "001"; + when "1111001" => val <= "011"; + when "1111010" => val <= "101"; + when "1111011" => val <= "111"; + when "1111100" => val <= "110"; + when "1111101" => val <= "100"; + when "1111110" => val <= "010"; + when "1111111" => val <= "000"; + when others => null; + end case; + end if; + end process; +end rtl; diff --git a/Arcade/Pacman Hardware/Eyes_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Eyes_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Eyes_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.qpf b/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.qpf new file mode 100644 index 00000000..9705f206 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Gorkans" diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.qsf b/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.qsf new file mode 100644 index 00000000..c0468a5c --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Gorkans_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Gorkans.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Gorkans +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.srf b/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/Gorkans.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/README.txt b/Arcade/Pacman Hardware/Gorkans_MiST/README.txt new file mode 100644 index 00000000..1d5f4e4c --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Gorkans for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE,CTRL : Slowdown +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/Release/Gorkans.rbf b/Arcade/Pacman Hardware/Gorkans_MiST/Release/Gorkans.rbf new file mode 100644 index 00000000..9edb814a Binary files /dev/null and b/Arcade/Pacman Hardware/Gorkans_MiST/Release/Gorkans.rbf differ diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/clean.bat b/Arcade/Pacman Hardware/Gorkans_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv new file mode 100644 index 00000000..eb1b781e --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/Gorkans.sv @@ -0,0 +1,196 @@ +//============================================================================ +// Arcade: Gorkans +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Gorkans +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Gorkans;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +assign LED = 1; +//wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +//wire m_skip = kbjoy[9]; + + +pacman gorkans +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + + .dipsw1(8'b1_1_11_00_11), + .dipsw2(8'b11111111), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..c4a2de4f --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"EE",X"11",X"11",X"33",X"EE",X"CC",X"00",X"11",X"33",X"66",X"44",X"44",X"33",X"11",X"00", + X"11",X"11",X"FF",X"FF",X"11",X"11",X"00",X"00",X"00",X"00",X"77",X"77",X"22",X"00",X"00",X"00", + X"11",X"99",X"DD",X"DD",X"FF",X"77",X"33",X"00",X"33",X"77",X"55",X"44",X"44",X"66",X"22",X"00", + X"66",X"FF",X"99",X"99",X"99",X"33",X"22",X"00",X"44",X"66",X"77",X"55",X"44",X"44",X"00",X"00", + X"44",X"FF",X"FF",X"44",X"44",X"CC",X"CC",X"00",X"00",X"77",X"77",X"66",X"33",X"11",X"00",X"00", + X"EE",X"FF",X"11",X"11",X"11",X"33",X"22",X"00",X"00",X"55",X"55",X"55",X"55",X"77",X"77",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"EE",X"00",X"00",X"44",X"44",X"44",X"66",X"33",X"11",X"00", + X"00",X"00",X"88",X"FF",X"77",X"00",X"00",X"00",X"66",X"77",X"55",X"44",X"44",X"66",X"66",X"00", + X"66",X"77",X"DD",X"DD",X"99",X"99",X"66",X"00",X"00",X"33",X"44",X"44",X"55",X"77",X"33",X"00", + X"CC",X"EE",X"BB",X"99",X"99",X"99",X"00",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"33",X"00", + X"F0",X"F0",X"F0",X"FF",X"FF",X"F0",X"F0",X"F0",X"F1",X"F1",X"F1",X"FF",X"FF",X"F1",X"F1",X"F1", + X"F0",X"F0",X"F0",X"FF",X"FF",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"F1",X"F1",X"F1", + X"F0",X"F0",X"F0",X"FF",X"FF",X"F0",X"F0",X"F0",X"F1",X"F1",X"F1",X"F1",X"F1",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"FF",X"F1",X"F1",X"F1", + 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X"03",X"34",X"4A",X"7E",X"C0",X"F5",X"74",X"04",X"4A",X"CA",X"34",X"6A",X"75",X"26",X"B5",X"22", + X"34",X"4A",X"00",X"22",X"FE",X"6A",X"28",X"34",X"B3",X"05",X"F5",X"6D",X"0F",X"80",X"16",X"91", + X"FD",X"FD",X"24",X"FD",X"09",X"21",X"34",X"5B",X"00",X"FD",X"5A",X"02",X"FD",X"5F",X"01",X"6C", + X"43",X"FD",X"5B",X"04",X"FD",X"5A",X"03",X"FD",X"5F",X"34",X"6A",X"5F",X"05",X"F5",X"74",X"03", + X"6A",X"5F",X"34",X"B1",X"75",X"04",X"F5",X"6A",X"23",X"B2",X"FE",X"26",X"34",X"51",X"00",X"6A", + X"23",X"96",X"B3",X"F5",X"34",X"27",X"0F",X"16",X"05",X"09",X"91",X"34",X"80",X"24",X"FD",X"FD", + X"21",X"FD",X"5B",X"01",X"FD",X"5A",X"00",X"FD",X"5F",X"08",X"6C",X"61",X"02",X"00",X"09",X"BB", + X"FD",X"5A",X"03",X"FD",X"5B",X"04",X"FD",X"5F",X"05",X"F5",X"F2",X"03",X"93",X"7E",X"25",X"4A", + X"74",X"04",X"F5",X"75",X"34",X"4A",X"7E",X"34",X"93",X"F2",X"25",X"F5",X"AB",X"26",X"B5",X"7E", + X"03",X"25",X"93",X"F2",X"80",X"B5",X"8A",X"26",X"F5",X"4A",X"04",X"34",X"7E",X"75",X"C0",X"F5", + X"7E",X"34",X"4A",X"AB",X"03",X"93",X"74",X"25",X"B5",X"7E",X"26",X"80",X"F2",X"04",X"F5",X"60", + X"BB",X"91",X"7E",X"09",X"F5",X"FD",X"05",X"24",X"34",X"5B",X"21",X"FD",X"FD",X"00",X"FD",X"5A", + X"01",X"6A",X"5F",X"34",X"FD",X"74",X"02",X"F5",X"5F",X"34",X"6A",X"5F",X"03",X"F5",X"75",X"04", + X"F5",X"85",X"00",X"B3",X"7E",X"26",X"09",X"0F",X"B5",X"76",X"45",X"56",X"EA",X"0B",X"D5",X"BB", + X"D1",X"B9",X"7E",X"26",X"F5",X"C1",X"06",X"C1",X"26",X"26",X"26",X"26",X"C2",X"88",X"E5",X"8F", + X"26",X"5B",X"43",X"FD",X"B1",X"03",X"FD",X"5A",X"04",X"B1",X"5F",X"60",X"FD",X"63",X"05",X"DB", + X"09",X"BB",X"00",X"BC",X"08",X"60",X"61",X"BB",X"41",X"6F",X"00",X"52",X"08",X"BD",X"4F",X"BB", + X"60",X"34",X"6A",X"07",X"99",X"9E",X"74",X"4A",X"22",X"34",X"6A",X"07",X"34",X"9E",X"75",X"4A", + X"23",X"34",X"6A",X"6F",X"34",X"B3",X"74",X"B3",X"6F",X"6A",X"6F",X"34",X"B3",X"75",X"57",X"B3", + X"6F",X"6F",X"6F",X"B5",X"B3",X"77",X"B3",X"B9",X"44",X"01",X"F5",X"86",X"B1",X"F5",X"7E",X"02", + X"17",X"5F",X"27",X"B3",X"9E",X"02",X"F5",X"68",X"B3",X"B3",X"B3",X"B1",X"68",X"68",X"68",X"6A", + X"03",X"26",X"09",X"0F",X"35",X"B3",X"FD",X"B3",X"0F",X"B9",X"EA",X"B2",X"B5",X"B5",X"45",X"29", + X"B1",X"B1",X"0B",X"7C",X"B5",X"B5",X"2A",X"2A",X"B1",X"B1",X"D5",X"2E",X"B5",X"B5",X"2A",X"2B", + X"B1",X"B1",X"87",X"98",X"B5",X"B5",X"2B",X"2B",X"B1",X"B1",X"4E",X"A4",X"B5",X"B5",X"2C",X"2C", + X"B1",X"B1",X"9D",X"6E",X"B5",X"B5",X"2C",X"2D",X"B1",X"B1",X"A2",X"D6",X"B5",X"B5",X"2D",X"2D", + X"B1",X"B1",X"D7",X"F0",X"B5",X"B5",X"2D",X"2D",X"B1",X"B1",X"F1",X"4F",X"B5",X"D5",X"2D",X"6F", + X"09",X"00",X"01",X"52",X"26",X"BD",X"46",X"7D",X"4F",X"01",X"09",X"72",X"6F",X"D1",X"40",X"46", + X"00",X"77",X"52",X"7D",X"BD",X"B1",X"55",X"BE",X"03",X"C6",X"B1",X"B3",X"3F",X"34",X"09",X"16", + X"B0",X"13",X"3E",X"A8",X"B3",X"09",X"28",X"34",X"7B",X"0B",X"0F",X"A6",X"86",X"7A",X"5F",X"0F", + X"5F",X"A6",X"6E",X"5F",X"0B",X"0F",X"00",X"68",X"02",X"C6",X"4A",X"B3",X"60",X"34",X"09",X"3E", + X"28",X"13",X"09",X"DF",X"43",X"41",X"DE",X"13",X"01",X"10",X"00",X"C8",X"05",X"BD",X"4E",X"AF", + X"4A",X"60",X"13",X"9C",X"DE",X"09",X"60",X"13",X"41",X"05",X"13",X"4E",X"9D",X"00",X"01",X"10", + X"BD",X"9C",X"AF",X"60",X"C8",X"13",X"4A",X"05",X"09",X"EB",X"34",X"C6",X"AB",X"09",X"60",X"34", + X"B3",X"09",X"28",X"34",X"3E",X"AA",X"74",X"41",X"FB",X"34",X"6A",X"B5",X"13",X"DD",X"C9",X"63", + X"40",X"BB",X"0B",X"8B",X"0B",X"2A",X"0B",X"34",X"D9",X"B3",X"04",X"B3",X"FE",X"0F",X"D0",X"0F", + X"6C",X"45",X"B5",X"C8",X"6C",X"B5",X"EA",X"41",X"D0",X"6C",X"C8",X"C8",X"6A",X"4A",X"34",X"34", + X"09",X"96",X"35",X"C6",X"08",X"09",X"B3",X"34",X"B3",X"6A",X"28",X"34",X"3E",X"C9",X"42",X"6C", + X"4A",X"8E",X"34",X"6C",X"C9",X"34",X"6A",X"4A",X"8E",X"00",X"B5",X"6A",X"34",X"B1",X"43",X"CA"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..17522bd2 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..374e887f --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"AF",X"06",X"08",X"21",X"00",X"50",X"77",X"23",X"10",X"FC",X"ED",X"56",X"31",X"F1",X"4F", + X"C3",X"00",X"3F",X"3A",X"A6",X"4C",X"FE",X"00",X"C8",X"47",X"3E",X"18",X"21",X"1D",X"40",X"77", + X"2B",X"10",X"FC",X"C9",X"3A",X"A7",X"4C",X"FE",X"00",X"C8",X"47",X"3E",X"18",X"21",X"02",X"40", + X"77",X"23",X"10",X"FC",X"C9",X"D6",X"FF",X"00",X"08",X"D9",X"DD",X"E5",X"FD",X"E5",X"AF",X"32", + X"00",X"50",X"2A",X"0C",X"4C",X"3A",X"0E",X"4C",X"77",X"2A",X"0F",X"4C",X"3A",X"11",X"4C",X"77", + X"2A",X"14",X"4C",X"3A",X"16",X"4C",X"77",X"2A",X"17",X"4C",X"3A",X"19",X"4C",X"77",X"2A",X"1C", + X"4C",X"3A",X"1E",X"4C",X"77",X"2A",X"1F",X"4C",X"3A",X"21",X"4C",X"77",X"2A",X"24",X"4C",X"3A", + X"26",X"4C",X"77",X"2A",X"27",X"4C",X"3A",X"29",X"4C",X"77",X"2A",X"2C",X"4C",X"3A",X"2E",X"4C", + X"77",X"2A",X"2F",X"4C",X"3A",X"31",X"4C",X"77",X"2A",X"34",X"4C",X"3A",X"36",X"4C",X"77",X"2A", + X"37",X"4C",X"3A",X"39",X"4C",X"77",X"2A",X"3C",X"4C",X"3A",X"3E",X"4C",X"77",X"2A",X"3F",X"4C", + X"3A",X"41",X"4C",X"77",X"2A",X"44",X"4C",X"3A",X"46",X"4C",X"77",X"2A",X"47",X"4C",X"3A",X"49", + X"4C",X"77",X"2A",X"4C",X"4C",X"3A",X"4E",X"4C",X"77",X"2A",X"4F",X"4C",X"3A",X"51",X"4C",X"77", + X"2A",X"54",X"4C",X"3A",X"56",X"4C",X"77",X"2A",X"57",X"4C",X"3A",X"59",X"4C",X"77",X"21",X"96", + X"4C",X"CB",X"7E",X"28",X"31",X"CB",X"6E",X"20",X"2D",X"06",X"06",X"21",X"64",X"4C",X"11",X"62", + X"50",X"3E",X"06",X"0E",X"02",X"ED",X"A0",X"ED",X"A0",X"CD",X"BA",X"15",X"10",X"F3",X"06",X"06", + X"21",X"66",X"4C",X"11",X"F2",X"4F",X"3E",X"06",X"0E",X"02",X"ED",X"A0",X"ED",X"A0",X"CD",X"BA", + X"15",X"10",X"F3",X"C3",X"7E",X"01",X"ED",X"5B",X"64",X"4C",X"CD",X"3D",X"0F",X"ED",X"53",X"62", + X"50",X"ED",X"5B",X"6C",X"4C",X"CD",X"3D",X"0F",X"ED",X"53",X"64",X"50",X"ED",X"5B",X"74",X"4C", + X"CD",X"3D",X"0F",X"ED",X"53",X"66",X"50",X"ED",X"5B",X"7C",X"4C",X"CD",X"3D",X"0F",X"ED",X"53", + X"68",X"50",X"ED",X"5B",X"84",X"4C",X"CD",X"3D",X"0F",X"ED",X"53",X"6A",X"50",X"ED",X"5B",X"8C", + X"4C",X"CD",X"3D",X"0F",X"ED",X"53",X"6C",X"50",X"2A",X"66",X"4C",X"CD",X"56",X"0F",X"22",X"F2", + X"4F",X"2A",X"6E",X"4C",X"CD",X"56",X"0F",X"22",X"F4",X"4F",X"2A",X"76",X"4C",X"CD",X"56",X"0F", + X"22",X"F6",X"4F",X"2A",X"7E",X"4C",X"CD",X"56",X"0F",X"22",X"F8",X"4F",X"2A",X"86",X"4C",X"CD", + X"56",X"0F",X"22",X"FA",X"4F",X"2A",X"8E",X"4C",X"CD",X"56",X"0F",X"22",X"FC",X"4F",X"2A",X"93", + X"4C",X"23",X"22",X"93",X"4C",X"7E",X"FE",X"FF",X"20",X"06",X"21",X"DB",X"3C",X"22",X"93",X"4C", + X"21",X"95",X"4C",X"CB",X"46",X"20",X"56",X"3A",X"00",X"50",X"CB",X"6F",X"CA",X"2A",X"02",X"CB", + X"8E",X"CB",X"56",X"20",X"3D",X"3A",X"00",X"50",X"CB",X"7F",X"CA",X"38",X"02",X"3A",X"98",X"4C", + X"FE",X"06",X"28",X"07",X"3C",X"32",X"98",X"4C",X"C3",X"3D",X"02",X"AF",X"32",X"98",X"4C",X"CB", + X"5E",X"20",X"0A",X"3A",X"99",X"4C",X"FE",X"00",X"20",X"0B",X"C3",X"3D",X"02",X"AF",X"32",X"07", + X"50",X"CB",X"9E",X"18",X"68",X"3D",X"32",X"99",X"4C",X"3E",X"01",X"32",X"07",X"50",X"CB",X"DE", + X"18",X"5B",X"3A",X"00",X"50",X"CB",X"7F",X"28",X"C4",X"CB",X"96",X"18",X"10",X"3A",X"00",X"50", + X"CB",X"6F",X"28",X"AD",X"CB",X"86",X"3A",X"99",X"4C",X"3C",X"32",X"99",X"4C",X"3A",X"9A",X"4C", + X"FE",X"14",X"30",X"1A",X"47",X"3A",X"9C",X"4C",X"80",X"32",X"9A",X"4C",X"CB",X"3F",X"06",X"00", + X"80",X"27",X"32",X"9D",X"4C",X"CD",X"27",X"15",X"CB",X"66",X"20",X"02",X"CB",X"EE",X"3A",X"05", + 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X"03",X"00",X"00",X"06",X"03",X"00",X"03",X"00",X"00",X"06",X"03",X"00",X"00",X"09",X"00",X"FF", + X"4C",X"52",X"53",X"50",X"42",X"03",X"4D",X"43",X"53",X"60",X"17",X"03",X"4A",X"4D",X"53",X"20", + X"85",X"02",X"42",X"4F",X"40",X"90",X"76",X"02",X"4A",X"53",X"40",X"50",X"31",X"02",X"4A",X"46", + X"53",X"90",X"10",X"02",X"46",X"53",X"4D",X"00",X"05",X"02",X"43",X"53",X"4D",X"60",X"01",X"02", + X"43",X"44",X"40",X"80",X"98",X"01",X"48",X"44",X"43",X"40",X"86",X"01",X"07",X"10",X"03",X"12", + X"96",X"47",X"4F",X"52",X"4B",X"41",X"4E",X"53",X"2C",X"43",X"4F",X"50",X"59",X"52",X"49",X"47", + X"48",X"54",X"20",X"31",X"39",X"38",X"33",X"54",X"45",X"43",X"48",X"53",X"54",X"41",X"52",X"20", + X"49",X"4E",X"43",X"00",X"FF",X"00",X"FF",X"00",X"FB",X"00",X"E3",X"00",X"FF",X"00",X"FF",X"00", + X"3E",X"00",X"3E",X"00",X"FF",X"00",X"FF",X"00",X"3E",X"00",X"3E",X"00",X"FF",X"00",X"FF",X"00", + X"02",X"00",X"CB",X"00",X"FF",X"00",X"FF",X"00",X"DA",X"00",X"F3",X"00",X"FF",X"00",X"FF",X"00", + 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X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00", + X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..f07cb2ca --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is +begin + data <= X"FF"; +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/build_id.v new file mode 100644 index 00000000..8a430b5b --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171122" +`define BUILD_TIME "101343" diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..24d19966 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman.vhd @@ -0,0 +1,469 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- Copyright (c) Sorgelig - 2017 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN is + generic( + eight_sprites : boolean := false + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- sn1_l 0x5040 - 0x504F sound +-- sn2_l 0x5050 - 0x505F sound +-- spr_l 0x5060 - 0x506F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"4" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"5" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"6" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - bfff + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(11 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..91313469 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pll.v b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Gorkans_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Gorkans_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf new file mode 100644 index 00000000..9dca993d --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "LizardWizard" diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf new file mode 100644 index 00000000..96599caf --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/LizardWizard.qsf @@ -0,0 +1,164 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 06:32:21 November 16, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# LizardWizard_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/LizardWizard.sv +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY LizardWizard + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------------- +# start ENTITY(LizardWizard) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(LizardWizard) +# ------------------------ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/README.txt b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/README.txt new file mode 100644 index 00000000..481e4e1b --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Lizzard Wizzard port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/Release/LizardWizard.rbf b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/Release/LizardWizard.rbf new file mode 100644 index 00000000..fadf4eb4 Binary files /dev/null and b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/Release/LizardWizard.rbf differ diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/clean.bat b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv new file mode 100644 index 00000000..45bd82bd --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/LizardWizard.sv @@ -0,0 +1,192 @@ +//============================================================================ +// Arcade: LizardWizard +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module LizardWizard +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Liz. Wizard;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(reset), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [15:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire rde, rhs, rvs; +wire [2:0] r,g,rr,rg; +wire [1:0] b,rb; +wire reset = status[0] | status[6] | buttons[1]; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(~reset), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +pacman LizardWizard +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + .dipsw_reg(8'b0_1_11_00_11), + + .RESET(reset), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(~reset), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..491ed13a --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"EE",X"11",X"11",X"33",X"EE",X"CC",X"00",X"11",X"33",X"66",X"44",X"44",X"33",X"11",X"00", + X"11",X"11",X"FF",X"FF",X"11",X"11",X"00",X"00",X"00",X"00",X"77",X"77",X"22",X"00",X"00",X"00", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..aabaa143 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"01",X"0C",X"0F",X"00",X"05",X"03",X"09",X"00",X"07",X"02",X"08", + X"00",X"0D",X"06",X"0E",X"00",X"0B",X"01",X"0A",X"00",X"04",X"03",X"09",X"00",X"06",X"04",X"09", + X"00",X"0B",X"09",X"04",X"00",X"0A",X"04",X"09",X"00",X"0D",X"01",X"06",X"00",X"05",X"03",X"00", + X"00",X"05",X"01",X"02",X"00",X"05",X"07",X"02",X"00",X"05",X"03",X"0D",X"00",X"03",X"05",X"01", + X"00",X"05",X"07",X"01",X"00",X"00",X"04",X"09",X"00",X"05",X"04",X"09",X"01",X"05",X"04",X"09", + X"00",X"01",X"04",X"09",X"0D",X"0D",X"04",X"09",X"02",X"02",X"04",X"09",X"01",X"0A",X"04",X"09", + X"00",X"02",X"08",X"0F",X"00",X"0B",X"0A",X"0F",X"00",X"05",X"04",X"03",X"00",X"0A",X"0A",X"0A", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..85afc9ad --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"62",X"85",X"2F",X"07",X"1D",X"28",X"8C",X"C7",X"3F",X"F8",X"C9",X"AC",X"18",X"38",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..b384853d --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"F1",X"4F",X"C3",X"59",X"00",X"21",X"16",X"40",X"11",X"17",X"40",X"01",X"08",X"00",X"36", + X"40",X"ED",X"B0",X"3A",X"A1",X"4D",X"FE",X"00",X"C8",X"47",X"3E",X"3A",X"21",X"1D",X"40",X"77", + X"2B",X"10",X"FC",X"C9",X"00",X"08",X"0A",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C3",X"08",X"0A",X"21",X"02",X"40",X"11",X"03", + X"40",X"01",X"08",X"00",X"36",X"40",X"ED",X"B0",X"3A",X"A2",X"4D",X"FE",X"00",X"C8",X"47",X"3E", + X"3A",X"21",X"02",X"40",X"77",X"23",X"10",X"FC",X"C9",X"AF",X"06",X"08",X"21",X"00",X"50",X"77", + X"23",X"10",X"FC",X"3A",X"00",X"50",X"CB",X"67",X"C2",X"57",X"03",X"AF",X"06",X"08",X"21",X"00", + X"50",X"77",X"23",X"10",X"FC",X"C3",X"95",X"00",X"06",X"03",X"0E",X"0F",X"3E",X"21",X"ED",X"A0", + X"CD",X"52",X"16",X"10",X"F7",X"23",X"23",X"3E",X"40",X"CD",X"52",X"16",X"CD",X"9C",X"11",X"3E", + X"04",X"CD",X"E3",X"15",X"C9",X"3E",X"00",X"32",X"03",X"50",X"31",X"F1",X"4F",X"CD",X"24",X"12", + X"F3",X"08",X"AF",X"08",X"21",X"00",X"40",X"CD",X"D2",X"02",X"08",X"CB",X"47",X"28",X"02",X"CB", + X"D7",X"CB",X"4F",X"28",X"02",X"CB",X"DF",X"08",X"21",X"00",X"44",X"CD",X"D2",X"02",X"08",X"CB", + X"47",X"28",X"02",X"CB",X"E7",X"CB",X"4F",X"28",X"02",X"CB",X"EF",X"08",X"31",X"FD",X"43",X"21", + X"00",X"4C",X"CD",X"D2",X"02",X"08",X"CB",X"47",X"28",X"02",X"CB",X"F7",X"CB",X"4F",X"28",X"02", + X"CB",X"FF",X"08",X"3E",X"01",X"CD",X"55",X"15",X"21",X"00",X"40",X"11",X"01",X"40",X"01",X"FE", + X"03",X"36",X"40",X"ED",X"B0",X"11",X"66",X"41",X"21",X"ED",X"1B",X"3E",X"01",X"06",X"0B",X"CD", + X"66",X"16",X"11",X"8A",X"40",X"21",X"F8",X"1B",X"3E",X"01",X"06",X"18",X"CD",X"66",X"16",X"11", + X"EC",X"40",X"21",X"10",X"1C",X"3E",X"01",X"06",X"14",X"CD",X"66",X"16",X"11",X"ED",X"40",X"21", + X"24",X"1C",X"3E",X"01",X"06",X"14",X"CD",X"66",X"16",X"11",X"EE",X"40",X"21",X"38",X"1C",X"3E", + X"01",X"06",X"14",X"CD",X"66",X"16",X"11",X"EF",X"40",X"21",X"4C",X"1C",X"3E",X"01",X"06",X"14", + X"CD",X"66",X"16",X"11",X"93",X"40",X"21",X"DC",X"1C",X"3E",X"01",X"06",X"18",X"CD",X"66",X"16", + X"11",X"F5",X"40",X"21",X"60",X"1C",X"3E",X"01",X"06",X"14",X"CD",X"66",X"16",X"11",X"F6",X"40", + X"21",X"74",X"1C",X"3E",X"01",X"06",X"14",X"CD",X"66",X"16",X"11",X"F7",X"40",X"21",X"88",X"1C", + X"3E",X"01",X"06",X"14",X"CD",X"66",X"16",X"11",X"F8",X"40",X"21",X"9C",X"1C",X"3E",X"01",X"06", + X"14",X"CD",X"66",X"16",X"11",X"F9",X"40",X"21",X"B0",X"1C",X"3E",X"01",X"06",X"14",X"CD",X"66", + X"16",X"11",X"FA",X"40",X"21",X"C4",X"1C",X"3E",X"01",X"06",X"14",X"CD",X"66",X"16",X"08",X"32", + X"FB",X"4D",X"08",X"3A",X"FB",X"4D",X"CB",X"57",X"28",X"0D",X"11",X"F5",X"40",X"21",X"D8",X"1C", + X"3E",X"01",X"06",X"04",X"CD",X"66",X"16",X"3A",X"FB",X"4D",X"CB",X"5F",X"28",X"0D",X"11",X"F6", + X"40",X"21",X"D8",X"1C",X"3E",X"01",X"06",X"04",X"CD",X"66",X"16",X"3A",X"FB",X"4D",X"CB",X"67", + X"28",X"0D",X"11",X"F7",X"40",X"21",X"D8",X"1C",X"3E",X"01",X"06",X"04",X"CD",X"66",X"16",X"3A", + X"FB",X"4D",X"CB",X"6F",X"28",X"0D",X"11",X"F8",X"40",X"21",X"D8",X"1C",X"3E",X"01",X"06",X"04", + X"CD",X"66",X"16",X"3A",X"FB",X"4D",X"CB",X"77",X"28",X"0D",X"11",X"F9",X"40",X"21",X"D8",X"1C", + X"3E",X"01",X"06",X"04",X"CD",X"66",X"16",X"3A",X"FB",X"4D",X"CB",X"7F",X"28",X"0D",X"11",X"FA", + X"40",X"21",X"D8",X"1C",X"3E",X"01",X"06",X"04",X"CD",X"66",X"16",X"1E",X"00",X"21",X"00",X"00", + X"CD",X"B9",X"02",X"30",X"02",X"CB",X"C3",X"21",X"00",X"10",X"CD",X"B9",X"02",X"30",X"02",X"CB", + X"CB",X"21",X"00",X"20",X"CD",X"B9",X"02",X"30",X"02",X"CB",X"D3",X"21",X"00",X"30",X"CD",X"B9", + X"02",X"30",X"02",X"CB",X"DB",X"3A",X"FB",X"4D",X"FE",X"00",X"28",X"02",X"3E",X"80",X"B3",X"32", + X"FB",X"4D",X"CB",X"47",X"28",X"0D",X"11",X"EC",X"40",X"21",X"D8",X"1C",X"3E",X"01",X"06",X"04", + X"CD",X"66",X"16",X"3A",X"FB",X"4D",X"CB",X"4F",X"28",X"0D",X"11",X"ED",X"40",X"21",X"D8",X"1C", + X"3E",X"01",X"06",X"04",X"CD",X"66",X"16",X"3A",X"FB",X"4D",X"CB",X"57",X"28",X"0D",X"11",X"EE", + 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X"50",X"4C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"58",X"85",X"11",X"60",X"4C",X"01",X"10",X"00", + X"ED",X"B0",X"21",X"58",X"85",X"11",X"70",X"4C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"58",X"85", + X"11",X"80",X"4C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"58",X"85",X"11",X"90",X"4C",X"01",X"10", + X"00",X"ED",X"B0",X"3E",X"FF",X"32",X"09",X"4F",X"3E",X"D0",X"32",X"59",X"4D",X"3E",X"09",X"32"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..c5abd4b0 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3E",X"9A",X"CD",X"45",X"15",X"3E",X"02",X"CD",X"55",X"15",X"21",X"6C",X"88",X"11",X"F9",X"4C", + X"01",X"07",X"00",X"ED",X"B0",X"21",X"84",X"88",X"11",X"11",X"4D",X"01",X"14",X"00",X"ED",X"B0", + X"3A",X"36",X"4D",X"21",X"84",X"88",X"11",X"29",X"4D",X"01",X"14",X"00",X"ED",X"B0",X"32",X"36", + X"4D",X"3A",X"27",X"4F",X"32",X"30",X"4D",X"3A",X"4E",X"4D",X"21",X"84",X"88",X"11",X"41",X"4D", + X"01",X"14",X"00",X"ED",X"B0",X"32",X"4E",X"4D",X"3A",X"28",X"4F",X"32",X"48",X"4D",X"21",X"6C", + X"88",X"11",X"59",X"4D",X"01",X"18",X"00",X"ED",X"B0",X"21",X"6C",X"88",X"11",X"71",X"4D",X"01", + X"18",X"00",X"ED",X"B0",X"21",X"58",X"85",X"11",X"00",X"4C",X"01",X"10",X"00",X"ED",X"B0",X"21", + X"58",X"85",X"11",X"10",X"4C",X"01",X"10",X"00",X"ED",X"B0",X"21",X"58",X"85",X"11",X"20",X"4C", + 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X"DD",X"36",X"00",X"04",X"C9",X"DD",X"36",X"00",X"05",X"C9",X"DD",X"36",X"00",X"00",X"DD",X"36", + X"01",X"00",X"2A",X"8E",X"4D",X"CB",X"46",X"CA",X"9F",X"1E",X"DD",X"36",X"05",X"BE",X"C9",X"DD", + X"36",X"05",X"BD",X"C9",X"D4",X"1E",X"E3",X"1E",X"F2",X"1E",X"01",X"1F",X"10",X"1F",X"1F",X"1F", + X"2E",X"1F",X"3D",X"1F",X"4C",X"1F",X"5B",X"1F",X"6A",X"1F",X"79",X"1F",X"88",X"1F",X"97",X"1F", + X"A6",X"1F",X"B5",X"1F",X"C4",X"1F",X"D3",X"1F",X"E2",X"1F",X"F1",X"1F",X"00",X"20",X"0F",X"20", + X"1E",X"20",X"2D",X"20",X"DD",X"36",X"07",X"D0",X"DD",X"36",X"08",X"F8",X"DD",X"36",X"09",X"01", + X"C3",X"36",X"1E",X"DD",X"36",X"07",X"98",X"DD",X"36",X"08",X"E8",X"DD",X"36",X"09",X"02",X"C3", + X"36",X"1E",X"DD",X"36",X"07",X"C8",X"DD",X"36",X"08",X"E8",X"DD",X"36",X"09",X"03",X"C3",X"36", + X"1E",X"DD",X"36",X"07",X"D0",X"DD",X"36",X"08",X"E0",X"DD",X"36",X"09",X"04",X"C3",X"36",X"1E", + X"DD",X"36",X"07",X"A0",X"DD",X"36",X"08",X"E0",X"DD",X"36",X"09",X"05",X"C3",X"36",X"1E",X"DD", + X"36",X"07",X"A0",X"DD",X"36",X"08",X"F8",X"DD",X"36",X"09",X"06",X"C3",X"36",X"1E",X"DD",X"36", + X"07",X"D8",X"DD",X"36",X"08",X"F0",X"DD",X"36",X"09",X"07",X"C3",X"36",X"1E",X"DD",X"36",X"07", + X"B8",X"DD",X"36",X"08",X"F8",X"DD",X"36",X"09",X"08",X"C3",X"36",X"1E",X"DD",X"36",X"07",X"A8", + X"DD",X"36",X"08",X"F0",X"DD",X"36",X"09",X"09",X"C3",X"36",X"1E",X"DD",X"36",X"07",X"C8",X"DD", + X"36",X"08",X"F0",X"DD",X"36",X"09",X"0A",X"C3",X"36",X"1E",X"DD",X"36",X"07",X"B0",X"DD",X"36", + X"08",X"E8",X"DD",X"36",X"09",X"0B",X"C3",X"36",X"1E",X"DD",X"36",X"07",X"B8",X"DD",X"36",X"08", + X"E0",X"DD",X"36",X"09",X"0B",X"C3",X"36",X"1E",X"DD",X"36",X"07",X"08",X"DD",X"36",X"08",X"F8", + X"DD",X"36",X"09",X"01",X"C3",X"39",X"20",X"DD",X"36",X"07",X"40",X"DD",X"36",X"08",X"E8",X"DD", + X"36",X"09",X"02",X"C3",X"39",X"20",X"DD",X"36",X"07",X"10",X"DD",X"36",X"08",X"E8",X"DD",X"36", + X"09",X"03",X"C3",X"39",X"20",X"DD",X"36",X"07",X"08",X"DD",X"36",X"08",X"E0",X"DD",X"36",X"09", + X"04",X"C3",X"39",X"20",X"DD",X"36",X"07",X"38",X"DD",X"36",X"08",X"E0",X"DD",X"36",X"09",X"05", + X"C3",X"39",X"20",X"DD",X"36",X"07",X"38",X"DD",X"36",X"08",X"F8",X"DD",X"36",X"09",X"06",X"C3", + X"39",X"20",X"DD",X"36",X"07",X"00",X"DD",X"36",X"08",X"F0",X"DD",X"36",X"09",X"07",X"C3",X"39", + X"20",X"DD",X"36",X"07",X"20",X"DD",X"36",X"7D",X"F8",X"DD",X"36",X"09",X"08",X"C3",X"39",X"0A"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.v new file mode 100644 index 00000000..7ec8a835 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171116" +`define BUILD_TIME "063224" diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..8325fe34 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman.vhd @@ -0,0 +1,629 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data_out : std_logic_vector(7 downto 0); + signal rom_data : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + rom_data <= program_rom_dinl when cpu_addr(15) = '0' else program_rom_dinh; + rom_data_out <= rom_data(7 downto 6) & rom_data(3) & rom_data(4) & rom_data(5) & rom_data(2 downto 0) when MRTNT = '1' else rom_data; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data_out, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data_out; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data_out; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => clk, + ADDR => cpu_addr(12 downto 0), + DATA => program_rom_dinh + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..895304e9 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_video.vhd @@ -0,0 +1,366 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Lizard_Wizard_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/ManiacMiner.qpf b/Arcade/Pacman Hardware/ManiacMiner_MiST/ManiacMiner.qpf new file mode 100644 index 00000000..9494ecc3 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/ManiacMiner.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "ManiacMiner" diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/ManiacMiner.qsf b/Arcade/Pacman Hardware/ManiacMiner_MiST/ManiacMiner.qsf new file mode 100644 index 00000000..ac408316 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/ManiacMiner.qsf @@ -0,0 +1,172 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:11:01 November 12, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ManiacMiner_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom7_dst.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom4_dst.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom3_dst.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/prom1_dst.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/gfx1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_rom_descrambler.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ManiacMiner.sv +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/sega_decode.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY ManiacMiner +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------- +# start ENTITY(ManiacMiner) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(ManiacMiner) +# ----------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/README.txt b/Arcade/Pacman Hardware/ManiacMiner_MiST/README.txt new file mode 100644 index 00000000..894c6c9e --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/README.txt @@ -0,0 +1,22 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Pacmanic Miner port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/Release/ManiacMiner.rbf b/Arcade/Pacman Hardware/ManiacMiner_MiST/Release/ManiacMiner.rbf new file mode 100644 index 00000000..ab3090f2 Binary files /dev/null and b/Arcade/Pacman Hardware/ManiacMiner_MiST/Release/ManiacMiner.rbf differ diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/clean.bat b/Arcade/Pacman Hardware/ManiacMiner_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ManiacMiner.sv b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ManiacMiner.sv new file mode 100644 index 00000000..53e42f31 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ManiacMiner.sv @@ -0,0 +1,198 @@ +//============================================================================ +// Arcade: ManiacMiner +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module ManiacMiner +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "M.Miner;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", +// "T5,Music;", +// "T6,Sound FX;", + "T7,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(reset), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire rde, rhs, rvs; +wire [2:0] r,g,rr,rg; +wire [1:0] b,rb; +wire reset = status[0] | status[7] | buttons[1]; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(~reset), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_jump = kbjoy[8] | m_up; +wire m_fx ;//= status[6]; +wire m_music = kbjoy[9]; + +PACMAN_MACHINE mminer +( + .video_r(r), + .video_g(g), + .video_b(b), + .hsync(hs), + .vsync(vs), + .h_blank(hblank), + .v_blank(vblank), + + .audio(audio), +// .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), +// .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + .in0_reg(~{2'b00, m_coin, 1'b0, m_down, m_right, m_left, m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, m_fx, m_jump, 1'b0, m_music}), + .dipsw1_reg(8'b0_1_00_11_01), + + .RESET(reset), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(~reset), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..aed0a451 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,2077 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ROM_PGM_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM_0 is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"C3",x"01",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x0000 + x"77",x"23",x"10",x"FC",x"C9",x"00",x"00",x"00", -- 0x0008 + x"85",x"6F",x"8C",x"95",x"67",x"7E",x"C9",x"00", -- 0x0010 + x"78",x"87",x"D7",x"5F",x"23",x"56",x"EB",x"C9", -- 0x0018 + x"E1",x"87",x"D7",x"5F",x"23",x"56",x"EB",x"E9", -- 0x0020 + x"ED",x"B0",x"AF",x"32",x"C0",x"50",x"C9",x"00", -- 0x0028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0030 + x"C3",x"68",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0058 + x"00",x"00",x"00",x"00",x"00",x"00",x"ED",x"45", -- 0x0060 + x"F3",x"F5",x"DD",x"E5",x"E5",x"D5",x"C5",x"AF", -- 0x0068 + x"32",x"00",x"50",x"32",x"C0",x"50",x"2A",x"00", -- 0x0070 + x"4C",x"23",x"22",x"00",x"4C",x"3E",x"00",x"B7", -- 0x0078 + x"C2",x"EE",x"00",x"21",x"53",x"4C",x"11",x"F2", -- 0x0080 + x"4F",x"01",x"0C",x"00",x"EF",x"11",x"04",x"00", -- 0x0088 + x"19",x"11",x"62",x"50",x"01",x"0C",x"00",x"EF", -- 0x0090 + x"3A",x"1B",x"4C",x"3C",x"32",x"1B",x"4C",x"E6", -- 0x0098 + x"01",x"28",x"1C",x"2A",x"51",x"4C",x"ED",x"5B", -- 0x00A0 + x"61",x"4C",x"22",x"FA",x"4F",x"ED",x"53",x"6A", -- 0x00A8 + x"50",x"2A",x"5F",x"4C",x"ED",x"5B",x"6F",x"4C", -- 0x00B0 + x"22",x"FC",x"4F",x"ED",x"53",x"6C",x"50",x"3A", -- 0x00B8 + x"50",x"4C",x"B7",x"28",x"14",x"AF",x"32",x"1C", -- 0x00C0 + x"4C",x"AF",x"32",x"50",x"4C",x"CD",x"DD",x"0C", -- 0x00C8 + x"CD",x"DC",x"0C",x"CD",x"B7",x"0C",x"CD",x"92", -- 0x00D0 + x"07",x"CD",x"AF",x"12",x"AF",x"32",x"C0",x"50", -- 0x00D8 + x"3E",x"01",x"32",x"00",x"50",x"C1",x"D1",x"E1", -- 0x00E0 + x"DD",x"E1",x"F1",x"FB",x"ED",x"4D",x"21",x"51", -- 0x00E8 + x"4C",x"11",x"F0",x"4F",x"01",x"10",x"00",x"EF", -- 0x00F0 + x"11",x"60",x"50",x"01",x"10",x"00",x"EF",x"18", -- 0x00F8 + x"BE",x"F3",x"31",x"F0",x"4F",x"ED",x"56",x"3E", -- 0x0100 + x"FF",x"D3",x"00",x"AF",x"21",x"00",x"50",x"01", -- 0x0108 + x"08",x"08",x"CF",x"AF",x"32",x"C0",x"50",x"21", -- 0x0110 + x"00",x"4C",x"06",x"BE",x"CF",x"CF",x"CF",x"CF", -- 0x0118 + x"3E",x"0F",x"32",x"4C",x"4C",x"32",x"4D",x"4C", -- 0x0120 + x"21",x"0D",x"4C",x"11",x"0E",x"4C",x"01",x"0C", -- 0x0128 + x"00",x"36",x"30",x"EF",x"AF",x"12",x"32",x"13", -- 0x0130 + x"4C",x"21",x"CE",x"FA",x"22",x"02",x"4C",x"21", -- 0x0138 + x"40",x"50",x"06",x"40",x"CF",x"3E",x"01",x"32", -- 0x0140 + x"00",x"50",x"FB",x"AF",x"32",x"C0",x"50",x"32", -- 0x0148 + x"48",x"4C",x"32",x"49",x"4C",x"32",x"4A",x"4C", -- 0x0150 + x"3E",x"01",x"32",x"1D",x"4C",x"3E",x"68",x"32", -- 0x0158 + x"1E",x"4C",x"3E",x"00",x"32",x"1F",x"4C",x"3E", -- 0x0160 + x"01",x"32",x"20",x"4C",x"AF",x"32",x"24",x"4C", -- 0x0168 + x"32",x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C", -- 0x0170 + x"AF",x"32",x"50",x"4C",x"32",x"48",x"4C",x"32", -- 0x0178 + x"49",x"4C",x"32",x"4A",x"4C",x"3E",x"01",x"CD", -- 0x0180 + x"A2",x"12",x"CD",x"24",x"0F",x"3A",x"0B",x"4C", -- 0x0188 + x"B7",x"20",x"14",x"21",x"D9",x"11",x"11",x"BC", -- 0x0190 + x"43",x"0E",x"01",x"CD",x"93",x"0B",x"CD",x"83", -- 0x0198 + x"0B",x"3A",x"0B",x"4C",x"B7",x"28",x"F7",x"21", -- 0x01A0 + x"BD",x"11",x"11",x"BC",x"43",x"0E",x"01",x"CD", -- 0x01A8 + x"93",x"0B",x"CD",x"83",x"0B",x"3A",x"09",x"4C", -- 0x01B0 + x"E6",x"20",x"28",x"F6",x"3A",x"0B",x"4C",x"3D", -- 0x01B8 + x"32",x"0B",x"4C",x"3E",x"02",x"CD",x"A2",x"12", -- 0x01C0 + x"3E",x"00",x"32",x"2F",x"4C",x"3E",x"05",x"32", -- 0x01C8 + x"27",x"4C",x"21",x"0D",x"4C",x"11",x"0E",x"4C", -- 0x01D0 + x"01",x"05",x"00",x"36",x"30",x"EF",x"AF",x"12", -- 0x01D8 + x"3A",x"2F",x"4C",x"CD",x"1B",x"0D",x"AF",x"32", -- 0x01E0 + x"24",x"4C",x"CD",x"E2",x"26",x"AF",x"32",x"2B", -- 0x01E8 + x"4C",x"3A",x"30",x"4C",x"3C",x"32",x"30",x"4C", -- 0x01F0 + x"3E",x"01",x"32",x"0A",x"4C",x"CD",x"83",x"0B", -- 0x01F8 + x"CD",x"83",x"0B",x"CD",x"83",x"0B",x"AF",x"32", -- 0x0200 + x"0A",x"4C",x"CD",x"83",x"0B",x"3A",x"2E",x"4C", -- 0x0208 + x"3C",x"FE",x"06",x"38",x"0F",x"CD",x"3C",x"0B", -- 0x0210 + x"3A",x"39",x"4C",x"B7",x"20",x"05",x"3E",x"02", -- 0x0218 + x"32",x"2B",x"4C",x"AF",x"32",x"2E",x"4C",x"3A", -- 0x0220 + x"31",x"4C",x"32",x"33",x"4C",x"3A",x"32",x"4C", -- 0x0228 + x"32",x"34",x"4C",x"3A",x"04",x"4C",x"32",x"31", -- 0x0230 + x"4C",x"3A",x"05",x"4C",x"32",x"32",x"4C",x"ED", -- 0x0238 + x"5B",x"1D",x"4C",x"7A",x"C6",x"10",x"57",x"CD", -- 0x0240 + x"4B",x"0C",x"20",x"0E",x"ED",x"5B",x"1D",x"4C", -- 0x0248 + x"1C",x"7A",x"C6",x"10",x"57",x"CD",x"4B",x"0C", -- 0x0250 + x"28",x"41",x"3A",x"2C",x"4C",x"FE",x"00",x"28", -- 0x0258 + x"1E",x"3A",x"1F",x"4C",x"E6",x"02",x"28",x"08", -- 0x0260 + x"3A",x"31",x"4C",x"2F",x"E6",x"02",x"20",x"0D", -- 0x0268 + x"3A",x"31",x"4C",x"E6",x"FB",x"F6",x"02",x"32", -- 0x0270 + x"31",x"4C",x"32",x"26",x"4C",x"18",x"1C",x"3A", -- 0x0278 + x"1F",x"4C",x"E6",x"02",x"20",x"08",x"3A",x"31", -- 0x0280 + x"4C",x"2F",x"E6",x"04",x"20",x"0D",x"3A",x"31", -- 0x0288 + x"4C",x"E6",x"FD",x"F6",x"04",x"32",x"31",x"4C", -- 0x0290 + x"32",x"26",x"4C",x"3A",x"24",x"4C",x"B7",x"28", -- 0x0298 + x"06",x"3A",x"25",x"4C",x"32",x"31",x"4C",x"3A", -- 0x02A0 + x"31",x"4C",x"CB",x"4F",x"20",x"6F",x"F6",x"04", -- 0x02A8 + x"32",x"31",x"4C",x"32",x"26",x"4C",x"32",x"25", -- 0x02B0 + x"4C",x"3A",x"1F",x"4C",x"CB",x"4F",x"20",x"10", -- 0x02B8 + x"3A",x"31",x"4C",x"F6",x"02",x"32",x"31",x"4C", -- 0x02C0 + x"32",x"26",x"4C",x"32",x"25",x"4C",x"18",x"45", -- 0x02C8 + x"D6",x"04",x"E6",x"0F",x"32",x"1F",x"4C",x"FE", -- 0x02D0 + x"0E",x"20",x"3A",x"ED",x"5B",x"1D",x"4C",x"1D", -- 0x02D8 + x"CD",x"3A",x"0C",x"20",x"2B",x"ED",x"5B",x"1D", -- 0x02E0 + x"4C",x"1D",x"7A",x"C6",x"08",x"57",x"CD",x"3A", -- 0x02E8 + x"0C",x"20",x"1D",x"ED",x"5B",x"1D",x"4C",x"1D", -- 0x02F0 + x"7A",x"C6",x"0F",x"57",x"CD",x"3A",x"0C",x"20", -- 0x02F8 + x"0F",x"3A",x"1D",x"4C",x"3D",x"32",x"1D",x"4C", -- 0x0300 + x"FE",x"FF",x"20",x"11",x"3C",x"32",x"1D",x"4C", -- 0x0308 + x"3E",x"02",x"32",x"1F",x"4C",x"3A",x"1F",x"4C", -- 0x0310 + x"F6",x"02",x"32",x"1F",x"4C",x"3A",x"31",x"4C", -- 0x0318 + x"CB",x"57",x"20",x"70",x"F6",x"02",x"32",x"31", -- 0x0320 + x"4C",x"32",x"26",x"4C",x"32",x"25",x"4C",x"3A", -- 0x0328 + x"1F",x"4C",x"CB",x"4F",x"28",x"10",x"3A",x"31", -- 0x0330 + x"4C",x"F6",x"04",x"32",x"31",x"4C",x"32",x"26", -- 0x0338 + x"4C",x"32",x"25",x"4C",x"18",x"46",x"C6",x"04", -- 0x0340 + x"E6",x"0F",x"32",x"1F",x"4C",x"20",x"3D",x"ED", -- 0x0348 + x"5B",x"1D",x"4C",x"1C",x"1C",x"CD",x"3A",x"0C", -- 0x0350 + x"20",x"2D",x"ED",x"5B",x"1D",x"4C",x"1C",x"1C", -- 0x0358 + x"7A",x"C6",x"08",x"57",x"CD",x"3A",x"0C",x"20", -- 0x0360 + x"1E",x"ED",x"5B",x"1D",x"4C",x"1C",x"1C",x"7A", -- 0x0368 + x"C6",x"0F",x"57",x"CD",x"3A",x"0C",x"20",x"0F", -- 0x0370 + x"3A",x"1D",x"4C",x"3C",x"FE",x"1B",x"32",x"1D", -- 0x0378 + x"4C",x"20",x"11",x"3D",x"32",x"1D",x"4C",x"3E", -- 0x0380 + x"0C",x"32",x"1F",x"4C",x"3A",x"1F",x"4C",x"E6", -- 0x0388 + x"FD",x"32",x"1F",x"4C",x"3A",x"32",x"4C",x"CB", -- 0x0390 + x"57",x"20",x"25",x"3A",x"24",x"4C",x"B7",x"20", -- 0x0398 + x"1F",x"AF",x"32",x"23",x"4C",x"3E",x"01",x"32", -- 0x03A0 + x"24",x"4C",x"3E",x"FC",x"32",x"22",x"4C",x"3A", -- 0x03A8 + x"1E",x"4C",x"32",x"28",x"4C",x"3A",x"31",x"4C", -- 0x03B0 + x"32",x"25",x"4C",x"3E",x"01",x"32",x"2A",x"4C", -- 0x03B8 + x"3A",x"24",x"4C",x"B7",x"CA",x"BB",x"04",x"3C", -- 0x03C0 + x"32",x"24",x"4C",x"ED",x"5B",x"22",x"4C",x"3A", -- 0x03C8 + x"1E",x"4C",x"83",x"32",x"1E",x"4C",x"3A",x"24", -- 0x03D0 + x"4C",x"E6",x"01",x"28",x"0D",x"7B",x"CB",x"7F", -- 0x03D8 + x"20",x"04",x"FE",x"04",x"30",x"04",x"3C",x"32", -- 0x03E0 + x"22",x"4C",x"3A",x"22",x"4C",x"CB",x"7F",x"C2", -- 0x03E8 + x"53",x"04",x"FE",x"03",x"38",x"5D",x"ED",x"5B", -- 0x03F0 + x"1D",x"4C",x"7A",x"C6",x"10",x"57",x"CD",x"1B", -- 0x03F8 + x"0C",x"28",x"20",x"AF",x"32",x"22",x"4C",x"32", -- 0x0400 + x"24",x"4C",x"3A",x"1E",x"4C",x"E6",x"F8",x"32", -- 0x0408 + x"1E",x"4C",x"3A",x"28",x"4C",x"C6",x"18",x"5F", -- 0x0410 + x"3A",x"1E",x"4C",x"BB",x"38",x"05",x"3E",x"02", -- 0x0418 + x"32",x"2B",x"4C",x"ED",x"5B",x"1D",x"4C",x"1C", -- 0x0420 + x"7A",x"C6",x"10",x"57",x"CD",x"1B",x"0C",x"28", -- 0x0428 + x"20",x"AF",x"32",x"22",x"4C",x"32",x"24",x"4C", -- 0x0430 + x"3A",x"1E",x"4C",x"E6",x"F8",x"32",x"1E",x"4C", -- 0x0438 + x"3A",x"28",x"4C",x"C6",x"18",x"5F",x"3A",x"1E", -- 0x0440 + x"4C",x"BB",x"38",x"05",x"3E",x"02",x"32",x"2B", -- 0x0448 + x"4C",x"18",x"56",x"ED",x"5B",x"1D",x"4C",x"15", -- 0x0450 + x"CD",x"3A",x"0C",x"20",x"0B",x"ED",x"5B",x"1D", -- 0x0458 + x"4C",x"1C",x"15",x"CD",x"3A",x"0C",x"28",x"41", -- 0x0460 + x"3A",x"22",x"4C",x"CB",x"7F",x"28",x"3A",x"AF", -- 0x0468 + x"32",x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C", -- 0x0470 + x"32",x"26",x"4C",x"3A",x"1E",x"4C",x"3D",x"E6", -- 0x0478 + x"78",x"C6",x"08",x"32",x"1E",x"4C",x"ED",x"5B", -- 0x0480 + x"1D",x"4C",x"7A",x"C6",x"10",x"57",x"D5",x"CD", -- 0x0488 + x"1B",x"0C",x"D1",x"20",x"06",x"1C",x"CD",x"1B", -- 0x0490 + x"0C",x"28",x"0E",x"AF",x"32",x"24",x"4C",x"32", -- 0x0498 + x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C",x"18", -- 0x04A0 + x"43",x"3A",x"23",x"4C",x"3C",x"32",x"23",x"4C", -- 0x04A8 + x"FE",x"11",x"38",x"38",x"3E",x"FF",x"32",x"25", -- 0x04B0 + x"4C",x"18",x"31",x"3A",x"24",x"4C",x"B7",x"20", -- 0x04B8 + x"2B",x"ED",x"5B",x"1D",x"4C",x"7A",x"C6",x"10", -- 0x04C0 + x"57",x"D5",x"CD",x"1B",x"0C",x"D1",x"20",x"1C", -- 0x04C8 + x"1C",x"CD",x"1B",x"0C",x"20",x"16",x"AF",x"32", -- 0x04D0 + x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C",x"3E", -- 0x04D8 + x"01",x"32",x"24",x"4C",x"3A",x"1E",x"4C",x"C6", -- 0x04E0 + x"10",x"32",x"28",x"4C",x"ED",x"5B",x"1D",x"4C", -- 0x04E8 + x"CB",x"23",x"CB",x"23",x"CB",x"23",x"ED",x"4B", -- 0x04F0 + x"1F",x"4C",x"D5",x"79",x"E6",x"0C",x"1F",x"D1", -- 0x04F8 + x"83",x"32",x"29",x"4C",x"ED",x"5B",x"1D",x"4C", -- 0x0500 + x"CB",x"23",x"CB",x"23",x"CB",x"23",x"ED",x"4B", -- 0x0508 + x"1F",x"4C",x"CB",x"49",x"28",x"04",x"79",x"EE", -- 0x0510 + x"0C",x"4F",x"3E",x"00",x"CD",x"D5",x"0B",x"DD", -- 0x0518 + x"21",x"71",x"4C",x"06",x"01",x"3A",x"41",x"4C", -- 0x0520 + x"B7",x"28",x"21",x"4F",x"C5",x"DD",x"5E",x"01", -- 0x0528 + x"CB",x"23",x"CB",x"23",x"CB",x"23",x"DD",x"56", -- 0x0530 + x"02",x"DD",x"4E",x"00",x"78",x"06",x"01",x"CD", -- 0x0538 + x"D5",x"0B",x"C1",x"11",x"07",x"00",x"DD",x"19", -- 0x0540 + x"04",x"0D",x"20",x"E0",x"DD",x"21",x"8D",x"4C", -- 0x0548 + x"3A",x"42",x"4C",x"B7",x"28",x"21",x"4F",x"C5", -- 0x0550 + x"DD",x"5E",x"01",x"CB",x"23",x"CB",x"23",x"CB", -- 0x0558 + x"23",x"DD",x"56",x"02",x"DD",x"4E",x"00",x"78", -- 0x0560 + x"06",x"01",x"CD",x"D5",x"0B",x"C1",x"11",x"07", -- 0x0568 + x"00",x"DD",x"19",x"04",x"0D",x"20",x"E0",x"78", -- 0x0570 + x"FE",x"08",x"28",x"0C",x"11",x"F0",x"F0",x"DD", -- 0x0578 + x"4E",x"00",x"CD",x"D5",x"0B",x"04",x"18",x"EF", -- 0x0580 + x"3E",x"01",x"32",x"50",x"4C",x"3A",x"24",x"4C", -- 0x0588 + x"B7",x"20",x"43",x"ED",x"5B",x"1D",x"4C",x"7A", -- 0x0590 + x"C6",x"10",x"57",x"CD",x"0F",x"0C",x"FE",x"68", -- 0x0598 + x"38",x"12",x"FE",x"A0",x"30",x"0E",x"3C",x"77", -- 0x05A0 + x"E6",x"07",x"20",x"08",x"36",x"03",x"CB",x"D4", -- 0x05A8 + x"3A",x"36",x"4C",x"77",x"ED",x"5B",x"1D",x"4C", -- 0x05B0 + x"1C",x"7A",x"C6",x"10",x"57",x"CD",x"0F",x"0C", -- 0x05B8 + x"FE",x"68",x"38",x"12",x"FE",x"A0",x"30",x"0E", -- 0x05C0 + x"3C",x"77",x"E6",x"07",x"20",x"08",x"36",x"03", -- 0x05C8 + x"CB",x"D4",x"3A",x"36",x"4C",x"77",x"ED",x"5B", -- 0x05D0 + x"1D",x"4C",x"CD",x"7A",x"0A",x"1C",x"CD",x"7A", -- 0x05D8 + x"0A",x"7A",x"C6",x"08",x"57",x"CD",x"7A",x"0A", -- 0x05E0 + x"1D",x"CD",x"7A",x"0A",x"7A",x"C6",x"07",x"57", -- 0x05E8 + x"CD",x"7A",x"0A",x"1C",x"CD",x"7A",x"0A",x"DD", -- 0x05F0 + x"21",x"71",x"4C",x"3A",x"41",x"4C",x"B7",x"28", -- 0x05F8 + x"61",x"47",x"DD",x"7E",x"03",x"DD",x"86",x"06", -- 0x0600 + x"DD",x"77",x"03",x"1F",x"1F",x"1F",x"DD",x"77", -- 0x0608 + x"01",x"DD",x"7E",x"03",x"DD",x"BE",x"04",x"38", -- 0x0610 + x"05",x"DD",x"BE",x"05",x"38",x"08",x"DD",x"7E", -- 0x0618 + x"06",x"2F",x"3C",x"DD",x"77",x"06",x"DD",x"7E", -- 0x0620 + x"03",x"E6",x"06",x"87",x"4F",x"DD",x"7E",x"00", -- 0x0628 + x"E6",x"F0",x"B1",x"DD",x"77",x"00",x"DD",x"CB", -- 0x0630 + x"06",x"7E",x"28",x"08",x"DD",x"7E",x"00",x"EE", -- 0x0638 + x"0E",x"DD",x"77",x"00",x"DD",x"5E",x"03",x"DD", -- 0x0640 + x"56",x"02",x"2A",x"1D",x"4C",x"3A",x"29",x"4C", -- 0x0648 + x"6F",x"CD",x"FA",x"09",x"38",x"05",x"3E",x"02", -- 0x0650 + x"32",x"2B",x"4C",x"11",x"07",x"00",x"DD",x"19", -- 0x0658 + x"10",x"A0",x"DD",x"21",x"8D",x"4C",x"3A",x"42", -- 0x0660 + x"4C",x"B7",x"CA",x"2C",x"07",x"47",x"DD",x"7E", -- 0x0668 + x"06",x"B7",x"28",x"11",x"3A",x"2F",x"4C",x"FE", -- 0x0670 + x"07",x"28",x"04",x"FE",x"0B",x"20",x"06",x"11", -- 0x0678 + x"0E",x"0A",x"CD",x"26",x"0A",x"DD",x"7E",x"02", -- 0x0680 + x"DD",x"86",x"06",x"DD",x"77",x"02",x"DD",x"BE", -- 0x0688 + x"04",x"38",x"05",x"DD",x"BE",x"05",x"38",x"4A", -- 0x0690 + x"DD",x"7E",x"06",x"2F",x"3C",x"DD",x"77",x"06", -- 0x0698 + x"3A",x"2F",x"4C",x"FE",x"07",x"28",x"37",x"FE", -- 0x06A0 + x"0B",x"28",x"33",x"FE",x"0D",x"28",x"13",x"FE", -- 0x06A8 + x"04",x"28",x"02",x"18",x"2D",x"3A",x"3C",x"4C", -- 0x06B0 + x"B7",x"20",x"27",x"3E",x"00",x"DD",x"77",x"06", -- 0x06B8 + x"18",x"20",x"DD",x"7E",x"03",x"C6",x"40",x"DD", -- 0x06C0 + x"77",x"03",x"1F",x"1F",x"1F",x"DD",x"77",x"01", -- 0x06C8 + x"AF",x"DD",x"77",x"02",x"DD",x"7E",x"06",x"2F", -- 0x06D0 + x"3C",x"DD",x"77",x"06",x"18",x"04",x"AF",x"32", -- 0x06D8 + x"42",x"4C",x"3A",x"30",x"4C",x"E6",x"03",x"20", -- 0x06E0 + x"23",x"DD",x"7E",x"00",x"FE",x"20",x"38",x"1C", -- 0x06E8 + x"FE",x"A0",x"38",x"13",x"C6",x"04",x"DD",x"77", -- 0x06F0 + x"00",x"E6",x"0C",x"FE",x"00",x"20",x"0D",x"DD", -- 0x06F8 + x"7E",x"00",x"D6",x"10",x"DD",x"77",x"00",x"EE", -- 0x0700 + x"04",x"DD",x"77",x"00",x"DD",x"5E",x"03",x"DD", -- 0x0708 + x"56",x"02",x"2A",x"1D",x"4C",x"3A",x"29",x"4C", -- 0x0710 + x"6F",x"CD",x"FA",x"09",x"38",x"05",x"3E",x"02", -- 0x0718 + x"32",x"2B",x"4C",x"11",x"07",x"00",x"DD",x"19", -- 0x0720 + x"05",x"C2",x"6E",x"06",x"3A",x"07",x"4C",x"E6", -- 0x0728 + x"20",x"28",x"0A",x"3A",x"05",x"4C",x"E6",x"60", -- 0x0730 + x"20",x"03",x"C3",x"58",x"01",x"3A",x"2B",x"4C", -- 0x0738 + x"B7",x"CA",x"ED",x"01",x"FE",x"01",x"28",x"1C", -- 0x0740 + x"3E",x"40",x"32",x"4E",x"4C",x"3A",x"27",x"4C", -- 0x0748 + x"3D",x"32",x"27",x"4C",x"C2",x"E0",x"01",x"AF", -- 0x0750 + x"32",x"47",x"4C",x"32",x"24",x"4C",x"CD",x"19", -- 0x0758 + x"09",x"C3",x"58",x"01",x"AF",x"32",x"24",x"4C", -- 0x0760 + x"3A",x"39",x"4C",x"B7",x"28",x"11",x"32",x"4A", -- 0x0768 + x"4C",x"CD",x"83",x"0B",x"CD",x"3C",x"0B",x"11", -- 0x0770 + x"14",x"0A",x"CD",x"26",x"0A",x"18",x"E5",x"3A", -- 0x0778 + x"2F",x"4C",x"3C",x"32",x"2F",x"4C",x"FE",x"14", -- 0x0780 + x"DA",x"E0",x"01",x"AF",x"32",x"2F",x"4C",x"C3", -- 0x0788 + x"E0",x"01",x"3A",x"2F",x"4C",x"FE",x"12",x"C0", -- 0x0790 + x"11",x"14",x"00",x"CD",x"6D",x"0B",x"CB",x"D4", -- 0x0798 + x"11",x"14",x"00",x"7E",x"FE",x"18",x"20",x"34", -- 0x07A0 + x"7E",x"FE",x"18",x"20",x"24",x"36",x"0F",x"2C", -- 0x07A8 + x"14",x"18",x"F5",x"01",x"E1",x"FF",x"09",x"15", -- 0x07B0 + x"1D",x"7E",x"FE",x"18",x"28",x"EA",x"18",x"1C", -- 0x07B8 + x"7E",x"FE",x"18",x"20",x"EE",x"36",x"0F",x"01", -- 0x07C0 + x"20",x"00",x"09",x"1D",x"FA",x"DC",x"07",x"18", -- 0x07C8 + x"EF",x"01",x"1F",x"00",x"09",x"15",x"1D",x"7E", -- 0x07D0 + x"FE",x"18",x"28",x"E9",x"21",x"A4",x"47",x"36", -- 0x07D8 + x"0F",x"2E",x"84",x"36",x"0F",x"DD",x"21",x"71", -- 0x07E0 + x"4C",x"3A",x"41",x"4C",x"B7",x"28",x"31",x"47", -- 0x07E8 + x"DD",x"5E",x"03",x"DD",x"56",x"02",x"CB",x"3B", -- 0x07F0 + x"CB",x"3B",x"CB",x"3B",x"CB",x"3A",x"CB",x"3A", -- 0x07F8 + x"CB",x"3A",x"CD",x"6D",x"0B",x"CB",x"D4",x"CD", -- 0x0800 + x"0B",x"09",x"2C",x"CD",x"0B",x"09",x"11",x"E0", -- 0x0808 + x"FF",x"19",x"CD",x"0B",x"09",x"2D",x"CD",x"0B", -- 0x0810 + x"09",x"11",x"07",x"00",x"DD",x"19",x"10",x"D0", -- 0x0818 + x"DD",x"21",x"8D",x"4C",x"3A",x"42",x"4C",x"B7", -- 0x0820 + x"CA",x"5E",x"08",x"47",x"DD",x"5E",x"03",x"DD", -- 0x0828 + x"56",x"02",x"CB",x"3B",x"CB",x"3B",x"CB",x"3B", -- 0x0830 + x"CB",x"3A",x"CB",x"3A",x"CB",x"3A",x"CD",x"6D", -- 0x0838 + x"0B",x"CB",x"D4",x"CD",x"0B",x"09",x"2C",x"CD", -- 0x0840 + x"0B",x"09",x"11",x"E0",x"FF",x"19",x"CD",x"0B", -- 0x0848 + x"09",x"2D",x"CD",x"0B",x"09",x"11",x"07",x"00", -- 0x0850 + x"DD",x"19",x"05",x"C2",x"2C",x"08",x"3A",x"2F", -- 0x0858 + x"4C",x"FE",x"12",x"C0",x"11",x"14",x"00",x"CD", -- 0x0860 + x"6D",x"0B",x"CB",x"D4",x"11",x"14",x"00",x"01", -- 0x0868 + x"20",x"00",x"7E",x"FE",x"16",x"28",x"13",x"FE", -- 0x0870 + x"0F",x"20",x"16",x"36",x"18",x"2C",x"14",x"18", -- 0x0878 + x"F1",x"7E",x"FE",x"16",x"28",x"F5",x"FE",x"0F", -- 0x0880 + x"20",x"07",x"36",x"18",x"09",x"1D",x"F2",x"81", -- 0x0888 + x"08",x"DD",x"21",x"71",x"4C",x"3A",x"41",x"4C", -- 0x0890 + x"B7",x"28",x"31",x"47",x"DD",x"5E",x"03",x"DD", -- 0x0898 + x"56",x"02",x"CB",x"3B",x"CB",x"3B",x"CB",x"3B", -- 0x08A0 + x"CB",x"3A",x"CB",x"3A",x"CB",x"3A",x"CD",x"6D", -- 0x08A8 + x"0B",x"CB",x"D4",x"CD",x"12",x"09",x"2C",x"CD", -- 0x08B0 + x"12",x"09",x"11",x"E0",x"FF",x"19",x"CD",x"12", -- 0x08B8 + x"09",x"2D",x"CD",x"12",x"09",x"11",x"07",x"00", -- 0x08C0 + x"DD",x"19",x"10",x"D0",x"DD",x"21",x"8D",x"4C", -- 0x08C8 + x"3A",x"42",x"4C",x"B7",x"CA",x"0A",x"09",x"47", -- 0x08D0 + x"DD",x"5E",x"03",x"DD",x"56",x"02",x"CB",x"3B", -- 0x08D8 + x"CB",x"3B",x"CB",x"3B",x"CB",x"3A",x"CB",x"3A", -- 0x08E0 + x"CB",x"3A",x"CD",x"6D",x"0B",x"CB",x"D4",x"CD", -- 0x08E8 + x"12",x"09",x"2C",x"CD",x"12",x"09",x"11",x"E0", -- 0x08F0 + x"FF",x"19",x"CD",x"12",x"09",x"2D",x"CD",x"12", -- 0x08F8 + x"09",x"11",x"07",x"00",x"DD",x"19",x"05",x"C2", -- 0x0900 + x"D8",x"08",x"C9",x"7E",x"FE",x"0F",x"C0",x"36", -- 0x0908 + x"16",x"C9",x"7E",x"FE",x"18",x"C8",x"36",x"0F", -- 0x0910 + x"C9",x"AF",x"32",x"50",x"4C",x"CD",x"83",x"0B", -- 0x0918 + x"11",x"00",x"00",x"06",x"1C",x"D5",x"C5",x"CD", -- 0x0920 + x"6D",x"0B",x"06",x"10",x"AF",x"36",x"03",x"CB", -- 0x0928 + x"D4",x"77",x"CB",x"94",x"2C",x"10",x"F6",x"C1", -- 0x0930 + x"D1",x"1C",x"10",x"E9",x"CD",x"CB",x"0E",x"3E", -- 0x0938 + x"60",x"32",x"1E",x"4C",x"CD",x"83",x"0B",x"ED", -- 0x0940 + x"5F",x"11",x"00",x"00",x"06",x"1C",x"D5",x"C5", -- 0x0948 + x"F5",x"CD",x"6D",x"0B",x"F1",x"06",x"10",x"CB", -- 0x0950 + x"D4",x"77",x"2C",x"10",x"FA",x"C1",x"D1",x"1C", -- 0x0958 + x"10",x"EC",x"21",x"20",x"46",x"3A",x"1E",x"4C", -- 0x0960 + x"47",x"3E",x"60",x"90",x"1F",x"1F",x"1F",x"E6", -- 0x0968 + x"1F",x"3C",x"47",x"3E",x"01",x"77",x"2C",x"10", -- 0x0970 + x"FC",x"ED",x"4B",x"1E",x"4C",x"3E",x"61",x"91", -- 0x0978 + x"1F",x"1F",x"1F",x"E6",x"1F",x"57",x"1E",x"0C", -- 0x0980 + x"CD",x"6D",x"0B",x"36",x"17",x"CB",x"D4",x"36", -- 0x0988 + x"01",x"11",x"5D",x"70",x"01",x"14",x"01",x"3E", -- 0x0990 + x"02",x"CD",x"D5",x"0B",x"11",x"60",x"60",x"01", -- 0x0998 + x"00",x"01",x"3E",x"01",x"CD",x"D5",x"0B",x"11", -- 0x09A0 + x"5E",x"00",x"ED",x"4B",x"1E",x"4C",x"3E",x"61", -- 0x09A8 + x"91",x"57",x"01",x"18",x"01",x"3E",x"00",x"CD", -- 0x09B0 + x"D5",x"0B",x"3A",x"1E",x"4C",x"3D",x"32",x"1E", -- 0x09B8 + x"4C",x"F5",x"CB",x"3F",x"CB",x"3F",x"32",x"4A", -- 0x09C0 + x"4C",x"F1",x"C2",x"44",x"09",x"11",x"00",x"00", -- 0x09C8 + x"06",x"1C",x"AF",x"D5",x"C5",x"F5",x"CD",x"6D", -- 0x09D0 + x"0B",x"F1",x"06",x"10",x"CB",x"D4",x"77",x"2C", -- 0x09D8 + x"10",x"FA",x"C1",x"D1",x"1C",x"10",x"EC",x"21", -- 0x09E0 + x"20",x"46",x"06",x"0C",x"3E",x"01",x"77",x"2C", -- 0x09E8 + x"10",x"FC",x"06",x"FA",x"CD",x"83",x"0B",x"10", -- 0x09F0 + x"FB",x"C9",x"7D",x"C6",x"06",x"BB",x"D8",x"7B", -- 0x09F8 + x"C6",x"06",x"BD",x"D8",x"7C",x"C6",x"0F",x"BA", -- 0x0A00 + x"D8",x"7A",x"C6",x"0F",x"BC",x"C9",x"00",x"00", -- 0x0A08 + x"01",x"00",x"00",x"00",x"08",x"00",x"00",x"00", -- 0x0A10 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"00", -- 0x0A18 + x"00",x"05",x"02",x"00",x"00",x"00",x"E5",x"C5", -- 0x0A20 + x"21",x"12",x"4C",x"01",x"00",x"06",x"1A",x"86", -- 0x0A28 + x"81",x"77",x"0E",x"00",x"FE",x"3A",x"38",x"04", -- 0x0A30 + x"D6",x"0A",x"77",x"0C",x"2B",x"13",x"10",x"EE", -- 0x0A38 + x"21",x"0D",x"4C",x"11",x"14",x"4C",x"06",x"06", -- 0x0A40 + x"1A",x"BE",x"28",x"0E",x"30",x"10",x"21",x"0D", -- 0x0A48 + x"4C",x"11",x"14",x"4C",x"01",x"06",x"00",x"EF", -- 0x0A50 + x"18",x"04",x"23",x"13",x"10",x"EA",x"CD",x"AE", -- 0x0A58 + x"0E",x"C1",x"E1",x"C9",x"CD",x"83",x"0B",x"3A", -- 0x0A60 + x"40",x"50",x"E6",x"20",x"20",x"F6",x"C9",x"CD", -- 0x0A68 + x"83",x"0B",x"3A",x"40",x"50",x"E6",x"20",x"28", -- 0x0A70 + x"F6",x"C9",x"D5",x"CD",x"0F",x"0C",x"D1",x"FE", -- 0x0A78 + x"18",x"D8",x"FE",x"20",x"DA",x"10",x"0B",x"FE", -- 0x0A80 + x"30",x"D8",x"FE",x"40",x"DA",x"10",x"0B",x"FE", -- 0x0A88 + x"FE",x"D2",x"16",x"0B",x"FE",x"DE",x"38",x"05", -- 0x0A90 + x"FE",x"E0",x"DA",x"16",x"0B",x"FE",x"44",x"28", -- 0x0A98 + x"42",x"FE",x"45",x"28",x"3E",x"FE",x"46",x"C0", -- 0x0AA0 + x"36",x"47",x"7B",x"FE",x"11",x"38",x"23",x"3A", -- 0x0AA8 + x"8D",x"4C",x"C6",x"08",x"32",x"8D",x"4C",x"3E", -- 0x0AB0 + x"04",x"32",x"93",x"4C",x"E5",x"D5",x"21",x"E2", -- 0x0AB8 + x"41",x"AF",x"77",x"11",x"E0",x"FF",x"19",x"77", -- 0x0AC0 + x"CB",x"D4",x"77",x"AF",x"ED",x"52",x"77",x"D1", -- 0x0AC8 + x"E1",x"C9",x"E5",x"D5",x"21",x"AB",x"41",x"AF", -- 0x0AD0 + x"77",x"2C",x"77",x"CB",x"D4",x"77",x"2D",x"77", -- 0x0AD8 + x"D1",x"E1",x"C9",x"36",x"03",x"CB",x"D4",x"3A", -- 0x0AE0 + x"36",x"4C",x"77",x"3A",x"3C",x"4C",x"3D",x"32", -- 0x0AE8 + x"3C",x"4C",x"D5",x"11",x"1A",x"0A",x"CD",x"26", -- 0x0AF0 + x"0A",x"D1",x"3E",x"02",x"32",x"4F",x"4C",x"3A", -- 0x0AF8 + x"2F",x"4C",x"FE",x"04",x"C0",x"3A",x"3C",x"4C", -- 0x0B00 + x"B7",x"C0",x"3E",x"01",x"32",x"93",x"4C",x"C9", -- 0x0B08 + x"3E",x"02",x"32",x"2B",x"4C",x"C9",x"3A",x"3C", -- 0x0B10 + x"4C",x"B7",x"C0",x"D5",x"3A",x"29",x"4C",x"C6", -- 0x0B18 + x"05",x"1F",x"1F",x"1F",x"E6",x"1F",x"5F",x"3A", -- 0x0B20 + x"1E",x"4C",x"C6",x"08",x"57",x"CD",x"0F",x"0C", -- 0x0B28 + x"D1",x"E6",x"DE",x"FE",x"DE",x"C0",x"3E",x"01", -- 0x0B30 + x"32",x"2B",x"4C",x"C9",x"3A",x"39",x"4C",x"B7", -- 0x0B38 + x"28",x"25",x"3D",x"32",x"39",x"4C",x"1F",x"1F", -- 0x0B40 + x"1F",x"E6",x"1F",x"C6",x"04",x"5F",x"16",x"11", -- 0x0B48 + x"CD",x"6D",x"0B",x"3A",x"39",x"4C",x"E6",x"07", -- 0x0B50 + x"C6",x"60",x"77",x"E6",x"07",x"FE",x"07",x"C0", -- 0x0B58 + x"11",x"E0",x"FF",x"19",x"36",x"A0",x"C9",x"21", -- 0x0B60 + x"31",x"43",x"36",x"A0",x"C9",x"7A",x"C6",x"A0", -- 0x0B68 + x"6F",x"26",x"43",x"7B",x"11",x"E0",x"FF",x"B7", -- 0x0B70 + x"C8",x"1F",x"30",x"01",x"19",x"EB",x"29",x"EB", -- 0x0B78 + x"C3",x"77",x"0B",x"E5",x"2A",x"00",x"4C",x"AF", -- 0x0B80 + x"32",x"C0",x"50",x"3A",x"00",x"4C",x"BD",x"28", -- 0x0B88 + x"F6",x"E1",x"C9",x"7E",x"23",x"B7",x"C8",x"C6", -- 0x0B90 + x"80",x"12",x"CB",x"D2",x"79",x"12",x"7B",x"D6", -- 0x0B98 + x"20",x"5F",x"CB",x"92",x"7A",x"DE",x"00",x"57", -- 0x0BA0 + x"C3",x"93",x"0B",x"7C",x"CD",x"B0",x"0B",x"7D", -- 0x0BA8 + x"F5",x"1F",x"1F",x"1F",x"1F",x"CD",x"B9",x"0B", -- 0x0BB0 + x"F1",x"E6",x"0F",x"FE",x"0A",x"38",x"02",x"C6", -- 0x0BB8 + x"07",x"C6",x"B0",x"E5",x"D5",x"F5",x"CD",x"6D", -- 0x0BC0 + x"0B",x"F1",x"77",x"CB",x"D4",x"36",x"12",x"CB", -- 0x0BC8 + x"94",x"D1",x"1C",x"E1",x"C9",x"F5",x"3E",x"F0", -- 0x0BD0 + x"BA",x"20",x"03",x"BB",x"28",x"2C",x"F1",x"3C", -- 0x0BD8 + x"D5",x"ED",x"5B",x"1C",x"4C",x"BB",x"38",x"03", -- 0x0BE0 + x"32",x"1C",x"4C",x"E6",x"07",x"87",x"5F",x"16", -- 0x0BE8 + x"00",x"21",x"51",x"4C",x"19",x"D1",x"71",x"23", -- 0x0BF0 + x"70",x"23",x"D5",x"11",x"0E",x"00",x"19",x"D1", -- 0x0BF8 + x"3E",x"EE",x"93",x"77",x"23",x"3E",x"00",x"92", -- 0x0C00 + x"77",x"C9",x"F1",x"3C",x"D5",x"18",x"DC",x"7A", -- 0x0C08 + x"1F",x"1F",x"1F",x"E6",x"1F",x"57",x"CD",x"6D", -- 0x0C10 + x"0B",x"7E",x"C9",x"CD",x"0F",x"0C",x"FE",x"05", -- 0x0C18 + x"38",x"14",x"FE",x"18",x"38",x"12",x"FE",x"20", -- 0x0C20 + x"38",x"0C",x"FE",x"30",x"38",x"0A",x"FE",x"48", -- 0x0C28 + x"38",x"04",x"FE",x"A0",x"38",x"02",x"AF",x"C9", -- 0x0C30 + x"B7",x"C9",x"CD",x"0F",x"0C",x"FE",x"20",x"38", -- 0x0C38 + x"04",x"FE",x"30",x"38",x"02",x"AF",x"C9",x"3E", -- 0x0C40 + x"01",x"B7",x"C9",x"CD",x"0F",x"0C",x"FE",x"48", -- 0x0C48 + x"38",x"04",x"FE",x"60",x"38",x"02",x"AF",x"C9", -- 0x0C50 + x"3E",x"01",x"B7",x"C9",x"32",x"36",x"4C",x"F5", -- 0x0C58 + x"AF",x"32",x"50",x"4C",x"CD",x"83",x"0B",x"F1", -- 0x0C60 + x"F3",x"E5",x"D5",x"C5",x"F5",x"21",x"00",x"40", -- 0x0C68 + x"11",x"01",x"40",x"01",x"00",x"04",x"36",x"03", -- 0x0C70 + x"ED",x"B0",x"01",x"40",x"00",x"36",x"00",x"ED", -- 0x0C78 + x"B0",x"01",x"80",x"03",x"77",x"ED",x"B0",x"36", -- 0x0C80 + x"00",x"01",x"3F",x"00",x"ED",x"B0",x"FB",x"CD", -- 0x0C88 + x"83",x"0B",x"F3",x"11",x"00",x"10",x"06",x"10", -- 0x0C90 + x"D5",x"C5",x"CD",x"6D",x"0B",x"11",x"E0",x"FF", -- 0x0C98 + x"CB",x"D4",x"06",x"20",x"36",x"00",x"19",x"10", -- 0x0CA0 + x"FB",x"C1",x"D1",x"14",x"10",x"EA",x"CD",x"69", -- 0x0CA8 + x"12",x"F1",x"C1",x"D1",x"E1",x"FB",x"C9",x"3A", -- 0x0CB0 + x"3C",x"4C",x"B7",x"C0",x"ED",x"5F",x"21",x"D8", -- 0x0CB8 + x"0C",x"E6",x"03",x"5F",x"16",x"00",x"19",x"7E", -- 0x0CC0 + x"2A",x"3F",x"4C",x"CB",x"D4",x"77",x"2C",x"77", -- 0x0CC8 + x"11",x"E0",x"FF",x"19",x"77",x"2D",x"77",x"C9", -- 0x0CD0 + x"09",x"11",x"14",x"17",x"C9",x"DD",x"2A",x"37", -- 0x0CD8 + x"4C",x"DD",x"7E",x"02",x"B7",x"C8",x"47",x"DD", -- 0x0CE0 + x"5E",x"00",x"DD",x"56",x"01",x"CD",x"6D",x"0B", -- 0x0CE8 + x"DD",x"7E",x"05",x"32",x"2C",x"4C",x"FE",x"00", -- 0x0CF0 + x"3A",x"30",x"4C",x"28",x"01",x"2F",x"E6",x"07", -- 0x0CF8 + x"DD",x"86",x"03",x"DD",x"4E",x"04",x"C3",x"09", -- 0x0D00 + x"0D",x"11",x"E0",x"FF",x"18",x"03",x"11",x"01", -- 0x0D08 + x"00",x"77",x"CB",x"D4",x"71",x"CB",x"94",x"19", -- 0x0D10 + x"10",x"F7",x"C9",x"6F",x"26",x"00",x"29",x"11", -- 0x0D18 + x"84",x"17",x"19",x"5E",x"23",x"56",x"D5",x"DD", -- 0x0D20 + x"E1",x"DD",x"7E",x"00",x"DD",x"23",x"CD",x"5C", -- 0x0D28 + x"0C",x"DD",x"5E",x"00",x"DD",x"56",x"01",x"CD", -- 0x0D30 + x"6D",x"0B",x"DD",x"7E",x"02",x"B7",x"28",x"1C", -- 0x0D38 + x"47",x"CB",x"B8",x"E6",x"80",x"DD",x"7E",x"03", -- 0x0D40 + x"DD",x"4E",x"04",x"11",x"05",x"00",x"DD",x"19", -- 0x0D48 + x"28",x"05",x"CD",x"0E",x"0D",x"18",x"DA",x"CD", -- 0x0D50 + x"09",x"0D",x"18",x"D5",x"22",x"3F",x"4C",x"36", -- 0x0D58 + x"DE",x"2C",x"36",x"FE",x"CB",x"D4",x"36",x"09", -- 0x0D60 + x"2D",x"36",x"09",x"CB",x"94",x"11",x"E0",x"FF", -- 0x0D68 + x"19",x"36",x"DF",x"2C",x"36",x"FF",x"CB",x"D4", -- 0x0D70 + x"36",x"09",x"2D",x"36",x"09",x"DD",x"7E",x"03", -- 0x0D78 + x"DD",x"4E",x"04",x"DD",x"46",x"05",x"11",x"06", -- 0x0D80 + x"00",x"DD",x"19",x"B7",x"28",x"16",x"F5",x"DD", -- 0x0D88 + x"5E",x"00",x"DD",x"56",x"01",x"DD",x"23",x"DD", -- 0x0D90 + x"23",x"CD",x"6D",x"0B",x"71",x"CB",x"D4",x"70", -- 0x0D98 + x"F1",x"3D",x"20",x"EA",x"DD",x"7E",x"00",x"DD", -- 0x0DA0 + x"4E",x"01",x"DD",x"46",x"02",x"11",x"03",x"00", -- 0x0DA8 + x"DD",x"19",x"B7",x"28",x"16",x"F5",x"DD",x"5E", -- 0x0DB0 + x"00",x"DD",x"56",x"01",x"DD",x"23",x"DD",x"23", -- 0x0DB8 + x"CD",x"6D",x"0B",x"71",x"CB",x"D4",x"70",x"F1", -- 0x0DC0 + x"3D",x"20",x"EA",x"21",x"B0",x"43",x"11",x"E0", -- 0x0DC8 + x"FF",x"06",x"1C",x"36",x"A0",x"CB",x"D4",x"36", -- 0x0DD0 + x"09",x"CB",x"94",x"19",x"10",x"F5",x"DD",x"5E", -- 0x0DD8 + x"00",x"DD",x"23",x"16",x"10",x"CD",x"6D",x"0B", -- 0x0DE0 + x"EB",x"DD",x"E5",x"E1",x"0E",x"09",x"CD",x"93", -- 0x0DE8 + x"0B",x"22",x"37",x"4C",x"11",x"06",x"00",x"19", -- 0x0DF0 + x"7E",x"32",x"1D",x"4C",x"FE",x"10",x"07",x"17", -- 0x0DF8 + x"E6",x"02",x"32",x"1F",x"4C",x"23",x"7E",x"87", -- 0x0E00 + x"87",x"87",x"32",x"1E",x"4C",x"23",x"3E",x"01", -- 0x0E08 + x"32",x"20",x"4C",x"AF",x"32",x"24",x"4C",x"32", -- 0x0E10 + x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C",x"22", -- 0x0E18 + x"3D",x"4C",x"7E",x"47",x"32",x"3C",x"4C",x"23", -- 0x0E20 + x"7E",x"32",x"3A",x"4C",x"23",x"7E",x"32",x"3B", -- 0x0E28 + x"4C",x"23",x"5E",x"23",x"56",x"23",x"E5",x"CD", -- 0x0E30 + x"6D",x"0B",x"3A",x"3A",x"4C",x"77",x"CB",x"D4", -- 0x0E38 + x"3A",x"3B",x"4C",x"77",x"E1",x"10",x"EB",x"7E", -- 0x0E40 + x"23",x"47",x"1F",x"1F",x"1F",x"1F",x"E6",x"07", -- 0x0E48 + x"32",x"41",x"4C",x"78",x"E6",x"07",x"32",x"42", -- 0x0E50 + x"4C",x"3A",x"41",x"4C",x"06",x"00",x"4F",x"87", -- 0x0E58 + x"81",x"87",x"81",x"4F",x"28",x"04",x"11",x"71", -- 0x0E60 + x"4C",x"EF",x"3A",x"42",x"4C",x"06",x"00",x"4F", -- 0x0E68 + x"87",x"81",x"87",x"81",x"4F",x"28",x"04",x"11", -- 0x0E70 + x"8D",x"4C",x"EF",x"21",x"1F",x"28",x"11",x"B1", -- 0x0E78 + x"43",x"0E",x"01",x"CD",x"93",x"0B",x"0E",x"05", -- 0x0E80 + x"CD",x"93",x"0B",x"3E",x"BF",x"32",x"39",x"4C", -- 0x0E88 + x"11",x"00",x"14",x"CD",x"6D",x"0B",x"3A",x"27", -- 0x0E90 + x"4C",x"47",x"11",x"C0",x"FF",x"36",x"DB",x"CB", -- 0x0E98 + x"D4",x"36",x"01",x"2C",x"36",x"01",x"CB",x"94", -- 0x0EA0 + x"36",x"FB",x"2D",x"19",x"10",x"EF",x"21",x"3D", -- 0x0EA8 + x"28",x"11",x"B3",x"43",x"0E",x"19",x"CD",x"93", -- 0x0EB0 + x"0B",x"21",x"14",x"4C",x"CD",x"93",x"0B",x"21", -- 0x0EB8 + x"46",x"28",x"CD",x"93",x"0B",x"21",x"0D",x"4C", -- 0x0EC0 + x"C3",x"93",x"0B",x"06",x"08",x"11",x"F0",x"F0", -- 0x0EC8 + x"3E",x"08",x"90",x"CD",x"D5",x"0B",x"10",x"F5", -- 0x0ED0 + x"C9",x"E5",x"CD",x"6D",x"0B",x"EB",x"E1",x"E5", -- 0x0ED8 + x"D5",x"C5",x"7D",x"2C",x"12",x"CB",x"D2",x"7C", -- 0x0EE0 + x"12",x"CB",x"92",x"3E",x"E0",x"83",x"5F",x"7A", -- 0x0EE8 + x"CE",x"FF",x"57",x"0D",x"20",x"EC",x"C1",x"D1", -- 0x0EF0 + x"E1",x"13",x"7D",x"C6",x"20",x"6F",x"10",x"DF", -- 0x0EF8 + x"C9",x"E5",x"CD",x"6D",x"0B",x"EB",x"E1",x"E5", -- 0x0F00 + x"D5",x"C5",x"7D",x"12",x"CB",x"D2",x"7C",x"12", -- 0x0F08 + x"CB",x"92",x"3E",x"E0",x"83",x"5F",x"7A",x"CE", -- 0x0F10 + x"FF",x"57",x"0D",x"20",x"ED",x"C1",x"D1",x"E1", -- 0x0F18 + x"13",x"10",x"E4",x"C9",x"AF",x"CD",x"5C",x"0C", -- 0x0F20 + x"21",x"50",x"0F",x"16",x"04",x"0E",x"17",x"1E", -- 0x0F28 + x"00",x"06",x"1B",x"7E",x"23",x"E6",x"01",x"28", -- 0x0F30 + x"0D",x"E5",x"D5",x"CD",x"6D",x"0B",x"36",x"A0", -- 0x0F38 + x"CB",x"D4",x"36",x"09",x"D1",x"E1",x"1C",x"10", -- 0x0F40 + x"EA",x"14",x"0D",x"20",x"E2",x"C3",x"CB",x"0E", -- 0x0F48 + x"30",x"30",x"30",x"30",x"30",x"31",x"31",x"31", -- 0x0F50 + x"31",x"30",x"30",x"30",x"31",x"31",x"31",x"30", -- 0x0F58 + x"30",x"30",x"31",x"31",x"31",x"30",x"30",x"30", -- 0x0F60 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0F68 + x"31",x"30",x"30",x"30",x"31",x"30",x"31",x"30", -- 0x0F70 + x"30",x"30",x"31",x"30",x"31",x"30",x"30",x"30", -- 0x0F78 + x"31",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0F80 + x"30",x"30",x"30",x"31",x"31",x"31",x"31",x"30", -- 0x0F88 + x"30",x"31",x"31",x"31",x"31",x"31",x"30",x"31", -- 0x0F90 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0F98 + x"30",x"30",x"30",x"30",x"30",x"30",x"31",x"30", -- 0x0FA0 + x"30",x"30",x"30",x"30",x"31",x"30",x"30",x"30", -- 0x0FA8 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x0FB0 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FB8 + x"30",x"31",x"30",x"30",x"30",x"30",x"30",x"31", -- 0x0FC0 + x"30",x"30",x"30",x"31",x"30",x"30",x"31",x"31", -- 0x0FC8 + x"31",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FD0 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FD8 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FE0 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FE8 + x"30",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x0FF0 + x"30",x"31",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x0FF8 + x"30",x"30",x"31",x"30",x"31",x"31",x"31",x"30", -- 0x1000 + x"30",x"31",x"31",x"31",x"30",x"31",x"31",x"30", -- 0x1008 + x"31",x"31",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1010 + x"30",x"31",x"31",x"30",x"30",x"31",x"30",x"30", -- 0x1018 + x"31",x"30",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1020 + x"31",x"30",x"31",x"30",x"31",x"30",x"31",x"31", -- 0x1028 + x"31",x"31",x"31",x"30",x"31",x"30",x"31",x"30", -- 0x1030 + x"31",x"30",x"30",x"31",x"30",x"30",x"31",x"30", -- 0x1038 + x"30",x"30",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1040 + x"30",x"31",x"30",x"30",x"30",x"31",x"30",x"31", -- 0x1048 + x"30",x"30",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x1050 + x"30",x"31",x"30",x"30",x"30",x"31",x"31",x"30", -- 0x1058 + x"30",x"30",x"31",x"30",x"31",x"30",x"30",x"30", -- 0x1060 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x1068 + x"31",x"31",x"31",x"30",x"30",x"31",x"31",x"31", -- 0x1070 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1078 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1080 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1088 + x"30",x"30",x"30",x"30",x"31",x"30",x"30",x"30", -- 0x1090 + x"31",x"30",x"31",x"31",x"31",x"30",x"31",x"30", -- 0x1098 + x"30",x"30",x"31",x"30",x"31",x"31",x"31",x"31", -- 0x10A0 + x"31",x"30",x"31",x"31",x"31",x"31",x"30",x"31", -- 0x10A8 + x"31",x"30",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x10B0 + x"30",x"31",x"31",x"30",x"30",x"31",x"30",x"31", -- 0x10B8 + x"30",x"30",x"30",x"30",x"30",x"31",x"30",x"30", -- 0x10C0 + x"30",x"31",x"31",x"30",x"31",x"30",x"31",x"30", -- 0x10C8 + x"30",x"31",x"30",x"30",x"31",x"30",x"31",x"30", -- 0x10D0 + x"31",x"30",x"31",x"31",x"30",x"30",x"30",x"30", -- 0x10D8 + x"31",x"31",x"31",x"31",x"30",x"31",x"30",x"30", -- 0x10E0 + x"30",x"31",x"30",x"30",x"31",x"30",x"30",x"31", -- 0x10E8 + x"30",x"30",x"31",x"31",x"30",x"31",x"30",x"30", -- 0x10F0 + x"30",x"30",x"30",x"31",x"30",x"30",x"31",x"30", -- 0x10F8 + x"31",x"30",x"30",x"30",x"31",x"30",x"31",x"31", -- 0x1100 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x1108 + x"31",x"31",x"31",x"31",x"31",x"30",x"31",x"30", -- 0x1110 + x"30",x"30",x"31",x"30",x"30",x"30",x"30",x"30", -- 0x1118 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1120 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1128 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1130 + x"30",x"30",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1138 + x"30",x"30",x"31",x"31",x"31",x"30",x"30",x"31", -- 0x1140 + x"30",x"30",x"30",x"31",x"30",x"30",x"30",x"30", -- 0x1148 + x"30",x"30",x"30",x"30",x"30",x"30",x"31",x"31", -- 0x1150 + x"30",x"31",x"31",x"30",x"31",x"30",x"30",x"30", -- 0x1158 + x"31",x"30",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x1160 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1168 + x"30",x"31",x"30",x"31",x"30",x"31",x"30",x"31", -- 0x1170 + x"31",x"31",x"31",x"31",x"30",x"31",x"30",x"31", -- 0x1178 + x"30",x"31",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1180 + x"30",x"30",x"30",x"30",x"31",x"30",x"30",x"30", -- 0x1188 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x1190 + x"31",x"30",x"30",x"31",x"31",x"30",x"30",x"30", -- 0x1198 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"31", -- 0x11A0 + x"30",x"30",x"30",x"31",x"30",x"31",x"30",x"30", -- 0x11A8 + x"30",x"31",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x11B0 + x"30",x"30",x"30",x"30",x"30",x"20",x"20",x"20", -- 0x11B8 + x"20",x"50",x"72",x"65",x"73",x"73",x"20",x"53", -- 0x11C0 + x"74",x"61",x"72",x"74",x"20",x"54",x"6F",x"20", -- 0x11C8 + x"50",x"6C",x"61",x"79",x"20",x"20",x"20",x"20", -- 0x11D0 + x"00",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x11D8 + x"20",x"49",x"6E",x"73",x"65",x"72",x"74",x"20", -- 0x11E0 + x"43",x"6F",x"69",x"6E",x"20",x"20",x"20",x"20", -- 0x11E8 + x"20",x"20",x"20",x"20",x"00",x"1E",x"00",x"D6", -- 0x11F0 + x"0A",x"38",x"03",x"1C",x"18",x"F9",x"C6",x"0A", -- 0x11F8 + x"C9",x"3A",x"0A",x"4C",x"B7",x"C0",x"3A",x"00", -- 0x1200 + x"50",x"32",x"04",x"4C",x"2F",x"5F",x"3A",x"06", -- 0x1208 + x"4C",x"57",x"2F",x"A3",x"32",x"07",x"4C",x"7B", -- 0x1210 + x"32",x"06",x"4C",x"3A",x"40",x"50",x"32",x"05", -- 0x1218 + x"4C",x"2F",x"5F",x"3A",x"08",x"4C",x"57",x"2F", -- 0x1220 + x"A3",x"32",x"09",x"4C",x"7B",x"32",x"08",x"4C", -- 0x1228 + x"3A",x"09",x"4C",x"E6",x"01",x"28",x"08",x"3A", -- 0x1230 + x"4C",x"4C",x"EE",x"0F",x"32",x"4C",x"4C",x"3A", -- 0x1238 + x"09",x"4C",x"E6",x"08",x"28",x"08",x"3A",x"4D", -- 0x1240 + x"4C",x"EE",x"0F",x"32",x"4D",x"4C",x"3A",x"07", -- 0x1248 + x"4C",x"E6",x"20",x"28",x"13",x"3A",x"0B",x"4C", -- 0x1250 + x"FE",x"63",x"28",x"0C",x"3C",x"32",x"0B",x"4C", -- 0x1258 + x"CD",x"69",x"12",x"3E",x"01",x"32",x"0C",x"4C", -- 0x1260 + x"C9",x"11",x"99",x"12",x"21",x"FD",x"43",x"1A", -- 0x1268 + x"13",x"B7",x"28",x"0C",x"C6",x"80",x"77",x"CB", -- 0x1270 + x"D4",x"36",x"19",x"CB",x"94",x"2D",x"18",x"EF", -- 0x1278 + x"3A",x"0B",x"4C",x"CD",x"F5",x"11",x"57",x"7B", -- 0x1280 + x"C6",x"B0",x"77",x"CB",x"D4",x"36",x"19",x"2D", -- 0x1288 + x"36",x"19",x"CB",x"94",x"7A",x"C6",x"B0",x"77", -- 0x1290 + x"C9",x"43",x"72",x"65",x"64",x"69",x"74",x"73", -- 0x1298 + x"20",x"00",x"32",x"47",x"4C",x"AF",x"32",x"46", -- 0x12A0 + x"4C",x"3E",x"01",x"32",x"4B",x"4C",x"C9",x"CD", -- 0x12A8 + x"01",x"12",x"3A",x"47",x"4C",x"B7",x"CA",x"A1", -- 0x12B0 + x"13",x"3A",x"4B",x"4C",x"D6",x"04",x"32",x"4B", -- 0x12B8 + x"4C",x"D2",x"10",x"13",x"3A",x"47",x"4C",x"87", -- 0x12C0 + x"5F",x"16",x"00",x"21",x"4F",x"14",x"19",x"5E", -- 0x12C8 + x"23",x"56",x"EB",x"3A",x"46",x"4C",x"5F",x"3C", -- 0x12D0 + x"32",x"46",x"4C",x"16",x"00",x"19",x"19",x"19", -- 0x12D8 + x"7E",x"FE",x"FF",x"CA",x"A1",x"13",x"B7",x"20", -- 0x12E0 + x"14",x"3C",x"32",x"46",x"4C",x"3A",x"47",x"4C", -- 0x12E8 + x"87",x"5F",x"16",x"00",x"21",x"4F",x"14",x"19", -- 0x12F0 + x"5E",x"23",x"56",x"EB",x"7E",x"32",x"4B",x"4C", -- 0x12F8 + x"23",x"7E",x"CD",x"FD",x"13",x"32",x"48",x"4C", -- 0x1300 + x"23",x"7E",x"CD",x"FD",x"13",x"32",x"49",x"4C", -- 0x1308 + x"3A",x"24",x"4C",x"B7",x"28",x"16",x"3A",x"2A", -- 0x1310 + x"4C",x"3C",x"32",x"2A",x"4C",x"1F",x"1F",x"E6", -- 0x1318 + x"3F",x"5F",x"16",x"00",x"21",x"AE",x"13",x"19", -- 0x1320 + x"7E",x"32",x"4A",x"4C",x"3A",x"4F",x"4C",x"B7", -- 0x1328 + x"28",x"10",x"C6",x"02",x"32",x"4F",x"4C",x"32", -- 0x1330 + x"4A",x"4C",x"FE",x"40",x"38",x"04",x"AF",x"32", -- 0x1338 + x"4F",x"4C",x"3A",x"0C",x"4C",x"B7",x"28",x"10", -- 0x1340 + x"C6",x"01",x"32",x"0C",x"4C",x"32",x"4A",x"4C", -- 0x1348 + x"FE",x"20",x"38",x"04",x"AF",x"32",x"0C",x"4C", -- 0x1350 + x"3A",x"4E",x"4C",x"B7",x"28",x"08",x"D6",x"04", -- 0x1358 + x"32",x"4E",x"4C",x"32",x"4A",x"4C",x"DD",x"21", -- 0x1360 + x"45",x"50",x"DD",x"36",x"00",x"01",x"ED",x"4B", -- 0x1368 + x"4C",x"4C",x"3A",x"48",x"4C",x"CD",x"16",x"14", -- 0x1370 + x"DD",x"21",x"4A",x"50",x"DD",x"36",x"00",x"03", -- 0x1378 + x"ED",x"4B",x"4C",x"4C",x"3A",x"49",x"4C",x"CD", -- 0x1380 + x"16",x"14",x"DD",x"21",x"4F",x"50",x"DD",x"36", -- 0x1388 + x"00",x"01",x"ED",x"4B",x"4D",x"4C",x"3A",x"4A", -- 0x1390 + x"4C",x"CD",x"16",x"14",x"AF",x"32",x"4A",x"4C", -- 0x1398 + x"C9",x"AF",x"32",x"48",x"4C",x"32",x"49",x"4C", -- 0x13A0 + x"32",x"47",x"4C",x"C3",x"10",x"13",x"04",x"09", -- 0x13A8 + x"0B",x"0D",x"0F",x"11",x"13",x"15",x"16",x"15", -- 0x13B0 + x"13",x"11",x"0F",x"0D",x"0B",x"09",x"09",x"08", -- 0x13B8 + x"08",x"07",x"07",x"06",x"06",x"05",x"05",x"04", -- 0x13C0 + x"04",x"04",x"03",x"03",x"03",x"03",x"02",x"02", -- 0x13C8 + x"02",x"02",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x13D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13F0 + x"00",x"00",x"00",x"00",x"00",x"FE",x"FF",x"C8", -- 0x13F8 + x"B7",x"C8",x"E5",x"D5",x"5F",x"21",x"44",x"16", -- 0x1400 + x"16",x"00",x"BE",x"28",x"05",x"23",x"23",x"14", -- 0x1408 + x"18",x"F8",x"7A",x"D1",x"E1",x"C9",x"E5",x"D5", -- 0x1410 + x"B7",x"28",x"2D",x"87",x"5F",x"16",x"00",x"21", -- 0x1418 + x"AC",x"16",x"19",x"5E",x"23",x"56",x"7B",x"DD", -- 0x1420 + x"77",x"0C",x"1F",x"1F",x"1F",x"1F",x"DD",x"77", -- 0x1428 + x"0D",x"7A",x"DD",x"77",x"0E",x"1F",x"1F",x"1F", -- 0x1430 + x"1F",x"DD",x"77",x"0F",x"79",x"DD",x"77",x"10", -- 0x1438 + x"3E",x"01",x"32",x"01",x"50",x"D1",x"E1",x"C9", -- 0x1440 + x"DD",x"36",x"10",x"00",x"D1",x"E1",x"C9",x"00", -- 0x1448 + x"00",x"55",x"14",x"81",x"15",x"50",x"80",x"80", -- 0x1450 + x"50",x"66",x"66",x"50",x"56",x"56",x"32",x"56", -- 0x1458 + x"56",x"32",x"AB",x"CB",x"32",x"2B",x"33",x"32", -- 0x1460 + x"2B",x"33",x"32",x"AB",x"CB",x"32",x"33",x"40", -- 0x1468 + x"32",x"33",x"40",x"32",x"AB",x"CB",x"32",x"80", -- 0x1470 + x"80",x"32",x"80",x"80",x"32",x"66",x"66",x"32", -- 0x1478 + x"56",x"56",x"32",x"60",x"56",x"32",x"AB",x"C0", -- 0x1480 + x"32",x"2B",x"30",x"32",x"2B",x"30",x"32",x"AB", -- 0x1488 + x"C0",x"32",x"30",x"44",x"32",x"30",x"44",x"32", -- 0x1490 + x"AB",x"C0",x"32",x"88",x"88",x"32",x"88",x"88", -- 0x1498 + x"32",x"72",x"72",x"32",x"4C",x"4C",x"32",x"4C", -- 0x14A0 + x"4C",x"32",x"AB",x"C0",x"32",x"26",x"30",x"32", -- 0x14A8 + x"26",x"30",x"32",x"AB",x"C0",x"32",x"30",x"44", -- 0x14B0 + x"32",x"30",x"44",x"32",x"AB",x"C0",x"32",x"88", -- 0x14B8 + x"88",x"32",x"88",x"88",x"32",x"72",x"72",x"32", -- 0x14C0 + x"4C",x"4C",x"32",x"4C",x"4C",x"32",x"AB",x"CB", -- 0x14C8 + x"32",x"26",x"33",x"32",x"26",x"33",x"32",x"AB", -- 0x14D0 + x"CB",x"32",x"33",x"40",x"32",x"33",x"40",x"32", -- 0x14D8 + x"AB",x"CB",x"32",x"80",x"80",x"32",x"80",x"80", -- 0x14E0 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"40", -- 0x14E8 + x"40",x"32",x"80",x"AB",x"32",x"20",x"2B",x"32", -- 0x14F0 + x"20",x"2B",x"32",x"80",x"AB",x"32",x"2B",x"33", -- 0x14F8 + x"32",x"2B",x"33",x"32",x"80",x"AB",x"32",x"80", -- 0x1500 + x"80",x"32",x"80",x"80",x"32",x"66",x"66",x"32", -- 0x1508 + x"56",x"56",x"32",x"40",x"40",x"32",x"80",x"98", -- 0x1510 + x"32",x"20",x"26",x"32",x"20",x"26",x"32",x"80", -- 0x1518 + x"98",x"32",x"26",x"30",x"32",x"26",x"30",x"32", -- 0x1520 + x"00",x"00",x"32",x"72",x"72",x"32",x"72",x"72", -- 0x1528 + x"32",x"60",x"60",x"32",x"4C",x"4C",x"32",x"4C", -- 0x1530 + x"98",x"32",x"4C",x"4C",x"32",x"4C",x"4C",x"32", -- 0x1538 + x"4C",x"98",x"32",x"5B",x"5B",x"32",x"56",x"56", -- 0x1540 + x"32",x"33",x"CB",x"32",x"33",x"33",x"32",x"33", -- 0x1548 + x"33",x"32",x"33",x"CB",x"32",x"40",x"40",x"32", -- 0x1550 + x"66",x"66",x"64",x"66",x"66",x"32",x"72",x"72", -- 0x1558 + x"64",x"4C",x"4C",x"32",x"56",x"56",x"32",x"80", -- 0x1560 + x"CB",x"19",x"80",x"00",x"19",x"80",x"80",x"32", -- 0x1568 + x"80",x"CB",x"FA",x"00",x"00",x"FA",x"00",x"00", -- 0x1570 + x"FA",x"00",x"00",x"FA",x"00",x"00",x"00",x"00", -- 0x1578 + x"00",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x1580 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x1588 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x1590 + x"56",x"32",x"51",x"51",x"32",x"60",x"60",x"32", -- 0x1598 + x"51",x"51",x"32",x"51",x"51",x"32",x"56",x"56", -- 0x15A0 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x15A8 + x"56",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x15B0 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x15B8 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x15C0 + x"56",x"32",x"51",x"51",x"32",x"60",x"60",x"32", -- 0x15C8 + x"51",x"51",x"32",x"51",x"51",x"32",x"56",x"56", -- 0x15D0 + x"32",x"56",x"56",x"32",x"56",x"56",x"32",x"56", -- 0x15D8 + x"56",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x15E0 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x15E8 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x15F0 + x"56",x"32",x"51",x"51",x"32",x"60",x"60",x"32", -- 0x15F8 + x"51",x"51",x"32",x"51",x"51",x"32",x"56",x"56", -- 0x1600 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x1608 + x"56",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x1610 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x1618 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"40", -- 0x1620 + x"40",x"32",x"56",x"56",x"32",x"66",x"66",x"32", -- 0x1628 + x"80",x"80",x"32",x"66",x"66",x"32",x"56",x"56", -- 0x1630 + x"32",x"56",x"56",x"32",x"56",x"56",x"32",x"56", -- 0x1638 + x"56",x"00",x"00",x"00",x"00",x"24",x"FF",x"24", -- 0x1640 + x"F2",x"04",x"E6",x"25",x"D8",x"05",x"CB",x"26", -- 0x1648 + x"C0",x"27",x"B4",x"07",x"AB",x"28",x"A2",x"08", -- 0x1650 + x"98",x"29",x"90",x"09",x"88",x"2A",x"80",x"2B", -- 0x1658 + x"79",x"0B",x"72",x"2C",x"6C",x"0C",x"66",x"2D", -- 0x1660 + x"60",x"2E",x"5B",x"0E",x"56",x"2F",x"51",x"0F", -- 0x1668 + x"4C",x"30",x"48",x"10",x"44",x"31",x"40",x"32", -- 0x1670 + x"3C",x"12",x"39",x"33",x"36",x"13",x"33",x"34", -- 0x1678 + x"30",x"35",x"2D",x"15",x"2B",x"36",x"28",x"16", -- 0x1680 + x"26",x"37",x"24",x"17",x"22",x"38",x"20",x"39", -- 0x1688 + x"1F",x"19",x"1D",x"3A",x"1B",x"1A",x"19",x"3B", -- 0x1690 + x"18",x"3C",x"17",x"1C",x"16",x"3D",x"14",x"1D", -- 0x1698 + x"13",x"3E",x"12",x"1E",x"11",x"3F",x"10",x"2B", -- 0x16A0 + x"01",x"01",x"01",x"01",x"57",x"00",x"5C",x"00", -- 0x16A8 + x"62",x"00",x"6A",x"00",x"6F",x"00",x"75",x"00", -- 0x16B0 + x"7D",x"00",x"85",x"00",x"8E",x"00",x"96",x"00", -- 0x16B8 + x"9E",x"00",x"A6",x"00",x"AE",x"00",x"B9",x"00", -- 0x16C0 + x"C4",x"00",x"D5",x"00",x"DF",x"00",x"EA",x"00", -- 0x16C8 + x"FB",x"00",x"0B",x"01",x"1C",x"01",x"2C",x"01", -- 0x16D0 + x"3C",x"01",x"4D",x"01",x"5D",x"01",x"73",x"01", -- 0x16D8 + x"89",x"01",x"AA",x"01",x"BF",x"01",x"D5",x"01", -- 0x16E0 + x"F6",x"01",x"17",x"02",x"38",x"02",x"58",x"02", -- 0x16E8 + x"79",x"02",x"9A",x"02",x"BA",x"02",x"E6",x"02", -- 0x16F0 + x"12",x"03",x"54",x"03",x"7E",x"03",x"AA",x"03", -- 0x16F8 + x"EC",x"03",x"2E",x"04",x"70",x"04",x"B0",x"04", -- 0x1700 + x"F2",x"04",x"34",x"05",x"74",x"05",x"CC",x"05", -- 0x1708 + x"24",x"06",x"A8",x"06",x"FC",x"06",x"54",x"07", -- 0x1710 + x"D8",x"07",x"5C",x"08",x"E0",x"08",x"60",x"09", -- 0x1718 + x"E4",x"09",x"68",x"0A",x"E8",x"0A",x"98",x"0B", -- 0x1720 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1728 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1730 + x"C8",x"13",x"D0",x"14",x"E8",x"0A",x"98",x"0B", -- 0x1738 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1740 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1748 + x"C8",x"13",x"D0",x"14",x"E8",x"0A",x"98",x"0B", -- 0x1750 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1758 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1760 + x"C8",x"13",x"D0",x"14",x"E8",x"0A",x"98",x"0B", -- 0x1768 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1770 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1778 + x"C8",x"13",x"D0",x"14",x"AC",x"17",x"30",x"18", -- 0x1780 + x"D3",x"18",x"67",x"19",x"1F",x"1A",x"C9",x"1A", -- 0x1788 + x"71",x"1B",x"2F",x"1C",x"13",x"1D",x"CC",x"1D", -- 0x1790 + x"A0",x"1E",x"77",x"1F",x"59",x"20",x"13",x"21", -- 0x1798 + x"FA",x"21",x"AF",x"22",x"68",x"23",x"3E",x"24", -- 0x17A0 + x"F2",x"24",x"A6",x"25",x"00",x"00",x"05",x"1C", -- 0x17A8 + x"08",x"01",x"0C",x"05",x"04",x"80",x"01",x"11", -- 0x17B0 + x"05",x"04",x"80",x"01",x"00",x"07",x"03",x"08", -- 0x17B8 + x"01",x"11",x"08",x"03",x"20",x"09",x"00",x"09", -- 0x17C0 + x"04",x"08",x"01",x"08",x"09",x"10",x"58",x"0F", -- 0x17C8 + x"1A",x"0A",x"02",x"08",x"01",x"14",x"0C",x"03", -- 0x17D0 + x"20",x"09",x"17",x"0C",x"03",x"80",x"01",x"1A", -- 0x17D8 + x"0C",x"02",x"08",x"01",x"04",x"0D",x"10",x"08", -- 0x17E0 + x"01",x"00",x"0F",x"1C",x"08",x"01",x"1A",x"0D", -- 0x17E8 + x"00",x"04",x"30",x"0F",x"17",x"04",x"1B",x"04", -- 0x17F0 + x"15",x"08",x"0C",x"0C",x"02",x"38",x"05",x"0B", -- 0x17F8 + x"00",x"10",x"00",x"07",x"43",x"45",x"4E",x"54", -- 0x1800 + x"52",x"41",x"4C",x"20",x"43",x"41",x"56",x"45", -- 0x1808 + x"52",x"4E",x"00",x"08",x"09",x"10",x"58",x"0F", -- 0x1810 + x"00",x"01",x"0D",x"05",x"45",x"07",x"09",x"00", -- 0x1818 + x"10",x"01",x"19",x"00",x"18",x"04",x"1B",x"06", -- 0x1820 + x"10",x"28",x"08",x"38",x"40",x"40",x"7E",x"01", -- 0x1828 + x"01",x"10",x"00",x"0C",x"20",x"09",x"12",x"03", -- 0x1830 + x"03",x"88",x"01",x"15",x"03",x"01",x"09",x"01", -- 0x1838 + x"00",x"05",x"12",x"09",x"01",x"12",x"06",x"02", -- 0x1840 + x"09",x"01",x"00",x"07",x"01",x"09",x"01",x"01", -- 0x1848 + x"07",x"04",x"88",x"01",x"08",x"09",x"07",x"09", -- 0x1850 + x"01",x"11",x"0A",x"04",x"88",x"01",x"0D",x"0C", -- 0x1858 + x"03",x"09",x"01",x"07",x"0D",x"03",x"88",x"01", -- 0x1860 + x"00",x"0F",x"1C",x"09",x"01",x"16",x"06",x"87", -- 0x1868 + x"20",x"09",x"19",x"05",x"88",x"20",x"09",x"17", -- 0x1870 + x"06",x"02",x"88",x"01",x"17",x"08",x"02",x"88", -- 0x1878 + x"01",x"17",x"09",x"02",x"88",x"01",x"17",x"0A", -- 0x1880 + x"02",x"88",x"01",x"17",x"0B",x"02",x"88",x"01", -- 0x1888 + x"17",x"0C",x"02",x"88",x"01",x"1A",x"0D",x"00", -- 0x1890 + x"00",x"31",x"07",x"01",x"39",x"05",x"1B",x"01", -- 0x1898 + x"08",x"54",x"48",x"45",x"20",x"43",x"4F",x"4C", -- 0x18A0 + x"44",x"20",x"52",x"4F",x"4F",x"4D",x"00",x"02", -- 0x18A8 + x"0B",x"04",x"58",x"14",x"01",x"01",x"0D",x"05", -- 0x18B0 + x"44",x"07",x"02",x"09",x"07",x"01",x"15",x"01", -- 0x18B8 + x"18",x"07",x"11",x"0C",x"20",x"30",x"10",x"18", -- 0x18C0 + x"80",x"08",x"80",x"FF",x"30",x"13",x"68",x"98", -- 0x18C8 + x"58",x"D4",x"FF",x"00",x"09",x"00",x"01",x"1C", -- 0x18D0 + x"03",x"11",x"00",x"01",x"1B",x"03",x"11",x"01", -- 0x18D8 + x"01",x"1C",x"03",x"1A",x"00",x"01",x"1C",x"03", -- 0x18E0 + x"00",x"05",x"04",x"0A",x"05",x"04",x"05",x"18", -- 0x18E8 + x"98",x"05",x"00",x"07",x"05",x"0A",x"05",x"19", -- 0x18F0 + x"07",x"03",x"0A",x"05",x"00",x"08",x"83",x"1B", -- 0x18F8 + x"03",x"00",x"0B",x"01",x"1C",x"03",x"05",x"09", -- 0x1900 + x"06",x"48",x"01",x"17",x"0A",x"05",x"0A",x"05", -- 0x1908 + x"0C",x"0B",x"05",x"0A",x"05",x"04",x"0C",x"06", -- 0x1910 + x"0A",x"05",x"13",x"0D",x"09",x"0A",x"05",x"00", -- 0x1918 + x"0F",x"1C",x"0A",x"05",x"1A",x"08",x"00",x"00", -- 0x1920 + x"1B",x"07",x"00",x"1C",x"05",x"08",x"54",x"48", -- 0x1928 + x"45",x"20",x"4D",x"45",x"4E",x"41",x"47",x"45", -- 0x1930 + x"52",x"49",x"45",x"00",x"05",x"09",x"06",x"48", -- 0x1938 + x"01",x"00",x"01",x"0D",x"05",x"45",x"1B",x"05", -- 0x1940 + x"00",x"0D",x"00",x"15",x"00",x"12",x"06",x"19", -- 0x1948 + x"06",x"30",x"40",x"13",x"68",x"A0",x"08",x"D0", -- 0x1950 + x"FF",x"40",x"10",x"18",x"50",x"08",x"68",x"FF", -- 0x1958 + x"40",x"12",x"18",x"90",x"78",x"D0",x"01",x"00", -- 0x1960 + x"06",x"00",x"01",x"1C",x"03",x"0D",x"00",x"0F", -- 0x1968 + x"20",x"05",x"12",x"03",x"05",x"0A",x"07",x"19", -- 0x1970 + x"04",x"03",x"0A",x"07",x"00",x"05",x"01",x"0A", -- 0x1978 + x"07",x"06",x"05",x"01",x"0A",x"07",x"10",x"05", -- 0x1980 + x"01",x"0A",x"07",x"0B",x"06",x"02",x"0A",x"07", -- 0x1988 + x"14",x"06",x"03",x"0A",x"07",x"00",x"07",x"03", -- 0x1990 + x"98",x"14",x"06",x"08",x"02",x"0A",x"07",x"18", -- 0x1998 + x"08",x"04",x"0A",x"07",x"11",x"09",x"03",x"0A", -- 0x19A0 + x"07",x"00",x"0A",x"03",x"48",x"05",x"1B",x"0A", -- 0x19A8 + x"01",x"0A",x"07",x"0B",x"0B",x"03",x"0A",x"07", -- 0x19B0 + x"15",x"0B",x"03",x"0A",x"07",x"05",x"0C",x"02", -- 0x19B8 + x"0A",x"07",x"16",x"0C",x"01",x"1C",x"03",x"19", -- 0x19C0 + x"0C",x"03",x"0A",x"07",x"11",x"0D",x"02",x"0A", -- 0x19C8 + x"07",x"00",x"0F",x"1C",x"0A",x"07",x"1A",x"01", -- 0x19D0 + x"00",x"00",x"1B",x"07",x"00",x"1C",x"05",x"01", -- 0x19D8 + x"41",x"42",x"41",x"4E",x"44",x"4F",x"4E",x"45", -- 0x19E0 + x"44",x"20",x"55",x"52",x"41",x"4E",x"49",x"55", -- 0x19E8 + x"4D",x"20",x"57",x"4F",x"52",x"4B",x"49",x"4E", -- 0x19F0 + x"47",x"53",x"00",x"00",x"0A",x"03",x"48",x"05", -- 0x19F8 + x"01",x"1A",x"0D",x"05",x"45",x"1B",x"00",x"00", -- 0x1A00 + x"0B",x"01",x"16",x"01",x"0F",x"07",x"19",x"07", -- 0x1A08 + x"20",x"50",x"08",x"68",x"08",x"08",x"60",x"01", -- 0x1A10 + x"50",x"28",x"68",x"28",x"20",x"78",x"01",x"09", -- 0x1A18 + x"12",x"00",x"01",x"3A",x"01",x"00",x"05",x"0C", -- 0x1A20 + x"0C",x"0F",x"10",x"05",x"04",x"68",x"0F",x"14", -- 0x1A28 + x"05",x"05",x"0C",x"0F",x"1A",x"06",x"02",x"0C", -- 0x1A30 + x"0F",x"10",x"08",x"09",x"48",x"01",x"03",x"09", -- 0x1A38 + x"09",x"0C",x"0F",x"00",x"0B",x"02",x"68",x"0F", -- 0x1A40 + x"02",x"0B",x"0A",x"0C",x"0F",x"10",x"0B",x"06", -- 0x1A48 + x"0C",x"0F",x"1B",x"0B",x"01",x"0C",x"0F",x"00", -- 0x1A50 + x"0D",x"02",x"0C",x"0F",x"00",x"0F",x"1C",x"0C", -- 0x1A58 + x"0F",x"07",x"0C",x"83",x"23",x"0F",x"0C",x"0D", -- 0x1A60 + x"82",x"23",x"0F",x"0F",x"0D",x"82",x"23",x"0F", -- 0x1A68 + x"10",x"0E",x"06",x"23",x"0F",x"07",x"0F",x"0F", -- 0x1A70 + x"23",x"0F",x"0D",x"0D",x"00",x"05",x"33",x"09", -- 0x1A78 + x"14",x"07",x"17",x"04",x"04",x"0E",x"16",x"0E", -- 0x1A80 + x"17",x"0E",x"01",x"3A",x"01",x"12",x"00",x"08", -- 0x1A88 + x"45",x"55",x"47",x"45",x"4E",x"45",x"27",x"53", -- 0x1A90 + x"20",x"4C",x"41",x"49",x"52",x"00",x"10",x"08", -- 0x1A98 + x"09",x"48",x"01",x"00",x"00",x"03",x"05",x"44", -- 0x1AA0 + x"09",x"1B",x"01",x"1A",x"07",x"09",x"06",x"08", -- 0x1AA8 + x"0C",x"06",x"0C",x"21",x"60",x"50",x"18",x"50", -- 0x1AB0 + x"08",x"50",x"FF",x"60",x"20",x"38",x"20",x"20", -- 0x1AB8 + x"50",x"01",x"1C",x"0D",x"08",x"68",x"08",x"58", -- 0x1AC0 + x"01",x"00",x"14",x"04",x"01",x"3B",x"07",x"07", -- 0x1AC8 + x"05",x"03",x"0D",x"0F",x"0E",x"05",x"02",x"0D", -- 0x1AD0 + x"0F",x"14",x"05",x"05",x"0D",x"0F",x"02",x"06", -- 0x1AD8 + x"02",x"0D",x"0F",x"0F",x"06",x"82",x"24",x"09", -- 0x1AE0 + x"1A",x"06",x"02",x"0D",x"0F",x"15",x"08",x"04", -- 0x1AE8 + x"0D",x"0F",x"00",x"09",x"02",x"0D",x"0F",x"06", -- 0x1AF0 + x"0A",x"09",x"0D",x"0F",x"0F",x"0A",x"83",x"24", -- 0x1AF8 + x"09",x"10",x"0A",x"08",x"0D",x"0F",x"10",x"0B", -- 0x1B00 + x"01",x"3B",x"07",x"02",x"0C",x"01",x"34",x"03", -- 0x1B08 + x"1A",x"0C",x"02",x"0D",x"0F",x"02",x"0D",x"04", -- 0x1B10 + x"58",x"0F",x"15",x"0D",x"02",x"0D",x"0F",x"00", -- 0x1B18 + x"0F",x"1C",x"0D",x"0F",x"1A",x"00",x"00",x"00", -- 0x1B20 + x"33",x"01",x"00",x"3A",x"01",x"06",x"50",x"52", -- 0x1B28 + x"4F",x"43",x"45",x"53",x"53",x"49",x"4E",x"47", -- 0x1B30 + x"20",x"50",x"4C",x"41",x"4E",x"54",x"00",x"02", -- 0x1B38 + x"0D",x"04",x"58",x"0F",x"00",x"0F",x"03",x"05", -- 0x1B40 + x"45",x"1B",x"00",x"0A",x"0B",x"0B",x"0E",x"06", -- 0x1B48 + x"10",x"06",x"1B",x"07",x"40",x"70",x"30",x"40", -- 0x1B50 + x"30",x"30",x"60",x"01",x"70",x"70",x"40",x"70", -- 0x1B58 + x"70",x"A0",x"01",x"70",x"38",x"68",x"38",x"38", -- 0x1B60 + x"98",x"01",x"70",x"B8",x"68",x"B8",x"B8",x"D8", -- 0x1B68 + x"01",x"00",x"0D",x"00",x"0F",x"25",x"05",x"0E", -- 0x1B70 + x"03",x"02",x"0B",x"09",x"10",x"03",x"8A",x"25", -- 0x1B78 + x"05",x"11",x"03",x"0B",x"90",x"01",x"11",x"04", -- 0x1B80 + x"0B",x"90",x"01",x"06",x"05",x"04",x"58",x"0F", -- 0x1B88 + x"0D",x"05",x"03",x"0B",x"09",x"11",x"05",x"0B", -- 0x1B90 + x"90",x"01",x"00",x"06",x"03",x"0B",x"09",x"11", -- 0x1B98 + x"06",x"0B",x"90",x"01",x"11",x"07",x"0B",x"90", -- 0x1BA0 + x"01",x"00",x"08",x"01",x"0B",x"09",x"11",x"08", -- 0x1BA8 + x"0B",x"90",x"01",x"0D",x"09",x"03",x"0B",x"09", -- 0x1BB0 + x"11",x"09",x"0B",x"90",x"01",x"01",x"0A",x"0A", -- 0x1BB8 + x"0B",x"09",x"11",x"0A",x"0B",x"90",x"01",x"11", -- 0x1BC0 + x"0B",x"0B",x"90",x"01",x"0D",x"0C",x"03",x"25", -- 0x1BC8 + x"05",x"11",x"0C",x"0B",x"90",x"01",x"08",x"0D", -- 0x1BD0 + x"03",x"0B",x"09",x"0D",x"0D",x"82",x"25",x"05", -- 0x1BD8 + x"00",x"0F",x"1C",x"0B",x"09",x"0D",x"0F",x"0F", -- 0x1BE0 + x"25",x"05",x"0E",x"0D",x"00",x"00",x"34",x"01", -- 0x1BE8 + x"04",x"18",x"09",x"19",x"05",x"16",x"08",x"19", -- 0x1BF0 + x"0A",x"16",x"0C",x"0B",x"54",x"48",x"45",x"20", -- 0x1BF8 + x"56",x"41",x"54",x"00",x"06",x"05",x"04",x"58", -- 0x1C00 + x"0F",x"01",x"00",x"0D",x"05",x"45",x"1B",x"1B", -- 0x1C08 + x"03",x"13",x"06",x"18",x"07",x"12",x"0A",x"1B", -- 0x1C10 + x"0B",x"30",x"80",x"70",x"08",x"70",x"70",x"D0", -- 0x1C18 + x"01",x"80",x"08",x"40",x"08",x"08",x"50",x"01", -- 0x1C20 + x"80",x"80",x"68",x"80",x"80",x"D0",x"01",x"00", -- 0x1C28 + x"01",x"00",x"01",x"3C",x"09",x"09",x"00",x"01", -- 0x1C30 + x"3C",x"09",x"13",x"00",x"82",x"26",x"09",x"10", -- 0x1C38 + x"00",x"8F",x"26",x"09",x"0E",x"02",x"02",x"08", -- 0x1C40 + x"01",x"1A",x"02",x"02",x"08",x"01",x"00",x"05", -- 0x1C48 + x"03",x"08",x"01",x"08",x"05",x"06",x"08",x"01", -- 0x1C50 + x"11",x"05",x"02",x"08",x"01",x"14",x"06",x"02", -- 0x1C58 + x"08",x"01",x"1B",x"06",x"01",x"08",x"01",x"01", -- 0x1C60 + x"07",x"03",x"08",x"01",x"18",x"07",x"01",x"08", -- 0x1C68 + x"01",x"07",x"08",x"03",x"08",x"01",x"11",x"09", -- 0x1C70 + x"03",x"08",x"01",x"00",x"0A",x"01",x"08",x"01", -- 0x1C78 + x"0B",x"0A",x"03",x"08",x"01",x"18",x"0A",x"03", -- 0x1C80 + x"08",x"01",x"08",x"0B",x"02",x"08",x"01",x"03", -- 0x1C88 + x"0C",x"02",x"08",x"01",x"15",x"0C",x"04",x"08", -- 0x1C90 + x"01",x"0A",x"0D",x"02",x"58",x"0F",x"0D",x"0D", -- 0x1C98 + x"82",x"26",x"09",x"11",x"0D",x"02",x"08",x"01", -- 0x1CA0 + x"15",x"0E",x"01",x"30",x"0F",x"00",x"0F",x"1C", -- 0x1CA8 + x"08",x"01",x"05",x"00",x"01",x"46",x"0F",x"11", -- 0x1CB0 + x"00",x"01",x"46",x"0F",x"0E",x"0D",x"00",x"00", -- 0x1CB8 + x"33",x"01",x"00",x"3A",x"01",x"00",x"4D",x"49", -- 0x1CC0 + x"4E",x"45",x"52",x"20",x"57",x"49",x"4C",x"4C", -- 0x1CC8 + x"59",x"20",x"4D",x"45",x"45",x"54",x"53",x"20", -- 0x1CD0 + x"4B",x"4F",x"4E",x"47",x"20",x"42",x"45",x"41", -- 0x1CD8 + x"53",x"54",x"00",x"0A",x"0D",x"03",x"58",x"0F", -- 0x1CE0 + x"00",x"00",x"0D",x"04",x"45",x"1B",x"0C",x"02", -- 0x1CE8 + x"0D",x"06",x"01",x"08",x"1A",x"0D",x"31",x"A0", -- 0x1CF0 + x"44",x"68",x"44",x"00",x"48",x"FF",x"A0",x"68", -- 0x1CF8 + x"58",x"68",x"54",x"74",x"01",x"A0",x"88",x"38", -- 0x1D00 + x"88",x"88",x"98",x"01",x"90",x"0E",x"00",x"70", -- 0x1D08 + x"00",x"68",x"00",x"00",x"02",x"00",x"01",x"27", -- 0x1D10 + x"09",x"00",x"05",x"04",x"0B",x"09",x"06",x"05", -- 0x1D18 + x"02",x"0B",x"09",x"0A",x"05",x"08",x"0B",x"09", -- 0x1D20 + x"14",x"05",x"02",x"0B",x"09",x"18",x"05",x"02", -- 0x1D28 + x"0B",x"09",x"1A",x"07",x"02",x"0B",x"09",x"02", -- 0x1D30 + x"08",x"02",x"0B",x"09",x"06",x"08",x"02",x"0B", -- 0x1D38 + x"09",x"0A",x"08",x"08",x"58",x"0F",x"14",x"09", -- 0x1D40 + x"02",x"0B",x"09",x"18",x"09",x"02",x"0B",x"09", -- 0x1D48 + x"00",x"0A",x"02",x"0B",x"09",x"02",x"0C",x"02", -- 0x1D50 + x"0B",x"09",x"06",x"0C",x"02",x"0B",x"09",x"0A", -- 0x1D58 + x"0C",x"08",x"0B",x"09",x"14",x"0C",x"02",x"0B", -- 0x1D60 + x"09",x"18",x"0C",x"02",x"0B",x"09",x"1A",x"0D", -- 0x1D68 + x"02",x"0B",x"09",x"00",x"0F",x"1C",x"0B",x"09", -- 0x1D70 + x"00",x"00",x"00",x"00",x"33",x"01",x"00",x"3A", -- 0x1D78 + x"01",x"06",x"57",x"41",x"43",x"4B",x"59",x"20", -- 0x1D80 + x"41",x"4D",x"4F",x"45",x"42",x"41",x"54",x"52", -- 0x1D88 + x"4F",x"4E",x"53",x"00",x"0A",x"08",x"08",x"58", -- 0x1D90 + x"0F",x"01",x"00",x"0D",x"01",x"45",x"1B",x"10", -- 0x1D98 + x"01",x"24",x"C0",x"58",x"18",x"58",x"58",x"80", -- 0x1DA0 + x"01",x"C0",x"58",x"50",x"58",x"58",x"80",x"01", -- 0x1DA8 + x"B0",x"04",x"08",x"20",x"04",x"68",x"01",x"B0", -- 0x1DB0 + x"08",x"08",x"40",x"04",x"68",x"02",x"B0",x"12", -- 0x1DB8 + x"08",x"90",x"04",x"68",x"01",x"B0",x"16",x"08", -- 0x1DC0 + x"B0",x"04",x"68",x"02",x"00",x"0C",x"00",x"03", -- 0x1DC8 + x"0E",x"0F",x"0F",x"00",x"8C",x"28",x"09",x"14", -- 0x1DD0 + x"00",x"08",x"0E",x"0F",x"00",x"02",x"06",x"0E", -- 0x1DD8 + x"0F",x"1A",x"02",x"02",x"0E",x"0F",x"10",x"04", -- 0x1DE0 + x"04",x"0E",x"0F",x"07",x"05",x"01",x"0E",x"0F", -- 0x1DE8 + x"08",x"05",x"07",x"78",x"01",x"16",x"05",x"06", -- 0x1DF0 + x"0E",x"0F",x"00",x"06",x"04",x"0E",x"0F",x"10", -- 0x1DF8 + x"07",x"07",x"0E",x"0F",x"17",x"07",x"03",x"78", -- 0x1E00 + x"01",x"00",x"08",x"05",x"0E",x"0F",x"08",x"09", -- 0x1E08 + x"07",x"0E",x"0F",x"1A",x"09",x"02",x"0E",x"0F", -- 0x1E10 + x"00",x"0A",x"04",x"0E",x"0F",x"04",x"0A",x"02", -- 0x1E18 + x"78",x"01",x"10",x"0A",x"07",x"0E",x"0F",x"17", -- 0x1E20 + x"0B",x"03",x"78",x"01",x"07",x"0C",x"0A",x"13", -- 0x1E28 + x"05",x"00",x"0D",x"03",x"0E",x"0F",x"19",x"0D", -- 0x1E30 + x"03",x"0E",x"0F",x"00",x"0F",x"1C",x"13",x"05", -- 0x1E38 + x"0B",x"0D",x"00",x"08",x"37",x"0F",x"0A",x"00", -- 0x1E40 + x"11",x"00",x"13",x"00",x"14",x"01",x"02",x"03", -- 0x1E48 + x"00",x"09",x"1B",x"0A",x"16",x"0B",x"00",x"3B", -- 0x1E50 + x"01",x"05",x"54",x"48",x"45",x"20",x"45",x"4E", -- 0x1E58 + x"44",x"4F",x"52",x"49",x"41",x"4E",x"20",x"46", -- 0x1E60 + x"4F",x"52",x"45",x"53",x"54",x"00",x"02",x"0D", -- 0x1E68 + x"00",x"58",x"0F",x"00",x"00",x"04",x"05",x"45", -- 0x1E70 + x"1B",x"0D",x"01",x"1B",x"01",x"14",x"02",x"0B", -- 0x1E78 + x"06",x"11",x"08",x"40",x"D0",x"40",x"38",x"40", -- 0x1E80 + x"40",x"68",x"01",x"D0",x"38",x"50",x"38",x"38", -- 0x1E88 + x"68",x"01",x"D0",x"18",x"68",x"18",x"18",x"B8", -- 0x1E90 + x"01",x"D0",x"80",x"28",x"80",x"80",x"A0",x"01", -- 0x1E98 + x"00",x"00",x"00",x"06",x"2A",x"07",x"00",x"03", -- 0x1EA0 + x"04",x"0F",x"01",x"04",x"05",x"06",x"0F",x"01", -- 0x1EA8 + x"0E",x"05",x"02",x"0F",x"01",x"10",x"05",x"05", -- 0x1EB0 + x"14",x"05",x"15",x"05",x"02",x"0F",x"01",x"1A", -- 0x1EB8 + x"06",x"02",x"0F",x"01",x"00",x"08",x"02",x"0F", -- 0x1EC0 + x"01",x"04",x"08",x"02",x"80",x"09",x"1A",x"08", -- 0x1EC8 + x"02",x"0F",x"01",x"0A",x"09",x"07",x"0F",x"01", -- 0x1ED0 + x"19",x"0A",x"01",x"0F",x"01",x"05",x"0B",x"03", -- 0x1ED8 + x"80",x"10",x"08",x"0B",x"01",x"0F",x"01",x"19", -- 0x1EE0 + x"0C",x"03",x"0F",x"01",x"00",x"0D",x"02",x"0F", -- 0x1EE8 + x"01",x"14",x"0D",x"03",x"0F",x"01",x"00",x"0F", -- 0x1EF0 + x"1C",x"0F",x"0F",x"00",x"01",x"00",x"04",x"1A", -- 0x1EF8 + x"09",x"10",x"01",x"15",x"09",x"10",x"0B",x"0B", -- 0x1F00 + x"0C",x"07",x"1B",x"01",x"10",x"00",x"15",x"06", -- 0x1F08 + x"15",x"07",x"15",x"08",x"0B",x"0A",x"0B",x"0B", -- 0x1F10 + x"10",x"0A",x"01",x"41",x"54",x"54",x"41",x"43", -- 0x1F18 + x"4B",x"20",x"4F",x"46",x"20",x"54",x"48",x"45", -- 0x1F20 + x"20",x"4D",x"55",x"54",x"41",x"4E",x"54",x"20", -- 0x1F28 + x"50",x"48",x"4F",x"4E",x"45",x"53",x"00",x"04", -- 0x1F30 + x"08",x"02",x"50",x"09",x"00",x"02",x"01",x"05", -- 0x1F38 + x"45",x"1B",x"15",x"00",x"1B",x"01",x"00",x"04", -- 0x1F40 + x"11",x"06",x"1B",x"0D",x"24",x"F0",x"70",x"18", -- 0x1F48 + x"70",x"70",x"A8",x"01",x"F0",x"20",x"68",x"20", -- 0x1F50 + x"20",x"90",x"01",x"E0",x"02",x"20",x"10",x"20", -- 0x1F58 + x"68",x"02",x"E0",x"0B",x"02",x"58",x"02",x"38", -- 0x1F60 + x"01",x"E0",x"12",x"30",x"90",x"30",x"68",x"01", -- 0x1F68 + x"E0",x"17",x"02",x"B8",x"02",x"68",x"FD",x"00", -- 0x1F70 + x"05",x"00",x"01",x"46",x"07",x"10",x"00",x"01", -- 0x1F78 + x"25",x"07",x"11",x"00",x"01",x"46",x"07",x"14", -- 0x1F80 + x"00",x"01",x"25",x"07",x"0E",x"02",x"02",x"80", -- 0x1F88 + x"01",x"00",x"05",x"03",x"08",x"01",x"08",x"05", -- 0x1F90 + x"05",x"80",x"01",x"0D",x"05",x"85",x"25",x"07", -- 0x1F98 + x"10",x"05",x"8B",x"25",x"07",x"11",x"05",x"04", -- 0x1FA0 + x"80",x"01",x"15",x"05",x"02",x"08",x"01",x"1B", -- 0x1FA8 + x"06",x"01",x"08",x"01",x"05",x"07",x"02",x"08", -- 0x1FB0 + x"01",x"02",x"08",x"01",x"08",x"01",x"16",x"08", -- 0x1FB8 + x"06",x"08",x"0F",x"09",x"09",x"04",x"08",x"01", -- 0x1FC0 + x"05",x"0A",x"01",x"08",x"01",x"11",x"0A",x"03", -- 0x1FC8 + x"08",x"01",x"16",x"0B",x"02",x"08",x"01",x"00", -- 0x1FD0 + x"0C",x"06",x"08",x"01",x"0A",x"0D",x"03",x"08", -- 0x1FD8 + x"01",x"0D",x"0D",x"83",x"25",x"07",x"11",x"0D", -- 0x1FE0 + x"08",x"50",x"09",x"00",x"0F",x"0D",x"08",x"01", -- 0x1FE8 + x"0D",x"0F",x"03",x"08",x"01",x"11",x"0F",x"0B", -- 0x1FF0 + x"08",x"01",x"0E",x"0D",x"00",x"02",x"30",x"0F", -- 0x1FF8 + x"14",x"0C",x"19",x"0C",x"02",x"3C",x"05",x"01", -- 0x2000 + x"00",x"09",x"00",x"00",x"52",x"45",x"54",x"55", -- 0x2008 + x"52",x"4E",x"20",x"4F",x"46",x"20",x"41",x"4C", -- 0x2010 + x"49",x"45",x"4E",x"20",x"4B",x"4F",x"4E",x"47", -- 0x2018 + x"20",x"42",x"45",x"41",x"53",x"54",x"00",x"11", -- 0x2020 + x"0D",x"09",x"50",x"09",x"01",x"00",x"0D",x"05", -- 0x2028 + x"45",x"1B",x"0E",x"03",x"17",x"05",x"01",x"06", -- 0x2030 + x"0F",x"07",x"1A",x"0D",x"31",x"A0",x"40",x"68", -- 0x2038 + x"40",x"00",x"40",x"FF",x"A0",x"50",x"58",x"50", -- 0x2040 + x"50",x"70",x"01",x"A0",x"B0",x"30",x"B0",x"B0", -- 0x2048 + x"C8",x"01",x"90",x"0E",x"00",x"70",x"00",x"70", -- 0x2050 + x"00",x"00",x"00",x"00",x"1C",x"27",x"09",x"02", -- 0x2058 + x"01",x"8E",x"16",x"09",x"06",x"03",x"12",x"05", -- 0x2060 + x"05",x"1A",x"03",x"02",x"05",x"05",x"06",x"06", -- 0x2068 + x"02",x"05",x"05",x"0A",x"06",x"04",x"05",x"05", -- 0x2070 + x"10",x"06",x"05",x"05",x"05",x"17",x"06",x"02", -- 0x2078 + x"05",x"05",x"1B",x"06",x"01",x"05",x"05",x"06", -- 0x2080 + x"09",x"05",x"05",x"05",x"0D",x"09",x"03",x"05", -- 0x2088 + x"05",x"13",x"09",x"03",x"05",x"05",x"18",x"09", -- 0x2090 + x"04",x"05",x"05",x"06",x"0C",x"03",x"05",x"05", -- 0x2098 + x"0B",x"0C",x"03",x"05",x"05",x"10",x"0C",x"04", -- 0x20A0 + x"05",x"05",x"16",x"0C",x"02",x"05",x"05",x"1A", -- 0x20A8 + x"0C",x"02",x"05",x"05",x"00",x"0F",x"02",x"05", -- 0x20B0 + x"05",x"02",x"0F",x"18",x"58",x"0F",x"1A",x"0F", -- 0x20B8 + x"02",x"05",x"05",x"00",x"0D",x"00",x"00",x"33", -- 0x20C0 + x"01",x"00",x"3A",x"01",x"08",x"4F",x"52",x"45", -- 0x20C8 + x"20",x"52",x"45",x"46",x"49",x"4E",x"45",x"52", -- 0x20D0 + x"59",x"00",x"02",x"0F",x"18",x"58",x"0F",x"01", -- 0x20D8 + x"1A",x"0D",x"05",x"45",x"1B",x"18",x"03",x"09", -- 0x20E0 + x"06",x"12",x"09",x"17",x"09",x"0A",x"0C",x"41", -- 0x20E8 + x"C0",x"30",x"08",x"30",x"30",x"D0",x"02",x"C0", -- 0x20F0 + x"80",x"20",x"80",x"30",x"D0",x"01",x"C0",x"88", -- 0x20F8 + x"38",x"88",x"30",x"D0",x"FE",x"C0",x"98",x"50", -- 0x2100 + x"98",x"30",x"D0",x"01",x"B0",x"04",x"38",x"20", -- 0x2108 + x"08",x"68",x"02",x"01",x"0E",x"05",x"01",x"06", -- 0x2110 + x"05",x"0F",x"05",x"01",x"07",x"05",x"02",x"06", -- 0x2118 + x"01",x"06",x"05",x"03",x"06",x"01",x"07",x"05", -- 0x2120 + x"0A",x"06",x"01",x"06",x"05",x"0B",x"06",x"01", -- 0x2128 + x"07",x"05",x"12",x"06",x"01",x"06",x"05",x"13", -- 0x2130 + x"06",x"01",x"07",x"05",x"1A",x"06",x"01",x"06", -- 0x2138 + x"05",x"1B",x"06",x"01",x"07",x"05",x"06",x"07", -- 0x2140 + x"01",x"06",x"05",x"07",x"07",x"01",x"07",x"05", -- 0x2148 + x"16",x"07",x"01",x"06",x"05",x"17",x"07",x"01", -- 0x2150 + x"07",x"05",x"04",x"09",x"01",x"06",x"05",x"05", -- 0x2158 + x"09",x"01",x"07",x"05",x"0C",x"09",x"01",x"06", -- 0x2160 + x"05",x"0D",x"09",x"01",x"07",x"05",x"14",x"09", -- 0x2168 + x"01",x"06",x"05",x"15",x"09",x"01",x"07",x"05", -- 0x2170 + x"1A",x"09",x"01",x"06",x"05",x"1B",x"09",x"01", -- 0x2178 + x"07",x"05",x"00",x"0B",x"01",x"06",x"05",x"01", -- 0x2180 + x"0B",x"01",x"07",x"05",x"08",x"0B",x"01",x"06", -- 0x2188 + x"05",x"09",x"0B",x"01",x"07",x"05",x"0E",x"0B", -- 0x2190 + x"06",x"58",x"0F",x"18",x"0B",x"01",x"06",x"05", -- 0x2198 + x"19",x"0B",x"01",x"07",x"05",x"06",x"0D",x"01", -- 0x21A0 + x"06",x"05",x"07",x"0D",x"01",x"07",x"05",x"00", -- 0x21A8 + x"0F",x"1C",x"29",x"05",x"0E",x"00",x"00",x"00", -- 0x21B0 + x"33",x"01",x"00",x"3A",x"01",x"05",x"53",x"4B", -- 0x21B8 + x"59",x"4C",x"41",x"42",x"20",x"4C",x"41",x"4E", -- 0x21C0 + x"44",x"49",x"4E",x"47",x"20",x"42",x"41",x"59", -- 0x21C8 + x"00",x"0E",x"0B",x"06",x"58",x"0F",x"00",x"1A", -- 0x21D0 + x"0D",x"04",x"44",x"01",x"16",x"02",x"0F",x"07", -- 0x21D8 + x"1A",x"07",x"02",x"08",x"03",x"E0",x"00",x"20", -- 0x21E0 + x"00",x"00",x"48",x"04",x"E0",x"0A",x"00",x"50", -- 0x21E8 + x"00",x"20",x"01",x"E0",x"14",x"10",x"A0",x"00", -- 0x21F0 + x"38",x"03",x"00",x"04",x"00",x"18",x"2A",x"07", -- 0x21F8 + x"1A",x"01",x"8E",x"15",x"07",x"1B",x"01",x"8E", -- 0x2200 + x"15",x"07",x"06",x"03",x"0F",x"50",x"05",x"15", -- 0x2208 + x"03",x"05",x"0F",x"01",x"06",x"04",x"01",x"1B", -- 0x2210 + x"01",x"06",x"05",x"01",x"1A",x"09",x"19",x"04", -- 0x2218 + x"86",x"1B",x"01",x"19",x"0A",x"01",x"1A",x"09", -- 0x2220 + x"00",x"05",x"04",x"0F",x"01",x"15",x"06",x"02", -- 0x2228 + x"0F",x"01",x"05",x"07",x"01",x"80",x"10",x"0A", -- 0x2230 + x"07",x"02",x"0F",x"01",x"02",x"08",x"02",x"0F", -- 0x2238 + x"01",x"10",x"08",x"02",x"0F",x"01",x"16",x"09", -- 0x2240 + x"02",x"0F",x"01",x"00",x"0A",x"02",x"0F",x"01", -- 0x2248 + x"0A",x"0A",x"02",x"0F",x"01",x"10",x"0B",x"02", -- 0x2250 + x"0F",x"01",x"04",x"0C",x"02",x"0F",x"01",x"15", -- 0x2258 + x"0C",x"02",x"0F",x"01",x"0A",x"0D",x"02",x"0F", -- 0x2260 + x"01",x"00",x"0F",x"1C",x"0F",x"01",x"00",x"03", -- 0x2268 + x"00",x"00",x"33",x"01",x"00",x"3A",x"01",x"0A", -- 0x2270 + x"54",x"48",x"45",x"20",x"42",x"41",x"4E",x"4B", -- 0x2278 + x"00",x"06",x"03",x"0F",x"50",x"05",x"00",x"01", -- 0x2280 + x"0D",x"03",x"45",x"1B",x"16",x"02",x"0A",x"06", -- 0x2288 + x"18",x"0E",x"13",x"C0",x"78",x"68",x"78",x"78", -- 0x2290 + x"88",x"01",x"E0",x"07",x"28",x"38",x"24",x"68", -- 0x2298 + x"02",x"E0",x"0D",x"40",x"68",x"24",x"68",x"01", -- 0x22A0 + x"E0",x"12",x"50",x"90",x"20",x"68",x"FD",x"00", -- 0x22A8 + x"00",x"05",x"01",x"08",x"01",x"05",x"05",x"01", -- 0x22B0 + x"08",x"01",x"14",x"05",x"02",x"08",x"01",x"03", -- 0x22B8 + x"07",x"01",x"08",x"01",x"16",x"07",x"06",x"08", -- 0x22C0 + x"01",x"0A",x"05",x"84",x"2B",x"17",x"0D",x"05", -- 0x22C8 + x"84",x"2B",x"17",x"0E",x"06",x"83",x"2B",x"17", -- 0x22D0 + x"0F",x"07",x"82",x"2B",x"17",x"10",x"08",x"81", -- 0x22D8 + x"2B",x"17",x"00",x"09",x"02",x"80",x"01",x"02", -- 0x22E0 + x"09",x"18",x"50",x"09",x"09",x"0B",x"02",x"2B", -- 0x22E8 + x"17",x"0B",x"0B",x"02",x"08",x"01",x"0B",x"0B", -- 0x22F0 + x"02",x"08",x"01",x"19",x"0B",x"01",x"08",x"01", -- 0x22F8 + x"00",x"0C",x"09",x"08",x"01",x"13",x"0D",x"01", -- 0x2300 + x"08",x"01",x"19",x"0D",x"01",x"08",x"01",x"16", -- 0x2308 + x"0E",x"03",x"36",x"0F",x"00",x"0F",x"1C",x"08", -- 0x2310 + x"01",x"0B",x"05",x"00",x"00",x"33",x"01",x"00", -- 0x2318 + x"3A",x"01",x"04",x"54",x"48",x"45",x"20",x"53", -- 0x2320 + x"49",x"58",x"54",x"45",x"45",x"4E",x"54",x"48", -- 0x2328 + x"20",x"43",x"41",x"56",x"45",x"52",x"4E",x"00", -- 0x2330 + x"02",x"09",x"18",x"50",x"09",x"00",x"01",x"0D", -- 0x2338 + x"04",x"45",x"1B",x"00",x"00",x"1B",x"02",x"0C", -- 0x2340 + x"07",x"10",x"0A",x"40",x"20",x"B0",x"28",x"B0", -- 0x2348 + x"B0",x"D0",x"01",x"20",x"88",x"38",x"88",x"88", -- 0x2350 + x"A0",x"01",x"20",x"10",x"50",x"10",x"02",x"38", -- 0x2358 + x"01",x"20",x"50",x"68",x"50",x"02",x"88",x"01", -- 0x2360 + x"00",x"00",x"05",x"1C",x"90",x"05",x"00",x"06", -- 0x2368 + x"1C",x"90",x"05",x"00",x"07",x"1C",x"90",x"05", -- 0x2370 + x"00",x"08",x"1C",x"90",x"05",x"00",x"09",x"1C", -- 0x2378 + x"90",x"05",x"00",x"0A",x"1C",x"90",x"05",x"00", -- 0x2380 + x"0B",x"1C",x"90",x"05",x"00",x"0C",x"1C",x"90", -- 0x2388 + x"05",x"02",x"08",x"85",x"00",x"00",x"03",x"08", -- 0x2390 + x"85",x"00",x"00",x"08",x"05",x"88",x"00",x"00", -- 0x2398 + x"09",x"05",x"88",x"00",x"00",x"11",x"05",x"85", -- 0x23A0 + x"00",x"00",x"12",x"05",x"85",x"00",x"00",x"18", -- 0x23A8 + x"05",x"88",x"00",x"00",x"19",x"05",x"88",x"00", -- 0x23B0 + x"00",x"0C",x"08",x"05",x"58",x"0F",x"00",x"05", -- 0x23B8 + x"02",x"11",x"05",x"1A",x"05",x"02",x"11",x"05", -- 0x23C0 + x"18",x"0E",x"04",x"11",x"05",x"00",x"0F",x"1C", -- 0x23C8 + x"11",x"05",x"1A",x"01",x"00",x"06",x"32",x"07", -- 0x23D0 + x"05",x"04",x"07",x"04",x"0B",x"04",x"0E",x"04", -- 0x23D8 + x"14",x"04",x"16",x"04",x"04",x"3E",x"05",x"02", -- 0x23E0 + x"06",x"17",x"07",x"14",x"0A",x"07",x"0B",x"08", -- 0x23E8 + x"54",x"48",x"45",x"20",x"57",x"41",x"52",x"45", -- 0x23F0 + x"48",x"4F",x"55",x"53",x"45",x"00",x"0C",x"08", -- 0x23F8 + x"05",x"58",x"0F",x"01",x"00",x"03",x"05",x"45", -- 0x2400 + x"1B",x"16",x"05",x"0D",x"07",x"00",x"09",x"11", -- 0x2408 + x"0A",x"17",x"0B",x"24",x"70",x"20",x"68",x"20", -- 0x2410 + x"20",x"30",x"01",x"70",x"50",x"68",x"50",x"50", -- 0x2418 + x"B0",x"01",x"40",x"02",x"40",x"10",x"40",x"68", -- 0x2420 + x"02",x"40",x"08",x"40",x"40",x"00",x"68",x"FD", -- 0x2428 + x"40",x"11",x"30",x"88",x"00",x"40",x"01",x"40", -- 0x2430 + x"18",x"00",x"C0",x"00",x"60",x"04",x"00",x"19", -- 0x2438 + x"00",x"01",x"2D",x"09",x"02",x"05",x"1A",x"08", -- 0x2440 + x"01",x"00",x"07",x"02",x"08",x"01",x"0B",x"08", -- 0x2448 + x"11",x"08",x"01",x"02",x"09",x"07",x"08",x"01", -- 0x2450 + x"1B",x"0A",x"01",x"08",x"01",x"02",x"0C",x"1A", -- 0x2458 + x"08",x"01",x"00",x"0D",x"02",x"08",x"01",x"04", -- 0x2460 + x"05",x"88",x"00",x"00",x"05",x"05",x"88",x"00", -- 0x2468 + x"00",x"09",x"05",x"88",x"00",x"00",x"0A",x"05", -- 0x2470 + x"88",x"00",x"00",x"13",x"05",x"88",x"00",x"00", -- 0x2478 + x"14",x"05",x"88",x"00",x"00",x"18",x"05",x"88", -- 0x2480 + x"00",x"00",x"19",x"05",x"88",x"00",x"00",x"00", -- 0x2488 + x"0F",x"1C",x"08",x"01",x"1A",x"00",x"00",x"00", -- 0x2490 + x"34",x"01",x"00",x"3B",x"01",x"04",x"4F",x"4D", -- 0x2498 + x"4F",x"45",x"42",x"41",x"54",x"52",x"4F",x"4E", -- 0x24A0 + x"53",x"27",x"20",x"52",x"45",x"56",x"45",x"4E", -- 0x24A8 + x"47",x"45",x"00",x"02",x"0D",x"00",x"58",x"0F", -- 0x24B0 + x"00",x"1A",x"0D",x"01",x"45",x"1B",x"0F",x"01", -- 0x24B8 + x"34",x"C0",x"58",x"30",x"58",x"58",x"88",x"02", -- 0x24C0 + x"C0",x"78",x"50",x"78",x"58",x"88",x"01",x"C0", -- 0x24C8 + x"70",x"68",x"70",x"58",x"88",x"FE",x"B0",x"04", -- 0x24D0 + x"68",x"20",x"05",x"68",x"FC",x"B0",x"09",x"48", -- 0x24D8 + x"48",x"05",x"68",x"02",x"B0",x"13",x"48",x"98", -- 0x24E0 + x"05",x"68",x"04",x"B0",x"18",x"28",x"C0",x"05", -- 0x24E8 + x"68",x"01",x"0F",x"00",x"00",x"02",x"20",x"09", -- 0x24F0 + x"02",x"05",x"01",x"12",x"15",x"07",x"05",x"06", -- 0x24F8 + x"12",x"15",x"15",x"05",x"07",x"12",x"15",x"11", -- 0x2500 + x"07",x"02",x"12",x"15",x"00",x"08",x"01",x"12", -- 0x2508 + x"15",x"0B",x"08",x"03",x"12",x"15",x"15",x"08", -- 0x2510 + x"07",x"12",x"15",x"11",x"0A",x"01",x"12",x"15", -- 0x2518 + x"00",x"0B",x"03",x"12",x"15",x"0C",x"0C",x"05", -- 0x2520 + x"12",x"15",x"15",x"0B",x"07",x"12",x"15",x"00", -- 0x2528 + x"0E",x"02",x"20",x"09",x"00",x"0F",x"02",x"20", -- 0x2530 + x"09",x"02",x"0F",x"1A",x"12",x"15",x"14",x"0F", -- 0x2538 + x"01",x"20",x"09",x"00",x"01",x"00",x"00",x"33", -- 0x2540 + x"01",x"00",x"3A",x"01",x"04",x"53",x"4F",x"4C", -- 0x2548 + x"41",x"52",x"20",x"50",x"4F",x"57",x"45",x"52", -- 0x2550 + x"20",x"47",x"45",x"4E",x"45",x"52",x"41",x"54", -- 0x2558 + x"4F",x"52",x"00",x"05",x"0C",x"04",x"58",x"0F", -- 0x2560 + x"00",x"0C",x"0A",x"03",x"44",x"0F",x"1B",x"01", -- 0x2568 + x"00",x"05",x"1B",x"0C",x"43",x"70",x"B8",x"18", -- 0x2570 + x"B8",x"A0",x"D0",x"02",x"70",x"D0",x"30",x"D0", -- 0x2578 + x"98",x"D0",x"FE",x"70",x"C8",x"48",x"C8",x"98", -- 0x2580 + x"D0",x"FF",x"70",x"78",x"68",x"78",x"60",x"D0", -- 0x2588 + x"02",x"E0",x"03",x"58",x"18",x"04",x"68",x"03", -- 0x2590 + x"E0",x"09",x"38",x"48",x"30",x"68",x"FE",x"E0", -- 0x2598 + x"0E",x"48",x"70",x"02",x"50",x"FF",x"00",x"00", -- 0x25A0 + x"00",x"05",x"03",x"0F",x"00",x"01",x"05",x"03", -- 0x25A8 + x"0F",x"00",x"02",x"04",x"03",x"0F",x"02",x"02", -- 0x25B0 + x"84",x"28",x"09",x"05",x"00",x"17",x"01",x"01", -- 0x25B8 + x"05",x"01",x"17",x"01",x"01",x"04",x"02",x"18", -- 0x25C0 + x"01",x"01",x"17",x"02",x"05",x"04",x"01",x"17", -- 0x25C8 + x"03",x"05",x"04",x"01",x"00",x"03",x"83",x"01", -- 0x25D0 + x"01",x"01",x"03",x"83",x"01",x"01",x"03",x"03", -- 0x25D8 + x"0C",x"01",x"01",x"03",x"04",x"03",x"01",x"01", -- 0x25E0 + x"06",x"04",x"01",x"3F",x"09",x"05",x"05",x"01", -- 0x25E8 + x"3F",x"09",x"07",x"04",x"02",x"2E",x"09",x"06", -- 0x25F0 + x"05",x"04",x"2E",x"09",x"09",x"04",x"01",x"1F", -- 0x25F8 + x"09",x"0A",x"05",x"01",x"1F",x"09",x"13",x"00", -- 0x2600 + x"01",x"3F",x"09",x"14",x"00",x"02",x"2E",x"09", -- 0x2608 + x"16",x"00",x"01",x"1F",x"09",x"13",x"01",x"82", -- 0x2610 + x"2E",x"0F",x"14",x"01",x"82",x"1E",x"01",x"15", -- 0x2618 + x"01",x"82",x"1E",x"01",x"16",x"01",x"82",x"2E", -- 0x2620 + x"0F",x"13",x"03",x"04",x"2E",x"0F",x"0A",x"04", -- 0x2628 + x"03",x"01",x"01",x"03",x"05",x"02",x"01",x"01", -- 0x2630 + x"0B",x"05",x"01",x"01",x"01",x"1A",x"08",x"02", -- 0x2638 + x"08",x"01",x"18",x"0A",x"01",x"80",x"01",x"19", -- 0x2640 + x"0B",x"01",x"08",x"01",x"00",x"0C",x"01",x"08", -- 0x2648 + x"01",x"03",x"0D",x"01",x"08",x"01",x"00",x"0F", -- 0x2650 + x"1C",x"08",x"01",x"0F",x"04",x"0D",x"24",x"15", -- 0x2658 + x"0D",x"05",x"03",x"24",x"15",x"12",x"05",x"83", -- 0x2660 + x"24",x"15",x"0D",x"06",x"03",x"24",x"15",x"00", -- 0x2668 + x"06",x"04",x"24",x"15",x"00",x"07",x"10",x"24", -- 0x2670 + x"15",x"04",x"06",x"03",x"03",x"0F",x"07",x"06", -- 0x2678 + x"02",x"01",x"01",x"09",x"06",x"04",x"03",x"0F", -- 0x2680 + x"0C",x"05",x"01",x"03",x"0F",x"10",x"05",x"00", -- 0x2688 + x"06",x"31",x"05",x"0D",x"04",x"0E",x"04",x"0F", -- 0x2690 + x"03",x"10",x"03",x"11",x"03",x"12",x"03",x"04", -- 0x2698 + x"1A",x"05",x"06",x"0B",x"09",x"0B",x"0E",x"0B", -- 0x26A0 + x"12",x"0B",x"06",x"54",x"48",x"45",x"20",x"46", -- 0x26A8 + x"49",x"4E",x"41",x"4C",x"20",x"42",x"41",x"52", -- 0x26B0 + x"52",x"49",x"45",x"52",x"00",x"00",x"0A",x"14", -- 0x26B8 + x"58",x"0F",x"01",x"19",x"0D",x"05",x"45",x"1B", -- 0x26C0 + x"14",x"05",x"1B",x"06",x"07",x"0B",x"0B",x"0B", -- 0x26C8 + x"10",x"0B",x"11",x"70",x"38",x"68",x"38",x"20", -- 0x26D0 + x"98",x"02",x"E0",x"15",x"30",x"A8",x"28",x"68", -- 0x26D8 + x"01",x"00",x"21",x"07",x"27",x"16",x"16",x"0E", -- 0x26E0 + x"0A",x"1E",x"00",x"06",x"1C",x"7E",x"23",x"E5", -- 0x26E8 + x"D5",x"F5",x"CD",x"6D",x"0B",x"F1",x"C6",x"80", -- 0x26F0 + x"77",x"CB",x"D4",x"36",x"1B",x"D1",x"E1",x"1C", -- 0x26F8 + x"10",x"EB",x"14",x"0D",x"20",x"E3",x"C9",x"20", -- 0x2700 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2708 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2710 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2718 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"50", -- 0x2720 + x"41",x"43",x"2D",x"4D",x"41",x"4E",x"49",x"43", -- 0x2728 + x"2D",x"4D",x"49",x"4E",x"45",x"52",x"2D",x"4D", -- 0x2730 + x"41",x"4E",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2738 + x"57",x"52",x"49",x"54",x"54",x"45",x"4E",x"20", -- 0x2740 + x"42",x"59",x"20",x"4A",x"49",x"4D",x"20",x"42", -- 0x2748 + x"41",x"47",x"4C",x"45",x"59",x"20",x"46",x"4F", -- 0x2750 + x"52",x"20",x"20",x"20",x"20",x"50",x"41",x"43", -- 0x2758 + x"4D",x"41",x"4E",x"20",x"41",x"52",x"43",x"41", -- 0x2760 + x"44",x"45",x"20",x"48",x"41",x"52",x"44",x"57", -- 0x2768 + x"41",x"52",x"45",x"2E",x"20",x"20",x"20",x"20", -- 0x2770 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2778 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2780 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2788 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2790 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2798 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x27A0 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x27A8 + x"20",x"20",x"4A",x"55",x"4D",x"50",x"20",x"3D", -- 0x27B0 + x"20",x"4A",x"4F",x"59",x"20",x"32",x"20",x"2D", -- 0x27B8 + x"3E",x"20",x"52",x"49",x"47",x"48",x"54",x"20", -- 0x27C0 + x"20",x"20",x"20",x"20",x"4D",x"55",x"53",x"49", -- 0x27C8 + x"43",x"20",x"4F",x"4E",x"2F",x"4F",x"46",x"46", -- 0x27D0 + x"20",x"3D",x"20",x"4A",x"4F",x"59",x"20",x"32", -- 0x27D8 + x"20",x"2D",x"3E",x"20",x"55",x"50",x"20",x"20", -- 0x27E0 + x"46",x"58",x"20",x"4F",x"4E",x"2F",x"4F",x"46", -- 0x27E8 + x"46",x"20",x"3D",x"20",x"4A",x"4F",x"59",x"20", -- 0x27F0 + x"32",x"20",x"2D",x"3E",x"20",x"44",x"4F",x"57", -- 0x27F8 + x"4E",x"2E",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2800 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2808 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2810 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"41", -- 0x2818 + x"49",x"52",x"20",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x2820 + x"E7",x"00",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x2828 + x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x2830 + x"E7",x"E7",x"E7",x"E7",x"00",x"48",x"49",x"53", -- 0x2838 + x"43",x"4F",x"52",x"45",x"20",x"00",x"20",x"20", -- 0x2840 + x"53",x"43",x"4F",x"52",x"45",x"20",x"00",x"00", -- 0x2848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3818 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3820 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3828 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3830 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3838 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..11395aeb --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,2077 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity ROM_PGM_1 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM_1 is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"C3",x"01",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x0000 + x"77",x"23",x"10",x"FC",x"C9",x"00",x"00",x"00", -- 0x0008 + x"85",x"6F",x"8C",x"95",x"67",x"7E",x"C9",x"00", -- 0x0010 + x"78",x"87",x"D7",x"5F",x"23",x"56",x"EB",x"C9", -- 0x0018 + x"E1",x"87",x"D7",x"5F",x"23",x"56",x"EB",x"E9", -- 0x0020 + x"ED",x"B0",x"AF",x"32",x"C0",x"50",x"C9",x"00", -- 0x0028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0030 + x"C3",x"68",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0058 + x"00",x"00",x"00",x"00",x"00",x"00",x"ED",x"45", -- 0x0060 + x"F3",x"F5",x"DD",x"E5",x"E5",x"D5",x"C5",x"AF", -- 0x0068 + x"32",x"00",x"50",x"32",x"C0",x"50",x"2A",x"00", -- 0x0070 + x"4C",x"23",x"22",x"00",x"4C",x"3E",x"00",x"B7", -- 0x0078 + x"C2",x"EE",x"00",x"21",x"53",x"4C",x"11",x"F2", -- 0x0080 + x"4F",x"01",x"0C",x"00",x"EF",x"11",x"04",x"00", -- 0x0088 + x"19",x"11",x"62",x"50",x"01",x"0C",x"00",x"EF", -- 0x0090 + x"3A",x"1B",x"4C",x"3C",x"32",x"1B",x"4C",x"E6", -- 0x0098 + x"01",x"28",x"1C",x"2A",x"51",x"4C",x"ED",x"5B", -- 0x00A0 + x"61",x"4C",x"22",x"FA",x"4F",x"ED",x"53",x"6A", -- 0x00A8 + x"50",x"2A",x"5F",x"4C",x"ED",x"5B",x"6F",x"4C", -- 0x00B0 + x"22",x"FC",x"4F",x"ED",x"53",x"6C",x"50",x"3A", -- 0x00B8 + x"50",x"4C",x"B7",x"28",x"14",x"AF",x"32",x"1C", -- 0x00C0 + x"4C",x"AF",x"32",x"50",x"4C",x"CD",x"DD",x"0C", -- 0x00C8 + x"CD",x"DC",x"0C",x"CD",x"B7",x"0C",x"CD",x"92", -- 0x00D0 + x"07",x"CD",x"AF",x"12",x"AF",x"32",x"C0",x"50", -- 0x00D8 + x"3E",x"01",x"32",x"00",x"50",x"C1",x"D1",x"E1", -- 0x00E0 + x"DD",x"E1",x"F1",x"FB",x"ED",x"4D",x"21",x"51", -- 0x00E8 + x"4C",x"11",x"F0",x"4F",x"01",x"10",x"00",x"EF", -- 0x00F0 + x"11",x"60",x"50",x"01",x"10",x"00",x"EF",x"18", -- 0x00F8 + x"BE",x"F3",x"31",x"F0",x"4F",x"ED",x"56",x"3E", -- 0x0100 + x"FF",x"D3",x"00",x"AF",x"21",x"00",x"50",x"01", -- 0x0108 + x"08",x"08",x"CF",x"AF",x"32",x"C0",x"50",x"21", -- 0x0110 + x"00",x"4C",x"06",x"BE",x"CF",x"CF",x"CF",x"CF", -- 0x0118 + x"3E",x"0F",x"32",x"4C",x"4C",x"32",x"4D",x"4C", -- 0x0120 + x"21",x"0D",x"4C",x"11",x"0E",x"4C",x"01",x"0C", -- 0x0128 + x"00",x"36",x"30",x"EF",x"AF",x"12",x"32",x"13", -- 0x0130 + x"4C",x"21",x"CE",x"FA",x"22",x"02",x"4C",x"21", -- 0x0138 + x"40",x"50",x"06",x"40",x"CF",x"3E",x"01",x"32", -- 0x0140 + x"00",x"50",x"FB",x"AF",x"32",x"C0",x"50",x"32", -- 0x0148 + x"48",x"4C",x"32",x"49",x"4C",x"32",x"4A",x"4C", -- 0x0150 + x"3E",x"01",x"32",x"1D",x"4C",x"3E",x"68",x"32", -- 0x0158 + x"1E",x"4C",x"3E",x"00",x"32",x"1F",x"4C",x"3E", -- 0x0160 + x"01",x"32",x"20",x"4C",x"AF",x"32",x"24",x"4C", -- 0x0168 + x"32",x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C", -- 0x0170 + x"AF",x"32",x"50",x"4C",x"32",x"48",x"4C",x"32", -- 0x0178 + x"49",x"4C",x"32",x"4A",x"4C",x"3E",x"01",x"CD", -- 0x0180 + x"A2",x"12",x"CD",x"24",x"0F",x"3A",x"0B",x"4C", -- 0x0188 + x"B7",x"20",x"14",x"21",x"D9",x"11",x"11",x"BC", -- 0x0190 + x"43",x"0E",x"01",x"CD",x"93",x"0B",x"CD",x"83", -- 0x0198 + x"0B",x"3A",x"0B",x"4C",x"B7",x"28",x"F7",x"21", -- 0x01A0 + x"BD",x"11",x"11",x"BC",x"43",x"0E",x"01",x"CD", -- 0x01A8 + x"93",x"0B",x"CD",x"83",x"0B",x"3A",x"09",x"4C", -- 0x01B0 + x"E6",x"20",x"28",x"F6",x"3A",x"0B",x"4C",x"3D", -- 0x01B8 + x"32",x"0B",x"4C",x"3E",x"02",x"CD",x"A2",x"12", -- 0x01C0 + x"3E",x"00",x"32",x"2F",x"4C",x"3E",x"05",x"32", -- 0x01C8 + x"27",x"4C",x"21",x"0D",x"4C",x"11",x"0E",x"4C", -- 0x01D0 + x"01",x"05",x"00",x"36",x"30",x"EF",x"AF",x"12", -- 0x01D8 + x"3A",x"2F",x"4C",x"CD",x"1B",x"0D",x"AF",x"32", -- 0x01E0 + x"24",x"4C",x"CD",x"E2",x"26",x"AF",x"32",x"2B", -- 0x01E8 + x"4C",x"3A",x"30",x"4C",x"3C",x"32",x"30",x"4C", -- 0x01F0 + x"3E",x"01",x"32",x"0A",x"4C",x"CD",x"83",x"0B", -- 0x01F8 + x"CD",x"83",x"0B",x"CD",x"83",x"0B",x"AF",x"32", -- 0x0200 + x"0A",x"4C",x"CD",x"83",x"0B",x"3A",x"2E",x"4C", -- 0x0208 + x"3C",x"FE",x"06",x"38",x"0F",x"CD",x"3C",x"0B", -- 0x0210 + x"3A",x"39",x"4C",x"B7",x"20",x"05",x"3E",x"02", -- 0x0218 + x"32",x"2B",x"4C",x"AF",x"32",x"2E",x"4C",x"3A", -- 0x0220 + x"31",x"4C",x"32",x"33",x"4C",x"3A",x"32",x"4C", -- 0x0228 + x"32",x"34",x"4C",x"3A",x"04",x"4C",x"32",x"31", -- 0x0230 + x"4C",x"3A",x"05",x"4C",x"32",x"32",x"4C",x"ED", -- 0x0238 + x"5B",x"1D",x"4C",x"7A",x"C6",x"10",x"57",x"CD", -- 0x0240 + x"4B",x"0C",x"20",x"0E",x"ED",x"5B",x"1D",x"4C", -- 0x0248 + x"1C",x"7A",x"C6",x"10",x"57",x"CD",x"4B",x"0C", -- 0x0250 + x"28",x"41",x"3A",x"2C",x"4C",x"FE",x"00",x"28", -- 0x0258 + x"1E",x"3A",x"1F",x"4C",x"E6",x"02",x"28",x"08", -- 0x0260 + x"3A",x"31",x"4C",x"2F",x"E6",x"02",x"20",x"0D", -- 0x0268 + x"3A",x"31",x"4C",x"E6",x"FB",x"F6",x"02",x"32", -- 0x0270 + x"31",x"4C",x"32",x"26",x"4C",x"18",x"1C",x"3A", -- 0x0278 + x"1F",x"4C",x"E6",x"02",x"20",x"08",x"3A",x"31", -- 0x0280 + x"4C",x"2F",x"E6",x"04",x"20",x"0D",x"3A",x"31", -- 0x0288 + x"4C",x"E6",x"FD",x"F6",x"04",x"32",x"31",x"4C", -- 0x0290 + x"32",x"26",x"4C",x"3A",x"24",x"4C",x"B7",x"28", -- 0x0298 + x"06",x"3A",x"25",x"4C",x"32",x"31",x"4C",x"3A", -- 0x02A0 + x"31",x"4C",x"CB",x"4F",x"20",x"6F",x"F6",x"04", -- 0x02A8 + x"32",x"31",x"4C",x"32",x"26",x"4C",x"32",x"25", -- 0x02B0 + x"4C",x"3A",x"1F",x"4C",x"CB",x"4F",x"20",x"10", -- 0x02B8 + x"3A",x"31",x"4C",x"F6",x"02",x"32",x"31",x"4C", -- 0x02C0 + x"32",x"26",x"4C",x"32",x"25",x"4C",x"18",x"45", -- 0x02C8 + x"D6",x"04",x"E6",x"0F",x"32",x"1F",x"4C",x"FE", -- 0x02D0 + x"0E",x"20",x"3A",x"ED",x"5B",x"1D",x"4C",x"1D", -- 0x02D8 + x"CD",x"3A",x"0C",x"20",x"2B",x"ED",x"5B",x"1D", -- 0x02E0 + x"4C",x"1D",x"7A",x"C6",x"08",x"57",x"CD",x"3A", -- 0x02E8 + x"0C",x"20",x"1D",x"ED",x"5B",x"1D",x"4C",x"1D", -- 0x02F0 + x"7A",x"C6",x"0F",x"57",x"CD",x"3A",x"0C",x"20", -- 0x02F8 + x"0F",x"3A",x"1D",x"4C",x"3D",x"32",x"1D",x"4C", -- 0x0300 + x"FE",x"FF",x"20",x"11",x"3C",x"32",x"1D",x"4C", -- 0x0308 + x"3E",x"02",x"32",x"1F",x"4C",x"3A",x"1F",x"4C", -- 0x0310 + x"F6",x"02",x"32",x"1F",x"4C",x"3A",x"31",x"4C", -- 0x0318 + x"CB",x"57",x"20",x"70",x"F6",x"02",x"32",x"31", -- 0x0320 + x"4C",x"32",x"26",x"4C",x"32",x"25",x"4C",x"3A", -- 0x0328 + x"1F",x"4C",x"CB",x"4F",x"28",x"10",x"3A",x"31", -- 0x0330 + x"4C",x"F6",x"04",x"32",x"31",x"4C",x"32",x"26", -- 0x0338 + x"4C",x"32",x"25",x"4C",x"18",x"46",x"C6",x"04", -- 0x0340 + x"E6",x"0F",x"32",x"1F",x"4C",x"20",x"3D",x"ED", -- 0x0348 + x"5B",x"1D",x"4C",x"1C",x"1C",x"CD",x"3A",x"0C", -- 0x0350 + x"20",x"2D",x"ED",x"5B",x"1D",x"4C",x"1C",x"1C", -- 0x0358 + x"7A",x"C6",x"08",x"57",x"CD",x"3A",x"0C",x"20", -- 0x0360 + x"1E",x"ED",x"5B",x"1D",x"4C",x"1C",x"1C",x"7A", -- 0x0368 + x"C6",x"0F",x"57",x"CD",x"3A",x"0C",x"20",x"0F", -- 0x0370 + x"3A",x"1D",x"4C",x"3C",x"FE",x"1B",x"32",x"1D", -- 0x0378 + x"4C",x"20",x"11",x"3D",x"32",x"1D",x"4C",x"3E", -- 0x0380 + x"0C",x"32",x"1F",x"4C",x"3A",x"1F",x"4C",x"E6", -- 0x0388 + x"FD",x"32",x"1F",x"4C",x"3A",x"32",x"4C",x"CB", -- 0x0390 + x"57",x"20",x"25",x"3A",x"24",x"4C",x"B7",x"20", -- 0x0398 + x"1F",x"AF",x"32",x"23",x"4C",x"3E",x"01",x"32", -- 0x03A0 + x"24",x"4C",x"3E",x"FC",x"32",x"22",x"4C",x"3A", -- 0x03A8 + x"1E",x"4C",x"32",x"28",x"4C",x"3A",x"31",x"4C", -- 0x03B0 + x"32",x"25",x"4C",x"3E",x"01",x"32",x"2A",x"4C", -- 0x03B8 + x"3A",x"24",x"4C",x"B7",x"CA",x"BB",x"04",x"3C", -- 0x03C0 + x"32",x"24",x"4C",x"ED",x"5B",x"22",x"4C",x"3A", -- 0x03C8 + x"1E",x"4C",x"83",x"32",x"1E",x"4C",x"3A",x"24", -- 0x03D0 + x"4C",x"E6",x"01",x"28",x"0D",x"7B",x"CB",x"7F", -- 0x03D8 + x"20",x"04",x"FE",x"04",x"30",x"04",x"3C",x"32", -- 0x03E0 + x"22",x"4C",x"3A",x"22",x"4C",x"CB",x"7F",x"C2", -- 0x03E8 + x"53",x"04",x"FE",x"03",x"38",x"5D",x"ED",x"5B", -- 0x03F0 + x"1D",x"4C",x"7A",x"C6",x"10",x"57",x"CD",x"1B", -- 0x03F8 + x"0C",x"28",x"20",x"AF",x"32",x"22",x"4C",x"32", -- 0x0400 + x"24",x"4C",x"3A",x"1E",x"4C",x"E6",x"F8",x"32", -- 0x0408 + x"1E",x"4C",x"3A",x"28",x"4C",x"C6",x"18",x"5F", -- 0x0410 + x"3A",x"1E",x"4C",x"BB",x"38",x"05",x"3E",x"02", -- 0x0418 + x"32",x"2B",x"4C",x"ED",x"5B",x"1D",x"4C",x"1C", -- 0x0420 + x"7A",x"C6",x"10",x"57",x"CD",x"1B",x"0C",x"28", -- 0x0428 + x"20",x"AF",x"32",x"22",x"4C",x"32",x"24",x"4C", -- 0x0430 + x"3A",x"1E",x"4C",x"E6",x"F8",x"32",x"1E",x"4C", -- 0x0438 + x"3A",x"28",x"4C",x"C6",x"18",x"5F",x"3A",x"1E", -- 0x0440 + x"4C",x"BB",x"38",x"05",x"3E",x"02",x"32",x"2B", -- 0x0448 + x"4C",x"18",x"56",x"ED",x"5B",x"1D",x"4C",x"15", -- 0x0450 + x"CD",x"3A",x"0C",x"20",x"0B",x"ED",x"5B",x"1D", -- 0x0458 + x"4C",x"1C",x"15",x"CD",x"3A",x"0C",x"28",x"41", -- 0x0460 + x"3A",x"22",x"4C",x"CB",x"7F",x"28",x"3A",x"AF", -- 0x0468 + x"32",x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C", -- 0x0470 + x"32",x"26",x"4C",x"3A",x"1E",x"4C",x"3D",x"E6", -- 0x0478 + x"78",x"C6",x"08",x"32",x"1E",x"4C",x"ED",x"5B", -- 0x0480 + x"1D",x"4C",x"7A",x"C6",x"10",x"57",x"D5",x"CD", -- 0x0488 + x"1B",x"0C",x"D1",x"20",x"06",x"1C",x"CD",x"1B", -- 0x0490 + x"0C",x"28",x"0E",x"AF",x"32",x"24",x"4C",x"32", -- 0x0498 + x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C",x"18", -- 0x04A0 + x"43",x"3A",x"23",x"4C",x"3C",x"32",x"23",x"4C", -- 0x04A8 + x"FE",x"11",x"38",x"38",x"3E",x"FF",x"32",x"25", -- 0x04B0 + x"4C",x"18",x"31",x"3A",x"24",x"4C",x"B7",x"20", -- 0x04B8 + x"2B",x"ED",x"5B",x"1D",x"4C",x"7A",x"C6",x"10", -- 0x04C0 + x"57",x"D5",x"CD",x"1B",x"0C",x"D1",x"20",x"1C", -- 0x04C8 + x"1C",x"CD",x"1B",x"0C",x"20",x"16",x"AF",x"32", -- 0x04D0 + x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C",x"3E", -- 0x04D8 + x"01",x"32",x"24",x"4C",x"3A",x"1E",x"4C",x"C6", -- 0x04E0 + x"10",x"32",x"28",x"4C",x"ED",x"5B",x"1D",x"4C", -- 0x04E8 + x"CB",x"23",x"CB",x"23",x"CB",x"23",x"ED",x"4B", -- 0x04F0 + x"1F",x"4C",x"D5",x"79",x"E6",x"0C",x"1F",x"D1", -- 0x04F8 + x"83",x"32",x"29",x"4C",x"ED",x"5B",x"1D",x"4C", -- 0x0500 + x"CB",x"23",x"CB",x"23",x"CB",x"23",x"ED",x"4B", -- 0x0508 + x"1F",x"4C",x"CB",x"49",x"28",x"04",x"79",x"EE", -- 0x0510 + x"0C",x"4F",x"3E",x"00",x"CD",x"D5",x"0B",x"DD", -- 0x0518 + x"21",x"71",x"4C",x"06",x"01",x"3A",x"41",x"4C", -- 0x0520 + x"B7",x"28",x"21",x"4F",x"C5",x"DD",x"5E",x"01", -- 0x0528 + x"CB",x"23",x"CB",x"23",x"CB",x"23",x"DD",x"56", -- 0x0530 + x"02",x"DD",x"4E",x"00",x"78",x"06",x"01",x"CD", -- 0x0538 + x"D5",x"0B",x"C1",x"11",x"07",x"00",x"DD",x"19", -- 0x0540 + x"04",x"0D",x"20",x"E0",x"DD",x"21",x"8D",x"4C", -- 0x0548 + x"3A",x"42",x"4C",x"B7",x"28",x"21",x"4F",x"C5", -- 0x0550 + x"DD",x"5E",x"01",x"CB",x"23",x"CB",x"23",x"CB", -- 0x0558 + x"23",x"DD",x"56",x"02",x"DD",x"4E",x"00",x"78", -- 0x0560 + x"06",x"01",x"CD",x"D5",x"0B",x"C1",x"11",x"07", -- 0x0568 + x"00",x"DD",x"19",x"04",x"0D",x"20",x"E0",x"78", -- 0x0570 + x"FE",x"08",x"28",x"0C",x"11",x"F0",x"F0",x"DD", -- 0x0578 + x"4E",x"00",x"CD",x"D5",x"0B",x"04",x"18",x"EF", -- 0x0580 + x"3E",x"01",x"32",x"50",x"4C",x"3A",x"24",x"4C", -- 0x0588 + x"B7",x"20",x"43",x"ED",x"5B",x"1D",x"4C",x"7A", -- 0x0590 + x"C6",x"10",x"57",x"CD",x"0F",x"0C",x"FE",x"68", -- 0x0598 + x"38",x"12",x"FE",x"A0",x"30",x"0E",x"3C",x"77", -- 0x05A0 + x"E6",x"07",x"20",x"08",x"36",x"03",x"CB",x"D4", -- 0x05A8 + x"3A",x"36",x"4C",x"77",x"ED",x"5B",x"1D",x"4C", -- 0x05B0 + x"1C",x"7A",x"C6",x"10",x"57",x"CD",x"0F",x"0C", -- 0x05B8 + x"FE",x"68",x"38",x"12",x"FE",x"A0",x"30",x"0E", -- 0x05C0 + x"3C",x"77",x"E6",x"07",x"20",x"08",x"36",x"03", -- 0x05C8 + x"CB",x"D4",x"3A",x"36",x"4C",x"77",x"ED",x"5B", -- 0x05D0 + x"1D",x"4C",x"CD",x"7A",x"0A",x"1C",x"CD",x"7A", -- 0x05D8 + x"0A",x"7A",x"C6",x"08",x"57",x"CD",x"7A",x"0A", -- 0x05E0 + x"1D",x"CD",x"7A",x"0A",x"7A",x"C6",x"07",x"57", -- 0x05E8 + x"CD",x"7A",x"0A",x"1C",x"CD",x"7A",x"0A",x"DD", -- 0x05F0 + x"21",x"71",x"4C",x"3A",x"41",x"4C",x"B7",x"28", -- 0x05F8 + x"61",x"47",x"DD",x"7E",x"03",x"DD",x"86",x"06", -- 0x0600 + x"DD",x"77",x"03",x"1F",x"1F",x"1F",x"DD",x"77", -- 0x0608 + x"01",x"DD",x"7E",x"03",x"DD",x"BE",x"04",x"38", -- 0x0610 + x"05",x"DD",x"BE",x"05",x"38",x"08",x"DD",x"7E", -- 0x0618 + x"06",x"2F",x"3C",x"DD",x"77",x"06",x"DD",x"7E", -- 0x0620 + x"03",x"E6",x"06",x"87",x"4F",x"DD",x"7E",x"00", -- 0x0628 + x"E6",x"F0",x"B1",x"DD",x"77",x"00",x"DD",x"CB", -- 0x0630 + x"06",x"7E",x"28",x"08",x"DD",x"7E",x"00",x"EE", -- 0x0638 + x"0E",x"DD",x"77",x"00",x"DD",x"5E",x"03",x"DD", -- 0x0640 + x"56",x"02",x"2A",x"1D",x"4C",x"3A",x"29",x"4C", -- 0x0648 + x"6F",x"CD",x"FA",x"09",x"38",x"05",x"3E",x"02", -- 0x0650 + x"32",x"2B",x"4C",x"11",x"07",x"00",x"DD",x"19", -- 0x0658 + x"10",x"A0",x"DD",x"21",x"8D",x"4C",x"3A",x"42", -- 0x0660 + x"4C",x"B7",x"CA",x"2C",x"07",x"47",x"DD",x"7E", -- 0x0668 + x"06",x"B7",x"28",x"11",x"3A",x"2F",x"4C",x"FE", -- 0x0670 + x"07",x"28",x"04",x"FE",x"0B",x"20",x"06",x"11", -- 0x0678 + x"0E",x"0A",x"CD",x"26",x"0A",x"DD",x"7E",x"02", -- 0x0680 + x"DD",x"86",x"06",x"DD",x"77",x"02",x"DD",x"BE", -- 0x0688 + x"04",x"38",x"05",x"DD",x"BE",x"05",x"38",x"4A", -- 0x0690 + x"DD",x"7E",x"06",x"2F",x"3C",x"DD",x"77",x"06", -- 0x0698 + x"3A",x"2F",x"4C",x"FE",x"07",x"28",x"37",x"FE", -- 0x06A0 + x"0B",x"28",x"33",x"FE",x"0D",x"28",x"13",x"FE", -- 0x06A8 + x"04",x"28",x"02",x"18",x"2D",x"3A",x"3C",x"4C", -- 0x06B0 + x"B7",x"20",x"27",x"3E",x"00",x"DD",x"77",x"06", -- 0x06B8 + x"18",x"20",x"DD",x"7E",x"03",x"C6",x"40",x"DD", -- 0x06C0 + x"77",x"03",x"1F",x"1F",x"1F",x"DD",x"77",x"01", -- 0x06C8 + x"AF",x"DD",x"77",x"02",x"DD",x"7E",x"06",x"2F", -- 0x06D0 + x"3C",x"DD",x"77",x"06",x"18",x"04",x"AF",x"32", -- 0x06D8 + x"42",x"4C",x"3A",x"30",x"4C",x"E6",x"03",x"20", -- 0x06E0 + x"23",x"DD",x"7E",x"00",x"FE",x"20",x"38",x"1C", -- 0x06E8 + x"FE",x"A0",x"38",x"13",x"C6",x"04",x"DD",x"77", -- 0x06F0 + x"00",x"E6",x"0C",x"FE",x"00",x"20",x"0D",x"DD", -- 0x06F8 + x"7E",x"00",x"D6",x"10",x"DD",x"77",x"00",x"EE", -- 0x0700 + x"04",x"DD",x"77",x"00",x"DD",x"5E",x"03",x"DD", -- 0x0708 + x"56",x"02",x"2A",x"1D",x"4C",x"3A",x"29",x"4C", -- 0x0710 + x"6F",x"CD",x"FA",x"09",x"38",x"05",x"3E",x"02", -- 0x0718 + x"32",x"2B",x"4C",x"11",x"07",x"00",x"DD",x"19", -- 0x0720 + x"05",x"C2",x"6E",x"06",x"3A",x"07",x"4C",x"E6", -- 0x0728 + x"20",x"28",x"0A",x"3A",x"05",x"4C",x"E6",x"60", -- 0x0730 + x"20",x"03",x"C3",x"58",x"01",x"3A",x"2B",x"4C", -- 0x0738 + x"B7",x"CA",x"ED",x"01",x"FE",x"01",x"28",x"1C", -- 0x0740 + x"3E",x"40",x"32",x"4E",x"4C",x"3A",x"27",x"4C", -- 0x0748 + x"3D",x"32",x"27",x"4C",x"C2",x"E0",x"01",x"AF", -- 0x0750 + x"32",x"47",x"4C",x"32",x"24",x"4C",x"CD",x"19", -- 0x0758 + x"09",x"C3",x"58",x"01",x"AF",x"32",x"24",x"4C", -- 0x0760 + x"3A",x"39",x"4C",x"B7",x"28",x"11",x"32",x"4A", -- 0x0768 + x"4C",x"CD",x"83",x"0B",x"CD",x"3C",x"0B",x"11", -- 0x0770 + x"14",x"0A",x"CD",x"26",x"0A",x"18",x"E5",x"3A", -- 0x0778 + x"2F",x"4C",x"3C",x"32",x"2F",x"4C",x"FE",x"14", -- 0x0780 + x"DA",x"E0",x"01",x"AF",x"32",x"2F",x"4C",x"C3", -- 0x0788 + x"E0",x"01",x"3A",x"2F",x"4C",x"FE",x"12",x"C0", -- 0x0790 + x"11",x"14",x"00",x"CD",x"6D",x"0B",x"CB",x"D4", -- 0x0798 + x"11",x"14",x"00",x"7E",x"FE",x"18",x"20",x"34", -- 0x07A0 + x"7E",x"FE",x"18",x"20",x"24",x"36",x"0F",x"2C", -- 0x07A8 + x"14",x"18",x"F5",x"01",x"E1",x"FF",x"09",x"15", -- 0x07B0 + x"1D",x"7E",x"FE",x"18",x"28",x"EA",x"18",x"1C", -- 0x07B8 + x"7E",x"FE",x"18",x"20",x"EE",x"36",x"0F",x"01", -- 0x07C0 + x"20",x"00",x"09",x"1D",x"FA",x"DC",x"07",x"18", -- 0x07C8 + x"EF",x"01",x"1F",x"00",x"09",x"15",x"1D",x"7E", -- 0x07D0 + x"FE",x"18",x"28",x"E9",x"21",x"A4",x"47",x"36", -- 0x07D8 + x"0F",x"2E",x"84",x"36",x"0F",x"DD",x"21",x"71", -- 0x07E0 + x"4C",x"3A",x"41",x"4C",x"B7",x"28",x"31",x"47", -- 0x07E8 + x"DD",x"5E",x"03",x"DD",x"56",x"02",x"CB",x"3B", -- 0x07F0 + x"CB",x"3B",x"CB",x"3B",x"CB",x"3A",x"CB",x"3A", -- 0x07F8 + x"CB",x"3A",x"CD",x"6D",x"0B",x"CB",x"D4",x"CD", -- 0x0800 + x"0B",x"09",x"2C",x"CD",x"0B",x"09",x"11",x"E0", -- 0x0808 + x"FF",x"19",x"CD",x"0B",x"09",x"2D",x"CD",x"0B", -- 0x0810 + x"09",x"11",x"07",x"00",x"DD",x"19",x"10",x"D0", -- 0x0818 + x"DD",x"21",x"8D",x"4C",x"3A",x"42",x"4C",x"B7", -- 0x0820 + x"CA",x"5E",x"08",x"47",x"DD",x"5E",x"03",x"DD", -- 0x0828 + x"56",x"02",x"CB",x"3B",x"CB",x"3B",x"CB",x"3B", -- 0x0830 + x"CB",x"3A",x"CB",x"3A",x"CB",x"3A",x"CD",x"6D", -- 0x0838 + x"0B",x"CB",x"D4",x"CD",x"0B",x"09",x"2C",x"CD", -- 0x0840 + x"0B",x"09",x"11",x"E0",x"FF",x"19",x"CD",x"0B", -- 0x0848 + x"09",x"2D",x"CD",x"0B",x"09",x"11",x"07",x"00", -- 0x0850 + x"DD",x"19",x"05",x"C2",x"2C",x"08",x"3A",x"2F", -- 0x0858 + x"4C",x"FE",x"12",x"C0",x"11",x"14",x"00",x"CD", -- 0x0860 + x"6D",x"0B",x"CB",x"D4",x"11",x"14",x"00",x"01", -- 0x0868 + x"20",x"00",x"7E",x"FE",x"16",x"28",x"13",x"FE", -- 0x0870 + x"0F",x"20",x"16",x"36",x"18",x"2C",x"14",x"18", -- 0x0878 + x"F1",x"7E",x"FE",x"16",x"28",x"F5",x"FE",x"0F", -- 0x0880 + x"20",x"07",x"36",x"18",x"09",x"1D",x"F2",x"81", -- 0x0888 + x"08",x"DD",x"21",x"71",x"4C",x"3A",x"41",x"4C", -- 0x0890 + x"B7",x"28",x"31",x"47",x"DD",x"5E",x"03",x"DD", -- 0x0898 + x"56",x"02",x"CB",x"3B",x"CB",x"3B",x"CB",x"3B", -- 0x08A0 + x"CB",x"3A",x"CB",x"3A",x"CB",x"3A",x"CD",x"6D", -- 0x08A8 + x"0B",x"CB",x"D4",x"CD",x"12",x"09",x"2C",x"CD", -- 0x08B0 + x"12",x"09",x"11",x"E0",x"FF",x"19",x"CD",x"12", -- 0x08B8 + x"09",x"2D",x"CD",x"12",x"09",x"11",x"07",x"00", -- 0x08C0 + x"DD",x"19",x"10",x"D0",x"DD",x"21",x"8D",x"4C", -- 0x08C8 + x"3A",x"42",x"4C",x"B7",x"CA",x"0A",x"09",x"47", -- 0x08D0 + x"DD",x"5E",x"03",x"DD",x"56",x"02",x"CB",x"3B", -- 0x08D8 + x"CB",x"3B",x"CB",x"3B",x"CB",x"3A",x"CB",x"3A", -- 0x08E0 + x"CB",x"3A",x"CD",x"6D",x"0B",x"CB",x"D4",x"CD", -- 0x08E8 + x"12",x"09",x"2C",x"CD",x"12",x"09",x"11",x"E0", -- 0x08F0 + x"FF",x"19",x"CD",x"12",x"09",x"2D",x"CD",x"12", -- 0x08F8 + x"09",x"11",x"07",x"00",x"DD",x"19",x"05",x"C2", -- 0x0900 + x"D8",x"08",x"C9",x"7E",x"FE",x"0F",x"C0",x"36", -- 0x0908 + x"16",x"C9",x"7E",x"FE",x"18",x"C8",x"36",x"0F", -- 0x0910 + x"C9",x"AF",x"32",x"50",x"4C",x"CD",x"83",x"0B", -- 0x0918 + x"11",x"00",x"00",x"06",x"1C",x"D5",x"C5",x"CD", -- 0x0920 + x"6D",x"0B",x"06",x"10",x"AF",x"36",x"03",x"CB", -- 0x0928 + x"D4",x"77",x"CB",x"94",x"2C",x"10",x"F6",x"C1", -- 0x0930 + x"D1",x"1C",x"10",x"E9",x"CD",x"CB",x"0E",x"3E", -- 0x0938 + x"60",x"32",x"1E",x"4C",x"CD",x"83",x"0B",x"ED", -- 0x0940 + x"5F",x"11",x"00",x"00",x"06",x"1C",x"D5",x"C5", -- 0x0948 + x"F5",x"CD",x"6D",x"0B",x"F1",x"06",x"10",x"CB", -- 0x0950 + x"D4",x"77",x"2C",x"10",x"FA",x"C1",x"D1",x"1C", -- 0x0958 + x"10",x"EC",x"21",x"20",x"46",x"3A",x"1E",x"4C", -- 0x0960 + x"47",x"3E",x"60",x"90",x"1F",x"1F",x"1F",x"E6", -- 0x0968 + x"1F",x"3C",x"47",x"3E",x"01",x"77",x"2C",x"10", -- 0x0970 + x"FC",x"ED",x"4B",x"1E",x"4C",x"3E",x"61",x"91", -- 0x0978 + x"1F",x"1F",x"1F",x"E6",x"1F",x"57",x"1E",x"0C", -- 0x0980 + x"CD",x"6D",x"0B",x"36",x"17",x"CB",x"D4",x"36", -- 0x0988 + x"01",x"11",x"5D",x"70",x"01",x"14",x"01",x"3E", -- 0x0990 + x"02",x"CD",x"D5",x"0B",x"11",x"60",x"60",x"01", -- 0x0998 + x"00",x"01",x"3E",x"01",x"CD",x"D5",x"0B",x"11", -- 0x09A0 + x"5E",x"00",x"ED",x"4B",x"1E",x"4C",x"3E",x"61", -- 0x09A8 + x"91",x"57",x"01",x"18",x"01",x"3E",x"00",x"CD", -- 0x09B0 + x"D5",x"0B",x"3A",x"1E",x"4C",x"3D",x"32",x"1E", -- 0x09B8 + x"4C",x"F5",x"CB",x"3F",x"CB",x"3F",x"32",x"4A", -- 0x09C0 + x"4C",x"F1",x"C2",x"44",x"09",x"11",x"00",x"00", -- 0x09C8 + x"06",x"1C",x"AF",x"D5",x"C5",x"F5",x"CD",x"6D", -- 0x09D0 + x"0B",x"F1",x"06",x"10",x"CB",x"D4",x"77",x"2C", -- 0x09D8 + x"10",x"FA",x"C1",x"D1",x"1C",x"10",x"EC",x"21", -- 0x09E0 + x"20",x"46",x"06",x"0C",x"3E",x"01",x"77",x"2C", -- 0x09E8 + x"10",x"FC",x"06",x"FA",x"CD",x"83",x"0B",x"10", -- 0x09F0 + x"FB",x"C9",x"7D",x"C6",x"06",x"BB",x"D8",x"7B", -- 0x09F8 + x"C6",x"06",x"BD",x"D8",x"7C",x"C6",x"0F",x"BA", -- 0x0A00 + x"D8",x"7A",x"C6",x"0F",x"BC",x"C9",x"00",x"00", -- 0x0A08 + x"01",x"00",x"00",x"00",x"08",x"00",x"00",x"00", -- 0x0A10 + x"00",x"00",x"00",x"00",x"01",x"00",x"00",x"00", -- 0x0A18 + x"00",x"05",x"02",x"00",x"00",x"00",x"E5",x"C5", -- 0x0A20 + x"21",x"12",x"4C",x"01",x"00",x"06",x"1A",x"86", -- 0x0A28 + x"81",x"77",x"0E",x"00",x"FE",x"3A",x"38",x"04", -- 0x0A30 + x"D6",x"0A",x"77",x"0C",x"2B",x"13",x"10",x"EE", -- 0x0A38 + x"21",x"0D",x"4C",x"11",x"14",x"4C",x"06",x"06", -- 0x0A40 + x"1A",x"BE",x"28",x"0E",x"30",x"10",x"21",x"0D", -- 0x0A48 + x"4C",x"11",x"14",x"4C",x"01",x"06",x"00",x"EF", -- 0x0A50 + x"18",x"04",x"23",x"13",x"10",x"EA",x"CD",x"AE", -- 0x0A58 + x"0E",x"C1",x"E1",x"C9",x"CD",x"83",x"0B",x"3A", -- 0x0A60 + x"40",x"50",x"E6",x"20",x"20",x"F6",x"C9",x"CD", -- 0x0A68 + x"83",x"0B",x"3A",x"40",x"50",x"E6",x"20",x"28", -- 0x0A70 + x"F6",x"C9",x"D5",x"CD",x"0F",x"0C",x"D1",x"FE", -- 0x0A78 + x"18",x"D8",x"FE",x"20",x"DA",x"10",x"0B",x"FE", -- 0x0A80 + x"30",x"D8",x"FE",x"40",x"DA",x"10",x"0B",x"FE", -- 0x0A88 + x"FE",x"D2",x"16",x"0B",x"FE",x"DE",x"38",x"05", -- 0x0A90 + x"FE",x"E0",x"DA",x"16",x"0B",x"FE",x"44",x"28", -- 0x0A98 + x"42",x"FE",x"45",x"28",x"3E",x"FE",x"46",x"C0", -- 0x0AA0 + x"36",x"47",x"7B",x"FE",x"11",x"38",x"23",x"3A", -- 0x0AA8 + x"8D",x"4C",x"C6",x"08",x"32",x"8D",x"4C",x"3E", -- 0x0AB0 + x"04",x"32",x"93",x"4C",x"E5",x"D5",x"21",x"E2", -- 0x0AB8 + x"41",x"AF",x"77",x"11",x"E0",x"FF",x"19",x"77", -- 0x0AC0 + x"CB",x"D4",x"77",x"AF",x"ED",x"52",x"77",x"D1", -- 0x0AC8 + x"E1",x"C9",x"E5",x"D5",x"21",x"AB",x"41",x"AF", -- 0x0AD0 + x"77",x"2C",x"77",x"CB",x"D4",x"77",x"2D",x"77", -- 0x0AD8 + x"D1",x"E1",x"C9",x"36",x"03",x"CB",x"D4",x"3A", -- 0x0AE0 + x"36",x"4C",x"77",x"3A",x"3C",x"4C",x"3D",x"32", -- 0x0AE8 + x"3C",x"4C",x"D5",x"11",x"1A",x"0A",x"CD",x"26", -- 0x0AF0 + x"0A",x"D1",x"3E",x"02",x"32",x"4F",x"4C",x"3A", -- 0x0AF8 + x"2F",x"4C",x"FE",x"04",x"C0",x"3A",x"3C",x"4C", -- 0x0B00 + x"B7",x"C0",x"3E",x"01",x"32",x"93",x"4C",x"C9", -- 0x0B08 + x"3E",x"02",x"32",x"2B",x"4C",x"C9",x"3A",x"3C", -- 0x0B10 + x"4C",x"B7",x"C0",x"D5",x"3A",x"29",x"4C",x"C6", -- 0x0B18 + x"05",x"1F",x"1F",x"1F",x"E6",x"1F",x"5F",x"3A", -- 0x0B20 + x"1E",x"4C",x"C6",x"08",x"57",x"CD",x"0F",x"0C", -- 0x0B28 + x"D1",x"E6",x"DE",x"FE",x"DE",x"C0",x"3E",x"01", -- 0x0B30 + x"32",x"2B",x"4C",x"C9",x"3A",x"39",x"4C",x"B7", -- 0x0B38 + x"28",x"25",x"3D",x"32",x"39",x"4C",x"1F",x"1F", -- 0x0B40 + x"1F",x"E6",x"1F",x"C6",x"04",x"5F",x"16",x"11", -- 0x0B48 + x"CD",x"6D",x"0B",x"3A",x"39",x"4C",x"E6",x"07", -- 0x0B50 + x"C6",x"60",x"77",x"E6",x"07",x"FE",x"07",x"C0", -- 0x0B58 + x"11",x"E0",x"FF",x"19",x"36",x"A0",x"C9",x"21", -- 0x0B60 + x"31",x"43",x"36",x"A0",x"C9",x"7A",x"C6",x"A0", -- 0x0B68 + x"6F",x"26",x"43",x"7B",x"11",x"E0",x"FF",x"B7", -- 0x0B70 + x"C8",x"1F",x"30",x"01",x"19",x"EB",x"29",x"EB", -- 0x0B78 + x"C3",x"77",x"0B",x"E5",x"2A",x"00",x"4C",x"AF", -- 0x0B80 + x"32",x"C0",x"50",x"3A",x"00",x"4C",x"BD",x"28", -- 0x0B88 + x"F6",x"E1",x"C9",x"7E",x"23",x"B7",x"C8",x"C6", -- 0x0B90 + x"80",x"12",x"CB",x"D2",x"79",x"12",x"7B",x"D6", -- 0x0B98 + x"20",x"5F",x"CB",x"92",x"7A",x"DE",x"00",x"57", -- 0x0BA0 + x"C3",x"93",x"0B",x"7C",x"CD",x"B0",x"0B",x"7D", -- 0x0BA8 + x"F5",x"1F",x"1F",x"1F",x"1F",x"CD",x"B9",x"0B", -- 0x0BB0 + x"F1",x"E6",x"0F",x"FE",x"0A",x"38",x"02",x"C6", -- 0x0BB8 + x"07",x"C6",x"B0",x"E5",x"D5",x"F5",x"CD",x"6D", -- 0x0BC0 + x"0B",x"F1",x"77",x"CB",x"D4",x"36",x"12",x"CB", -- 0x0BC8 + x"94",x"D1",x"1C",x"E1",x"C9",x"F5",x"3E",x"F0", -- 0x0BD0 + x"BA",x"20",x"03",x"BB",x"28",x"2C",x"F1",x"3C", -- 0x0BD8 + x"D5",x"ED",x"5B",x"1C",x"4C",x"BB",x"38",x"03", -- 0x0BE0 + x"32",x"1C",x"4C",x"E6",x"07",x"87",x"5F",x"16", -- 0x0BE8 + x"00",x"21",x"51",x"4C",x"19",x"D1",x"71",x"23", -- 0x0BF0 + x"70",x"23",x"D5",x"11",x"0E",x"00",x"19",x"D1", -- 0x0BF8 + x"3E",x"EE",x"93",x"77",x"23",x"3E",x"00",x"92", -- 0x0C00 + x"77",x"C9",x"F1",x"3C",x"D5",x"18",x"DC",x"7A", -- 0x0C08 + x"1F",x"1F",x"1F",x"E6",x"1F",x"57",x"CD",x"6D", -- 0x0C10 + x"0B",x"7E",x"C9",x"CD",x"0F",x"0C",x"FE",x"05", -- 0x0C18 + x"38",x"14",x"FE",x"18",x"38",x"12",x"FE",x"20", -- 0x0C20 + x"38",x"0C",x"FE",x"30",x"38",x"0A",x"FE",x"48", -- 0x0C28 + x"38",x"04",x"FE",x"A0",x"38",x"02",x"AF",x"C9", -- 0x0C30 + x"B7",x"C9",x"CD",x"0F",x"0C",x"FE",x"20",x"38", -- 0x0C38 + x"04",x"FE",x"30",x"38",x"02",x"AF",x"C9",x"3E", -- 0x0C40 + x"01",x"B7",x"C9",x"CD",x"0F",x"0C",x"FE",x"48", -- 0x0C48 + x"38",x"04",x"FE",x"60",x"38",x"02",x"AF",x"C9", -- 0x0C50 + x"3E",x"01",x"B7",x"C9",x"32",x"36",x"4C",x"F5", -- 0x0C58 + x"AF",x"32",x"50",x"4C",x"CD",x"83",x"0B",x"F1", -- 0x0C60 + x"F3",x"E5",x"D5",x"C5",x"F5",x"21",x"00",x"40", -- 0x0C68 + x"11",x"01",x"40",x"01",x"00",x"04",x"36",x"03", -- 0x0C70 + x"ED",x"B0",x"01",x"40",x"00",x"36",x"00",x"ED", -- 0x0C78 + x"B0",x"01",x"80",x"03",x"77",x"ED",x"B0",x"36", -- 0x0C80 + x"00",x"01",x"3F",x"00",x"ED",x"B0",x"FB",x"CD", -- 0x0C88 + x"83",x"0B",x"F3",x"11",x"00",x"10",x"06",x"10", -- 0x0C90 + x"D5",x"C5",x"CD",x"6D",x"0B",x"11",x"E0",x"FF", -- 0x0C98 + x"CB",x"D4",x"06",x"20",x"36",x"00",x"19",x"10", -- 0x0CA0 + x"FB",x"C1",x"D1",x"14",x"10",x"EA",x"CD",x"69", -- 0x0CA8 + x"12",x"F1",x"C1",x"D1",x"E1",x"FB",x"C9",x"3A", -- 0x0CB0 + x"3C",x"4C",x"B7",x"C0",x"ED",x"5F",x"21",x"D8", -- 0x0CB8 + x"0C",x"E6",x"03",x"5F",x"16",x"00",x"19",x"7E", -- 0x0CC0 + x"2A",x"3F",x"4C",x"CB",x"D4",x"77",x"2C",x"77", -- 0x0CC8 + x"11",x"E0",x"FF",x"19",x"77",x"2D",x"77",x"C9", -- 0x0CD0 + x"09",x"11",x"14",x"17",x"C9",x"DD",x"2A",x"37", -- 0x0CD8 + x"4C",x"DD",x"7E",x"02",x"B7",x"C8",x"47",x"DD", -- 0x0CE0 + x"5E",x"00",x"DD",x"56",x"01",x"CD",x"6D",x"0B", -- 0x0CE8 + x"DD",x"7E",x"05",x"32",x"2C",x"4C",x"FE",x"00", -- 0x0CF0 + x"3A",x"30",x"4C",x"28",x"01",x"2F",x"E6",x"07", -- 0x0CF8 + x"DD",x"86",x"03",x"DD",x"4E",x"04",x"C3",x"09", -- 0x0D00 + x"0D",x"11",x"E0",x"FF",x"18",x"03",x"11",x"01", -- 0x0D08 + x"00",x"77",x"CB",x"D4",x"71",x"CB",x"94",x"19", -- 0x0D10 + x"10",x"F7",x"C9",x"6F",x"26",x"00",x"29",x"11", -- 0x0D18 + x"84",x"17",x"19",x"5E",x"23",x"56",x"D5",x"DD", -- 0x0D20 + x"E1",x"DD",x"7E",x"00",x"DD",x"23",x"CD",x"5C", -- 0x0D28 + x"0C",x"DD",x"5E",x"00",x"DD",x"56",x"01",x"CD", -- 0x0D30 + x"6D",x"0B",x"DD",x"7E",x"02",x"B7",x"28",x"1C", -- 0x0D38 + x"47",x"CB",x"B8",x"E6",x"80",x"DD",x"7E",x"03", -- 0x0D40 + x"DD",x"4E",x"04",x"11",x"05",x"00",x"DD",x"19", -- 0x0D48 + x"28",x"05",x"CD",x"0E",x"0D",x"18",x"DA",x"CD", -- 0x0D50 + x"09",x"0D",x"18",x"D5",x"22",x"3F",x"4C",x"36", -- 0x0D58 + x"DE",x"2C",x"36",x"FE",x"CB",x"D4",x"36",x"09", -- 0x0D60 + x"2D",x"36",x"09",x"CB",x"94",x"11",x"E0",x"FF", -- 0x0D68 + x"19",x"36",x"DF",x"2C",x"36",x"FF",x"CB",x"D4", -- 0x0D70 + x"36",x"09",x"2D",x"36",x"09",x"DD",x"7E",x"03", -- 0x0D78 + x"DD",x"4E",x"04",x"DD",x"46",x"05",x"11",x"06", -- 0x0D80 + x"00",x"DD",x"19",x"B7",x"28",x"16",x"F5",x"DD", -- 0x0D88 + x"5E",x"00",x"DD",x"56",x"01",x"DD",x"23",x"DD", -- 0x0D90 + x"23",x"CD",x"6D",x"0B",x"71",x"CB",x"D4",x"70", -- 0x0D98 + x"F1",x"3D",x"20",x"EA",x"DD",x"7E",x"00",x"DD", -- 0x0DA0 + x"4E",x"01",x"DD",x"46",x"02",x"11",x"03",x"00", -- 0x0DA8 + x"DD",x"19",x"B7",x"28",x"16",x"F5",x"DD",x"5E", -- 0x0DB0 + x"00",x"DD",x"56",x"01",x"DD",x"23",x"DD",x"23", -- 0x0DB8 + x"CD",x"6D",x"0B",x"71",x"CB",x"D4",x"70",x"F1", -- 0x0DC0 + x"3D",x"20",x"EA",x"21",x"B0",x"43",x"11",x"E0", -- 0x0DC8 + x"FF",x"06",x"1C",x"36",x"A0",x"CB",x"D4",x"36", -- 0x0DD0 + x"09",x"CB",x"94",x"19",x"10",x"F5",x"DD",x"5E", -- 0x0DD8 + x"00",x"DD",x"23",x"16",x"10",x"CD",x"6D",x"0B", -- 0x0DE0 + x"EB",x"DD",x"E5",x"E1",x"0E",x"09",x"CD",x"93", -- 0x0DE8 + x"0B",x"22",x"37",x"4C",x"11",x"06",x"00",x"19", -- 0x0DF0 + x"7E",x"32",x"1D",x"4C",x"FE",x"10",x"07",x"17", -- 0x0DF8 + x"E6",x"02",x"32",x"1F",x"4C",x"23",x"7E",x"87", -- 0x0E00 + x"87",x"87",x"32",x"1E",x"4C",x"23",x"3E",x"01", -- 0x0E08 + x"32",x"20",x"4C",x"AF",x"32",x"24",x"4C",x"32", -- 0x0E10 + x"22",x"4C",x"3E",x"FF",x"32",x"25",x"4C",x"22", -- 0x0E18 + x"3D",x"4C",x"7E",x"47",x"32",x"3C",x"4C",x"23", -- 0x0E20 + x"7E",x"32",x"3A",x"4C",x"23",x"7E",x"32",x"3B", -- 0x0E28 + x"4C",x"23",x"5E",x"23",x"56",x"23",x"E5",x"CD", -- 0x0E30 + x"6D",x"0B",x"3A",x"3A",x"4C",x"77",x"CB",x"D4", -- 0x0E38 + x"3A",x"3B",x"4C",x"77",x"E1",x"10",x"EB",x"7E", -- 0x0E40 + x"23",x"47",x"1F",x"1F",x"1F",x"1F",x"E6",x"07", -- 0x0E48 + x"32",x"41",x"4C",x"78",x"E6",x"07",x"32",x"42", -- 0x0E50 + x"4C",x"3A",x"41",x"4C",x"06",x"00",x"4F",x"87", -- 0x0E58 + x"81",x"87",x"81",x"4F",x"28",x"04",x"11",x"71", -- 0x0E60 + x"4C",x"EF",x"3A",x"42",x"4C",x"06",x"00",x"4F", -- 0x0E68 + x"87",x"81",x"87",x"81",x"4F",x"28",x"04",x"11", -- 0x0E70 + x"8D",x"4C",x"EF",x"21",x"1F",x"28",x"11",x"B1", -- 0x0E78 + x"43",x"0E",x"01",x"CD",x"93",x"0B",x"0E",x"05", -- 0x0E80 + x"CD",x"93",x"0B",x"3E",x"BF",x"32",x"39",x"4C", -- 0x0E88 + x"11",x"00",x"14",x"CD",x"6D",x"0B",x"3A",x"27", -- 0x0E90 + x"4C",x"47",x"11",x"C0",x"FF",x"36",x"DB",x"CB", -- 0x0E98 + x"D4",x"36",x"01",x"2C",x"36",x"01",x"CB",x"94", -- 0x0EA0 + x"36",x"FB",x"2D",x"19",x"10",x"EF",x"21",x"3D", -- 0x0EA8 + x"28",x"11",x"B3",x"43",x"0E",x"19",x"CD",x"93", -- 0x0EB0 + x"0B",x"21",x"14",x"4C",x"CD",x"93",x"0B",x"21", -- 0x0EB8 + x"46",x"28",x"CD",x"93",x"0B",x"21",x"0D",x"4C", -- 0x0EC0 + x"C3",x"93",x"0B",x"06",x"08",x"11",x"F0",x"F0", -- 0x0EC8 + x"3E",x"08",x"90",x"CD",x"D5",x"0B",x"10",x"F5", -- 0x0ED0 + x"C9",x"E5",x"CD",x"6D",x"0B",x"EB",x"E1",x"E5", -- 0x0ED8 + x"D5",x"C5",x"7D",x"2C",x"12",x"CB",x"D2",x"7C", -- 0x0EE0 + x"12",x"CB",x"92",x"3E",x"E0",x"83",x"5F",x"7A", -- 0x0EE8 + x"CE",x"FF",x"57",x"0D",x"20",x"EC",x"C1",x"D1", -- 0x0EF0 + x"E1",x"13",x"7D",x"C6",x"20",x"6F",x"10",x"DF", -- 0x0EF8 + x"C9",x"E5",x"CD",x"6D",x"0B",x"EB",x"E1",x"E5", -- 0x0F00 + x"D5",x"C5",x"7D",x"12",x"CB",x"D2",x"7C",x"12", -- 0x0F08 + x"CB",x"92",x"3E",x"E0",x"83",x"5F",x"7A",x"CE", -- 0x0F10 + x"FF",x"57",x"0D",x"20",x"ED",x"C1",x"D1",x"E1", -- 0x0F18 + x"13",x"10",x"E4",x"C9",x"AF",x"CD",x"5C",x"0C", -- 0x0F20 + x"21",x"50",x"0F",x"16",x"04",x"0E",x"17",x"1E", -- 0x0F28 + x"00",x"06",x"1B",x"7E",x"23",x"E6",x"01",x"28", -- 0x0F30 + x"0D",x"E5",x"D5",x"CD",x"6D",x"0B",x"36",x"A0", -- 0x0F38 + x"CB",x"D4",x"36",x"09",x"D1",x"E1",x"1C",x"10", -- 0x0F40 + x"EA",x"14",x"0D",x"20",x"E2",x"C3",x"CB",x"0E", -- 0x0F48 + x"30",x"30",x"30",x"30",x"30",x"31",x"31",x"31", -- 0x0F50 + x"31",x"30",x"30",x"30",x"31",x"31",x"31",x"30", -- 0x0F58 + x"30",x"30",x"31",x"31",x"31",x"30",x"30",x"30", -- 0x0F60 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0F68 + x"31",x"30",x"30",x"30",x"31",x"30",x"31",x"30", -- 0x0F70 + x"30",x"30",x"31",x"30",x"31",x"30",x"30",x"30", -- 0x0F78 + x"31",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0F80 + x"30",x"30",x"30",x"31",x"31",x"31",x"31",x"30", -- 0x0F88 + x"30",x"31",x"31",x"31",x"31",x"31",x"30",x"31", -- 0x0F90 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0F98 + x"30",x"30",x"30",x"30",x"30",x"30",x"31",x"30", -- 0x0FA0 + x"30",x"30",x"30",x"30",x"31",x"30",x"30",x"30", -- 0x0FA8 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x0FB0 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FB8 + x"30",x"31",x"30",x"30",x"30",x"30",x"30",x"31", -- 0x0FC0 + x"30",x"30",x"30",x"31",x"30",x"30",x"31",x"31", -- 0x0FC8 + x"31",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FD0 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FD8 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FE0 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0FE8 + x"30",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x0FF0 + x"30",x"31",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x0FF8 + x"30",x"30",x"31",x"30",x"31",x"31",x"31",x"30", -- 0x1000 + x"30",x"31",x"31",x"31",x"30",x"31",x"31",x"30", -- 0x1008 + x"31",x"31",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1010 + x"30",x"31",x"31",x"30",x"30",x"31",x"30",x"30", -- 0x1018 + x"31",x"30",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1020 + x"31",x"30",x"31",x"30",x"31",x"30",x"31",x"31", -- 0x1028 + x"31",x"31",x"31",x"30",x"31",x"30",x"31",x"30", -- 0x1030 + x"31",x"30",x"30",x"31",x"30",x"30",x"31",x"30", -- 0x1038 + x"30",x"30",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1040 + x"30",x"31",x"30",x"30",x"30",x"31",x"30",x"31", -- 0x1048 + x"30",x"30",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x1050 + x"30",x"31",x"30",x"30",x"30",x"31",x"31",x"30", -- 0x1058 + x"30",x"30",x"31",x"30",x"31",x"30",x"30",x"30", -- 0x1060 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x1068 + x"31",x"31",x"31",x"30",x"30",x"31",x"31",x"31", -- 0x1070 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1078 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1080 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1088 + x"30",x"30",x"30",x"30",x"31",x"30",x"30",x"30", -- 0x1090 + x"31",x"30",x"31",x"31",x"31",x"30",x"31",x"30", -- 0x1098 + x"30",x"30",x"31",x"30",x"31",x"31",x"31",x"31", -- 0x10A0 + x"31",x"30",x"31",x"31",x"31",x"31",x"30",x"31", -- 0x10A8 + x"31",x"30",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x10B0 + x"30",x"31",x"31",x"30",x"30",x"31",x"30",x"31", -- 0x10B8 + x"30",x"30",x"30",x"30",x"30",x"31",x"30",x"30", -- 0x10C0 + x"30",x"31",x"31",x"30",x"31",x"30",x"31",x"30", -- 0x10C8 + x"30",x"31",x"30",x"30",x"31",x"30",x"31",x"30", -- 0x10D0 + x"31",x"30",x"31",x"31",x"30",x"30",x"30",x"30", -- 0x10D8 + x"31",x"31",x"31",x"31",x"30",x"31",x"30",x"30", -- 0x10E0 + x"30",x"31",x"30",x"30",x"31",x"30",x"30",x"31", -- 0x10E8 + x"30",x"30",x"31",x"31",x"30",x"31",x"30",x"30", -- 0x10F0 + x"30",x"30",x"30",x"31",x"30",x"30",x"31",x"30", -- 0x10F8 + x"31",x"30",x"30",x"30",x"31",x"30",x"31",x"31", -- 0x1100 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x1108 + x"31",x"31",x"31",x"31",x"31",x"30",x"31",x"30", -- 0x1110 + x"30",x"30",x"31",x"30",x"30",x"30",x"30",x"30", -- 0x1118 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1120 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1128 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1130 + x"30",x"30",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x1138 + x"30",x"30",x"31",x"31",x"31",x"30",x"30",x"31", -- 0x1140 + x"30",x"30",x"30",x"31",x"30",x"30",x"30",x"30", -- 0x1148 + x"30",x"30",x"30",x"30",x"30",x"30",x"31",x"31", -- 0x1150 + x"30",x"31",x"31",x"30",x"31",x"30",x"30",x"30", -- 0x1158 + x"31",x"30",x"31",x"31",x"30",x"30",x"31",x"30", -- 0x1160 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1168 + x"30",x"31",x"30",x"31",x"30",x"31",x"30",x"31", -- 0x1170 + x"31",x"31",x"31",x"31",x"30",x"31",x"30",x"31", -- 0x1178 + x"30",x"31",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x1180 + x"30",x"30",x"30",x"30",x"31",x"30",x"30",x"30", -- 0x1188 + x"31",x"30",x"31",x"30",x"30",x"30",x"31",x"30", -- 0x1190 + x"31",x"30",x"30",x"31",x"31",x"30",x"30",x"30", -- 0x1198 + x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"31", -- 0x11A0 + x"30",x"30",x"30",x"31",x"30",x"31",x"30",x"30", -- 0x11A8 + x"30",x"31",x"30",x"31",x"30",x"30",x"30",x"31", -- 0x11B0 + x"30",x"30",x"30",x"30",x"30",x"20",x"20",x"20", -- 0x11B8 + x"20",x"50",x"72",x"65",x"73",x"73",x"20",x"53", -- 0x11C0 + x"74",x"61",x"72",x"74",x"20",x"54",x"6F",x"20", -- 0x11C8 + x"50",x"6C",x"61",x"79",x"20",x"20",x"20",x"20", -- 0x11D0 + x"00",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x11D8 + x"20",x"49",x"6E",x"73",x"65",x"72",x"74",x"20", -- 0x11E0 + x"43",x"6F",x"69",x"6E",x"20",x"20",x"20",x"20", -- 0x11E8 + x"20",x"20",x"20",x"20",x"00",x"1E",x"00",x"D6", -- 0x11F0 + x"0A",x"38",x"03",x"1C",x"18",x"F9",x"C6",x"0A", -- 0x11F8 + x"C9",x"3A",x"0A",x"4C",x"B7",x"C0",x"3A",x"00", -- 0x1200 + x"50",x"32",x"04",x"4C",x"2F",x"5F",x"3A",x"06", -- 0x1208 + x"4C",x"57",x"2F",x"A3",x"32",x"07",x"4C",x"7B", -- 0x1210 + x"32",x"06",x"4C",x"3A",x"40",x"50",x"32",x"05", -- 0x1218 + x"4C",x"2F",x"5F",x"3A",x"08",x"4C",x"57",x"2F", -- 0x1220 + x"A3",x"32",x"09",x"4C",x"7B",x"32",x"08",x"4C", -- 0x1228 + x"3A",x"09",x"4C",x"E6",x"01",x"28",x"08",x"3A", -- 0x1230 + x"4C",x"4C",x"EE",x"0F",x"32",x"4C",x"4C",x"3A", -- 0x1238 + x"09",x"4C",x"E6",x"08",x"28",x"08",x"3A",x"4D", -- 0x1240 + x"4C",x"EE",x"0F",x"32",x"4D",x"4C",x"3A",x"07", -- 0x1248 + x"4C",x"E6",x"20",x"28",x"13",x"3A",x"0B",x"4C", -- 0x1250 + x"FE",x"63",x"28",x"0C",x"3C",x"32",x"0B",x"4C", -- 0x1258 + x"CD",x"69",x"12",x"3E",x"01",x"32",x"0C",x"4C", -- 0x1260 + x"C9",x"11",x"99",x"12",x"21",x"FD",x"43",x"1A", -- 0x1268 + x"13",x"B7",x"28",x"0C",x"C6",x"80",x"77",x"CB", -- 0x1270 + x"D4",x"36",x"19",x"CB",x"94",x"2D",x"18",x"EF", -- 0x1278 + x"3A",x"0B",x"4C",x"CD",x"F5",x"11",x"57",x"7B", -- 0x1280 + x"C6",x"B0",x"77",x"CB",x"D4",x"36",x"19",x"2D", -- 0x1288 + x"36",x"19",x"CB",x"94",x"7A",x"C6",x"B0",x"77", -- 0x1290 + x"C9",x"43",x"72",x"65",x"64",x"69",x"74",x"73", -- 0x1298 + x"20",x"00",x"32",x"47",x"4C",x"AF",x"32",x"46", -- 0x12A0 + x"4C",x"3E",x"01",x"32",x"4B",x"4C",x"C9",x"CD", -- 0x12A8 + x"01",x"12",x"3A",x"47",x"4C",x"B7",x"CA",x"A1", -- 0x12B0 + x"13",x"3A",x"4B",x"4C",x"D6",x"04",x"32",x"4B", -- 0x12B8 + x"4C",x"D2",x"10",x"13",x"3A",x"47",x"4C",x"87", -- 0x12C0 + x"5F",x"16",x"00",x"21",x"4F",x"14",x"19",x"5E", -- 0x12C8 + x"23",x"56",x"EB",x"3A",x"46",x"4C",x"5F",x"3C", -- 0x12D0 + x"32",x"46",x"4C",x"16",x"00",x"19",x"19",x"19", -- 0x12D8 + x"7E",x"FE",x"FF",x"CA",x"A1",x"13",x"B7",x"20", -- 0x12E0 + x"14",x"3C",x"32",x"46",x"4C",x"3A",x"47",x"4C", -- 0x12E8 + x"87",x"5F",x"16",x"00",x"21",x"4F",x"14",x"19", -- 0x12F0 + x"5E",x"23",x"56",x"EB",x"7E",x"32",x"4B",x"4C", -- 0x12F8 + x"23",x"7E",x"CD",x"FD",x"13",x"32",x"48",x"4C", -- 0x1300 + x"23",x"7E",x"CD",x"FD",x"13",x"32",x"49",x"4C", -- 0x1308 + x"3A",x"24",x"4C",x"B7",x"28",x"16",x"3A",x"2A", -- 0x1310 + x"4C",x"3C",x"32",x"2A",x"4C",x"1F",x"1F",x"E6", -- 0x1318 + x"3F",x"5F",x"16",x"00",x"21",x"AE",x"13",x"19", -- 0x1320 + x"7E",x"32",x"4A",x"4C",x"3A",x"4F",x"4C",x"B7", -- 0x1328 + x"28",x"10",x"C6",x"02",x"32",x"4F",x"4C",x"32", -- 0x1330 + x"4A",x"4C",x"FE",x"40",x"38",x"04",x"AF",x"32", -- 0x1338 + x"4F",x"4C",x"3A",x"0C",x"4C",x"B7",x"28",x"10", -- 0x1340 + x"C6",x"01",x"32",x"0C",x"4C",x"32",x"4A",x"4C", -- 0x1348 + x"FE",x"20",x"38",x"04",x"AF",x"32",x"0C",x"4C", -- 0x1350 + x"3A",x"4E",x"4C",x"B7",x"28",x"08",x"D6",x"04", -- 0x1358 + x"32",x"4E",x"4C",x"32",x"4A",x"4C",x"DD",x"21", -- 0x1360 + x"45",x"50",x"DD",x"36",x"00",x"01",x"ED",x"4B", -- 0x1368 + x"4C",x"4C",x"3A",x"48",x"4C",x"CD",x"16",x"14", -- 0x1370 + x"DD",x"21",x"4A",x"50",x"DD",x"36",x"00",x"03", -- 0x1378 + x"ED",x"4B",x"4C",x"4C",x"3A",x"49",x"4C",x"CD", -- 0x1380 + x"16",x"14",x"DD",x"21",x"4F",x"50",x"DD",x"36", -- 0x1388 + x"00",x"01",x"ED",x"4B",x"4D",x"4C",x"3A",x"4A", -- 0x1390 + x"4C",x"CD",x"16",x"14",x"AF",x"32",x"4A",x"4C", -- 0x1398 + x"C9",x"AF",x"32",x"48",x"4C",x"32",x"49",x"4C", -- 0x13A0 + x"32",x"47",x"4C",x"C3",x"10",x"13",x"04",x"09", -- 0x13A8 + x"0B",x"0D",x"0F",x"11",x"13",x"15",x"16",x"15", -- 0x13B0 + x"13",x"11",x"0F",x"0D",x"0B",x"09",x"09",x"08", -- 0x13B8 + x"08",x"07",x"07",x"06",x"06",x"05",x"05",x"04", -- 0x13C0 + x"04",x"04",x"03",x"03",x"03",x"03",x"02",x"02", -- 0x13C8 + x"02",x"02",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x13D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13F0 + x"00",x"00",x"00",x"00",x"00",x"FE",x"FF",x"C8", -- 0x13F8 + x"B7",x"C8",x"E5",x"D5",x"5F",x"21",x"44",x"16", -- 0x1400 + x"16",x"00",x"BE",x"28",x"05",x"23",x"23",x"14", -- 0x1408 + x"18",x"F8",x"7A",x"D1",x"E1",x"C9",x"E5",x"D5", -- 0x1410 + x"B7",x"28",x"2D",x"87",x"5F",x"16",x"00",x"21", -- 0x1418 + x"AC",x"16",x"19",x"5E",x"23",x"56",x"7B",x"DD", -- 0x1420 + x"77",x"0C",x"1F",x"1F",x"1F",x"1F",x"DD",x"77", -- 0x1428 + x"0D",x"7A",x"DD",x"77",x"0E",x"1F",x"1F",x"1F", -- 0x1430 + x"1F",x"DD",x"77",x"0F",x"79",x"DD",x"77",x"10", -- 0x1438 + x"3E",x"01",x"32",x"01",x"50",x"D1",x"E1",x"C9", -- 0x1440 + x"DD",x"36",x"10",x"00",x"D1",x"E1",x"C9",x"00", -- 0x1448 + x"00",x"55",x"14",x"81",x"15",x"50",x"80",x"80", -- 0x1450 + x"50",x"66",x"66",x"50",x"56",x"56",x"32",x"56", -- 0x1458 + x"56",x"32",x"AB",x"CB",x"32",x"2B",x"33",x"32", -- 0x1460 + x"2B",x"33",x"32",x"AB",x"CB",x"32",x"33",x"40", -- 0x1468 + x"32",x"33",x"40",x"32",x"AB",x"CB",x"32",x"80", -- 0x1470 + x"80",x"32",x"80",x"80",x"32",x"66",x"66",x"32", -- 0x1478 + x"56",x"56",x"32",x"60",x"56",x"32",x"AB",x"C0", -- 0x1480 + x"32",x"2B",x"30",x"32",x"2B",x"30",x"32",x"AB", -- 0x1488 + x"C0",x"32",x"30",x"44",x"32",x"30",x"44",x"32", -- 0x1490 + x"AB",x"C0",x"32",x"88",x"88",x"32",x"88",x"88", -- 0x1498 + x"32",x"72",x"72",x"32",x"4C",x"4C",x"32",x"4C", -- 0x14A0 + x"4C",x"32",x"AB",x"C0",x"32",x"26",x"30",x"32", -- 0x14A8 + x"26",x"30",x"32",x"AB",x"C0",x"32",x"30",x"44", -- 0x14B0 + x"32",x"30",x"44",x"32",x"AB",x"C0",x"32",x"88", -- 0x14B8 + x"88",x"32",x"88",x"88",x"32",x"72",x"72",x"32", -- 0x14C0 + x"4C",x"4C",x"32",x"4C",x"4C",x"32",x"AB",x"CB", -- 0x14C8 + x"32",x"26",x"33",x"32",x"26",x"33",x"32",x"AB", -- 0x14D0 + x"CB",x"32",x"33",x"40",x"32",x"33",x"40",x"32", -- 0x14D8 + x"AB",x"CB",x"32",x"80",x"80",x"32",x"80",x"80", -- 0x14E0 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"40", -- 0x14E8 + x"40",x"32",x"80",x"AB",x"32",x"20",x"2B",x"32", -- 0x14F0 + x"20",x"2B",x"32",x"80",x"AB",x"32",x"2B",x"33", -- 0x14F8 + x"32",x"2B",x"33",x"32",x"80",x"AB",x"32",x"80", -- 0x1500 + x"80",x"32",x"80",x"80",x"32",x"66",x"66",x"32", -- 0x1508 + x"56",x"56",x"32",x"40",x"40",x"32",x"80",x"98", -- 0x1510 + x"32",x"20",x"26",x"32",x"20",x"26",x"32",x"80", -- 0x1518 + x"98",x"32",x"26",x"30",x"32",x"26",x"30",x"32", -- 0x1520 + x"00",x"00",x"32",x"72",x"72",x"32",x"72",x"72", -- 0x1528 + x"32",x"60",x"60",x"32",x"4C",x"4C",x"32",x"4C", -- 0x1530 + x"98",x"32",x"4C",x"4C",x"32",x"4C",x"4C",x"32", -- 0x1538 + x"4C",x"98",x"32",x"5B",x"5B",x"32",x"56",x"56", -- 0x1540 + x"32",x"33",x"CB",x"32",x"33",x"33",x"32",x"33", -- 0x1548 + x"33",x"32",x"33",x"CB",x"32",x"40",x"40",x"32", -- 0x1550 + x"66",x"66",x"64",x"66",x"66",x"32",x"72",x"72", -- 0x1558 + x"64",x"4C",x"4C",x"32",x"56",x"56",x"32",x"80", -- 0x1560 + x"CB",x"19",x"80",x"00",x"19",x"80",x"80",x"32", -- 0x1568 + x"80",x"CB",x"FA",x"00",x"00",x"FA",x"00",x"00", -- 0x1570 + x"FA",x"00",x"00",x"FA",x"00",x"00",x"00",x"00", -- 0x1578 + x"00",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x1580 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x1588 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x1590 + x"56",x"32",x"51",x"51",x"32",x"60",x"60",x"32", -- 0x1598 + x"51",x"51",x"32",x"51",x"51",x"32",x"56",x"56", -- 0x15A0 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x15A8 + x"56",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x15B0 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x15B8 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x15C0 + x"56",x"32",x"51",x"51",x"32",x"60",x"60",x"32", -- 0x15C8 + x"51",x"51",x"32",x"51",x"51",x"32",x"56",x"56", -- 0x15D0 + x"32",x"56",x"56",x"32",x"56",x"56",x"32",x"56", -- 0x15D8 + x"56",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x15E0 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x15E8 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x15F0 + x"56",x"32",x"51",x"51",x"32",x"60",x"60",x"32", -- 0x15F8 + x"51",x"51",x"32",x"51",x"51",x"32",x"56",x"56", -- 0x1600 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"56", -- 0x1608 + x"56",x"32",x"80",x"80",x"32",x"72",x"72",x"32", -- 0x1610 + x"66",x"66",x"32",x"60",x"60",x"32",x"56",x"56", -- 0x1618 + x"32",x"66",x"66",x"32",x"56",x"56",x"32",x"40", -- 0x1620 + x"40",x"32",x"56",x"56",x"32",x"66",x"66",x"32", -- 0x1628 + x"80",x"80",x"32",x"66",x"66",x"32",x"56",x"56", -- 0x1630 + x"32",x"56",x"56",x"32",x"56",x"56",x"32",x"56", -- 0x1638 + x"56",x"00",x"00",x"00",x"00",x"24",x"FF",x"24", -- 0x1640 + x"F2",x"04",x"E6",x"25",x"D8",x"05",x"CB",x"26", -- 0x1648 + x"C0",x"27",x"B4",x"07",x"AB",x"28",x"A2",x"08", -- 0x1650 + x"98",x"29",x"90",x"09",x"88",x"2A",x"80",x"2B", -- 0x1658 + x"79",x"0B",x"72",x"2C",x"6C",x"0C",x"66",x"2D", -- 0x1660 + x"60",x"2E",x"5B",x"0E",x"56",x"2F",x"51",x"0F", -- 0x1668 + x"4C",x"30",x"48",x"10",x"44",x"31",x"40",x"32", -- 0x1670 + x"3C",x"12",x"39",x"33",x"36",x"13",x"33",x"34", -- 0x1678 + x"30",x"35",x"2D",x"15",x"2B",x"36",x"28",x"16", -- 0x1680 + x"26",x"37",x"24",x"17",x"22",x"38",x"20",x"39", -- 0x1688 + x"1F",x"19",x"1D",x"3A",x"1B",x"1A",x"19",x"3B", -- 0x1690 + x"18",x"3C",x"17",x"1C",x"16",x"3D",x"14",x"1D", -- 0x1698 + x"13",x"3E",x"12",x"1E",x"11",x"3F",x"10",x"2B", -- 0x16A0 + x"01",x"01",x"01",x"01",x"57",x"00",x"5C",x"00", -- 0x16A8 + x"62",x"00",x"6A",x"00",x"6F",x"00",x"75",x"00", -- 0x16B0 + x"7D",x"00",x"85",x"00",x"8E",x"00",x"96",x"00", -- 0x16B8 + x"9E",x"00",x"A6",x"00",x"AE",x"00",x"B9",x"00", -- 0x16C0 + x"C4",x"00",x"D5",x"00",x"DF",x"00",x"EA",x"00", -- 0x16C8 + x"FB",x"00",x"0B",x"01",x"1C",x"01",x"2C",x"01", -- 0x16D0 + x"3C",x"01",x"4D",x"01",x"5D",x"01",x"73",x"01", -- 0x16D8 + x"89",x"01",x"AA",x"01",x"BF",x"01",x"D5",x"01", -- 0x16E0 + x"F6",x"01",x"17",x"02",x"38",x"02",x"58",x"02", -- 0x16E8 + x"79",x"02",x"9A",x"02",x"BA",x"02",x"E6",x"02", -- 0x16F0 + x"12",x"03",x"54",x"03",x"7E",x"03",x"AA",x"03", -- 0x16F8 + x"EC",x"03",x"2E",x"04",x"70",x"04",x"B0",x"04", -- 0x1700 + x"F2",x"04",x"34",x"05",x"74",x"05",x"CC",x"05", -- 0x1708 + x"24",x"06",x"A8",x"06",x"FC",x"06",x"54",x"07", -- 0x1710 + x"D8",x"07",x"5C",x"08",x"E0",x"08",x"60",x"09", -- 0x1718 + x"E4",x"09",x"68",x"0A",x"E8",x"0A",x"98",x"0B", -- 0x1720 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1728 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1730 + x"C8",x"13",x"D0",x"14",x"E8",x"0A",x"98",x"0B", -- 0x1738 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1740 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1748 + x"C8",x"13",x"D0",x"14",x"E8",x"0A",x"98",x"0B", -- 0x1750 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1758 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1760 + x"C8",x"13",x"D0",x"14",x"E8",x"0A",x"98",x"0B", -- 0x1768 + x"48",x"0C",x"50",x"0D",x"F8",x"0D",x"A8",x"0E", -- 0x1770 + x"B0",x"0F",x"B8",x"10",x"C0",x"11",x"C0",x"12", -- 0x1778 + x"C8",x"13",x"D0",x"14",x"AC",x"17",x"30",x"18", -- 0x1780 + x"D3",x"18",x"67",x"19",x"1F",x"1A",x"C9",x"1A", -- 0x1788 + x"71",x"1B",x"2F",x"1C",x"13",x"1D",x"CC",x"1D", -- 0x1790 + x"A0",x"1E",x"77",x"1F",x"59",x"20",x"13",x"21", -- 0x1798 + x"FA",x"21",x"AF",x"22",x"68",x"23",x"3E",x"24", -- 0x17A0 + x"F2",x"24",x"A6",x"25",x"00",x"00",x"05",x"1C", -- 0x17A8 + x"08",x"01",x"0C",x"05",x"04",x"80",x"01",x"11", -- 0x17B0 + x"05",x"04",x"80",x"01",x"00",x"07",x"03",x"08", -- 0x17B8 + x"01",x"11",x"08",x"03",x"20",x"09",x"00",x"09", -- 0x17C0 + x"04",x"08",x"01",x"08",x"09",x"10",x"58",x"0F", -- 0x17C8 + x"1A",x"0A",x"02",x"08",x"01",x"14",x"0C",x"03", -- 0x17D0 + x"20",x"09",x"17",x"0C",x"03",x"80",x"01",x"1A", -- 0x17D8 + x"0C",x"02",x"08",x"01",x"04",x"0D",x"10",x"08", -- 0x17E0 + x"01",x"00",x"0F",x"1C",x"08",x"01",x"1A",x"0D", -- 0x17E8 + x"00",x"04",x"30",x"0F",x"17",x"04",x"1B",x"04", -- 0x17F0 + x"15",x"08",x"0C",x"0C",x"02",x"38",x"05",x"0B", -- 0x17F8 + x"00",x"10",x"00",x"07",x"43",x"45",x"4E",x"54", -- 0x1800 + x"52",x"41",x"4C",x"20",x"43",x"41",x"56",x"45", -- 0x1808 + x"52",x"4E",x"00",x"08",x"09",x"10",x"58",x"0F", -- 0x1810 + x"00",x"01",x"0D",x"05",x"45",x"07",x"09",x"00", -- 0x1818 + x"10",x"01",x"19",x"00",x"18",x"04",x"1B",x"06", -- 0x1820 + x"10",x"28",x"08",x"38",x"40",x"40",x"7E",x"01", -- 0x1828 + x"01",x"10",x"00",x"0C",x"20",x"09",x"12",x"03", -- 0x1830 + x"03",x"88",x"01",x"15",x"03",x"01",x"09",x"01", -- 0x1838 + x"00",x"05",x"12",x"09",x"01",x"12",x"06",x"02", -- 0x1840 + x"09",x"01",x"00",x"07",x"01",x"09",x"01",x"01", -- 0x1848 + x"07",x"04",x"88",x"01",x"08",x"09",x"07",x"09", -- 0x1850 + x"01",x"11",x"0A",x"04",x"88",x"01",x"0D",x"0C", -- 0x1858 + x"03",x"09",x"01",x"07",x"0D",x"03",x"88",x"01", -- 0x1860 + x"00",x"0F",x"1C",x"09",x"01",x"16",x"06",x"87", -- 0x1868 + x"20",x"09",x"19",x"05",x"88",x"20",x"09",x"17", -- 0x1870 + x"06",x"02",x"88",x"01",x"17",x"08",x"02",x"88", -- 0x1878 + x"01",x"17",x"09",x"02",x"88",x"01",x"17",x"0A", -- 0x1880 + x"02",x"88",x"01",x"17",x"0B",x"02",x"88",x"01", -- 0x1888 + x"17",x"0C",x"02",x"88",x"01",x"1A",x"0D",x"00", -- 0x1890 + x"00",x"31",x"07",x"01",x"39",x"05",x"1B",x"01", -- 0x1898 + x"08",x"54",x"48",x"45",x"20",x"43",x"4F",x"4C", -- 0x18A0 + x"44",x"20",x"52",x"4F",x"4F",x"4D",x"00",x"02", -- 0x18A8 + x"0B",x"04",x"58",x"14",x"01",x"01",x"0D",x"05", -- 0x18B0 + x"44",x"07",x"02",x"09",x"07",x"01",x"15",x"01", -- 0x18B8 + x"18",x"07",x"11",x"0C",x"20",x"30",x"10",x"18", -- 0x18C0 + x"80",x"08",x"80",x"FF",x"30",x"13",x"68",x"98", -- 0x18C8 + x"58",x"D4",x"FF",x"00",x"09",x"00",x"01",x"1C", -- 0x18D0 + x"03",x"11",x"00",x"01",x"1B",x"03",x"11",x"01", -- 0x18D8 + x"01",x"1C",x"03",x"1A",x"00",x"01",x"1C",x"03", -- 0x18E0 + x"00",x"05",x"04",x"0A",x"05",x"04",x"05",x"18", -- 0x18E8 + x"98",x"05",x"00",x"07",x"05",x"0A",x"05",x"19", -- 0x18F0 + x"07",x"03",x"0A",x"05",x"00",x"08",x"83",x"1B", -- 0x18F8 + x"03",x"00",x"0B",x"01",x"1C",x"03",x"05",x"09", -- 0x1900 + x"06",x"48",x"01",x"17",x"0A",x"05",x"0A",x"05", -- 0x1908 + x"0C",x"0B",x"05",x"0A",x"05",x"04",x"0C",x"06", -- 0x1910 + x"0A",x"05",x"13",x"0D",x"09",x"0A",x"05",x"00", -- 0x1918 + x"0F",x"1C",x"0A",x"05",x"1A",x"08",x"00",x"00", -- 0x1920 + x"1B",x"07",x"00",x"1C",x"05",x"08",x"54",x"48", -- 0x1928 + x"45",x"20",x"4D",x"45",x"4E",x"41",x"47",x"45", -- 0x1930 + x"52",x"49",x"45",x"00",x"05",x"09",x"06",x"48", -- 0x1938 + x"01",x"00",x"01",x"0D",x"05",x"45",x"1B",x"05", -- 0x1940 + x"00",x"0D",x"00",x"15",x"00",x"12",x"06",x"19", -- 0x1948 + x"06",x"30",x"40",x"13",x"68",x"A0",x"08",x"D0", -- 0x1950 + x"FF",x"40",x"10",x"18",x"50",x"08",x"68",x"FF", -- 0x1958 + x"40",x"12",x"18",x"90",x"78",x"D0",x"01",x"00", -- 0x1960 + x"06",x"00",x"01",x"1C",x"03",x"0D",x"00",x"0F", -- 0x1968 + x"20",x"05",x"12",x"03",x"05",x"0A",x"07",x"19", -- 0x1970 + x"04",x"03",x"0A",x"07",x"00",x"05",x"01",x"0A", -- 0x1978 + x"07",x"06",x"05",x"01",x"0A",x"07",x"10",x"05", -- 0x1980 + x"01",x"0A",x"07",x"0B",x"06",x"02",x"0A",x"07", -- 0x1988 + x"14",x"06",x"03",x"0A",x"07",x"00",x"07",x"03", -- 0x1990 + x"98",x"14",x"06",x"08",x"02",x"0A",x"07",x"18", -- 0x1998 + x"08",x"04",x"0A",x"07",x"11",x"09",x"03",x"0A", -- 0x19A0 + x"07",x"00",x"0A",x"03",x"48",x"05",x"1B",x"0A", -- 0x19A8 + x"01",x"0A",x"07",x"0B",x"0B",x"03",x"0A",x"07", -- 0x19B0 + x"15",x"0B",x"03",x"0A",x"07",x"05",x"0C",x"02", -- 0x19B8 + x"0A",x"07",x"16",x"0C",x"01",x"1C",x"03",x"19", -- 0x19C0 + x"0C",x"03",x"0A",x"07",x"11",x"0D",x"02",x"0A", -- 0x19C8 + x"07",x"00",x"0F",x"1C",x"0A",x"07",x"1A",x"01", -- 0x19D0 + x"00",x"00",x"1B",x"07",x"00",x"1C",x"05",x"01", -- 0x19D8 + x"41",x"42",x"41",x"4E",x"44",x"4F",x"4E",x"45", -- 0x19E0 + x"44",x"20",x"55",x"52",x"41",x"4E",x"49",x"55", -- 0x19E8 + x"4D",x"20",x"57",x"4F",x"52",x"4B",x"49",x"4E", -- 0x19F0 + x"47",x"53",x"00",x"00",x"0A",x"03",x"48",x"05", -- 0x19F8 + x"01",x"1A",x"0D",x"05",x"45",x"1B",x"00",x"00", -- 0x1A00 + x"0B",x"01",x"16",x"01",x"0F",x"07",x"19",x"07", -- 0x1A08 + x"20",x"50",x"08",x"68",x"08",x"08",x"60",x"01", -- 0x1A10 + x"50",x"28",x"68",x"28",x"20",x"78",x"01",x"09", -- 0x1A18 + x"12",x"00",x"01",x"3A",x"01",x"00",x"05",x"0C", -- 0x1A20 + x"0C",x"0F",x"10",x"05",x"04",x"68",x"0F",x"14", -- 0x1A28 + x"05",x"05",x"0C",x"0F",x"1A",x"06",x"02",x"0C", -- 0x1A30 + x"0F",x"10",x"08",x"09",x"48",x"01",x"03",x"09", -- 0x1A38 + x"09",x"0C",x"0F",x"00",x"0B",x"02",x"68",x"0F", -- 0x1A40 + x"02",x"0B",x"0A",x"0C",x"0F",x"10",x"0B",x"06", -- 0x1A48 + x"0C",x"0F",x"1B",x"0B",x"01",x"0C",x"0F",x"00", -- 0x1A50 + x"0D",x"02",x"0C",x"0F",x"00",x"0F",x"1C",x"0C", -- 0x1A58 + x"0F",x"07",x"0C",x"83",x"23",x"0F",x"0C",x"0D", -- 0x1A60 + x"82",x"23",x"0F",x"0F",x"0D",x"82",x"23",x"0F", -- 0x1A68 + x"10",x"0E",x"06",x"23",x"0F",x"07",x"0F",x"0F", -- 0x1A70 + x"23",x"0F",x"0D",x"0D",x"00",x"05",x"33",x"09", -- 0x1A78 + x"14",x"07",x"17",x"04",x"04",x"0E",x"16",x"0E", -- 0x1A80 + x"17",x"0E",x"01",x"3A",x"01",x"12",x"00",x"08", -- 0x1A88 + x"45",x"55",x"47",x"45",x"4E",x"45",x"27",x"53", -- 0x1A90 + x"20",x"4C",x"41",x"49",x"52",x"00",x"10",x"08", -- 0x1A98 + x"09",x"48",x"01",x"00",x"00",x"03",x"05",x"44", -- 0x1AA0 + x"09",x"1B",x"01",x"1A",x"07",x"09",x"06",x"08", -- 0x1AA8 + x"0C",x"06",x"0C",x"21",x"60",x"50",x"18",x"50", -- 0x1AB0 + x"08",x"50",x"FF",x"60",x"20",x"38",x"20",x"20", -- 0x1AB8 + x"50",x"01",x"1C",x"0D",x"08",x"68",x"08",x"58", -- 0x1AC0 + x"01",x"00",x"14",x"04",x"01",x"3B",x"07",x"07", -- 0x1AC8 + x"05",x"03",x"0D",x"0F",x"0E",x"05",x"02",x"0D", -- 0x1AD0 + x"0F",x"14",x"05",x"05",x"0D",x"0F",x"02",x"06", -- 0x1AD8 + x"02",x"0D",x"0F",x"0F",x"06",x"82",x"24",x"09", -- 0x1AE0 + x"1A",x"06",x"02",x"0D",x"0F",x"15",x"08",x"04", -- 0x1AE8 + x"0D",x"0F",x"00",x"09",x"02",x"0D",x"0F",x"06", -- 0x1AF0 + x"0A",x"09",x"0D",x"0F",x"0F",x"0A",x"83",x"24", -- 0x1AF8 + x"09",x"10",x"0A",x"08",x"0D",x"0F",x"10",x"0B", -- 0x1B00 + x"01",x"3B",x"07",x"02",x"0C",x"01",x"34",x"03", -- 0x1B08 + x"1A",x"0C",x"02",x"0D",x"0F",x"02",x"0D",x"04", -- 0x1B10 + x"58",x"0F",x"15",x"0D",x"02",x"0D",x"0F",x"00", -- 0x1B18 + x"0F",x"1C",x"0D",x"0F",x"1A",x"00",x"00",x"00", -- 0x1B20 + x"33",x"01",x"00",x"3A",x"01",x"06",x"50",x"52", -- 0x1B28 + x"4F",x"43",x"45",x"53",x"53",x"49",x"4E",x"47", -- 0x1B30 + x"20",x"50",x"4C",x"41",x"4E",x"54",x"00",x"02", -- 0x1B38 + x"0D",x"04",x"58",x"0F",x"00",x"0F",x"03",x"05", -- 0x1B40 + x"45",x"1B",x"00",x"0A",x"0B",x"0B",x"0E",x"06", -- 0x1B48 + x"10",x"06",x"1B",x"07",x"40",x"70",x"30",x"40", -- 0x1B50 + x"30",x"30",x"60",x"01",x"70",x"70",x"40",x"70", -- 0x1B58 + x"70",x"A0",x"01",x"70",x"38",x"68",x"38",x"38", -- 0x1B60 + x"98",x"01",x"70",x"B8",x"68",x"B8",x"B8",x"D8", -- 0x1B68 + x"01",x"00",x"0D",x"00",x"0F",x"25",x"05",x"0E", -- 0x1B70 + x"03",x"02",x"0B",x"09",x"10",x"03",x"8A",x"25", -- 0x1B78 + x"05",x"11",x"03",x"0B",x"90",x"01",x"11",x"04", -- 0x1B80 + x"0B",x"90",x"01",x"06",x"05",x"04",x"58",x"0F", -- 0x1B88 + x"0D",x"05",x"03",x"0B",x"09",x"11",x"05",x"0B", -- 0x1B90 + x"90",x"01",x"00",x"06",x"03",x"0B",x"09",x"11", -- 0x1B98 + x"06",x"0B",x"90",x"01",x"11",x"07",x"0B",x"90", -- 0x1BA0 + x"01",x"00",x"08",x"01",x"0B",x"09",x"11",x"08", -- 0x1BA8 + x"0B",x"90",x"01",x"0D",x"09",x"03",x"0B",x"09", -- 0x1BB0 + x"11",x"09",x"0B",x"90",x"01",x"01",x"0A",x"0A", -- 0x1BB8 + x"0B",x"09",x"11",x"0A",x"0B",x"90",x"01",x"11", -- 0x1BC0 + x"0B",x"0B",x"90",x"01",x"0D",x"0C",x"03",x"25", -- 0x1BC8 + x"05",x"11",x"0C",x"0B",x"90",x"01",x"08",x"0D", -- 0x1BD0 + x"03",x"0B",x"09",x"0D",x"0D",x"82",x"25",x"05", -- 0x1BD8 + x"00",x"0F",x"1C",x"0B",x"09",x"0D",x"0F",x"0F", -- 0x1BE0 + x"25",x"05",x"0E",x"0D",x"00",x"00",x"34",x"01", -- 0x1BE8 + x"04",x"18",x"09",x"19",x"05",x"16",x"08",x"19", -- 0x1BF0 + x"0A",x"16",x"0C",x"0B",x"54",x"48",x"45",x"20", -- 0x1BF8 + x"56",x"41",x"54",x"00",x"06",x"05",x"04",x"58", -- 0x1C00 + x"0F",x"01",x"00",x"0D",x"05",x"45",x"1B",x"1B", -- 0x1C08 + x"03",x"13",x"06",x"18",x"07",x"12",x"0A",x"1B", -- 0x1C10 + x"0B",x"30",x"80",x"70",x"08",x"70",x"70",x"D0", -- 0x1C18 + x"01",x"80",x"08",x"40",x"08",x"08",x"50",x"01", -- 0x1C20 + x"80",x"80",x"68",x"80",x"80",x"D0",x"01",x"00", -- 0x1C28 + x"01",x"00",x"01",x"3C",x"09",x"09",x"00",x"01", -- 0x1C30 + x"3C",x"09",x"13",x"00",x"82",x"26",x"09",x"10", -- 0x1C38 + x"00",x"8F",x"26",x"09",x"0E",x"02",x"02",x"08", -- 0x1C40 + x"01",x"1A",x"02",x"02",x"08",x"01",x"00",x"05", -- 0x1C48 + x"03",x"08",x"01",x"08",x"05",x"06",x"08",x"01", -- 0x1C50 + x"11",x"05",x"02",x"08",x"01",x"14",x"06",x"02", -- 0x1C58 + x"08",x"01",x"1B",x"06",x"01",x"08",x"01",x"01", -- 0x1C60 + x"07",x"03",x"08",x"01",x"18",x"07",x"01",x"08", -- 0x1C68 + x"01",x"07",x"08",x"03",x"08",x"01",x"11",x"09", -- 0x1C70 + x"03",x"08",x"01",x"00",x"0A",x"01",x"08",x"01", -- 0x1C78 + x"0B",x"0A",x"03",x"08",x"01",x"18",x"0A",x"03", -- 0x1C80 + x"08",x"01",x"08",x"0B",x"02",x"08",x"01",x"03", -- 0x1C88 + x"0C",x"02",x"08",x"01",x"15",x"0C",x"04",x"08", -- 0x1C90 + x"01",x"0A",x"0D",x"02",x"58",x"0F",x"0D",x"0D", -- 0x1C98 + x"82",x"26",x"09",x"11",x"0D",x"02",x"08",x"01", -- 0x1CA0 + x"15",x"0E",x"01",x"30",x"0F",x"00",x"0F",x"1C", -- 0x1CA8 + x"08",x"01",x"05",x"00",x"01",x"46",x"0F",x"11", -- 0x1CB0 + x"00",x"01",x"46",x"0F",x"0E",x"0D",x"00",x"00", -- 0x1CB8 + x"33",x"01",x"00",x"3A",x"01",x"00",x"4D",x"49", -- 0x1CC0 + x"4E",x"45",x"52",x"20",x"57",x"49",x"4C",x"4C", -- 0x1CC8 + x"59",x"20",x"4D",x"45",x"45",x"54",x"53",x"20", -- 0x1CD0 + x"4B",x"4F",x"4E",x"47",x"20",x"42",x"45",x"41", -- 0x1CD8 + x"53",x"54",x"00",x"0A",x"0D",x"03",x"58",x"0F", -- 0x1CE0 + x"00",x"00",x"0D",x"04",x"45",x"1B",x"0C",x"02", -- 0x1CE8 + x"0D",x"06",x"01",x"08",x"1A",x"0D",x"31",x"A0", -- 0x1CF0 + x"44",x"68",x"44",x"00",x"48",x"FF",x"A0",x"68", -- 0x1CF8 + x"58",x"68",x"54",x"74",x"01",x"A0",x"88",x"38", -- 0x1D00 + x"88",x"88",x"98",x"01",x"90",x"0E",x"00",x"70", -- 0x1D08 + x"00",x"68",x"00",x"00",x"02",x"00",x"01",x"27", -- 0x1D10 + x"09",x"00",x"05",x"04",x"0B",x"09",x"06",x"05", -- 0x1D18 + x"02",x"0B",x"09",x"0A",x"05",x"08",x"0B",x"09", -- 0x1D20 + x"14",x"05",x"02",x"0B",x"09",x"18",x"05",x"02", -- 0x1D28 + x"0B",x"09",x"1A",x"07",x"02",x"0B",x"09",x"02", -- 0x1D30 + x"08",x"02",x"0B",x"09",x"06",x"08",x"02",x"0B", -- 0x1D38 + x"09",x"0A",x"08",x"08",x"58",x"0F",x"14",x"09", -- 0x1D40 + x"02",x"0B",x"09",x"18",x"09",x"02",x"0B",x"09", -- 0x1D48 + x"00",x"0A",x"02",x"0B",x"09",x"02",x"0C",x"02", -- 0x1D50 + x"0B",x"09",x"06",x"0C",x"02",x"0B",x"09",x"0A", -- 0x1D58 + x"0C",x"08",x"0B",x"09",x"14",x"0C",x"02",x"0B", -- 0x1D60 + x"09",x"18",x"0C",x"02",x"0B",x"09",x"1A",x"0D", -- 0x1D68 + x"02",x"0B",x"09",x"00",x"0F",x"1C",x"0B",x"09", -- 0x1D70 + x"00",x"00",x"00",x"00",x"33",x"01",x"00",x"3A", -- 0x1D78 + x"01",x"06",x"57",x"41",x"43",x"4B",x"59",x"20", -- 0x1D80 + x"41",x"4D",x"4F",x"45",x"42",x"41",x"54",x"52", -- 0x1D88 + x"4F",x"4E",x"53",x"00",x"0A",x"08",x"08",x"58", -- 0x1D90 + x"0F",x"01",x"00",x"0D",x"01",x"45",x"1B",x"10", -- 0x1D98 + x"01",x"24",x"C0",x"58",x"18",x"58",x"58",x"80", -- 0x1DA0 + x"01",x"C0",x"58",x"50",x"58",x"58",x"80",x"01", -- 0x1DA8 + x"B0",x"04",x"08",x"20",x"04",x"68",x"01",x"B0", -- 0x1DB0 + x"08",x"08",x"40",x"04",x"68",x"02",x"B0",x"12", -- 0x1DB8 + x"08",x"90",x"04",x"68",x"01",x"B0",x"16",x"08", -- 0x1DC0 + x"B0",x"04",x"68",x"02",x"00",x"0C",x"00",x"03", -- 0x1DC8 + x"0E",x"0F",x"0F",x"00",x"8C",x"28",x"09",x"14", -- 0x1DD0 + x"00",x"08",x"0E",x"0F",x"00",x"02",x"06",x"0E", -- 0x1DD8 + x"0F",x"1A",x"02",x"02",x"0E",x"0F",x"10",x"04", -- 0x1DE0 + x"04",x"0E",x"0F",x"07",x"05",x"01",x"0E",x"0F", -- 0x1DE8 + x"08",x"05",x"07",x"78",x"01",x"16",x"05",x"06", -- 0x1DF0 + x"0E",x"0F",x"00",x"06",x"04",x"0E",x"0F",x"10", -- 0x1DF8 + x"07",x"07",x"0E",x"0F",x"17",x"07",x"03",x"78", -- 0x1E00 + x"01",x"00",x"08",x"05",x"0E",x"0F",x"08",x"09", -- 0x1E08 + x"07",x"0E",x"0F",x"1A",x"09",x"02",x"0E",x"0F", -- 0x1E10 + x"00",x"0A",x"04",x"0E",x"0F",x"04",x"0A",x"02", -- 0x1E18 + x"78",x"01",x"10",x"0A",x"07",x"0E",x"0F",x"17", -- 0x1E20 + x"0B",x"03",x"78",x"01",x"07",x"0C",x"0A",x"13", -- 0x1E28 + x"05",x"00",x"0D",x"03",x"0E",x"0F",x"19",x"0D", -- 0x1E30 + x"03",x"0E",x"0F",x"00",x"0F",x"1C",x"13",x"05", -- 0x1E38 + x"0B",x"0D",x"00",x"08",x"37",x"0F",x"0A",x"00", -- 0x1E40 + x"11",x"00",x"13",x"00",x"14",x"01",x"02",x"03", -- 0x1E48 + x"00",x"09",x"1B",x"0A",x"16",x"0B",x"00",x"3B", -- 0x1E50 + x"01",x"05",x"54",x"48",x"45",x"20",x"45",x"4E", -- 0x1E58 + x"44",x"4F",x"52",x"49",x"41",x"4E",x"20",x"46", -- 0x1E60 + x"4F",x"52",x"45",x"53",x"54",x"00",x"02",x"0D", -- 0x1E68 + x"00",x"58",x"0F",x"00",x"00",x"04",x"05",x"45", -- 0x1E70 + x"1B",x"0D",x"01",x"1B",x"01",x"14",x"02",x"0B", -- 0x1E78 + x"06",x"11",x"08",x"40",x"D0",x"40",x"38",x"40", -- 0x1E80 + x"40",x"68",x"01",x"D0",x"38",x"50",x"38",x"38", -- 0x1E88 + x"68",x"01",x"D0",x"18",x"68",x"18",x"18",x"B8", -- 0x1E90 + x"01",x"D0",x"80",x"28",x"80",x"80",x"A0",x"01", -- 0x1E98 + x"00",x"00",x"00",x"06",x"2A",x"07",x"00",x"03", -- 0x1EA0 + x"04",x"0F",x"01",x"04",x"05",x"06",x"0F",x"01", -- 0x1EA8 + x"0E",x"05",x"02",x"0F",x"01",x"10",x"05",x"05", -- 0x1EB0 + x"14",x"05",x"15",x"05",x"02",x"0F",x"01",x"1A", -- 0x1EB8 + x"06",x"02",x"0F",x"01",x"00",x"08",x"02",x"0F", -- 0x1EC0 + x"01",x"04",x"08",x"02",x"80",x"09",x"1A",x"08", -- 0x1EC8 + x"02",x"0F",x"01",x"0A",x"09",x"07",x"0F",x"01", -- 0x1ED0 + x"19",x"0A",x"01",x"0F",x"01",x"05",x"0B",x"03", -- 0x1ED8 + x"80",x"10",x"08",x"0B",x"01",x"0F",x"01",x"19", -- 0x1EE0 + x"0C",x"03",x"0F",x"01",x"00",x"0D",x"02",x"0F", -- 0x1EE8 + x"01",x"14",x"0D",x"03",x"0F",x"01",x"00",x"0F", -- 0x1EF0 + x"1C",x"0F",x"0F",x"00",x"01",x"00",x"04",x"1A", -- 0x1EF8 + x"09",x"10",x"01",x"15",x"09",x"10",x"0B",x"0B", -- 0x1F00 + x"0C",x"07",x"1B",x"01",x"10",x"00",x"15",x"06", -- 0x1F08 + x"15",x"07",x"15",x"08",x"0B",x"0A",x"0B",x"0B", -- 0x1F10 + x"10",x"0A",x"01",x"41",x"54",x"54",x"41",x"43", -- 0x1F18 + x"4B",x"20",x"4F",x"46",x"20",x"54",x"48",x"45", -- 0x1F20 + x"20",x"4D",x"55",x"54",x"41",x"4E",x"54",x"20", -- 0x1F28 + x"50",x"48",x"4F",x"4E",x"45",x"53",x"00",x"04", -- 0x1F30 + x"08",x"02",x"50",x"09",x"00",x"02",x"01",x"05", -- 0x1F38 + x"45",x"1B",x"15",x"00",x"1B",x"01",x"00",x"04", -- 0x1F40 + x"11",x"06",x"1B",x"0D",x"24",x"F0",x"70",x"18", -- 0x1F48 + x"70",x"70",x"A8",x"01",x"F0",x"20",x"68",x"20", -- 0x1F50 + x"20",x"90",x"01",x"E0",x"02",x"20",x"10",x"20", -- 0x1F58 + x"68",x"02",x"E0",x"0B",x"02",x"58",x"02",x"38", -- 0x1F60 + x"01",x"E0",x"12",x"30",x"90",x"30",x"68",x"01", -- 0x1F68 + x"E0",x"17",x"02",x"B8",x"02",x"68",x"FD",x"00", -- 0x1F70 + x"05",x"00",x"01",x"46",x"07",x"10",x"00",x"01", -- 0x1F78 + x"25",x"07",x"11",x"00",x"01",x"46",x"07",x"14", -- 0x1F80 + x"00",x"01",x"25",x"07",x"0E",x"02",x"02",x"80", -- 0x1F88 + x"01",x"00",x"05",x"03",x"08",x"01",x"08",x"05", -- 0x1F90 + x"05",x"80",x"01",x"0D",x"05",x"85",x"25",x"07", -- 0x1F98 + x"10",x"05",x"8B",x"25",x"07",x"11",x"05",x"04", -- 0x1FA0 + x"80",x"01",x"15",x"05",x"02",x"08",x"01",x"1B", -- 0x1FA8 + x"06",x"01",x"08",x"01",x"05",x"07",x"02",x"08", -- 0x1FB0 + x"01",x"02",x"08",x"01",x"08",x"01",x"16",x"08", -- 0x1FB8 + x"06",x"08",x"0F",x"09",x"09",x"04",x"08",x"01", -- 0x1FC0 + x"05",x"0A",x"01",x"08",x"01",x"11",x"0A",x"03", -- 0x1FC8 + x"08",x"01",x"16",x"0B",x"02",x"08",x"01",x"00", -- 0x1FD0 + x"0C",x"06",x"08",x"01",x"0A",x"0D",x"03",x"08", -- 0x1FD8 + x"01",x"0D",x"0D",x"83",x"25",x"07",x"11",x"0D", -- 0x1FE0 + x"08",x"50",x"09",x"00",x"0F",x"0D",x"08",x"01", -- 0x1FE8 + x"0D",x"0F",x"03",x"08",x"01",x"11",x"0F",x"0B", -- 0x1FF0 + x"08",x"01",x"0E",x"0D",x"00",x"02",x"30",x"0F", -- 0x1FF8 + x"14",x"0C",x"19",x"0C",x"02",x"3C",x"05",x"01", -- 0x2000 + x"00",x"09",x"00",x"00",x"52",x"45",x"54",x"55", -- 0x2008 + x"52",x"4E",x"20",x"4F",x"46",x"20",x"41",x"4C", -- 0x2010 + x"49",x"45",x"4E",x"20",x"4B",x"4F",x"4E",x"47", -- 0x2018 + x"20",x"42",x"45",x"41",x"53",x"54",x"00",x"11", -- 0x2020 + x"0D",x"09",x"50",x"09",x"01",x"00",x"0D",x"05", -- 0x2028 + x"45",x"1B",x"0E",x"03",x"17",x"05",x"01",x"06", -- 0x2030 + x"0F",x"07",x"1A",x"0D",x"31",x"A0",x"40",x"68", -- 0x2038 + x"40",x"00",x"40",x"FF",x"A0",x"50",x"58",x"50", -- 0x2040 + x"50",x"70",x"01",x"A0",x"B0",x"30",x"B0",x"B0", -- 0x2048 + x"C8",x"01",x"90",x"0E",x"00",x"70",x"00",x"70", -- 0x2050 + x"00",x"00",x"00",x"00",x"1C",x"27",x"09",x"02", -- 0x2058 + x"01",x"8E",x"16",x"09",x"06",x"03",x"12",x"05", -- 0x2060 + x"05",x"1A",x"03",x"02",x"05",x"05",x"06",x"06", -- 0x2068 + x"02",x"05",x"05",x"0A",x"06",x"04",x"05",x"05", -- 0x2070 + x"10",x"06",x"05",x"05",x"05",x"17",x"06",x"02", -- 0x2078 + x"05",x"05",x"1B",x"06",x"01",x"05",x"05",x"06", -- 0x2080 + x"09",x"05",x"05",x"05",x"0D",x"09",x"03",x"05", -- 0x2088 + x"05",x"13",x"09",x"03",x"05",x"05",x"18",x"09", -- 0x2090 + x"04",x"05",x"05",x"06",x"0C",x"03",x"05",x"05", -- 0x2098 + x"0B",x"0C",x"03",x"05",x"05",x"10",x"0C",x"04", -- 0x20A0 + x"05",x"05",x"16",x"0C",x"02",x"05",x"05",x"1A", -- 0x20A8 + x"0C",x"02",x"05",x"05",x"00",x"0F",x"02",x"05", -- 0x20B0 + x"05",x"02",x"0F",x"18",x"58",x"0F",x"1A",x"0F", -- 0x20B8 + x"02",x"05",x"05",x"00",x"0D",x"00",x"00",x"33", -- 0x20C0 + x"01",x"00",x"3A",x"01",x"08",x"4F",x"52",x"45", -- 0x20C8 + x"20",x"52",x"45",x"46",x"49",x"4E",x"45",x"52", -- 0x20D0 + x"59",x"00",x"02",x"0F",x"18",x"58",x"0F",x"01", -- 0x20D8 + x"1A",x"0D",x"05",x"45",x"1B",x"18",x"03",x"09", -- 0x20E0 + x"06",x"12",x"09",x"17",x"09",x"0A",x"0C",x"41", -- 0x20E8 + x"C0",x"30",x"08",x"30",x"30",x"D0",x"02",x"C0", -- 0x20F0 + x"80",x"20",x"80",x"30",x"D0",x"01",x"C0",x"88", -- 0x20F8 + x"38",x"88",x"30",x"D0",x"FE",x"C0",x"98",x"50", -- 0x2100 + x"98",x"30",x"D0",x"01",x"B0",x"04",x"38",x"20", -- 0x2108 + x"08",x"68",x"02",x"01",x"0E",x"05",x"01",x"06", -- 0x2110 + x"05",x"0F",x"05",x"01",x"07",x"05",x"02",x"06", -- 0x2118 + x"01",x"06",x"05",x"03",x"06",x"01",x"07",x"05", -- 0x2120 + x"0A",x"06",x"01",x"06",x"05",x"0B",x"06",x"01", -- 0x2128 + x"07",x"05",x"12",x"06",x"01",x"06",x"05",x"13", -- 0x2130 + x"06",x"01",x"07",x"05",x"1A",x"06",x"01",x"06", -- 0x2138 + x"05",x"1B",x"06",x"01",x"07",x"05",x"06",x"07", -- 0x2140 + x"01",x"06",x"05",x"07",x"07",x"01",x"07",x"05", -- 0x2148 + x"16",x"07",x"01",x"06",x"05",x"17",x"07",x"01", -- 0x2150 + x"07",x"05",x"04",x"09",x"01",x"06",x"05",x"05", -- 0x2158 + x"09",x"01",x"07",x"05",x"0C",x"09",x"01",x"06", -- 0x2160 + x"05",x"0D",x"09",x"01",x"07",x"05",x"14",x"09", -- 0x2168 + x"01",x"06",x"05",x"15",x"09",x"01",x"07",x"05", -- 0x2170 + x"1A",x"09",x"01",x"06",x"05",x"1B",x"09",x"01", -- 0x2178 + x"07",x"05",x"00",x"0B",x"01",x"06",x"05",x"01", -- 0x2180 + x"0B",x"01",x"07",x"05",x"08",x"0B",x"01",x"06", -- 0x2188 + x"05",x"09",x"0B",x"01",x"07",x"05",x"0E",x"0B", -- 0x2190 + x"06",x"58",x"0F",x"18",x"0B",x"01",x"06",x"05", -- 0x2198 + x"19",x"0B",x"01",x"07",x"05",x"06",x"0D",x"01", -- 0x21A0 + x"06",x"05",x"07",x"0D",x"01",x"07",x"05",x"00", -- 0x21A8 + x"0F",x"1C",x"29",x"05",x"0E",x"00",x"00",x"00", -- 0x21B0 + x"33",x"01",x"00",x"3A",x"01",x"05",x"53",x"4B", -- 0x21B8 + x"59",x"4C",x"41",x"42",x"20",x"4C",x"41",x"4E", -- 0x21C0 + x"44",x"49",x"4E",x"47",x"20",x"42",x"41",x"59", -- 0x21C8 + x"00",x"0E",x"0B",x"06",x"58",x"0F",x"00",x"1A", -- 0x21D0 + x"0D",x"04",x"44",x"01",x"16",x"02",x"0F",x"07", -- 0x21D8 + x"1A",x"07",x"02",x"08",x"03",x"E0",x"00",x"20", -- 0x21E0 + x"00",x"00",x"48",x"04",x"E0",x"0A",x"00",x"50", -- 0x21E8 + x"00",x"20",x"01",x"E0",x"14",x"10",x"A0",x"00", -- 0x21F0 + x"38",x"03",x"00",x"04",x"00",x"18",x"2A",x"07", -- 0x21F8 + x"1A",x"01",x"8E",x"15",x"07",x"1B",x"01",x"8E", -- 0x2200 + x"15",x"07",x"06",x"03",x"0F",x"50",x"05",x"15", -- 0x2208 + x"03",x"05",x"0F",x"01",x"06",x"04",x"01",x"1B", -- 0x2210 + x"01",x"06",x"05",x"01",x"1A",x"09",x"19",x"04", -- 0x2218 + x"86",x"1B",x"01",x"19",x"0A",x"01",x"1A",x"09", -- 0x2220 + x"00",x"05",x"04",x"0F",x"01",x"15",x"06",x"02", -- 0x2228 + x"0F",x"01",x"05",x"07",x"01",x"80",x"10",x"0A", -- 0x2230 + x"07",x"02",x"0F",x"01",x"02",x"08",x"02",x"0F", -- 0x2238 + x"01",x"10",x"08",x"02",x"0F",x"01",x"16",x"09", -- 0x2240 + x"02",x"0F",x"01",x"00",x"0A",x"02",x"0F",x"01", -- 0x2248 + x"0A",x"0A",x"02",x"0F",x"01",x"10",x"0B",x"02", -- 0x2250 + x"0F",x"01",x"04",x"0C",x"02",x"0F",x"01",x"15", -- 0x2258 + x"0C",x"02",x"0F",x"01",x"0A",x"0D",x"02",x"0F", -- 0x2260 + x"01",x"00",x"0F",x"1C",x"0F",x"01",x"00",x"03", -- 0x2268 + x"00",x"00",x"33",x"01",x"00",x"3A",x"01",x"0A", -- 0x2270 + x"54",x"48",x"45",x"20",x"42",x"41",x"4E",x"4B", -- 0x2278 + x"00",x"06",x"03",x"0F",x"50",x"05",x"00",x"01", -- 0x2280 + x"0D",x"03",x"45",x"1B",x"16",x"02",x"0A",x"06", -- 0x2288 + x"18",x"0E",x"13",x"C0",x"78",x"68",x"78",x"78", -- 0x2290 + x"88",x"01",x"E0",x"07",x"28",x"38",x"24",x"68", -- 0x2298 + x"02",x"E0",x"0D",x"40",x"68",x"24",x"68",x"01", -- 0x22A0 + x"E0",x"12",x"50",x"90",x"20",x"68",x"FD",x"00", -- 0x22A8 + x"00",x"05",x"01",x"08",x"01",x"05",x"05",x"01", -- 0x22B0 + x"08",x"01",x"14",x"05",x"02",x"08",x"01",x"03", -- 0x22B8 + x"07",x"01",x"08",x"01",x"16",x"07",x"06",x"08", -- 0x22C0 + x"01",x"0A",x"05",x"84",x"2B",x"17",x"0D",x"05", -- 0x22C8 + x"84",x"2B",x"17",x"0E",x"06",x"83",x"2B",x"17", -- 0x22D0 + x"0F",x"07",x"82",x"2B",x"17",x"10",x"08",x"81", -- 0x22D8 + x"2B",x"17",x"00",x"09",x"02",x"80",x"01",x"02", -- 0x22E0 + x"09",x"18",x"50",x"09",x"09",x"0B",x"02",x"2B", -- 0x22E8 + x"17",x"0B",x"0B",x"02",x"08",x"01",x"0B",x"0B", -- 0x22F0 + x"02",x"08",x"01",x"19",x"0B",x"01",x"08",x"01", -- 0x22F8 + x"00",x"0C",x"09",x"08",x"01",x"13",x"0D",x"01", -- 0x2300 + x"08",x"01",x"19",x"0D",x"01",x"08",x"01",x"16", -- 0x2308 + x"0E",x"03",x"36",x"0F",x"00",x"0F",x"1C",x"08", -- 0x2310 + x"01",x"0B",x"05",x"00",x"00",x"33",x"01",x"00", -- 0x2318 + x"3A",x"01",x"04",x"54",x"48",x"45",x"20",x"53", -- 0x2320 + x"49",x"58",x"54",x"45",x"45",x"4E",x"54",x"48", -- 0x2328 + x"20",x"43",x"41",x"56",x"45",x"52",x"4E",x"00", -- 0x2330 + x"02",x"09",x"18",x"50",x"09",x"00",x"01",x"0D", -- 0x2338 + x"04",x"45",x"1B",x"00",x"00",x"1B",x"02",x"0C", -- 0x2340 + x"07",x"10",x"0A",x"40",x"20",x"B0",x"28",x"B0", -- 0x2348 + x"B0",x"D0",x"01",x"20",x"88",x"38",x"88",x"88", -- 0x2350 + x"A0",x"01",x"20",x"10",x"50",x"10",x"02",x"38", -- 0x2358 + x"01",x"20",x"50",x"68",x"50",x"02",x"88",x"01", -- 0x2360 + x"00",x"00",x"05",x"1C",x"90",x"05",x"00",x"06", -- 0x2368 + x"1C",x"90",x"05",x"00",x"07",x"1C",x"90",x"05", -- 0x2370 + x"00",x"08",x"1C",x"90",x"05",x"00",x"09",x"1C", -- 0x2378 + x"90",x"05",x"00",x"0A",x"1C",x"90",x"05",x"00", -- 0x2380 + x"0B",x"1C",x"90",x"05",x"00",x"0C",x"1C",x"90", -- 0x2388 + x"05",x"02",x"08",x"85",x"00",x"00",x"03",x"08", -- 0x2390 + x"85",x"00",x"00",x"08",x"05",x"88",x"00",x"00", -- 0x2398 + x"09",x"05",x"88",x"00",x"00",x"11",x"05",x"85", -- 0x23A0 + x"00",x"00",x"12",x"05",x"85",x"00",x"00",x"18", -- 0x23A8 + x"05",x"88",x"00",x"00",x"19",x"05",x"88",x"00", -- 0x23B0 + x"00",x"0C",x"08",x"05",x"58",x"0F",x"00",x"05", -- 0x23B8 + x"02",x"11",x"05",x"1A",x"05",x"02",x"11",x"05", -- 0x23C0 + x"18",x"0E",x"04",x"11",x"05",x"00",x"0F",x"1C", -- 0x23C8 + x"11",x"05",x"1A",x"01",x"00",x"06",x"32",x"07", -- 0x23D0 + x"05",x"04",x"07",x"04",x"0B",x"04",x"0E",x"04", -- 0x23D8 + x"14",x"04",x"16",x"04",x"04",x"3E",x"05",x"02", -- 0x23E0 + x"06",x"17",x"07",x"14",x"0A",x"07",x"0B",x"08", -- 0x23E8 + x"54",x"48",x"45",x"20",x"57",x"41",x"52",x"45", -- 0x23F0 + x"48",x"4F",x"55",x"53",x"45",x"00",x"0C",x"08", -- 0x23F8 + x"05",x"58",x"0F",x"01",x"00",x"03",x"05",x"45", -- 0x2400 + x"1B",x"16",x"05",x"0D",x"07",x"00",x"09",x"11", -- 0x2408 + x"0A",x"17",x"0B",x"24",x"70",x"20",x"68",x"20", -- 0x2410 + x"20",x"30",x"01",x"70",x"50",x"68",x"50",x"50", -- 0x2418 + x"B0",x"01",x"40",x"02",x"40",x"10",x"40",x"68", -- 0x2420 + x"02",x"40",x"08",x"40",x"40",x"00",x"68",x"FD", -- 0x2428 + x"40",x"11",x"30",x"88",x"00",x"40",x"01",x"40", -- 0x2430 + x"18",x"00",x"C0",x"00",x"60",x"04",x"00",x"19", -- 0x2438 + x"00",x"01",x"2D",x"09",x"02",x"05",x"1A",x"08", -- 0x2440 + x"01",x"00",x"07",x"02",x"08",x"01",x"0B",x"08", -- 0x2448 + x"11",x"08",x"01",x"02",x"09",x"07",x"08",x"01", -- 0x2450 + x"1B",x"0A",x"01",x"08",x"01",x"02",x"0C",x"1A", -- 0x2458 + x"08",x"01",x"00",x"0D",x"02",x"08",x"01",x"04", -- 0x2460 + x"05",x"88",x"00",x"00",x"05",x"05",x"88",x"00", -- 0x2468 + x"00",x"09",x"05",x"88",x"00",x"00",x"0A",x"05", -- 0x2470 + x"88",x"00",x"00",x"13",x"05",x"88",x"00",x"00", -- 0x2478 + x"14",x"05",x"88",x"00",x"00",x"18",x"05",x"88", -- 0x2480 + x"00",x"00",x"19",x"05",x"88",x"00",x"00",x"00", -- 0x2488 + x"0F",x"1C",x"08",x"01",x"1A",x"00",x"00",x"00", -- 0x2490 + x"34",x"01",x"00",x"3B",x"01",x"04",x"4F",x"4D", -- 0x2498 + x"4F",x"45",x"42",x"41",x"54",x"52",x"4F",x"4E", -- 0x24A0 + x"53",x"27",x"20",x"52",x"45",x"56",x"45",x"4E", -- 0x24A8 + x"47",x"45",x"00",x"02",x"0D",x"00",x"58",x"0F", -- 0x24B0 + x"00",x"1A",x"0D",x"01",x"45",x"1B",x"0F",x"01", -- 0x24B8 + x"34",x"C0",x"58",x"30",x"58",x"58",x"88",x"02", -- 0x24C0 + x"C0",x"78",x"50",x"78",x"58",x"88",x"01",x"C0", -- 0x24C8 + x"70",x"68",x"70",x"58",x"88",x"FE",x"B0",x"04", -- 0x24D0 + x"68",x"20",x"05",x"68",x"FC",x"B0",x"09",x"48", -- 0x24D8 + x"48",x"05",x"68",x"02",x"B0",x"13",x"48",x"98", -- 0x24E0 + x"05",x"68",x"04",x"B0",x"18",x"28",x"C0",x"05", -- 0x24E8 + x"68",x"01",x"0F",x"00",x"00",x"02",x"20",x"09", -- 0x24F0 + x"02",x"05",x"01",x"12",x"15",x"07",x"05",x"06", -- 0x24F8 + x"12",x"15",x"15",x"05",x"07",x"12",x"15",x"11", -- 0x2500 + x"07",x"02",x"12",x"15",x"00",x"08",x"01",x"12", -- 0x2508 + x"15",x"0B",x"08",x"03",x"12",x"15",x"15",x"08", -- 0x2510 + x"07",x"12",x"15",x"11",x"0A",x"01",x"12",x"15", -- 0x2518 + x"00",x"0B",x"03",x"12",x"15",x"0C",x"0C",x"05", -- 0x2520 + x"12",x"15",x"15",x"0B",x"07",x"12",x"15",x"00", -- 0x2528 + x"0E",x"02",x"20",x"09",x"00",x"0F",x"02",x"20", -- 0x2530 + x"09",x"02",x"0F",x"1A",x"12",x"15",x"14",x"0F", -- 0x2538 + x"01",x"20",x"09",x"00",x"01",x"00",x"00",x"33", -- 0x2540 + x"01",x"00",x"3A",x"01",x"04",x"53",x"4F",x"4C", -- 0x2548 + x"41",x"52",x"20",x"50",x"4F",x"57",x"45",x"52", -- 0x2550 + x"20",x"47",x"45",x"4E",x"45",x"52",x"41",x"54", -- 0x2558 + x"4F",x"52",x"00",x"05",x"0C",x"04",x"58",x"0F", -- 0x2560 + x"00",x"0C",x"0A",x"03",x"44",x"0F",x"1B",x"01", -- 0x2568 + x"00",x"05",x"1B",x"0C",x"43",x"70",x"B8",x"18", -- 0x2570 + x"B8",x"A0",x"D0",x"02",x"70",x"D0",x"30",x"D0", -- 0x2578 + x"98",x"D0",x"FE",x"70",x"C8",x"48",x"C8",x"98", -- 0x2580 + x"D0",x"FF",x"70",x"78",x"68",x"78",x"60",x"D0", -- 0x2588 + x"02",x"E0",x"03",x"58",x"18",x"04",x"68",x"03", -- 0x2590 + x"E0",x"09",x"38",x"48",x"30",x"68",x"FE",x"E0", -- 0x2598 + x"0E",x"48",x"70",x"02",x"50",x"FF",x"00",x"00", -- 0x25A0 + x"00",x"05",x"03",x"0F",x"00",x"01",x"05",x"03", -- 0x25A8 + x"0F",x"00",x"02",x"04",x"03",x"0F",x"02",x"02", -- 0x25B0 + x"84",x"28",x"09",x"05",x"00",x"17",x"01",x"01", -- 0x25B8 + x"05",x"01",x"17",x"01",x"01",x"04",x"02",x"18", -- 0x25C0 + x"01",x"01",x"17",x"02",x"05",x"04",x"01",x"17", -- 0x25C8 + x"03",x"05",x"04",x"01",x"00",x"03",x"83",x"01", -- 0x25D0 + x"01",x"01",x"03",x"83",x"01",x"01",x"03",x"03", -- 0x25D8 + x"0C",x"01",x"01",x"03",x"04",x"03",x"01",x"01", -- 0x25E0 + x"06",x"04",x"01",x"3F",x"09",x"05",x"05",x"01", -- 0x25E8 + x"3F",x"09",x"07",x"04",x"02",x"2E",x"09",x"06", -- 0x25F0 + x"05",x"04",x"2E",x"09",x"09",x"04",x"01",x"1F", -- 0x25F8 + x"09",x"0A",x"05",x"01",x"1F",x"09",x"13",x"00", -- 0x2600 + x"01",x"3F",x"09",x"14",x"00",x"02",x"2E",x"09", -- 0x2608 + x"16",x"00",x"01",x"1F",x"09",x"13",x"01",x"82", -- 0x2610 + x"2E",x"0F",x"14",x"01",x"82",x"1E",x"01",x"15", -- 0x2618 + x"01",x"82",x"1E",x"01",x"16",x"01",x"82",x"2E", -- 0x2620 + x"0F",x"13",x"03",x"04",x"2E",x"0F",x"0A",x"04", -- 0x2628 + x"03",x"01",x"01",x"03",x"05",x"02",x"01",x"01", -- 0x2630 + x"0B",x"05",x"01",x"01",x"01",x"1A",x"08",x"02", -- 0x2638 + x"08",x"01",x"18",x"0A",x"01",x"80",x"01",x"19", -- 0x2640 + x"0B",x"01",x"08",x"01",x"00",x"0C",x"01",x"08", -- 0x2648 + x"01",x"03",x"0D",x"01",x"08",x"01",x"00",x"0F", -- 0x2650 + x"1C",x"08",x"01",x"0F",x"04",x"0D",x"24",x"15", -- 0x2658 + x"0D",x"05",x"03",x"24",x"15",x"12",x"05",x"83", -- 0x2660 + x"24",x"15",x"0D",x"06",x"03",x"24",x"15",x"00", -- 0x2668 + x"06",x"04",x"24",x"15",x"00",x"07",x"10",x"24", -- 0x2670 + x"15",x"04",x"06",x"03",x"03",x"0F",x"07",x"06", -- 0x2678 + x"02",x"01",x"01",x"09",x"06",x"04",x"03",x"0F", -- 0x2680 + x"0C",x"05",x"01",x"03",x"0F",x"10",x"05",x"00", -- 0x2688 + x"06",x"31",x"05",x"0D",x"04",x"0E",x"04",x"0F", -- 0x2690 + x"03",x"10",x"03",x"11",x"03",x"12",x"03",x"04", -- 0x2698 + x"1A",x"05",x"06",x"0B",x"09",x"0B",x"0E",x"0B", -- 0x26A0 + x"12",x"0B",x"06",x"54",x"48",x"45",x"20",x"46", -- 0x26A8 + x"49",x"4E",x"41",x"4C",x"20",x"42",x"41",x"52", -- 0x26B0 + x"52",x"49",x"45",x"52",x"00",x"00",x"0A",x"14", -- 0x26B8 + x"58",x"0F",x"01",x"19",x"0D",x"05",x"45",x"1B", -- 0x26C0 + x"14",x"05",x"1B",x"06",x"07",x"0B",x"0B",x"0B", -- 0x26C8 + x"10",x"0B",x"11",x"70",x"38",x"68",x"38",x"20", -- 0x26D0 + x"98",x"02",x"E0",x"15",x"30",x"A8",x"28",x"68", -- 0x26D8 + x"01",x"00",x"21",x"07",x"27",x"16",x"16",x"0E", -- 0x26E0 + x"0A",x"1E",x"00",x"06",x"1C",x"7E",x"23",x"E5", -- 0x26E8 + x"D5",x"F5",x"CD",x"6D",x"0B",x"F1",x"C6",x"80", -- 0x26F0 + x"77",x"CB",x"D4",x"36",x"1B",x"D1",x"E1",x"1C", -- 0x26F8 + x"10",x"EB",x"14",x"0D",x"20",x"E3",x"C9",x"20", -- 0x2700 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2708 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2710 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2718 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"50", -- 0x2720 + x"41",x"43",x"2D",x"4D",x"41",x"4E",x"49",x"43", -- 0x2728 + x"2D",x"4D",x"49",x"4E",x"45",x"52",x"2D",x"4D", -- 0x2730 + x"41",x"4E",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2738 + x"57",x"52",x"49",x"54",x"54",x"45",x"4E",x"20", -- 0x2740 + x"42",x"59",x"20",x"4A",x"49",x"4D",x"20",x"42", -- 0x2748 + x"41",x"47",x"4C",x"45",x"59",x"20",x"46",x"4F", -- 0x2750 + x"52",x"20",x"20",x"20",x"20",x"50",x"41",x"43", -- 0x2758 + x"4D",x"41",x"4E",x"20",x"41",x"52",x"43",x"41", -- 0x2760 + x"44",x"45",x"20",x"48",x"41",x"52",x"44",x"57", -- 0x2768 + x"41",x"52",x"45",x"2E",x"20",x"20",x"20",x"20", -- 0x2770 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2778 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2780 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2788 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2790 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2798 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x27A0 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x27A8 + x"20",x"20",x"4A",x"55",x"4D",x"50",x"20",x"3D", -- 0x27B0 + x"20",x"4A",x"4F",x"59",x"20",x"32",x"20",x"2D", -- 0x27B8 + x"3E",x"20",x"52",x"49",x"47",x"48",x"54",x"20", -- 0x27C0 + x"20",x"20",x"20",x"20",x"4D",x"55",x"53",x"49", -- 0x27C8 + x"43",x"20",x"4F",x"4E",x"2F",x"4F",x"46",x"46", -- 0x27D0 + x"20",x"3D",x"20",x"4A",x"4F",x"59",x"20",x"32", -- 0x27D8 + x"20",x"2D",x"3E",x"20",x"55",x"50",x"20",x"20", -- 0x27E0 + x"46",x"58",x"20",x"4F",x"4E",x"2F",x"4F",x"46", -- 0x27E8 + x"46",x"20",x"3D",x"20",x"4A",x"4F",x"59",x"20", -- 0x27F0 + x"32",x"20",x"2D",x"3E",x"20",x"44",x"4F",x"57", -- 0x27F8 + x"4E",x"2E",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2800 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2808 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x2810 + x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"41", -- 0x2818 + x"49",x"52",x"20",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x2820 + x"E7",x"00",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x2828 + x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x2830 + x"E7",x"E7",x"E7",x"E7",x"00",x"48",x"49",x"53", -- 0x2838 + x"43",x"4F",x"52",x"45",x"20",x"00",x"20",x"20", -- 0x2840 + x"53",x"43",x"4F",x"52",x"45",x"20",x"00",x"00", -- 0x2848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3818 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3820 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3828 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3830 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3838 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/gfx1.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/gfx1.vhd new file mode 100644 index 00000000..e2802758 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/gfx1.vhd @@ -0,0 +1,2077 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity GFX1 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of GFX1 is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0008 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0010 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0018 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0028 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0030 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0038 + x"F0",x"0F",x"0F",x"F0",x"F0",x"0F",x"0F",x"F0", -- 0x0040 + x"C3",x"0F",x"0F",x"C3",x"C3",x"0F",x"0F",x"C3", -- 0x0048 + x"33",x"33",x"BB",x"77",x"33",x"33",x"BB",x"77", -- 0x0050 + x"EE",x"DD",x"CC",x"CC",x"EE",x"DD",x"CC",x"CC", -- 0x0058 + x"F0",x"F0",x"F0",x"F8",x"FC",x"FF",x"FF",x"F0", -- 0x0060 + x"FC",x"FE",x"FD",x"FC",x"FC",x"FF",x"FF",x"FC", -- 0x0068 + x"F0",x"FF",x"FF",x"FC",x"F8",x"F0",x"F0",x"F0", -- 0x0070 + x"FC",x"FF",x"FF",x"FC",x"FC",x"FD",x"FE",x"FC", -- 0x0078 + x"88",x"00",x"88",x"00",x"00",x"00",x"CC",x"88", -- 0x0080 + x"EE",x"FF",x"DD",x"FF",x"EE",x"DD",x"FF",x"EE", -- 0x0088 + x"78",x"F0",x"78",x"F0",x"F0",x"F0",x"3C",x"78", -- 0x0090 + x"1E",x"0F",x"0F",x"0F",x"1E",x"2D",x"0F",x"1E", -- 0x0098 + x"66",x"AA",x"AA",x"66",x"66",x"AA",x"AA",x"66", -- 0x00A0 + x"DD",x"EE",x"EE",x"DD",x"DD",x"EE",x"EE",x"DD", -- 0x00A8 + x"88",x"00",x"88",x"00",x"00",x"00",x"CC",x"88", -- 0x00B0 + x"EE",x"FF",x"DD",x"FF",x"EE",x"DD",x"FF",x"EE", -- 0x00B8 + x"87",x"0F",x"87",x"0F",x"0F",x"0F",x"C3",x"87", -- 0x00C0 + x"E1",x"F0",x"D2",x"F0",x"E1",x"D2",x"F0",x"E1", -- 0x00C8 + x"C0",x"A0",x"A0",x"C0",x"C0",x"A0",x"A0",x"C0", -- 0x00D0 + x"F0",x"C0",x"C0",x"F0",x"F0",x"C0",x"C0",x"F0", -- 0x00D8 + x"00",x"00",x"80",x"F0",x"00",x"00",x"00",x"00", -- 0x00E0 + x"60",x"70",x"F0",x"F0",x"D0",x"E0",x"E0",x"60", -- 0x00E8 + x"80",x"00",x"80",x"00",x"00",x"00",x"C0",x"80", -- 0x00F0 + x"E0",x"F0",x"D0",x"F0",x"E0",x"D0",x"F0",x"E0", -- 0x00F8 + x"F8",x"F0",x"F8",x"F0",x"F0",x"F0",x"FC",x"F8", -- 0x0100 + x"FE",x"FF",x"FD",x"FF",x"FE",x"FD",x"FF",x"FE", -- 0x0108 + x"80",x"00",x"80",x"00",x"00",x"00",x"C0",x"80", -- 0x0110 + x"E0",x"F0",x"D0",x"F0",x"E0",x"D0",x"F0",x"E0", -- 0x0118 + x"70",x"F0",x"70",x"F0",x"F0",x"F0",x"30",x"70", -- 0x0120 + x"10",x"00",x"20",x"00",x"10",x"20",x"00",x"10", -- 0x0128 + x"00",x"AA",x"00",x"44",x"88",x"44",x"00",x"AA", -- 0x0130 + x"DD",x"EE",x"DD",x"EE",x"CC",x"DD",x"FF",x"EE", -- 0x0138 + x"00",x"88",x"00",x"88",x"00",x"88",x"00",x"88", -- 0x0140 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148 + x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0150 + x"CC",x"CC",x"CC",x"FF",x"FF",x"CC",x"CC",x"CC", -- 0x0158 + x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0160 + x"FF",x"88",x"88",x"88",x"88",x"88",x"88",x"FF", -- 0x0168 + x"0F",x"5A",x"A5",x"5A",x"A5",x"5A",x"A5",x"0F", -- 0x0170 + x"0F",x"5A",x"A5",x"5A",x"A5",x"5A",x"A5",x"0F", -- 0x0178 + x"F2",x"F4",x"FF",x"FC",x"FC",x"FF",x"F4",x"F2", -- 0x0180 + x"F9",x"F5",x"FA",x"F3",x"F3",x"FA",x"F5",x"F9", -- 0x0188 + x"00",x"44",x"55",x"AA",x"FF",x"AA",x"55",x"44", -- 0x0190 + x"00",x"00",x"11",x"00",x"FF",x"00",x"11",x"00", -- 0x0198 + x"00",x"99",x"AA",x"44",x"FF",x"44",x"AA",x"99", -- 0x01A0 + x"00",x"22",x"22",x"11",x"FF",x"11",x"22",x"22", -- 0x01A8 + x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x01B8 + x"00",x"22",x"66",x"99",x"88",x"99",x"66",x"22", -- 0x01C0 + x"00",x"55",x"55",x"22",x"FF",x"22",x"55",x"55", -- 0x01C8 + x"00",x"00",x"00",x"00",x"F0",x"00",x"00",x"00", -- 0x01D0 + x"00",x"00",x"00",x"00",x"F0",x"00",x"00",x"00", -- 0x01D8 + x"00",x"0E",x"0E",x"0E",x"0E",x"0E",x"0E",x"00", -- 0x01E0 + x"00",x"07",x"07",x"07",x"07",x"07",x"07",x"00", -- 0x01E8 + x"1F",x"3F",x"7F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x01F0 + x"0F",x"0F",x"0F",x"0F",x"1F",x"3F",x"7F",x"FF", -- 0x01F8 + x"F5",x"FD",x"F5",x"F7",x"F5",x"FD",x"F5",x"F7", -- 0x0200 + x"F5",x"FD",x"F5",x"F7",x"F5",x"FD",x"F5",x"F7", -- 0x0208 + x"FF",x"F2",x"F4",x"F8",x"F8",x"F4",x"F2",x"FF", -- 0x0210 + x"FF",x"F4",x"F2",x"F1",x"F1",x"F2",x"F4",x"FF", -- 0x0218 + x"FA",x"F2",x"FA",x"F8",x"FA",x"F2",x"FA",x"F8", -- 0x0220 + x"FA",x"F2",x"FA",x"F8",x"FA",x"F2",x"FA",x"F8", -- 0x0228 + x"5F",x"DF",x"5F",x"7F",x"5F",x"DF",x"5F",x"7F", -- 0x0230 + x"7F",x"DF",x"5F",x"7F",x"5F",x"DF",x"5F",x"7F", -- 0x0238 + x"FE",x"FB",x"FB",x"FE",x"FE",x"FB",x"FB",x"FE", -- 0x0240 + x"FE",x"FB",x"FB",x"FE",x"FE",x"FB",x"FB",x"FE", -- 0x0248 + x"F5",x"FD",x"F5",x"F7",x"F5",x"FD",x"F5",x"F7", -- 0x0250 + x"F5",x"FD",x"F5",x"F7",x"F5",x"FD",x"F5",x"F7", -- 0x0258 + x"FA",x"F2",x"FA",x"F8",x"FA",x"F2",x"FA",x"F8", -- 0x0260 + x"FA",x"F2",x"FA",x"F8",x"FA",x"F2",x"FA",x"F8", -- 0x0268 + x"F0",x"FF",x"F0",x"FF",x"FF",x"F0",x"FF",x"F0", -- 0x0270 + x"F0",x"FF",x"F0",x"FF",x"FF",x"F0",x"FF",x"F0", -- 0x0278 + x"F0",x"F7",x"F8",x"F7",x"F8",x"F3",x"FC",x"F0", -- 0x0280 + x"F0",x"FF",x"F0",x"FE",x"F1",x"F0",x"FF",x"F0", -- 0x0288 + x"FF",x"EE",x"CC",x"88",x"88",x"44",x"22",x"11", -- 0x0290 + x"77",x"BB",x"DD",x"EE",x"FF",x"EE",x"CC",x"88", -- 0x0298 + x"F5",x"FA",x"F5",x"FA",x"F5",x"FA",x"F5",x"FA", -- 0x02A0 + x"F5",x"FA",x"F5",x"FA",x"F5",x"FA",x"F5",x"FA", -- 0x02A8 + x"F9",x"F9",x"F9",x"FF",x"FA",x"FA",x"FF",x"F9", -- 0x02B0 + x"FF",x"F2",x"F2",x"FF",x"F4",x"F4",x"FF",x"F4", -- 0x02B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02C8 + x"FF",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"FF", -- 0x02D0 + x"FF",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"FF", -- 0x02D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x02E8 + x"FF",x"F2",x"F4",x"F8",x"F8",x"F4",x"F2",x"FF", -- 0x02F0 + x"FF",x"F4",x"F2",x"F1",x"F1",x"F2",x"F4",x"FF", -- 0x02F8 + x"80",x"40",x"C0",x"20",x"F0",x"80",x"60",x"40", -- 0x0300 + x"10",x"00",x"A0",x"40",x"30",x"40",x"90",x"20", -- 0x0308 + x"F8",x"F4",x"FC",x"F2",x"FF",x"F8",x"F6",x"F4", -- 0x0310 + x"F1",x"F0",x"FA",x"F4",x"F3",x"F4",x"F9",x"F2", -- 0x0318 + x"88",x"44",x"CC",x"22",x"FF",x"88",x"66",x"44", -- 0x0320 + x"11",x"00",x"AA",x"44",x"33",x"44",x"99",x"22", -- 0x0328 + x"F8",x"F4",x"FC",x"F2",x"FF",x"F8",x"F6",x"F4", -- 0x0330 + x"F1",x"F0",x"FA",x"F4",x"F3",x"F4",x"F9",x"F2", -- 0x0338 + x"88",x"44",x"CC",x"22",x"FF",x"88",x"66",x"44", -- 0x0340 + x"11",x"00",x"AA",x"44",x"33",x"44",x"99",x"22", -- 0x0348 + x"87",x"4B",x"C3",x"2D",x"F0",x"87",x"69",x"4B", -- 0x0350 + x"1E",x"0F",x"A5",x"4B",x"3C",x"4B",x"96",x"2D", -- 0x0358 + x"10",x"F0",x"F0",x"70",x"10",x"F0",x"F0",x"70", -- 0x0360 + x"00",x"00",x"F0",x"00",x"00",x"00",x"F0",x"00", -- 0x0368 + x"30",x"50",x"50",x"60",x"80",x"E0",x"90",x"60", -- 0x0370 + x"20",x"50",x"20",x"A0",x"70",x"40",x"A0",x"40", -- 0x0378 + x"00",x"00",x"CC",x"FF",x"00",x"00",x"CC",x"00", -- 0x0380 + x"88",x"EE",x"FF",x"FF",x"FF",x"FF",x"FF",x"CC", -- 0x0388 + x"F0",x"F0",x"FC",x"FF",x"F0",x"F0",x"FC",x"F0", -- 0x0390 + x"F8",x"FE",x"FF",x"FF",x"FE",x"FD",x"FF",x"FC", -- 0x0398 + x"FF",x"FF",x"FF",x"F0",x"F7",x"FF",x"FF",x"FF", -- 0x03A0 + x"FF",x"F7",x"F1",x"F0",x"F0",x"F3",x"F7",x"FF", -- 0x03A8 + x"CC",x"88",x"DD",x"77",x"77",x"DD",x"88",x"CC", -- 0x03B0 + x"33",x"11",x"BB",x"EE",x"EE",x"BB",x"11",x"33", -- 0x03B8 + x"00",x"00",x"00",x"FF",x"88",x"00",x"00",x"00", -- 0x03C0 + x"00",x"88",x"EE",x"FF",x"FF",x"CC",x"88",x"00", -- 0x03C8 + x"F0",x"F0",x"F0",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x03D0 + x"F0",x"F8",x"FE",x"FF",x"FF",x"FC",x"F8",x"F0", -- 0x03D8 + x"FA",x"F4",x"F0",x"F9",x"FA",x"F1",x"F8",x"F4", -- 0x03E0 + x"FA",x"F1",x"F8",x"FD",x"F9",x"FC",x"F0",x"F9", -- 0x03E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F",x"1F", -- 0x03F0 + x"FF",x"7F",x"3F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 + x"F2",x"FF",x"F6",x"F2",x"FF",x"F6",x"F2",x"FF", -- 0x0400 + x"F9",x"FF",x"FB",x"F9",x"FF",x"FB",x"F9",x"FF", -- 0x0408 + x"FF",x"F6",x"F2",x"FF",x"F6",x"F2",x"FF",x"F6", -- 0x0410 + x"FF",x"FB",x"F9",x"FF",x"FB",x"F9",x"FF",x"FB", -- 0x0418 + x"F9",x"FF",x"FB",x"F9",x"FF",x"FB",x"F9",x"FF", -- 0x0420 + x"F4",x"FF",x"FD",x"F4",x"FF",x"FD",x"F4",x"FF", -- 0x0428 + x"FF",x"FB",x"F9",x"FF",x"FB",x"F9",x"FF",x"FB", -- 0x0430 + x"FF",x"FD",x"F4",x"FF",x"FD",x"F4",x"FF",x"FD", -- 0x0438 + x"F0",x"F2",x"F5",x"FA",x"F0",x"F8",x"F8",x"F0", -- 0x0440 + x"F0",x"F0",x"F0",x"F6",x"F9",x"F8",x"F4",x"F3", -- 0x0448 + x"00",x"22",x"55",x"AA",x"00",x"88",x"88",x"00", -- 0x0450 + x"00",x"00",x"00",x"66",x"99",x"88",x"44",x"33", -- 0x0458 + x"00",x"00",x"88",x"88",x"CC",x"BB",x"33",x"00", -- 0x0460 + x"EE",x"99",x"88",x"88",x"88",x"88",x"99",x"EE", -- 0x0468 + x"00",x"33",x"BB",x"CC",x"88",x"88",x"00",x"00", -- 0x0470 + x"EE",x"99",x"88",x"88",x"88",x"88",x"99",x"EE", -- 0x0478 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x0480 + x"88",x"55",x"11",x"66",x"22",x"FF",x"BB",x"CC", -- 0x0488 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x0490 + x"88",x"DD",x"33",x"66",x"22",x"77",x"99",x"CC", -- 0x0498 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x04A0 + x"88",x"FF",x"BB",x"66",x"22",x"55",x"11",x"CC", -- 0x04A8 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x04B0 + x"AA",x"FF",x"BB",x"EE",x"00",x"55",x"11",x"44", -- 0x04B8 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x04C0 + x"AA",x"FF",x"BB",x"CC",x"88",x"55",x"11",x"66", -- 0x04C8 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x04D0 + x"22",x"77",x"99",x"CC",x"88",x"DD",x"33",x"66", -- 0x04D8 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x04E0 + x"22",x"55",x"11",x"CC",x"88",x"FF",x"BB",x"66", -- 0x04E8 + x"00",x"88",x"88",x"00",x"00",x"88",x"88",x"00", -- 0x04F0 + x"00",x"55",x"11",x"44",x"AA",x"FF",x"BB",x"EE", -- 0x04F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 + x"00",x"AA",x"EE",x"EE",x"AA",x"AA",x"EE",x"EE", -- 0x0508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 + x"44",x"AA",x"AA",x"EE",x"EE",x"AA",x"AA",x"EE", -- 0x0518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"44",x"EE",x"AA",x"AA",x"EE",x"EE",x"AA",x"AA", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"00",x"EE",x"EE",x"AA",x"AA",x"EE",x"EE",x"AA", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 + x"00",x"AA",x"EE",x"EE",x"AA",x"AA",x"EE",x"EE", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"44",x"AA",x"AA",x"EE",x"EE",x"AA",x"AA",x"EE", -- 0x0558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 + x"44",x"EE",x"AA",x"AA",x"EE",x"EE",x"AA",x"AA", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"00",x"EE",x"EE",x"AA",x"AA",x"EE",x"EE",x"AA", -- 0x0578 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x0580 + x"00",x"50",x"50",x"00",x"A0",x"F0",x"F0",x"A0", -- 0x0588 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x0590 + x"80",x"50",x"50",x"20",x"20",x"F0",x"F0",x"80", -- 0x0598 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x05A0 + x"80",x"D0",x"70",x"20",x"20",x"70",x"D0",x"80", -- 0x05A8 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x05B0 + x"80",x"F0",x"F0",x"20",x"20",x"50",x"50",x"80", -- 0x05B8 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x05C0 + x"A0",x"F0",x"F0",x"A0",x"00",x"50",x"50",x"00", -- 0x05C8 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x05D0 + x"20",x"F0",x"F0",x"80",x"80",x"50",x"50",x"20", -- 0x05D8 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x05E0 + x"20",x"70",x"D0",x"80",x"80",x"D0",x"70",x"20", -- 0x05E8 + x"60",x"20",x"20",x"60",x"60",x"20",x"20",x"60", -- 0x05F0 + x"20",x"50",x"50",x"80",x"80",x"F0",x"F0",x"20", -- 0x05F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"3F", -- 0x0600 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"CF", -- 0x0608 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"3F",x"3F", -- 0x0610 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"CF",x"CF", -- 0x0618 + x"FF",x"FF",x"FF",x"FF",x"FF",x"3F",x"3F",x"3F", -- 0x0620 + x"FF",x"FF",x"FF",x"FF",x"FF",x"CF",x"CF",x"CF", -- 0x0628 + x"FF",x"FF",x"FF",x"FF",x"3F",x"3F",x"3F",x"3F", -- 0x0630 + x"FF",x"FF",x"FF",x"FF",x"CF",x"CF",x"CF",x"CF", -- 0x0638 + x"FF",x"FF",x"FF",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0640 + x"FF",x"FF",x"FF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0648 + x"FF",x"FF",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0650 + x"FF",x"FF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0658 + x"FF",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0660 + x"FF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0668 + x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0670 + x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0678 + x"0F",x"87",x"0F",x"2D",x"87",x"4B",x"87",x"0F", -- 0x0680 + x"E1",x"C3",x"B4",x"C3",x"C3",x"B4",x"C3",x"E1", -- 0x0688 + x"0F",x"4B",x"87",x"1E",x"4B",x"A5",x"4B",x"0F", -- 0x0690 + x"78",x"69",x"5A",x"69",x"69",x"5A",x"69",x"78", -- 0x0698 + x"87",x"2D",x"C3",x"0F",x"2D",x"D2",x"2D",x"87", -- 0x06A0 + x"3C",x"3C",x"2D",x"3C",x"3C",x"2D",x"3C",x"3C", -- 0x06A8 + x"C3",x"96",x"69",x"87",x"96",x"69",x"96",x"C3", -- 0x06B0 + x"1E",x"1E",x"1E",x"1E",x"1E",x"1E",x"1E",x"1E", -- 0x06B8 + x"E1",x"C3",x"B4",x"C3",x"C3",x"B4",x"C3",x"E1", -- 0x06C0 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x06C8 + x"78",x"69",x"5A",x"69",x"69",x"5A",x"69",x"78", -- 0x06D0 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x06D8 + x"3C",x"3C",x"2D",x"3C",x"3C",x"2D",x"3C",x"3C", -- 0x06E0 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x06E8 + x"1E",x"1E",x"1E",x"1E",x"1E",x"1E",x"1E",x"1E", -- 0x06F0 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x06F8 + x"88",x"88",x"88",x"EE",x"88",x"88",x"88",x"88", -- 0x0700 + x"77",x"77",x"FF",x"EE",x"EE",x"EE",x"EE",x"FF", -- 0x0708 + x"CC",x"CC",x"CC",x"77",x"44",x"44",x"44",x"CC", -- 0x0710 + x"33",x"33",x"77",x"77",x"77",x"77",x"77",x"77", -- 0x0718 + x"EE",x"EE",x"EE",x"BB",x"AA",x"AA",x"AA",x"EE", -- 0x0720 + x"11",x"11",x"33",x"33",x"33",x"33",x"33",x"33", -- 0x0728 + x"FF",x"FF",x"FF",x"DD",x"DD",x"DD",x"DD",x"FF", -- 0x0730 + x"00",x"00",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x0738 + x"77",x"77",x"FF",x"EE",x"EE",x"EE",x"EE",x"FF", -- 0x0740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 + x"33",x"33",x"77",x"77",x"77",x"77",x"77",x"77", -- 0x0750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"11",x"11",x"33",x"33",x"33",x"33",x"33",x"33", -- 0x0760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 + x"00",x"00",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x0770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"00",x"00",x"00",x"EE",x"00",x"00",x"00",x"00", -- 0x0780 + x"66",x"66",x"FF",x"DD",x"CC",x"CC",x"CC",x"EE", -- 0x0788 + x"00",x"00",x"88",x"FF",x"00",x"00",x"00",x"00", -- 0x0790 + x"33",x"33",x"77",x"66",x"66",x"66",x"66",x"77", -- 0x0798 + x"88",x"88",x"CC",x"77",x"00",x"00",x"00",x"88", -- 0x07A0 + x"11",x"11",x"33",x"33",x"33",x"33",x"33",x"33", -- 0x07A8 + x"CC",x"CC",x"EE",x"BB",x"88",x"88",x"88",x"CC", -- 0x07B0 + x"00",x"00",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x07B8 + x"66",x"66",x"FF",x"DD",x"CC",x"CC",x"CC",x"EE", -- 0x07C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 + x"33",x"33",x"77",x"66",x"66",x"66",x"66",x"77", -- 0x07D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 + x"11",x"11",x"33",x"33",x"33",x"33",x"33",x"33", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 + x"00",x"88",x"00",x"22",x"88",x"44",x"88",x"00", -- 0x0800 + x"EE",x"CC",x"BB",x"CC",x"CC",x"BB",x"CC",x"EE", -- 0x0808 + x"00",x"44",x"88",x"11",x"44",x"AA",x"44",x"00", -- 0x0810 + x"77",x"66",x"55",x"66",x"66",x"55",x"66",x"77", -- 0x0818 + x"88",x"22",x"CC",x"00",x"22",x"DD",x"22",x"88", -- 0x0820 + x"33",x"33",x"22",x"33",x"33",x"22",x"33",x"33", -- 0x0828 + x"CC",x"99",x"66",x"88",x"99",x"66",x"99",x"CC", -- 0x0830 + x"11",x"11",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x0838 + x"EE",x"CC",x"BB",x"CC",x"CC",x"BB",x"CC",x"EE", -- 0x0840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 + x"77",x"66",x"55",x"66",x"66",x"55",x"66",x"77", -- 0x0850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 + x"33",x"33",x"22",x"33",x"33",x"22",x"33",x"33", -- 0x0860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 + x"11",x"11",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x0870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 + x"F0",x"78",x"F0",x"D2",x"78",x"B4",x"78",x"F0", -- 0x0880 + x"1E",x"3C",x"4B",x"3C",x"3C",x"4B",x"3C",x"1E", -- 0x0888 + x"F0",x"B4",x"78",x"E1",x"B4",x"5A",x"B4",x"F0", -- 0x0890 + x"87",x"96",x"A5",x"96",x"96",x"A5",x"96",x"87", -- 0x0898 + x"78",x"D2",x"3C",x"F0",x"D2",x"2D",x"D2",x"78", -- 0x08A0 + x"C3",x"C3",x"D2",x"C3",x"C3",x"D2",x"C3",x"C3", -- 0x08A8 + x"3C",x"69",x"96",x"78",x"69",x"96",x"69",x"3C", -- 0x08B0 + x"E1",x"E1",x"E1",x"E1",x"E1",x"E1",x"E1",x"E1", -- 0x08B8 + x"1E",x"3C",x"4B",x"3C",x"3C",x"4B",x"3C",x"1E", -- 0x08C0 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x08C8 + x"87",x"96",x"A5",x"96",x"96",x"A5",x"96",x"87", -- 0x08D0 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x08D8 + x"C3",x"C3",x"D2",x"C3",x"C3",x"D2",x"C3",x"C3", -- 0x08E0 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x08E8 + x"E1",x"E1",x"E1",x"E1",x"E1",x"E1",x"E1",x"E1", -- 0x08F0 + x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x08F8 + x"AA",x"55",x"AA",x"55",x"AA",x"55",x"AA",x"55", -- 0x0900 + x"AA",x"DD",x"AA",x"DD",x"AA",x"DD",x"AA",x"DD", -- 0x0908 + x"55",x"AA",x"55",x"AA",x"55",x"AA",x"55",x"AA", -- 0x0910 + x"55",x"66",x"55",x"66",x"55",x"66",x"55",x"66", -- 0x0918 + x"AA",x"55",x"AA",x"55",x"AA",x"55",x"AA",x"55", -- 0x0920 + x"22",x"33",x"22",x"33",x"22",x"33",x"22",x"33", -- 0x0928 + x"55",x"AA",x"55",x"AA",x"55",x"AA",x"55",x"AA", -- 0x0930 + x"11",x"11",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x0938 + x"AA",x"DD",x"AA",x"DD",x"AA",x"DD",x"AA",x"DD", -- 0x0940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 + x"55",x"66",x"55",x"66",x"55",x"66",x"55",x"66", -- 0x0950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 + x"22",x"33",x"22",x"33",x"22",x"33",x"22",x"33", -- 0x0960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 + x"11",x"11",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x0970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 + x"00",x"AA",x"00",x"66",x"44",x"22",x"AA",x"22", -- 0x0980 + x"DD",x"EE",x"EE",x"DD",x"DD",x"EE",x"EE",x"DD", -- 0x0988 + x"88",x"55",x"00",x"BB",x"AA",x"11",x"55",x"99", -- 0x0990 + x"66",x"77",x"77",x"66",x"66",x"77",x"77",x"66", -- 0x0998 + x"44",x"AA",x"88",x"55",x"55",x"88",x"AA",x"44", -- 0x09A0 + x"33",x"33",x"33",x"33",x"33",x"33",x"33",x"33", -- 0x09A8 + x"AA",x"DD",x"CC",x"AA",x"AA",x"CC",x"DD",x"AA", -- 0x09B0 + x"11",x"11",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x09B8 + x"DD",x"EE",x"EE",x"DD",x"DD",x"EE",x"EE",x"DD", -- 0x09C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 + x"66",x"77",x"77",x"66",x"66",x"77",x"77",x"66", -- 0x09D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 + x"33",x"33",x"33",x"33",x"33",x"33",x"33",x"33", -- 0x09E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 + x"11",x"11",x"11",x"11",x"11",x"11",x"11",x"11", -- 0x09F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A08 + x"FF",x"FF",x"FF",x"FF",x"5F",x"FF",x"FF",x"FF", -- 0x0A10 + x"FF",x"FF",x"FF",x"FF",x"8F",x"FF",x"FF",x"FF", -- 0x0A18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A20 + x"FF",x"FF",x"9F",x"FF",x"FF",x"9F",x"FF",x"FF", -- 0x0A28 + x"FF",x"BF",x"1F",x"BF",x"BF",x"1F",x"BF",x"FF", -- 0x0A30 + x"FF",x"DF",x"8F",x"DF",x"DF",x"8F",x"DF",x"FF", -- 0x0A38 + x"FF",x"1F",x"5F",x"0F",x"5F",x"5F",x"FF",x"FF", -- 0x0A40 + x"FF",x"DF",x"DF",x"8F",x"DF",x"CF",x"FF",x"FF", -- 0x0A48 + x"FF",x"9F",x"9F",x"FF",x"7F",x"BF",x"DF",x"FF", -- 0x0A50 + x"FF",x"BF",x"DF",x"EF",x"FF",x"9F",x"9F",x"FF", -- 0x0A58 + x"FF",x"5F",x"BF",x"5F",x"DF",x"5F",x"BF",x"FF", -- 0x0A60 + x"FF",x"FF",x"FF",x"DF",x"AF",x"DF",x"FF",x"FF", -- 0x0A68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0A70 + x"FF",x"FF",x"FF",x"BF",x"DF",x"FF",x"FF",x"FF", -- 0x0A78 + x"FF",x"FF",x"DF",x"3F",x"FF",x"FF",x"FF",x"FF", -- 0x0A80 + x"FF",x"FF",x"BF",x"CF",x"FF",x"FF",x"FF",x"FF", -- 0x0A88 + x"FF",x"FF",x"FF",x"FF",x"3F",x"DF",x"FF",x"FF", -- 0x0A90 + x"FF",x"FF",x"FF",x"FF",x"CF",x"BF",x"FF",x"FF", -- 0x0A98 + x"FF",x"7F",x"5F",x"3F",x"5F",x"7F",x"FF",x"FF", -- 0x0AA0 + x"FF",x"FF",x"DF",x"EF",x"DF",x"FF",x"FF",x"FF", -- 0x0AA8 + x"FF",x"7F",x"7F",x"1F",x"7F",x"7F",x"FF",x"FF", -- 0x0AB0 + x"FF",x"FF",x"FF",x"CF",x"FF",x"FF",x"FF",x"FF", -- 0x0AB8 + x"FF",x"FF",x"FF",x"9F",x"EF",x"FF",x"FF",x"FF", -- 0x0AC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC8 + x"FF",x"7F",x"7F",x"7F",x"7F",x"7F",x"FF",x"FF", -- 0x0AD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD8 + x"FF",x"FF",x"FF",x"9F",x"9F",x"FF",x"FF",x"FF", -- 0x0AE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE8 + x"FF",x"FF",x"FF",x"7F",x"BF",x"DF",x"FF",x"FF", -- 0x0AF0 + x"FF",x"DF",x"EF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF8 + x"FF",x"3F",x"DF",x"DF",x"5F",x"9F",x"3F",x"FF", -- 0x0B00 + x"FF",x"CF",x"9F",x"AF",x"BF",x"BF",x"CF",x"FF", -- 0x0B08 + x"FF",x"DF",x"DF",x"1F",x"DF",x"DF",x"FF",x"FF", -- 0x0B10 + x"FF",x"FF",x"FF",x"8F",x"BF",x"DF",x"FF",x"FF", -- 0x0B18 + x"FF",x"DF",x"5F",x"5F",x"5F",x"5F",x"9F",x"FF", -- 0x0B20 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"DF",x"FF", -- 0x0B28 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"BF",x"FF", -- 0x0B30 + x"FF",x"DF",x"AF",x"AF",x"BF",x"BF",x"DF",x"FF", -- 0x0B38 + x"FF",x"BF",x"BF",x"1F",x"BF",x"BF",x"3F",x"FF", -- 0x0B40 + x"FF",x"FF",x"FF",x"8F",x"DF",x"EF",x"FF",x"FF", -- 0x0B48 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"BF",x"FF", -- 0x0B50 + x"FF",x"BF",x"AF",x"AF",x"AF",x"AF",x"8F",x"FF", -- 0x0B58 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0B60 + x"FF",x"FF",x"AF",x"AF",x"AF",x"AF",x"CF",x"FF", -- 0x0B68 + x"FF",x"FF",x"FF",x"7F",x"9F",x"FF",x"FF",x"FF", -- 0x0B70 + x"FF",x"9F",x"AF",x"BF",x"BF",x"BF",x"BF",x"FF", -- 0x0B78 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0B80 + x"FF",x"DF",x"AF",x"AF",x"AF",x"AF",x"DF",x"FF", -- 0x0B88 + x"FF",x"3F",x"5F",x"5F",x"5F",x"5F",x"FF",x"FF", -- 0x0B90 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"CF",x"FF", -- 0x0B98 + x"FF",x"FF",x"FF",x"FF",x"DF",x"FF",x"FF",x"FF", -- 0x0BA0 + x"FF",x"FF",x"FF",x"FF",x"EF",x"FF",x"FF",x"FF", -- 0x0BA8 + x"FF",x"FF",x"FF",x"FF",x"9F",x"EF",x"FF",x"FF", -- 0x0BB0 + x"FF",x"FF",x"FF",x"FF",x"DF",x"FF",x"FF",x"FF", -- 0x0BB8 + x"FF",x"FF",x"DF",x"BF",x"7F",x"FF",x"FF",x"FF", -- 0x0BC0 + x"FF",x"FF",x"DF",x"EF",x"FF",x"FF",x"FF",x"FF", -- 0x0BC8 + x"FF",x"BF",x"BF",x"BF",x"BF",x"BF",x"FF",x"FF", -- 0x0BD0 + x"FF",x"EF",x"EF",x"EF",x"EF",x"EF",x"FF",x"FF", -- 0x0BD8 + x"FF",x"FF",x"7F",x"BF",x"DF",x"FF",x"FF",x"FF", -- 0x0BE0 + x"FF",x"FF",x"FF",x"EF",x"DF",x"FF",x"FF",x"FF", -- 0x0BE8 + x"FF",x"FF",x"FF",x"5F",x"FF",x"FF",x"FF",x"FF", -- 0x0BF0 + x"FF",x"DF",x"AF",x"BF",x"BF",x"BF",x"DF",x"FF", -- 0x0BF8 + x"FF",x"7F",x"5F",x"5F",x"5F",x"DF",x"3F",x"FF", -- 0x0C00 + x"FF",x"CF",x"AF",x"9F",x"AF",x"BF",x"CF",x"FF", -- 0x0C08 + x"FF",x"1F",x"7F",x"7F",x"7F",x"7F",x"1F",x"FF", -- 0x0C10 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"CF",x"FF", -- 0x0C18 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"1F",x"FF", -- 0x0C20 + x"FF",x"DF",x"AF",x"AF",x"AF",x"AF",x"8F",x"FF", -- 0x0C28 + x"FF",x"BF",x"DF",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0C30 + x"FF",x"DF",x"BF",x"BF",x"BF",x"BF",x"CF",x"FF", -- 0x0C38 + x"FF",x"7F",x"BF",x"DF",x"DF",x"DF",x"1F",x"FF", -- 0x0C40 + x"FF",x"EF",x"DF",x"BF",x"BF",x"BF",x"8F",x"FF", -- 0x0C48 + x"FF",x"DF",x"DF",x"DF",x"DF",x"DF",x"1F",x"FF", -- 0x0C50 + x"FF",x"BF",x"AF",x"AF",x"AF",x"AF",x"8F",x"FF", -- 0x0C58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"1F",x"FF", -- 0x0C60 + x"FF",x"BF",x"AF",x"AF",x"AF",x"AF",x"8F",x"FF", -- 0x0C68 + x"FF",x"3F",x"5F",x"5F",x"DF",x"DF",x"3F",x"FF", -- 0x0C70 + x"FF",x"DF",x"BF",x"BF",x"BF",x"BF",x"CF",x"FF", -- 0x0C78 + x"FF",x"1F",x"FF",x"FF",x"FF",x"FF",x"1F",x"FF", -- 0x0C80 + x"FF",x"8F",x"EF",x"EF",x"EF",x"EF",x"8F",x"FF", -- 0x0C88 + x"FF",x"DF",x"DF",x"1F",x"DF",x"DF",x"FF",x"FF", -- 0x0C90 + x"FF",x"BF",x"BF",x"8F",x"BF",x"BF",x"FF",x"FF", -- 0x0C98 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0CA0 + x"FF",x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0CA8 + x"FF",x"DF",x"BF",x"7F",x"FF",x"FF",x"1F",x"FF", -- 0x0CB0 + x"FF",x"FF",x"BF",x"DF",x"EF",x"EF",x"8F",x"FF", -- 0x0CB8 + x"FF",x"DF",x"DF",x"DF",x"DF",x"DF",x"1F",x"FF", -- 0x0CC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F",x"FF", -- 0x0CC8 + x"FF",x"1F",x"FF",x"FF",x"FF",x"FF",x"1F",x"FF", -- 0x0CD0 + x"FF",x"8F",x"DF",x"EF",x"EF",x"DF",x"8F",x"FF", -- 0x0CD8 + x"FF",x"1F",x"BF",x"7F",x"FF",x"FF",x"1F",x"FF", -- 0x0CE0 + x"FF",x"8F",x"FF",x"FF",x"EF",x"DF",x"8F",x"FF", -- 0x0CE8 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0CF0 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"CF",x"FF", -- 0x0CF8 + x"FF",x"FF",x"7F",x"7F",x"7F",x"7F",x"1F",x"FF", -- 0x0D00 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"8F",x"FF", -- 0x0D08 + x"FF",x"3F",x"DF",x"9F",x"5F",x"DF",x"3F",x"FF", -- 0x0D10 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"CF",x"FF", -- 0x0D18 + x"FF",x"DF",x"3F",x"7F",x"7F",x"7F",x"1F",x"FF", -- 0x0D20 + x"FF",x"CF",x"BF",x"BF",x"BF",x"BF",x"8F",x"FF", -- 0x0D28 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"BF",x"FF", -- 0x0D30 + x"FF",x"FF",x"AF",x"AF",x"AF",x"AF",x"DF",x"FF", -- 0x0D38 + x"FF",x"FF",x"FF",x"FF",x"1F",x"FF",x"FF",x"FF", -- 0x0D40 + x"FF",x"BF",x"BF",x"BF",x"8F",x"BF",x"BF",x"BF", -- 0x0D48 + x"FF",x"3F",x"DF",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0D50 + x"FF",x"8F",x"FF",x"FF",x"FF",x"FF",x"8F",x"FF", -- 0x0D58 + x"FF",x"7F",x"BF",x"DF",x"DF",x"BF",x"7F",x"FF", -- 0x0D60 + x"FF",x"8F",x"FF",x"FF",x"FF",x"FF",x"8F",x"FF", -- 0x0D68 + x"FF",x"3F",x"DF",x"BF",x"BF",x"DF",x"3F",x"FF", -- 0x0D70 + x"FF",x"8F",x"FF",x"FF",x"FF",x"FF",x"8F",x"FF", -- 0x0D78 + x"FF",x"DF",x"BF",x"7F",x"7F",x"BF",x"DF",x"FF", -- 0x0D80 + x"FF",x"BF",x"DF",x"EF",x"EF",x"DF",x"BF",x"FF", -- 0x0D88 + x"FF",x"FF",x"FF",x"FF",x"1F",x"FF",x"FF",x"FF", -- 0x0D90 + x"FF",x"BF",x"DF",x"EF",x"FF",x"EF",x"DF",x"BF", -- 0x0D98 + x"FF",x"DF",x"DF",x"DF",x"5F",x"9F",x"DF",x"FF", -- 0x0DA0 + x"FF",x"BF",x"9F",x"AF",x"BF",x"BF",x"BF",x"FF", -- 0x0DA8 + x"00",x"08",x"0D",x"0F",x"0F",x"0D",x"00",x"00", -- 0x0DB0 + x"00",x"0C",x"0F",x"06",x"07",x"07",x"02",x"00", -- 0x0DB8 + x"FF",x"FF",x"DF",x"BF",x"7F",x"FF",x"FF",x"FF", -- 0x0DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"EF",x"DF",x"FF", -- 0x0DC8 + x"FF",x"FF",x"FF",x"FF",x"1F",x"DF",x"DF",x"FF", -- 0x0DD0 + x"FF",x"FF",x"FF",x"FF",x"8F",x"BF",x"BF",x"FF", -- 0x0DD8 + x"2F",x"FF",x"6F",x"2F",x"FF",x"6F",x"2F",x"FF", -- 0x0DE0 + x"9F",x"FF",x"BF",x"9F",x"FF",x"BF",x"9F",x"FF", -- 0x0DE8 + x"FF",x"6F",x"2F",x"FF",x"6F",x"2F",x"FF",x"6F", -- 0x0DF0 + x"FF",x"BF",x"9F",x"FF",x"BF",x"9F",x"FF",x"BF", -- 0x0DF8 + x"FF",x"DF",x"DF",x"DF",x"DF",x"1F",x"DF",x"FF", -- 0x0E00 + x"FF",x"DF",x"BF",x"AF",x"AF",x"CF",x"EF",x"FF", -- 0x0E08 + x"FF",x"FF",x"1F",x"5F",x"5F",x"5F",x"BF",x"FF", -- 0x0E10 + x"FF",x"FF",x"EF",x"DF",x"DF",x"DF",x"FF",x"FF", -- 0x0E18 + x"FF",x"3F",x"DF",x"DF",x"DF",x"1F",x"FF",x"FF", -- 0x0E20 + x"FF",x"FF",x"EF",x"EF",x"EF",x"8F",x"FF",x"FF", -- 0x0E28 + x"FF",x"FF",x"DF",x"DF",x"DF",x"3F",x"FF",x"FF", -- 0x0E30 + x"FF",x"FF",x"DF",x"DF",x"DF",x"EF",x"FF",x"FF", -- 0x0E38 + x"FF",x"FF",x"1F",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0E40 + x"FF",x"FF",x"8F",x"EF",x"EF",x"EF",x"FF",x"FF", -- 0x0E48 + x"FF",x"FF",x"DF",x"5F",x"5F",x"5F",x"3F",x"FF", -- 0x0E50 + x"FF",x"FF",x"EF",x"DF",x"DF",x"DF",x"EF",x"FF", -- 0x0E58 + x"FF",x"FF",x"FF",x"FF",x"1F",x"FF",x"FF",x"FF", -- 0x0E60 + x"FF",x"FF",x"BF",x"AF",x"CF",x"FF",x"FF",x"FF", -- 0x0E68 + x"FF",x"FF",x"1F",x"AF",x"AF",x"AF",x"7F",x"FF", -- 0x0E70 + x"FF",x"FF",x"CF",x"DF",x"DF",x"DF",x"EF",x"FF", -- 0x0E78 + x"FF",x"FF",x"1F",x"FF",x"FF",x"FF",x"1F",x"FF", -- 0x0E80 + x"FF",x"FF",x"FF",x"EF",x"EF",x"EF",x"8F",x"FF", -- 0x0E88 + x"FF",x"FF",x"FF",x"DF",x"1F",x"DF",x"FF",x"FF", -- 0x0E90 + x"FF",x"FF",x"FF",x"FF",x"AF",x"EF",x"FF",x"FF", -- 0x0E98 + x"FF",x"FF",x"1F",x"EF",x"EF",x"DF",x"FF",x"FF", -- 0x0EA0 + x"FF",x"FF",x"AF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EA8 + x"FF",x"FF",x"DF",x"BF",x"7F",x"1F",x"FF",x"FF", -- 0x0EB0 + x"FF",x"FF",x"FF",x"DF",x"EF",x"8F",x"FF",x"FF", -- 0x0EB8 + x"FF",x"FF",x"DF",x"DF",x"3F",x"FF",x"FF",x"FF", -- 0x0EC0 + x"FF",x"FF",x"FF",x"FF",x"8F",x"FF",x"FF",x"FF", -- 0x0EC8 + x"FF",x"FF",x"1F",x"FF",x"1F",x"FF",x"1F",x"FF", -- 0x0ED0 + x"FF",x"FF",x"EF",x"DF",x"EF",x"DF",x"CF",x"FF", -- 0x0ED8 + x"FF",x"FF",x"1F",x"FF",x"FF",x"FF",x"1F",x"FF", -- 0x0EE0 + x"FF",x"FF",x"EF",x"DF",x"DF",x"DF",x"CF",x"FF", -- 0x0EE8 + x"FF",x"FF",x"3F",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0EF0 + x"FF",x"FF",x"EF",x"DF",x"DF",x"DF",x"EF",x"FF", -- 0x0EF8 + x"FF",x"FF",x"7F",x"BF",x"BF",x"BF",x"0F",x"FF", -- 0x0F00 + x"FF",x"FF",x"EF",x"DF",x"DF",x"DF",x"CF",x"FF", -- 0x0F08 + x"FF",x"EF",x"0F",x"BF",x"BF",x"BF",x"7F",x"FF", -- 0x0F10 + x"FF",x"FF",x"CF",x"DF",x"DF",x"DF",x"EF",x"FF", -- 0x0F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"1F",x"FF",x"FF", -- 0x0F20 + x"FF",x"FF",x"DF",x"DF",x"DF",x"EF",x"FF",x"FF", -- 0x0F28 + x"FF",x"FF",x"BF",x"5F",x"5F",x"5F",x"DF",x"FF", -- 0x0F30 + x"FF",x"FF",x"FF",x"DF",x"DF",x"DF",x"EF",x"FF", -- 0x0F38 + x"FF",x"FF",x"DF",x"DF",x"3F",x"FF",x"FF",x"FF", -- 0x0F40 + x"FF",x"FF",x"FF",x"DF",x"8F",x"DF",x"FF",x"FF", -- 0x0F48 + x"FF",x"FF",x"3F",x"DF",x"DF",x"DF",x"3F",x"FF", -- 0x0F50 + x"FF",x"FF",x"CF",x"FF",x"FF",x"FF",x"CF",x"FF", -- 0x0F58 + x"FF",x"FF",x"FF",x"3F",x"DF",x"3F",x"FF",x"FF", -- 0x0F60 + x"FF",x"FF",x"CF",x"FF",x"FF",x"FF",x"CF",x"FF", -- 0x0F68 + x"FF",x"FF",x"3F",x"DF",x"3F",x"DF",x"3F",x"FF", -- 0x0F70 + x"FF",x"FF",x"CF",x"FF",x"EF",x"FF",x"CF",x"FF", -- 0x0F78 + x"FF",x"FF",x"DF",x"BF",x"7F",x"BF",x"DF",x"FF", -- 0x0F80 + x"FF",x"FF",x"DF",x"EF",x"FF",x"EF",x"DF",x"FF", -- 0x0F88 + x"FF",x"FF",x"1F",x"AF",x"AF",x"AF",x"7F",x"FF", -- 0x0F90 + x"FF",x"FF",x"CF",x"FF",x"FF",x"FF",x"CF",x"FF", -- 0x0F98 + x"FF",x"FF",x"DF",x"DF",x"5F",x"9F",x"DF",x"FF", -- 0x0FA0 + x"FF",x"FF",x"DF",x"CF",x"DF",x"DF",x"DF",x"FF", -- 0x0FA8 + x"01",x"07",x"0F",x"0A",x"0D",x"0F",x"07",x"00", -- 0x0FB0 + x"03",x"0F",x"0E",x"0D",x"0F",x"0F",x"0F",x"03", -- 0x0FB8 + x"FF",x"FF",x"FF",x"1F",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0 + x"FF",x"FF",x"FF",x"8F",x"FF",x"FF",x"FF",x"FF", -- 0x0FC8 + x"3F",x"DF",x"EF",x"AF",x"AF",x"6F",x"DF",x"3F", -- 0x0FD0 + x"CF",x"BF",x"7F",x"5F",x"5F",x"6F",x"BF",x"CF", -- 0x0FD8 + x"9F",x"FF",x"BF",x"9F",x"FF",x"BF",x"9F",x"FF", -- 0x0FE0 + x"4F",x"FF",x"DF",x"4F",x"FF",x"DF",x"4F",x"FF", -- 0x0FE8 + x"FF",x"BF",x"9F",x"FF",x"BF",x"9F",x"FF",x"BF", -- 0x0FF0 + x"FF",x"DF",x"4F",x"FF",x"DF",x"4F",x"FF",x"DF", -- 0x0FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1018 + x"01",x"07",x"0F",x"0A",x"0D",x"0F",x"07",x"00", -- 0x1020 + x"00",x"0C",x"0F",x"06",x"07",x"07",x"02",x"00", -- 0x1028 + x"00",x"08",x"0D",x"0F",x"0F",x"0D",x"00",x"00", -- 0x1030 + x"03",x"0F",x"0E",x"0D",x"0F",x"0F",x"0F",x"03", -- 0x1038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0C", -- 0x1048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"08", -- 0x1050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0F", -- 0x1058 + x"09",x"0F",x"0F",x"08",x"00",x"00",x"00",x"00", -- 0x1060 + x"0F",x"06",x"07",x"07",x"02",x"00",x"00",x"00", -- 0x1068 + x"0D",x"0F",x"0F",x"0D",x"00",x"00",x"00",x"00", -- 0x1070 + x"0F",x"0E",x"01",x"0F",x"0F",x"00",x"00",x"00", -- 0x1078 + x"00",x"00",x"00",x"00",x"01",x"07",x"0F",x"0A", -- 0x1080 + x"00",x"00",x"00",x"00",x"00",x"0C",x"0F",x"06", -- 0x1088 + x"00",x"00",x"00",x"00",x"00",x"08",x"0D",x"0F", -- 0x1090 + x"00",x"00",x"00",x"00",x"03",x"0F",x"0E",x"0D", -- 0x1098 + x"0D",x"0F",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x10A0 + x"07",x"07",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x10A8 + x"0F",x"0D",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10B0 + x"0F",x"0F",x"0F",x"03",x"00",x"00",x"00",x"00", -- 0x10B8 + x"00",x"06",x"03",x"0E",x"0C",x"08",x"0C",x"0D", -- 0x10C0 + x"00",x"00",x"00",x"0C",x"0F",x"06",x"07",x"07", -- 0x10C8 + x"00",x"00",x"00",x"08",x"0D",x"0F",x"0F",x"0D", -- 0x10D0 + x"00",x"03",x"07",x"0E",x"0F",x"0F",x"0F",x"0F", -- 0x10D8 + x"07",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10E0 + x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x10F0 + x"0E",x"07",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x10F8 + x"08",x"04",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x1100 + x"05",x"05",x"03",x"01",x"01",x"0B",x"07",x"0B", -- 0x1108 + x"05",x"05",x"06",x"0C",x"0C",x"0E",x"0B",x"0B", -- 0x1110 + x"00",x"01",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x1118 + x"0F",x"04",x"04",x"06",x"0E",x"06",x"0C",x"00", -- 0x1120 + x"07",x"0B",x"06",x"02",x"03",x"01",x"01",x"00", -- 0x1128 + x"07",x"0F",x"07",x"07",x"0F",x"0B",x"0A",x"0A", -- 0x1130 + x"07",x"01",x"01",x"03",x"02",x"03",x"01",x"00", -- 0x1138 + x"00",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x1140 + x"0B",x"0C",x"0D",x"0C",x"0B",x"08",x"0F",x"08", -- 0x1148 + x"00",x"08",x"03",x"04",x"09",x"00",x"0F",x"00", -- 0x1150 + x"00",x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00", -- 0x1158 + x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00",x"00", -- 0x1160 + x"08",x"0F",x"08",x"0B",x"0C",x"0D",x"0C",x"0B", -- 0x1168 + x"00",x"0F",x"00",x"09",x"04",x"03",x"08",x"00", -- 0x1170 + x"00",x"0F",x"00",x"0F",x"00",x"0F",x"00",x"00", -- 0x1178 + x"01",x"0F",x"E1",x"E1",x"E1",x"E1",x"69",x"E1", -- 0x1180 + x"00",x"00",x"00",x"00",x"00",x"00",x"0E",x"4A", -- 0x1188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"07", -- 0x1190 + x"00",x"00",x"01",x"12",x"12",x"03",x"34",x"5A", -- 0x1198 + x"E1",x"E1",x"0F",x"E1",x"E1",x"E1",x"0F",x"01", -- 0x11A0 + x"87",x"5A",x"96",x"4B",x"86",x"0E",x"00",x"00", -- 0x11A8 + x"3C",x"B4",x"B4",x"3C",x"07",x"00",x"00",x"00", -- 0x11B0 + x"69",x"B4",x"F0",x"E1",x"69",x"16",x"01",x"00", -- 0x11B8 + x"00",x"08",x"00",x"00",x"01",x"09",x"0F",x"08", -- 0x11C0 + x"00",x"00",x"00",x"03",x"07",x"07",x"0F",x"0F", -- 0x11C8 + x"01",x"02",x"0B",x"08",x"07",x"07",x"07",x"0A", -- 0x11D0 + x"0F",x"00",x"08",x"0E",x"07",x"05",x"06",x"0E", -- 0x11D8 + x"08",x"0F",x"09",x"01",x"00",x"00",x"08",x"00", -- 0x11E0 + x"0F",x"0F",x"07",x"07",x"03",x"00",x"00",x"00", -- 0x11E8 + x"0A",x"07",x"07",x"07",x"08",x"0B",x"02",x"01", -- 0x11F0 + x"0E",x"06",x"05",x"07",x"0E",x"08",x"00",x"0F", -- 0x11F8 + x"00",x"00",x"00",x"00",x"00",x"08",x"04",x"0E", -- 0x1200 + x"00",x"00",x"00",x"00",x"00",x"0F",x"06",x"06", -- 0x1208 + x"00",x"00",x"00",x"00",x"00",x"00",x"02",x"06", -- 0x1210 + x"00",x"00",x"00",x"00",x"00",x"00",x"08",x"0C", -- 0x1218 + x"0D",x"08",x"00",x"08",x"0D",x"0E",x"04",x"08", -- 0x1220 + x"0F",x"09",x"09",x"0F",x"0E",x"04",x"00",x"00", -- 0x1228 + x"0E",x"0F",x"0F",x"0F",x"0F",x"02",x"07",x"0A", -- 0x1230 + x"0D",x"0F",x"0F",x"0F",x"0D",x"00",x"00",x"08", -- 0x1238 + x"00",x"00",x"00",x"00",x"02",x"02",x"0F",x"0D", -- 0x1240 + x"00",x"00",x"0F",x"06",x"06",x"06",x"0F",x"09", -- 0x1248 + x"00",x"00",x"00",x"00",x"03",x"07",x"0F",x"0F", -- 0x1250 + x"00",x"00",x"00",x"00",x"08",x"0C",x"0C",x"0F", -- 0x1258 + x"00",x"0D",x"0F",x"02",x"02",x"00",x"00",x"00", -- 0x1260 + x"09",x"0F",x"0E",x"04",x"00",x"01",x"00",x"00", -- 0x1268 + x"0F",x"0F",x"0F",x"02",x"0F",x"02",x"00",x"00", -- 0x1270 + x"0F",x"0F",x"0C",x"00",x"08",x"04",x"00",x"00", -- 0x1278 + x"00",x"00",x"00",x"00",x"01",x"0F",x"09",x"00", -- 0x1280 + x"00",x"0F",x"06",x"06",x"0F",x"09",x"09",x"0F", -- 0x1288 + x"00",x"00",x"02",x"06",x"0E",x"0F",x"0F",x"0F", -- 0x1290 + x"00",x"00",x"08",x"0C",x"0C",x"0F",x"0D",x"09", -- 0x1298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x12A0 + x"0E",x"04",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x12A8 + x"0F",x"02",x"07",x"0A",x"00",x"00",x"00",x"00", -- 0x12B0 + x"04",x"00",x"00",x"08",x"00",x"00",x"00",x"00", -- 0x12B8 + x"02",x"02",x"0F",x"0D",x"00",x"00",x"06",x"00", -- 0x12C0 + x"0F",x"06",x"0F",x"09",x"09",x"0F",x"0E",x"04", -- 0x12C8 + x"04",x"04",x"0E",x"0F",x"0F",x"0F",x"0F",x"02", -- 0x12D0 + x"04",x"04",x"0C",x"0F",x"0D",x"09",x"04",x"00", -- 0x12D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x12E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x12E8 + x"02",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x12F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x12F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1300 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x1308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1318 + x"08",x"05",x"05",x"07",x"0D",x"0C",x"08",x"04", -- 0x1320 + x"02",x"07",x"0D",x"0F",x"07",x"00",x"00",x"00", -- 0x1328 + x"09",x"06",x"01",x"0B",x"0F",x"0F",x"00",x"00", -- 0x1330 + x"0F",x"00",x"08",x"0E",x"00",x"0F",x"0F",x"00", -- 0x1338 + x"00",x"00",x"00",x"00",x"00",x"00",x"0A",x"05", -- 0x1340 + x"00",x"00",x"00",x"00",x"01",x"01",x"02",x"07", -- 0x1348 + x"00",x"00",x"00",x"00",x"00",x"00",x"09",x"07", -- 0x1350 + x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"00", -- 0x1358 + x"07",x"05",x"0F",x"0D",x"08",x"04",x"00",x"00", -- 0x1360 + x"0D",x"0F",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x1368 + x"03",x"0A",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x1370 + x"0C",x"0E",x"02",x"0D",x"0F",x"00",x"00",x"00", -- 0x1378 + x"00",x"00",x"00",x"04",x"0A",x"05",x"07",x"05", -- 0x1380 + x"00",x"00",x"01",x"01",x"02",x"07",x"0D",x"0F", -- 0x1388 + x"00",x"00",x"00",x"00",x"09",x"06",x"01",x"0B", -- 0x1390 + x"00",x"00",x"00",x"00",x"0F",x"00",x"08",x"0E", -- 0x1398 + x"0D",x"0F",x"09",x"04",x"00",x"00",x"00",x"00", -- 0x13A0 + x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13A8 + x"0F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13B0 + x"00",x"0F",x"0F",x"00",x"00",x"00",x"00",x"00", -- 0x13B8 + x"00",x"00",x"0A",x"05",x"07",x"05",x"0F",x"0D", -- 0x13C0 + x"01",x"01",x"02",x"07",x"0D",x"0F",x"07",x"00", -- 0x13C8 + x"00",x"00",x"09",x"06",x"01",x"0B",x"0F",x"0F", -- 0x13D0 + x"00",x"00",x"0F",x"00",x"0E",x"08",x"00",x"0F", -- 0x13D8 + x"08",x"04",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13F0 + x"0F",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x13F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1400 + x"00",x"00",x"00",x"00",x"00",x"00",x"02",x"06", -- 0x1408 + x"00",x"00",x"00",x"00",x"00",x"00",x"06",x"0F", -- 0x1410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1418 + x"00",x"00",x"01",x"0E",x"01",x"00",x"00",x"00", -- 0x1420 + x"0B",x"0F",x"06",x"00",x"00",x"00",x"00",x"00", -- 0x1428 + x"09",x"03",x"02",x"02",x"02",x"03",x"01",x"03", -- 0x1430 + x"0E",x"07",x"03",x"07",x"03",x"07",x"0A",x"04", -- 0x1438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1440 + x"00",x"00",x"00",x"00",x"02",x"06",x"0B",x"0F", -- 0x1448 + x"00",x"00",x"00",x"00",x"06",x"0F",x"09",x"03", -- 0x1450 + x"00",x"00",x"00",x"00",x"00",x"00",x"0E",x"0F", -- 0x1458 + x"0A",x"04",x"0A",x"00",x"08",x"00",x"00",x"00", -- 0x1460 + x"06",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1468 + x"02",x"02",x"02",x"03",x"01",x"03",x"00",x"00", -- 0x1470 + x"02",x"01",x"02",x"09",x"0E",x"04",x"00",x"00", -- 0x1478 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"08", -- 0x1480 + x"00",x"00",x"02",x"06",x"0B",x"0F",x"06",x"00", -- 0x1488 + x"00",x"00",x"06",x"0F",x"09",x"03",x"02",x"02", -- 0x1490 + x"00",x"00",x"00",x"00",x"0E",x"07",x"03",x"07", -- 0x1498 + x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x14A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x14A8 + x"02",x"03",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x14B0 + x"03",x"07",x"0A",x"04",x"00",x"00",x"00",x"00", -- 0x14B8 + x"00",x"00",x"00",x"00",x"02",x"0C",x"02",x"00", -- 0x14C0 + x"02",x"06",x"0B",x"0F",x"06",x"01",x"00",x"00", -- 0x14C8 + x"06",x"0F",x"09",x"06",x"0A",x"04",x"0A",x"05", -- 0x14D0 + x"00",x"00",x"0E",x"0F",x"07",x"07",x"07",x"07", -- 0x14D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x14E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x14E8 + x"01",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x14F0 + x"0E",x"04",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x14F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"0E", -- 0x1500 + x"00",x"00",x"00",x"00",x"00",x"00",x"03",x"07", -- 0x1508 + x"00",x"00",x"00",x"00",x"00",x"00",x"08",x"0C", -- 0x1510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x1518 + x"0C",x"0E",x"0F",x"0F",x"07",x"03",x"0E",x"02", -- 0x1520 + x"0F",x"0F",x"08",x"04",x"03",x"00",x"00",x"00", -- 0x1528 + x"0F",x"0E",x"02",x"04",x"08",x"00",x"00",x"00", -- 0x1530 + x"0F",x"0B",x"0F",x"00",x"00",x"00",x"00",x"00", -- 0x1538 + x"00",x"00",x"00",x"00",x"07",x"0E",x"0C",x"0E", -- 0x1540 + x"00",x"00",x"00",x"00",x"03",x"04",x"0F",x"0F", -- 0x1548 + x"00",x"00",x"00",x"00",x"08",x"04",x"0F",x"0E", -- 0x1550 + x"00",x"00",x"00",x"00",x"00",x"01",x"0F",x"0B", -- 0x1558 + x"0F",x"0F",x"07",x"07",x"03",x"0E",x"02",x"00", -- 0x1560 + x"0B",x"04",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x1568 + x"0A",x"04",x"08",x"00",x"00",x"00",x"00",x"00", -- 0x1570 + x"0F",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1578 + x"00",x"00",x"07",x"0E",x"0C",x"0E",x"0F",x"0F", -- 0x1580 + x"00",x"00",x"03",x"04",x"08",x"0F",x"0F",x"07", -- 0x1588 + x"00",x"00",x"08",x"04",x"03",x"0E",x"0E",x"0C", -- 0x1590 + x"00",x"00",x"00",x"01",x"0F",x"0B",x"0F",x"01", -- 0x1598 + x"0F",x"07",x"07",x"03",x"02",x"0E",x"02",x"00", -- 0x15A0 + x"03",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x15A8 + x"08",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x15B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x15B8 + x"07",x"0E",x"0C",x"0E",x"0F",x"0F",x"07",x"07", -- 0x15C0 + x"03",x"07",x"0C",x"08",x"0C",x"07",x"03",x"00", -- 0x15C8 + x"08",x"0C",x"07",x"02",x"06",x"0C",x"08",x"00", -- 0x15D0 + x"00",x"01",x"0F",x"0B",x"0F",x"00",x"00",x"00", -- 0x15D8 + x"03",x"03",x"0E",x"02",x"00",x"00",x"00",x"00", -- 0x15E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x15E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x15F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x15F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"08", -- 0x1600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1608 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x1610 + x"00",x"00",x"00",x"00",x"00",x"00",x"0E",x"0F", -- 0x1618 + x"0F",x"0F",x"0F",x"07",x"0F",x"0C",x"0F",x"07", -- 0x1620 + x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"0F", -- 0x1628 + x"01",x"01",x"01",x"01",x"01",x"00",x"0F",x"0F", -- 0x1630 + x"0F",x"0F",x"0F",x"0F",x"0E",x"04",x"0C",x"0C", -- 0x1638 + x"00",x"00",x"00",x"00",x"00",x"08",x"0F",x"0F", -- 0x1640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1648 + x"00",x"00",x"00",x"00",x"00",x"08",x"04",x"04", -- 0x1650 + x"00",x"00",x"00",x"00",x"0E",x"0F",x"0F",x"0F", -- 0x1658 + x"0F",x"07",x"0F",x"0C",x"0F",x"07",x"00",x"00", -- 0x1660 + x"00",x"00",x"00",x"00",x"0F",x"0F",x"00",x"00", -- 0x1668 + x"02",x"02",x"01",x"00",x"0F",x"0F",x"00",x"00", -- 0x1670 + x"0F",x"0F",x"0E",x"04",x"0C",x"0C",x"00",x"00", -- 0x1678 + x"00",x"00",x"00",x"08",x"0F",x"0F",x"0F",x"07", -- 0x1680 + x"00",x"00",x"00",x"00",x"00",x"02",x"01",x"00", -- 0x1688 + x"00",x"00",x"00",x"00",x"00",x"00",x"08",x"06", -- 0x1690 + x"00",x"00",x"0E",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x1698 + x"0F",x"0C",x"0F",x"07",x"00",x"00",x"00",x"00", -- 0x16A0 + x"00",x"00",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x16A8 + x"01",x"00",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x16B0 + x"0E",x"04",x"0C",x"0C",x"00",x"00",x"00",x"00", -- 0x16B8 + x"00",x"08",x"0F",x"0F",x"0F",x"07",x"0F",x"0C", -- 0x16C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x16C8 + x"00",x"08",x"04",x"04",x"02",x"02",x"01",x"00", -- 0x16D0 + x"0E",x"0F",x"0F",x"0F",x"0F",x"0F",x"0E",x"04", -- 0x16D8 + x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x16E0 + x"0F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x16E8 + x"0F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x16F0 + x"0C",x"0C",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x16F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1700 + x"00",x"00",x"00",x"00",x"00",x"02",x"06",x"07", -- 0x1708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x1710 + x"00",x"00",x"00",x"00",x"00",x"08",x"0C",x"0C", -- 0x1718 + x"01",x"0F",x"01",x"0F",x"01",x"00",x"00",x"00", -- 0x1720 + x"0F",x"0F",x"0C",x"0C",x"0F",x"07",x"07",x"01", -- 0x1728 + x"01",x"0B",x"0B",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x1730 + x"0E",x"0F",x"0E",x"0F",x"0E",x"0C",x"0C",x"00", -- 0x1738 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"0C", -- 0x1740 + x"00",x"00",x"00",x"01",x"07",x"07",x"0F",x"0C", -- 0x1748 + x"00",x"00",x"00",x"0B",x"0B",x"0B",x"0B",x"0B", -- 0x1750 + x"00",x"00",x"00",x"00",x"0C",x"0C",x"0E",x"0F", -- 0x1758 + x"04",x"0C",x"04",x"00",x"00",x"00",x"00",x"00", -- 0x1760 + x"0C",x"0F",x"0F",x"07",x"07",x"01",x"00",x"00", -- 0x1768 + x"0B",x"0F",x"0F",x"0F",x"0F",x"0F",x"00",x"00", -- 0x1770 + x"0E",x"0F",x"0E",x"0C",x"0C",x"00",x"00",x"00", -- 0x1778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1780 + x"00",x"02",x"06",x"07",x"0F",x"0F",x"0C",x"0C", -- 0x1788 + x"00",x"00",x"00",x"01",x"01",x"0B",x"0B",x"0F", -- 0x1790 + x"00",x"08",x"0C",x"0C",x"0F",x"0F",x"0F",x"0F", -- 0x1798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x17A0 + x"0F",x"07",x"07",x"01",x"00",x"00",x"00",x"00", -- 0x17A8 + x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x17B0 + x"0F",x"0C",x"0C",x"00",x"00",x"00",x"00",x"00", -- 0x17B8 + x"00",x"00",x"04",x"0C",x"04",x"0C",x"04",x"00", -- 0x17C0 + x"04",x"06",x"0F",x"0F",x"09",x"09",x"0F",x"07", -- 0x17C8 + x"00",x"00",x"01",x"01",x"0B",x"0F",x"0F",x"0F", -- 0x17D0 + x"04",x"0C",x"0E",x"0F",x"0E",x"0F",x"0E",x"0C", -- 0x17D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x17E0 + x"07",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x17E8 + x"0F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x17F0 + x"0C",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x17F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x1808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1818 + x"02",x"04",x"08",x"00",x"00",x"00",x"0C",x"02", -- 0x1820 + x"01",x"03",x"05",x"0F",x"0C",x"00",x"00",x"00", -- 0x1828 + x"01",x"02",x"0F",x"0F",x"07",x"00",x"00",x"00", -- 0x1830 + x"00",x"07",x"0F",x"0F",x"0E",x"0F",x"01",x"00", -- 0x1838 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"0D", -- 0x1840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1848 + x"00",x"00",x"00",x"00",x"00",x"0C",x"04",x"0E", -- 0x1850 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"09", -- 0x1858 + x"0E",x"0E",x"08",x"0C",x"06",x"02",x"01",x"00", -- 0x1860 + x"01",x"03",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x1868 + x"07",x"0F",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x1870 + x"0F",x"0F",x"0F",x"03",x"00",x"00",x"00",x"00", -- 0x1878 + x"00",x"00",x"00",x"01",x"01",x"07",x"0F",x"0F", -- 0x1880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1888 + x"00",x"00",x"00",x"03",x"01",x"03",x"05",x"0F", -- 0x1890 + x"00",x"00",x"00",x"00",x"01",x"0A",x"0F",x"0F", -- 0x1898 + x"0E",x"0F",x"03",x"01",x"01",x"01",x"00",x"00", -- 0x18A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x18A8 + x"0C",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x18B0 + x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x18B8 + x"00",x"00",x"02",x"0A",x"0C",x"0C",x"08",x"0C", -- 0x18C0 + x"00",x"00",x"00",x"00",x"01",x"03",x"03",x"00", -- 0x18C8 + x"00",x"0C",x"04",x"0E",x"07",x"0F",x"01",x"00", -- 0x18D0 + x"00",x"00",x"04",x"09",x"0F",x"0F",x"0F",x"03", -- 0x18D8 + x"0E",x"02",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x18E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x18E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x18F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x18F8 + x"00",x"00",x"08",x"00",x"09",x"0D",x"07",x"00", -- 0x1900 + x"00",x"00",x"00",x"0C",x"06",x"07",x"0B",x"0E", -- 0x1908 + x"00",x"00",x"00",x"00",x"01",x"0B",x"07",x"0B", -- 0x1910 + x"00",x"03",x"06",x"0C",x"08",x"09",x"0F",x"0E", -- 0x1918 + x"00",x"07",x"0D",x"09",x"00",x"08",x"00",x"00", -- 0x1920 + x"0E",x"0B",x"07",x"06",x"0C",x"00",x"00",x"00", -- 0x1928 + x"0B",x"07",x"0B",x"01",x"00",x"00",x"00",x"00", -- 0x1930 + x"0E",x"0F",x"09",x"08",x"0C",x"06",x"03",x"00", -- 0x1938 + x"00",x"00",x"01",x"01",x"07",x"0C",x"08",x"00", -- 0x1940 + x"00",x"00",x"00",x"00",x"0E",x"07",x"0B",x"0E", -- 0x1948 + x"00",x"00",x"00",x"01",x"01",x"09",x"07",x"0B", -- 0x1950 + x"07",x"0D",x"0C",x"08",x"08",x"0D",x"0F",x"0F", -- 0x1958 + x"00",x"08",x"0C",x"07",x"01",x"01",x"00",x"00", -- 0x1960 + x"0E",x"0B",x"07",x"0E",x"00",x"00",x"00",x"00", -- 0x1968 + x"0B",x"07",x"09",x"01",x"01",x"00",x"00",x"00", -- 0x1970 + x"0F",x"0F",x"0D",x"08",x"08",x"0C",x"0D",x"07", -- 0x1978 + x"00",x"00",x"00",x"00",x"07",x"0E",x"0D",x"07", -- 0x1980 + x"00",x"01",x"01",x"08",x"0A",x"0F",x"05",x"00", -- 0x1988 + x"00",x"04",x"0E",x"03",x"01",x"07",x"0F",x"0F", -- 0x1990 + x"00",x"00",x"00",x"00",x"08",x"0D",x"0E",x"0D", -- 0x1998 + x"07",x"0D",x"0E",x"07",x"00",x"00",x"00",x"00", -- 0x19A0 + x"00",x"05",x"0F",x"0A",x"08",x"01",x"01",x"00", -- 0x19A8 + x"0F",x"0F",x"07",x"01",x"03",x"0E",x"04",x"00", -- 0x19B0 + x"0D",x"0E",x"0D",x"08",x"00",x"00",x"00",x"00", -- 0x19B8 + x"00",x"00",x"00",x"08",x"06",x"0E",x"0D",x"07", -- 0x19C0 + x"00",x"08",x"08",x"0C",x"06",x"03",x"01",x"00", -- 0x19C8 + x"00",x"0A",x"0F",x"01",x"00",x"07",x"0F",x"0F", -- 0x19D0 + x"00",x"00",x"00",x"08",x"0C",x"0D",x"0E",x"0D", -- 0x19D8 + x"07",x"0D",x"0E",x"06",x"08",x"00",x"00",x"00", -- 0x19E0 + x"00",x"01",x"03",x"06",x"0C",x"08",x"08",x"00", -- 0x19E8 + x"0F",x"0F",x"07",x"00",x"01",x"0F",x"0A",x"00", -- 0x19F0 + x"0D",x"0E",x"0D",x"0C",x"08",x"00",x"00",x"00", -- 0x19F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0C", -- 0x1A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"02", -- 0x1A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"08", -- 0x1A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"03",x"0C", -- 0x1A18 + x"02",x"02",x"01",x"0D",x"02",x"02",x"0C",x"00", -- 0x1A20 + x"05",x"00",x"05",x"0A",x"00",x"01",x"00",x"00", -- 0x1A28 + x"05",x"01",x"02",x"0A",x"01",x"05",x"0A",x"00", -- 0x1A30 + x"00",x"00",x"0D",x"02",x"00",x"00",x"0C",x"03", -- 0x1A38 + x"00",x"00",x"00",x"00",x"00",x"0C",x"02",x"02", -- 0x1A40 + x"00",x"00",x"00",x"00",x"00",x"05",x"02",x"00", -- 0x1A48 + x"00",x"00",x"00",x"00",x"00",x"04",x"09",x"01", -- 0x1A50 + x"00",x"00",x"00",x"00",x"03",x"0C",x"04",x"02", -- 0x1A58 + x"01",x"01",x"02",x"0A",x"0C",x"00",x"00",x"00", -- 0x1A60 + x"05",x"0A",x"00",x"02",x"05",x"00",x"00",x"00", -- 0x1A68 + x"02",x"0A",x"01",x"09",x"04",x"00",x"00",x"00", -- 0x1A70 + x"01",x"02",x"01",x"00",x"0C",x"03",x"00",x"00", -- 0x1A78 + x"00",x"00",x"00",x"0C",x"02",x"02",x"01",x"01", -- 0x1A80 + x"00",x"00",x"01",x"02",x"00",x"05",x"0A",x"00", -- 0x1A88 + x"00",x"00",x"04",x"0A",x"01",x"01",x"0A",x"02", -- 0x1A90 + x"00",x"00",x"03",x"0C",x"01",x"01",x"02",x"01", -- 0x1A98 + x"02",x"02",x"0C",x"00",x"00",x"00",x"00",x"00", -- 0x1AA0 + x"00",x"05",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x1AA8 + x"01",x"05",x"08",x"00",x"00",x"00",x"00",x"00", -- 0x1AB0 + x"02",x"02",x"0C",x"03",x"00",x"00",x"00",x"00", -- 0x1AB8 + x"00",x"0C",x"02",x"06",x"09",x"01",x"02",x"02", -- 0x1AC0 + x"00",x"05",x"0A",x"00",x"00",x"05",x"0A",x"00", -- 0x1AC8 + x"00",x"04",x"09",x"01",x"02",x"02",x"09",x"01", -- 0x1AD0 + x"03",x"0C",x"00",x"00",x"02",x"05",x"08",x"00", -- 0x1AD8 + x"0C",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1AE0 + x"05",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1AE8 + x"04",x"0A",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1AF0 + x"0C",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1AF8 + x"00",x"0C",x"08",x"01",x"03",x"0C",x"00",x"0F", -- 0x1B00 + x"00",x"01",x"00",x"04",x"02",x"0D",x"07",x"00", -- 0x1B08 + x"01",x"0A",x"0A",x"0A",x"05",x"03",x"0F",x"0F", -- 0x1B10 + x"06",x"04",x"0D",x"05",x"06",x"0F",x"0E",x"0F", -- 0x1B18 + x"04",x"03",x"09",x"04",x"03",x"09",x"0C",x"00", -- 0x1B20 + x"03",x"0C",x"04",x"09",x"05",x"01",x"00",x"00", -- 0x1B28 + x"0F",x"07",x"0B",x"02",x"02",x"0A",x"0A",x"03", -- 0x1B30 + x"0E",x"0F",x"0C",x"02",x"09",x"09",x"0C",x"06", -- 0x1B38 + x"00",x"00",x"08",x"02",x"06",x"08",x"03",x"0F", -- 0x1B40 + x"00",x"00",x"01",x"00",x"01",x"05",x"03",x"00", -- 0x1B48 + x"00",x"00",x"0B",x"0A",x"05",x"03",x"0F",x"0F", -- 0x1B50 + x"00",x"02",x"05",x"05",x"06",x"0F",x"0E",x"0F", -- 0x1B58 + x"04",x"06",x"08",x"06",x"02",x"08",x"00",x"00", -- 0x1B60 + x"07",x"02",x"04",x"00",x"01",x"01",x"00",x"00", -- 0x1B68 + x"0F",x"07",x"0B",x"0A",x"0A",x"02",x"00",x"00", -- 0x1B70 + x"0E",x"0F",x"0C",x"0A",x"09",x"0D",x"04",x"00", -- 0x1B78 + x"00",x"00",x"00",x"00",x"04",x"0C",x"02",x"0E", -- 0x1B80 + x"00",x"00",x"00",x"00",x"00",x"03",x"01",x"00", -- 0x1B88 + x"00",x"00",x"00",x"09",x"05",x"03",x"0F",x"0F", -- 0x1B90 + x"00",x"00",x"00",x"05",x"06",x"0F",x"0E",x"0F", -- 0x1B98 + x"08",x"04",x"08",x"04",x"00",x"00",x"00",x"00", -- 0x1BA0 + x"01",x"02",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x1BA8 + x"0F",x"07",x"0B",x"02",x"02",x"00",x"00",x"00", -- 0x1BB0 + x"0E",x"0F",x"0E",x"0A",x"0D",x"00",x"00",x"00", -- 0x1BB8 + x"00",x"00",x"08",x"02",x"06",x"08",x"03",x"0F", -- 0x1BC0 + x"00",x"00",x"01",x"00",x"01",x"05",x"03",x"00", -- 0x1BC8 + x"00",x"00",x"0B",x"0A",x"05",x"03",x"0F",x"0F", -- 0x1BD0 + x"00",x"02",x"05",x"05",x"06",x"0F",x"0E",x"0F", -- 0x1BD8 + x"04",x"06",x"08",x"06",x"02",x"08",x"00",x"00", -- 0x1BE0 + x"07",x"02",x"04",x"00",x"01",x"01",x"00",x"00", -- 0x1BE8 + x"0F",x"07",x"0B",x"0A",x"0A",x"02",x"00",x"00", -- 0x1BF0 + x"0E",x"0F",x"0C",x"0A",x"09",x"0D",x"04",x"00", -- 0x1BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"06",x"0D", -- 0x1C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"02",x"02", -- 0x1C18 + x"0B",x"06",x"00",x"00",x"06",x"0B",x"0D",x"06", -- 0x1C20 + x"00",x"00",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x1C28 + x"00",x"00",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x1C30 + x"02",x"02",x"0F",x"0F",x"02",x"02",x"02",x"02", -- 0x1C38 + x"00",x"00",x"00",x"00",x"06",x"09",x"0F",x"06", -- 0x1C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C50 + x"00",x"00",x"00",x"00",x"02",x"02",x"02",x"02", -- 0x1C58 + x"00",x"00",x"06",x"0B",x"0B",x"06",x"00",x"00", -- 0x1C60 + x"0F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C68 + x"0F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1C70 + x"0F",x"0F",x"02",x"02",x"02",x"02",x"00",x"00", -- 0x1C78 + x"00",x"00",x"06",x"0B",x"0D",x"06",x"00",x"00", -- 0x1C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"0F", -- 0x1C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"0F", -- 0x1C90 + x"00",x"00",x"02",x"02",x"02",x"02",x"0F",x"0F", -- 0x1C98 + x"06",x"0D",x"0B",x"06",x"00",x"00",x"00",x"00", -- 0x1CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CB0 + x"02",x"02",x"02",x"02",x"00",x"00",x"00",x"00", -- 0x1CB8 + x"06",x"09",x"0F",x"06",x"00",x"00",x"06",x"0B", -- 0x1CC0 + x"00",x"00",x"00",x"00",x"0F",x"0F",x"00",x"00", -- 0x1CC8 + x"00",x"00",x"00",x"00",x"0F",x"0F",x"00",x"00", -- 0x1CD0 + x"02",x"02",x"02",x"02",x"0F",x"0F",x"02",x"02", -- 0x1CD8 + x"0B",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CF0 + x"02",x"02",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1D18 + x"01",x"07",x"0F",x"0A",x"0D",x"0F",x"07",x"00", -- 0x1D20 + x"00",x"00",x"03",x"02",x"0F",x"0B",x"0E",x"00", -- 0x1D28 + x"00",x"0C",x"0D",x"0F",x"0F",x"0D",x"00",x"00", -- 0x1D30 + x"03",x"0F",x"0E",x"0D",x"0F",x"0F",x"0F",x"03", -- 0x1D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0C", -- 0x1D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0F", -- 0x1D58 + x"09",x"0F",x"0F",x"08",x"00",x"00",x"00",x"00", -- 0x1D60 + x"03",x"02",x"0F",x"0B",x"0E",x"00",x"00",x"00", -- 0x1D68 + x"0D",x"0F",x"0F",x"0D",x"00",x"00",x"00",x"00", -- 0x1D70 + x"0F",x"0E",x"01",x"0F",x"0F",x"00",x"00",x"00", -- 0x1D78 + x"00",x"00",x"00",x"00",x"01",x"07",x"0F",x"0A", -- 0x1D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"03",x"02", -- 0x1D88 + x"00",x"00",x"00",x"00",x"00",x"0C",x"0D",x"0F", -- 0x1D90 + x"00",x"00",x"00",x"00",x"03",x"0F",x"0E",x"0D", -- 0x1D98 + x"0D",x"0F",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x1DA0 + x"0F",x"0B",x"0E",x"00",x"00",x"00",x"00",x"00", -- 0x1DA8 + x"0F",x"0D",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1DB0 + x"0F",x"0F",x"0F",x"03",x"00",x"00",x"00",x"00", -- 0x1DB8 + x"00",x"06",x"03",x"0E",x"0C",x"08",x"0C",x"0D", -- 0x1DC0 + x"00",x"00",x"00",x"00",x"03",x"02",x"0F",x"0B", -- 0x1DC8 + x"00",x"00",x"00",x"0C",x"0D",x"0F",x"0F",x"0D", -- 0x1DD0 + x"00",x"03",x"07",x"0E",x"0F",x"0F",x"0F",x"0F", -- 0x1DD8 + x"07",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1DE0 + x"0E",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1DF0 + x"0E",x"07",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x1DF8 + x"00",x"00",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x1E00 + x"00",x"01",x"03",x"02",x"02",x"02",x"03",x"03", -- 0x1E08 + x"0C",x"0C",x"0C",x"00",x"0E",x"03",x"0B",x"0B", -- 0x1E10 + x"00",x"00",x"00",x"03",x"0F",x"09",x"06",x"06", -- 0x1E18 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"00",x"00", -- 0x1E20 + x"03",x"03",x"02",x"02",x"02",x"03",x"01",x"00", -- 0x1E28 + x"0B",x"0B",x"03",x"0E",x"00",x"0C",x"0C",x"0C", -- 0x1E30 + x"06",x"06",x"09",x"0F",x"03",x"00",x"00",x"00", -- 0x1E38 + x"00",x"00",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x1E40 + x"00",x"01",x"01",x"02",x"02",x"02",x"07",x"07", -- 0x1E48 + x"0E",x"0E",x"0E",x"00",x"0E",x"03",x"0B",x"03", -- 0x1E50 + x"00",x"00",x"00",x"03",x"0F",x"09",x"06",x"06", -- 0x1E58 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"00",x"00", -- 0x1E60 + x"07",x"07",x"0E",x"0E",x"0E",x"0F",x"07",x"00", -- 0x1E68 + x"03",x"03",x"03",x"0E",x"00",x"00",x"00",x"00", -- 0x1E70 + x"06",x"06",x"09",x"0F",x"03",x"00",x"00",x"00", -- 0x1E78 + x"00",x"00",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x1E80 + x"00",x"01",x"03",x"02",x"02",x"02",x"03",x"03", -- 0x1E88 + x"0C",x"0C",x"0C",x"00",x"0E",x"03",x"0B",x"0B", -- 0x1E90 + x"00",x"00",x"00",x"03",x"0F",x"09",x"06",x"06", -- 0x1E98 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"00",x"00", -- 0x1EA0 + x"03",x"03",x"02",x"02",x"02",x"03",x"01",x"00", -- 0x1EA8 + x"0B",x"0B",x"03",x"0E",x"00",x"0C",x"0C",x"0C", -- 0x1EB0 + x"06",x"06",x"09",x"0F",x"03",x"00",x"00",x"00", -- 0x1EB8 + x"00",x"00",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x1EC0 + x"00",x"07",x"0F",x"0E",x"0E",x"0E",x"07",x"07", -- 0x1EC8 + x"00",x"00",x"00",x"00",x"0E",x"03",x"03",x"03", -- 0x1ED0 + x"00",x"00",x"00",x"03",x"0F",x"09",x"06",x"06", -- 0x1ED8 + x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"00",x"00", -- 0x1EE0 + x"07",x"07",x"02",x"02",x"02",x"01",x"01",x"00", -- 0x1EE8 + x"03",x"0B",x"03",x"0E",x"00",x"0E",x"0E",x"0E", -- 0x1EF0 + x"06",x"06",x"09",x"0F",x"03",x"00",x"00",x"00", -- 0x1EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"0C",x"0E", -- 0x1F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x1F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"0C",x"02", -- 0x1F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1F18 + x"0C",x"0D",x"0D",x"0D",x"0C",x"0D",x"0E",x"04", -- 0x1F20 + x"02",x"04",x"0F",x"0B",x"04",x"02",x"01",x"00", -- 0x1F28 + x"01",x"00",x"0F",x"0F",x"00",x"01",x"02",x"0C", -- 0x1F30 + x"02",x"0A",x"0F",x"05",x"0A",x"02",x"01",x"00", -- 0x1F38 + x"00",x"00",x"00",x"00",x"04",x"0E",x"0D",x"0C", -- 0x1F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x1F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"0C",x"03", -- 0x1F50 + x"00",x"00",x"00",x"00",x"00",x"01",x"02",x"02", -- 0x1F58 + x"0D",x"0D",x"0D",x"0C",x"0E",x"0C",x"00",x"00", -- 0x1F60 + x"0F",x"0D",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x1F68 + x"0F",x"0E",x"03",x"0C",x"00",x"00",x"00",x"00", -- 0x1F70 + x"0D",x"0F",x"02",x"02",x"00",x"00",x"00",x"00", -- 0x1F78 + x"00",x"00",x"08",x"0E",x"0D",x"0D",x"0C",x"0D", -- 0x1F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"0F", -- 0x1F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"03",x"0F", -- 0x1F90 + x"00",x"00",x"00",x"01",x"02",x"00",x"0F",x"0F", -- 0x1F98 + x"0D",x"0D",x"0C",x"0C",x"00",x"00",x"00",x"00", -- 0x1FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1FB0 + x"02",x"00",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x1FB8 + x"0C",x"0C",x"0D",x"0D",x"0D",x"0C",x"0D",x"0D", -- 0x1FC0 + x"00",x"00",x"03",x"04",x"0B",x"0F",x"04",x"03", -- 0x1FC8 + x"00",x"0C",x"03",x"00",x"0F",x"0F",x"00",x"03", -- 0x1FD0 + x"00",x"01",x"00",x"0A",x"07",x"0F",x"08",x"02", -- 0x1FD8 + x"0E",x"08",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1FE8 + x"0C",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1FF0 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x20F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x21F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x22F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x23F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x24F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x25F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x26F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x27F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2818 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2820 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2828 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2830 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2838 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x28F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x29F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x2FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3818 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3820 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3828 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3830 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3838 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom1_dst.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom1_dst.vhd new file mode 100644 index 00000000..5a7d9423 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom1_dst.vhd @@ -0,0 +1,61 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PROM1_DST is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(7 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of PROM1_DST is + + + type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"07",x"09",x"0A",x"0B",x"0C",x"0D",x"0D",x"0E", -- 0x0000 + x"0E",x"0E",x"0D",x"0D",x"0C",x"0B",x"0A",x"09", -- 0x0008 + x"07",x"05",x"04",x"03",x"02",x"01",x"01",x"00", -- 0x0010 + x"00",x"00",x"01",x"01",x"02",x"03",x"04",x"05", -- 0x0018 + x"07",x"0C",x"0E",x"0E",x"0D",x"0B",x"09",x"0A", -- 0x0020 + x"0B",x"0B",x"0A",x"09",x"06",x"04",x"03",x"05", -- 0x0028 + x"07",x"09",x"0B",x"0A",x"08",x"05",x"04",x"03", -- 0x0030 + x"03",x"04",x"05",x"03",x"01",x"00",x"00",x"02", -- 0x0038 + x"07",x"0A",x"0C",x"0D",x"0E",x"0D",x"0C",x"0A", -- 0x0040 + x"07",x"04",x"02",x"01",x"00",x"01",x"02",x"04", -- 0x0048 + x"07",x"0B",x"0D",x"0E",x"0D",x"0B",x"07",x"03", -- 0x0050 + x"01",x"00",x"01",x"03",x"07",x"0E",x"07",x"00", -- 0x0058 + x"07",x"0D",x"0B",x"08",x"0B",x"0D",x"09",x"06", -- 0x0060 + x"0B",x"0E",x"0C",x"07",x"09",x"0A",x"06",x"02", -- 0x0068 + x"07",x"0C",x"08",x"04",x"05",x"07",x"02",x"00", -- 0x0070 + x"03",x"08",x"05",x"01",x"03",x"06",x"03",x"01", -- 0x0078 + x"00",x"08",x"0F",x"07",x"01",x"08",x"0E",x"07", -- 0x0080 + x"02",x"08",x"0D",x"07",x"03",x"08",x"0C",x"07", -- 0x0088 + x"04",x"08",x"0B",x"07",x"05",x"08",x"0A",x"07", -- 0x0090 + x"06",x"08",x"09",x"07",x"07",x"08",x"08",x"07", -- 0x0098 + x"07",x"08",x"06",x"09",x"05",x"0A",x"04",x"0B", -- 0x00A0 + x"03",x"0C",x"02",x"0D",x"01",x"0E",x"00",x"0F", -- 0x00A8 + x"00",x"0F",x"01",x"0E",x"02",x"0D",x"03",x"0C", -- 0x00B0 + x"04",x"0B",x"05",x"0A",x"06",x"09",x"07",x"08", -- 0x00B8 + x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07", -- 0x00C0 + x"08",x"09",x"0A",x"0B",x"0C",x"0D",x"0E",x"0F", -- 0x00C8 + x"0F",x"0E",x"0D",x"0C",x"0B",x"0A",x"09",x"08", -- 0x00D0 + x"07",x"06",x"05",x"04",x"03",x"02",x"01",x"00", -- 0x00D8 + x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07", -- 0x00E0 + x"08",x"09",x"0A",x"0B",x"0C",x"0D",x"0E",x"0F", -- 0x00E8 + x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07", -- 0x00F0 + x"08",x"09",x"0A",x"0B",x"0C",x"0D",x"0E",x"0F" -- 0x00F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom3_dst.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom3_dst.vhd new file mode 100644 index 00000000..b14b4860 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom3_dst.vhd @@ -0,0 +1,43 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PROM3_DST is + port ( + ADDR : in std_logic_vector(6 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of PROM3_DST is + + + type ROM_ARRAY is array(0 to 127) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0000 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0008 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0010 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0018 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0020 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0028 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0030 + x"0F",x"0D",x"0F",x"0F",x"0F",x"0D",x"0F",x"0F", -- 0x0038 + x"07",x"0F",x"0E",x"0D",x"0F",x"0F",x"0E",x"0D", -- 0x0040 + x"0F",x"0F",x"0E",x"0D",x"0F",x"0F",x"0E",x"0D", -- 0x0048 + x"0F",x"0F",x"0E",x"0D",x"0F",x"0F",x"0F",x"0B", -- 0x0050 + x"07",x"0F",x"0E",x"0D",x"0F",x"0F",x"0E",x"0D", -- 0x0058 + x"0F",x"0F",x"0E",x"0D",x"0F",x"0F",x"0E",x"0D", -- 0x0060 + x"0F",x"0F",x"0F",x"0B",x"07",x"0F",x"0E",x"0D", -- 0x0068 + x"0F",x"0F",x"0E",x"0D",x"0F",x"0F",x"0E",x"0D", -- 0x0070 + x"0F",x"0F",x"0E",x"0D",x"0F",x"0F",x"0F",x"0B" -- 0x0078 + ); + +begin + + p_rom : process(ADDR) + begin + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom4_dst.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom4_dst.vhd new file mode 100644 index 00000000..5cae9812 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom4_dst.vhd @@ -0,0 +1,155 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PROM4_DST is + port ( + ADDR : in std_logic_vector(9 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of PROM4_DST is + + + type ROM_ARRAY is array(0 to 1023) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"00",x"00",x"00",x"00",x"0F",x"0B",x"01", -- 0x0000 + x"00",x"00",x"00",x"00",x"00",x"0F",x"0B",x"03", -- 0x0008 + x"00",x"00",x"00",x"00",x"00",x"0F",x"0B",x"05", -- 0x0010 + x"00",x"00",x"00",x"00",x"00",x"0F",x"0B",x"07", -- 0x0018 + x"00",x"00",x"00",x"00",x"00",x"0B",x"01",x"09", -- 0x0020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0030 + x"00",x"0F",x"00",x"0E",x"00",x"01",x"0C",x"0F", -- 0x0038 + x"00",x"0E",x"00",x"0B",x"00",x"0C",x"0B",x"0E", -- 0x0040 + x"00",x"0C",x"0F",x"01",x"00",x"00",x"00",x"00", -- 0x0048 + x"00",x"01",x"02",x"0F",x"00",x"07",x"0C",x"02", -- 0x0050 + x"00",x"09",x"06",x"0F",x"00",x"0D",x"0C",x"0F", -- 0x0058 + x"00",x"05",x"03",x"09",x"00",x"0F",x"0B",x"00", -- 0x0060 + x"00",x"0E",x"00",x"0B",x"00",x"0E",x"00",x"0B", -- 0x0068 + x"00",x"00",x"00",x"00",x"00",x"0F",x"0E",x"01", -- 0x0070 + x"00",x"0F",x"0B",x"0E",x"00",x"0E",x"00",x"0F", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x03F8 + ); + +begin + + p_rom : process(ADDR) + begin + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom7_dst.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom7_dst.vhd new file mode 100644 index 00000000..05520377 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/ROM/prom7_dst.vhd @@ -0,0 +1,33 @@ +-- generated with romgen v3.0 by MikeJ +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PROM7_DST is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(4 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of PROM7_DST is + + + type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"00",x"07",x"66",x"EF",x"00",x"F8",x"EA",x"6F", -- 0x0000 + x"00",x"3F",x"00",x"C9",x"38",x"AA",x"AF",x"F6", -- 0x0008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0018 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/build_id.v new file mode 100644 index 00000000..159d6521 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171112" +`define BUILD_TIME "231105" diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/keyboard.v new file mode 100644 index 00000000..8556280d --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/keyboard.v @@ -0,0 +1,83 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h29: joystick[0] <= ~release_btn; // Space + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + 'h76: joystick[3] <= ~release_btn; // Escape + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/osd.v b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..d68aba42 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman.vhd @@ -0,0 +1,552 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_MACHINE is + generic ( + -- only set one of these + PENGO : std_logic := '0'; -- set to 1 when using Pengo ROMs, 0 otherwise + PACMAN : std_logic := '1'; -- set to 1 for all other Pacman hardware games + -- only set one of these when PACMAN is set + MRTNT : std_logic := '0'; -- set to 1 when using Mr TNT ROMs, 0 otherwise + LIZWIZ : std_logic := '0'; -- set to 1 when using Lizard Wizard ROMs, 0 otherwise + MSPACMAN : std_logic := '0'; -- set to 1 when using Ms Pacman ROMs, 0 otherwise + MMINER : std_logic := '1' -- set to 1 when using Maniac Miner ROMs, 0 otherwise + ); + port ( + clk : in std_logic; + ena_6 : in std_logic; + reset : in std_logic; + + -- video + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + hsync : out std_logic; + vsync : out std_logic; + v_blank : out std_logic; + h_blank : out std_logic; + + -- audio + audio : out std_logic_vector(7 downto 0); + + -- controls + in0_reg : in std_logic_vector( 7 downto 0); + in1_reg : in std_logic_vector( 7 downto 0); + dipsw1_reg : in std_logic_vector( 7 downto 0); + dipsw2_reg : in std_logic_vector( 7 downto 0) + ); + end; + +architecture RTL of PACMAN_MACHINE is + + -- timing + signal hcnt : std_logic_vector( 8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector( 8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean := true; + signal hblank : std_logic; + signal vblank : std_logic; +-- signal comp_sync_l : std_logic; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector( 7 downto 0); + signal cpu_data_in : std_logic_vector( 7 downto 0); + + signal program_rom : std_logic_vector( 7 downto 0); + signal program_rom_dinl : std_logic_vector( 7 downto 0); + signal program_rom_dinh : std_logic_vector( 7 downto 0); + signal program_rom_bufl : std_logic_vector( 7 downto 0); + signal program_rom_bufh : std_logic_vector( 7 downto 0); + signal program_rom_din : std_logic_vector( 7 downto 0); + signal rom_to_dec : std_logic_vector( 7 downto 0); + signal rom_from_dec : std_logic_vector( 7 downto 0); +-- signal program_rom_cs_l : std_logic; + + signal control_reg : std_logic_vector( 7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_reg : std_logic_vector( 7 downto 0); + signal sync_bus_db : std_logic_vector( 7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + signal sync_bus_cs_l : std_logic; + + signal cpu_vec_reg : std_logic_vector( 7 downto 0) := (others => '0'); + signal ps_reg : std_logic_vector( 2 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector( 7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector( 3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + v_blank <= vblank; + h_blank <= hblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + vsync <= not vcnt(8); + do_hsync <= true when (hcnt = "010101111") else false; -- 0AF + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off +-- watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + -- 7M + -- 7N + sync_bus_cs_l <= '1'; + -- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + + -- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then + -- program_rom_cs_l <= '0'; + -- end if; + + if (PENGO = '1' and cpu_addr(15) = '1') or (PACMAN = '1' and cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + + -- + -- vram addresser custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H => hcnt, + V => vcnt(7 downto 0), + FLIP => control_reg(3) + ); + + --When 2H is low, the CPU controls the bus. + ab <= cpu_addr(11 downto 0) when hcnt(1) = '0' else vram_addr_ab; + + -- vram_l <= not ((not (cpu_addr(12) or sync_bus_stb)) or (hcnt(1) and hcnt(0))); + vram_l <= ( (cpu_addr(12) or sync_bus_stb) and not (hcnt(1) and hcnt(0)) ); + + -- PENGO PACMAN + + -- WRITE + -- wr0_l 0x9000 - 0x900F voice 1,2,3 waveform wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x9010 - 0x901F x50 wr voice 1,2,3 freq/vol wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x9020 - 0x902F sprites wr2_l 0x5060 - 0x506F sprite + -- 0x5080 - 0x50BF unused + -- out_l 0x9040 - 0x904F control space out_l 0x5000 - 0x503F control space + -- wdr_l 0x9070 - 0x907F watchdog reset wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + -- dipsw2_l 0x9000 - 0x903F dip switch 2 + -- dipsw1_l 0x9040 - 0x907F dip switch 1 dipsw1_l 0x5080 - 0x50BF dip switches + -- in1_l 0x9080 - 0x90BF in port 1 in1_l 0x5040 - 0x507F in port 1 + -- in0_l 0x90C0 - 0x90FF in port 0 in0_l 0x5000 - 0x503F in port 0 + + -- writes <------------- PENGO -------------> <------------- PACMAN ------------> + wr0_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"0") or (PACMAN='1' and ab(7 downto 4)=x"4") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr voice 1,2,3 waveform + wr1_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"1") or (PACMAN='1' and ab(7 downto 4)=x"5") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr voice 1,2,3 freq/vol + wr2_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"2") or (PACMAN='1' and ab(7 downto 4)=x"6") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr sprites + iodec_out_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"4") or (PACMAN='1' and ab(7 downto 6)="00") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr control space + iodec_wdr_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"7") or (PACMAN='1' and ab(7 downto 6)="11") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr watchdog reset + + -- reads + iodec_dipsw2_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="00") or (PACMAN='1' and ab(7 downto 6)="11") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in dip sw2 + iodec_dipsw1_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="01") or (PACMAN='1' and ab(7 downto 6)="10") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in dip sw1 + iodec_in1_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="10") or (PACMAN='1' and ab(7 downto 6)="01") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in port 1 + iodec_in0_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="11") or (PACMAN='1' and ab(7 downto 6)="00") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in port 0 + + ps_reg <= control_reg(7) & control_reg(6) & control_reg(2) when PENGO = '1' else "000"; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + -- 8 bit addressable latch 7K (made into register) + + -- PENGO PACMAN + -- 0 Interrupt ena Interrupt ena + -- 1 Sound ena Sound ena + -- 2 PS1 Not used + -- 3 Flip Flip + -- 4 Coin 1 meter 1 player start lamp + -- 5 Coin 2 meter 2 player start lamp + -- 6 PS2 Coin lockout + -- 7 PS3 Coin counter + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + sync_bus_db <= cpu_data_out when hcnt(1) = '0' else rams_data_out; + + -- address decoder + cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when (sync_bus_wreq_l = '0') else + program_rom when (PENGO = '1' and cpu_addr(15) = '0') else -- ROM at 0000 - 7fff (Pengo descrambler) + program_rom when (PACMAN = '1' and cpu_addr(15 downto 14) = "00") else -- ROM at 0000 - 3fff and 8000 - bfff + program_rom when (PACMAN = '1' and cpu_addr(15 downto 13) = "100") else -- ROM at 8000 - 9fff (LizWiz) + in0_reg when (iodec_in0_l = '0') else + in1_reg when (iodec_in1_l = '0') else + dipsw1_reg when (iodec_dipsw1_l = '0') else + -- dipsw2_reg when (iodec_dipsw2_l = '0') else + rams_data_out; + + u_adec : entity work.rom_descrambler + generic map ( + PENGO => PENGO, + PACMAN => PACMAN, + MRTNT => MRTNT, + LIZWIZ => LIZWIZ, + MSPACMAN => MSPACMAN, + MMINER => MMINER + ) + port map ( + CLK => clk, + ENA => ena_6, + cpu_m1_l => cpu_m1_l, + addr => cpu_addr, + data => program_rom + ); + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab, + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab, + data_b_o => rams_data_out + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_PS => ps_reg, + I_WR2_L => wr2_l, + -- + O_RED => video_r, + O_GREEN => video_g, + O_BLUE => video_b, + -- + ENA_6 => ena_6, + CLK => clk + ); + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => audio, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_rom_descrambler.vhd new file mode 100644 index 00000000..9f0db0a6 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_rom_descrambler.vhd @@ -0,0 +1,480 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) d18c7db (gmail) - May 2013 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- + + +-- The following comments and source code in the comments are from MAME source code and are +-- included here to help make sense of the logic used in the VHDL address mapper and descrambler +-- +--/************************************ +-- * +-- * Ms. Pac-Man +-- * +-- ************************************/ +-- +--/* +-- Ms. Pac-Man has an auxiliary PCB with ribbon cable that plugs into the Z-80 CPU socket of a Pac-Man main PCB. Also the +-- graphics ROMs at 5E, 5F on the main board are replaced. +-- +-- The aux board contains three ROMs (two 2532 at U6, U7 and one 2716 at U5), a Z-80, and four PAL/HAL logic chips. +-- +-- The aux board logic decodes the Z-80 address and determines whether to enable the main board ROMs (containing Pac-Man +-- code) or the aux board ROMs (containing Ms. Pac-Man code). Normally the Pac-Man ROMs reside at address 0x0000-0x3fff +-- and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). The aux board logic modifies the address map and +-- enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. Furthermore there are forty 8-byte "patch" +-- regions which reside in the 0x0000-0x2fff address range. Any access to these patch addresses will disable the Pac-Man +-- ROMs and enable the aux board ROM. Aux board ROM addresses 0x8000-0x81ef are mapped onto the patch regions. These +-- patches typically insert jumps to new code above 0x8000. +-- +-- The aux board logic also acts as a software protection circuit which inhibits dumping of the ROMs (e.g., using a +-- microprocessor emulator system). There are several "trap" address regions which enable and disable the decode +-- functions. In order to properly operate as Ms. Pac-Man you must access one of the "latch set" trap addresses. This +-- enables the decode. If a "latch clear" address is accessed then decode is disabled and all you get is Pac-Man. For +-- more info see U.S. Patent 4,525,599 "Software protection methods and apparatus". +-- +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 +-- +-- Any memory access will trigger the trap behavior: instruction fetch, data read, data write. The latch clear addresses +-- should never be accessed during normal Ms. Pac-Man operation, so when the circuitry detects an access it clears the +-- latch and prevents any further dumping of the aux board ROMs. +-- +-- The Pac-Man self-test code does a checksum of the ROM 0x0000-0x2fff. This works because the checksum routine walks the +-- ROM starting from the low address and hits the latch clear trap at 0x0038 prior to encountering any of the patch +-- regions. The decode stays disabled for the rest of the checksum routine, and thus the checksum is calculated for the +-- Pac-Man ROMs with no patches applied. +-- +-- During normal operation every VBLANK (60.6Hz) interrupt will fetch its interrupt vector from the 0x3ff8 trap region, so +-- the latch is continually being enabled. +-- +-- In a further attempt to thwart copying, the aux board ROMs have a simple encryption scheme: their address and data +-- lines are bit flipped (i.e., wired in a nonstandard fashion). The specific bit flips were selected to minimize the +-- vias required to lay out the aux PCB. +--*/ + +-- +--static void mspacman_install_patches(UINT8 *ROM) +--{ +-- int i; +-- +-- /* copy forty 8-byte patches into Pac-Man code */ +-- for (i = 0; i < 8; i++) +-- { +-- ROM[0x0410+i] = ROM[0x8008+i]; +-- ROM[0x08E0+i] = ROM[0x81D8+i]; +-- ROM[0x0A30+i] = ROM[0x8118+i]; +-- ROM[0x0BD0+i] = ROM[0x80D8+i]; +-- ROM[0x0C20+i] = ROM[0x8120+i]; +-- ROM[0x0E58+i] = ROM[0x8168+i]; +-- ROM[0x0EA8+i] = ROM[0x8198+i]; +-- +-- ROM[0x1000+i] = ROM[0x8020+i]; +-- ROM[0x1008+i] = ROM[0x8010+i]; +-- ROM[0x1288+i] = ROM[0x8098+i]; +-- ROM[0x1348+i] = ROM[0x8048+i]; +-- ROM[0x1688+i] = ROM[0x8088+i]; +-- ROM[0x16B0+i] = ROM[0x8188+i]; +-- ROM[0x16D8+i] = ROM[0x80C8+i]; +-- ROM[0x16F8+i] = ROM[0x81C8+i]; +-- ROM[0x19A8+i] = ROM[0x80A8+i]; +-- ROM[0x19B8+i] = ROM[0x81A8+i]; +-- +-- ROM[0x2060+i] = ROM[0x8148+i]; +-- ROM[0x2108+i] = ROM[0x8018+i]; +-- ROM[0x21A0+i] = ROM[0x81A0+i]; +-- ROM[0x2298+i] = ROM[0x80A0+i]; +-- ROM[0x23E0+i] = ROM[0x80E8+i]; +-- ROM[0x2418+i] = ROM[0x8000+i]; +-- ROM[0x2448+i] = ROM[0x8058+i]; +-- ROM[0x2470+i] = ROM[0x8140+i]; +-- ROM[0x2488+i] = ROM[0x8080+i]; +-- ROM[0x24B0+i] = ROM[0x8180+i]; +-- ROM[0x24D8+i] = ROM[0x80C0+i]; +-- ROM[0x24F8+i] = ROM[0x81C0+i]; +-- ROM[0x2748+i] = ROM[0x8050+i]; +-- ROM[0x2780+i] = ROM[0x8090+i]; +-- ROM[0x27B8+i] = ROM[0x8190+i]; +-- ROM[0x2800+i] = ROM[0x8028+i]; +-- ROM[0x2B20+i] = ROM[0x8100+i]; +-- ROM[0x2B30+i] = ROM[0x8110+i]; +-- ROM[0x2BF0+i] = ROM[0x81D0+i]; +-- ROM[0x2CC0+i] = ROM[0x80D0+i]; +-- ROM[0x2CD8+i] = ROM[0x80E0+i]; +-- ROM[0x2CF0+i] = ROM[0x81E0+i]; +-- ROM[0x2D60+i] = ROM[0x8160+i]; +-- } +--} +-- +--DRIVER_INIT_MEMBER(pacman_state,mspacman) +--{ +-- int i; +-- UINT8 *ROM, *DROM; +-- +-- /* CPU ROMs */ +-- +-- /* Pac-Man code is in low bank */ +-- ROM = machine().root_device().memregion("maincpu")->base(); +-- +-- /* decrypted Ms. Pac-Man code is in high bank */ +-- DROM = &machine().root_device().memregion("maincpu")->base()[0x10000]; +-- +-- /* copy ROMs into decrypted bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0x0000+i] = ROM[0x0000+i]; /* pacman.6e */ +-- DROM[0x1000+i] = ROM[0x1000+i]; /* pacman.6f */ +-- DROM[0x2000+i] = ROM[0x2000+i]; /* pacman.6h */ +-- DROM[0x3000+i] = BITSWAP8(ROM[0xb000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u7 */ +-- } +-- for (i = 0; i < 0x800; i++) +-- { +-- DROM[0x8000+i] = BITSWAP8(ROM[0x8000+BITSWAP16(i,15,14,13,12,11,8,7,5,9,10,6,3,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u5 */ +-- DROM[0x8800+i] = BITSWAP8(ROM[0x9800+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +-- DROM[0x9000+i] = BITSWAP8(ROM[0x9000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +--// 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 +-- DROM[0x9800+i] = ROM[0x1800+i]; /* mirror of pacman.6f high */ +-- } +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0xa000+i] = ROM[0x2000+i]; /* mirror of pacman.6h */ +-- DROM[0xb000+i] = ROM[0x3000+i]; /* mirror of pacman.6j */ +-- } +-- /* install patches into decrypted bank */ +-- mspacman_install_patches(DROM); +-- +-- /* mirror Pac-Man ROMs into upper addresses of normal bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- ROM[0x8000+i] = ROM[0x0000+i]; +-- ROM[0x9000+i] = ROM[0x1000+i]; +-- ROM[0xa000+i] = ROM[0x2000+i]; +-- ROM[0xb000+i] = ROM[0x3000+i]; +-- } +-- +-- /* initialize the banks */ +-- machine().root_device().membank("bank1")->configure_entries(0, 2, &ROM[0x00000], 0x10000); +-- machine().root_device().membank("bank1")->set_entry(1); +--} +-- +--ROM_START( puckmana ) +-- ROM_REGION( 0x10000, "maincpu", 0 ) +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "prg7", 0x3000, 0x0800, CRC(b6289b26) SHA1(d249fa9cdde774d5fee7258147cd25fa3f4dc2b3) ) +-- ROM_LOAD( "prg8", 0x3800, 0x0800, CRC(17a88c13) SHA1(eb462de79f49b7aa8adb0cc6d31535b10550c0ce) ) +-- +--ROM_START( mspacman ) +-- ROM_REGION( 0x20000, "maincpu", 0 ) /* 64k for code+64k for decrypted code */ +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "pacman.6j", 0x3000, 0x1000, CRC(817d94e3) SHA1(d4a70d56bb01d27d094d73db8667ffb00ca69cb9) ) +-- +-- ROM_LOAD( "u5", 0x8000, 0x0800, CRC(f45fbbcd) SHA1(b26cc1c8ee18e9b1daa97956d2159b954703a0ec) ) +-- ROM_LOAD( "u6", 0x9000, 0x1000, CRC(a90e7000) SHA1(e4df96f1db753533f7d770aa62ae1973349ea4cf) ) +-- ROM_LOAD( "u7", 0xb000, 0x1000, CRC(c82cd714) SHA1(1d8ac7ad03db2dc4c8c18ade466e12032673f874) ) +-- +-- +--Normally the Pac-Man ROMs reside at address 0x0000-0x3fff and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). +--The aux board logic modifies the address map and enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity rom_descrambler is + generic ( + -- only set one of these + PENGO : std_logic := '0'; -- set to 1 when using Pengo ROMs, 0 otherwise + PACMAN : std_logic := '1'; -- set to 1 for all other Pacman hardware games + -- only set one of these when PACMAN is set + MRTNT : std_logic := '0'; -- set to 1 when using Mr TNT ROMs, 0 otherwise + LIZWIZ : std_logic := '0'; -- set to 1 when using Lizard Wizard ROMs, 0 otherwise + MSPACMAN : std_logic := '0'; -- set to 1 when using Ms Pacman ROMs, 0 otherwise + MMINER : std_logic := '1' -- set to 1 when using Maniac Miner ROMs, 0 otherwise + ); + port ( + CLK : in std_logic; + ENA : in std_logic; + -- + cpu_m1_l : in std_logic; + addr : in std_logic_vector(15 downto 0); + data : out std_logic_vector( 7 downto 0) + ); + +end rom_descrambler; + +architecture rtl of rom_descrambler is + signal overlay_on : std_logic := '0'; + signal sega_dec_ena : std_logic; + signal rom_patched : std_logic_vector(15 downto 0); + signal rom_addr : std_logic_vector(15 downto 0); + signal rom_lo : std_logic_vector( 7 downto 0); + signal rom_hi : std_logic_vector( 7 downto 0); + signal rom_data_in : std_logic_vector( 7 downto 0); + signal rom_data_out : std_logic_vector( 7 downto 0); + signal sega_dec : std_logic_vector( 7 downto 0); +begin + -- ROM at 0000 - 3FFF + u_program_rom0 : entity work.ROM_PGM_0 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_lo + ); + + -- ROM at 8000 - BFFF (Liz Wiz) +-- u_program_rom1 : entity work.ROM_PGM_1 +-- port map ( +-- CLK => CLK, +-- ADDR => rom_addr(13 downto 0), +-- DATA => rom_hi +-- ); + + -- Sega ROM descrambler adapted from MAME segacrpt.c source code + u_sega_decode : entity work.sega_decode + port map ( + I_CK => clk, + I_DEC => sega_dec_ena, -- passthrough when low + I_A(6) => cpu_m1_l, + I_A(5) => rom_addr(12), + I_A(4) => rom_addr(8), + I_A(3) => rom_addr(4), + I_A(2) => rom_addr(0), + I_A(1) => rom_data_in(5), + I_A(0) => rom_data_in(3), + I_D => rom_data_in, + O_D => sega_dec + ); + + sega_dec_ena <= PENGO and (not rom_addr(15)); + +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 + p_overlay : process + variable trap_addr : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + trap_addr := addr(15 downto 3) & "000"; + if trap_addr = x"3ff8" then + overlay_on <= '1'; + elsif + trap_addr = x"0038" or + trap_addr = x"03b0" or + trap_addr = x"1600" or + trap_addr = x"2120" or + trap_addr = x"3ff0" or + trap_addr = x"8000" or + trap_addr = x"97f0" + then + overlay_on <= '0'; + end if; + end process; + + p_decoder_comb : process(clk, rom_addr, addr, rom_data_in, rom_data_out, rom_patched, rom_hi, rom_lo, overlay_on, sega_dec) + variable patch_addr : std_logic_vector(15 downto 0); + begin + rom_addr <= addr; + rom_patched <= addr; + data <= rom_data_out; + + -- default is unscrambled data + rom_data_out <= rom_data_in ; + + -- mux ROMs to same data bus + -- ignore A15 so that Pacman ROMs 0000-3FFF mirror in high mem at 8000-BFFF + if rom_addr(14) = '0' then + rom_data_in <= rom_lo; + else + rom_data_in <= rom_hi; + end if; + + -- Mr TNT program ROMs have data lines D3 and D5 swapped + -- Mr TNT video ROMs have data lines D4 and D6 and address lines A0 and A2 swapped + if MRTNT = '1' then + rom_data_out <= rom_data_in(7 downto 6) & rom_data_in(3) & rom_data_in(4) & rom_data_in(5) & rom_data_in(2 downto 0); + end if; + + if PENGO = '1' then + -- ROM at 0000 - 7fff (Pengo) + if rom_addr(15) = '0' then + rom_data_out <= sega_dec; + end if; + end if; + + if MSPACMAN = '1' and overlay_on = '1' then + -- forty 8-byte patches into Pac-Man code + -- If the CPU address presented falls in a patch range, substitute it with patched address + -- OH THE HUMANITY!!! + patch_addr := addr(15 downto 3) & "000"; + case patch_addr is + when x"0410" => rom_patched <= x"800" & '1' & addr(2 downto 0); -- ROM[0x0410+i] = ROM[0x8008+i] + when x"08E0" => rom_patched <= x"81D" & '1' & addr(2 downto 0); -- ROM[0x08E0+i] = ROM[0x81D8+i] + when x"0A30" => rom_patched <= x"811" & '1' & addr(2 downto 0); -- ROM[0x0A30+i] = ROM[0x8118+i] + when x"0BD0" => rom_patched <= x"80D" & '1' & addr(2 downto 0); -- ROM[0x0BD0+i] = ROM[0x80D8+i] + when x"0C20" => rom_patched <= x"812" & '0' & addr(2 downto 0); -- ROM[0x0C20+i] = ROM[0x8120+i] + when x"0E58" => rom_patched <= x"816" & '1' & addr(2 downto 0); -- ROM[0x0E58+i] = ROM[0x8168+i] + when x"0EA8" => rom_patched <= x"819" & '1' & addr(2 downto 0); -- ROM[0x0EA8+i] = ROM[0x8198+i] + + when x"1000" => rom_patched <= x"802" & '0' & addr(2 downto 0); -- ROM[0x1000+i] = ROM[0x8020+i] + when x"1008" => rom_patched <= x"801" & '0' & addr(2 downto 0); -- ROM[0x1008+i] = ROM[0x8010+i] + when x"1288" => rom_patched <= x"809" & '1' & addr(2 downto 0); -- ROM[0x1288+i] = ROM[0x8098+i] + when x"1348" => rom_patched <= x"804" & '1' & addr(2 downto 0); -- ROM[0x1348+i] = ROM[0x8048+i] + when x"1688" => rom_patched <= x"808" & '1' & addr(2 downto 0); -- ROM[0x1688+i] = ROM[0x8088+i] + when x"16B0" => rom_patched <= x"818" & '1' & addr(2 downto 0); -- ROM[0x16B0+i] = ROM[0x8188+i] + when x"16D8" => rom_patched <= x"80C" & '1' & addr(2 downto 0); -- ROM[0x16D8+i] = ROM[0x80C8+i] + when x"16F8" => rom_patched <= x"81C" & '1' & addr(2 downto 0); -- ROM[0x16F8+i] = ROM[0x81C8+i] + when x"19A8" => rom_patched <= x"80A" & '1' & addr(2 downto 0); -- ROM[0x19A8+i] = ROM[0x80A8+i] + when x"19B8" => rom_patched <= x"81A" & '1' & addr(2 downto 0); -- ROM[0x19B8+i] = ROM[0x81A8+i] + + when x"2060" => rom_patched <= x"814" & '1' & addr(2 downto 0); -- ROM[0x2060+i] = ROM[0x8148+i] + when x"2108" => rom_patched <= x"801" & '1' & addr(2 downto 0); -- ROM[0x2108+i] = ROM[0x8018+i] + when x"21A0" => rom_patched <= x"81A" & '0' & addr(2 downto 0); -- ROM[0x21A0+i] = ROM[0x81A0+i] + when x"2298" => rom_patched <= x"80A" & '0' & addr(2 downto 0); -- ROM[0x2298+i] = ROM[0x80A0+i] + when x"23E0" => rom_patched <= x"80E" & '1' & addr(2 downto 0); -- ROM[0x23E0+i] = ROM[0x80E8+i] + when x"2418" => rom_patched <= x"800" & '0' & addr(2 downto 0); -- ROM[0x2418+i] = ROM[0x8000+i] + when x"2448" => rom_patched <= x"805" & '1' & addr(2 downto 0); -- ROM[0x2448+i] = ROM[0x8058+i] + when x"2470" => rom_patched <= x"814" & '0' & addr(2 downto 0); -- ROM[0x2470+i] = ROM[0x8140+i] + when x"2488" => rom_patched <= x"808" & '0' & addr(2 downto 0); -- ROM[0x2488+i] = ROM[0x8080+i] + when x"24B0" => rom_patched <= x"818" & '0' & addr(2 downto 0); -- ROM[0x24B0+i] = ROM[0x8180+i] + when x"24D8" => rom_patched <= x"80C" & '0' & addr(2 downto 0); -- ROM[0x24D8+i] = ROM[0x80C0+i] + when x"24F8" => rom_patched <= x"81C" & '0' & addr(2 downto 0); -- ROM[0x24F8+i] = ROM[0x81C0+i] + when x"2748" => rom_patched <= x"805" & '0' & addr(2 downto 0); -- ROM[0x2748+i] = ROM[0x8050+i] + when x"2780" => rom_patched <= x"809" & '0' & addr(2 downto 0); -- ROM[0x2780+i] = ROM[0x8090+i] + when x"27B8" => rom_patched <= x"819" & '0' & addr(2 downto 0); -- ROM[0x27B8+i] = ROM[0x8190+i] + when x"2800" => rom_patched <= x"802" & '1' & addr(2 downto 0); -- ROM[0x2800+i] = ROM[0x8028+i] + when x"2B20" => rom_patched <= x"810" & '0' & addr(2 downto 0); -- ROM[0x2B20+i] = ROM[0x8100+i] + when x"2B30" => rom_patched <= x"811" & '0' & addr(2 downto 0); -- ROM[0x2B30+i] = ROM[0x8110+i] + when x"2BF0" => rom_patched <= x"81D" & '0' & addr(2 downto 0); -- ROM[0x2BF0+i] = ROM[0x81D0+i] + when x"2CC0" => rom_patched <= x"80D" & '0' & addr(2 downto 0); -- ROM[0x2CC0+i] = ROM[0x80D0+i] + when x"2CD8" => rom_patched <= x"80E" & '0' & addr(2 downto 0); -- ROM[0x2CD8+i] = ROM[0x80E0+i] + when x"2CF0" => rom_patched <= x"81E" & '0' & addr(2 downto 0); -- ROM[0x2CF0+i] = ROM[0x81E0+i] + when x"2D60" => rom_patched <= x"816" & '0' & addr(2 downto 0); -- ROM[0x2D60+i] = ROM[0x8160+i] + when others => rom_patched <= addr; + end case; + +-- Pacman ROMs +-- 0x0000-0x0FFF = 0x0000-0x0FFF; /* pacman.6e */ +-- 0x1000-0x1FFF = 0x1000-0x1FFF; /* pacman.6f */ +-- 0x2000-0x2FFF = 0x2000-0x2FFF; /* pacman.6h */ +-- 0x3000-0x3FFF = 0x3000-0x3FFF; /* pacman.6j */ + +-- ROM mirror (easy just ignore A15) +-- 0x8000-0x8FFF = 0x0000-0x0FFF; /* mirror of pacman.6e */ +-- 0x9000-0x9FFF = 0x1000-0x1FFF; /* mirror of pacman.6f */ +-- 0xA000-0xAFFF = 0x2000-0x2FFF; /* mirror of pacman.6h */ +-- 0xB000-0xBFFF = 0x3000-0x3FFF; /* mirror of pacman.6j */ + +-- Ms Pacman overlays + +-- no xlate +-- 0x8000-0x87FF = 0x8000-0x87FF (physical ROM hi 0000-07FF); /* decrypt u5 */ +-- 0x9000-0x97FF = 0x9000-0x97FF (physical ROM hi 1000-17FF); /* decrypt half of u6 */ + +-- xlate addr +-- 0x3000-0x3FFF = 0xB000-0xBFFF (physical ROM hi 2000-2FFF); /* decrypt u7 */ + +-- xlate addr +-- 0x8800-0x8FFF = 0x9800-0x9FFF (physical ROM hi 1800-1FFF); /* decrypt half of u6 */ + +-- ROM hi mem map +-- u5 2K 0000-07FF (0x8000-0x87FF) +-- u5 2K 0800-0FFF N/A +-- u6b 2K 1000-17FF (0x9000-0x97FF) +-- u6t 2K 1800-1FFF (0x8800-0x8FFF) +-- u7 4K 2000-2FFF (0x3000-0x3FFF) + + -- If the new patched address falls in certain Ms Pacman ranges, swap in ROM overlays and descramble address and data + -- high address bits are not scrambled so we know for sure this only accesses ROM hi after address translation + case rom_patched(15 downto 11) is + + -- addr = 0x3000-0x37FF, xlate to 0xB000-0xB7FF (physical ROM hi 2000-27FF), decrypt half of u7 + when "00110" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x3800-0x3FFF, xlate to 0xB800-0xBFFF (physical ROM hi 2800-2FFF), decrypt half of u7 + when "00111" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8000-0x87FF, no xlate (physical ROM hi 0000-07FF), decrypt u5 + when "10000" => + rom_addr <= x"0" & rom_patched(11) & rom_patched(8) & rom_patched(7) & rom_patched(5) & rom_patched(9) & rom_patched(10) & rom_patched(6) & rom_patched(3) & rom_patched(4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8800-0x8FFF, xlate to 0x9800-0x9FFF (physical ROM hi 1800-1FFF), decrypt half of u6 + when "10001" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x9000-0x97FF, no xlate (physical ROM hi 1000-17FF), decrypt half of u6 + when "10010" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- catch all default action + when others => null; + rom_addr <= rom_patched; + rom_data_out <= rom_data_in; + end case; + end if; + end process; + +end rtl; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..ec6bcb54 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_video.vhd @@ -0,0 +1,371 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '1' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_PS : in std_logic_vector( 2 downto 0); + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(13 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, I_PS(2), + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(13) <= I_PS(2); + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + -- CLK => CLK, + ADDR(9) => '0', + ADDR(8) => I_PS(1), + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(4) => I_PS(0), + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..33b9febe --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,73 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is +port ( + AB : out std_logic_vector (11 downto 0); + H : in std_logic_vector ( 8 downto 0); -- H256_L H128 H64 H32 H16 H8 H4 H2 H1 + V : in std_logic_vector ( 7 downto 0); -- V128 V64 v32 V16 V8 V4 V2 V1 + FLIP : in std_logic +); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + signal sel : std_logic; + signal y157_bus : std_logic_vector (11 downto 0); + signal y257_bus : std_logic_vector (11 downto 0); + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); +begin + hp <= H(7 downto 3) xor (FLIP & FLIP & FLIP & FLIP & FLIP); + vp <= V(7 downto 3) xor (FLIP & FLIP & FLIP & FLIP & FLIP); + + sel <= not ( (H(5) xor H(4)) or (H(5) xor H(6)) ); + y157_bus <= '0' & H(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp when sel='1' else x"FF" & H(6 downto 4) & H(2); + y257_bus <= y157_bus when H(8)='0' else '0' & H(2) & vp & hp; + AB <= y257_bus when H(1) = '1' else (others => 'Z'); + +end RTL; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/sega_decode.vhd b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/sega_decode.vhd new file mode 100644 index 00000000..8ae8141d --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/sega_decode.vhd @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------- +-- Pengo decode table +-- /* opcode (M1=0) data (M1=1) address */ +-- /* 0 1 2 3 0 1 2 3 A12 A8 A4 A0 */ +-- { 0xa0,0x80,0xa8,0x88 }, { 0x28,0xa8,0x08,0x88 }, /* ...0...0...0...0 */ +-- { 0x28,0xa8,0x08,0x88 }, { 0xa0,0x80,0xa8,0x88 }, /* ...0...0...0...1 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...0...0...1...0 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0xa0,0x80,0xa8,0x88 }, /* ...0...0...1...1 */ +-- { 0x08,0x00,0x88,0x80 }, { 0x28,0xa8,0x08,0x88 }, /* ...0...1...0...0 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0x08,0x00,0x88,0x80 }, /* ...0...1...0...1 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...0...1...1...0 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0x00,0x08,0x20,0x28 }, /* ...0...1...1...1 */ +-- { 0x88,0x80,0x08,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...1...0...0...0 */ +-- { 0x88,0x80,0x08,0x00 }, { 0x00,0x08,0x20,0x28 }, /* ...1...0...0...1 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0x08,0x28,0x88,0xa8 }, /* ...1...0...1...0 */ +-- { 0xa0,0x80,0xa8,0x88 }, { 0xa0,0x80,0x20,0x00 }, /* ...1...0...1...1 */ +-- { 0x08,0x00,0x88,0x80 }, { 0x88,0x80,0x08,0x00 }, /* ...1...1...0...0 */ +-- { 0x00,0x08,0x20,0x28 }, { 0x88,0x80,0x08,0x00 }, /* ...1...1...0...1 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0x08,0x28,0x88,0xa8 }, /* ...1...1...1...0 */ +-- { 0x08,0x00,0x88,0x80 }, { 0xa0,0x80,0x20,0x00 } /* ...1...1...1...1 */ +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity sega_decode is + port ( + I_DEC : in std_logic; + I_CK : in std_logic; + -- + I_A : in std_logic_vector(6 downto 0); + I_D : in std_logic_vector(7 downto 0); + O_D : out std_logic_vector(7 downto 0) + ); + +end sega_decode; + +architecture rtl of sega_decode is + signal sel : std_logic_vector(6 downto 0); + signal val : std_logic_vector(2 downto 0); +begin + p_decoder : process + begin + wait until rising_edge(I_CK); + if (I_DEC = '0') then + O_D <= I_D; -- passthough + else + sel <= I_A xor ("00000" & I_D(7) & I_D(7)); + O_D(7) <= I_D(7) xor val(2); + O_D(6) <= I_D(6); + O_D(5) <= I_D(7) xor val(1); + O_D(4) <= I_D(4); + O_D(3) <= I_D(7) xor val(0); + O_D(2) <= I_D(2); + O_D(1) <= I_D(1); + O_D(0) <= I_D(0); + case sel is -- M1 A12 A8 A4 A0 D5 D3 + when "0000000" => val <= "110"; + when "0000001" => val <= "100"; + when "0000010" => val <= "111"; + when "0000011" => val <= "101"; + when "0000100" => val <= "011"; + when "0000101" => val <= "111"; + when "0000110" => val <= "001"; + when "0000111" => val <= "101"; + when "0001000" => val <= "110"; + when "0001001" => val <= "100"; + when "0001010" => val <= "010"; + when "0001011" => val <= "000"; + when "0001100" => val <= "001"; + when "0001101" => val <= "011"; + when "0001110" => val <= "101"; + when "0001111" => val <= "111"; + when "0010000" => val <= "001"; + when "0010001" => val <= "000"; + when "0010010" => val <= "101"; + when "0010011" => val <= "100"; + when "0010100" => val <= "110"; + when "0010101" => val <= "100"; + when "0010110" => val <= "010"; + when "0010111" => val <= "000"; + when "0011000" => val <= "110"; + when "0011001" => val <= "100"; + when "0011010" => val <= "010"; + when "0011011" => val <= "000"; + when "0011100" => val <= "110"; + when "0011101" => val <= "100"; + when "0011110" => val <= "010"; + when "0011111" => val <= "000"; + when "0100000" => val <= "101"; + when "0100001" => val <= "100"; + when "0100010" => val <= "001"; + when "0100011" => val <= "000"; + when "0100100" => val <= "101"; + when "0100101" => val <= "100"; + when "0100110" => val <= "001"; + when "0100111" => val <= "000"; + when "0101000" => val <= "001"; + when "0101001" => val <= "011"; + when "0101010" => val <= "101"; + when "0101011" => val <= "111"; + when "0101100" => val <= "110"; + when "0101101" => val <= "100"; + when "0101110" => val <= "111"; + when "0101111" => val <= "101"; + when "0110000" => val <= "001"; + when "0110001" => val <= "000"; + when "0110010" => val <= "101"; + when "0110011" => val <= "100"; + when "0110100" => val <= "000"; + when "0110101" => val <= "001"; + when "0110110" => val <= "010"; + when "0110111" => val <= "011"; + when "0111000" => val <= "001"; + when "0111001" => val <= "011"; + when "0111010" => val <= "101"; + when "0111011" => val <= "111"; + when "0111100" => val <= "001"; + when "0111101" => val <= "000"; + when "0111110" => val <= "101"; + when "0111111" => val <= "100"; + when "1000000" => val <= "011"; + when "1000001" => val <= "111"; + when "1000010" => val <= "001"; + when "1000011" => val <= "101"; + when "1000100" => val <= "110"; + when "1000101" => val <= "100"; + when "1000110" => val <= "111"; + when "1000111" => val <= "101"; + when "1001000" => val <= "110"; + when "1001001" => val <= "100"; + when "1001010" => val <= "010"; + when "1001011" => val <= "000"; + when "1001100" => val <= "110"; + when "1001101" => val <= "100"; + when "1001110" => val <= "111"; + when "1001111" => val <= "101"; + when "1010000" => val <= "011"; + when "1010001" => val <= "111"; + when "1010010" => val <= "001"; + when "1010011" => val <= "101"; + when "1010100" => val <= "001"; + when "1010101" => val <= "000"; + when "1010110" => val <= "101"; + when "1010111" => val <= "100"; + when "1011000" => val <= "110"; + when "1011001" => val <= "100"; + when "1011010" => val <= "010"; + when "1011011" => val <= "000"; + when "1011100" => val <= "000"; + when "1011101" => val <= "001"; + when "1011110" => val <= "010"; + when "1011111" => val <= "011"; + when "1100000" => val <= "110"; + when "1100001" => val <= "100"; + when "1100010" => val <= "010"; + when "1100011" => val <= "000"; + when "1100100" => val <= "000"; + when "1100101" => val <= "001"; + when "1100110" => val <= "010"; + when "1100111" => val <= "011"; + when "1101000" => val <= "001"; + when "1101001" => val <= "011"; + when "1101010" => val <= "101"; + when "1101011" => val <= "111"; + when "1101100" => val <= "110"; + when "1101101" => val <= "100"; + when "1101110" => val <= "010"; + when "1101111" => val <= "000"; + when "1110000" => val <= "101"; + when "1110001" => val <= "100"; + when "1110010" => val <= "001"; + when "1110011" => val <= "000"; + when "1110100" => val <= "101"; + when "1110101" => val <= "100"; + when "1110110" => val <= "001"; + when "1110111" => val <= "000"; + when "1111000" => val <= "001"; + when "1111001" => val <= "011"; + when "1111010" => val <= "101"; + when "1111011" => val <= "111"; + when "1111100" => val <= "110"; + when "1111101" => val <= "100"; + when "1111110" => val <= "010"; + when "1111111" => val <= "000"; + when others => null; + end case; + end if; + end process; +end rtl; diff --git a/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/ManiacMiner_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/MrTNT.qpf b/Arcade/Pacman Hardware/MrTNT_MiST/MrTNT.qpf new file mode 100644 index 00000000..11f72dde --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/MrTNT.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "MrTNT" diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/MrTNT.qsf b/Arcade/Pacman Hardware/MrTNT_MiST/MrTNT.qsf new file mode 100644 index 00000000..d2244a4a --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/MrTNT.qsf @@ -0,0 +1,164 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:14:41 November 10, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# MrTNT_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY MrTNT +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------- +# start ENTITY(MrTNT) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(MrTNT) +# ----------------- +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrTNT.sv +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/README.txt b/Arcade/Pacman Hardware/MrTNT_MiST/README.txt new file mode 100644 index 00000000..d59b2005 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Mr.TNT port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/Release/MrTNT.rbf b/Arcade/Pacman Hardware/MrTNT_MiST/Release/MrTNT.rbf new file mode 100644 index 00000000..e91c94f3 Binary files /dev/null and b/Arcade/Pacman Hardware/MrTNT_MiST/Release/MrTNT.rbf differ diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/clean.bat b/Arcade/Pacman Hardware/MrTNT_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv new file mode 100644 index 00000000..b93c50bd --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/MrTNT.sv @@ -0,0 +1,190 @@ +//============================================================================ +// Arcade: Mr.TNT +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module MrTNT +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "MR. TNT;;", + "O2,Joystick Control,Normal,Upright;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(~reset), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_down = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[7] | joystick_0[0] | joystick_1[0]; +wire m_left = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_right = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[4] | joystick_0[3] | joystick_1[3]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4];//btn_fire | joy[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +pacman mrtnt +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + .dipsw_reg(8'b0_1_11_00_11), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..ca003047 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"9C",X"63",X"41",X"9C",X"BE",X"BE",X"41",X"00",X"41",X"14",X"36",X"41",X"63",X"63",X"14",X"00", + X"41",X"41",X"FF",X"00",X"41",X"41",X"FF",X"00",X"00",X"22",X"77",X"00",X"00",X"00",X"77",X"00", + X"41",X"FF",X"DD",X"63",X"C9",X"77",X"DD",X"00",X"63",X"14",X"55",X"22",X"77",X"36",X"14",X"00", + X"36",X"C9",X"C9",X"22",X"FF",X"63",X"C9",X"00",X"14",X"14",X"77",X"00",X"36",X"14",X"55",X"00", + X"14",X"14",X"FF",X"9C",X"FF",X"9C",X"14",X"00",X"00",X"63",X"77",X"00",X"77",X"41",X"36",X"00", + X"BE",X"41",X"41",X"22",X"FF",X"63",X"41",X"00",X"00",X"55",X"55",X"77",X"55",X"77",X"55",X"00", + X"36",X"C9",X"C9",X"BE",X"FF",X"FF",X"C9",X"00",X"00",X"36",X"14",X"41",X"14",X"63",X"14",X"00", + X"00",X"77",X"88",X"00",X"00",X"00",X"FF",X"00",X"36",X"14",X"55",X"36",X"77",X"36",X"14",X"00", + X"36",X"C9",X"DD",X"36",X"77",X"C9",X"DD",X"00",X"00",X"55",X"14",X"63",X"63",X"77",X"14",X"00", + X"9C",X"C9",X"EB",X"00",X"BE",X"C9",X"C9",X"00",X"63",X"14",X"14",X"63",X"77",X"77",X"14",X"00", + X"F0",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"F0",X"F1",X"FF",X"F1",X"F1",X"F1",X"F1",X"FF",X"F1", + X"F0",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"F0",X"F0",X"F1",X"F0",X"F1",X"F0",X"F1",X"F1",X"F1", + X"F0",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"F0",X"F1",X"F1",X"F1",X"F0",X"F1",X"F0",X"F1",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"FF",X"F0",X"F1",X"F0",X"F1",X"FF",X"F1", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"FF",X"F1",X"F0",X"F1",X"F0",X"FF",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"F1",X"F1",X"F1",X"F1",X"F1",X"F1", + X"F0",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"F0",X"F0",X"FF",X"F0",X"F0",X"F0",X"F0",X"FF",X"F0", + X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + 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X"9E",X"34",X"4A",X"75",X"07",X"6A",X"22",X"34",X"9E",X"34",X"4A",X"74",X"07",X"6A",X"23",X"34", + X"B3",X"B3",X"B3",X"57",X"6F",X"6F",X"6F",X"6A",X"75",X"B3",X"B3",X"B3",X"34",X"6F",X"6F",X"6F", + X"77",X"B1",X"F7",X"7E",X"B5",X"F5",X"44",X"01",X"F5",X"9E",X"02",X"F5",X"86",X"27",X"17",X"5F", + X"02",X"68",X"68",X"68",X"B3",X"B3",X"B3",X"B3",X"68",X"35",X"6A",X"20",X"B1",X"09",X"03",X"27", + X"B3",X"B5",X"B3",X"45",X"0F",X"C8",X"0F",X"B9",X"B5",X"B5",X"0F",X"0F",X"42",X"34",X"B1",X"B1", + X"B5",X"B5",X"0F",X"0F",X"86",X"90",X"B1",X"B1",X"B5",X"B5",X"0F",X"28",X"FA",X"4C",X"B1",X"B1", + X"B5",X"B5",X"28",X"28",X"3E",X"A8",X"B1",X"B1",X"B5",X"B5",X"28",X"29",X"9A",X"64",X"B1",X"B1", + X"B5",X"B5",X"29",X"29",X"56",X"C0",X"B1",X"B1",X"B5",X"B5",X"29",X"29",X"B2",X"B3",X"B1",X"B1", + X"B5",X"B5",X"29",X"29",X"B4",X"B5",X"B1",X"B1",X"D5",X"26",X"6F",X"46",X"4F",X"01",X"09",X"00", + X"BD",X"6F",X"7D",X"40",X"52",X"09",X"4F",X"01",X"D1",X"BD",X"46",X"55",X"72",X"52",X"00",X"77", + X"B1",X"3F",X"BE",X"09",X"7D",X"B1",X"03",X"C6",X"34",X"B3",X"16",X"28",X"B3",X"3E",X"B0",X"13", + X"09",X"86",X"34",X"5F",X"A8",X"0F",X"7B",X"0B",X"7A",X"0B",X"0F",X"00",X"A6",X"6E",X"5F",X"A6", + X"0F",X"60",X"68",X"09",X"5F",X"4A",X"02",X"C6",X"34",X"43",X"3E",X"DE",X"B3",X"09",X"28",X"13", + X"41",X"05",X"13",X"4E",X"DF",X"00",X"01",X"10",X"BD",X"DE",X"AF",X"60",X"C8",X"13",X"4A",X"60", + X"09",X"9D",X"13",X"01",X"9C",X"13",X"41",X"05",X"00",X"C8",X"10",X"4A",X"4E",X"AF",X"BD",X"9C", + X"13",X"AB",X"05",X"60",X"60",X"34",X"09",X"EB",X"09",X"3E",X"34",X"74",X"C6",X"28",X"B3",X"09", + X"AA",X"13",X"41",X"C9",X"34",X"6A",X"FB",X"34",X"DD",X"0B",X"0E",X"0B",X"B5",X"0B",X"40",X"BB", + X"2A",X"FE",X"34",X"D0",X"8B",X"04",X"D9",X"B3",X"0F",X"6C",X"0F",X"C8",X"B3",X"B5",X"6C",X"45", + X"B5",X"6A",X"41",X"34",X"AA",X"C8",X"D0",X"6C",X"4A",X"08",X"34",X"B3",X"C8",X"35",X"09",X"96", + X"09",X"3E",X"34",X"42",X"C6",X"28",X"B3",X"6A",X"C9",X"C9",X"6C",X"6A",X"34",X"34",X"4A",X"8E"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..4bfa195f --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..e0dd3c1e --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"DB",X"AF",X"06",X"20",X"09",X"00",X"50",X"5F",X"0B",X"10",X"FC",X"ED",X"56",X"19",X"D9",X"67", + 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X"64",X"93",X"17",X"D2",X"B8",X"C4",X"44",X"64",X"06",X"02",X"D2",X"A8",X"C4",X"64",X"14",X"02", + X"D0",X"E4",X"33",X"02",X"DD",X"05",X"D2",X"62",X"CA",X"15",X"D3",X"30",X"D0",X"62",X"1C",X"02", + X"D5",X"C3",X"F1",X"61",X"18",X"02",X"FC",X"08",X"F0",X"61",X"81",X"17",X"FD",X"08",X"C5",X"47"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..ce051ca2 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"DB",X"AF",X"06",X"20",X"09",X"00",X"50",X"5F",X"0B",X"10",X"FC",X"ED",X"56",X"19",X"D9",X"67", + X"C3",X"C7",X"02",X"3A",X"8E",X"64",X"FE",X"00",X"E0",X"47",X"3E",X"30",X"09",X"35",X"40",X"5F", + X"2B",X"10",X"FC",X"E1",X"3A",X"8F",X"64",X"FE",X"00",X"E0",X"47",X"3E",X"30",X"09",X"02",X"40", + X"5F",X"0B",X"10",X"FC",X"E1",X"40",X"00",X"00",X"20",X"F1",X"F5",X"CD",X"FD",X"CD",X"AF",X"1A", + X"00",X"50",X"2A",X"24",X"64",X"3A",X"26",X"64",X"5F",X"2A",X"27",X"64",X"3A",X"11",X"64",X"5F", + X"2A",X"14",X"64",X"3A",X"16",X"64",X"5F",X"2A",X"17",X"64",X"3A",X"31",X"64",X"5F",X"2A",X"34", + X"64",X"3A",X"36",X"64",X"5F",X"2A",X"37",X"64",X"3A",X"09",X"64",X"5F",X"2A",X"0C",X"64",X"3A", + X"0E",X"64",X"5F",X"2A",X"0F",X"64",X"3A",X"29",X"64",X"5F",X"2A",X"2C",X"64",X"3A",X"2E",X"64", + X"5F",X"2A",X"2F",X"64",X"3A",X"19",X"64",X"5F",X"2A",X"1C",X"64",X"3A",X"1E",X"64",X"5F",X"2A", + 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X"91",X"6F",X"13",X"32",X"B0",X"4F",X"E1",X"6F",X"0E",X"00",X"32",X"95",X"6F",X"13",X"32",X"B4", + X"4F",X"E1",X"77",X"16",X"00",X"7B",X"96",X"77",X"7A",X"0B",X"B6",X"57",X"EB",X"E1",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"93",X"1B",X"93",X"1B",X"58",X"0E",X"24",X"2A",X"B4",X"03",X"F8",X"29",X"EC",X"2E",X"48",X"2F", + X"00",X"00",X"F1",X"13",X"9D",X"0C",X"65",X"0E",X"FF",X"7F",X"2F",X"03",X"BA",X"06",X"00",X"04", + X"FC",X"03",X"F7",X"12",X"8F",X"03",X"D5",X"03",X"F3",X"03",X"A5",X"27",X"EA",X"03",X"DF",X"03", + X"A2",X"03",X"00",X"12",X"25",X"12",X"32",X"12",X"E7",X"16",X"CA",X"03",X"21",X"13",X"1B",X"13", + X"F2",X"E7",X"16",X"DA",X"20",X"D2",X"67",X"70",X"A2",X"03",X"F2",X"A8",X"C4",X"52",X"67",X"57", + X"A5",X"27",X"85",X"C7",X"66",X"61",X"66",X"52",X"41",X"57",X"00",X"12",X"97",X"E5",X"52",X"54", + X"8D",X"31",X"96",X"10",X"C5",X"64",X"54",X"61",X"54",X"56",X"32",X"A3",X"E5",X"71",X"53",X"AD", + X"13",X"96",X"40",X"C2",X"55",X"53",X"98",X"14",X"F2",X"90",X"C7",X"66",X"61",X"52",X"54",X"53", + X"D3",X"31",X"95",X"C5",X"64",X"54",X"61",X"54",X"53",X"06",X"34",X"A4",X"E4",X"52",X"53",X"1C", + X"12",X"F1",X"38",X"C1",X"52",X"53",X"89",X"14",X"F1",X"28",X"C5",X"43",X"41",X"50",X"53",X"2E", + X"16",X"A1",X"D0",X"53",X"78",X"00",X"F8",X"18",X"C1",X"64",X"53",X"9A",X"34",X"F1",X"08",X"D2", + X"60",X"53",X"89",X"12",X"B7",X"E4",X"60",X"53",X"C1",X"12",X"B6",X"D4",X"45",X"53",X"DF",X"34", + X"F0",X"C0",X"C7",X"45",X"53",X"94",X"00",X"B2",X"E6",X"67",X"61",X"54",X"43",X"45",X"53",X"0F", + X"12",X"8A",X"00",X"C6",X"43",X"53",X"26",X"35",X"D1",X"1F",X"D2",X"41",X"64",X"41",X"43",X"53", + X"6B",X"35",X"8F",X"C3",X"42",X"53",X"78",X"30",X"F4",X"B0",X"42",X"D4",X"53",X"52",X"5F",X"15", + X"F7",X"C4",X"52",X"52",X"D1",X"12",X"D2",X"4F",X"C1",X"43",X"52",X"52",X"B8",X"00",X"D1",X"27", + X"C3",X"52",X"52",X"59",X"16",X"F1",X"20",X"C1",X"52",X"52",X"C2",X"00",X"D1",X"37",X"D2",X"52", + X"CD",X"00",X"F1",X"30",X"C4",X"64",X"52",X"F6",X"00",X"D2",X"6F",X"C1",X"43",X"64",X"52",X"4D", + X"16",X"D1",X"07",X"C3",X"64",X"52",X"49",X"12",X"F1",X"00",X"C1",X"64",X"52",X"DA",X"00",X"D1", + X"17",X"E4",X"52",X"20",X"01",X"F1",X"10",X"E6",X"54",X"45",X"52",X"D0",X"00",X"D2",X"45",X"E1", + X"54",X"45",X"52",X"91",X"12",X"D2",X"65",X"D4",X"45",X"52",X"15",X"01",X"D7",X"E1",X"C5",X"65", + X"55",X"53",X"45",X"52",X"01",X"01",X"8D",X"C5",X"56",X"52",X"45",X"53",X"45",X"52",X"7D",X"16", + X"8C",X"01",X"D3",X"45",X"52",X"D6",X"00",X"F0",X"80",X"D4",X"41",X"45",X"50",X"45",X"52",X"40", + X"01",X"A7",X"D2",X"27",X"01",X"DB",X"E0",X"53",X"55",X"50",X"51",X"01",X"F6",X"C5",X"D0",X"67", + X"50",X"2C",X"01",X"F6",X"C1",X"E7",X"50",X"0D",X"01",X"DA",X"08",X"C5",X"50",X"F9",X"00",X"DA", + X"28",X"C5",X"47",X"41",X"50",X"26",X"17",X"A0",X"30",X"D0",X"63",X"16",X"DA",X"18",X"E1",X"54", + X"55",X"67",X"5F",X"01",X"D2",X"8B",X"C4",X"54",X"55",X"67",X"66",X"15",X"D2",X"AB",X"D4",X"55", + X"67",X"A4",X"01",X"C9",X"41",X"D2",X"61",X"54",X"67",X"71",X"16",X"D2",X"9B",X"D2",X"44",X"54", + X"67",X"7C",X"01",X"D2",X"BB",X"C7",X"52",X"67",X"E7",X"14",X"81",X"D2",X"67",X"85",X"15",X"F2", + X"98",X"F2",X"66",X"43",X"12",X"DA",X"00",X"D0",X"67",X"66",X"7F",X"31",X"D1",X"00",X"D4",X"53", + X"61",X"64",X"67",X"66",X"88",X"00",X"87",X"C7",X"45",X"66",X"45",X"35",X"D2",X"44",X"D2",X"60", + X"43",X"66",X"8B",X"01",X"B4",X"C3",X"66",X"03",X"33",X"DA",X"10",X"C5",X"65",X"41",X"66",X"D4", + X"01",X"AB",X"C4",X"67",X"65",X"78",X"34",X"B5",X"C7",X"45",X"65",X"8E",X"17",X"96",X"D8",X"C5", + X"65",X"38",X"35",X"96",X"FF",X"E7",X"52",X"43",X"41",X"65",X"F5",X"32",X"91",X"E5",X"6F",X"17", + X"DA",X"38",X"E7",X"64",X"EA",X"32",X"B1",X"D4",X"53",X"61",X"64",X"19",X"15",X"86",X"D2",X"61", + X"44",X"64",X"A2",X"17",X"D2",X"98",X"E1",X"44",X"64",X"F7",X"14",X"D2",X"88",X"D2",X"44",X"44", + X"64",X"93",X"17",X"D2",X"B8",X"C4",X"44",X"64",X"06",X"02",X"D2",X"A8",X"C4",X"64",X"14",X"02", + X"D0",X"E4",X"33",X"02",X"DD",X"05",X"D2",X"62",X"CA",X"15",X"D3",X"30",X"D0",X"62",X"1C",X"02", + X"D5",X"C3",X"F1",X"61",X"18",X"02",X"FC",X"08",X"F0",X"61",X"81",X"17",X"FD",X"08",X"C5",X"47"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/build_id.v new file mode 100644 index 00000000..81162513 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171113" +`define BUILD_TIME "104226" diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/osd.v b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..9b976d32 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman.vhd @@ -0,0 +1,629 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN is +generic ( + MRTNT : std_logic := '1' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data_out : std_logic_vector(7 downto 0); + signal rom_data : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + rom_data <= program_rom_dinl when cpu_addr(15) = '0' else program_rom_dinh; + rom_data_out <= rom_data(7 downto 6) & rom_data(3) & rom_data(4) & rom_data(5) & rom_data(2 downto 0) when MRTNT = '1' else rom_data; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data_out, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data_out; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data_out; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..895304e9 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_video.vhd @@ -0,0 +1,366 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/MrTNT_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/MrTNT_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/MSPacman.qpf b/Arcade/Pacman Hardware/MsPacman_MiST/MSPacman.qpf new file mode 100644 index 00000000..c4a7439a --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/MSPacman.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "MSPacman" diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/MSPacman.qsf b/Arcade/Pacman Hardware/MsPacman_MiST/MSPacman.qsf new file mode 100644 index 00000000..63fc5594 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/MSPacman.qsf @@ -0,0 +1,171 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:26:45 November 13, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# MSPacman_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_rom_descrambler.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/MSPacman.sv +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY MSPacman +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ---------------------- +# start ENTITY(MSPacman) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(MSPacman) +# -------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/README.txt b/Arcade/Pacman Hardware/MsPacman_MiST/README.txt new file mode 100644 index 00000000..d825ff57 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Ms. Pacman port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE,CTRL : Slow +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/Release/MSPacman.rbf b/Arcade/Pacman Hardware/MsPacman_MiST/Release/MSPacman.rbf new file mode 100644 index 00000000..7464d251 Binary files /dev/null and b/Arcade/Pacman Hardware/MsPacman_MiST/Release/MSPacman.rbf differ diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/clean.bat b/Arcade/Pacman Hardware/MsPacman_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv new file mode 100644 index 00000000..1a0e78dc --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/MSPacman.sv @@ -0,0 +1,190 @@ +//============================================================================ +// Arcade: Ms.Pacman +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module MSPacman +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Ms Pacman;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire;// = kbjoy[0] | joystick_0[4] | joystick_1[4]; //Reset the Game +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +pacman mrspacman +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + .dipsw_reg(8'b0_1_00_11_01), + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..834eafbd --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"EE",X"11",X"11",X"33",X"EE",X"CC",X"00",X"11",X"33",X"66",X"44",X"44",X"33",X"11",X"00", + X"11",X"11",X"FF",X"FF",X"11",X"11",X"00",X"00",X"00",X"00",X"77",X"77",X"22",X"00",X"00",X"00", + X"11",X"99",X"DD",X"DD",X"FF",X"77",X"33",X"00",X"33",X"77",X"55",X"44",X"44",X"66",X"22",X"00", + X"66",X"FF",X"99",X"99",X"99",X"33",X"22",X"00",X"44",X"66",X"77",X"55",X"44",X"44",X"00",X"00", + X"44",X"FF",X"FF",X"44",X"44",X"CC",X"CC",X"00",X"00",X"77",X"77",X"66",X"33",X"11",X"00",X"00", + X"EE",X"FF",X"11",X"11",X"11",X"33",X"22",X"00",X"00",X"55",X"55",X"55",X"55",X"77",X"77",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"EE",X"00",X"00",X"44",X"44",X"44",X"66",X"33",X"11",X"00", + X"00",X"00",X"88",X"FF",X"77",X"00",X"00",X"00",X"66",X"77",X"55",X"44",X"44",X"66",X"66",X"00", + X"66",X"77",X"DD",X"DD",X"99",X"99",X"66",X"00",X"00",X"33",X"44",X"44",X"55",X"77",X"33",X"00", + X"CC",X"EE",X"BB",X"99",X"99",X"99",X"00",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"33",X"00", + X"FF",X"FF",X"44",X"44",X"44",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"66",X"33",X"11",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"FF",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"77",X"00", + X"22",X"33",X"11",X"11",X"33",X"EE",X"CC",X"00",X"22",X"66",X"44",X"44",X"66",X"33",X"11",X"00", + X"CC",X"EE",X"33",X"11",X"11",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"44",X"77",X"77",X"00", + X"11",X"99",X"99",X"99",X"FF",X"FF",X"00",X"00",X"44",X"44",X"44",X"44",X"77",X"77",X"00",X"00", + X"00",X"88",X"88",X"88",X"88",X"FF",X"FF",X"00",X"44",X"44",X"44",X"44",X"44",X"77",X"77",X"00", + X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"0C",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0C",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"07",X"03", + X"0C",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0C",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"07",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"00",X"77",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"DD",X"FF",X"33", + X"CC",X"C0",X"E0",X"68",X"80",X"00",X"00",X"00",X"00",X"00",X"30",X"33",X"11",X"00",X"00",X"00", + X"00",X"33",X"EE",X"FF",X"FF",X"77",X"00",X"00",X"FF",X"3B",X"77",X"FE",X"E9",X"F8",X"30",X"00", + X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"CC",X"00",X"00",X"11",X"33",X"30",X"00",X"00",X"00", + X"00",X"77",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"DD",X"FF",X"33", + X"CC",X"C0",X"E0",X"68",X"80",X"00",X"00",X"00",X"00",X"00",X"30",X"33",X"11",X"00",X"00",X"00", + X"00",X"33",X"EE",X"FF",X"FF",X"77",X"00",X"00",X"FF",X"3B",X"77",X"FE",X"E9",X"F8",X"30",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..4bfa195f --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..333a80cb --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"3E",X"3F",X"ED",X"47",X"C3",X"0B",X"23",X"77",X"23",X"10",X"FC",X"C9",X"C3",X"0E",X"07", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"78",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"C9", + X"E1",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"E9",X"E1",X"46",X"23",X"4E",X"23",X"E5",X"18",X"12", + X"11",X"90",X"4C",X"06",X"10",X"C3",X"51",X"00",X"AF",X"32",X"00",X"50",X"32",X"07",X"50",X"C3", + X"38",X"00",X"2A",X"80",X"4C",X"70",X"2C",X"71",X"2C",X"20",X"02",X"2E",X"C0",X"22",X"80",X"4C", + X"C9",X"1A",X"A7",X"28",X"06",X"1C",X"1C",X"1C",X"10",X"F7",X"C9",X"E1",X"06",X"03",X"7E",X"12", + X"23",X"1C",X"10",X"FA",X"E9",X"C3",X"2D",X"20",X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07", + X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"10",X"11",X"12",X"13",X"14",X"01",X"03",X"04", + X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"10",X"11",X"14",X"F5",X"32",X"C0", + X"50",X"AF",X"32",X"00",X"50",X"F3",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5",X"21",X"8C",X"4E", + X"11",X"50",X"50",X"01",X"10",X"00",X"ED",X"B0",X"3A",X"CC",X"4E",X"A7",X"3A",X"CF",X"4E",X"20", + X"03",X"3A",X"9F",X"4E",X"32",X"45",X"50",X"3A",X"DC",X"4E",X"A7",X"3A",X"DF",X"4E",X"20",X"03", + X"3A",X"AF",X"4E",X"32",X"4A",X"50",X"3A",X"EC",X"4E",X"A7",X"3A",X"EF",X"4E",X"20",X"03",X"3A", + X"BF",X"4E",X"32",X"4F",X"50",X"21",X"02",X"4C",X"11",X"22",X"4C",X"01",X"1C",X"00",X"ED",X"B0", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..3e443f07 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,790 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 12287) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"53",X"22",X"00",X"10",X"5B",X"74",X"89",X"44",X"95",X"5A",X"53",X"17",X"F0",X"AC",X"E4",X"00", + X"5C",X"A8",X"53",X"17",X"D8",X"EC",X"3F",X"DE",X"17",X"AA",X"A8",X"3F",X"C4",X"22",X"10",X"22", + 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X"E6",X"E6",X"E6",X"6E",X"0F",X"6E",X"01",X"02",X"04",X"02",X"02",X"02",X"02",X"04",X"08",X"08", + X"08",X"08",X"08",X"0C",X"04",X"04",X"04",X"04",X"0C",X"04",X"04",X"04",X"04",X"0C",X"08",X"0A", + X"81",X"88",X"89",X"4E",X"C1",X"8A",X"C9",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"C9",X"8C",X"C9",X"8C",X"C9",X"8C",X"B4",X"20",X"F7",X"0F",X"00",X"04",X"4E",X"00", + X"D2",X"02",X"0C",X"42",X"00",X"00",X"04",X"00",X"D2",X"06",X"0C",X"46",X"00",X"00",X"04",X"00", + X"28",X"00",X"0C",X"40",X"04",X"00",X"44",X"00",X"B0",X"08",X"00",X"00",X"00",X"00",X"40",X"00", + X"94",X"52",X"5C",X"1E",X"10",X"6E",X"4F",X"6E",X"16",X"E6",X"5A",X"1A",X"5C",X"6E",X"4F",X"6E", + X"10",X"10",X"10",X"10",X"6E",X"0B",X"6E",X"01",X"52",X"2C",X"10",X"10",X"6E",X"0F",X"6E",X"01", + X"1A",X"1A",X"98",X"6E",X"4F",X"6E",X"01",X"48",X"6E",X"4F",X"6E",X"01",X"E4",X"04",X"5C",X"FD", + X"DE",X"08",X"8D",X"EC",X"47",X"EC",X"48",X"00",X"41",X"A8",X"67",X"EC",X"4B",X"A8",X"A3",X"EC", + X"DB",X"7C",X"10",X"DB",X"3C",X"12",X"AC",X"03",X"53",X"4A",X"6F",X"E3",X"F5",X"22",X"EE",X"0C", + X"3C",X"02",X"AA",X"DB",X"7C",X"04",X"DB",X"3C",X"82",X"AA",X"DB",X"7C",X"84",X"DB",X"3C",X"86", + X"AA",X"DB",X"7C",X"24",X"DB",X"3C",X"26",X"AC",X"DB",X"7C",X"A4",X"DB",X"3C",X"A6",X"AC",X"05", + X"7C",X"14",X"DB",X"3C",X"16",X"AC",X"05",X"DB",X"94",X"DB",X"3C",X"96",X"AC",X"07",X"53",X"91", + X"10",X"9A",X"94",X"16",X"50",X"52",X"5C",X"E6",X"51",X"04",X"10",X"5A",X"12",X"16",X"50",X"52", + X"6E",X"01",X"51",X"04",X"10",X"94",X"5E",X"5A",X"6E",X"07",X"6E",X"01",X"2A",X"01",X"03",X"0B", + X"90",X"1A",X"94",X"10",X"90",X"12",X"16",X"E6",X"12",X"5C",X"6E",X"43",X"6E",X"01",X"6E",X"81", + X"6E",X"4F",X"6E",X"81",X"A0",X"01",X"10",X"10",X"43",X"45",X"4B",X"4D",X"6E",X"43",X"6E",X"81", + X"14",X"5E",X"5C",X"9A",X"96",X"10",X"10",X"5C",X"06",X"14",X"5E",X"5C",X"9A",X"96",X"10",X"6E", + X"56",X"5A",X"12",X"5C",X"6E",X"4F",X"6E",X"01",X"10",X"6E",X"4F",X"6E",X"01",X"4C",X"06",X"9A", + X"6E",X"01",X"44",X"04",X"A0",X"A0",X"A0",X"6E",X"96",X"9A",X"56",X"1A",X"2C",X"6E",X"0B",X"6E", + X"22",X"B5",X"E2",X"9F",X"84",X"26",X"86",X"FC",X"B4",X"D5",X"7F",X"0A",X"02",X"7F",X"80",X"88", + X"3E",X"61",X"67",X"69",X"49",X"0D",X"BC",X"BA",X"F4",X"F0",X"F0",X"BC",X"B6",X"78",X"65",X"61", + X"BA",X"BC",X"BE",X"F0",X"B2",X"B6",X"B8",X"BA",X"70",X"65",X"63",X"65",X"74",X"30",X"45",X"BC", + X"B2",X"70",X"70",X"32",X"36",X"74",X"61",X"78",X"2C",X"0F",X"B0",X"B1",X"CB",X"E8",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"10",X"10",X"10",X"90",X"52",X"5C",X"56",X"D2",X"96",X"10",X"90",X"12",X"16",X"E6",X"5A",X"12", + X"10",X"10",X"52",X"5C",X"56",X"D2",X"10",X"10",X"A2",X"E2",X"E0",X"A0",X"E4",X"A2",X"E2",X"E0", + X"10",X"10",X"10",X"10",X"96",X"9A",X"1A",X"6E",X"52",X"5E",X"94",X"10",X"10",X"10",X"10",X"6E", + X"50",X"10",X"10",X"10",X"10",X"10",X"6E",X"4F",X"16",X"50",X"12",X"96",X"1A",X"10",X"6E",X"4F", + X"02",X"02",X"06",X"02",X"02",X"08",X"02",X"02",X"08",X"C0",X"0A",X"02",X"02",X"02",X"8E",X"04", + X"BC",X"02",X"02",X"02",X"02",X"06",X"02",X"02",X"04",X"08",X"04",X"08",X"46",X"02",X"02",X"02", + X"04",X"04",X"4C",X"04",X"08",X"04",X"08",X"04",X"06",X"02",X"02",X"02",X"06",X"02",X"02",X"06", + X"10",X"10",X"4C",X"EA",X"EC",X"80",X"15",X"16",X"5E",X"E4",X"AC",X"88",X"C4",X"2F",X"51",X"86", + X"C8",X"B0",X"47",X"40",X"00",X"02",X"0C",X"00",X"9C",X"00",X"04",X"44",X"0E",X"06",X"48",X"00", + X"24",X"02",X"02",X"0C",X"00",X"02",X"0E",X"00",X"00",X"9E",X"D8",X"32",X"3E",X"7A",X"B8",X"F6", + X"99",X"E6",X"B7",X"E6",X"D0",X"E8",X"8B",X"E8",X"B7",X"44",X"B9",X"04",X"81",X"F8",X"F6",X"F4", + X"B6",X"B4",X"83",X"61",X"41",X"30",X"54",X"58",X"83",X"8B",X"41",X"8B",X"8B",X"C1",X"89",X"8F", + X"53",X"EC",X"53",X"7F",X"C8",X"48",X"EC",X"30",X"8D",X"17",X"4D",X"0A",X"7F",X"C8",X"4A",X"17", + X"17",X"4D",X"0A",X"7F",X"C8",X"6E",X"17",X"4D",X"C8",X"A6",X"17",X"4D",X"0A",X"7F",X"C8",X"4C", + X"0A",X"6F",X"A4",X"88",X"5C",X"17",X"F8",X"0A",X"5E",X"5E",X"57",X"03",X"0C",X"00",X"DB",X"22", + X"DB",X"7C",X"00",X"DB",X"3C",X"02",X"AC",X"0F",X"DB",X"7C",X"20",X"DB",X"3C",X"22",X"AC",X"45", + X"14",X"A0",X"14",X"80",X"14",X"B1",X"12",X"91",X"12",X"A0",X"12",X"80",X"12",X"B1",X"10",X"91", + X"10",X"69",X"10",X"67",X"10",X"65",X"10",X"63",X"12",X"52",X"12",X"72",X"12",X"43",X"12",X"63", + X"14",X"52",X"14",X"72",X"14",X"43",X"14",X"63",X"14",X"5B",X"14",X"5D",X"14",X"5F",X"14",X"91", + X"14",X"5B",X"14",X"5D",X"14",X"5F",X"14",X"91",X"53",X"00",X"00",X"A0",X"4B",X"00",X"BA",X"B6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/build_id.v new file mode 100644 index 00000000..c283ed44 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171113" +`define BUILD_TIME "103258" diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/osd.v b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..6ccb7094 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman.vhd @@ -0,0 +1,619 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN is +generic ( + MRTNT : std_logic := '0'; -- 1 to descramble Mr TNT ROMs, 0 otherwise + MSPACMAN : std_logic := '1' -- set to 1 when using Ms Pacman ROMs, 0 otherwise +); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + u_program_rom: work.rom_descrambler + generic map ( + MRTNT => MRTNT, + MSPACMAN => MSPACMAN + ) + port map( + CLK => clk, + cpu_m1_l => cpu_m1_l, + addr => cpu_addr, + data => rom_data + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd new file mode 100644 index 00000000..b8d20de6 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_rom_descrambler.vhd @@ -0,0 +1,446 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) d18c7db (gmail) - May 2013 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- + + +-- The following comments and source code in the comments are from MAME source code and are +-- included here to help make sense of the logic used in the VHDL address mapper and descrambler +-- +--/************************************ +-- * +-- * Ms. Pac-Man +-- * +-- ************************************/ +-- +--/* +-- Ms. Pac-Man has an auxiliary PCB with ribbon cable that plugs into the Z-80 CPU socket of a Pac-Man main PCB. Also the +-- graphics ROMs at 5E, 5F on the main board are replaced. +-- +-- The aux board contains three ROMs (two 2532 at U6, U7 and one 2716 at U5), a Z-80, and four PAL/HAL logic chips. +-- +-- The aux board logic decodes the Z-80 address and determines whether to enable the main board ROMs (containing Pac-Man +-- code) or the aux board ROMs (containing Ms. Pac-Man code). Normally the Pac-Man ROMs reside at address 0x0000-0x3fff +-- and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). The aux board logic modifies the address map and +-- enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. Furthermore there are forty 8-byte "patch" +-- regions which reside in the 0x0000-0x2fff address range. Any access to these patch addresses will disable the Pac-Man +-- ROMs and enable the aux board ROM. Aux board ROM addresses 0x8000-0x81ef are mapped onto the patch regions. These +-- patches typically insert jumps to new code above 0x8000. +-- +-- The aux board logic also acts as a software protection circuit which inhibits dumping of the ROMs (e.g., using a +-- microprocessor emulator system). There are several "trap" address regions which enable and disable the decode +-- functions. In order to properly operate as Ms. Pac-Man you must access one of the "latch set" trap addresses. This +-- enables the decode. If a "latch clear" address is accessed then decode is disabled and all you get is Pac-Man. For +-- more info see U.S. Patent 4,525,599 "Software protection methods and apparatus". +-- +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 +-- +-- Any memory access will trigger the trap behavior: instruction fetch, data read, data write. The latch clear addresses +-- should never be accessed during normal Ms. Pac-Man operation, so when the circuitry detects an access it clears the +-- latch and prevents any further dumping of the aux board ROMs. +-- +-- The Pac-Man self-test code does a checksum of the ROM 0x0000-0x2fff. This works because the checksum routine walks the +-- ROM starting from the low address and hits the latch clear trap at 0x0038 prior to encountering any of the patch +-- regions. The decode stays disabled for the rest of the checksum routine, and thus the checksum is calculated for the +-- Pac-Man ROMs with no patches applied. +-- +-- During normal operation every VBLANK (60.6Hz) interrupt will fetch its interrupt vector from the 0x3ff8 trap region, so +-- the latch is continually being enabled. +-- +-- In a further attempt to thwart copying, the aux board ROMs have a simple encryption scheme: their address and data +-- lines are bit flipped (i.e., wired in a nonstandard fashion). The specific bit flips were selected to minimize the +-- vias required to lay out the aux PCB. +--*/ + +-- +--static void mspacman_install_patches(UINT8 *ROM) +--{ +-- int i; +-- +-- /* copy forty 8-byte patches into Pac-Man code */ +-- for (i = 0; i < 8; i++) +-- { +-- ROM[0x0410+i] = ROM[0x8008+i]; +-- ROM[0x08E0+i] = ROM[0x81D8+i]; +-- ROM[0x0A30+i] = ROM[0x8118+i]; +-- ROM[0x0BD0+i] = ROM[0x80D8+i]; +-- ROM[0x0C20+i] = ROM[0x8120+i]; +-- ROM[0x0E58+i] = ROM[0x8168+i]; +-- ROM[0x0EA8+i] = ROM[0x8198+i]; +-- +-- ROM[0x1000+i] = ROM[0x8020+i]; +-- ROM[0x1008+i] = ROM[0x8010+i]; +-- ROM[0x1288+i] = ROM[0x8098+i]; +-- ROM[0x1348+i] = ROM[0x8048+i]; +-- ROM[0x1688+i] = ROM[0x8088+i]; +-- ROM[0x16B0+i] = ROM[0x8188+i]; +-- ROM[0x16D8+i] = ROM[0x80C8+i]; +-- ROM[0x16F8+i] = ROM[0x81C8+i]; +-- ROM[0x19A8+i] = ROM[0x80A8+i]; +-- ROM[0x19B8+i] = ROM[0x81A8+i]; +-- +-- ROM[0x2060+i] = ROM[0x8148+i]; +-- ROM[0x2108+i] = ROM[0x8018+i]; +-- ROM[0x21A0+i] = ROM[0x81A0+i]; +-- ROM[0x2298+i] = ROM[0x80A0+i]; +-- ROM[0x23E0+i] = ROM[0x80E8+i]; +-- ROM[0x2418+i] = ROM[0x8000+i]; +-- ROM[0x2448+i] = ROM[0x8058+i]; +-- ROM[0x2470+i] = ROM[0x8140+i]; +-- ROM[0x2488+i] = ROM[0x8080+i]; +-- ROM[0x24B0+i] = ROM[0x8180+i]; +-- ROM[0x24D8+i] = ROM[0x80C0+i]; +-- ROM[0x24F8+i] = ROM[0x81C0+i]; +-- ROM[0x2748+i] = ROM[0x8050+i]; +-- ROM[0x2780+i] = ROM[0x8090+i]; +-- ROM[0x27B8+i] = ROM[0x8190+i]; +-- ROM[0x2800+i] = ROM[0x8028+i]; +-- ROM[0x2B20+i] = ROM[0x8100+i]; +-- ROM[0x2B30+i] = ROM[0x8110+i]; +-- ROM[0x2BF0+i] = ROM[0x81D0+i]; +-- ROM[0x2CC0+i] = ROM[0x80D0+i]; +-- ROM[0x2CD8+i] = ROM[0x80E0+i]; +-- ROM[0x2CF0+i] = ROM[0x81E0+i]; +-- ROM[0x2D60+i] = ROM[0x8160+i]; +-- } +--} +-- +--DRIVER_INIT_MEMBER(pacman_state,mspacman) +--{ +-- int i; +-- UINT8 *ROM, *DROM; +-- +-- /* CPU ROMs */ +-- +-- /* Pac-Man code is in low bank */ +-- ROM = machine().root_device().memregion("maincpu")->base(); +-- +-- /* decrypted Ms. Pac-Man code is in high bank */ +-- DROM = &machine().root_device().memregion("maincpu")->base()[0x10000]; +-- +-- /* copy ROMs into decrypted bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0x0000+i] = ROM[0x0000+i]; /* pacman.6e */ +-- DROM[0x1000+i] = ROM[0x1000+i]; /* pacman.6f */ +-- DROM[0x2000+i] = ROM[0x2000+i]; /* pacman.6h */ +-- DROM[0x3000+i] = BITSWAP8(ROM[0xb000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u7 */ +-- } +-- for (i = 0; i < 0x800; i++) +-- { +-- DROM[0x8000+i] = BITSWAP8(ROM[0x8000+BITSWAP16(i,15,14,13,12,11,8,7,5,9,10,6,3,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u5 */ +-- DROM[0x8800+i] = BITSWAP8(ROM[0x9800+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +-- DROM[0x9000+i] = BITSWAP8(ROM[0x9000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +--// 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 +-- DROM[0x9800+i] = ROM[0x1800+i]; /* mirror of pacman.6f high */ +-- } +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0xa000+i] = ROM[0x2000+i]; /* mirror of pacman.6h */ +-- DROM[0xb000+i] = ROM[0x3000+i]; /* mirror of pacman.6j */ +-- } +-- /* install patches into decrypted bank */ +-- mspacman_install_patches(DROM); +-- +-- /* mirror Pac-Man ROMs into upper addresses of normal bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- ROM[0x8000+i] = ROM[0x0000+i]; +-- ROM[0x9000+i] = ROM[0x1000+i]; +-- ROM[0xa000+i] = ROM[0x2000+i]; +-- ROM[0xb000+i] = ROM[0x3000+i]; +-- } +-- +-- /* initialize the banks */ +-- machine().root_device().membank("bank1")->configure_entries(0, 2, &ROM[0x00000], 0x10000); +-- machine().root_device().membank("bank1")->set_entry(1); +--} +-- +--ROM_START( puckmana ) +-- ROM_REGION( 0x10000, "maincpu", 0 ) +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "prg7", 0x3000, 0x0800, CRC(b6289b26) SHA1(d249fa9cdde774d5fee7258147cd25fa3f4dc2b3) ) +-- ROM_LOAD( "prg8", 0x3800, 0x0800, CRC(17a88c13) SHA1(eb462de79f49b7aa8adb0cc6d31535b10550c0ce) ) +-- +--ROM_START( mspacman ) +-- ROM_REGION( 0x20000, "maincpu", 0 ) /* 64k for code+64k for decrypted code */ +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "pacman.6j", 0x3000, 0x1000, CRC(817d94e3) SHA1(d4a70d56bb01d27d094d73db8667ffb00ca69cb9) ) +-- +-- ROM_LOAD( "u5", 0x8000, 0x0800, CRC(f45fbbcd) SHA1(b26cc1c8ee18e9b1daa97956d2159b954703a0ec) ) +-- ROM_LOAD( "u6", 0x9000, 0x1000, CRC(a90e7000) SHA1(e4df96f1db753533f7d770aa62ae1973349ea4cf) ) +-- ROM_LOAD( "u7", 0xb000, 0x1000, CRC(c82cd714) SHA1(1d8ac7ad03db2dc4c8c18ade466e12032673f874) ) +-- +-- +--Normally the Pac-Man ROMs reside at address 0x0000-0x3fff and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). +--The aux board logic modifies the address map and enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity rom_descrambler is + generic ( + -- only set one of these when PACMAN is set + MRTNT : std_logic := '0'; -- set to 1 when using Mr TNT ROMs, 0 otherwise + MSPACMAN : std_logic := '0' -- set to 1 when using Ms Pacman ROMs, 0 otherwise + ); + port ( + CLK : in std_logic; + cpu_m1_l : in std_logic; + addr : in std_logic_vector(15 downto 0); + data : out std_logic_vector( 7 downto 0) + ); + +end rom_descrambler; + +architecture rtl of rom_descrambler is + signal overlay_on : std_logic := '0'; + signal rom_patched : std_logic_vector(15 downto 0); + signal rom_addr : std_logic_vector(15 downto 0); + signal rom_lo : std_logic_vector( 7 downto 0); + signal rom_hi : std_logic_vector( 7 downto 0); + signal rom_data_in : std_logic_vector( 7 downto 0); + signal rom_data_out : std_logic_vector( 7 downto 0); +begin + -- ROM at 0000 - 3FFF + u_program_rom0 : entity work.ROM_PGM_0 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_lo + ); + + -- ROM at 8000 - BFFF (Liz Wiz) + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_hi + ); + +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 + p_overlay : process + variable trap_addr : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + trap_addr := addr(15 downto 3) & "000"; + if trap_addr = x"3ff8" then + overlay_on <= '1'; + elsif + trap_addr = x"0038" or + trap_addr = x"03b0" or + trap_addr = x"1600" or + trap_addr = x"2120" or + trap_addr = x"3ff0" or + trap_addr = x"8000" or + trap_addr = x"97f0" + then + overlay_on <= '0'; + end if; + end process; + + p_decoder_comb : process(clk, rom_addr, addr, rom_data_in, rom_data_out, rom_patched, rom_hi, rom_lo, overlay_on) + variable patch_addr : std_logic_vector(15 downto 0); + begin + rom_addr <= addr; + rom_patched <= addr; + data <= rom_data_out; + + -- default is unscrambled data + rom_data_out <= rom_data_in ; + + -- mux ROMs to same data bus + -- ignore A15 so that Pacman ROMs 0000-3FFF mirror in high mem at 8000-BFFF + if rom_addr(14) = '0' then + rom_data_in <= rom_lo; + else + rom_data_in <= rom_hi; + end if; + + -- Mr TNT program ROMs have data lines D3 and D5 swapped + -- Mr TNT video ROMs have data lines D4 and D6 and address lines A0 and A2 swapped + if MRTNT = '1' then + rom_data_out <= rom_data_in(7 downto 6) & rom_data_in(3) & rom_data_in(4) & rom_data_in(5) & rom_data_in(2 downto 0); + end if; + + if MSPACMAN = '1' and overlay_on = '1' then + -- forty 8-byte patches into Pac-Man code + -- If the CPU address presented falls in a patch range, substitute it with patched address + -- OH THE HUMANITY!!! + patch_addr := addr(15 downto 3) & "000"; + case patch_addr is + when x"0410" => rom_patched <= x"800" & '1' & addr(2 downto 0); -- ROM[0x0410+i] = ROM[0x8008+i] + when x"08E0" => rom_patched <= x"81D" & '1' & addr(2 downto 0); -- ROM[0x08E0+i] = ROM[0x81D8+i] + when x"0A30" => rom_patched <= x"811" & '1' & addr(2 downto 0); -- ROM[0x0A30+i] = ROM[0x8118+i] + when x"0BD0" => rom_patched <= x"80D" & '1' & addr(2 downto 0); -- ROM[0x0BD0+i] = ROM[0x80D8+i] + when x"0C20" => rom_patched <= x"812" & '0' & addr(2 downto 0); -- ROM[0x0C20+i] = ROM[0x8120+i] + when x"0E58" => rom_patched <= x"816" & '1' & addr(2 downto 0); -- ROM[0x0E58+i] = ROM[0x8168+i] + when x"0EA8" => rom_patched <= x"819" & '1' & addr(2 downto 0); -- ROM[0x0EA8+i] = ROM[0x8198+i] + + when x"1000" => rom_patched <= x"802" & '0' & addr(2 downto 0); -- ROM[0x1000+i] = ROM[0x8020+i] + when x"1008" => rom_patched <= x"801" & '0' & addr(2 downto 0); -- ROM[0x1008+i] = ROM[0x8010+i] + when x"1288" => rom_patched <= x"809" & '1' & addr(2 downto 0); -- ROM[0x1288+i] = ROM[0x8098+i] + when x"1348" => rom_patched <= x"804" & '1' & addr(2 downto 0); -- ROM[0x1348+i] = ROM[0x8048+i] + when x"1688" => rom_patched <= x"808" & '1' & addr(2 downto 0); -- ROM[0x1688+i] = ROM[0x8088+i] + when x"16B0" => rom_patched <= x"818" & '1' & addr(2 downto 0); -- ROM[0x16B0+i] = ROM[0x8188+i] + when x"16D8" => rom_patched <= x"80C" & '1' & addr(2 downto 0); -- ROM[0x16D8+i] = ROM[0x80C8+i] + when x"16F8" => rom_patched <= x"81C" & '1' & addr(2 downto 0); -- ROM[0x16F8+i] = ROM[0x81C8+i] + when x"19A8" => rom_patched <= x"80A" & '1' & addr(2 downto 0); -- ROM[0x19A8+i] = ROM[0x80A8+i] + when x"19B8" => rom_patched <= x"81A" & '1' & addr(2 downto 0); -- ROM[0x19B8+i] = ROM[0x81A8+i] + + when x"2060" => rom_patched <= x"814" & '1' & addr(2 downto 0); -- ROM[0x2060+i] = ROM[0x8148+i] + when x"2108" => rom_patched <= x"801" & '1' & addr(2 downto 0); -- ROM[0x2108+i] = ROM[0x8018+i] + when x"21A0" => rom_patched <= x"81A" & '0' & addr(2 downto 0); -- ROM[0x21A0+i] = ROM[0x81A0+i] + when x"2298" => rom_patched <= x"80A" & '0' & addr(2 downto 0); -- ROM[0x2298+i] = ROM[0x80A0+i] + when x"23E0" => rom_patched <= x"80E" & '1' & addr(2 downto 0); -- ROM[0x23E0+i] = ROM[0x80E8+i] + when x"2418" => rom_patched <= x"800" & '0' & addr(2 downto 0); -- ROM[0x2418+i] = ROM[0x8000+i] + when x"2448" => rom_patched <= x"805" & '1' & addr(2 downto 0); -- ROM[0x2448+i] = ROM[0x8058+i] + when x"2470" => rom_patched <= x"814" & '0' & addr(2 downto 0); -- ROM[0x2470+i] = ROM[0x8140+i] + when x"2488" => rom_patched <= x"808" & '0' & addr(2 downto 0); -- ROM[0x2488+i] = ROM[0x8080+i] + when x"24B0" => rom_patched <= x"818" & '0' & addr(2 downto 0); -- ROM[0x24B0+i] = ROM[0x8180+i] + when x"24D8" => rom_patched <= x"80C" & '0' & addr(2 downto 0); -- ROM[0x24D8+i] = ROM[0x80C0+i] + when x"24F8" => rom_patched <= x"81C" & '0' & addr(2 downto 0); -- ROM[0x24F8+i] = ROM[0x81C0+i] + when x"2748" => rom_patched <= x"805" & '0' & addr(2 downto 0); -- ROM[0x2748+i] = ROM[0x8050+i] + when x"2780" => rom_patched <= x"809" & '0' & addr(2 downto 0); -- ROM[0x2780+i] = ROM[0x8090+i] + when x"27B8" => rom_patched <= x"819" & '0' & addr(2 downto 0); -- ROM[0x27B8+i] = ROM[0x8190+i] + when x"2800" => rom_patched <= x"802" & '1' & addr(2 downto 0); -- ROM[0x2800+i] = ROM[0x8028+i] + when x"2B20" => rom_patched <= x"810" & '0' & addr(2 downto 0); -- ROM[0x2B20+i] = ROM[0x8100+i] + when x"2B30" => rom_patched <= x"811" & '0' & addr(2 downto 0); -- ROM[0x2B30+i] = ROM[0x8110+i] + when x"2BF0" => rom_patched <= x"81D" & '0' & addr(2 downto 0); -- ROM[0x2BF0+i] = ROM[0x81D0+i] + when x"2CC0" => rom_patched <= x"80D" & '0' & addr(2 downto 0); -- ROM[0x2CC0+i] = ROM[0x80D0+i] + when x"2CD8" => rom_patched <= x"80E" & '0' & addr(2 downto 0); -- ROM[0x2CD8+i] = ROM[0x80E0+i] + when x"2CF0" => rom_patched <= x"81E" & '0' & addr(2 downto 0); -- ROM[0x2CF0+i] = ROM[0x81E0+i] + when x"2D60" => rom_patched <= x"816" & '0' & addr(2 downto 0); -- ROM[0x2D60+i] = ROM[0x8160+i] + when others => rom_patched <= addr; + end case; + +-- Pacman ROMs +-- 0x0000-0x0FFF = 0x0000-0x0FFF; /* pacman.6e */ +-- 0x1000-0x1FFF = 0x1000-0x1FFF; /* pacman.6f */ +-- 0x2000-0x2FFF = 0x2000-0x2FFF; /* pacman.6h */ +-- 0x3000-0x3FFF = 0x3000-0x3FFF; /* pacman.6j */ + +-- ROM mirror (easy just ignore A15) +-- 0x8000-0x8FFF = 0x0000-0x0FFF; /* mirror of pacman.6e */ +-- 0x9000-0x9FFF = 0x1000-0x1FFF; /* mirror of pacman.6f */ +-- 0xA000-0xAFFF = 0x2000-0x2FFF; /* mirror of pacman.6h */ +-- 0xB000-0xBFFF = 0x3000-0x3FFF; /* mirror of pacman.6j */ + +-- Ms Pacman overlays + +-- no xlate +-- 0x8000-0x87FF = 0x8000-0x87FF (physical ROM hi 0000-07FF); /* decrypt u5 */ +-- 0x9000-0x97FF = 0x9000-0x97FF (physical ROM hi 1000-17FF); /* decrypt half of u6 */ + +-- xlate addr +-- 0x3000-0x3FFF = 0xB000-0xBFFF (physical ROM hi 2000-2FFF); /* decrypt u7 */ + +-- xlate addr +-- 0x8800-0x8FFF = 0x9800-0x9FFF (physical ROM hi 1800-1FFF); /* decrypt half of u6 */ + +-- ROM hi mem map +-- u5 2K 0000-07FF (0x8000-0x87FF) +-- u5 2K 0800-0FFF N/A +-- u6b 2K 1000-17FF (0x9000-0x97FF) +-- u6t 2K 1800-1FFF (0x8800-0x8FFF) +-- u7 4K 2000-2FFF (0x3000-0x3FFF) + + -- If the new patched address falls in certain Ms Pacman ranges, swap in ROM overlays and descramble address and data + -- high address bits are not scrambled so we know for sure this only accesses ROM hi after address translation + case rom_patched(15 downto 11) is + + -- addr = 0x3000-0x37FF, xlate to 0xB000-0xB7FF (physical ROM hi 2000-27FF), decrypt half of u7 + when "00110" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x3800-0x3FFF, xlate to 0xB800-0xBFFF (physical ROM hi 2800-2FFF), decrypt half of u7 + when "00111" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8000-0x87FF, no xlate (physical ROM hi 0000-07FF), decrypt u5 + when "10000" => + rom_addr <= x"0" & rom_patched(11) & rom_patched(8) & rom_patched(7) & rom_patched(5) & rom_patched(9) & rom_patched(10) & rom_patched(6) & rom_patched(3) & rom_patched(4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8800-0x8FFF, xlate to 0x9800-0x9FFF (physical ROM hi 1800-1FFF), decrypt half of u6 + when "10001" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x9000-0x97FF, no xlate (physical ROM hi 1000-17FF), decrypt half of u6 + when "10010" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- catch all default action + when others => null; + rom_addr <= rom_patched; + rom_data_out <= rom_data_in; + end case; + end if; + end process; + +end rtl; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..895304e9 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_video.vhd @@ -0,0 +1,366 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/MsPacman_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/MsPacman_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf b/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf new file mode 100644 index 00000000..62b1a305 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "PacmanClub" diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf b/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf new file mode 100644 index 00000000..e8e925e1 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# PacmanClub_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/PacmanClub.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY PacmanClub +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.srf b/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/PacmanClub.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/README.txt b/Arcade/Pacman Hardware/PacmanClub_MiST/README.txt new file mode 100644 index 00000000..68679f56 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: PacmanClub for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- UP,DOWN,LEFT,RIGHT arrows : Movements Player 1 +-- W,S,A,D : Movements Player 2 +-- +-- Two Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/Release/PacmanClub.rbf b/Arcade/Pacman Hardware/PacmanClub_MiST/Release/PacmanClub.rbf new file mode 100644 index 00000000..88e329a1 Binary files /dev/null and b/Arcade/Pacman Hardware/PacmanClub_MiST/Release/PacmanClub.rbf differ diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/clean.bat b/Arcade/Pacman Hardware/PacmanClub_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv new file mode 100644 index 00000000..95086032 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/PacmanClub.sv @@ -0,0 +1,205 @@ +//============================================================================ +// Arcade: PacmanClub +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module PacmanClub +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "PacmanClub;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [13:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +assign LED = 1; +//wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] : kbjoy[4] | joystick_0[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] : kbjoy[5] | joystick_0[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] : kbjoy[6] | joystick_0[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] : kbjoy[7] | joystick_0[0]; + +wire m2_up = status[2] ? kbjoy[11] | joystick_1[1] : kbjoy[10] | joystick_1[3]; +wire m2_down = status[2] ? kbjoy[13] | joystick_1[0] : kbjoy[12] | joystick_1[2]; +wire m2_left = status[2] ? kbjoy[12] | joystick_1[2] : kbjoy[11] | joystick_1[1]; +wire m2_right = status[2] ? kbjoy[10] | joystick_1[3] : kbjoy[13] | joystick_1[0]; + + +//wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +//wire m_skip = kbjoy[9]; + + +pacman pacmanclub +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{2'b00, m_coin, 1'b0}), + .in1(~{1'b0, m_start2, m_start1, 5'b00000}), + + .in_a({m_down,m_right,m_left,m_up}), + .in_b({m2_down,m2_right,m2_left,m2_up}), + + .dipsw1(8'b1_1_00_11_01), + .dipsw2(8'b11111111), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..834eafbd --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"EE",X"11",X"11",X"33",X"EE",X"CC",X"00",X"11",X"33",X"66",X"44",X"44",X"33",X"11",X"00", + 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X"00",X"C0",X"F1",X"79",X"F7",X"EE",X"CD",X"FF",X"00",X"00",X"EE",X"FF",X"FF",X"77",X"CC",X"00", + X"00",X"00",X"00",X"C0",X"CC",X"88",X"00",X"00",X"33",X"33",X"33",X"11",X"11",X"00",X"00",X"00", + X"CC",X"FF",X"BB",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"EE",X"00", + X"00",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"EE",X"00",X"00",X"00",X"10",X"61",X"70",X"30",X"33", + X"00",X"C0",X"F1",X"79",X"F7",X"FF",X"DD",X"9B",X"00",X"00",X"EE",X"FF",X"FF",X"DD",X"77",X"77", + X"EE",X"EE",X"EE",X"CC",X"CC",X"88",X"00",X"00",X"33",X"33",X"33",X"11",X"11",X"00",X"00",X"00", + X"AA",X"EE",X"CC",X"CC",X"C8",X"C8",X"00",X"00",X"33",X"33",X"11",X"11",X"10",X"10",X"00",X"00", + X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"CC",X"00",X"00",X"11",X"33",X"30",X"00",X"00",X"00", + X"00",X"77",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"DD",X"FF",X"33", + X"CC",X"C0",X"E0",X"68",X"80",X"00",X"00",X"00",X"00",X"00",X"30",X"33",X"11",X"00",X"00",X"00", + X"00",X"33",X"EE",X"FF",X"FF",X"77",X"00",X"00",X"FF",X"3B",X"77",X"FE",X"E9",X"F8",X"30",X"00", + X"00",X"00",X"88",X"CC",X"CC",X"EE",X"EE",X"EE",X"00",X"00",X"00",X"11",X"11",X"33",X"33",X"33", + X"00",X"00",X"C8",X"C8",X"CC",X"CC",X"EE",X"AA",X"00",X"00",X"10",X"10",X"11",X"11",X"33",X"33", + X"EE",X"EE",X"CC",X"CC",X"88",X"00",X"00",X"00",X"33",X"30",X"70",X"61",X"10",X"00",X"00",X"00", + X"9B",X"DD",X"FF",X"F7",X"79",X"F1",X"C0",X"00",X"77",X"77",X"DD",X"FF",X"FF",X"EE",X"00",X"00", + X"00",X"00",X"00",X"88",X"CC",X"C0",X"00",X"00",X"00",X"00",X"00",X"10",X"61",X"70",X"30",X"33", + X"00",X"C0",X"F1",X"79",X"F7",X"EE",X"CD",X"FF",X"00",X"00",X"EE",X"FF",X"FF",X"77",X"CC",X"00", + X"00",X"00",X"00",X"C0",X"CC",X"88",X"00",X"00",X"33",X"33",X"33",X"11",X"11",X"00",X"00",X"00", + X"CC",X"FF",X"BB",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"EE",X"00", + X"00",X"00",X"00",X"88",X"CC",X"CC",X"EE",X"EE",X"00",X"00",X"00",X"10",X"61",X"70",X"30",X"33", + X"00",X"C0",X"F1",X"79",X"F7",X"FF",X"DD",X"9B",X"00",X"00",X"EE",X"FF",X"FF",X"DD",X"77",X"77", + X"EE",X"EE",X"EE",X"CC",X"CC",X"88",X"00",X"00",X"33",X"33",X"33",X"11",X"11",X"00",X"00",X"00", + X"AA",X"EE",X"CC",X"CC",X"C8",X"C8",X"00",X"00",X"33",X"33",X"11",X"11",X"10",X"10",X"00",X"00", + X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"CC",X"00",X"00",X"11",X"33",X"30",X"00",X"00",X"00", + X"00",X"77",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"DD",X"FF",X"33", + X"CC",X"C0",X"E0",X"68",X"80",X"00",X"00",X"00",X"00",X"00",X"30",X"33",X"11",X"00",X"00",X"00", + X"00",X"33",X"EE",X"FF",X"FF",X"77",X"00",X"00",X"FF",X"3B",X"77",X"FE",X"E9",X"F8",X"30",X"00", + X"00",X"00",X"00",X"88",X"88",X"CC",X"CC",X"CC",X"00",X"00",X"11",X"33",X"30",X"00",X"00",X"00", + X"00",X"77",X"FF",X"FF",X"FF",X"33",X"00",X"00",X"00",X"CC",X"FF",X"FF",X"FF",X"DD",X"FF",X"33", + X"CC",X"C0",X"E0",X"68",X"80",X"00",X"00",X"00",X"00",X"00",X"30",X"33",X"11",X"00",X"00",X"00", + X"00",X"33",X"EE",X"FF",X"FF",X"77",X"00",X"00",X"FF",X"3B",X"77",X"FE",X"E9",X"F8",X"30",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..17522bd2 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..48cb873c --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"3E",X"00",X"C3",X"D5",X"1F",X"00",X"00",X"77",X"23",X"10",X"FC",X"C9",X"C3",X"65",X"09", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"AB",X"00",X"00",X"00",X"00",X"00",X"00",X"F5",X"C5",X"E5",X"CD",X"A0",X"B3",X"E1",X"C1",X"F1"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..a49aa779 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C9",X"E6",X"07",X"CD",X"2C",X"AF",X"E6",X"00",X"E7",X"17",X"80",X"56",X"3F",X"74",X"3F",X"74", + X"3F",X"56",X"3F",X"38",X"3F",X"92",X"3F",X"26",X"40",X"3A",X"01",X"4F",X"E6",X"0F",X"F6",X"60", + X"C6",X"03",X"6F",X"2D",X"11",X"49",X"3B",X"36",X"40",X"7C",X"C6",X"04",X"67",X"36",X"0F",X"7C", + X"C6",X"FC",X"67",X"1A",X"A7",X"28",X"09",X"13",X"85",X"6F",X"D2",X"27",X"80",X"24",X"18",X"E7", + X"26",X"40",X"3A",X"01",X"4F",X"E6",X"0F",X"F6",X"60",X"C6",X"03",X"6F",X"11",X"49",X"3B",X"36", + X"14",X"7C",X"C6",X"04",X"67",X"36",X"0F",X"7C",X"C6",X"FC",X"67",X"1A",X"A7",X"C8",X"13",X"85", + X"6F",X"D2",X"4F",X"80",X"24",X"18",X"E8",X"C9",X"3E",X"00",X"32",X"70",X"4C",X"3E",X"01",X"32", + X"13",X"4E",X"C3",X"08",X"3F",X"C9",X"3E",X"01",X"32",X"70",X"4C",X"3E",X"02",X"32",X"13",X"4E", + X"C3",X"08",X"3F",X"3E",X"02",X"32",X"70",X"4C",X"3E",X"03",X"32",X"13",X"4E",X"C3",X"08",X"3F", + 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X"20",X"20",X"20",X"20",X"8C",X"85",X"99",X"20",X"31",X"31",X"37",X"32",X"33",X"20",X"2E",X"20", + X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20", + X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"E5", + X"F5",X"2A",X"6C",X"4C",X"7D",X"B4",X"28",X"03",X"F1",X"E1",X"C9",X"F1",X"3E",X"F3",X"E1",X"C9"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/build_id.v new file mode 100644 index 00000000..d08c51bc --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171122" +`define BUILD_TIME "112757" diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/keyboard.v new file mode 100644 index 00000000..2f179e0c --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/keyboard.v @@ -0,0 +1,87 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[13:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + + 'h1D: joystick[10] <= ~release_btn; //W + 'h1C: joystick[11] <= ~release_btn; //A + 'h1B: joystick[12] <= ~release_btn; //S + 'h23: joystick[13] <= ~release_btn; //D + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/osd.v b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..38e3993c --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman.vhd @@ -0,0 +1,479 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- Copyright (c) Sorgelig - 2017 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN is + generic( + eight_sprites : boolean := false + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(3 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + + in_a : in std_logic_vector(3 downto 0); + in_b : in std_logic_vector(3 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal inj : std_logic_vector(3 downto 0); + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(7 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= X"FF"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= X"00"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = X"FF") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- sn1_l 0x5040 - 0x504F sound +-- sn2_l 0x5050 - 0x505F sound +-- spr_l 0x5060 - 0x506F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"4" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"5" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"6" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +inj <= not in_a when control_reg(5 downto 4) = "01" else + not in_b when control_reg(5 downto 4) = "10" else + not (in_a or in_b); + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - bfff + in0 & inj when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(11 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..91313469 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pll.v b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanClub_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf b/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf new file mode 100644 index 00000000..de6f8ac6 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "PacmanPlus" diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf b/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf new file mode 100644 index 00000000..0dcaf95f --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Alibaba_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY PacmanPlus +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/PacmanPlus.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.srf b/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/PacmanPlus.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/README.txt b/Arcade/Pacman Hardware/PacmanPlus_MiST/README.txt new file mode 100644 index 00000000..e2f75a6c --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Pacman Plus for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Dream Shopper hardware +-- Copyright (c) Sorgelig +-- Based on Pacman core: Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE,CTRL : Action +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/Release/PacmanPlus.rbf b/Arcade/Pacman Hardware/PacmanPlus_MiST/Release/PacmanPlus.rbf new file mode 100644 index 00000000..161f709f Binary files /dev/null and b/Arcade/Pacman Hardware/PacmanPlus_MiST/Release/PacmanPlus.rbf differ diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/clean.bat b/Arcade/Pacman Hardware/PacmanPlus_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv new file mode 100644 index 00000000..3830ddf7 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/PacmanPlus.sv @@ -0,0 +1,196 @@ +//============================================================================ +// Arcade: PacmanPlus +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module PacmanPlus +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "PacmanPlus;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +//wire m_skip = kbjoy[9]; + + +pacman pacmanpls +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{2'b00, m_coin, m_fire, m_down,m_right,m_left,m_up}), + .in1(~{1'b0, m_start2, m_start1, 5'b00000}), + + .dipsw1(8'b1_1_00_11_01), + .dipsw2(8'b11111111), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..4203ec94 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"EE",X"11",X"11",X"33",X"EE",X"CC",X"00",X"11",X"33",X"66",X"44",X"44",X"33",X"11",X"00", + X"11",X"11",X"FF",X"FF",X"11",X"11",X"00",X"00",X"00",X"00",X"77",X"77",X"22",X"00",X"00",X"00", + X"11",X"99",X"DD",X"DD",X"FF",X"77",X"33",X"00",X"33",X"77",X"55",X"44",X"44",X"66",X"22",X"00", + X"66",X"FF",X"99",X"99",X"99",X"33",X"22",X"00",X"44",X"66",X"77",X"55",X"44",X"44",X"00",X"00", + X"44",X"FF",X"FF",X"44",X"44",X"CC",X"CC",X"00",X"00",X"77",X"77",X"66",X"33",X"11",X"00",X"00", + X"EE",X"FF",X"11",X"11",X"11",X"33",X"22",X"00",X"00",X"55",X"55",X"55",X"55",X"77",X"77",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"EE",X"00",X"00",X"44",X"44",X"44",X"66",X"33",X"11",X"00", + X"00",X"00",X"88",X"FF",X"77",X"00",X"00",X"00",X"66",X"77",X"55",X"44",X"44",X"66",X"66",X"00", + X"66",X"77",X"DD",X"DD",X"99",X"99",X"66",X"00",X"00",X"33",X"44",X"44",X"55",X"77",X"33",X"00", + X"CC",X"EE",X"BB",X"99",X"99",X"99",X"00",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"33",X"00", + X"FF",X"FF",X"44",X"44",X"44",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"66",X"33",X"11",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"FF",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"77",X"00", + X"22",X"33",X"11",X"11",X"33",X"EE",X"CC",X"00",X"22",X"66",X"44",X"44",X"66",X"33",X"11",X"00", + X"CC",X"EE",X"33",X"11",X"11",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"44",X"77",X"77",X"00", + X"11",X"99",X"99",X"99",X"FF",X"FF",X"00",X"00",X"44",X"44",X"44",X"44",X"77",X"77",X"00",X"00", + X"00",X"88",X"88",X"88",X"88",X"FF",X"FF",X"00",X"44",X"44",X"44",X"44",X"44",X"77",X"77",X"00", + X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"00",X"00",X"08",X"0C",X"0C",X"08",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00", + X"0C",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0C",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"07",X"03", + X"0C",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0C",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"07",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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X"00",X"00",X"00",X"00",X"22",X"44",X"11",X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"11",X"00",X"00",X"00",X"11",X"99",X"44",X"00",X"00", + X"00",X"22",X"11",X"88",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"11",X"22",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"22",X"22",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..5a83d11e --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"02",X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"04",X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"05", + X"00",X"00",X"00",X"00",X"00",X"07",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"08",X"00",X"01",X"0B",X"0F", + X"00",X"08",X"00",X"09",X"00",X"06",X"08",X"07",X"00",X"0F",X"08",X"0F",X"00",X"00",X"00",X"00", + X"00",X"0F",X"02",X"0D",X"00",X"0F",X"0A",X"06",X"00",X"01",X"0D",X"0C",X"00",X"0B",X"0F",X"0D", + X"00",X"04",X"03",X"01",X"00",X"0F",X"07",X"00",X"00",X"08",X"00",X"09",X"00",X"08",X"00",X"09", + X"00",X"00",X"00",X"00",X"00",X"0F",X"08",X"02",X"00",X"0F",X"07",X"08",X"00",X"08",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + +data <= rom_data(to_integer(unsigned(addr))); + +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..fcbfc200 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"3F",X"07",X"EF",X"F8",X"6F",X"38",X"C9",X"AF",X"AA",X"20",X"D5",X"BF",X"5D",X"ED",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..a2579c4f --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"3E",X"3F",X"ED",X"47",X"C3",X"0B",X"23",X"77",X"23",X"10",X"FC",X"C9",X"C3",X"0E",X"07", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"78",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"C9", + X"E1",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"E9",X"E1",X"46",X"23",X"4E",X"23",X"E5",X"18",X"12", + X"11",X"90",X"4C",X"06",X"10",X"C3",X"51",X"00",X"AF",X"32",X"00",X"50",X"32",X"07",X"50",X"C3", + X"38",X"00",X"2A",X"80",X"4C",X"70",X"2C",X"71",X"2C",X"20",X"02",X"2E",X"C0",X"22",X"80",X"4C", + X"C9",X"1A",X"A7",X"28",X"06",X"1C",X"1C",X"1C",X"10",X"F7",X"C9",X"E1",X"06",X"03",X"7E",X"12", + X"23",X"1C",X"10",X"FA",X"E9",X"C3",X"2D",X"20",X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07", + X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"10",X"11",X"12",X"13",X"14",X"01",X"03",X"04", + X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"10",X"11",X"14",X"F5",X"32",X"C0", + X"50",X"AF",X"32",X"00",X"50",X"F3",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5",X"21",X"8C",X"4E", + X"11",X"50",X"50",X"01",X"10",X"00",X"ED",X"B0",X"3A",X"CC",X"4E",X"A7",X"3A",X"CF",X"4E",X"20", + X"03",X"3A",X"9F",X"4E",X"32",X"45",X"50",X"3A",X"DC",X"4E",X"A7",X"3A",X"DF",X"4E",X"20",X"03", + X"3A",X"AF",X"4E",X"32",X"4A",X"50",X"3A",X"EC",X"4E",X"A7",X"3A",X"EF",X"4E",X"20",X"03",X"3A", + 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X"01",X"D2",X"B9",X"C9",X"50",X"43",X"51",X"01",X"D2",X"A1",X"00",X"30",X"8D",X"00",X"BB",X"D1"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..f07cb2ca --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is +begin + data <= X"FF"; +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.v new file mode 100644 index 00000000..6d3056e6 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "205349" diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/osd.v b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..24d19966 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman.vhd @@ -0,0 +1,469 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- Copyright (c) Sorgelig - 2017 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN is + generic( + eight_sprites : boolean := false + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- sn1_l 0x5040 - 0x504F sound +-- sn2_l 0x5050 - 0x505F sound +-- spr_l 0x5060 - 0x506F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"4" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"5" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"6" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - bfff + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(11 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..91313469 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pll.v b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/PacmanPlus_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Pacman_MiST/Pacman.qpf b/Arcade/Pacman Hardware/Pacman_MiST/Pacman.qpf new file mode 100644 index 00000000..787ace51 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/Pacman.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Pacman" diff --git a/Arcade/Pacman Hardware/Pacman_MiST/Pacman.qsf b/Arcade/Pacman Hardware/Pacman_MiST/Pacman.qsf new file mode 100644 index 00000000..09a4452e --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/Pacman.qsf @@ -0,0 +1,174 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 17:05:52 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Pacman_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pacman.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Pacman +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------- +# start ENTITY(Pacman) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Pacman) +# ------------------ +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Pacman_MiST/Pacman.srf b/Arcade/Pacman Hardware/Pacman_MiST/Pacman.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/Pacman.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/Pacman_MiST/README.txt b/Arcade/Pacman Hardware/Pacman_MiST/README.txt new file mode 100644 index 00000000..90dabc41 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Pacman port to MiST by Gehstock +-- 09 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Pacman_MiST/Release/Pacman(PACE).rbf b/Arcade/Pacman Hardware/Pacman_MiST/Release/Pacman(PACE).rbf new file mode 100644 index 00000000..1181c186 Binary files /dev/null and b/Arcade/Pacman Hardware/Pacman_MiST/Release/Pacman(PACE).rbf differ diff --git a/Arcade/Pacman Hardware/Pacman_MiST/Release/Pacman.rbf b/Arcade/Pacman Hardware/Pacman_MiST/Release/Pacman.rbf new file mode 100644 index 00000000..9602f3b3 Binary files /dev/null and b/Arcade/Pacman Hardware/Pacman_MiST/Release/Pacman.rbf differ diff --git a/Arcade/Pacman Hardware/Pacman_MiST/clean.bat b/Arcade/Pacman Hardware/Pacman_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/Pacman.sv b/Arcade/Pacman Hardware/Pacman_MiST/rtl/Pacman.sv new file mode 100644 index 00000000..8b6f31c0 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/Pacman.sv @@ -0,0 +1,201 @@ +//============================================================================ +// Arcade: Pacman +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Pacman +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Pacman;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +reg ce_1m79; +always @(posedge clk_sys) begin + reg [3:0] div; + + div <= div + 1'd1; + if(div == 12) div <= 0; + ce_1m79 <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire m_Serv = kbjoy[9]; + +pacmant pacmant +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .I_JOYSTICK_A(~{m_fire,m_right,m_left,m_down,m_up}), + .I_JOYSTICK_B(5'b11111), + + .I_SW({m_start2, m_coin, 1'b0, m_start1}), + .RESET(RESET | status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..4203ec94 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"EE",X"11",X"11",X"33",X"EE",X"CC",X"00",X"11",X"33",X"66",X"44",X"44",X"33",X"11",X"00", + X"11",X"11",X"FF",X"FF",X"11",X"11",X"00",X"00",X"00",X"00",X"77",X"77",X"22",X"00",X"00",X"00", + X"11",X"99",X"DD",X"DD",X"FF",X"77",X"33",X"00",X"33",X"77",X"55",X"44",X"44",X"66",X"22",X"00", + X"66",X"FF",X"99",X"99",X"99",X"33",X"22",X"00",X"44",X"66",X"77",X"55",X"44",X"44",X"00",X"00", + X"44",X"FF",X"FF",X"44",X"44",X"CC",X"CC",X"00",X"00",X"77",X"77",X"66",X"33",X"11",X"00",X"00", + X"EE",X"FF",X"11",X"11",X"11",X"33",X"22",X"00",X"00",X"55",X"55",X"55",X"55",X"77",X"77",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"EE",X"00",X"00",X"44",X"44",X"44",X"66",X"33",X"11",X"00", + X"00",X"00",X"88",X"FF",X"77",X"00",X"00",X"00",X"66",X"77",X"55",X"44",X"44",X"66",X"66",X"00", + X"66",X"77",X"DD",X"DD",X"99",X"99",X"66",X"00",X"00",X"33",X"44",X"44",X"55",X"77",X"33",X"00", + X"CC",X"EE",X"BB",X"99",X"99",X"99",X"00",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"33",X"00", + X"FF",X"FF",X"44",X"44",X"44",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"66",X"33",X"11",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"FF",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"77",X"00", + X"22",X"33",X"11",X"11",X"33",X"EE",X"CC",X"00",X"22",X"66",X"44",X"44",X"66",X"33",X"11",X"00", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"33",X"77", + X"CC",X"EE",X"EE",X"EE",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"77",X"33",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"44",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"33", + X"CC",X"EE",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"33",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"CC",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"22",X"44",X"11",X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"11",X"00",X"00",X"00",X"11",X"99",X"44",X"00",X"00", + X"00",X"22",X"11",X"88",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"11",X"22",X"00",X"11",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"22",X"22",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..4bfa195f --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..21b4691d --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"3E",X"00",X"ED",X"47",X"C3",X"0B",X"23",X"77",X"23",X"10",X"FC",X"C9",X"C3",X"0E",X"07", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"78",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"C9", + X"E1",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"E9",X"E1",X"46",X"23",X"4E",X"23",X"E5",X"18",X"12", + X"11",X"90",X"4C",X"06",X"10",X"C3",X"51",X"00",X"C3",X"3C",X"0F",X"50",X"32",X"07",X"50",X"C3", + X"38",X"00",X"2A",X"80",X"4C",X"70",X"2C",X"71",X"2C",X"20",X"02",X"2E",X"C0",X"22",X"80",X"4C", + X"C9",X"1A",X"A7",X"28",X"06",X"1C",X"1C",X"1C",X"10",X"F7",X"C9",X"E1",X"06",X"03",X"7E",X"12", + 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Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..f07cb2ca --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is +begin + data <= X"FF"; +end architecture; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Pacman_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Pacman_MiST/rtl/build_id.v new file mode 100644 index 00000000..318db7e9 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "171150" diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Pacman_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Pacman_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Pacman_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Pacman_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..87ed2b83 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman.vhd @@ -0,0 +1,669 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity pacmant is + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + I_JOYSTICK_A : in std_logic_vector(4 downto 0); + I_JOYSTICK_B : in std_logic_vector(4 downto 0); + + I_SW : in std_logic_vector(3 downto 0); -- active high + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of pacmant is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + signal freeze : std_logic; + + -- ip registers + signal button_in : std_logic_vector(13 downto 0); + signal button_debounced : std_logic_vector(13 downto 0); + signal in0_reg : std_logic_vector(7 downto 0); + signal in1_reg : std_logic_vector(7 downto 0); + signal dipsw_reg : std_logic_vector(7 downto 0); + signal joystick_reg : std_logic_vector(4 downto 0); + signal joystick_reg2 : std_logic_vector(4 downto 0); + + +begin + joystick_reg <= I_JOYSTICK_A; + joystick_reg2 <= I_JOYSTICK_B; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(freeze, sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (freeze = '1') or (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank and (freeze = '0') then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, program_rom_dinl, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= program_rom_dinl; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= X"00"; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + + button_in(8 downto 5) <= I_SW(3 downto 0); + button_in(4 downto 0) <= joystick_reg(4 downto 0); + button_in(13 downto 9) <= joystick_reg2(4 downto 0); + + button_debounced <= button_in; + +--button_debounced Arcade MegaWing Location +-- 8 RIGHT PushButton +-- 7 DOWN PushButton +-- 6 UP PushButton +-- 5 LEFT PushButton +-- 4 Fire Joystick +-- 3 RIGHT Joystick +-- 2 LEFT Joystick +-- 1 DOWN Joystick +-- 0 UP Joystick + + p_input_registers : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- on is low + in0_reg(7) <= not button_debounced(6); -- credit Up Pushbutton + in0_reg(6) <= '1'; -- coin2 + in0_reg(5) <= not button_debounced(7); -- coin1 DOWN PushButton + in0_reg(4) <= '1'; -- test_l dipswitch (rack advance) + in0_reg(3) <= button_debounced(1); -- p1 down + in0_reg(2) <= button_debounced(3); -- p1 right + in0_reg(1) <= button_debounced(2); -- p1 left + in0_reg(0) <= button_debounced(0); -- p1 up + + in1_reg(7) <= '1'; -- table 1-upright 0-cocktail + in1_reg(6) <= not button_debounced(8); -- start2 RIGHT PushButton + in1_reg(5) <= not button_debounced(5); -- start1 LEFT PushButton + in1_reg(4) <= button_debounced(13); -- test and fire + in1_reg(3) <= button_debounced(10); -- p2 down + in1_reg(2) <= button_debounced(12); -- p2 right + in1_reg(1) <= button_debounced(11); -- p2 left + in1_reg(0) <= button_debounced(9); -- p2 up + + -- on is low + freeze <= '0'; + dipsw_reg(7) <= '1'; -- character set ? + dipsw_reg(6) <= '1'; -- difficulty ? + dipsw_reg(5 downto 4) <= "00"; -- bonus pacman at 10K + dipsw_reg(3 downto 2) <= "11"; -- pacman (3) + dipsw_reg(1 downto 0) <= "01"; -- cost (1 coin, 1 play) + end if; + end process; + +end RTL; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..ef80481d --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_video.vhd @@ -0,0 +1,360 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal ra : std_logic_vector(7 downto 0); + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal sprite_ram_addr : std_logic_vector(7 downto 0); + signal sprite_ram_addr_t1 : std_logic_vector(7 downto 0); + signal vout_obj_on_t1 : std_logic; + signal col_rom_addr : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal vout_hblank_t1 : std_logic; + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_out : std_logic_vector(7 downto 0); + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + -- 2h, 4e + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(2) <= char_sum_reg(2) xor xflip; + ca(1) <= char_sum_reg(1) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end process; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_dout + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + p_lut_4a_comb : process(vout_db, shift_op) + begin + col_rom_addr <= '0' & vout_db(4 downto 0) & shift_op(1 downto 0); + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR => col_rom_addr, + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + sprite_ram_addr <= ra; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on, + addr_a_i => sprite_ram_addr, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => sprite_ram_addr, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR => final_col, + DATA => video_out + ); + + -- assign outputs + O_BLUE (1 downto 0) <= video_out(7 downto 6); + O_GREEN(2 downto 0) <= video_out(5 downto 3); + O_RED (2 downto 0) <= video_out(2 downto 0); + +end architecture; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/pll.v b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Pacman_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Pacman_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Pacman_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Pacman_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Pengo_MiST/Pengo.qpf b/Arcade/Pacman Hardware/Pengo_MiST/Pengo.qpf new file mode 100644 index 00000000..bfc9f179 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/Pengo.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Pengo" diff --git a/Arcade/Pacman Hardware/Pengo_MiST/Pengo.qsf b/Arcade/Pacman Hardware/Pengo_MiST/Pengo.qsf new file mode 100644 index 00000000..bfcc5b24 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/Pengo.qsf @@ -0,0 +1,169 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:14:41 November 10, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Pengo_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Pengo +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------- +# start ENTITY(MrTNT) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(MrTNT) +# ----------------- +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pengo.sv +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_rom_descrambler.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/sega_decode.vhd +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Pengo_MiST/README.txt b/Arcade/Pacman Hardware/Pengo_MiST/README.txt new file mode 100644 index 00000000..ffdc61c9 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Pengo port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE,CTRL : Slow +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Pengo_MiST/Release/Pengo.rbf b/Arcade/Pacman Hardware/Pengo_MiST/Release/Pengo.rbf new file mode 100644 index 00000000..07c31620 Binary files /dev/null and b/Arcade/Pacman Hardware/Pengo_MiST/Release/Pengo.rbf differ diff --git a/Arcade/Pacman Hardware/Pengo_MiST/clean.bat b/Arcade/Pacman Hardware/Pengo_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/Pengo.sv b/Arcade/Pacman Hardware/Pengo_MiST/rtl/Pengo.sv new file mode 100644 index 00000000..7799a969 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/Pengo.sv @@ -0,0 +1,192 @@ +//============================================================================ +// Arcade: Pengo +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Pengo +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Pengo;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(292), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +PACMAN_MACHINE Pengo +( + .video_r(r), + .video_g(g), + .video_b(b), + .hsync(hs), + .vsync(vs), + .h_blank(hblank), + .v_blank(vblank), + + .audio(audio), + .in0_reg(~{m_fire, 2'b00,m_coin,m_right,m_left,m_down,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, 5'b00000}), + + .dipsw1_reg(8'b11100000), + .dipsw2_reg(8'b11001100), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..f263b100 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F", + X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"CF",X"CF",X"F7",X"F0",X"11",X"11",X"11",X"33",X"30",X"30",X"10",X"00",X"00",X"00",X"00",X"00", + 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X"F0",X"D0",X"C0",X"40",X"60",X"30",X"00",X"00",X"F0",X"F0",X"90",X"90",X"90",X"F0",X"F0",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"30",X"30", + X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"00",X"00",X"00",X"C0",X"E0",X"F0",X"F0",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"30",X"10",X"10",X"00",X"00",X"00",X"00", + X"70",X"40",X"D0",X"F0",X"70",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00", + X"00",X"00",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"30",X"30",X"70",X"70",X"70",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"C0",X"C0",X"C0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"70",X"60",X"60",X"30",X"30",X"00",X"00",X"00",X"F0",X"F0",X"90",X"90",X"F0",X"F0",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10", + X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"70",X"C0",X"F0",X"70",X"00",X"00",X"00",X"00",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"10",X"30",X"30",X"30",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0", + X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"20",X"30",X"10",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"F0",X"F0",X"00",X"00",X"00", + X"00",X"00",X"00",X"80",X"80",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"30",X"70",X"70",X"F0",X"F0", + X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"C0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"C0",X"C0",X"80",X"80",X"00",X"00",X"00",X"00",X"F0",X"60",X"60",X"30",X"10",X"00",X"00",X"00", + X"10",X"00",X"66",X"76",X"F0",X"16",X"02",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"C0",X"00",X"00", + X"C0",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"10", + X"00",X"30",X"70",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"F0",X"F0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"E0",X"C0",X"F3",X"F3",X"60",X"10",X"00",X"00",X"70",X"30",X"30",X"30",X"70",X"F0",X"3C",X"08", + X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"00",X"00",X"00",X"10",X"30",X"30",X"70",X"70", + X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"90",X"00",X"00",X"C0",X"E0",X"F0",X"F0",X"F0",X"F0", + X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"30",X"30",X"10",X"00",X"00",X"00",X"00", + X"00",X"66",X"F6",X"F0",X"16",X"02",X"00",X"00",X"F0",X"F0",X"F0",X"E0",X"80",X"00",X"00",X"00", + X"00",X"80",X"C0",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"30",X"70",X"70",X"F0",X"F0",X"F0",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"70", + X"E0",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"E0",X"71",X"71",X"30",X"10",X"00",X"00",X"00",X"30",X"B8",X"B8",X"70",X"F0",X"3C",X"08",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"30",X"30", + X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"90",X"00",X"00",X"00",X"C0",X"E0",X"F0",X"F0",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00", + X"54",X"D4",X"F0",X"16",X"02",X"00",X"00",X"00",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"00", + X"00",X"00",X"80",X"C0",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"10",X"30",X"30",X"70",X"70",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"C0",X"C0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"70",X"30",X"30",X"10",X"00",X"00",X"00",X"00",X"30",X"B8",X"B8",X"F0",X"3C",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10", + X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"30",X"00",X"00",X"00",X"00",X"C0",X"E0",X"E0",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"54",X"F0",X"34",X"04",X"00",X"00",X"00",X"00",X"E0",X"E0",X"C0",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"80",X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"10",X"10",X"30",X"30",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"F0",X"F0", + X"80",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"30",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"30",X"B8",X"F0",X"78",X"08",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..84f8d265 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"08",X"08",X"08",X"08",X"08",X"0F",X"0F",X"08",X"08",X"00",X"00",X"00",X"08",X"08",X"08",X"08", + X"0F",X"0F",X"0F",X"08",X"00",X"00",X"08",X"08",X"08",X"08",X"0F",X"0F",X"08",X"08",X"00",X"00", + X"07",X"09",X"0A",X"0B",X"07",X"0D",X"0D",X"07",X"0E",X"07",X"0D",X"0D",X"07",X"0B",X"0A",X"09", + X"07",X"05",X"07",X"03",X"07",X"01",X"07",X"00",X"07",X"00",X"07",X"01",X"07",X"03",X"07",X"05", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"08",X"00",X"08",X"08",X"0F",X"0F",X"00",X"00",X"08",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"08",X"08",X"00",X"0F",X"0F",X"08",X"08",X"08",X"08",X"0F",X"08",X"00",X"00",X"00",X"08", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0E",X"0C",X"09",X"0C",X"0E",X"0A",X"07",X"0C",X"0F",X"0D",X"08",X"0A",X"0B",X"07",X"02", + X"08",X"0D",X"09",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"07",X"08",X"0A",X"0C",X"0E",X"0D",X"0C",X"0C",X"0B",X"0A",X"08",X"07",X"05",X"06",X"07",X"08", + X"08",X"09",X"0A",X"0B",X"09",X"08",X"06",X"05",X"04",X"04",X"03",X"02",X"04",X"06",X"08",X"09", + X"0A",X"0C",X"0C",X"0A",X"07",X"07",X"08",X"0B",X"0D",X"0E",X"0D",X"0A",X"06",X"05",X"05",X"07", + X"09",X"09",X"08",X"04",X"01",X"00",X"01",X"03",X"06",X"07",X"07",X"04",X"02",X"02",X"04",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..4f86b49a --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(6 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 127) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B" + ); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..b9cfb224 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,86 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(9 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 1023) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"05",X"03",X"01",X"00",X"05",X"02",X"01",X"00",X"05",X"06",X"01", + X"00",X"05",X"07",X"01",X"00",X"05",X"0A",X"01",X"00",X"05",X"0B",X"01",X"00",X"05",X"0C",X"01", + X"00",X"05",X"0D",X"01",X"00",X"05",X"04",X"01",X"00",X"03",X"06",X"01",X"00",X"03",X"02",X"01", + X"00",X"03",X"07",X"01",X"00",X"03",X"05",X"01",X"00",X"02",X"03",X"01",X"00",X"00",X"00",X"00", + X"00",X"08",X"03",X"01",X"00",X"09",X"02",X"05",X"00",X"08",X"05",X"0D",X"04",X"04",X"04",X"04", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"02",X"00",X"03",X"03",X"03", + X"00",X"06",X"06",X"06",X"00",X"07",X"07",X"07",X"00",X"0A",X"0A",X"0A",X"00",X"0B",X"0B",X"0B", + X"00",X"01",X"01",X"01",X"00",X"05",X"05",X"05",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"00",X"00",X"00",X"00",X"03",X"07",X"0D",X"00",X"0C",X"0F",X"0B",X"00",X"0C",X"0E",X"0B", + X"00",X"0C",X"06",X"0B",X"00",X"0C",X"07",X"0B",X"00",X"0C",X"03",X"0B",X"00",X"0C",X"08",X"0B", + X"00",X"0C",X"0D",X"0B",X"00",X"0C",X"04",X"0B",X"00",X"0C",X"09",X"0B",X"00",X"0C",X"05",X"0B", + X"00",X"0C",X"02",X"0B",X"00",X"0C",X"0B",X"02",X"00",X"08",X"0C",X"02",X"00",X"08",X"0F",X"02", + X"00",X"03",X"02",X"01",X"00",X"02",X"0F",X"03",X"00",X"0F",X"0E",X"02",X"00",X"0E",X"07",X"0F", + X"00",X"07",X"06",X"0E",X"00",X"06",X"05",X"07",X"00",X"05",X"00",X"06",X"00",X"00",X"0B",X"05", + X"00",X"0B",X"0C",X"00",X"00",X"0C",X"0D",X"0B",X"00",X"0D",X"08",X"0C",X"00",X"08",X"09",X"0D", + X"00",X"09",X"0A",X"08",X"00",X"0A",X"01",X"09",X"00",X"01",X"04",X"0A",X"00",X"04",X"03",X"01", + X"00",X"00",X"00",X"00",X"00",X"03",X"07",X"0D",X"00",X"0C",X"0F",X"0B",X"00",X"0C",X"0E",X"0B", + X"00",X"0C",X"06",X"0B",X"00",X"0C",X"07",X"0B",X"00",X"0C",X"03",X"0B",X"00",X"0C",X"08",X"0B", + X"00",X"0C",X"0D",X"0B",X"00",X"0C",X"04",X"0B",X"00",X"0C",X"09",X"0B",X"00",X"0C",X"05",X"0B", + X"00",X"0C",X"02",X"0B",X"00",X"0C",X"0B",X"02",X"00",X"08",X"0C",X"02",X"00",X"08",X"0F",X"02", + X"00",X"03",X"02",X"01",X"00",X"02",X"0F",X"03",X"00",X"0F",X"0E",X"02",X"00",X"0E",X"07",X"0F", + X"00",X"07",X"06",X"0E",X"00",X"06",X"05",X"07",X"00",X"05",X"00",X"06",X"00",X"00",X"0B",X"05", + X"00",X"0B",X"0C",X"00",X"00",X"0C",X"0D",X"0B",X"00",X"0D",X"08",X"0C",X"00",X"08",X"09",X"0D", + X"00",X"09",X"0A",X"08",X"00",X"0A",X"01",X"09",X"00",X"01",X"04",X"0A",X"00",X"04",X"03",X"01", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"07", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"0D", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F", + X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"07", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00", + X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"0D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..bc8de866 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"F6",X"07",X"38",X"C9",X"F8",X"3F",X"EF",X"6F",X"16",X"2F",X"7F",X"F0",X"36",X"DB",X"C6", + X"00",X"F6",X"D8",X"F0",X"F8",X"16",X"07",X"2F",X"36",X"3F",X"7F",X"28",X"32",X"38",X"EF",X"C6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..672efd2e --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"91",X"50",X"2F",X"4D",X"DE",X"81",X"A0",X"88",X"82",X"90",X"28",X"EB",X"FC",X"8B",X"88",X"A0", + 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X"65",X"59",X"08",X"69",X"90",X"C1",X"75",X"9C",X"17",X"61",X"2F",X"89",X"FB",X"8F",X"91",X"2A", + X"28",X"77",X"11",X"77",X"11",X"77",X"11",X"77",X"61",X"DD",X"D6",X"23",X"19",X"DA",X"B7",X"C3", + X"27",X"A5",X"7A",X"B7",X"8B",X"68",X"17",X"68",X"46",X"68",X"86",X"28",X"75",X"D6",X"84",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..45b338e5 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"A3",X"80",X"A1",X"15",X"0F",X"EE",X"A6",X"A8",X"8F",X"A7",X"7D",X"D7",X"A2",X"7D",X"F6",X"8C", + X"D6",X"8B",X"20",X"8C",X"DD",X"63",X"2A",X"6E",X"CD",X"23",X"B1",X"75",X"34",X"AB",X"C9",X"86", + X"A1",X"30",X"79",X"7D",X"6B",X"A9",X"E6",X"6C",X"06",X"C8",X"6D",X"97",X"E0",X"69",X"7D",X"96", + X"AA",X"89",X"DD",X"9E",X"A9",X"AF",X"C9",X"1A",X"24",X"28",X"07",X"E0",X"DD",X"5E",X"AA",X"1D", + X"A0",X"8C",X"7D",X"D7",X"22",X"69",X"7D",X"96",X"21",X"88",X"7D",X"94",X"23",X"69",X"7D",X"96", + X"BF",X"8A",X"C9",X"75",X"F6",X"AB",X"39",X"FC",X"68",X"E3",X"8F",X"A5",X"D2",X"B7",X"E6",X"C8", + X"37",X"C8",X"46",X"C8",X"5A",X"B7",X"46",X"C8",X"37",X"C8",X"46",X"C8",X"66",X"C8",X"7D",X"6B", + X"A9",X"CE",X"CC",X"F1",X"68",X"65",X"0A",X"C8",X"C9",X"75",X"36",X"AA",X"2A",X"75",X"36",X"A9", + X"27",X"69",X"B2",X"84",X"28",X"CE",X"37",X"E8",X"7D",X"56",X"22",X"15",X"A0",X"8C",X"7D",X"D7", + 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X"84",X"2A",X"87",X"2C",X"82",X"2A",X"84",X"2C",X"7D",X"2C",X"85",X"2A",X"85",X"2A",X"7A",X"28", + X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7", + X"7F",X"D7",X"7F",X"D7",X"7F",X"D7",X"7F",X"D7",X"7F",X"D7",X"7F",X"D7",X"7F",X"D7",X"7F",X"D7", + X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7",X"D7", + X"7C",X"28",X"80",X"28",X"80",X"28",X"80",X"28",X"12",X"28",X"7D",X"28",X"9C",X"28",X"D9",X"28"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Pengo_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Pengo_MiST/rtl/build_id.v new file mode 100644 index 00000000..85d5514d --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171113" +`define BUILD_TIME "103644" diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Pengo_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Pengo_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Pengo_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Pengo_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..235df11b --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman.vhd @@ -0,0 +1,550 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_MACHINE is + generic ( + -- only set one of these + PENGO : std_logic := '1'; -- set to 1 when using Pengo ROMs, 0 otherwise + PACMAN : std_logic := '0'; -- set to 1 for all other Pacman hardware games + -- only set one of these when PACMAN is set + MRTNT : std_logic := '0'; -- set to 1 when using Mr TNT ROMs, 0 otherwise + LIZWIZ : std_logic := '0'; -- set to 1 when using Lizard Wizard ROMs, 0 otherwise + MSPACMAN : std_logic := '0' -- set to 1 when using Ms Pacman ROMs, 0 otherwise + ); + port ( + clk : in std_logic; + ena_6 : in std_logic; + reset : in std_logic; + + -- video + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + hsync : out std_logic; + vsync : out std_logic; + v_blank : out std_logic; + h_blank : out std_logic; + + -- audio + audio : out std_logic_vector(7 downto 0); + + -- controls + in0_reg : in std_logic_vector( 7 downto 0); + in1_reg : in std_logic_vector( 7 downto 0); + dipsw1_reg : in std_logic_vector( 7 downto 0); + dipsw2_reg : in std_logic_vector( 7 downto 0) + ); + end; + +architecture RTL of PACMAN_MACHINE is + + -- timing + signal hcnt : std_logic_vector( 8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector( 8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean := true; + signal hblank : std_logic; + signal vblank : std_logic; +-- signal comp_sync_l : std_logic; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector( 7 downto 0); + signal cpu_data_in : std_logic_vector( 7 downto 0); + + signal program_rom : std_logic_vector( 7 downto 0); + signal program_rom_dinl : std_logic_vector( 7 downto 0); + signal program_rom_dinh : std_logic_vector( 7 downto 0); + signal program_rom_bufl : std_logic_vector( 7 downto 0); + signal program_rom_bufh : std_logic_vector( 7 downto 0); + signal program_rom_din : std_logic_vector( 7 downto 0); + signal rom_to_dec : std_logic_vector( 7 downto 0); + signal rom_from_dec : std_logic_vector( 7 downto 0); +-- signal program_rom_cs_l : std_logic; + + signal control_reg : std_logic_vector( 7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_reg : std_logic_vector( 7 downto 0); + signal sync_bus_db : std_logic_vector( 7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + signal sync_bus_cs_l : std_logic; + + signal cpu_vec_reg : std_logic_vector( 7 downto 0) := (others => '0'); + signal ps_reg : std_logic_vector( 2 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector( 7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector( 3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + v_blank <= vblank; + h_blank <= hblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + vsync <= not vcnt(8); + do_hsync <= true when (hcnt = "010101111") else false; -- 0AF + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off +-- watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + -- 7M + -- 7N + sync_bus_cs_l <= '1'; + -- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + + -- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then + -- program_rom_cs_l <= '0'; + -- end if; + + if (PENGO = '1' and cpu_addr(15) = '1') or (PACMAN = '1' and cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + + -- + -- vram addresser custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H => hcnt, + V => vcnt(7 downto 0), + FLIP => control_reg(3) + ); + + --When 2H is low, the CPU controls the bus. + ab <= cpu_addr(11 downto 0) when hcnt(1) = '0' else vram_addr_ab; + + -- vram_l <= not ((not (cpu_addr(12) or sync_bus_stb)) or (hcnt(1) and hcnt(0))); + vram_l <= ( (cpu_addr(12) or sync_bus_stb) and not (hcnt(1) and hcnt(0)) ); + + -- PENGO PACMAN + + -- WRITE + -- wr0_l 0x9000 - 0x900F voice 1,2,3 waveform wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x9010 - 0x901F x50 wr voice 1,2,3 freq/vol wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x9020 - 0x902F sprites wr2_l 0x5060 - 0x506F sprite + -- 0x5080 - 0x50BF unused + -- out_l 0x9040 - 0x904F control space out_l 0x5000 - 0x503F control space + -- wdr_l 0x9070 - 0x907F watchdog reset wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + -- dipsw2_l 0x9000 - 0x903F dip switch 2 + -- dipsw1_l 0x9040 - 0x907F dip switch 1 dipsw1_l 0x5080 - 0x50BF dip switches + -- in1_l 0x9080 - 0x90BF in port 1 in1_l 0x5040 - 0x507F in port 1 + -- in0_l 0x90C0 - 0x90FF in port 0 in0_l 0x5000 - 0x503F in port 0 + + -- writes <------------- PENGO -------------> <------------- PACMAN ------------> + wr0_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"0") or (PACMAN='1' and ab(7 downto 4)=x"4") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr voice 1,2,3 waveform + wr1_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"1") or (PACMAN='1' and ab(7 downto 4)=x"5") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr voice 1,2,3 freq/vol + wr2_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"2") or (PACMAN='1' and ab(7 downto 4)=x"6") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr sprites + iodec_out_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"4") or (PACMAN='1' and ab(7 downto 6)="00") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr control space + iodec_wdr_l <= '0' when sync_bus_r_w_l='0' and ( (PACMAN='0' and ab(7 downto 4)=x"7") or (PACMAN='1' and ab(7 downto 6)="11") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- wr watchdog reset + + -- reads + iodec_dipsw2_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="00") or (PACMAN='1' and ab(7 downto 6)="11") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in dip sw2 + iodec_dipsw1_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="01") or (PACMAN='1' and ab(7 downto 6)="10") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in dip sw1 + iodec_in1_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="10") or (PACMAN='1' and ab(7 downto 6)="01") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in port 1 + iodec_in0_l <= '0' when sync_bus_r_w_l='1' and ( (PACMAN='0' and ab(7 downto 6)="11") or (PACMAN='1' and ab(7 downto 6)="00") ) and cpu_addr(12)='1' and sync_bus_stb='0' else '1'; -- rd in port 0 + + ps_reg <= control_reg(7) & control_reg(6) & control_reg(2) when PENGO = '1' else "000"; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + -- 8 bit addressable latch 7K (made into register) + + -- PENGO PACMAN + -- 0 Interrupt ena Interrupt ena + -- 1 Sound ena Sound ena + -- 2 PS1 Not used + -- 3 Flip Flip + -- 4 Coin 1 meter 1 player start lamp + -- 5 Coin 2 meter 2 player start lamp + -- 6 PS2 Coin lockout + -- 7 PS3 Coin counter + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + sync_bus_db <= cpu_data_out when hcnt(1) = '0' else rams_data_out; + + -- address decoder + cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when (sync_bus_wreq_l = '0') else + program_rom when (PENGO = '1' and cpu_addr(15) = '0') else -- ROM at 0000 - 7fff (Pengo descrambler) + program_rom when (PACMAN = '1' and cpu_addr(15 downto 14) = "00") else -- ROM at 0000 - 3fff and 8000 - bfff + program_rom when (PACMAN = '1' and cpu_addr(15 downto 13) = "100") else -- ROM at 8000 - 9fff (LizWiz) + in0_reg when (iodec_in0_l = '0') else + in1_reg when (iodec_in1_l = '0') else + dipsw1_reg when (iodec_dipsw1_l = '0') else + dipsw2_reg when (iodec_dipsw2_l = '0') else + rams_data_out; + + u_adec : entity work.rom_descrambler + generic map ( + PENGO => PENGO, + PACMAN => PACMAN, + MRTNT => MRTNT, + LIZWIZ => LIZWIZ, + MSPACMAN => MSPACMAN + ) + port map ( + CLK => clk, + ENA => ena_6, + cpu_m1_l => cpu_m1_l, + addr => cpu_addr, + data => program_rom + ); + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab, + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab, + data_b_o => rams_data_out + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_PS => ps_reg, + I_WR2_L => wr2_l, + -- + O_RED => video_r, + O_GREEN => video_g, + O_BLUE => video_b, + -- + ENA_6 => ena_6, + CLK => clk + ); + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => audio, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd new file mode 100644 index 00000000..d5e5f484 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_rom_descrambler.vhd @@ -0,0 +1,479 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) d18c7db (gmail) - May 2013 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- + + +-- The following comments and source code in the comments are from MAME source code and are +-- included here to help make sense of the logic used in the VHDL address mapper and descrambler +-- +--/************************************ +-- * +-- * Ms. Pac-Man +-- * +-- ************************************/ +-- +--/* +-- Ms. Pac-Man has an auxiliary PCB with ribbon cable that plugs into the Z-80 CPU socket of a Pac-Man main PCB. Also the +-- graphics ROMs at 5E, 5F on the main board are replaced. +-- +-- The aux board contains three ROMs (two 2532 at U6, U7 and one 2716 at U5), a Z-80, and four PAL/HAL logic chips. +-- +-- The aux board logic decodes the Z-80 address and determines whether to enable the main board ROMs (containing Pac-Man +-- code) or the aux board ROMs (containing Ms. Pac-Man code). Normally the Pac-Man ROMs reside at address 0x0000-0x3fff +-- and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). The aux board logic modifies the address map and +-- enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. Furthermore there are forty 8-byte "patch" +-- regions which reside in the 0x0000-0x2fff address range. Any access to these patch addresses will disable the Pac-Man +-- ROMs and enable the aux board ROM. Aux board ROM addresses 0x8000-0x81ef are mapped onto the patch regions. These +-- patches typically insert jumps to new code above 0x8000. +-- +-- The aux board logic also acts as a software protection circuit which inhibits dumping of the ROMs (e.g., using a +-- microprocessor emulator system). There are several "trap" address regions which enable and disable the decode +-- functions. In order to properly operate as Ms. Pac-Man you must access one of the "latch set" trap addresses. This +-- enables the decode. If a "latch clear" address is accessed then decode is disabled and all you get is Pac-Man. For +-- more info see U.S. Patent 4,525,599 "Software protection methods and apparatus". +-- +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 +-- +-- Any memory access will trigger the trap behavior: instruction fetch, data read, data write. The latch clear addresses +-- should never be accessed during normal Ms. Pac-Man operation, so when the circuitry detects an access it clears the +-- latch and prevents any further dumping of the aux board ROMs. +-- +-- The Pac-Man self-test code does a checksum of the ROM 0x0000-0x2fff. This works because the checksum routine walks the +-- ROM starting from the low address and hits the latch clear trap at 0x0038 prior to encountering any of the patch +-- regions. The decode stays disabled for the rest of the checksum routine, and thus the checksum is calculated for the +-- Pac-Man ROMs with no patches applied. +-- +-- During normal operation every VBLANK (60.6Hz) interrupt will fetch its interrupt vector from the 0x3ff8 trap region, so +-- the latch is continually being enabled. +-- +-- In a further attempt to thwart copying, the aux board ROMs have a simple encryption scheme: their address and data +-- lines are bit flipped (i.e., wired in a nonstandard fashion). The specific bit flips were selected to minimize the +-- vias required to lay out the aux PCB. +--*/ + +-- +--static void mspacman_install_patches(UINT8 *ROM) +--{ +-- int i; +-- +-- /* copy forty 8-byte patches into Pac-Man code */ +-- for (i = 0; i < 8; i++) +-- { +-- ROM[0x0410+i] = ROM[0x8008+i]; +-- ROM[0x08E0+i] = ROM[0x81D8+i]; +-- ROM[0x0A30+i] = ROM[0x8118+i]; +-- ROM[0x0BD0+i] = ROM[0x80D8+i]; +-- ROM[0x0C20+i] = ROM[0x8120+i]; +-- ROM[0x0E58+i] = ROM[0x8168+i]; +-- ROM[0x0EA8+i] = ROM[0x8198+i]; +-- +-- ROM[0x1000+i] = ROM[0x8020+i]; +-- ROM[0x1008+i] = ROM[0x8010+i]; +-- ROM[0x1288+i] = ROM[0x8098+i]; +-- ROM[0x1348+i] = ROM[0x8048+i]; +-- ROM[0x1688+i] = ROM[0x8088+i]; +-- ROM[0x16B0+i] = ROM[0x8188+i]; +-- ROM[0x16D8+i] = ROM[0x80C8+i]; +-- ROM[0x16F8+i] = ROM[0x81C8+i]; +-- ROM[0x19A8+i] = ROM[0x80A8+i]; +-- ROM[0x19B8+i] = ROM[0x81A8+i]; +-- +-- ROM[0x2060+i] = ROM[0x8148+i]; +-- ROM[0x2108+i] = ROM[0x8018+i]; +-- ROM[0x21A0+i] = ROM[0x81A0+i]; +-- ROM[0x2298+i] = ROM[0x80A0+i]; +-- ROM[0x23E0+i] = ROM[0x80E8+i]; +-- ROM[0x2418+i] = ROM[0x8000+i]; +-- ROM[0x2448+i] = ROM[0x8058+i]; +-- ROM[0x2470+i] = ROM[0x8140+i]; +-- ROM[0x2488+i] = ROM[0x8080+i]; +-- ROM[0x24B0+i] = ROM[0x8180+i]; +-- ROM[0x24D8+i] = ROM[0x80C0+i]; +-- ROM[0x24F8+i] = ROM[0x81C0+i]; +-- ROM[0x2748+i] = ROM[0x8050+i]; +-- ROM[0x2780+i] = ROM[0x8090+i]; +-- ROM[0x27B8+i] = ROM[0x8190+i]; +-- ROM[0x2800+i] = ROM[0x8028+i]; +-- ROM[0x2B20+i] = ROM[0x8100+i]; +-- ROM[0x2B30+i] = ROM[0x8110+i]; +-- ROM[0x2BF0+i] = ROM[0x81D0+i]; +-- ROM[0x2CC0+i] = ROM[0x80D0+i]; +-- ROM[0x2CD8+i] = ROM[0x80E0+i]; +-- ROM[0x2CF0+i] = ROM[0x81E0+i]; +-- ROM[0x2D60+i] = ROM[0x8160+i]; +-- } +--} +-- +--DRIVER_INIT_MEMBER(pacman_state,mspacman) +--{ +-- int i; +-- UINT8 *ROM, *DROM; +-- +-- /* CPU ROMs */ +-- +-- /* Pac-Man code is in low bank */ +-- ROM = machine().root_device().memregion("maincpu")->base(); +-- +-- /* decrypted Ms. Pac-Man code is in high bank */ +-- DROM = &machine().root_device().memregion("maincpu")->base()[0x10000]; +-- +-- /* copy ROMs into decrypted bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0x0000+i] = ROM[0x0000+i]; /* pacman.6e */ +-- DROM[0x1000+i] = ROM[0x1000+i]; /* pacman.6f */ +-- DROM[0x2000+i] = ROM[0x2000+i]; /* pacman.6h */ +-- DROM[0x3000+i] = BITSWAP8(ROM[0xb000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u7 */ +-- } +-- for (i = 0; i < 0x800; i++) +-- { +-- DROM[0x8000+i] = BITSWAP8(ROM[0x8000+BITSWAP16(i,15,14,13,12,11,8,7,5,9,10,6,3,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt u5 */ +-- DROM[0x8800+i] = BITSWAP8(ROM[0x9800+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +-- DROM[0x9000+i] = BITSWAP8(ROM[0x9000+BITSWAP16(i,15,14,13,12,11,3,7,9,10,8,6,5,4,2,1,0)],0,4,5,7,6,3,2,1); /* decrypt half of u6 */ +--// 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 +-- DROM[0x9800+i] = ROM[0x1800+i]; /* mirror of pacman.6f high */ +-- } +-- for (i = 0; i < 0x1000; i++) +-- { +-- DROM[0xa000+i] = ROM[0x2000+i]; /* mirror of pacman.6h */ +-- DROM[0xb000+i] = ROM[0x3000+i]; /* mirror of pacman.6j */ +-- } +-- /* install patches into decrypted bank */ +-- mspacman_install_patches(DROM); +-- +-- /* mirror Pac-Man ROMs into upper addresses of normal bank */ +-- for (i = 0; i < 0x1000; i++) +-- { +-- ROM[0x8000+i] = ROM[0x0000+i]; +-- ROM[0x9000+i] = ROM[0x1000+i]; +-- ROM[0xa000+i] = ROM[0x2000+i]; +-- ROM[0xb000+i] = ROM[0x3000+i]; +-- } +-- +-- /* initialize the banks */ +-- machine().root_device().membank("bank1")->configure_entries(0, 2, &ROM[0x00000], 0x10000); +-- machine().root_device().membank("bank1")->set_entry(1); +--} +-- +--ROM_START( puckmana ) +-- ROM_REGION( 0x10000, "maincpu", 0 ) +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "prg7", 0x3000, 0x0800, CRC(b6289b26) SHA1(d249fa9cdde774d5fee7258147cd25fa3f4dc2b3) ) +-- ROM_LOAD( "prg8", 0x3800, 0x0800, CRC(17a88c13) SHA1(eb462de79f49b7aa8adb0cc6d31535b10550c0ce) ) +-- +--ROM_START( mspacman ) +-- ROM_REGION( 0x20000, "maincpu", 0 ) /* 64k for code+64k for decrypted code */ +-- ROM_LOAD( "pacman.6e", 0x0000, 0x1000, CRC(c1e6ab10) SHA1(e87e059c5be45753f7e9f33dff851f16d6751181) ) +-- ROM_LOAD( "pacman.6f", 0x1000, 0x1000, CRC(1a6fb2d4) SHA1(674d3a7f00d8be5e38b1fdc208ebef5a92d38329) ) +-- ROM_LOAD( "pacman.6h", 0x2000, 0x1000, CRC(bcdd1beb) SHA1(8e47e8c2c4d6117d174cdac150392042d3e0a881) ) +-- ROM_LOAD( "pacman.6j", 0x3000, 0x1000, CRC(817d94e3) SHA1(d4a70d56bb01d27d094d73db8667ffb00ca69cb9) ) +-- +-- ROM_LOAD( "u5", 0x8000, 0x0800, CRC(f45fbbcd) SHA1(b26cc1c8ee18e9b1daa97956d2159b954703a0ec) ) +-- ROM_LOAD( "u6", 0x9000, 0x1000, CRC(a90e7000) SHA1(e4df96f1db753533f7d770aa62ae1973349ea4cf) ) +-- ROM_LOAD( "u7", 0xb000, 0x1000, CRC(c82cd714) SHA1(1d8ac7ad03db2dc4c8c18ade466e12032673f874) ) +-- +-- +--Normally the Pac-Man ROMs reside at address 0x0000-0x3fff and are mirrored at 0x8000-0xbfff (Z-80 A15 is not used in Pac-Man). +--The aux board logic modifies the address map and enables the aux board ROMs for addresses 0x3000-0x3fff and 0x8000-0x97ff. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity rom_descrambler is + generic ( + -- only set one of these + PENGO : std_logic := '0'; -- set to 1 when using Pengo ROMs, 0 otherwise + PACMAN : std_logic := '1'; -- set to 1 for all other Pacman hardware games + -- only set one of these when PACMAN is set + MRTNT : std_logic := '0'; -- set to 1 when using Mr TNT ROMs, 0 otherwise + LIZWIZ : std_logic := '0'; -- set to 1 when using Lizard Wizard ROMs, 0 otherwise + MSPACMAN : std_logic := '0' -- set to 1 when using Ms Pacman ROMs, 0 otherwise + ); + port ( + CLK : in std_logic; + ENA : in std_logic; + -- + cpu_m1_l : in std_logic; + addr : in std_logic_vector(15 downto 0); + data : out std_logic_vector( 7 downto 0) + ); + +end rom_descrambler; + +architecture rtl of rom_descrambler is + signal overlay_on : std_logic := '0'; + signal sega_dec_ena : std_logic; + signal rom_patched : std_logic_vector(15 downto 0); + signal rom_addr : std_logic_vector(15 downto 0); + signal rom_lo : std_logic_vector( 7 downto 0); + signal rom_hi : std_logic_vector( 7 downto 0); + signal rom_data_in : std_logic_vector( 7 downto 0); + signal rom_data_out : std_logic_vector( 7 downto 0); + signal sega_dec : std_logic_vector( 7 downto 0); +begin + -- ROM at 0000 - 3FFF + u_program_rom0 : entity work.ROM_PGM_0 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_lo + ); + + -- ROM at 8000 - BFFF (Liz Wiz) + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => CLK, + ADDR => rom_addr(13 downto 0), + DATA => rom_hi + ); + + -- Sega ROM descrambler adapted from MAME segacrpt.c source code + u_sega_decode : entity work.sega_decode + port map ( + I_CK => clk, + I_DEC => sega_dec_ena, -- passthrough when low + I_A(6) => cpu_m1_l, + I_A(5) => rom_addr(12), + I_A(4) => rom_addr(8), + I_A(3) => rom_addr(4), + I_A(2) => rom_addr(0), + I_A(1) => rom_data_in(5), + I_A(0) => rom_data_in(3), + I_D => rom_data_in, + O_D => sega_dec + ); + + sega_dec_ena <= PENGO and (not rom_addr(15)); + +-- The trap regions are 8 bytes in length starting on the following addresses: +-- +-- latch clear, decode disable +-- 0x0038 +-- 0x03b0 +-- 0x1600 +-- 0x2120 +-- 0x3ff0 +-- 0x8000 +-- 0x97f0 +-- +-- latch set, decode enable +-- 0x3ff8 + p_overlay : process + variable trap_addr : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + trap_addr := addr(15 downto 3) & "000"; + if trap_addr = x"3ff8" then + overlay_on <= '1'; + elsif + trap_addr = x"0038" or + trap_addr = x"03b0" or + trap_addr = x"1600" or + trap_addr = x"2120" or + trap_addr = x"3ff0" or + trap_addr = x"8000" or + trap_addr = x"97f0" + then + overlay_on <= '0'; + end if; + end process; + + p_decoder_comb : process(clk, rom_addr, addr, rom_data_in, rom_data_out, rom_patched, rom_hi, rom_lo, overlay_on, sega_dec) + variable patch_addr : std_logic_vector(15 downto 0); + begin + rom_addr <= addr; + rom_patched <= addr; + data <= rom_data_out; + + -- default is unscrambled data + rom_data_out <= rom_data_in ; + + -- mux ROMs to same data bus + -- ignore A15 so that Pacman ROMs 0000-3FFF mirror in high mem at 8000-BFFF + if rom_addr(14) = '0' then + rom_data_in <= rom_lo; + else + rom_data_in <= rom_hi; + end if; + + -- Mr TNT program ROMs have data lines D3 and D5 swapped + -- Mr TNT video ROMs have data lines D4 and D6 and address lines A0 and A2 swapped + if MRTNT = '1' then + rom_data_out <= rom_data_in(7 downto 6) & rom_data_in(3) & rom_data_in(4) & rom_data_in(5) & rom_data_in(2 downto 0); + end if; + + if PENGO = '1' then + -- ROM at 0000 - 7fff (Pengo) + if rom_addr(15) = '0' then + rom_data_out <= sega_dec; + end if; + end if; + + if MSPACMAN = '1' and overlay_on = '1' then + -- forty 8-byte patches into Pac-Man code + -- If the CPU address presented falls in a patch range, substitute it with patched address + -- OH THE HUMANITY!!! + patch_addr := addr(15 downto 3) & "000"; + case patch_addr is + when x"0410" => rom_patched <= x"800" & '1' & addr(2 downto 0); -- ROM[0x0410+i] = ROM[0x8008+i] + when x"08E0" => rom_patched <= x"81D" & '1' & addr(2 downto 0); -- ROM[0x08E0+i] = ROM[0x81D8+i] + when x"0A30" => rom_patched <= x"811" & '1' & addr(2 downto 0); -- ROM[0x0A30+i] = ROM[0x8118+i] + when x"0BD0" => rom_patched <= x"80D" & '1' & addr(2 downto 0); -- ROM[0x0BD0+i] = ROM[0x80D8+i] + when x"0C20" => rom_patched <= x"812" & '0' & addr(2 downto 0); -- ROM[0x0C20+i] = ROM[0x8120+i] + when x"0E58" => rom_patched <= x"816" & '1' & addr(2 downto 0); -- ROM[0x0E58+i] = ROM[0x8168+i] + when x"0EA8" => rom_patched <= x"819" & '1' & addr(2 downto 0); -- ROM[0x0EA8+i] = ROM[0x8198+i] + + when x"1000" => rom_patched <= x"802" & '0' & addr(2 downto 0); -- ROM[0x1000+i] = ROM[0x8020+i] + when x"1008" => rom_patched <= x"801" & '0' & addr(2 downto 0); -- ROM[0x1008+i] = ROM[0x8010+i] + when x"1288" => rom_patched <= x"809" & '1' & addr(2 downto 0); -- ROM[0x1288+i] = ROM[0x8098+i] + when x"1348" => rom_patched <= x"804" & '1' & addr(2 downto 0); -- ROM[0x1348+i] = ROM[0x8048+i] + when x"1688" => rom_patched <= x"808" & '1' & addr(2 downto 0); -- ROM[0x1688+i] = ROM[0x8088+i] + when x"16B0" => rom_patched <= x"818" & '1' & addr(2 downto 0); -- ROM[0x16B0+i] = ROM[0x8188+i] + when x"16D8" => rom_patched <= x"80C" & '1' & addr(2 downto 0); -- ROM[0x16D8+i] = ROM[0x80C8+i] + when x"16F8" => rom_patched <= x"81C" & '1' & addr(2 downto 0); -- ROM[0x16F8+i] = ROM[0x81C8+i] + when x"19A8" => rom_patched <= x"80A" & '1' & addr(2 downto 0); -- ROM[0x19A8+i] = ROM[0x80A8+i] + when x"19B8" => rom_patched <= x"81A" & '1' & addr(2 downto 0); -- ROM[0x19B8+i] = ROM[0x81A8+i] + + when x"2060" => rom_patched <= x"814" & '1' & addr(2 downto 0); -- ROM[0x2060+i] = ROM[0x8148+i] + when x"2108" => rom_patched <= x"801" & '1' & addr(2 downto 0); -- ROM[0x2108+i] = ROM[0x8018+i] + when x"21A0" => rom_patched <= x"81A" & '0' & addr(2 downto 0); -- ROM[0x21A0+i] = ROM[0x81A0+i] + when x"2298" => rom_patched <= x"80A" & '0' & addr(2 downto 0); -- ROM[0x2298+i] = ROM[0x80A0+i] + when x"23E0" => rom_patched <= x"80E" & '1' & addr(2 downto 0); -- ROM[0x23E0+i] = ROM[0x80E8+i] + when x"2418" => rom_patched <= x"800" & '0' & addr(2 downto 0); -- ROM[0x2418+i] = ROM[0x8000+i] + when x"2448" => rom_patched <= x"805" & '1' & addr(2 downto 0); -- ROM[0x2448+i] = ROM[0x8058+i] + when x"2470" => rom_patched <= x"814" & '0' & addr(2 downto 0); -- ROM[0x2470+i] = ROM[0x8140+i] + when x"2488" => rom_patched <= x"808" & '0' & addr(2 downto 0); -- ROM[0x2488+i] = ROM[0x8080+i] + when x"24B0" => rom_patched <= x"818" & '0' & addr(2 downto 0); -- ROM[0x24B0+i] = ROM[0x8180+i] + when x"24D8" => rom_patched <= x"80C" & '0' & addr(2 downto 0); -- ROM[0x24D8+i] = ROM[0x80C0+i] + when x"24F8" => rom_patched <= x"81C" & '0' & addr(2 downto 0); -- ROM[0x24F8+i] = ROM[0x81C0+i] + when x"2748" => rom_patched <= x"805" & '0' & addr(2 downto 0); -- ROM[0x2748+i] = ROM[0x8050+i] + when x"2780" => rom_patched <= x"809" & '0' & addr(2 downto 0); -- ROM[0x2780+i] = ROM[0x8090+i] + when x"27B8" => rom_patched <= x"819" & '0' & addr(2 downto 0); -- ROM[0x27B8+i] = ROM[0x8190+i] + when x"2800" => rom_patched <= x"802" & '1' & addr(2 downto 0); -- ROM[0x2800+i] = ROM[0x8028+i] + when x"2B20" => rom_patched <= x"810" & '0' & addr(2 downto 0); -- ROM[0x2B20+i] = ROM[0x8100+i] + when x"2B30" => rom_patched <= x"811" & '0' & addr(2 downto 0); -- ROM[0x2B30+i] = ROM[0x8110+i] + when x"2BF0" => rom_patched <= x"81D" & '0' & addr(2 downto 0); -- ROM[0x2BF0+i] = ROM[0x81D0+i] + when x"2CC0" => rom_patched <= x"80D" & '0' & addr(2 downto 0); -- ROM[0x2CC0+i] = ROM[0x80D0+i] + when x"2CD8" => rom_patched <= x"80E" & '0' & addr(2 downto 0); -- ROM[0x2CD8+i] = ROM[0x80E0+i] + when x"2CF0" => rom_patched <= x"81E" & '0' & addr(2 downto 0); -- ROM[0x2CF0+i] = ROM[0x81E0+i] + when x"2D60" => rom_patched <= x"816" & '0' & addr(2 downto 0); -- ROM[0x2D60+i] = ROM[0x8160+i] + when others => rom_patched <= addr; + end case; + +-- Pacman ROMs +-- 0x0000-0x0FFF = 0x0000-0x0FFF; /* pacman.6e */ +-- 0x1000-0x1FFF = 0x1000-0x1FFF; /* pacman.6f */ +-- 0x2000-0x2FFF = 0x2000-0x2FFF; /* pacman.6h */ +-- 0x3000-0x3FFF = 0x3000-0x3FFF; /* pacman.6j */ + +-- ROM mirror (easy just ignore A15) +-- 0x8000-0x8FFF = 0x0000-0x0FFF; /* mirror of pacman.6e */ +-- 0x9000-0x9FFF = 0x1000-0x1FFF; /* mirror of pacman.6f */ +-- 0xA000-0xAFFF = 0x2000-0x2FFF; /* mirror of pacman.6h */ +-- 0xB000-0xBFFF = 0x3000-0x3FFF; /* mirror of pacman.6j */ + +-- Ms Pacman overlays + +-- no xlate +-- 0x8000-0x87FF = 0x8000-0x87FF (physical ROM hi 0000-07FF); /* decrypt u5 */ +-- 0x9000-0x97FF = 0x9000-0x97FF (physical ROM hi 1000-17FF); /* decrypt half of u6 */ + +-- xlate addr +-- 0x3000-0x3FFF = 0xB000-0xBFFF (physical ROM hi 2000-2FFF); /* decrypt u7 */ + +-- xlate addr +-- 0x8800-0x8FFF = 0x9800-0x9FFF (physical ROM hi 1800-1FFF); /* decrypt half of u6 */ + +-- ROM hi mem map +-- u5 2K 0000-07FF (0x8000-0x87FF) +-- u5 2K 0800-0FFF N/A +-- u6b 2K 1000-17FF (0x9000-0x97FF) +-- u6t 2K 1800-1FFF (0x8800-0x8FFF) +-- u7 4K 2000-2FFF (0x3000-0x3FFF) + + -- If the new patched address falls in certain Ms Pacman ranges, swap in ROM overlays and descramble address and data + -- high address bits are not scrambled so we know for sure this only accesses ROM hi after address translation + case rom_patched(15 downto 11) is + + -- addr = 0x3000-0x37FF, xlate to 0xB000-0xB7FF (physical ROM hi 2000-27FF), decrypt half of u7 + when "00110" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x3800-0x3FFF, xlate to 0xB800-0xBFFF (physical ROM hi 2800-2FFF), decrypt half of u7 + when "00111" => + rom_addr <= x"2" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8000-0x87FF, no xlate (physical ROM hi 0000-07FF), decrypt u5 + when "10000" => + rom_addr <= x"0" & rom_patched(11) & rom_patched(8) & rom_patched(7) & rom_patched(5) & rom_patched(9) & rom_patched(10) & rom_patched(6) & rom_patched(3) & rom_patched(4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x8800-0x8FFF, xlate to 0x9800-0x9FFF (physical ROM hi 1800-1FFF), decrypt half of u6 + when "10001" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- addr = 0x9000-0x97FF, no xlate (physical ROM hi 1000-17FF), decrypt half of u6 + when "10010" => + rom_addr <= x"1" & rom_patched(11) & rom_patched(3) & rom_patched(7) & rom_patched(9) & rom_patched(10) & rom_patched(8) & rom_patched(6 downto 4) & rom_patched(2 downto 0); + rom_data_out <= rom_hi(0) & rom_hi(4) & rom_hi(5) & rom_hi(7 downto 6) & rom_hi(3 downto 1); + + -- catch all default action + when others => null; + rom_addr <= rom_patched; + rom_data_out <= rom_data_in; + end case; + end if; + end process; + +end rtl; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..d502530c --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_video.vhd @@ -0,0 +1,371 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '1' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_PS : in std_logic_vector( 2 downto 0); + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(13 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, I_PS(2), + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(13) <= I_PS(2); + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(9) => '0', + ADDR(8) => I_PS(1), + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(4) => I_PS(0), + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..33b9febe --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,73 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is +port ( + AB : out std_logic_vector (11 downto 0); + H : in std_logic_vector ( 8 downto 0); -- H256_L H128 H64 H32 H16 H8 H4 H2 H1 + V : in std_logic_vector ( 7 downto 0); -- V128 V64 v32 V16 V8 V4 V2 V1 + FLIP : in std_logic +); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + signal sel : std_logic; + signal y157_bus : std_logic_vector (11 downto 0); + signal y257_bus : std_logic_vector (11 downto 0); + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); +begin + hp <= H(7 downto 3) xor (FLIP & FLIP & FLIP & FLIP & FLIP); + vp <= V(7 downto 3) xor (FLIP & FLIP & FLIP & FLIP & FLIP); + + sel <= not ( (H(5) xor H(4)) or (H(5) xor H(6)) ); + y157_bus <= '0' & H(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp when sel='1' else x"FF" & H(6 downto 4) & H(2); + y257_bus <= y157_bus when H(8)='0' else '0' & H(2) & vp & hp; + AB <= y257_bus when H(1) = '1' else (others => 'Z'); + +end RTL; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Pengo_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd b/Arcade/Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd new file mode 100644 index 00000000..8ae8141d --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/sega_decode.vhd @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------- +-- Pengo decode table +-- /* opcode (M1=0) data (M1=1) address */ +-- /* 0 1 2 3 0 1 2 3 A12 A8 A4 A0 */ +-- { 0xa0,0x80,0xa8,0x88 }, { 0x28,0xa8,0x08,0x88 }, /* ...0...0...0...0 */ +-- { 0x28,0xa8,0x08,0x88 }, { 0xa0,0x80,0xa8,0x88 }, /* ...0...0...0...1 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...0...0...1...0 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0xa0,0x80,0xa8,0x88 }, /* ...0...0...1...1 */ +-- { 0x08,0x00,0x88,0x80 }, { 0x28,0xa8,0x08,0x88 }, /* ...0...1...0...0 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0x08,0x00,0x88,0x80 }, /* ...0...1...0...1 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...0...1...1...0 */ +-- { 0xa0,0x80,0x20,0x00 }, { 0x00,0x08,0x20,0x28 }, /* ...0...1...1...1 */ +-- { 0x88,0x80,0x08,0x00 }, { 0xa0,0x80,0x20,0x00 }, /* ...1...0...0...0 */ +-- { 0x88,0x80,0x08,0x00 }, { 0x00,0x08,0x20,0x28 }, /* ...1...0...0...1 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0x08,0x28,0x88,0xa8 }, /* ...1...0...1...0 */ +-- { 0xa0,0x80,0xa8,0x88 }, { 0xa0,0x80,0x20,0x00 }, /* ...1...0...1...1 */ +-- { 0x08,0x00,0x88,0x80 }, { 0x88,0x80,0x08,0x00 }, /* ...1...1...0...0 */ +-- { 0x00,0x08,0x20,0x28 }, { 0x88,0x80,0x08,0x00 }, /* ...1...1...0...1 */ +-- { 0x08,0x28,0x88,0xa8 }, { 0x08,0x28,0x88,0xa8 }, /* ...1...1...1...0 */ +-- { 0x08,0x00,0x88,0x80 }, { 0xa0,0x80,0x20,0x00 } /* ...1...1...1...1 */ +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity sega_decode is + port ( + I_DEC : in std_logic; + I_CK : in std_logic; + -- + I_A : in std_logic_vector(6 downto 0); + I_D : in std_logic_vector(7 downto 0); + O_D : out std_logic_vector(7 downto 0) + ); + +end sega_decode; + +architecture rtl of sega_decode is + signal sel : std_logic_vector(6 downto 0); + signal val : std_logic_vector(2 downto 0); +begin + p_decoder : process + begin + wait until rising_edge(I_CK); + if (I_DEC = '0') then + O_D <= I_D; -- passthough + else + sel <= I_A xor ("00000" & I_D(7) & I_D(7)); + O_D(7) <= I_D(7) xor val(2); + O_D(6) <= I_D(6); + O_D(5) <= I_D(7) xor val(1); + O_D(4) <= I_D(4); + O_D(3) <= I_D(7) xor val(0); + O_D(2) <= I_D(2); + O_D(1) <= I_D(1); + O_D(0) <= I_D(0); + case sel is -- M1 A12 A8 A4 A0 D5 D3 + when "0000000" => val <= "110"; + when "0000001" => val <= "100"; + when "0000010" => val <= "111"; + when "0000011" => val <= "101"; + when "0000100" => val <= "011"; + when "0000101" => val <= "111"; + when "0000110" => val <= "001"; + when "0000111" => val <= "101"; + when "0001000" => val <= "110"; + when "0001001" => val <= "100"; + when "0001010" => val <= "010"; + when "0001011" => val <= "000"; + when "0001100" => val <= "001"; + when "0001101" => val <= "011"; + when "0001110" => val <= "101"; + when "0001111" => val <= "111"; + when "0010000" => val <= "001"; + when "0010001" => val <= "000"; + when "0010010" => val <= "101"; + when "0010011" => val <= "100"; + when "0010100" => val <= "110"; + when "0010101" => val <= "100"; + when "0010110" => val <= "010"; + when "0010111" => val <= "000"; + when "0011000" => val <= "110"; + when "0011001" => val <= "100"; + when "0011010" => val <= "010"; + when "0011011" => val <= "000"; + when "0011100" => val <= "110"; + when "0011101" => val <= "100"; + when "0011110" => val <= "010"; + when "0011111" => val <= "000"; + when "0100000" => val <= "101"; + when "0100001" => val <= "100"; + when "0100010" => val <= "001"; + when "0100011" => val <= "000"; + when "0100100" => val <= "101"; + when "0100101" => val <= "100"; + when "0100110" => val <= "001"; + when "0100111" => val <= "000"; + when "0101000" => val <= "001"; + when "0101001" => val <= "011"; + when "0101010" => val <= "101"; + when "0101011" => val <= "111"; + when "0101100" => val <= "110"; + when "0101101" => val <= "100"; + when "0101110" => val <= "111"; + when "0101111" => val <= "101"; + when "0110000" => val <= "001"; + when "0110001" => val <= "000"; + when "0110010" => val <= "101"; + when "0110011" => val <= "100"; + when "0110100" => val <= "000"; + when "0110101" => val <= "001"; + when "0110110" => val <= "010"; + when "0110111" => val <= "011"; + when "0111000" => val <= "001"; + when "0111001" => val <= "011"; + when "0111010" => val <= "101"; + when "0111011" => val <= "111"; + when "0111100" => val <= "001"; + when "0111101" => val <= "000"; + when "0111110" => val <= "101"; + when "0111111" => val <= "100"; + when "1000000" => val <= "011"; + when "1000001" => val <= "111"; + when "1000010" => val <= "001"; + when "1000011" => val <= "101"; + when "1000100" => val <= "110"; + when "1000101" => val <= "100"; + when "1000110" => val <= "111"; + when "1000111" => val <= "101"; + when "1001000" => val <= "110"; + when "1001001" => val <= "100"; + when "1001010" => val <= "010"; + when "1001011" => val <= "000"; + when "1001100" => val <= "110"; + when "1001101" => val <= "100"; + when "1001110" => val <= "111"; + when "1001111" => val <= "101"; + when "1010000" => val <= "011"; + when "1010001" => val <= "111"; + when "1010010" => val <= "001"; + when "1010011" => val <= "101"; + when "1010100" => val <= "001"; + when "1010101" => val <= "000"; + when "1010110" => val <= "101"; + when "1010111" => val <= "100"; + when "1011000" => val <= "110"; + when "1011001" => val <= "100"; + when "1011010" => val <= "010"; + when "1011011" => val <= "000"; + when "1011100" => val <= "000"; + when "1011101" => val <= "001"; + when "1011110" => val <= "010"; + when "1011111" => val <= "011"; + when "1100000" => val <= "110"; + when "1100001" => val <= "100"; + when "1100010" => val <= "010"; + when "1100011" => val <= "000"; + when "1100100" => val <= "000"; + when "1100101" => val <= "001"; + when "1100110" => val <= "010"; + when "1100111" => val <= "011"; + when "1101000" => val <= "001"; + when "1101001" => val <= "011"; + when "1101010" => val <= "101"; + when "1101011" => val <= "111"; + when "1101100" => val <= "110"; + when "1101101" => val <= "100"; + when "1101110" => val <= "010"; + when "1101111" => val <= "000"; + when "1110000" => val <= "101"; + when "1110001" => val <= "100"; + when "1110010" => val <= "001"; + when "1110011" => val <= "000"; + when "1110100" => val <= "101"; + when "1110101" => val <= "100"; + when "1110110" => val <= "001"; + when "1110111" => val <= "000"; + when "1111000" => val <= "001"; + when "1111001" => val <= "011"; + when "1111010" => val <= "101"; + when "1111011" => val <= "111"; + when "1111100" => val <= "110"; + when "1111101" => val <= "100"; + when "1111110" => val <= "010"; + when "1111111" => val <= "000"; + when others => null; + end case; + end if; + end process; +end rtl; diff --git a/Arcade/Pacman Hardware/Pengo_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Pengo_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Pengo_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf b/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf new file mode 100644 index 00000000..c49afdb0 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Ponpoko" diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf b/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf new file mode 100644 index 00000000..4fcaf782 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Ponpoko_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Ponpoko.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Ponpoko +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.srf b/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/Ponpoko.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/README.txt b/Arcade/Pacman Hardware/Ponpoko_MiST/README.txt new file mode 100644 index 00000000..ed50b674 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/README.txt @@ -0,0 +1,24 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Ponpoko for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- SPACE,CTRL : Jump +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/Release/Ponpoko.rbf b/Arcade/Pacman Hardware/Ponpoko_MiST/Release/Ponpoko.rbf new file mode 100644 index 00000000..58c58abf Binary files /dev/null and b/Arcade/Pacman Hardware/Ponpoko_MiST/Release/Ponpoko.rbf differ diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/clean.bat b/Arcade/Pacman Hardware/Ponpoko_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv new file mode 100644 index 00000000..21d45217 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/Ponpoko.sv @@ -0,0 +1,195 @@ +//============================================================================ +// Arcade: Ponpoko +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Ponpoko +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Ponpoko;;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +assign LED = 1; +//wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +//wire m_skip = kbjoy[9]; + + +pacman ponpoko +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0({~{2'b00, m_coin}, m_fire, m_down,m_right,m_left,m_up}), + .in1({1'b0, m_start2, m_start1, m_fire, m_down,m_right,m_left,m_up}), + + .dipsw1(8'b1_1_11_11_01), + .dipsw2(8'b1111_0001), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..f0842342 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"CC",X"66",X"33",X"33",X"33",X"22",X"CC",X"00",X"11",X"22",X"66",X"66",X"66",X"33",X"11",X"00", + X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"FF",X"00",X"00",X"11",X"00",X"00",X"00",X"00",X"33",X"00", + X"EE",X"33",X"77",X"EE",X"88",X"00",X"FF",X"00",X"33",X"66",X"00",X"11",X"33",X"66",X"77",X"00", + X"FF",X"66",X"CC",X"EE",X"33",X"33",X"EE",X"00",X"77",X"00",X"00",X"11",X"00",X"44",X"33",X"00", + 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X"0E",X"08",X"66",X"6E",X"0F",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"03",X"03",X"01",X"00",X"00",X"00",X"03",X"03",X"0E",X"0A",X"02",X"0A",X"07",X"02", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00",X"01",X"07",X"0F",X"02",X"06", + X"00",X"01",X"07",X"0F",X"3C",X"E0",X"00",X"00",X"04",X"08",X"08",X"87",X"01",X"01",X"01",X"01", + X"00",X"00",X"00",X"02",X"07",X"0E",X"0E",X"08",X"00",X"00",X"00",X"00",X"0C",X"0E",X"06",X"01", + X"00",X"00",X"00",X"00",X"60",X"02",X"02",X"07",X"00",X"00",X"00",X"00",X"60",X"04",X"04",X"0E", + X"00",X"0C",X"00",X"0C",X"00",X"08",X"04",X"08",X"00",X"07",X"08",X"03",X"04",X"09",X"02",X"04", + X"2F",X"1F",X"1F",X"1F",X"2F",X"03",X"00",X"00",X"4F",X"8F",X"8F",X"8F",X"4F",X"0C",X"00",X"00", + X"00",X"02",X"06",X"0C",X"09",X"0B",X"0E",X"08",X"00",X"00",X"08",X"04",X"02",X"0E",X"06",X"01", + X"00",X"00",X"00",X"00",X"60",X"02",X"02",X"07",X"00",X"00",X"00",X"00",X"60",X"04",X"04",X"0E", + X"00",X"0E",X"01",X"0C",X"02",X"09",X"04",X"02",X"00",X"03",X"00",X"03",X"00",X"01",X"02",X"01", + X"2F",X"1F",X"1F",X"1F",X"2F",X"03",X"00",X"00",X"4F",X"8F",X"8F",X"8F",X"4F",X"0C",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"11",X"0C",X"03",X"11", + X"00",X"FF",X"FF",X"FF",X"F9",X"FD",X"FF",X"FF",X"00",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"EE", + X"00",X"00",X"00",X"88",X"BB",X"CC",X"CC",X"00",X"33",X"11",X"00",X"00",X"11",X"11",X"00",X"00", + X"FF",X"FF",X"66",X"FF",X"FF",X"FF",X"CC",X"00",X"CC",X"00",X"00",X"99",X"FF",X"FF",X"CC",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"33",X"11",X"00",X"03",X"1D", + X"00",X"FF",X"FF",X"FF",X"F9",X"FD",X"FF",X"FF",X"00",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"EE", + X"00",X"00",X"00",X"22",X"AA",X"CC",X"00",X"00",X"33",X"11",X"00",X"00",X"11",X"11",X"11",X"00", + X"FF",X"FF",X"66",X"EE",X"FF",X"FF",X"33",X"00",X"CC",X"00",X"00",X"66",X"FF",X"FF",X"33",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"70",X"71",X"31",X"10",X"00", + X"00",X"80",X"D0",X"D0",X"FD",X"F5",X"D2",X"0F",X"00",X"C0",X"E0",X"F0",X"FC",X"E4",X"C1",X"0E", + X"00",X"00",X"20",X"42",X"42",X"48",X"08",X"00",X"03",X"00",X"01",X"02",X"00",X"00",X"00",X"00", + X"7F",X"3F",X"F0",X"07",X"70",X"07",X"30",X"00",X"8F",X"0C",X"E0",X"0C",X"C2",X"1E",X"90",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"00",X"10",X"30",X"70",X"71",X"31",X"14",X"03", + X"00",X"80",X"D0",X"D0",X"FD",X"F5",X"D2",X"0F",X"00",X"C0",X"E0",X"F0",X"FC",X"E4",X"C0",X"0F", + X"00",X"08",X"00",X"00",X"48",X"4A",X"08",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00", + X"7F",X"3F",X"07",X"70",X"07",X"70",X"03",X"00",X"8E",X"0D",X"0E",X"C0",X"0E",X"D2",X"18",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..17522bd2 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"03", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"05",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"07", + X"00",X"00",X"00",X"00",X"00",X"0B",X"01",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"00",X"01",X"0C",X"0F", + X"00",X"0E",X"00",X"0B",X"00",X"0C",X"0B",X"0E",X"00",X"0C",X"0F",X"01",X"00",X"00",X"00",X"00", + X"00",X"01",X"02",X"0F",X"00",X"07",X"0C",X"02",X"00",X"09",X"06",X"0F",X"00",X"0D",X"0C",X"0F", + X"00",X"05",X"03",X"09",X"00",X"0F",X"0B",X"00",X"00",X"0E",X"00",X"0B",X"00",X"0E",X"00",X"0B", + X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"01",X"00",X"0F",X"0B",X"0E",X"00",X"0E",X"00",X"0F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..e6cf72e3 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C3",X"C8",X"B1",X"C3",X"67",X"32",X"FE",X"00",X"C3",X"24",X"31",X"00",X"C3",X"C7",X"17",X"00", + X"C3",X"1B",X"16",X"00",X"C3",X"2D",X"1A",X"00",X"C3",X"DF",X"19",X"00",X"C3",X"82",X"0F",X"00", + X"C3",X"A6",X"0E",X"00",X"C3",X"A3",X"32",X"00",X"C3",X"91",X"34",X"00",X"C3",X"8C",X"19",X"00", + X"C3",X"97",X"31",X"00",X"C3",X"C2",X"19",X"00",X"C3",X"45",X"0B",X"1A",X"BE",X"D8",X"C0",X"13", + X"23",X"1A",X"BE",X"D8",X"C0",X"13",X"23",X"1A",X"BE",X"C9",X"21",X"00",X"40",X"11",X"00",X"04", + X"06",X"0F",X"18",X"33",X"21",X"00",X"44",X"11",X"00",X"04",X"18",X"29",X"21",X"F0",X"4F",X"11", + X"40",X"50",X"06",X"40",X"3E",X"00",X"77",X"12",X"23",X"13",X"10",X"FA",X"C9",X"21",X"00",X"4C", + X"11",X"20",X"00",X"18",X"10",X"21",X"80",X"40",X"11",X"00",X"03",X"06",X"0F",X"18",X"08",X"21", + X"00",X"4C",X"11",X"D0",X"03",X"06",X"00",X"70",X"23",X"1B",X"7A",X"B3",X"20",X"F9",X"C9",X"DD", + X"21",X"21",X"4C",X"11",X"26",X"4C",X"DD",X"7E",X"00",X"A7",X"28",X"08",X"DD",X"35",X"00",X"20", + X"03",X"3E",X"01",X"12",X"DD",X"23",X"13",X"DD",X"7E",X"00",X"A7",X"28",X"11",X"DD",X"35",X"01", + X"20",X"0C",X"DD",X"36",X"01",X"3C",X"DD",X"35",X"00",X"20",X"03",X"3E",X"01",X"12",X"2A",X"24", + X"4C",X"13",X"7C",X"B5",X"C8",X"01",X"FF",X"FF",X"3F",X"ED",X"5A",X"20",X"06",X"3E",X"01",X"12", + X"21",X"00",X"00",X"22",X"24",X"4C",X"C9",X"DD",X"21",X"00",X"04",X"EB",X"DD",X"19",X"EB",X"23", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..f3b27c53 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"05",X"02",X"00",X"01",X"03",X"06",X"04",X"07",X"08",X"09",X"0B",X"0A",X"0C",X"0E",X"0D",X"08", + X"0B",X"0F",X"0A",X"10",X"3C",X"80",X"5C",X"81",X"A6",X"82",X"8C",X"83",X"B2",X"84",X"F6",X"85", + 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X"BF",X"AB",X"1D",X"F2",X"CB",X"BC",X"FC",X"BD",X"6D",X"03",X"FF",X"BF",X"93",X"FF",X"AF",X"FB", + X"A3",X"4F",X"C6",X"7D",X"DB",X"79",X"F5",X"7B",X"7D",X"EB",X"FD",X"EB",X"CD",X"A1",X"F1",X"0E", + X"D2",X"D5",X"AE",X"EB",X"FC",X"EE",X"8D",X"A9",X"FF",X"DF",X"1F",X"F4",X"E2",X"DD",X"36",X"F7", + X"7F",X"13",X"7D",X"AD",X"F6",X"0E",X"DF",X"CF",X"F7",X"64",X"C3",X"7B",X"F5",X"BE",X"EB",X"39", + X"AE",X"9F",X"FE",X"EB",X"FD",X"9B",X"56",X"85",X"EB",X"7F",X"59",X"1F",X"3E",X"62",X"C0",X"5F", + X"7B",X"ED",X"DF",X"F6",X"65",X"79",X"2B",X"FE",X"E7",X"CF",X"7F",X"ED",X"1D",X"FF",X"AF",X"57", + X"88",X"64",X"4B",X"22",X"C0",X"10",X"A4",X"10",X"19",X"22",X"7A",X"AE",X"0A",X"26",X"A0",X"B4", + X"18",X"4D",X"B8",X"81",X"29",X"88",X"31",X"70",X"A0",X"F6",X"00",X"14",X"10",X"F0",X"10",X"70", + X"86",X"80",X"12",X"3E",X"52",X"02",X"B6",X"C9",X"08",X"C0",X"A0",X"70",X"52",X"D8",X"00",X"20", + X"12",X"08",X"50",X"0D",X"02",X"20",X"8C",X"F3",X"28",X"80",X"90",X"80",X"90",X"16",X"78",X"92", + X"20",X"22",X"24",X"58",X"2A",X"4D",X"2D",X"85",X"10",X"30",X"01",X"39",X"00",X"00",X"09",X"33", + X"3F",X"99",X"B0",X"80",X"42",X"72",X"42",X"00",X"11",X"22",X"23",X"A1",X"04",X"08",X"92",X"A3", + X"B1",X"15",X"10",X"5A",X"A8",X"0A",X"40",X"92",X"A5",X"C4",X"92",X"1B",X"20",X"A0",X"00",X"30", + X"42",X"59",X"F2",X"1C",X"0C",X"D0",X"C6",X"CA",X"B0",X"AA",X"1A",X"19",X"5A",X"84",X"BF",X"3D", + X"7D",X"3F",X"EF",X"4D",X"9D",X"99",X"67",X"5B",X"67",X"EB",X"7D",X"D9",X"4D",X"FF",X"D5",X"3D", + X"9F",X"B4",X"9F",X"C7",X"1D",X"49",X"7D",X"B6",X"A7",X"3E",X"CF",X"AB",X"45",X"EF",X"DD",X"EF", + X"FF",X"7D",X"C7",X"BB",X"63",X"E7",X"F3",X"BF",X"6F",X"F6",X"EF",X"DF",X"DB",X"DB",X"A7",X"DF", + X"FB",X"BE",X"AD",X"4B",X"1B",X"5A",X"FF",X"DF",X"3F",X"E7",X"DF",X"87",X"BF",X"ED",X"FD",X"F7", + X"CF",X"D5",X"FF",X"EB",X"B3",X"F1",X"FF",X"83",X"E5",X"D9",X"DE",X"EC",X"EB",X"CD",X"FF",X"33", + X"D7",X"CD",X"79",X"B7",X"F7",X"DE",X"CE",X"EF",X"6B",X"A7",X"BD",X"FE",X"FF",X"E3",X"F6",X"9F", + X"B3",X"FC",X"6B",X"D3",X"79",X"F2",X"D9",X"CF",X"AB",X"8F",X"E7",X"BB",X"F9",X"EE",X"BF",X"B5", + X"E7",X"8A",X"B3",X"FB",X"3E",X"6F",X"6F",X"6C",X"56",X"EF",X"EB",X"CB",X"D3",X"81",X"F5",X"B1", + X"60",X"6B",X"4A",X"98",X"10",X"A8",X"E9",X"28",X"98",X"1D",X"98",X"A0",X"08",X"BC",X"1A",X"8D", + X"86",X"38",X"5D",X"01",X"60",X"A8",X"A2",X"16",X"02",X"64",X"00",X"00",X"A7",X"91",X"03",X"00", + X"70",X"3A",X"00",X"30",X"18",X"25",X"02",X"90",X"50",X"06",X"80",X"88",X"52",X"80",X"10",X"00", + X"E8",X"ED",X"A2",X"12",X"00",X"23",X"A4",X"0B",X"84",X"C4",X"80",X"60",X"20",X"82",X"20",X"0C", + X"88",X"CE",X"2B",X"3E",X"80",X"B7",X"01",X"44",X"10",X"22",X"90",X"03",X"23",X"88",X"11",X"03", + X"81",X"42",X"00",X"39",X"18",X"DA",X"5A",X"36",X"78",X"80",X"48",X"00",X"84",X"0E",X"20",X"00", + X"16",X"82",X"66",X"81",X"30",X"14",X"08",X"10",X"84",X"01",X"51",X"A8",X"09",X"04",X"B3",X"00", + X"4C",X"41",X"40",X"20",X"16",X"C0",X"5A",X"D0",X"02",X"92",X"02",X"19",X"48",X"02",X"80",X"0C", + X"F9",X"99",X"D5",X"79",X"F0",X"79",X"E8",X"B3",X"97",X"6B",X"39",X"FF",X"FF",X"F9",X"B9",X"3A", + X"F1",X"79",X"B3",X"A9",X"A0",X"E9",X"7A",X"B1",X"95",X"30",X"A9",X"9D",X"F9",X"30",X"FD",X"72", + X"5C",X"FC",X"B1",X"F2",X"B9",X"F9",X"59",X"C9",X"73",X"BB",X"3A",X"FA",X"DB",X"98",X"F2",X"D5", + X"51",X"E8",X"7D",X"FB",X"F9",X"5D",X"F9",X"FF",X"32",X"75",X"FE",X"71",X"B1",X"68",X"F4",X"B9", + X"FF",X"F9",X"FD",X"B9",X"B1",X"BA",X"59",X"B9",X"BE",X"E8",X"B8",X"F1",X"F7",X"B8",X"F1",X"49", + X"6D",X"F1",X"9E",X"35",X"E1",X"78",X"E0",X"F9",X"B9",X"F9",X"B0",X"BC",X"D4",X"61",X"63",X"59", + X"F0",X"87",X"D9",X"B9",X"58",X"72",X"D8",X"EB",X"8A",X"F1",X"35",X"33",X"B5",X"79",X"79",X"FD", + X"D0",X"6D",X"39",X"F9",X"FF",X"F9",X"54",X"F9",X"7B",X"F9",X"FB",X"E9",X"AD",X"F8",X"79",X"F0", + X"77",X"07",X"30",X"5D",X"8F",X"C7",X"A5",X"07",X"04",X"A7",X"8D",X"44",X"86",X"C6",X"A0",X"45", + X"18",X"07",X"D4",X"7F",X"1F",X"03",X"04",X"05",X"07",X"4E",X"66",X"05",X"6E",X"06",X"06",X"4E", + X"07",X"2E",X"47",X"46",X"06",X"26",X"06",X"46",X"76",X"06",X"02",X"01",X"97",X"D3",X"C6",X"87", + X"A2",X"87",X"00",X"2A",X"37",X"32",X"A4",X"87",X"66",X"76",X"41",X"1E",X"7E",X"63",X"14",X"89", + X"BE",X"06",X"0F",X"53",X"CA",X"8E",X"06",X"02",X"46",X"26",X"07",X"87",X"4F",X"44",X"04",X"0A", + X"96",X"EC",X"10",X"4E",X"0A",X"0C",X"A6",X"A6",X"0E",X"4F",X"C7",X"86",X"02",X"8E",X"06",X"AC", + X"D6",X"00",X"9B",X"23",X"45",X"2E",X"0C",X"67",X"07",X"22",X"83",X"43",X"62",X"C7",X"0C",X"0E", + X"87",X"06",X"14",X"66",X"BD",X"16",X"E7",X"0E",X"8F",X"06",X"64",X"0F",X"86",X"0F",X"06",X"86", + X"FF",X"D1",X"99",X"78",X"5D",X"69",X"F9",X"71",X"DB",X"71",X"3B",X"9B",X"ED",X"7D",X"F8",X"79", + X"9C",X"F9",X"DB",X"F6",X"EB",X"41",X"77",X"43",X"D9",X"59",X"FB",X"33",X"FF",X"F5",X"B9",X"39", + X"A8",X"C9",X"31",X"A3",X"5D",X"B4",X"71",X"69",X"78",X"7B",X"BE",X"FD",X"78",X"BD",X"73",X"39", + X"F4",X"F9",X"BC",X"B1",X"F9",X"64",X"22",X"3C",X"9B",X"5A",X"B9",X"74",X"5C",X"99",X"6B",X"F9", + X"7F",X"90",X"F9",X"78",X"F8",X"B9",X"3B",X"B1",X"39",X"F9",X"6F",X"F8",X"DE",X"FF",X"B1",X"D8", + X"A9",X"96",X"E8",X"DA",X"F5",X"7A",X"A4",X"39",X"B9",X"F9",X"DD",X"4B",X"DB",X"FA",X"D8",X"7B", + X"F5",X"C1",X"B9",X"FC",X"D8",X"79",X"9E",X"90",X"E9",X"50",X"34",X"99",X"A1",X"59",X"FD",X"69", + X"A1",X"FB",X"1B",X"B8",X"77",X"B9",X"14",X"1B",X"27",X"48",X"FF",X"08",X"F8",X"EB",X"B0",X"F8", + X"B9",X"66",X"03",X"46",X"0F",X"47",X"75",X"C6",X"47",X"02",X"07",X"02",X"0C",X"24",X"2F",X"02", + X"8C",X"43",X"82",X"D5",X"2A",X"0F",X"9C",X"02",X"28",X"0C",X"03",X"8D",X"36",X"04",X"23",X"86", + X"42",X"D2",X"A4",X"46",X"CF",X"8C",X"76",X"96",X"C7",X"05",X"86",X"80",X"5B",X"66",X"46",X"0E", + X"16",X"4C",X"4E",X"46",X"52",X"07",X"A7",X"C5",X"03",X"0F",X"44",X"A3",X"0E",X"46",X"46",X"64", + X"0E",X"27",X"26",X"0B",X"07",X"4E",X"82",X"C6",X"07",X"06",X"D6",X"46",X"4E",X"C2",X"A4",X"06", + X"07",X"47",X"17",X"87",X"58",X"15",X"57",X"07",X"44",X"97",X"0C",X"42",X"04",X"86",X"06",X"57", + X"03",X"44",X"06",X"46",X"D2",X"0E",X"0F",X"43",X"47",X"56",X"AC",X"4C",X"06",X"06",X"37",X"86", + X"06",X"56",X"B4",X"07",X"6E",X"28",X"54",X"07",X"C6",X"86",X"07",X"83",X"1E",X"88",X"46",X"AD"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/build_id.v new file mode 100644 index 00000000..43d5a87c --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171122" +`define BUILD_TIME "113935" diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..13e51d6c --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman.vhd @@ -0,0 +1,469 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- Copyright (c) Sorgelig - 2017 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN is + generic( + eight_sprites : boolean := true + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- sn1_l 0x5040 - 0x504F sound +-- sn2_l 0x5050 - 0x505F sound +-- spr_l 0x5060 - 0x506F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"4" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"5" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"6" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - bfff + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(11 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..91313469 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pll.v b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Ponpoko_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/README.txt b/Arcade/Pacman Hardware/SuperGlob_MiST/README.txt new file mode 100644 index 00000000..f62cb1ea --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Super Glob port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/Release/SuperGlob.rbf b/Arcade/Pacman Hardware/SuperGlob_MiST/Release/SuperGlob.rbf new file mode 100644 index 00000000..302f6ebd Binary files /dev/null and b/Arcade/Pacman Hardware/SuperGlob_MiST/Release/SuperGlob.rbf differ diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf b/Arcade/Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf new file mode 100644 index 00000000..c46ed6f6 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/SuperGlob.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "SuperGlob" diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf b/Arcade/Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf new file mode 100644 index 00000000..690feaad --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/SuperGlob.qsf @@ -0,0 +1,165 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:14:41 November 10, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# SuperGlob_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY SuperGlob +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------- +# start ENTITY(MrTNT) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(MrTNT) +# ----------------- + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM3_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/pacman_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperGlob.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/clean.bat b/Arcade/Pacman Hardware/SuperGlob_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..e6ac7fc9 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"37",X"37",X"7F",X"FF",X"EE",X"00",X"00",X"00",X"CE",X"CE",X"67",X"33",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F", + X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0", + X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF", + X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C", + X"00",X"00",X"EE",X"FF",X"7F",X"37",X"37",X"7F",X"00",X"00",X"00",X"33",X"67",X"CE",X"CE",X"EF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"0F", + 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X"77",X"44",X"FF",X"00",X"00",X"FF",X"77",X"00",X"EE",X"00",X"CC",X"00",X"00",X"EE",X"CC",X"00", + X"03",X"01",X"00",X"08",X"0F",X"0F",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"0C",X"0F",X"0F",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0F",X"07",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00", + X"07",X"0F",X"0C",X"08",X"08",X"0C",X"0E",X"0F",X"0E",X"0F",X"03",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"01",X"01",X"01",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"03", + X"00",X"00",X"00",X"00",X"00",X"0E",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F", + X"0F",X"00",X"00",X"00",X"01",X"03",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0C",X"00",X"00",X"00",X"00",X"00",X"0F",X"0E",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"0E",X"0C",X"00",X"08",X"0C",X"0F",X"00",X"08",X"0F",X"0F",X"00", + X"01",X"07",X"0F",X"00",X"00",X"0F",X"0F",X"00",X"0E",X"08",X"00",X"00",X"00",X"0F",X"0F",X"00", + X"00",X"0E",X"0F",X"0F",X"0E",X"0E",X"0C",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"0C",X"0F",X"0F",X"0C",X"0C",X"00",X"00",X"08",X"01",X"0F",X"0F",X"01",X"01",X"03",X"0F", + X"00",X"00",X"08",X"0C",X"0C",X"0C",X"08",X"08",X"01",X"07",X"0E",X"0C",X"08",X"08",X"0C",X"0F", + X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E",X"07",X"01",X"00",X"00",X"01",X"0F", + X"0C",X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"0F",X"00",X"00",X"07",X"0F",X"0C",X"00",X"00", + X"0F",X"00",X"00",X"0F",X"0F",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"0E",X"0F",X"03",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..84f8d265 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"08",X"08",X"08",X"08",X"08",X"0F",X"0F",X"08",X"08",X"00",X"00",X"00",X"08",X"08",X"08",X"08", + X"0F",X"0F",X"0F",X"08",X"00",X"00",X"08",X"08",X"08",X"08",X"0F",X"0F",X"08",X"08",X"00",X"00", + X"07",X"09",X"0A",X"0B",X"07",X"0D",X"0D",X"07",X"0E",X"07",X"0D",X"0D",X"07",X"0B",X"0A",X"09", + X"07",X"05",X"07",X"03",X"07",X"01",X"07",X"00",X"07",X"00",X"07",X"01",X"07",X"03",X"07",X"05", + X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"08",X"00",X"08",X"08",X"0F",X"0F",X"00",X"00",X"08",X"08",X"08",X"0F",X"0F",X"0F", + X"00",X"08",X"08",X"00",X"0F",X"0F",X"08",X"08",X"08",X"08",X"0F",X"08",X"00",X"00",X"00",X"08", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0E",X"0C",X"09",X"0C",X"0E",X"0A",X"07",X"0C",X"0F",X"0D",X"08",X"0A",X"0B",X"07",X"02", + X"08",X"0D",X"09",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"07",X"08",X"0A",X"0C",X"0E",X"0D",X"0C",X"0C",X"0B",X"0A",X"08",X"07",X"05",X"06",X"07",X"08", + X"08",X"09",X"0A",X"0B",X"09",X"08",X"06",X"05",X"04",X"04",X"03",X"02",X"04",X"06",X"08",X"09", + X"0A",X"0C",X"0C",X"0A",X"07",X"07",X"08",X"0B",X"0D",X"0E",X"0D",X"0A",X"06",X"05",X"05",X"07", + X"09",X"09",X"08",X"04",X"01",X"00",X"01",X"03",X"06",X"07",X"07",X"04",X"02",X"02",X"04",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..c996a6b9 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"07",X"0E",X"08",X"00",X"02",X"0E",X"0A",X"00",X"06",X"0C",X"0A", + X"00",X"0F",X"02",X"0D",X"00",X"01",X"09",X"0B",X"00",X"0F",X"01",X"07",X"00",X"05",X"02",X"0E", + X"00",X"07",X"0B",X"05",X"00",X"07",X"0F",X"04",X"00",X"07",X"0B",X"08",X"00",X"01",X"08",X"03", + X"00",X"0E",X"01",X"0F",X"00",X"05",X"07",X"01",X"00",X"05",X"07",X"02",X"00",X"05",X"03",X"02", + X"00",X"01",X"07",X"01",X"00",X"01",X"07",X"02",X"00",X"01",X"03",X"02",X"00",X"02",X"07",X"01", + X"00",X"02",X"07",X"02",X"00",X"02",X"03",X"02",X"00",X"0C",X"07",X"01",X"00",X"0C",X"07",X"02", + X"00",X"0C",X"03",X"02",X"00",X"04",X"07",X"01",X"00",X"04",X"07",X"02",X"00",X"04",X"03",X"02", + X"00",X"07",X"07",X"01",X"00",X"07",X"07",X"02",X"00",X"07",X"03",X"02",X"00",X"0F",X"02",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..48c2a533 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"47",X"38",X"C8",X"E8",X"3F",X"C6",X"FF",X"9F",X"29",X"DF",X"37",X"86",X"1F",X"27",X"1D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..95ab1e86 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"97",X"32",X"00",X"50",X"32",X"C0",X"50",X"DB",X"02",X"ED",X"56",X"31",X"F0",X"4F",X"06", + X"64",X"DB",X"03",X"CD",X"65",X"03",X"3A",X"00",X"3F",X"00",X"97",X"21",X"00",X"4C",X"01",X"04", + X"00",X"77",X"23",X"10",X"FC",X"32",X"C0",X"50",X"0D",X"20",X"F6",X"DB",X"04",X"DB",X"0A",X"CD", + X"ED",X"06",X"C3",X"07",X"02",X"07",X"37",X"00",X"F5",X"C5",X"D5",X"E5",X"3A",X"3B",X"4C",X"A7", + X"CA",X"32",X"01",X"DB",X"07",X"11",X"F2",X"4F",X"01",X"62",X"50",X"21",X"8C",X"4E",X"DB",X"08", + X"DB",X"0A",X"DB",X"0B",X"3E",X"06",X"00",X"F5",X"DB",X"14",X"DB",X"15",X"F1",X"F5",X"3A",X"A8", + X"4C",X"A7",X"28",X"26",X"3A",X"A9",X"4C",X"A7",X"28",X"20",X"7E",X"3D",X"CB",X"4E",X"20",X"02", + X"C6",X"04",X"12",X"13",X"23",X"7E",X"12",X"13",X"23",X"3E",X"E6",X"96",X"C6",X"26",X"02",X"03", + X"23",X"7E",X"D6",X"18",X"D6",X"F8",X"ED",X"44",X"18",X"0D",X"7E",X"12",X"13",X"23",X"7E",X"12", + X"13",X"23",X"7E",X"02",X"03",X"23",X"7E",X"02",X"03",X"23",X"F1",X"3D",X"20",X"BF",X"3A",X"A7", + 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd new file mode 100644 index 00000000..4d4bfda4 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"97",X"32",X"00",X"50",X"32",X"C0",X"50",X"DB",X"02",X"ED",X"56",X"31",X"F0",X"4F",X"06", + X"64",X"DB",X"03",X"CD",X"65",X"03",X"3A",X"00",X"3F",X"00",X"97",X"21",X"00",X"4C",X"01",X"04", + X"00",X"77",X"23",X"10",X"FC",X"32",X"C0",X"50",X"0D",X"20",X"F6",X"DB",X"04",X"DB",X"0A",X"CD", + X"ED",X"06",X"C3",X"07",X"02",X"07",X"37",X"00",X"F5",X"C5",X"D5",X"E5",X"3A",X"3B",X"4C",X"A7", + X"CA",X"32",X"01",X"DB",X"07",X"11",X"F2",X"4F",X"01",X"62",X"50",X"21",X"8C",X"4E",X"DB",X"08", + X"DB",X"0A",X"DB",X"0B",X"3E",X"06",X"00",X"F5",X"DB",X"14",X"DB",X"15",X"F1",X"F5",X"3A",X"A8", + X"4C",X"A7",X"28",X"26",X"3A",X"A9",X"4C",X"A7",X"28",X"20",X"7E",X"3D",X"CB",X"4E",X"20",X"02", + X"C6",X"04",X"12",X"13",X"23",X"7E",X"12",X"13",X"23",X"3E",X"E6",X"96",X"C6",X"26",X"02",X"03", + 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X"FF",X"FF",X"FF",X"05",X"80",X"06",X"85",X"05",X"80",X"05",X"88",X"05",X"80",X"12",X"85",X"05", + X"80",X"05",X"88",X"05",X"80",X"0C",X"84",X"0C",X"85",X"05",X"80",X"05",X"88",X"05",X"80",X"1E", + X"84",X"05",X"80",X"FF",X"FF",X"FF",X"05",X"80",X"0A",X"84",X"0A",X"87",X"14",X"84",X"0C",X"80", + X"37",X"85",X"32",X"84",X"0C",X"80",X"32",X"85",X"0A",X"87",X"05",X"84",X"05",X"80",X"FF",X"05", + X"80",X"05",X"84",X"05",X"80",X"05",X"88",X"05",X"80",X"0A",X"85",X"05",X"80",X"05",X"88",X"05", + X"80",X"0F",X"84",X"0A",X"87",X"0A",X"85",X"05",X"84",X"05",X"88",X"10",X"80",X"05",X"84",X"0A", + X"86",X"28",X"85",X"05",X"80",X"05",X"84",X"FF",X"05",X"80",X"04",X"85",X"05",X"88",X"1C",X"80", + X"04",X"85",X"28",X"87",X"0A",X"80",X"10",X"84",X"0C",X"84",X"0A",X"86",X"28",X"85",X"40",X"80", + X"FF",X"21",X"9E",X"43",X"11",X"5C",X"3E",X"CD",X"6B",X"04",X"3A",X"80",X"50",X"E6",X"1C",X"EE", + X"1C",X"0F",X"0F",X"C6",X"32",X"21",X"DE",X"41",X"CD",X"1A",X"04",X"C9",X"FF",X"0B",X"42",X"4F", + X"4E",X"55",X"53",X"20",X"47",X"4C",X"4F",X"42",X"20",X"41",X"54",X"20",X"30",X"30",X"30",X"30", + X"30",X"20",X"50",X"4F",X"49",X"4E",X"54",X"53",X"FF",X"FF",X"97",X"42",X"A7",X"3E",X"1E",X"F6", + X"09",X"00",X"3F",X"00",X"00",X"40",X"3F",X"3F",X"3F",X"80",X"3F",X"3F",X"3E",X"C0",X"3F",X"3F", + X"3D",X"80",X"3F",X"3F",X"3B",X"40",X"3F",X"3F",X"37",X"C0",X"3F",X"3F",X"2F",X"C0",X"3F",X"3F", + X"1F",X"40",X"3F",X"3F",X"00",X"3F",X"FF",X"4D",X"45",X"45",X"54",X"20",X"54",X"48",X"45",X"20", + X"47",X"4C",X"4F",X"42",X"FF",X"FF",X"4D",X"55",X"4E",X"43",X"48",X"20",X"41",X"4C",X"4C",X"20", + X"54",X"48",X"45",X"20",X"53",X"4E",X"41",X"43",X"4B",X"53",X"FF",X"FE",X"54",X"4F",X"20",X"43", + X"4C",X"45",X"41",X"52",X"20",X"54",X"48",X"45",X"20",X"4C",X"45",X"56",X"45",X"4C",X"FF",X"FF", + X"50",X"55",X"53",X"48",X"20",X"43",X"41",X"4C",X"4C",X"20",X"42",X"55",X"54",X"54",X"4F",X"4E", + X"FF",X"FE",X"54",X"4F",X"20",X"52",X"49",X"44",X"45",X"20",X"45",X"4C",X"45",X"56",X"41",X"54", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv new file mode 100644 index 00000000..17336abb --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/SuperGlob.sv @@ -0,0 +1,189 @@ +//============================================================================ +// Arcade: SuperGlob +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module SuperGlob +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Super Glob;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +pacman mrtnt +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + .in0_reg(~{2'b00, m_coin, 1'b0, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + .dipsw_reg(8'b1_1_0_100_00), + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/build_id.v new file mode 100644 index 00000000..6ea3a1fd --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171113" +`define BUILD_TIME "101935" diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/osd.v b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..70300d20 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman.vhd @@ -0,0 +1,629 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data_out : std_logic_vector(7 downto 0); + signal rom_data : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr0_l : std_logic; + signal wr1_l : std_logic; + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.PACMAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr0_l 0x5040 - 0x504F sound + -- wr1_l 0x5050 - 0x505F sound + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw_l <= dec(6); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr0_l <= decb(0); + wr1_l <= decb(1); + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + rom_data <= program_rom_dinl when cpu_addr(15) = '0' else program_rom_dinh; + rom_data_out <= rom_data(7 downto 6) & rom_data(3) & rom_data(4) & rom_data(5) & rom_data(2 downto 0) when MRTNT = '1' else rom_data; + + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw_l, cpu_vec_reg, sync_bus_reg, rom_data_out, + rams_data_out, in0_reg, in1_reg, dipsw_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data_out; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data_out; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw_l = '0') then cpu_data_in <= dipsw_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh + ); + + -- + -- video subsystem + -- + u_video : entity work.PACMAN_VIDEO + generic map ( + MRTNT => MRTNT + ) + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + u_audio : entity work.PACMAN_AUDIO + port map ( + I_HCNT => hcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_WR1_L => wr1_l, + I_WR0_L => wr0_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..39619ea0 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR1_L, + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => rom3m(1), + addr_a_i => addr(3 downto 0), + data_a_i => data, + + clk_b_i => CLK, + addr_b_i => addr(3 downto 0), + data_b_o => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..895304e9 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_video.vhd @@ -0,0 +1,366 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_VIDEO is +generic ( + MRTNT : std_logic := '0' -- 1 to descramble Mr TNT ROMs, 0 otherwise +); +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of PACMAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_dout : std_logic_vector(7 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + + -- descramble ROMs for Mr TNT (swap address lines A0 and A2) + if MRTNT = '1' then + ca(2) <= char_sum_reg(0) xor xflip; + ca(0) <= char_sum_reg(2) xor xflip; + else + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end if; + end process; + + + -- descramble ROMs for Mr TNT (swap data lines D4 and D6) + char_rom_5ef_dout <= char_rom_5ef_buf(7) & char_rom_5ef_buf(4) & char_rom_5ef_buf(5) & char_rom_5ef_buf(6) & char_rom_5ef_buf(3 downto 0) when MRTNT = '1' else char_rom_5ef_buf; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_dout(7 downto 4); -- load + shift_regl <= char_rom_5ef_dout(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd new file mode 100644 index 00000000..b26824c4 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pacman_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of PACMAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/SuperGlob_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/README.txt b/Arcade/Pacman Hardware/VanVanCar_MiST/README.txt new file mode 100644 index 00000000..be39499e --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/README.txt @@ -0,0 +1,27 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Van-Van Car for MiST by Gehstock +-- 16 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Van-Van Car hardware +-- Copyright (c) Sorgelig +-- Based on Pacman core: Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE,CTRL : Action +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + +ToDo: Fix Sound diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/Release/VanVanCar.rbf b/Arcade/Pacman Hardware/VanVanCar_MiST/Release/VanVanCar.rbf new file mode 100644 index 00000000..18c922cc Binary files /dev/null and b/Arcade/Pacman Hardware/VanVanCar_MiST/Release/VanVanCar.rbf differ diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf b/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf new file mode 100644 index 00000000..455ed812 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "VanVanCar" \ No newline at end of file diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf b/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf new file mode 100644 index 00000000..d1f11d06 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.qsf @@ -0,0 +1,137 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY VanVanCar +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd +set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd +set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd +set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_latch_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_clock_div.vhd +set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_attenuator.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/VanVanCar.sv +set_global_assignment -name VHDL_FILE rtl/vanvan_vram_addr.vhd +set_global_assignment -name VHDL_FILE rtl/vanvan_video.vhd +set_global_assignment -name VHDL_FILE rtl/vanvan.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.srf b/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/VanVanCar.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/clean.bat b/Arcade/Pacman Hardware/VanVanCar_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..cdd351ac --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + 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X"00",X"88",X"CC",X"CC",X"CC",X"88",X"00",X"00",X"33",X"33",X"77",X"77",X"76",X"32",X"31",X"11", + X"FF",X"FF",X"FF",X"F1",X"F0",X"F0",X"FF",X"DD",X"F9",X"F3",X"F1",X"F8",X"F1",X"F3",X"FF",X"CC"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..795f03b7 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"07",X"08",X"0F",X"00",X"07",X"08",X"04",X"00",X"07",X"08",X"01", + X"00",X"07",X"08",X"03",X"00",X"03",X"08",X"05",X"00",X"03",X"02",X"07",X"00",X"07",X"08",X"05", + X"00",X"07",X"0C",X"00",X"00",X"07",X"03",X"05",X"0D",X"00",X"00",X"07",X"0D",X"07",X"01",X"05", + X"0D",X"03",X"05",X"02",X"0D",X"08",X"09",X"06",X"0D",X"02",X"05",X"08",X"0D",X"01",X"04",X"03", + X"00",X"04",X"0A",X"05",X"00",X"01",X"03",X"00",X"00",X"05",X"08",X"00",X"00",X"03",X"02",X"00", + X"00",X"07",X"08",X"01",X"00",X"03",X"01",X"07",X"00",X"02",X"03",X"00",X"00",X"09",X"0E",X"02", + X"00",X"05",X"03",X"08",X"00",X"00",X"00",X"00",X"00",X"03",X"05",X"0F",X"00",X"03",X"0D",X"07", + X"00",X"01",X"0D",X"07",X"00",X"0F",X"0D",X"07",X"0D",X"01",X"03",X"0E",X"00",X"05",X"0D",X"07", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..28b22eff --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"C0",X"38",X"07",X"87",X"3F",X"F0",X"FF",X"27",X"14",X"1C",X"80",X"A4",X"01",X"AE",X"28"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..13f1535f --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"31",X"F0",X"4F",X"E7",X"C3",X"B4",X"01",X"FF",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF", + X"D5",X"07",X"5F",X"16",X"00",X"19",X"D1",X"C9",X"E1",X"18",X"33",X"FF",X"FF",X"FF",X"FF",X"FF", + X"AF",X"32",X"00",X"50",X"32",X"C0",X"50",X"C9",X"E7",X"3E",X"01",X"32",X"00",X"50",X"C9",X"FF", + X"18",X"1C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"CD",X"AA",X"01",X"0F",X"0F",X"0F",X"E6",X"1E", + X"5F",X"16",X"00",X"21",X"CB",X"01",X"19",X"5E",X"23",X"56",X"EB",X"F1",X"F5",X"E9",X"CB",X"27", + X"5F",X"16",X"00",X"19",X"5E",X"23",X"56",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"ED",X"73",X"1E",X"48",X"31",X"C0",X"4F",X"08",X"D9",X"E7", + X"DD",X"E5",X"FD",X"E5",X"CD",X"DD",X"01",X"FD",X"E1",X"DD",X"E1",X"0E",X"03",X"21",X"B0",X"4B", + X"06",X"08",X"11",X"06",X"00",X"7E",X"FE",X"01",X"23",X"20",X"1B",X"79",X"A6",X"23",X"28",X"03", + X"35",X"28",X"0C",X"19",X"10",X"EF",X"EF",X"D9",X"08",X"ED",X"7B",X"1E",X"48",X"ED",X"45",X"2B", + X"CB",X"FE",X"2B",X"36",X"03",X"23",X"23",X"18",X"EA",X"31",X"F0",X"4F",X"FB",X"0E",X"00",X"21", + X"B0",X"4B",X"06",X"08",X"11",X"08",X"00",X"7E",X"CB",X"7F",X"20",X"04",X"FE",X"02",X"30",X"06", + X"0C",X"19",X"10",X"F3",X"18",X"E7",X"F3",X"79",X"32",X"00",X"48",X"7E",X"36",X"02",X"23",X"CB", + X"BE",X"23",X"36",X"00",X"23",X"5E",X"23",X"56",X"23",X"4E",X"23",X"46",X"23",X"EB",X"FE",X"04", + X"20",X"04",X"50",X"59",X"FB",X"E9",X"F9",X"FE",X"02",X"28",X"04",X"1A",X"C1",X"18",X"01",X"F1", + X"C1",X"D1",X"E1",X"FD",X"E1",X"DD",X"E1",X"FB",X"C9",X"CD",X"9A",X"01",X"36",X"04",X"23",X"72", + X"23",X"72",X"23",X"71",X"23",X"70",X"18",X"E7",X"CD",X"9A",X"01",X"72",X"18",X"E1",X"CD",X"97", + X"01",X"7E",X"FE",X"02",X"C2",X"A9",X"00",X"23",X"7E",X"CB",X"7F",X"20",X"15",X"E6",X"40",X"4F", + X"F1",X"F5",X"E6",X"0F",X"B1",X"77",X"23",X"70",X"2B",X"2B",X"36",X"01",X"CD",X"89",X"01",X"C3", + X"A9",X"00",X"CB",X"BE",X"1E",X"06",X"19",X"7E",X"18",X"B2",X"CD",X"9A",X"01",X"CB",X"BE",X"7E", + X"B7",X"28",X"AC",X"FE",X"04",X"28",X"A8",X"1E",X"07",X"19",X"70",X"11",X"FA",X"FF",X"19",X"CB", + X"F6",X"CB",X"FE",X"FE",X"01",X"20",X"98",X"2B",X"36",X"03",X"18",X"93",X"CD",X"9A",X"01",X"7E", + X"B7",X"28",X"8C",X"CB",X"FE",X"18",X"88",X"CD",X"97",X"01",X"72",X"C3",X"A9",X"00",X"CD",X"9A", + X"01",X"1E",X"05",X"19",X"71",X"23",X"70",X"C3",X"EF",X"00",X"CD",X"97",X"01",X"23",X"CB",X"76", + X"CB",X"B6",X"1E",X"06",X"19",X"7E",X"C3",X"EC",X"00",X"01",X"03",X"00",X"09",X"EB",X"21",X"02", + X"00",X"39",X"EB",X"73",X"23",X"72",X"C9",X"3A",X"00",X"48",X"E6",X"0F",X"21",X"B0",X"4B",X"16", + X"00",X"5F",X"CB",X"23",X"CB",X"23",X"CB",X"23",X"19",X"C9",X"DD",X"E3",X"FD",X"E5",X"E5",X"D5", + X"C5",X"F5",X"DD",X"E9",X"21",X"00",X"48",X"01",X"00",X"18",X"36",X"00",X"23",X"0B",X"78",X"B1", + X"20",X"F8",X"3E",X"07",X"01",X"30",X"35",X"FF",X"C3",X"A9",X"00",X"F9",X"00",X"08",X"01",X"0E", + X"01",X"0E",X"01",X"3A",X"01",X"5C",X"01",X"67",X"01",X"6E",X"01",X"7A",X"01",X"3A",X"C0",X"50", + X"2F",X"32",X"20",X"48",X"21",X"80",X"50",X"36",X"01",X"36",X"00",X"21",X"03",X"48",X"3A",X"00", + X"50",X"2F",X"E6",X"A0",X"20",X"07",X"7E",X"B7",X"20",X"12",X"C3",X"80",X"02",X"36",X"06",X"FE", + X"80",X"CA",X"80",X"02",X"3E",X"01",X"32",X"07",X"50",X"C3",X"80",X"02",X"AF",X"32",X"07",X"50", + X"36",X"00",X"23",X"7E",X"3C",X"77",X"23",X"86",X"B7",X"28",X"36",X"CB",X"7F",X"20",X"32",X"47", + X"AF",X"32",X"04",X"48",X"23",X"7E",X"80",X"77",X"FE",X"64",X"30",X"1A",X"05",X"CB",X"20",X"48", + X"06",X"00",X"21",X"41",X"02",X"09",X"11",X"08",X"48",X"06",X"02",X"CD",X"54",X"3D",X"18",X"11", + X"00",X"01",X"00",X"02",X"00",X"03",X"3E",X"63",X"32",X"06",X"48",X"21",X"09",X"09",X"22",X"07", + X"48",X"21",X"02",X"48",X"CB",X"7E",X"20",X"1B",X"E5",X"21",X"49",X"42",X"DD",X"21",X"07",X"48", + X"1E",X"0B",X"06",X"02",X"0E",X"00",X"CD",X"8A",X"3D",X"3E",X"08",X"16",X"00",X"1E",X"00",X"CD", + X"20",X"2C",X"E1",X"2B",X"CB",X"7E",X"CB",X"FE",X"20",X"06",X"3E",X"07",X"01",X"35",X"35",X"FF", + X"21",X"88",X"4B",X"DD",X"21",X"F0",X"4F",X"FD",X"21",X"60",X"50",X"06",X"08",X"CB",X"7E",X"20", + X"4F",X"4E",X"0C",X"3A",X"21",X"48",X"57",X"CB",X"FE",X"23",X"7E",X"CB",X"42",X"28",X"09",X"EE", + X"C0",X"E6",X"C0",X"5F",X"3E",X"3F",X"A6",X"B3",X"07",X"07",X"DD",X"77",X"00",X"23",X"7E",X"CB", + X"42",X"28",X"04",X"ED",X"44",X"C6",X"10",X"D6",X"02",X"FD",X"77",X"00",X"23",X"7E",X"DD",X"77", + X"01",X"23",X"7E",X"CB",X"42",X"28",X"04",X"ED",X"44",X"C6",X"10",X"FD",X"77",X"01",X"23",X"DD", + X"23",X"DD",X"23",X"FD",X"23",X"FD",X"23",X"05",X"CA",X"5E",X"2D",X"0D",X"28",X"AF",X"18",X"B3", + X"11",X"05",X"00",X"19",X"DD",X"23",X"DD",X"23",X"FD",X"23",X"FD",X"23",X"10",X"9F",X"C3",X"5E", + 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00000000..ba7f34be --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"FD",X"6E",X"06",X"FD",X"66",X"07",X"29",X"F5",X"11",X"00",X"00",X"ED",X"5A",X"F1",X"FD",X"75", + X"06",X"FD",X"74",X"07",X"38",X"36",X"FD",X"7E",X"04",X"FE",X"07",X"D8",X"21",X"32",X"25",X"FD", + X"7E",X"11",X"B7",X"28",X"03",X"FD",X"35",X"11",X"FD",X"46",X"0A",X"FD",X"7E",X"09",X"FE",X"02", + X"20",X"04",X"78",X"EE",X"02",X"47",X"78",X"CD",X"E1",X"3D",X"D5",X"C1",X"FD",X"66",X"01",X"FD", + X"6E",X"03",X"CD",X"83",X"3D",X"FD",X"74",X"01",X"FD",X"75",X"03",X"C9",X"FD",X"7E",X"04",X"FE", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv new file mode 100644 index 00000000..e1ee9579 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/VanVanCar.sv @@ -0,0 +1,204 @@ +//============================================================================ +// Arcade: Van Van Car +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module VanVanCar +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Van Van Car;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +reg ce_4m; +always @(posedge clk_sys) begin + reg [2:0] div; + + div <= div + 1'd1; + if(div == 5) div <= 0; + ce_4m <= !div; +end + + + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [8:0] audio; +assign LED = 1; + +wire hblank, vblank; +wire ce_vid = ce_6m; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + + +video_mixer #(.LINE_LENGTH(492), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_vid), + .ce_pix_actual(ce_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + +vanvan vanvan +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0_reg(~{2'b00, m_coin, m_fire, m_down,m_right,m_left,m_up}), + .in1_reg(~{1'b0, m_start2, m_start1, 5'b00000}), + + .dipsw1_reg(8'b11_00_10_0_0), + .dipsw2_reg(8'b00000000), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m), + .ENA_4(ce_4m) +); + + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio[7:0]), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/build_id.v new file mode 100644 index 00000000..dfd21773 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "175540" diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/dac.vhd new file mode 100644 index 00000000..83d1861e --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 9 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/osd.v b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd new file mode 100644 index 00000000..3c952a1a --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/pll.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 9, + clk0_duty_cycle => 50, + clk0_multiply_by => 8, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..eba1d598 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING new file mode 100644 index 00000000..60549be5 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README new file mode 100644 index 00000000..33630144 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/README @@ -0,0 +1,143 @@ + +An SN76489AN Compatible Implementation in VHDL +============================================== +Version: $Date: 2006/06/18 19:28:40 $ + +Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +See the file COPYING. + + +Integration +----------- + +The sn76489 design exhibits all interface signals as the original chip. It +only differs in the audio data output which is provided as an 8 bit signed +vector instead of an analog output pin. + + generic ( + clock_div_16_g : integer := 1 + -- Set to '1' when operating the design in SN76489 mode. The primary clock + -- input is divided by 16 in this variant. The data sheet mentions the + -- SN76494 which contains a divide-by-2 clock input stage. Set the generic + -- to '0' to enable this mode. + ); + port ( + clock_i : in std_logic; + -- Primary clock input + -- Drive with the target frequency or any integer multiple of it. + + clock_en_i : in std_logic; + -- Clock enable + -- A '1' on this input qualifies a valid rising edge on clock_i. A '0' + -- disables the next rising clock edge, effectivley halting the design + -- until the next enabled rising clock edge. + -- Can be used to run the core at lower frequencies than applied on + -- clock_i. + + res_n_i : in std_logic; + -- Asynchronous low active reset input. + -- Sets all sequential elements to a known state. + + ce_n_i : in std_logic; + -- Chip enable, low active. + + we_n_i : in std_logic; + -- Write enable, low active. + + ready_o : out std_logic; + -- Ready indication to microprocessor. + + d_i : in std_logic_vector(0 to 7); + -- Data input + -- MSB 0 ... 7 LSB + + aout_o : out signed(0 to 7) + -- Audio output, signed vector + -- MSB/SIGN 0 ... 7 LSB + ); + + +Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the +MSB and bit 7 to be the LSB. This has been implemented according to TI's data +sheet, thus all register/data format figures apply 1:1 for this design. +Many systems will flip the system data bus bit wise before it is connected to +this PSG. This is simply achieved with the following VHDL construct: + + signal data_s : std_logic_vector(7 downto 0); + + ... + d_i => data_s, + ... + +d_i and data_s will be assigned from left to right, resulting in the expected +bit assignment: + + d_i data_s + 0 7 + 1 6 + ... + 6 1 + 7 0 + + +As this design is fully synchronous, care has to be taken when the design +replaces an SN76489 in asynchronous mode. No problems are expected when +interfacing the code to other synchronous components. + + +Design Hierarchy +---------------- + + sn76489_top + | + +-- sn76489_latch_ctrl + | + +-- sn76489_clock_div + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + +-- sn76489_tone + | | + | \-- sn76489_attentuator + | + \-- sn76489_noise + | + \-- sn76489_attentuator + +Resulting compilation sequence: + + sn76489_comp_pack-p.vhd + sn76489_top.vhd + sn76489_latch_ctrl.vhd + sn76489_latch_ctrl-c.vhd + sn76489_clock_div.vhd + sn76489_clock_div-c.vhd + sn76489_attenuator.vhd + sn76489_attenuator-c.vhd + sn76489_tone.vhd + sn76489_tone-c.vhd + sn76489_noise.vhd + sn76489_noise-c.vhd + sn76489_top-c.vhd + +Skip the files containing VHDL configurations when analyzing the code for +synthesis. + + +References +---------- + +* TI Data sheet SN76489.pdf + ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf + +* John Kortink's article on the SN76489: + http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ + +* Maxim's "SN76489 notes" in + http://www.smspower.org/maxim/docs/SN76489.txt diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd new file mode 100644 index 00000000..444064e5 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_attenuator.vhd @@ -0,0 +1,114 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $ +-- +-- Attenuator Module +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_attenuator is + + port ( + attenuation_i : in std_logic_vector(0 to 3); + factor_i : in signed(0 to 1); + product_o : out signed(0 to 7) + ); + +end sn76489_attenuator; + + +architecture rtl of sn76489_attenuator is + +begin + + ----------------------------------------------------------------------------- + -- Process attenuate + -- + -- Purpose: + -- Determine the attenuation and generate the resulting product. + -- + -- The maximum attenuation value is 31 which corresponds to volume off. + -- As described in the data sheet, the maximum "playing" attenuation is + -- 28 = 16 + 8 + 4 + -- + -- The table for the volume constants is derived from the following + -- formula (each step is 2dB voltage): + -- v(0) = 31 + -- v(n+1) = v(n) * 0.79432823 + -- + attenuate: process (attenuation_i, + factor_i) + + type volume_t is array (natural range 0 to 15) of natural; + constant volume_c : volume_t := + (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0); + + variable attenuation_v : unsigned(attenuation_i'range); + variable volume_v : signed(product_o'range); + + begin + + attenuation_v := unsigned(attenuation_i); + + -- volume look-up table + volume_v := to_signed(volume_c(to_integer(attenuation_v)), + product_o'length); + + -- this replaces a multiplier and consumes a bit fewer + -- resources + case to_integer(factor_i) is + when +1 => + product_o <= volume_v; + when -1 => + product_o <= -volume_v; + when others => + product_o <= (others => '0'); + end case; + + end process attenuate; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd new file mode 100644 index 00000000..eab86beb --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_clock_div.vhd @@ -0,0 +1,134 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $ +-- +-- Clock Divider Circuit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_clock_div is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + clk_en_o : out boolean + ); + +end sn76489_clock_div; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_clock_div is + + signal cnt_s, + cnt_q : unsigned(3 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential counter element. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + cnt_q <= (others => '0'); + elsif clock_i'event and clock_i = '1' then + cnt_q <= cnt_s; + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process comb + -- + -- Purpose: + -- Implements the combinational counter logic. + -- + comb: process (clock_en_i, + cnt_q) + begin + -- default assignments + cnt_s <= cnt_q; + clk_en_o <= false; + + if clock_en_i = '1' then + + if cnt_q = 0 then + clk_en_o <= true; + + if clock_div_16_g = 1 then + cnt_s <= to_unsigned(15, cnt_q'length); + elsif clock_div_16_g = 0 then + cnt_s <= to_unsigned( 1, cnt_q'length); + else + -- pragma translate_off + assert false + report "Generic clock_div_16_g must be either 0 or 1." + severity failure; + -- pragma translate_on + end if; + + else + cnt_s <= cnt_q - 1; + + end if; + + end if; + + end process comb; + -- + ----------------------------------------------------------------------------- + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd new file mode 100644 index 00000000..789720c2 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd @@ -0,0 +1,138 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Latch Control Unit +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity sn76489_latch_ctrl is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + d_i : in std_logic_vector(0 to 7); + ready_o : out std_logic; + tone1_we_o : out boolean; + tone2_we_o : out boolean; + tone3_we_o : out boolean; + noise_we_o : out boolean; + r2_o : out std_logic + ); + +end sn76489_latch_ctrl; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of sn76489_latch_ctrl is + + signal reg_q : std_logic_vector(0 to 2); + signal we_q : boolean; + signal ready_q : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements. + -- + seq: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + reg_q <= (others => '0'); + we_q <= false; + ready_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + -- READY Flag Output ---------------------------------------------------- + if ready_q = '0' and we_q then + if clk_en_i then + -- assert READY when write access happened + ready_q <= '1'; + end if; + elsif ce_n_i = '1' then + -- deassert READY when access has finished + ready_q <= '0'; + end if; + + -- Register Selection --------------------------------------------------- + if ce_n_i = '0' and we_n_i = '0' then + if clk_en_i then + if d_i(0) = '1' then + reg_q <= d_i(1 to 3); + end if; + we_q <= true; + end if; + else + we_q <= false; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + tone1_we_o <= reg_q(0 to 1) = "00" and we_q; + tone2_we_o <= reg_q(0 to 1) = "01" and we_q; + tone3_we_o <= reg_q(0 to 1) = "10" and we_q; + noise_we_o <= reg_q(0 to 1) = "11" and we_q; + + r2_o <= reg_q(2); + + ready_o <= ready_q + when ce_n_i = '0' else + '1'; + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd new file mode 100644 index 00000000..688bdd56 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_noise.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ +-- +-- Noise Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_noise is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + tone3_ff_i : in std_logic; + noise_o : out signed(0 to 7) + ); + +end sn76489_noise; + +architecture rtl of sn76489_noise is + + signal nf_q : std_logic_vector(0 to 1); + signal fb_q : std_logic; + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 6); + signal freq_ff_q : std_logic; + + signal shift_source_s, + shift_source_q : std_logic; + signal shift_rise_edge_s : boolean; + + signal lfsr_q : std_logic_vector(0 to 15); + + signal freq_s : signed(0 to 1); + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + nf_q <= (others => '0'); + fb_q <= '0'; + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to control register + -- both access types can write to the control register! + nf_q <= d_i(6 to 7); + fb_q <= d_i(5); + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- reload frequency counter according to NF setting + case nf_q is + when "00" => + freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length); + when "01" => + freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length); + when "10" => + freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length); + when others => + null; + end case; + + freq_ff_q <= not freq_ff_q; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Multiplex the source of the LFSR's shift enable + ----------------------------------------------------------------------------- + shift_source_s <= tone3_ff_i + when nf_q = "11" else + freq_ff_q; + + ----------------------------------------------------------------------------- + -- Process rise_edge + -- + -- Purpose: + -- Detect the rising edge of the selected LFSR shift source. + -- + rise_edge: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + shift_source_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + shift_source_q <= shift_source_s; + end if; + end if; + end process rise_edge; + -- + ----------------------------------------------------------------------------- + + -- detect rising edge on shift source + shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1'; + + + ----------------------------------------------------------------------------- + -- Process lfsr + -- + -- Purpose: + -- Implements the LFSR that generates noise. + -- Note: This implementation shifts the register right, i.e. from index + -- 15 towards 0 => bit 15 is the input, bit 0 is the output + -- + -- Tapped bits according to MAME's sn76496.c, implemented in function + -- lfsr_tapped_f. + -- + lfsr: process (clock_i, res_n_i) + + function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is + constant tapped_bits_c : std_logic_vector(0 to 15) + -- tapped bits are 0, 2, 15 + := "1010000000000001"; + variable parity_v : std_logic; + begin + parity_v := '0'; + + for idx in lfsr'low to lfsr'high loop + parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx)); + end loop; + + return parity_v; + end; + + begin + if res_n_i = '0' then + -- reset LFSR to "0000000000000001" + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if we_i and r2_i = '0' then + -- write to noise register + -- -> reset LFSR + lfsr_q <= (others => '0'); + lfsr_q(lfsr_q'right) <= '1'; + + elsif shift_rise_edge_s then + + -- shift LFSR left towards MSB + for idx in lfsr_q'right-1 downto lfsr_q'left loop + lfsr_q(idx) <= lfsr_q(idx+1); + end loop; + + -- determine input bit + if fb_q = '0' then + -- "Periodic" Noise + -- -> input to LFSR is output + lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left); + else + -- "White" Noise + -- -> input to LFSR is parity of tapped bits + lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q); + end if; + + end if; + + end if; + end if; + end process lfsr; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map output of LFSR to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when lfsr_q(0) = '1' else + to_signed( 0, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => noise_o + ); + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd new file mode 100644 index 00000000..3658efcc --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_tone.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $ +-- +-- Tone Generator +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sn76489_tone is + + port ( + clock_i : in std_logic; + clk_en_i : in boolean; + res_n_i : in std_logic; + we_i : in boolean; + d_i : in std_logic_vector(0 to 7); + r2_i : in std_logic; + ff_o : out std_logic; + tone_o : out signed(0 to 7) + ); + +end sn76489_tone; + +architecture rtl of sn76489_tone is + + signal f_q : std_logic_vector(0 to 9); + signal a_q : std_logic_vector(0 to 3); + signal freq_cnt_q : unsigned(0 to 9); + signal freq_ff_q : std_logic; + + signal freq_s : signed(0 to 1); + + function all_zero(a : in std_logic_vector) return boolean is + variable result_v : boolean; + begin + result_v := true; + + for idx in a'low to a'high loop + if a(idx) /= '0' then + result_v := false; + end if; + end loop; + + return result_v; + end; + +begin + + ----------------------------------------------------------------------------- + -- Process cpu_regs + -- + -- Purpose: + -- Implements the registers writable by the CPU. + -- + cpu_regs: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + f_q <= (others => '0'); + a_q <= (others => '1'); + + elsif clock_i'event and clock_i = '1' then + if clk_en_i and we_i then + if r2_i = '0' then + -- access to frequency register + if d_i(0) = '0' then + f_q(0 to 5) <= d_i(2 to 7); + else + f_q(6 to 9) <= d_i(4 to 7); + end if; + + else + -- access to attenuator register + -- both access types can write to the attenuator register! + a_q <= d_i(4 to 7); + + end if; + end if; + end if; + end process cpu_regs; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process freq_gen + -- + -- Purpose: + -- Implements the frequency generation components. + -- + freq_gen: process (clock_i, res_n_i) + begin + if res_n_i = '0' then + freq_cnt_q <= (others => '0'); + freq_ff_q <= '0'; + + elsif clock_i'event and clock_i = '1' then + if clk_en_i then + if freq_cnt_q = 0 then + -- update counter from frequency register + freq_cnt_q <= unsigned(f_q); + + -- and toggle the frequency flip-flop if enabled + if not all_zero(f_q) then + freq_ff_q <= not freq_ff_q; + else + -- if frequency setting is 0, then keep flip-flop at +1 + freq_ff_q <= '1'; + end if; + + else + -- decrement frequency counter + freq_cnt_q <= freq_cnt_q - 1; + + end if; + end if; + end if; + end process freq_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Map frequency flip-flop to signed value for attenuator. + ----------------------------------------------------------------------------- + freq_s <= to_signed(+1, 2) + when freq_ff_q = '1' else + to_signed(-1, 2); + + + ----------------------------------------------------------------------------- + -- The attenuator itself + ----------------------------------------------------------------------------- + attenuator_b : entity work.sn76489_attenuator + port map ( + attenuation_i => a_q, + factor_i => freq_s, + product_o => tone_o + ); + + + ----------------------------------------------------------------------------- + -- Output mapping + ----------------------------------------------------------------------------- + ff_o <= freq_ff_q; + +end rtl; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd new file mode 100644 index 00000000..c26d0e1a --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/sn76489/sn76489_top.vhd @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------- +-- +-- Synthesizable model of TI's SN76489AN. +-- +-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $ +-- +-- Chip Toplevel +-- +-- References: +-- +-- * TI Data sheet SN76489.pdf +-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf +-- +-- * John Kortink's article on the SN76489: +-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ +-- +-- * Maxim's "SN76489 notes" in +-- http://www.smspower.org/maxim/docs/SN76489.txt +-- +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library ieee; +use ieee.numeric_std.all; + +entity sn76489_top is + + generic ( + clock_div_16_g : integer := 1 + ); + port ( + clock_i : in std_logic; + clock_en_i : in std_logic; + res_n_i : in std_logic; + ce_n_i : in std_logic; + we_n_i : in std_logic; + ready_o : out std_logic; + d_i : in std_logic_vector(0 to 7); + aout_o : out signed(0 to 7) + ); + +end sn76489_top; + +architecture struct of sn76489_top is + + signal clk_en_s : boolean; + + signal tone1_we_s, + tone2_we_s, + tone3_we_s, + noise_we_s : boolean; + signal r2_s : std_logic; + + signal tone1_s, + tone2_s, + tone3_s, + noise_s : signed(0 to 7); + + signal tone3_ff_s : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock Divider + ----------------------------------------------------------------------------- + clock_div_b : entity work.sn76489_clock_div + generic map ( + clock_div_16_g => clock_div_16_g + ) + port map ( + clock_i => clock_i, + clock_en_i => clock_en_i, + res_n_i => res_n_i, + clk_en_o => clk_en_s + ); + + + ----------------------------------------------------------------------------- + -- Latch Control = CPU Interface + ----------------------------------------------------------------------------- + latch_ctrl_b : entity work.sn76489_latch_ctrl + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + ce_n_i => ce_n_i, + we_n_i => we_n_i, + d_i => d_i, + ready_o => ready_o, + tone1_we_o => tone1_we_s, + tone2_we_o => tone2_we_s, + tone3_we_o => tone3_we_s, + noise_we_o => noise_we_s, + r2_o => r2_s + ); + + + ----------------------------------------------------------------------------- + -- Tone Channel 1 + ----------------------------------------------------------------------------- + tone1_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone1_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone1_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 2 + ----------------------------------------------------------------------------- + tone2_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone2_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => open, + tone_o => tone2_s + ); + + ----------------------------------------------------------------------------- + -- Tone Channel 3 + ----------------------------------------------------------------------------- + tone3_b : entity work.sn76489_tone + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => tone3_we_s, + d_i => d_i, + r2_i => r2_s, + ff_o => tone3_ff_s, + tone_o => tone3_s + ); + + ----------------------------------------------------------------------------- + -- Noise Channel + ----------------------------------------------------------------------------- + noise_b : entity work.sn76489_noise + port map ( + clock_i => clock_i, + clk_en_i => clk_en_s, + res_n_i => res_n_i, + we_i => noise_we_s, + d_i => d_i, + r2_i => r2_s, + tone3_ff_i => tone3_ff_s, + noise_o => noise_s + ); + + + aout_o <= tone1_s + tone2_s + tone3_s + noise_s; + +end struct; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd new file mode 100644 index 00000000..ba50a44a --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan.vhd @@ -0,0 +1,674 @@ +-- +-- A simulation model of Van-Van Car hardware +-- Copyright (c) Sorgelig - 2017 +-- +-- Based on Pacman core +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + + +entity VANVAN is + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out signed(8 downto 0); + -- + in0_reg : in std_logic_vector(7 downto 0); + in1_reg : in std_logic_vector(7 downto 0); + dipsw1_reg : in std_logic_vector(7 downto 0); + dipsw2_reg : in std_logic_vector(7 downto 0); + + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic; + ENA_4 : in std_logic + ); +end; + +architecture RTL of VANVAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_ena : std_logic; + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic := '1'; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal rom_data : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal vram_addr_ab : std_logic_vector(11 downto 0); + signal ab : std_logic_vector(11 downto 0); + + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal vram_l : std_logic; + signal rams_data_out : std_logic_vector(7 downto 0); + -- more decode + signal wr2_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn1_ce : std_logic; + signal sn2_ce : std_logic; + signal sn1_ready : std_logic; + signal sn2_ready : std_logic; + signal sn_d : std_logic_vector(7 downto 0); + signal old_we : std_logic; + signal wav1,wav2 : signed(7 downto 0); + +begin + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + end process; + + p_sync : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + + if (hcnt = "010010111") then -- 097 + O_HBLANK <= '1'; + elsif (hcnt = "010001111") then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") then + hblank <= '0'; -- 0EF + O_HBLANK <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + -- + -- cpu + -- + p_cpu_wait_comb : process(sync_bus_wreq_l) + begin + cpu_wait_l <= '1'; + if (sync_bus_wreq_l = '0') then + cpu_wait_l <= '0'; + end if; + end process; + + p_irq_req_watchdog : process + variable rising_vblank : boolean; + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + --rising_vblank := do_hsync; -- debug + -- interrupt 8c + + if (control_reg(0) = '0') then + cpu_nmi_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_nmi_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + + -- simulation + -- pragma translate_off + -- synopsys translate_off + watchdog_reset_l <= not reset; -- watchdog disable + -- synopsys translate_on + -- pragma translate_on + end if; + end process; + + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_int_l <= '1'; + + p_cpu_ena : process(hcnt, ena_6) + begin + cpu_ena <= '0'; + if (ena_6 = '1') then + cpu_ena <= hcnt(0); + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr) + begin + -- rom 0x0000 - 0x3FFF + -- syncbus 0x4000 - 0x7FFF + + -- 7M + -- 7N + sync_bus_cs_l <= '1'; +-- program_rom_cs_l <= '1'; + + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + +-- if (cpu_addr(14) = '0') and (cpu_rd_l = '0') then +-- program_rom_cs_l <= '0'; +-- end if; + + if (cpu_addr(14) = '1') then + sync_bus_cs_l <= '0'; + end if; + + end if; + end process; + -- + -- sync bus custom ic + -- + p_sync_bus_reg : process + begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; + end process; + + p_sync_bus_comb : process(cpu_rd_l, sync_bus_cs_l, hcnt) + begin + -- sync_bus_stb is now an active low clock enable signal + sync_bus_stb <= '1'; + sync_bus_r_w_l <= '1'; + + if (sync_bus_cs_l = '0') and (hcnt(1) = '0') then + if (cpu_rd_l = '1') then + sync_bus_r_w_l <= '0'; + end if; + sync_bus_stb <= '0'; + end if; + + sync_bus_wreq_l <= '1'; + if (sync_bus_cs_l = '0') and (hcnt(1) = '1') and (cpu_rd_l = '0') then + sync_bus_wreq_l <= '0'; + end if; + end process; + -- + -- vram addr custom ic + -- + u_vram_addr : entity work.VANVAN_VRAM_ADDR + port map ( + AB => vram_addr_ab, + H256_L => hcnt(8), + H128 => hcnt(7), + H64 => hcnt(6), + H32 => hcnt(5), + H16 => hcnt(4), + H8 => hcnt(3), + H4 => hcnt(2), + H2 => hcnt(1), + H1 => hcnt(0), + V128 => vcnt(7), + V64 => vcnt(6), + V32 => vcnt(5), + V16 => vcnt(4), + V8 => vcnt(3), + V4 => vcnt(2), + V2 => vcnt(1), + V1 => vcnt(0), + FLIP => control_reg(3) + ); + + p_ab_mux_comb : process(hcnt, cpu_addr, vram_addr_ab) + begin + --When 2H is low, the CPU controls the bus. + if (hcnt(1) = '0') then + ab <= cpu_addr(11 downto 0); + else + ab <= vram_addr_ab; + end if; + end process; + + p_vram_comb : process(hcnt, cpu_addr, sync_bus_stb) + variable a,b : std_logic; + begin + + a := not (cpu_addr(12) or sync_bus_stb); + b := hcnt(1) and hcnt(0); + vram_l <= not (a or b); + end process; + + p_io_decode_comb : process(sync_bus_r_w_l, sync_bus_stb, ab, cpu_addr) + variable sel : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + variable selb : std_logic_vector(1 downto 0); + variable decb : std_logic_vector(3 downto 0); + begin + -- WRITE + + -- out_l 0x5000 - 0x503F control space + + -- wr2_l 0x5060 - 0x506F sprite + + -- 0x5080 - 0x50BF unused + + -- wdr_l 0x50C0 - 0x50FF watchdog reset + + -- READ + + -- in0_l 0x5000 - 0x503F in port 0 + -- in1_l 0x5040 - 0x507F in port 1 + -- dipsw_l 0x5080 - 0x50BF dip switches + + -- 7J + dec := "11111111"; + sel := sync_bus_r_w_l & ab(7) & ab(6); + if (cpu_addr(12) = '1') and ( sync_bus_stb = '0') then + case sel is + when "000" => dec := "11111110"; + when "001" => dec := "11111101"; + when "010" => dec := "11111011"; + when "011" => dec := "11110111"; + when "100" => dec := "11101111"; + when "101" => dec := "11011111"; + when "110" => dec := "10111111"; + when "111" => dec := "01111111"; + when others => null; + end case; + end if; + iodec_out_l <= dec(0); + iodec_wdr_l <= dec(3); + + iodec_in0_l <= dec(4); + iodec_in1_l <= dec(5); + iodec_dipsw1_l<= dec(6); + iodec_dipsw2_l<= dec(7); + + -- 7M + decb := "1111"; + selb := ab(5) & ab(4); + if (dec(1) = '0') then + case selb is + when "00" => decb := "1110"; + when "01" => decb := "1101"; + when "10" => decb := "1011"; + when "11" => decb := "0111"; + when others => null; + end case; + end if; + wr2_l <= decb(2); + end process; + + p_control_reg : process + variable ena : std_logic_vector(7 downto 0); + begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + ena := "00000000"; + if (iodec_out_l = '0') then + case ab(2 downto 0) is + when "000" => ena := "00000001"; + when "001" => ena := "00000010"; + when "010" => ena := "00000100"; + when "011" => ena := "00001000"; + when "100" => ena := "00010000"; + when "101" => ena := "00100000"; + when "110" => ena := "01000000"; + when "111" => ena := "10000000"; + when others => null; + end case; + end if; + + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (ena(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_db_mux_comb : process(hcnt, cpu_data_out, rams_data_out) + begin + -- simplified data source for video subsystem + -- only cpu or ram are sources of interest + if (hcnt(1) = '0') then + sync_bus_db <= cpu_data_out; + else + sync_bus_db <= rams_data_out; + end if; + end process; + + rom_data <= program_rom_dinl when cpu_addr(15) = '0' else program_rom_dinh; + p_cpu_data_in_mux_comb : process(cpu_addr, cpu_iorq_l, cpu_m1_l, sync_bus_wreq_l, + iodec_in0_l, iodec_in1_l, iodec_dipsw1_l, iodec_dipsw2_l, cpu_vec_reg, sync_bus_reg, rom_data, + rams_data_out, in0_reg, in1_reg, dipsw1_reg, dipsw2_reg) + begin + -- simplifed again + if (cpu_iorq_l = '0') and (cpu_m1_l = '0') then + cpu_data_in <= cpu_vec_reg; + elsif (sync_bus_wreq_l = '0') then + cpu_data_in <= sync_bus_reg; + else + if (cpu_addr(15 downto 14) = "00") then -- ROM at 0000 - 3fff + cpu_data_in <= rom_data; + elsif (cpu_addr(15 downto 13) = "100") then -- ROM at 8000 - 9fff + cpu_data_in <= rom_data; + else + cpu_data_in <= rams_data_out; + if (iodec_in0_l = '0') then cpu_data_in <= in0_reg; end if; + if (iodec_in1_l = '0') then cpu_data_in <= in1_reg; end if; + if (iodec_dipsw1_l = '0') then cpu_data_in <= dipsw1_reg; end if; + if (iodec_dipsw2_l = '0') then cpu_data_in <= dipsw2_reg; end if; + end if; + end if; + end process; + + u_rams : work.dpram generic map (12,8) + port map + ( + clk_a_i => clk, + en_a_i => ena_6, + we_i => not sync_bus_r_w_l and not vram_l, + addr_a_i => ab(11 downto 0), + data_a_i => cpu_data_out, -- cpu only source of ram data + + clk_b_i => clk, + addr_b_i => ab(11 downto 0), + data_b_o => rams_data_out + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom : entity work.ROM_PGM_0 + port map ( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl + ); + + -- example of internal program rom, if you have a big enough device + u_program_rom1 : entity work.ROM_PGM_1 + port map ( + CLK => clk, + ADDR => cpu_addr(11 downto 0), + DATA => program_rom_dinh + ); + + -- + -- video subsystem + -- + u_video : entity work.VANVAN_VIDEO + port map ( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + I_AB => ab, + I_DB => sync_bus_db, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + I_WR2_L => wr2_l, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk + ); + + O_HSYNC <= hSync; + O_VSYNC <= vSync; + + --O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- + -- audio subsystem + -- + process(clk, reset) begin + if reset = '1' then + sn1_ce <= '1'; + sn2_ce <= '1'; + elsif rising_edge(clk) then + + if sn1_ready = '1' then + sn1_ce <= '1'; + end if; + + if sn2_ready = '1' then + sn2_ce <= '1'; + end if; + + old_we <= cpu_wr_l; + if old_we = '1' and cpu_wr_l = '0' and cpu_iorq_l = '0' then + if cpu_addr(7 downto 0) = X"01" then + sn1_ce <= '0'; + sn_d <= cpu_data_out; + end if; + if cpu_addr(7 downto 0) = X"02" then + sn2_ce <= '0'; + sn_d <= cpu_data_out; + end if; + end if; + end if; + end process; + + sn1 : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk, + clock_en_i => ena_4, + res_n_i => not RESET, + ce_n_i => sn1_ce, + we_n_i => sn1_ce, + ready_o => sn1_ready, + d_i => sn_d, + aout_o => wav1 + ); + + sn2 : entity work.sn76489_top + generic map ( + clock_div_16_g => 1 + ) + port map ( + clock_i => clk, + clock_en_i => ena_4, + res_n_i => not RESET, + ce_n_i => sn2_ce, + we_n_i => sn2_ce, + ready_o => sn2_ready, + d_i => sn_d, + aout_o => wav2 + ); + + O_AUDIO <= resize(wav1, 9) + resize(wav2, 9); + +end RTL; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd new file mode 100644 index 00000000..0090d174 --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_video.vhd @@ -0,0 +1,349 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity VANVAN_VIDEO is +port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + I_WR2_L : in std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic +); +end; + +architecture RTL of VANVAN_VIDEO is + + signal sprite_xy_ram_temp : std_logic_vector(7 downto 0); + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal db_reg : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal cntr_ld : std_logic; + signal sprite_ram_ip : std_logic_vector(3 downto 0); + signal sprite_ram_op : std_logic_vector(3 downto 0); + signal ra : std_logic_vector(7 downto 0); + signal ra_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(3 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + + -- ram enable is low when HBLANK_L is 0 (for sprite access) or + -- 2H is low (for cpu writes) + -- we can simplify this + dr <= not sprite_xy_ram_temp when I_HBLANK = '1' else "11111111"; -- pull ups on board + + sprite_xy_ram : work.dpram generic map (4,8) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => not I_WR2_L, + addr_a_i => I_AB(3 downto 0), + data_a_i => I_DB, + + clk_b_i => CLK, + addr_b_i => I_AB(3 downto 0), + data_b_o => sprite_xy_ram_temp + ); + + p_char_regs : process + variable inc : std_logic; + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; + begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + inc := (not I_HBLANK); + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & inc); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + db_reg <= I_DB; -- character reg + end if; + end process; + + p_flip_comb : process(char_hblank_reg, I_FLIP, db_reg) + begin + if (char_hblank_reg = '0') then + xflip <= I_FLIP; + yflip <= I_FLIP; + else + xflip <= db_reg(1); + yflip <= db_reg(0); + end if; + end process; + + p_char_addr_comb : process(db_reg, I_HCNT, + char_match_reg, char_sum_reg, char_hblank_reg, + xflip, yflip) + begin + obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + + ca(12) <= char_hblank_reg; + ca(11 downto 6) <= db_reg(7 downto 2); + + -- 2h, 4e + if (char_hblank_reg = '0') then + ca(5) <= db_reg(1); + ca(4) <= db_reg(0); + else + ca(5) <= char_sum_reg(3) xor xflip; + ca(4) <= I_HCNT(3); + end if; + + ca(3) <= I_HCNT(2) xor yflip; + ca(1) <= char_sum_reg(1) xor xflip; + ca(2) <= char_sum_reg(2) xor xflip; + ca(0) <= char_sum_reg(0) xor xflip; + end process; + + -- char roms + char_rom_5ef : entity work.GFX1 + port map ( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf + ); + + p_char_shift : process + begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; + end process; + + p_char_shift_comb : process(I_HCNT, vout_yflip, shift_regu, shift_regl) + variable ip : std_logic; + begin + ip := I_HCNT(0) and I_HCNT(1); + if (vout_yflip = '0') then + + shift_sel(0) <= ip; + shift_sel(1) <= '1'; + shift_op(0) <= shift_regl(3); + shift_op(1) <= shift_regu(3); + else + + shift_sel(0) <= '1'; + shift_sel(1) <= ip; + shift_op(0) <= shift_regl(0); + shift_op(1) <= shift_regu(0); + end if; + end process; + + p_video_out_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= I_DB(4 downto 0); -- colour reg + end if; + end if; + end process; + + col_rom_4a : entity work.PROM4_DST + port map ( + CLK => CLK, + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a + ); + + cntr_ld <= '1' when (I_HCNT(3 downto 0) = "0111") and (vout_hblank='1' or vout_obj_on='0') else '0'; + + p_ra_cnt : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (cntr_ld = '1') then + ra <= dr; + else + ra <= ra + "1"; + end if; + end if; + end process; + + u_sprite_ram : work.dpram generic map (8,4) + port map + ( + clk_a_i => CLK, + en_a_i => ENA_6, + we_i => vout_obj_on_t1, + addr_a_i => ra_t1, + data_a_i => sprite_ram_ip, + + clk_b_i => CLK, + addr_b_i => ra, + data_b_o => sprite_ram_op + ); + + sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "0000"; + video_op_sel <= '1' when not (sprite_ram_reg = "0000") else '0'; + + p_sprite_ram_ip_reg : process + begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + ra_t1 <= ra; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + end if; + end process; + + p_sprite_ram_ip_comb : process(vout_hblank_t1, video_op_sel, sprite_ram_reg, lut_4a_t1) + begin + -- 3a + if (vout_hblank_t1 = '0') then + sprite_ram_ip <= (others => '0'); + else + if (video_op_sel = '1') then + sprite_ram_ip <= sprite_ram_reg; + else + sprite_ram_ip <= lut_4a_t1(3 downto 0); + end if; + end if; + end process; + + p_video_op_comb : process(vout_hblank, I_VBLANK, video_op_sel, sprite_ram_reg, lut_4a) + begin + -- 3b + if (vout_hblank = '1') or (I_VBLANK = '1') then + final_col <= (others => '0'); + else + if (video_op_sel = '1') then + final_col <= sprite_ram_reg; -- sprite + else + final_col <= lut_4a(3 downto 0); + end if; + end if; + end process; + + -- assign video outputs from color LUT PROM + col_rom_7f : entity work.PROM7_DST + port map ( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE + ); + +end architecture; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd new file mode 100644 index 00000000..f99d8aee --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/vanvan_vram_addr.vhd @@ -0,0 +1,273 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ & CarlW - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity X74_157 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end; + +architecture RTL of X74_157 is +begin + p_y_comb : process(S,G,A,B) + begin + for i in 0 to 3 loop + -- quad 2 line to 1 line mux (true logic) + if (G = '1') then + Y(i) <= '0'; + else + if (S = '0') then + Y(i) <= A(i); + else + Y(i) <= B(i); + end if; + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity X74_257 is + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end; + +architecture RTL of X74_257 is +signal ab : std_logic_vector (3 downto 0); +begin + + Y <= ab; -- no tristate + p_ab : process(S,A,B) + begin + for i in 0 to 3 loop + if (S = '0') then + AB(i) <= A(i); + else + AB(i) <= B(i); + end if; + end loop; + end process; +end RTL; + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity VANVAN_VRAM_ADDR is + port ( + AB : out std_logic_vector (11 downto 0); + H256_L : in std_logic; + H128 : in std_logic; + H64 : in std_logic; + H32 : in std_logic; + H16 : in std_logic; + H8 : in std_logic; + H4 : in std_logic; + H2 : in std_logic; + H1 : in std_logic; + V128 : in std_logic; + V64 : in std_logic; + V32 : in std_logic; + V16 : in std_logic; + V8 : in std_logic; + V4 : in std_logic; + V2 : in std_logic; + V1 : in std_logic; + FLIP : in std_logic + ); +end; + +architecture RTL of VANVAN_VRAM_ADDR is + +signal v128p : std_logic; +signal v64p : std_logic; +signal v32p : std_logic; +signal v16p : std_logic; +signal v8p : std_logic; +signal h128p : std_logic; +signal h64p : std_logic; +signal h32p : std_logic; +signal h16p : std_logic; +signal h8p : std_logic; +signal sel : std_logic; +signal y157 : std_logic_vector (11 downto 0); + +component X74_157 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + G : in std_logic; + S : in std_logic + ); +end component; + +component X74_257 + port ( + Y : out std_logic_vector (3 downto 0); + B : in std_logic_vector (3 downto 0); + A : in std_logic_vector (3 downto 0); + S : in std_logic + ); +end component; + +begin + p_vp_comb : process(FLIP, V8, V16, V32, V64, V128) + begin + v128p <= FLIP xor V128; + v64p <= FLIP xor V64; + v32p <= FLIP xor V32; + v16p <= FLIP xor V16; + v8p <= FLIP xor V8; + end process; + + p_hp_comb : process(FLIP, H8, H16, H32, H64, H128) + begin + H128P <= FLIP xor H128; + H64P <= FLIP xor H64; + H32P <= FLIP xor H32; + H16P <= FLIP xor H16; + H8P <= FLIP xor H8; + end process; + + p_sel : process(H16, H32, H64) + begin + sel <= not((H32 xor H16) or (H32 xor H64)); + end process; + + --p_oe257 : process(H2) + --begin + -- oe <= not(H2); + --end process; + + U6 : X74_157 + port map( + Y => y157(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => h64p, + B(0) => h64p, + A => "1111", + G => '0', + S => sel + ); + + U5 : X74_157 + port map( + Y => y157(7 downto 4), + B(3) => h64p, + B(2) => h64p, + B(1) => h8p, + B(0) => v128p, + A => "1111", + G => '0', + S => sel + ); + + U4 : X74_157 + port map( + Y => y157(3 downto 0), + B(3) => v64p, + B(2) => v32p, + B(1) => v16p, + B(0) => v8p, + A(3) => H64, + A(2) => H32, + A(1) => H16, + A(0) => H4, + G => '0', + S => sel + ); + + U3 : X74_257 + port map( + Y => AB(11 downto 8), + B(3) => '0', + B(2) => H4, + B(1) => v128p, + B(0) => v64p, + A => y157(11 downto 8), + S => H256_L + ); + + U2 : X74_257 + port map( + Y => AB(7 downto 4), + B(3) => v32p, + B(2) => v16p, + B(1) => v8p, + B(0) => h128p, + A => y157(7 downto 4), + S => H256_L + ); + + U1 : X74_257 + port map( + Y => AB(3 downto 0), + B(3) => h64p, + B(2) => h32p, + B(1) => h16p, + B(0) => h8p, + A => y157(3 downto 0), + S => H256_L + ); + +end RTL; diff --git a/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/VanVanCar_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/README.txt b/Arcade/Pacman Hardware/Woodpecker_MiST/README.txt new file mode 100644 index 00000000..2b2f11e6 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/README.txt @@ -0,0 +1,25 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Woodpecker for MiST by Gehstock +-- 21 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F1 : Start 1 player +-- F2 : Start 2 players +-- TAB : Skip the level +-- SPACE,CTRL : Fire +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/Release/Woodpecker.rbf b/Arcade/Pacman Hardware/Woodpecker_MiST/Release/Woodpecker.rbf new file mode 100644 index 00000000..3035a305 Binary files /dev/null and b/Arcade/Pacman Hardware/Woodpecker_MiST/Release/Woodpecker.rbf differ diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf b/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf new file mode 100644 index 00000000..18a22124 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Woodpecker" diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf b/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf new file mode 100644 index 00000000..5d0c79ee --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:43:12 November 20, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Woodpecker_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/GFX1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM7_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM4_DST.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/PROM1_DST.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_video.vhd +set_global_assignment -name VHDL_FILE rtl/pacman_audio.vhd +set_global_assignment -name VHDL_FILE rtl/pacman.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Woodpecker.sv + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Woodpecker +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(Alibaba) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Alibaba) +# ------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.srf b/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/Woodpecker.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/clean.bat b/Arcade/Pacman Hardware/Woodpecker_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd new file mode 100644 index 00000000..0a2b6466 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/GFX1.vhd @@ -0,0 +1,534 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity GFX1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(12 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of GFX1 is + type rom is array(0 to 8191) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"8C",X"4C",X"22",X"EE",X"4C",X"88",X"00",X"00",X"11",X"46",X"26",X"33",X"4C",X"9D",X"01", + X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"08",X"08",X"08",X"08",X"08",X"08",X"08",X"08", + X"01",X"01",X"01",X"01",X"01",X"01",X"E1",X"E1",X"08",X"08",X"08",X"08",X"08",X"08",X"78",X"78", + X"01",X"01",X"01",X"01",X"E1",X"E1",X"E1",X"E1",X"08",X"08",X"08",X"08",X"78",X"78",X"78",X"78", + X"01",X"01",X"E1",X"E1",X"E1",X"E1",X"E1",X"E1",X"08",X"08",X"78",X"78",X"78",X"78",X"78",X"78", + X"E1",X"E1",X"E1",X"E1",X"E1",X"E1",X"E1",X"E1",X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"78", + X"E1",X"E1",X"01",X"01",X"01",X"01",X"01",X"01",X"78",X"78",X"08",X"08",X"08",X"08",X"08",X"08", + X"E1",X"E1",X"E1",X"E1",X"01",X"01",X"01",X"01",X"78",X"78",X"78",X"78",X"08",X"08",X"08",X"08", + X"E1",X"E1",X"E1",X"E1",X"E1",X"E1",X"01",X"01",X"78",X"78",X"78",X"78",X"78",X"78",X"08",X"08", + X"CC",X"EE",X"BB",X"99",X"99",X"99",X"00",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"33",X"00", + X"FF",X"FF",X"44",X"44",X"44",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"66",X"33",X"11",X"00", + X"66",X"FF",X"99",X"99",X"99",X"FF",X"FF",X"00",X"33",X"77",X"44",X"44",X"44",X"77",X"77",X"00", + X"22",X"33",X"11",X"11",X"33",X"EE",X"CC",X"00",X"22",X"66",X"44",X"44",X"66",X"33",X"11",X"00", + X"CC",X"EE",X"33",X"11",X"11",X"FF",X"FF",X"00",X"11",X"33",X"66",X"44",X"44",X"77",X"77",X"00", + X"11",X"99",X"99",X"99",X"FF",X"FF",X"00",X"00",X"44",X"44",X"44",X"44",X"77",X"77",X"00",X"00", + X"00",X"88",X"88",X"88",X"88",X"FF",X"FF",X"00",X"44",X"44",X"44",X"44",X"44",X"77",X"77",X"00", + X"8F",X"8F",X"8F",X"CF",X"CF",X"8F",X"8F",X"0F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"8F",X"8F",X"8F",X"CF",X"CF",X"8F",X"8F",X"0F",X"FF",X"FF",X"FF",X"77",X"BB",X"FF",X"FF",X"FF", + X"8F",X"8F",X"8F",X"CF",X"CF",X"8F",X"8F",X"0F",X"FF",X"FF",X"FF",X"FF",X"33",X"FF",X"FF",X"FF", + X"CF",X"CF",X"C7",X"EB",X"EB",X"C7",X"CF",X"CF",X"77",X"7E",X"3F",X"1F",X"1F",X"3F",X"76",X"77", + X"CF",X"CF",X"8F",X"8F",X"01",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"EE",X"CC", + X"00",X"00",X"00",X"01",X"8F",X"8F",X"CF",X"CF",X"CC",X"EE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"80",X"E0",X"F0",X"F0",X"F0",X"F0",X"E0",X"80",X"30",X"70",X"78",X"3C",X"3C",X"78",X"70",X"30", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"F0",X"1E",X"1E",X"1A",X"1E",X"1A",X"1E",X"F0",X"30",X"43",X"42",X"87",X"85",X"43",X"43",X"30", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"10", + 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X"00",X"00",X"00",X"17",X"1F",X"1F",X"08",X"08",X"00",X"00",X"70",X"F0",X"70",X"30",X"70",X"F0", + X"00",X"00",X"00",X"80",X"C0",X"C0",X"E0",X"E1",X"00",X"00",X"C8",X"C8",X"C8",X"40",X"0F",X"0F", + X"08",X"08",X"4C",X"4C",X"44",X"00",X"00",X"00",X"F0",X"70",X"30",X"70",X"F0",X"70",X"00",X"00", + X"E1",X"E0",X"C0",X"F2",X"B2",X"32",X"00",X"00",X"0F",X"0F",X"40",X"C0",X"C0",X"80",X"00",X"00", + X"00",X"00",X"00",X"1F",X"1F",X"1F",X"08",X"08",X"00",X"00",X"70",X"F0",X"70",X"30",X"70",X"F0", + X"00",X"00",X"00",X"80",X"C0",X"C0",X"E0",X"E1",X"00",X"00",X"62",X"62",X"62",X"40",X"0F",X"0F", + X"08",X"08",X"88",X"88",X"88",X"00",X"00",X"00",X"F0",X"70",X"30",X"70",X"F0",X"70",X"00",X"00", + X"E1",X"E0",X"C0",X"C0",X"80",X"00",X"F8",X"F8",X"0F",X"0F",X"41",X"41",X"C0",X"80",X"80",X"00", + X"00",X"00",X"00",X"88",X"88",X"88",X"08",X"08",X"00",X"00",X"70",X"F0",X"70",X"30",X"70",X"F0", + X"F8",X"F8",X"00",X"80",X"C0",X"C0",X"E0",X"E1",X"00",X"80",X"80",X"C0",X"41",X"41",X"0F",X"0F", + X"08",X"08",X"1F",X"1F",X"1F",X"00",X"00",X"00",X"F0",X"70",X"30",X"70",X"F0",X"70",X"00",X"00", + X"E1",X"E0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"0F",X"0F",X"40",X"62",X"62",X"62",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd new file mode 100644 index 00000000..0450232c --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM1_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM1_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM1_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09", + X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05", + X"07",X"0C",X"0E",X"0E",X"0D",X"0B",X"09",X"0A",X"0B",X"0B",X"0A",X"09",X"06",X"04",X"03",X"05", + X"07",X"09",X"0B",X"0A",X"08",X"05",X"04",X"03",X"03",X"04",X"05",X"03",X"01",X"00",X"00",X"02", + X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04", + X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00", + X"07",X"0D",X"0B",X"08",X"0B",X"0D",X"09",X"06",X"0B",X"0E",X"0C",X"07",X"09",X"0A",X"06",X"02", + X"07",X"0C",X"08",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01", + X"00",X"08",X"0F",X"07",X"01",X"08",X"0E",X"07",X"02",X"08",X"0D",X"07",X"03",X"08",X"0C",X"07", + X"04",X"08",X"0B",X"07",X"05",X"08",X"0A",X"07",X"06",X"08",X"09",X"07",X"07",X"08",X"08",X"07", + X"07",X"08",X"06",X"09",X"05",X"0A",X"04",X"0B",X"03",X"0C",X"02",X"0D",X"01",X"0E",X"00",X"0F", + X"00",X"0F",X"01",X"0E",X"02",X"0D",X"03",X"0C",X"04",X"0B",X"05",X"0A",X"06",X"09",X"07",X"08", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"0F",X"0E",X"0D",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"04",X"03",X"02",X"01",X"00", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F", + X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd new file mode 100644 index 00000000..84462c00 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM3_DST.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM3_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM3_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F", + X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D", + X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd new file mode 100644 index 00000000..50779097 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM4_DST.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM4_DST is +port ( + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM4_DST is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"01",X"00",X"00",X"00",X"00", + X"00",X"0F",X"0B",X"03",X"00",X"00",X"00",X"00",X"00",X"0F",X"0B",X"09",X"00",X"00",X"00",X"00", + X"00",X"0F",X"0B",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"0E", + X"00",X"0C",X"0F",X"01",X"00",X"01",X"0C",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"02",X"0B", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"0C",X"0B",X"0E",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"09",X"00",X"05",X"03",X"09", + X"00",X"0B",X"01",X"09",X"00",X"03",X"0C",X"0F",X"00",X"0E",X"00",X"0F",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin + data <= rom_data(to_integer(unsigned(addr))); +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd new file mode 100644 index 00000000..88b2ecb3 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/PROM7_DST.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity PROM7_DST is +port ( + clk : in std_logic; + addr : in std_logic_vector(3 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of PROM7_DST is + type rom is array(0 to 15) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"66",X"EF",X"00",X"F8",X"EA",X"6F",X"00",X"3F",X"00",X"C9",X"38",X"AA",X"AF",X"F6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd new file mode 100644 index 00000000..4f33c297 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_0.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_0 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"F3",X"3E",X"00",X"ED",X"47",X"C3",X"24",X"92",X"77",X"23",X"10",X"FC",X"C9",X"C3",X"18",X"04", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"78",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"C9", + X"E1",X"87",X"D7",X"5F",X"23",X"56",X"EB",X"E9",X"E1",X"46",X"23",X"4E",X"23",X"E5",X"18",X"12", + X"11",X"90",X"4C",X"06",X"10",X"C3",X"51",X"00",X"F5",X"ED",X"57",X"B7",X"20",X"27",X"F1",X"C3", + X"4F",X"9F",X"2A",X"80",X"4C",X"70",X"2C",X"71",X"2C",X"20",X"02",X"2E",X"C0",X"22",X"80",X"4C", + X"C9",X"1A",X"A7",X"28",X"06",X"1C",X"1C",X"1C",X"10",X"F7",X"C9",X"E1",X"06",X"03",X"7E",X"12", + X"23",X"1C",X"10",X"FA",X"E9",X"32",X"C0",X"50",X"AF",X"32",X"00",X"50",X"F3",X"C5",X"D5",X"E5", + X"DD",X"E5",X"FD",X"E5",X"21",X"8C",X"4E",X"11",X"50",X"50",X"01",X"10",X"00",X"ED",X"B0",X"3A", + X"9C",X"4E",X"A7",X"3A",X"CF",X"4E",X"28",X"03",X"3A",X"9F",X"4E",X"32",X"45",X"50",X"3A",X"AC", + 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mode 100644 index 00000000..1a7dea71 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/ROM/ROM_PGM_1.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM_1 is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3E",X"02",X"32",X"22",X"4E",X"C9",X"06",X"01",X"0E",X"0A",X"CD",X"A4",X"80",X"3A",X"E3",X"4D", + X"A7",X"C0",X"0E",X"02",X"16",X"00",X"1E",X"00",X"CD",X"CA",X"80",X"C9",X"06",X"06",X"0E",X"0A", + X"CD",X"A4",X"80",X"3A",X"E3",X"4D",X"A7",X"C0",X"0E",X"02",X"16",X"00",X"1E",X"00",X"CD",X"CA", + X"80",X"C9",X"06",X"00",X"18",X"12",X"06",X"02",X"18",X"0E",X"06",X"03",X"18",X"0A",X"06",X"04", + X"18",X"06",X"06",X"05",X"18",X"02",X"06",X"07",X"0E",X"0A",X"CD",X"A4",X"80",X"3A",X"E3",X"4D", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv new file mode 100644 index 00000000..9a6e01a1 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/Woodpecker.sv @@ -0,0 +1,196 @@ +//============================================================================ +// Arcade: Woodpecker +// +// Version for MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Woodpecker +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Woodpecker;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +//////////////////// CLOCKS /////////////////// + +wire clk_sys, clk_snd; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + + +reg ce_6m; +always @(posedge clk_sys) begin + reg [1:0] div; + + div <= div + 1'd1; + ce_6m <= !div; +end + +/////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +assign LED = 1; +//wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(340), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6m), + .ce_pix_actual(ce_6m), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; +wire m_skip = kbjoy[9]; + + +pacman woodpecker +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .in0(~{2'b00, m_coin, m_skip, m_down,m_right,m_left,m_up}), + .in1(~{1'b0, m_start2, m_start1, m_fire, 4'b0000}), + + .dipsw1(8'b1_1_00_11_01), + .dipsw2(8'b11111111), + + .RESET(status[0] | status[6] | buttons[1]), + .CLK(clk_sys), + .ENA_6(ce_6m) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/build_id.v b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/build_id.v new file mode 100644 index 00000000..54801cd2 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171122" +`define BUILD_TIME "110214" diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80sed.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/dac.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..fec08f5f --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/dpram.vhd @@ -0,0 +1,75 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + PORT + ( + address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0'); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) + ); +END dpram; + + +ARCHITECTURE SYN OF dpram IS +BEGIN + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2**addr_width_g, + numwords_b => 2**addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +END SYN; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/hq2x.sv b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/keyboard.v b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/mist_io.v b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/osd.v b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd new file mode 100644 index 00000000..24d19966 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman.vhd @@ -0,0 +1,469 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- Copyright (c) Sorgelig - 2017 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 006 Refactoring, 8 sprites support by Sorgelig +-- version 005 Papilio release by Jack Gassett +-- version 004 spartan3e release +-- version 003 Jan 2006 release, general tidy up +-- version 002 optional vga scan doubler +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN is + generic( + eight_sprites : boolean := false + ); + port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(1 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + -- + in0 : in std_logic_vector(7 downto 0); + in1 : in std_logic_vector(7 downto 0); + dipsw1 : in std_logic_vector(7 downto 0); + dipsw2 : in std_logic_vector(7 downto 0); + -- + RESET : in std_logic; + CLK : in std_logic; + ENA_6 : in std_logic + ); +end; + +architecture RTL of PACMAN is + + + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal do_hsync : boolean; + signal hsync : std_logic; + signal vsync : std_logic; + signal hblank : std_logic; + signal vblank : std_logic := '1'; + + -- cpu + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_int_l : std_logic := '1'; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal program_rom_dinl : std_logic_vector(7 downto 0); + signal program_rom_dinh : std_logic_vector(7 downto 0); + signal sync_bus_cs_l : std_logic; + + signal control_reg : std_logic_vector(7 downto 0); + -- + signal sync_bus_db : std_logic_vector(7 downto 0); + signal sync_bus_r_w_l : std_logic; + signal sync_bus_wreq_l : std_logic; + signal sync_bus_stb : std_logic; + + signal cpu_vec_reg : std_logic_vector(7 downto 0); + signal sync_bus_reg : std_logic_vector(7 downto 0); + + signal hp : std_logic_vector ( 4 downto 0); + signal vp : std_logic_vector ( 4 downto 0); + signal ram_cs : std_logic; + signal ram_data : std_logic_vector(7 downto 0); + signal vram_data : std_logic_vector(7 downto 0); + signal sprite_xy_data : std_logic_vector(7 downto 0); + signal vram_addr : std_logic_vector(11 downto 0); + + signal iodec_spr_l : std_logic; + signal iodec_out_l : std_logic; + signal iodec_wdr_l : std_logic; + signal iodec_sn1_l : std_logic; + signal iodec_sn2_l : std_logic; + signal iodec_in0_l : std_logic; + signal iodec_in1_l : std_logic; + signal iodec_dipsw1_l : std_logic; + signal iodec_dipsw2_l : std_logic; + + -- watchdog + signal watchdog_cnt : std_logic_vector(3 downto 0); + signal watchdog_reset_l : std_logic; + + signal sn_we : std_logic; + signal wav1,wav2,wav3 : std_logic_vector(7 downto 0); + + component ym2149 is port + ( + CLK : in std_logic; + CE : in std_logic; + RESET : in std_logic; + BDIR : in std_logic; + BC : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + CHANNEL_A: out std_logic_vector(7 downto 0); + CHANNEL_B: out std_logic_vector(7 downto 0); + CHANNEL_C: out std_logic_vector(7 downto 0); + + SEL : in std_logic; + MODE : in std_logic; + IOA_in : in std_logic_vector(7 downto 0); + IOA_out : out std_logic_vector(7 downto 0); + + IOB_in : in std_logic_vector(7 downto 0); + IOB_out : out std_logic_vector(7 downto 0) + ); + end component; + +begin + +-- +-- video timing +-- +p_hvcnt : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + if hcnt = "111111111" then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + if do_hsync then + if vcnt = "111111111" then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; +end process; + +vsync <= not vcnt(8); +do_hsync <= (hcnt = "010101111"); -- 0AF + +p_sync : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + + if (hcnt = "010001111") and not eight_sprites then -- 08F + hblank <= '1'; + elsif (hcnt = "011101111") and not eight_sprites then + hblank <= '0'; -- 0EF + elsif (hcnt = "111111111") and eight_sprites then + hblank <= '1'; + elsif (hcnt = "011111111") and eight_sprites then + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if (vcnt = "111101111") then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; +end process; + +-- +-- cpu +-- +p_irq_req_watchdog : process + variable rising_vblank : boolean; +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + rising_vblank := do_hsync and (vcnt = "111101111"); -- 1EF + + if (control_reg(0) = '0') then + cpu_int_l <= '1'; + elsif rising_vblank then -- 1EF + cpu_int_l <= '0'; + end if; + + -- watchdog 8c + -- note sync reset + if (reset = '1') then + watchdog_cnt <= "1111"; + elsif (iodec_wdr_l = '0') then + watchdog_cnt <= "0000"; + elsif rising_vblank then + watchdog_cnt <= watchdog_cnt + "1"; + end if; + + --watchdog_reset_l <= not reset; + + watchdog_reset_l <= '1'; + if (watchdog_cnt = "1111") then + watchdog_reset_l <= '0'; + end if; + end if; +end process; + +u_cpu : entity work.T80sed +port map +( + RESET_n => watchdog_reset_l, + CLK_n => clk, + CLKEN => hcnt(0) and ena_6, + WAIT_n => sync_bus_wreq_l, + INT_n => cpu_int_l, + NMI_n => '1', + BUSRQ_n => '1', + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => open, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out +); + +-- rom 0x0000 - 0x3FFF +-- syncbus 0x4000 - 0x7FFF +sync_bus_cs_l <= '0' when cpu_mreq_l = '0' and cpu_rfsh_l = '1' and cpu_addr(14) = '1' else '1'; +sync_bus_wreq_l <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '1' and cpu_rd_l = '0' else '1'; +sync_bus_stb <= '0' when sync_bus_cs_l = '0' and hcnt(1) = '0' else '1'; +sync_bus_r_w_l <= '0' when sync_bus_stb = '0' and cpu_rd_l = '1' else '1'; + +-- +-- sync bus custom ic +-- +p_sync_bus_reg : process +begin + wait until rising_edge(clk); + if (ena_6 = '1') then + -- register on sync bus module that is used to store interrupt vector + if (cpu_iorq_l = '0') and (cpu_m1_l = '1') then + cpu_vec_reg <= cpu_data_out; + end if; + + -- read holding reg + if (hcnt(1 downto 0) = "01") then + sync_bus_reg <= cpu_data_in; + end if; + end if; +end process; + + +-- WRITE +-- out_l 0x5000 - 0x503F control space +-- sn1_l 0x5040 - 0x504F sound +-- sn2_l 0x5050 - 0x505F sound +-- spr_l 0x5060 - 0x506F sprite +-- wdr_l 0x50C0 - 0x50FF watchdog reset +iodec_out_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_sn1_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"4" else '1'; +iodec_sn2_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"5" else '1'; +iodec_spr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 4) = X"50"&X"6" else '1'; +iodec_wdr_l <= '0' when sync_bus_r_w_l = '0' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +-- READ +-- in0_l 0x5000 - 0x503F in port 0 +-- in1_l 0x5040 - 0x507F in port 1 +-- dipsw_l 0x5080 - 0x50BF dip switches +iodec_in0_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"00" else '1'; +iodec_in1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"01" else '1'; +iodec_dipsw1_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"10" else '1'; +iodec_dipsw2_l <= '0' when sync_bus_r_w_l = '1' and cpu_addr(15 downto 6) = X"50"&"11" else '1'; + +p_control_reg : process +begin + -- 8 bit addressable latch 7K + -- (made into register) + + -- 0 interrupt ena + -- 1 sound ena + -- 2 not used + -- 3 flip + -- 4 1 player start lamp + -- 5 2 player start lamp + -- 6 coin lockout + -- 7 coin counter + + wait until rising_edge(clk); + if (ena_6 = '1') then + if (watchdog_reset_l = '0') then + control_reg <= (others => '0'); + elsif (iodec_out_l = '0') then + control_reg(to_integer(unsigned(cpu_addr(2 downto 0)))) <= cpu_data_out(0); + end if; + end if; +end process; + +cpu_data_in <= cpu_vec_reg when (cpu_iorq_l = '0') and (cpu_m1_l = '0') else + sync_bus_reg when sync_bus_wreq_l = '0' else + program_rom_dinl when cpu_addr(15 downto 14) = "00" else -- ROM at 0000 - 3fff + program_rom_dinh when cpu_addr(15 downto 14) = "10" else -- ROM at 8000 - bfff + in0 when iodec_in0_l = '0' else + in1 when iodec_in1_l = '0' else + dipsw1 when iodec_dipsw1_l = '0' else + dipsw2 when iodec_dipsw2_l = '0' else + ram_data; + +u_program_rom : entity work.ROM_PGM_0 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinl +); + +u_program_rom1 : entity work.ROM_PGM_1 +port map +( + CLK => clk, + ADDR => cpu_addr(13 downto 0), + DATA => program_rom_dinh +); + +ram_cs <= '1' when cpu_addr(15 downto 12) = X"4" else '0'; + +u_rams : work.dpram generic map (12,8) +port map +( + clock_a => clk, + enable_a => ena_6, + wren_a => not sync_bus_r_w_l and ram_cs, + address_a => cpu_addr(11 downto 0), + data_a => cpu_data_out, -- cpu only source of ram data + q_a => ram_data, + + clock_b => clk, + address_b => vram_addr(11 downto 0), + q_b => vram_data +); + +-- +-- video subsystem +-- + +-- vram addr custom ic +hp <= hcnt(7 downto 3) when control_reg(3) = '0' else not hcnt(7 downto 3); +vp <= vcnt(7 downto 3) when control_reg(3) = '0' else not vcnt(7 downto 3); +vram_addr <= '0' & hcnt(2) & vp & hp when hcnt(8)='1' else + x"FF" & hcnt(6 downto 4) & hcnt(2) when hblank = '1' else + '0' & hcnt(2) & hp(3) & hp(3) & hp(3) & hp(3) & hp(0) & vp; + +sprite_xy_ram : work.dpram generic map (4,8) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not iodec_spr_l, + address_a => cpu_addr(3 downto 0), + data_a => cpu_data_out, + + clock_b => CLK, + address_b => vram_addr(3 downto 0), + q_b => sprite_xy_data +); + +u_video : entity work.PACMAN_VIDEO +port map +( + I_HCNT => hcnt, + I_VCNT => vcnt, + -- + vram_data => vram_data, + sprite_xy => sprite_xy_data, + -- + I_HBLANK => hblank, + I_VBLANK => vblank, + I_FLIP => control_reg(3), + O_HBLANK => O_HBLANK, + -- + O_RED => O_VIDEO_R, + O_GREEN => O_VIDEO_G, + O_BLUE => O_VIDEO_B, + -- + ENA_6 => ena_6, + CLK => clk +); + +O_HSYNC <= hSync; +O_VSYNC <= vSync; +O_VBLANK <= vblank; + +-- +-- +-- audio subsystem +-- +u_audio : entity work.PACMAN_AUDIO +port map ( + I_HCNT => hcnt, + -- + I_AB => cpu_addr(11 downto 0), + I_DB => cpu_data_out, + -- + I_WR1_L => iodec_sn2_l, + I_WR0_L => iodec_sn1_l, + I_SOUND_ON => control_reg(1), + -- + O_AUDIO => O_AUDIO, + ENA_6 => ena_6, + CLK => clk +); + +end RTL; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd new file mode 100644 index 00000000..91313469 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman_audio.vhd @@ -0,0 +1,209 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 003 Jan 2006 release, general tidy up +-- version 002 added volume multiplier +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +library UNISIM; + +entity PACMAN_AUDIO is + port ( + I_HCNT : in std_logic_vector(8 downto 0); + -- + I_AB : in std_logic_vector(11 downto 0); + I_DB : in std_logic_vector( 7 downto 0); + -- + I_WR1_L : in std_logic; + I_WR0_L : in std_logic; + I_SOUND_ON : in std_logic; + -- + O_AUDIO : out std_logic_vector(7 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_AUDIO is + + signal addr : std_logic_vector(3 downto 0); + signal data : std_logic_vector(3 downto 0); + signal vol_ram_dout : std_logic_vector(3 downto 0); + signal frq_ram_dout : std_logic_vector(3 downto 0); + + signal sum : std_logic_vector(5 downto 0); + signal accum_reg : std_logic_vector(5 downto 0); + signal rom3m_n : std_logic_vector(15 downto 0); + signal rom3m_w : std_logic_vector(3 downto 0); + signal rom3m : std_logic_vector(3 downto 0); + + signal rom1m_addr : std_logic_vector(7 downto 0); + signal rom1m_data : std_logic_vector(7 downto 0); + +begin + p_sel_com : process(I_HCNT, I_AB, I_DB, accum_reg) + begin + if (I_HCNT(1) = '0') then -- 2h, + addr <= I_AB(3 downto 0); + data <= I_DB(3 downto 0); -- removed invert + else + addr <= I_HCNT(5 downto 2); + data <= accum_reg(4 downto 1); + end if; + end process; + + vol_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => not I_WR1_L, + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => vol_ram_dout + ); + + frq_ram : work.dpram generic map (4,4) + port map + ( + clock_a => CLK, + enable_a => ENA_6, + wren_a => rom3m(1), + address_a => addr(3 downto 0), + data_a => data, + + clock_b => CLK, + address_b => addr(3 downto 0), + q_b => frq_ram_dout + ); + + p_control_rom_comb : process(I_HCNT) + begin + rom3m_n <= x"0000"; rom3m_w <= x"0"; -- default assign + case I_HCNT(3 downto 0) is + when x"0" => rom3m_n <= x"0008"; rom3m_w <= x"0"; + when x"1" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"2" => rom3m_n <= x"1111"; rom3m_w <= x"0"; + when x"3" => rom3m_n <= x"2222"; rom3m_w <= x"0"; + when x"4" => rom3m_n <= x"0000"; rom3m_w <= x"0"; + when x"5" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"6" => rom3m_n <= x"1101"; rom3m_w <= x"0"; + when x"7" => rom3m_n <= x"2242"; rom3m_w <= x"0"; + when x"8" => rom3m_n <= x"0080"; rom3m_w <= x"0"; + when x"9" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"A" => rom3m_n <= x"1011"; rom3m_w <= x"0"; + when x"B" => rom3m_n <= x"2422"; rom3m_w <= x"0"; + when x"C" => rom3m_n <= x"0800"; rom3m_w <= x"0"; + when x"D" => rom3m_n <= x"0000"; rom3m_w <= x"2"; + when x"E" => rom3m_n <= x"0111"; rom3m_w <= x"0"; + when x"F" => rom3m_n <= x"4222"; rom3m_w <= x"0"; + when others => null; + end case; + end process; + + p_control_rom_op_comb : process(I_HCNT, I_WR0_L, rom3m_n, rom3m_w) + begin + rom3m <= rom3m_w; + if (I_WR0_L = '1') then + case I_HCNT(5 downto 4) is + when "00" => rom3m <= rom3m_n( 3 downto 0); + when "01" => rom3m <= rom3m_n( 7 downto 4); + when "10" => rom3m <= rom3m_n(11 downto 8); + when "11" => rom3m <= rom3m_n(15 downto 12); + when others => null; + end case; + end if; + end process; + + p_adder : process(vol_ram_dout, frq_ram_dout, accum_reg) + begin + -- 1K 4 bit adder + sum <= ('0' & vol_ram_dout & '1') + ('0' & frq_ram_dout & accum_reg(5)); + end process; + + p_accum_reg : process + begin + -- 1L + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (rom3m(3) = '1') then -- clear + accum_reg <= "000000"; + elsif (rom3m(0) = '1') then -- rising edge clk + accum_reg <= sum(5 downto 1) & accum_reg(4); + end if; + end if; + end process; + + p_rom_1m_addr_comb : process(accum_reg, frq_ram_dout) + begin + rom1m_addr(7 downto 5) <= frq_ram_dout(2 downto 0); + rom1m_addr(4 downto 0) <= accum_reg(4 downto 0); + + end process; + + audio_rom_1m : entity work.PROM1_DST + port map( + CLK => CLK, + ADDR => rom1m_addr, + DATA => rom1m_data + ); + + p_original_output_reg : process + begin + -- 2m used to use async clear + wait until rising_edge(CLK); + if (ENA_6 = '1') then + if (I_SOUND_ON = '0') then + O_AUDIO <= "00000000"; + elsif (rom3m(2) = '1') then + O_AUDIO <= vol_ram_dout(3 downto 0) * rom1m_data(3 downto 0); + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd new file mode 100644 index 00000000..1552d65b --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pacman_video.vhd @@ -0,0 +1,279 @@ +-- +-- A simulation model of Pacman hardware +-- Copyright (c) MikeJ - January 2006 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email pacman@fpgaarcade.com +-- +-- Revision list +-- +-- version 004 Refactoring, 8 sprite support by Sorgelig +-- version 003 Jan 2006 release, general tidy up +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity PACMAN_VIDEO is + generic( + alt_transp : boolean := false + ); + port ( + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + -- + vram_data : in std_logic_vector(7 downto 0); + sprite_xy : in std_logic_vector(7 downto 0); + -- + I_HBLANK : in std_logic; + I_VBLANK : in std_logic; + I_FLIP : in std_logic; + O_HBLANK : out std_logic; + -- + O_RED : out std_logic_vector(2 downto 0); + O_GREEN : out std_logic_vector(2 downto 0); + O_BLUE : out std_logic_vector(1 downto 0); + ENA_6 : in std_logic; + CLK : in std_logic + ); +end; + +architecture RTL of PACMAN_VIDEO is + + signal dr : std_logic_vector(7 downto 0); + + signal char_reg : std_logic_vector(7 downto 0); + signal char_sum_reg : std_logic_vector(3 downto 0); + signal char_match_reg : std_logic; + signal char_hblank_reg : std_logic; + signal char_hblank_reg_t1 : std_logic; + signal sprite_data : std_logic_vector(7 downto 0); + + signal xflip : std_logic; + signal yflip : std_logic; + signal obj_on : std_logic; + signal obj_on2 : std_logic; + + signal ca : std_logic_vector(12 downto 0); + signal char_rom_5ef_buf : std_logic_vector(7 downto 0); + + signal shift_regl : std_logic_vector(3 downto 0); + signal shift_regu : std_logic_vector(3 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_op_t1 : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + + signal vout_obj_on : std_logic; + signal vout_obj_on_t1 : std_logic; + signal vout_yflip : std_logic; + signal vout_hblank : std_logic; + signal vout_hblank_t1 : std_logic; + signal vout_db : std_logic_vector(4 downto 0); + + signal sprite_ram_ip : std_logic_vector(5 downto 0); + signal sprite_ram_op : std_logic_vector(5 downto 0); + signal sprite_addr : std_logic_vector(7 downto 0); + signal sprite_addr_t1 : std_logic_vector(7 downto 0); + + signal lut_4a : std_logic_vector(7 downto 0); + signal lut_4a_t1 : std_logic_vector(7 downto 0); + signal sprite_ram_reg : std_logic_vector(5 downto 0); + + signal video_op_sel : std_logic; + signal final_col : std_logic_vector(3 downto 0); + +begin + +dr <= not sprite_xy when I_HBLANK = '1' else "11111111"; -- pull ups on board + +p_char_regs : process + variable sum : std_logic_vector(8 downto 0); + variable match : std_logic; +begin + wait until rising_edge (CLK); + if (I_HCNT(2 downto 0) = "011") and (ENA_6 = '1') then -- rising 4h + + -- 1f, 2f + sum := (I_VCNT(7 downto 0) & '1') + (dr & not I_HBLANK); + + -- 3e + match := '0'; + + if (sum(8 downto 5) = "1111") then + match := '1'; + end if; + + -- 1h + char_sum_reg <= sum(4 downto 1); + char_match_reg <= match; + char_hblank_reg <= I_HBLANK; + + -- 4d + sprite_data <= vram_data; -- character reg + end if; +end process; + +xflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(1); +yflip <= I_FLIP when char_hblank_reg = '0' else sprite_data(0); + +obj_on <= char_match_reg or I_HCNT(8); -- 256h not 256h_l + +ca(12) <= char_hblank_reg; +ca(11 downto 6) <= sprite_data(7 downto 2); +ca(5) <= sprite_data(1) when char_hblank_reg = '0' else char_sum_reg(3) xor xflip; +ca(4) <= sprite_data(0) when char_hblank_reg = '0' else I_HCNT(3); +ca(3) <= I_HCNT(2) xor yflip; +ca(2) <= char_sum_reg(2) xor xflip; +ca(1) <= char_sum_reg(1) xor xflip; +ca(0) <= char_sum_reg(0) xor xflip; + +-- char roms +char_rom_5ef : entity work.GFX1 +port map +( + CLK => CLK, + ADDR => ca, + DATA => char_rom_5ef_buf +); + +p_char_shift : process +begin + -- 4 bit shift req + wait until rising_edge (CLK); + if (ENA_6 = '1') then + case shift_sel is + when "00" => null; + + when "01" => shift_regu <= '0' & shift_regu(3 downto 1); + shift_regl <= '0' & shift_regl(3 downto 1); + + when "10" => shift_regu <= shift_regu(2 downto 0) & '0'; + shift_regl <= shift_regl(2 downto 0) & '0'; + + when "11" => shift_regu <= char_rom_5ef_buf(7 downto 4); -- load + shift_regl <= char_rom_5ef_buf(3 downto 0); + when others => null; + end case; + end if; +end process; + +shift_sel(0) <= I_HCNT(0) and I_HCNT(1) when vout_yflip = '0' else '1'; +shift_sel(1) <= '1' when vout_yflip = '0' else I_HCNT(0) and I_HCNT(1); +shift_op(0) <= shift_regl(3) when vout_yflip = '0' else shift_regl(0); +shift_op(1) <= shift_regu(3) when vout_yflip = '0' else shift_regu(0); + +p_video_out_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + if (I_HCNT(2 downto 0) = "111") then + vout_obj_on <= obj_on; + vout_yflip <= yflip; + vout_hblank <= I_HBLANK; + vout_db(4 downto 0) <= vram_data(4 downto 0); -- colour reg + end if; + + if I_HCNT(3 downto 0) = "0111" and (vout_hblank='1' or I_HBLANK='1' or vout_obj_on='0') then + sprite_addr <= dr; + else + sprite_addr <= sprite_addr + "1"; + end if; + end if; +end process; + +col_rom_4a : entity work.PROM4_DST +port map +( + ADDR(7) => '0', + ADDR(6 downto 2) => vout_db(4 downto 0), + ADDR(1 downto 0) => shift_op(1 downto 0), + DATA => lut_4a +); + +u_sprite_ram : work.dpram generic map (8,6) +port map +( + clock_a => CLK, + enable_a => ENA_6, + wren_a => vout_obj_on_t1, + address_a => sprite_addr_t1, + data_a => sprite_ram_ip, + + clock_b => CLK, + enable_b => ENA_6, + address_b => sprite_addr, + q_b => sprite_ram_op +); + +sprite_ram_reg <= sprite_ram_op when vout_obj_on_t1 = '1' else "000000"; +video_op_sel <= '0' when alt_transp and (sprite_ram_reg(1 downto 0) = "00") else + '0' when not alt_transp and (sprite_ram_reg(5 downto 2) = "0000") else + '1'; + +p_sprite_ram_ip_reg : process +begin + wait until rising_edge (CLK); + if (ENA_6 = '1') then + sprite_addr_t1 <= sprite_addr; + vout_obj_on_t1 <= vout_obj_on; + vout_hblank_t1 <= vout_hblank; + lut_4a_t1 <= lut_4a; + shift_op_t1 <= shift_op; + end if; +end process; + +sprite_ram_ip <= (others => '0') when vout_hblank_t1 = '0' else + sprite_ram_reg when video_op_sel = '1' else + lut_4a_t1(3 downto 0) & shift_op_t1; + +final_col <= (others => '0') when (vout_hblank = '1') or (I_VBLANK = '1') else + sprite_ram_reg(5 downto 2) when video_op_sel = '1' else + lut_4a(3 downto 0); + +-- assign video outputs from color LUT PROM +col_rom_7f : entity work.PROM7_DST +port map +( + CLK => CLK, + ADDR(3 downto 0) => final_col, + DATA(2 downto 0) => O_RED, + DATA(5 downto 3) => O_GREEN, + DATA(7 downto 6) => O_BLUE +); + +O_HBLANK <= vout_hblank and vout_hblank_t1; + +end architecture; diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pll.qip b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pll.v b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pll.v new file mode 100644 index 00000000..60297687 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 9, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/scandoubler.v b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/video_mixer.sv b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Pacman Hardware/Woodpecker_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/README.txt b/Arcade/README.txt new file mode 100644 index 00000000..a5461c9f --- /dev/null +++ b/Arcade/README.txt @@ -0,0 +1,79 @@ +Arcade Cores + +#Custom Hardware + Computer Space + Galaga + Phoenix + Pooyan + River Raid(Clone) + Time Pilot + +#Data East Cassette + Burnin Rubber + Burger Time + +#Galaxian Hardware + Azurian Attack + Black Hole + Catacomb + Galaxian + Moon Cresta + Mr. Do´s Nightmare + Omega + Orbitron + Pisces + War of Bugs + +#Irem M52 Hardware + Moon Patrol + +#Ladybug Hardware + Cosmic Avenger + Dorodon + Lady Bug + Snapjack + +#Konami Classic + Pooyan + Time Pilot + +#Midway 8080 Hardware + Galaxy Wars + Lunar Rescue + Space Attack + Space Invaders + Space Invaders II(Deluxe) + Space Laser + Super Earth Invasion + +#Pacman Hardware + Ali Baba and 40 Thieves + Crush Roller + Dream Shopper + Eeekk + Eyes + Gorkans + Lizard Wizard + Maniac Miner + Mr. TNT + Ms. Pacman + Pacman + Pacman Club + Pacman Plus + Pengo + Ponpoko + Super Glob + Van Van Car + Woodpecker + +#Scramble Hardware + Amidar + Frogger + Scramble + The End + + + + + + diff --git a/Arcade/Scramble Hardware/Amidar_MiST/Amidar.qpf b/Arcade/Scramble Hardware/Amidar_MiST/Amidar.qpf new file mode 100644 index 00000000..45200a41 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/Amidar.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Amidar" diff --git a/Arcade/Scramble Hardware/Amidar_MiST/Amidar.qsf b/Arcade/Scramble Hardware/Amidar_MiST/Amidar.qsf new file mode 100644 index 00000000..a61f9bf0 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/Amidar.qsf @@ -0,0 +1,170 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 05:08:48 November 15, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Amidar_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY Amidar + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ---------------------- +# start ENTITY(Scramble) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Scramble) +# -------------------- +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_LUT.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd +set_global_assignment -name VHDL_FILE rtl/i82c55.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VERILOG_FILE rtl/build_id.v +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd +set_global_assignment -name VHDL_FILE rtl/scramble.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Amidar.sv +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Amidar_MiST/Amidar.srf b/Arcade/Scramble Hardware/Amidar_MiST/Amidar.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/Amidar.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Scramble Hardware/Amidar_MiST/README.txt b/Arcade/Scramble Hardware/Amidar_MiST/README.txt new file mode 100644 index 00000000..df8b7083 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/README.txt @@ -0,0 +1,23 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Amidar port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Scramble Hardware/Amidar_MiST/Release/Amidar.rbf b/Arcade/Scramble Hardware/Amidar_MiST/Release/Amidar.rbf new file mode 100644 index 00000000..c3501900 Binary files /dev/null and b/Arcade/Scramble Hardware/Amidar_MiST/Release/Amidar.rbf differ diff --git a/Arcade/Scramble Hardware/Amidar_MiST/clean.bat b/Arcade/Scramble Hardware/Amidar_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/Amidar.sv b/Arcade/Scramble Hardware/Amidar_MiST/rtl/Amidar.sv new file mode 100644 index 00000000..40a982bd --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/Amidar.sv @@ -0,0 +1,203 @@ +//============================================================================ +// Arcade: Amidar +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module Amidar +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Amidar;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6p, ce_6n, ce_12, ce_1p79; +always @(negedge clk_sys) begin + reg [1:0] div = 0; + reg [3:0] div179 = 0; + + div <= div + 1'd1; + + ce_12 <= div[0]; + ce_6p <= div[0] & ~div[1]; + ce_6n <= div[0] & div[1]; + + ce_1p79 <= 0; + div179 <= div179 - 1'd1; + if(!div179) begin + div179 <= 13; + ce_1p79 <= 1; + end +end + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +wire hsync,vsync; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [3:0] r,b,g; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6p), + .ce_pix_actual(ce_6p), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r[1:0]}), + .G({g,g[1:0]}), + .B({b,b[1:0]}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire m_Serv = kbjoy[9]; + +scramble_top scramble +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .button_in1(~{m_start1, m_fire, m_bomb, m_left, m_right, m_up, m_down}), + .button_in2(~{m_start2, m_fire, m_bomb, m_left, m_right, m_up, m_down}), + .Coin_in(~m_coin), + .Service_in(~m_Serv), + .RESET(status[0] | status[6] | buttons[1]), + .clk(clk_sys), + .ena_12(ce_12), + .ena_6(ce_6p), + .ena_6b(ce_6n), + .ena_1_79(ce_1p79) +); +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd new file mode 100644 index 00000000..32535505 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/MULT18X18.vhd @@ -0,0 +1,53 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY MULT18X18 IS + PORT + ( + A : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); +END MULT18X18; + + +ARCHITECTURE SYN OF mult18x18 IS + + COMPONENT lpm_mult + GENERIC ( + lpm_hint : STRING; + lpm_representation : STRING; + lpm_type : STRING; + lpm_widtha : NATURAL; + lpm_widthb : NATURAL; + lpm_widthp : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + lpm_mult_component : lpm_mult + GENERIC MAP ( + lpm_hint => "MAXIMIZE_SPEED=5", + lpm_representation => "SIGNED", + lpm_type => "LPM_MULT", + lpm_widtha => 18, + lpm_widthb => 18, + lpm_widthp => 36 + ) + PORT MAP ( + dataa => A, + datab => B, + result => P + ); + +END SYN; + diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd new file mode 100644 index 00000000..f356cfca --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_LUT.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_LUT is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_LUT is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"C0",X"B6",X"00",X"38",X"C5",X"67",X"00",X"30",X"07",X"3F",X"00",X"07",X"30",X"3F", + X"00",X"3F",X"30",X"07",X"00",X"38",X"67",X"3F",X"00",X"FF",X"07",X"DF",X"00",X"F8",X"07",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd new file mode 100644 index 00000000..698a76f7 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"92",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"3C",X"42",X"81",X"A5",X"A5",X"99",X"42",X"3C",X"00",X"00",X"C0",X"F0",X"FB",X"03",X"00",X"00", + X"0C",X"1E",X"1E",X"1E",X"3C",X"3C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"30",X"78",X"7C",X"3E",X"7C",X"78",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00", + X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00", + X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00", + X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00",X"9E",X"9E",X"92",X"92",X"C6",X"7C",X"38",X"00", + X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00", + X"FC",X"FE",X"02",X"02",X"02",X"06",X"04",X"00",X"82",X"C6",X"6E",X"3C",X"18",X"FE",X"FE",X"00", + X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00", + X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00", + X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"00",X"00",X"81",X"C3",X"7E",X"3C",X"00",X"00", + X"72",X"F6",X"9E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00", + X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00", + X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"FE",X"FE",X"1C",X"38",X"1C",X"FE",X"FE",X"00", + X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"E0",X"F0",X"1E",X"1E",X"F0",X"E0",X"00",X"00", + X"10",X"12",X"1C",X"78",X"1C",X"12",X"10",X"00",X"00",X"00",X"10",X"10",X"10",X"10",X"10",X"00", + X"00",X"1D",X"3F",X"7B",X"71",X"73",X"63",X"37",X"00",X"0C",X"08",X"00",X"32",X"7D",X"FD",X"FC", + X"7D",X"39",X"01",X"31",X"10",X"00",X"00",X"00",X"F8",X"F8",X"F0",X"F4",X"E8",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03", + X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03", + X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03", + X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF", + X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF",X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF", + X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF",X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF", + X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF",X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF", + X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80", + X"03",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"03",X"07",X"07", + X"03",X"00",X"00",X"00",X"00",X"03",X"07",X"07",X"00",X"00",X"00",X"00",X"00",X"03",X"87",X"87", + X"03",X"00",X"00",X"00",X"00",X"03",X"87",X"87",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03", + X"03",X"03",X"03",X"03",X"03",X"03",X"83",X"83",X"03",X"03",X"03",X"03",X"03",X"03",X"83",X"83", + X"03",X"03",X"03",X"03",X"03",X"03",X"07",X"07",X"03",X"03",X"03",X"03",X"03",X"03",X"07",X"07", + X"03",X"03",X"03",X"03",X"03",X"03",X"87",X"87",X"03",X"03",X"03",X"03",X"03",X"03",X"87",X"87", + X"03",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF", + 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Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd new file mode 100644 index 00000000..eedda2b1 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_OBJ_1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + 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std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"68",X"C3",X"71",X"00",X"FF",X"77",X"3C",X"23",X"77",X"3C",X"19",X"C9",X"FF", + X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"87",X"E1",X"5F",X"16",X"00",X"19",X"5E",X"23", + X"56",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"FF",X"E5",X"26",X"40",X"3A",X"A0",X"40",X"6F",X"CB", + X"7E",X"28",X"0E",X"72",X"2C",X"73",X"2C",X"7D",X"FE",X"C0",X"30",X"02",X"3E",X"C0",X"32",X"A0", + X"40",X"E1",X"C9",X"0F",X"11",X"22",X"04",X"31",X"06",X"15",X"02",X"33",X"07",X"21",X"03",X"24", + X"05",X"13",X"01",X"FF",X"FF",X"FF",X"C3",X"A3",X"04",X"80",X"40",X"20",X"10",X"08",X"04",X"02", + X"01",X"21",X"00",X"40",X"11",X"01",X"40",X"01",X"00",X"08",X"36",X"00",X"ED",X"B0",X"3E",X"9B", + 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-0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_0 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"21",X"00",X"80",X"06",X"00",X"C3",X"B3",X"01",X"D3",X"40",X"DB",X"80",X"C9",X"FF",X"FF",X"FF", + X"D3",X"10",X"DB",X"20",X"C9",X"FF",X"FF",X"FF",X"78",X"CF",X"79",X"D3",X"80",X"C9",X"FF",X"FF", + X"78",X"D7",X"79",X"D3",X"20",X"C9",X"FF",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E", + X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"41",X"00",X"08",X"D9",X"FB", + X"C9",X"3E",X"0E",X"CF",X"B7",X"28",X"09",X"F2",X"7A",X"00",X"CB",X"BF",X"CD",X"6D",X"00",X"C9", + X"21",X"00",X"80",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00",X"80",X"06",X"06", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd new file mode 100644 index 00000000..58fdcb19 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"DD",X"7E",X"01",X"FD",X"77",X"01",X"DD",X"7E",X"02",X"FD",X"77",X"02",X"FD",X"36",X"05",X"00", + X"C3",X"62",X"0F",X"04",X"0F",X"0F",X"00",X"21",X"13",X"10",X"11",X"A8",X"80",X"01",X"04",X"00", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd new file mode 100644 index 00000000..43e9cd64 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/ROM/ROM_SND_2.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_2 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"8C",X"8F",X"8C",X"88",X"8C",X"88",X"8C",X"8F",X"8C",X"88",X"AF",X"FF",X"1F",X"0A",X"5F", + X"09",X"A8",X"80",X"68",X"68",X"A8",X"80",X"68",X"68",X"88",X"83",X"88",X"8C",X"88",X"83",X"88", + X"83",X"88",X"8C",X"88",X"83",X"88",X"83",X"88",X"8C",X"88",X"83",X"AC",X"FF",X"FF",X"CD",X"C7", + X"06",X"3E",X"01",X"32",X"73",X"80",X"CD",X"0D",X"05",X"C3",X"8E",X"0F",X"CD",X"C7",X"06",X"CD", + X"0D",X"05",X"C9",X"CD",X"C7",X"06",X"CD",X"0D",X"05",X"C9",X"DD",X"21",X"50",X"80",X"C3",X"DA", + X"0D",X"DD",X"21",X"58",X"80",X"C3",X"DA",X"0D",X"DD",X"21",X"60",X"80",X"C3",X"DA",X"0D",X"1F", + X"0A",X"3F",X"0E",X"5F",X"08",X"85",X"85",X"85",X"8A",X"8A",X"8A",X"8A",X"91",X"91",X"91",X"91", + X"8F",X"8F",X"D6",X"93",X"8F",X"93",X"B6",X"93",X"8F",X"93",X"B6",X"FF",X"1F",X"0A",X"5F",X"08", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/build_id.tcl b/Arcade/Scramble Hardware/Amidar_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/build_id.v b/Arcade/Scramble Hardware/Amidar_MiST/rtl/build_id.v new file mode 100644 index 00000000..7a9ccfc6 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171117" +`define BUILD_TIME "104831" diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/dac.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/dpram.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/hq2x.sv b/Arcade/Scramble Hardware/Amidar_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd new file mode 100644 index 00000000..d415d932 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/i82c55.vhd @@ -0,0 +1,686 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity I82C55 is + port ( + + I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_CS_L : in std_logic; + I_RD_L : in std_logic; + I_WR_L : in std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_PC : in std_logic_vector(7 downto 0); + O_PC : out std_logic_vector(7 downto 0); + O_PC_OE_L : out std_logic_vector(7 downto 0); + + RESET : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + CLK : in std_logic + ); +end; + +architecture RTL of I82C55 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(I_DATA) + begin + bit_mask <= x"01"; + case I_DATA(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and I_DATA(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (I_CS_L = '0') and (I_WR_L = '0') then + case I_ADDR is + when "00" => r_porta <= I_DATA; + when "01" => r_portb <= I_DATA; + when "10" => r_portc <= I_DATA; + + when "11" => if (I_DATA(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= I_DATA; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + p_oe : process(I_CS_L, I_RD_L) + begin + O_DATA_OE_L <= '1'; + if (I_CS_L = '0') and (I_RD_L = '0') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read) + begin + O_DATA <= x"00"; -- default + --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required + case I_ADDR is + when "00" => O_DATA <= porta_read; + when "01" => O_DATA <= portb_read; + when "10" => O_DATA <= portc_read; + when "11" => O_DATA <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (I_CS_L = '0') and (I_ADDR = "00") then + porta_we <= not I_WR_L; + porta_re <= not I_RD_L; + end if; + + if (I_CS_L = '0') and (I_ADDR = "01") then + portb_we <= not I_WR_L; + portb_re <= not I_RD_L; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= I_DATA(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= I_DATA(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= I_DATA(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + O_PA <= x"FF"; -- if not driven, float high + O_PA_OE_L <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= I_PA; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_control, groupb_mode, r_portb, I_PB, portb_ipreg) + begin + O_PB <= x"FF"; -- if not driven, float high + O_PB_OE_L <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= I_PB; + else -- strobed mode + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + O_PC <= x"FF"; -- if not driven, float high + O_PC_OE_L <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + O_PC (7 downto 4) <= r_portc(7 downto 4); + O_PC_OE_L(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + O_PC (5 downto 4) <= r_portc(5 downto 4); + O_PC_OE_L(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + O_PC (7 downto 6) <= r_portc(7 downto 6); + O_PC_OE_L(7 downto 6) <= "00"; + end if; + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + O_PC (3) <= r_portc(3); + O_PC_OE_L(3) <= '0'; + end if; + -- + else -- stolen + O_PC (3) <= a_intr; + O_PC_OE_L(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + O_PC (2 downto 0) <= r_portc(2 downto 0); + O_PC_OE_L(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + O_PC (1) <= b_obf_l; + O_PC_OE_L(1) <= '0'; + else -- input + O_PC (1) <= b_ibf; + O_PC_OE_L(1) <= '0'; + end if; + O_PC (0) <= b_intr; + O_PC_OE_L(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= I_PC(6); + else -- port a input + a_stb_l <= I_PC(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= I_PC(6); + a_stb_l <= I_PC(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= I_PC(2); + else -- input + b_stb_l <= I_PC(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= I_PC(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= I_PC(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= I_PA; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= I_PB; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/keyboard.v b/Arcade/Scramble Hardware/Amidar_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/mist_io.v b/Arcade/Scramble Hardware/Amidar_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/osd.v b/Arcade/Scramble Hardware/Amidar_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/pll.qip b/Arcade/Scramble Hardware/Amidar_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/pll.v b/Arcade/Scramble Hardware/Amidar_MiST/rtl/pll.v new file mode 100644 index 00000000..1d3529bd --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/scandoubler.v b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble.vhd new file mode 100644 index 00000000..e496ae76 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble.vhd @@ -0,0 +1,587 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE is + port ( + I_HWSEL_FROGGER : in boolean; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + -- to audio board + -- + O_ADDR : out std_logic_vector(15 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + I_DATA_OE_L : in std_logic; + O_RD_L : out std_logic; + O_WR_L : out std_logic; + O_IOPC7 : out std_logic; + O_RESET_WD_L : out std_logic; + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + -- + RESET : in std_logic; -- active high + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE is + + type array_4x8 is array (0 to 3) of std_logic_vector(7 downto 0); + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal reset_wd_l : std_logic; + + -- timing decode + signal do_hsync : boolean; + signal set_vblank : boolean; + signal vsync : std_logic; + signal hsync : std_logic; + signal vblank : std_logic; + signal hblank : std_logic; + -- + -- cpu + signal cpu_ena : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal page_4to7_l : std_logic; + + signal wren : std_logic; + + signal objen_l : std_logic; + signal waen_l : std_logic; + + signal objramrd_l : std_logic; + signal vramrd_l : std_logic; + + signal select_l : std_logic; + signal objramwr_l : std_logic; + signal vramwr_l : std_logic; + + -- control reg + signal control_reg : std_logic_vector(7 downto 0); + signal intst_l : std_logic; + signal iopc7 : std_logic; + signal pout1 : std_logic; + signal starson : std_logic; + signal hcma : std_logic; + signal vcma : std_logic; + + signal pgm_rom_dout : array_4x8; + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + signal ram_ena : std_logic; + + signal vram_data : std_logic_vector(7 downto 0); + +begin + + O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + set_vblank <= (vcnt = "111101111"); -- 1EF + end process; + + p_sync : process + begin + wait until rising_edge(CLK); + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + if (ENA = '1') then + if (hcnt = "010000001") then -- 081 + hblank <= '1'; + elsif (hcnt = "011111111") then -- 0f9 + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if set_vblank then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + p_video_timing_reg : process + begin + wait until rising_edge(CLK); + -- match output delay in video module + if (ENA = '1') then + O_HSYNC <= HSYNC; + O_VSYNC <= VSYNC; + end if; + end process; + + p_cpu_ena : process(hcnt, ENA) + begin + -- cpu clocked on rising edge of 1h, late + cpu_ena <= ENA and hcnt(0); -- 1h + end process; + -- + -- video + -- + u_video : entity work.SCRAMBLE_VIDEO + port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_HCNT => hcnt, + I_VCNT => vcnt, + I_VBLANK => vblank, + I_VSYNC => vsync, + + I_VCMA => vcma, + I_HCMA => hcma, + -- + I_CPU_ADDR => cpu_addr, + I_CPU_DATA => cpu_data_out, + O_VRAM_DATA => vram_data, + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L => vramwr_l, + I_VRAMRD_L => vramrd_l, + I_OBJRAMWR_L => objramwr_l, + I_OBJRAMRD_L => objramrd_l, + I_OBJEN_L => objen_l, + -- + I_STARSON => starson, + I_POUT1 => pout1, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + -- + ENA => ENA, + ENAB => ENAB, + ENA_12 => ENA_12, + CLK => CLK + ); + + -- other cpu signals + reset_wd_l <= not RESET; -- FIX + + p_cpu_wait : process(vblank, hblank, waen_l) + begin + -- this is done a bit differently, the original had a late + -- clock to the cpu, and as mreq came out a litle early it could assert + -- wait and then gate off the write strobe to vram/objram in time. + -- + -- we are a nice synchronous system therefore we need to do this combinatorially. + -- timing is still ok. + -- + if (vblank = '1') then + cpu_wait_l <='1'; + else + cpu_wait_l <= '1'; + if (hblank = '0') and (waen_l = '0') then + cpu_wait_l <= '0'; + end if; + end if; + end process; + wren <= cpu_wait_l; + + p_cpu_int : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (intst_l = '0') then + cpu_nmi_l <= '1'; + else + if do_hsync and set_vblank then + cpu_nmi_l <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => reset_wd_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => open, + MREQ_n => cpu_mreq_l, + IORQ_n => open, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode : process(cpu_rfsh_l, cpu_rd_l, cpu_wr_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + begin + -- Scramble map + --0000-3fff ROM + --4000-47ff RAM + --4800-4bff Video RAM + --5000-50ff Object RAM + --5000-503f screen attributes + --5040-505f sprites + --5060-507f bullets + --5080-50ff unused? + + --read: + --7000 Watchdog Reset (Scramble) + --8100 IN0 + --8101 IN1 + --8102 IN2 (bits 5 and 7 used for protection check in Scramble) + + --write: + --6800-6807 control reg + --8200 To AY-3-8910 port A (commands for the audio CPU) + --8201 bit 3 = interrupt trigger on audio CPU bit 4 = AMPM (?) + --8202 protection check control? + + -- Frogger map + --0000-3fff ROM + --8000-87ff RAM + --a800-abff Video RAM + --b000-b0ff Object RAM + --b000-b03f screen attributes + --b040-b05f sprites + --b060-b0ff unused? + + --read: + --8800 Watchdog Reset + --e000 IN0 + --e002 IN1 + --e004 IN2 + cpu_int_l <= '1'; + cpu_busrq_l <= '1'; + + page_4to7_l <= '1'; + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + + if I_HWSEL_FROGGER then + cpu_int_l <= '0'; + cpu_busrq_l <= cpu_addr(15); + end if; + + if not I_HWSEL_FROGGER then + if (cpu_addr(15 downto 14) = "01") then page_4to7_l <= '0'; end if; + else + if (cpu_addr(15 downto 14) = "10") then page_4to7_l <= '0'; end if; + end if; + end if; + + end process; + + p_mem_decode2 : process(I_HWSEL_FROGGER, cpu_addr, page_4to7_l, cpu_rfsh_l, cpu_rd_l, cpu_wr_l, wren) + begin + waen_l <= '1'; + objen_l <= '1'; + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "001") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objen_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "101") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objen_l <= '0'; end if; + end if; + end if; + + -- read decode + vramrd_l <= '1'; + objramrd_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "001") then vramrd_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramrd_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "101") then vramrd_l <= '0'; end if; + end if; + end if; + -- write decode + vramwr_l <= '1'; + objramwr_l <= '1'; + select_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "001") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "101") then select_l <= '0'; end if; -- control reg + end if; + else + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "101") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "111") then select_l <= '0'; end if; -- control reg + end if; + end if; + end process; + + p_control_reg : process + variable addr : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- scramble + --6801 interrupt enable + --6802 coin counter + --6803 ? (POUT1) + --6804 stars on + --6805 ? (POUT2) + --6806 screen vertical flip + --6807 screen horizontal flip + if not I_HWSEL_FROGGER then + addr := cpu_addr(2 downto 0); + else + addr := cpu_addr(4 downto 2); + end if; + + dec := "00000000"; + if (select_l = '0') then + case addr(2 downto 0) is + when "000" => dec := "00000001"; + when "001" => dec := "00000010"; + when "010" => dec := "00000100"; + when "011" => dec := "00001000"; + when "100" => dec := "00010000"; + when "101" => dec := "00100000"; + when "110" => dec := "01000000"; + when "111" => dec := "10000000"; + when others => null; + end case; + end if; + + if (reset_wd_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (dec(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_control_reg_assign : process(control_reg, I_HWSEL_FROGGER) + begin + if not I_HWSEL_FROGGER then + -- Scramble + intst_l <= control_reg(1); + iopc7 <= control_reg(2); + pout1 <= control_reg(3); + starson <= control_reg(4); + hcma <= control_reg(6); + vcma <= control_reg(7); + else + intst_l <= control_reg(2); + iopc7 <= control_reg(6); + pout1 <= control_reg(7); + starson <= '0'; + hcma <= control_reg(4); + vcma <= control_reg(3); + end if; + end process; + -- + -- + -- roms / rams + pgm_rom : entity work.ROM_PGM + port map (CLK => CLK, ADDR => cpu_addr(13 downto 0), DATA => rom_dout); +-- pgm_rom01 : entity work.ROM_PGM_01 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(0)); +-- pgm_rom23 : entity work.ROM_PGM_23 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(1)); +-- pgm_rom45 : entity work.ROM_PGM_45 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(2)); +-- pgm_rom56 : entity work.ROM_PGM_67 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(3)); + +-- p_rom_mux : process(cpu_addr, pgm_rom_dout) +-- begin +-- rom_dout <= (others => '0'); +-- case cpu_addr(13 downto 12) is +-- when "00" => rom_dout <= pgm_rom_dout(0); +-- when "01" => rom_dout <= pgm_rom_dout(1); +-- when "10" => rom_dout <= pgm_rom_dout(2); +-- when "11" => rom_dout <= pgm_rom_dout(3); +-- when others => null; +-- end case; +-- end process; + + u_cpu_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => ram_ena and (not cpu_wr_l), + + addr_a_i => cpu_addr(10 downto 0), + data_a_i => cpu_data_out, + + clk_b_i => clk, + addr_b_i => cpu_addr(10 downto 0), + data_b_o => ram_dout + ); + + p_ram_ctrl : process(cpu_addr, page_4to7_l) + begin + ram_ena <= '0'; + if (page_4to7_l = '0') and (cpu_addr(13 downto 11) = "000") then + ram_ena <= '1'; + end if; + end process; + + p_cpu_data_in_mux : process(I_HWSEL_FROGGER, cpu_addr, cpu_rd_l, cpu_mreq_l, cpu_rfsh_l, ram_dout, rom_dout, vramrd_l, vram_data, I_DATA_OE_L, I_DATA ) + variable ram_addr : std_logic_vector(1 downto 0); + begin + + if not I_HWSEL_FROGGER then + ram_addr := "01"; + else + ram_addr := "10"; + end if; + + cpu_data_in <= (others => '0'); + if (vramrd_l = '0') then + cpu_data_in <= vram_data; + -- + elsif (I_DATA_OE_L = '0') then + cpu_data_in <= I_DATA; + -- + elsif (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(15 downto 14) = "00") and (cpu_rd_l = '0') and (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + cpu_data_in <= rom_dout; + -- + elsif (cpu_addr(15 downto 14) = ram_addr) then + if (cpu_addr(13 downto 11) = "000") and (cpu_rd_l = '0') then + cpu_data_in <= ram_dout; + else + cpu_data_in <= x"FF"; + end if; + end if; + else + cpu_data_in <= x"FF"; + end if; + + end process; + + -- to audio + O_ADDR <= cpu_addr; + O_DATA <= cpu_data_out; + O_RD_L <= cpu_rd_l; + O_WR_L <= cpu_wr_l; + O_IOPC7 <= iopc7; + O_RESET_WD_L <= reset_wd_l; + +end RTL; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd new file mode 100644 index 00000000..21d6f5f8 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_audio.vhd @@ -0,0 +1,834 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_AUDIO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_ADDR : in std_logic_vector(15 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + O_DATA_OE_L : out std_logic; + -- + I_RD_L : in std_logic; + I_WR_L : in std_logic; + I_IOPC7 : in std_logic; + -- + O_AUDIO : out std_logic_vector( 9 downto 0); + -- + I_1P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_SERVICE : in std_logic; + I_COIN1 : in std_logic; + I_COIN2 : in std_logic; + O_COIN_COUNTER : out std_logic; + -- + I_DIP : in std_logic_vector( 5 downto 1); + -- + I_RESET_L : in std_logic; + ENA : in std_logic; -- 6 MHz + ENA_1_79 : in std_logic; -- 1.78975 MHz + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE_AUDIO is + + signal reset : std_logic; + signal cpu_ena : std_logic; + signal cpu_ena_gated : std_logic; + -- + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + -- + signal ram_cs : std_logic; + signal rom_oe : std_logic; + signal filter_load : std_logic; + signal filter_reg : std_logic_vector(11 downto 0); + -- + signal cpu_rom0_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom1_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom2_dout : std_logic_vectoR(7 downto 0); + signal rom_active : std_logic; + + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + -- + signal i8255_addr : std_logic_vector(1 downto 0); + signal i8255_1D_data : std_logic_vector(7 downto 0); + signal i8255_1D_data_oe_l : std_logic; + signal i8255_1D_cs_l : std_logic; + signal i8255_1D_pa_out : std_logic_vector(7 downto 0); + signal i8255_1D_pb_out : std_logic_vector(7 downto 0); + -- + signal i8255_1E_data : std_logic_vector(7 downto 0); + signal i8255_1E_data_oe_l : std_logic; + signal i8255_1E_cs_l : std_logic; + signal i8255_1E_pa : std_logic_vector(7 downto 0); + signal i8255_1E_pb : std_logic_vector(7 downto 0); + signal i8255_1E_pc : std_logic_vector(7 downto 0); + + -- security + signal net_1e10_i : std_logic; + signal net_1e12_i : std_logic; + signal xb : std_logic_vector(7 downto 0); + signal xbo : std_logic_vector(7 downto 0); + + signal audio_div_cnt : std_logic_vector( 8 downto 0) := (others => '0'); + signal ls90_op : std_logic_vector(3 downto 0); + signal ls90_clk : std_logic; + signal ls90_cnt : std_logic_vector( 3 downto 0) := (others => '0'); + -- ym2149 3C + signal ym2149_3C_dv : std_logic_vector(7 downto 0); + signal ym2149_3C_oe_l : std_logic; + signal ym2149_3C_bdir : std_logic; + signal ym2149_3C_bc2 : std_logic; + signal ym2149_3C_bc1 : std_logic; + signal ym2149_3C_audio : std_logic_vector(7 downto 0); + signal ym2149_3C_chan : std_logic_vector(1 downto 0); + signal ym2149_3C_chan_t1 : std_logic_vector(1 downto 0); + -- + -- ym2149 3D + signal ym2149_3D_dv : std_logic_vector(7 downto 0); + signal ym2149_3D_oe_l : std_logic; + signal ym2149_3D_bdir : std_logic; + signal ym2149_3D_bc2 : std_logic; + signal ym2149_3D_bc1 : std_logic; + signal ym2149_3D_audio : std_logic_vector(7 downto 0); + signal ym2149_3D_chan : std_logic_vector(1 downto 0); + signal ym2149_3D_chan_t1 : std_logic_vector(1 downto 0); + signal ym2149_3D_ioa_in : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_out : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_oe_l : std_logic; + signal ym2149_3D_iob_in : std_logic_vector(7 downto 0); + -- + signal ampm : std_logic; + signal sint : std_logic; + signal sint_t1 : std_logic; + -- + signal audio_3C_mix : std_logic_vector(9 downto 0); + signal audio_3C_final : std_logic_vector(9 downto 0); + signal audio_3D_mix : std_logic_vector(9 downto 0); + signal audio_3D_final : std_logic_vector(9 downto 0); + signal audio_final : std_logic_vector(10 downto 0); + + signal security_count : std_logic_vector(2 downto 0); + signal rd_l_t1 : std_logic; + -- filters + signal ym2149_3C_k : std_logic_vector(16 downto 0); + signal ym2149_3D_k : std_logic_vector(16 downto 0); + signal audio_in_m_out_3C : std_logic_vector(17 downto 0); + signal audio_in_m_out_3D : std_logic_vector(17 downto 0); + signal audio_mult_3C : std_logic_vector(35 downto 0); + signal audio_mult_3D : std_logic_vector(35 downto 0); + + + + type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0); + constant K_Filter : array_4of17 := ('0' & x"00A3", + '0' & x"00C6", + '0' & x"039D", + '1' & x"0000" ); + + type filter_pipe is array (3 downto 0) of std_logic_vector(17 downto 0); + signal ym2149_3C_audio_pipe : filter_pipe; + signal ym2149_3D_audio_pipe : filter_pipe; + -- LP filter out = in.k + out_t1.(1-k) + -- + -- = (in-out_t1).k + out_t1 + -- + -- using + -- -(Ts.2.PI.Fc) + -- k = 1-e + -- + -- sampling freq = 1.79 MHz + -- + -- cut off freqs bit 0 1 + -- + --0.267uf ~ 713 Hz 1 1 0.00249996 x 00A3 + --0.220uf ~ 865 Hz 1 0 0.00303210 x 00C6 + --0.047uf ~ 4050 Hz 0 1 0.01411753 x 039D + -- 0 0 x10000 + +begin + -- scramble + --0000-1fff ROM + --8000-83ff RAM + + -- frogger + --0000-17ff ROM + --4000-43ff RAM + + cpu_ena <= '1'; -- run at audio clock speed + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + cpu_wait_l <= '1'; + -- + cpu_ena_gated <= ENA_1_79 and cpu_ena; + u_cpu : entity work.T80sed + port map ( + RESET_n => I_RESET_L, + CLK_n => CLK, + CLKEN => cpu_ena_gated, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + p_cpu_int : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + cpu_int_l <= '1'; + sint_t1 <= '0'; + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + sint_t1 <= sint; + + if (cpu_m1_l = '0') and (cpu_iorq_l = '0') then + cpu_int_l <= '1'; + elsif (sint = '0') and (sint_t1 = '1') then + cpu_int_l <= '0'; + end if; + end if; + end if; + end process; + + p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + variable decode : std_logic; + begin + if not I_HWSEL_FROGGER then + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(12)); + else + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(14) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(13) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(13)); + end if; + + rom_oe <= '0'; + if not I_HWSEL_FROGGER then + if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + else + if (cpu_addr(14) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + end if; + + end process; + + u_rom_5c : entity work.ROM_SND_0 + port map ( + CLK => CLK, + ADDR => cpu_addr(11 downto 0), + DATA => cpu_rom0_dout + ); + + u_rom_5d : entity work.ROM_SND_1 + port map ( + CLK => CLK, + ADDR => cpu_addr(11 downto 0), + DATA => cpu_rom1_dout + ); + + p_rom_mux : process(I_HWSEL_FROGGER, cpu_rom0_dout, cpu_rom1_dout, cpu_addr, rom_oe) + variable rom_oe_decode : std_logic; + variable cpu_rom0_dout_s : std_logic_vector(7 downto 0); + begin + if not I_HWSEL_FROGGER then + cpu_rom0_dout_s := cpu_rom0_dout; + else -- swap bits 0 and 1 + cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1); + end if; + + rom_dout <= (others => '0'); + rom_oe_decode := '0'; + case cpu_addr(13 downto 12) is + when "00" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1'; + when "01" => rom_dout <= cpu_rom1_dout; rom_oe_decode := '1'; + when others => null; + end case; + + rom_active <= '0'; + if (rom_oe = '1') then + rom_active <= rom_oe_decode; + end if; + end process; + + u_ram_6c_6d : work.dpram generic map (10,8) + port map + ( + addr_a_i => cpu_addr(9 downto 0), + data_a_i => cpu_data_out, + clk_b_i => clk, + addr_b_i => cpu_addr(9 downto 0), + data_b_o => ram_dout, + we_i => ram_cs and (not cpu_wr_l), + en_a_i => ENA_1_79, + clk_a_i => clk + ); + + p_cpu_data_mux : process(rom_dout, rom_active, ram_dout, ym2149_3C_oe_l, ym2149_3C_dv, ym2149_3D_oe_l, ym2149_3D_dv, ram_cs, cpu_wr_l) + begin + if (rom_active = '1') then + cpu_data_in <= rom_dout; + elsif (ram_cs = '1') and (cpu_wr_l = '1') then + cpu_data_in <= ram_dout; + elsif (ym2149_3C_oe_l = '0') then + cpu_data_in <= ym2149_3C_dv; + elsif (ym2149_3D_oe_l = '0') then + cpu_data_in <= ym2149_3D_dv; + else + cpu_data_in <= (others => '1'); -- float high + end if; + end process; + + p_filter_reg : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + if (filter_load = '1') then + filter_reg <= cpu_addr(11 downto 0); + end if; + end if; + end process; + + p_8255_decode : process(I_RESET_L, I_ADDR, I_HWSEL_FROGGER) + begin + reset <= not I_RESET_L; + i8255_1D_cs_l <= '1'; + i8255_1E_cs_l <= '1'; + + if not I_HWSEL_FROGGER then + -- the interface one + if (I_ADDR(9) = '1') and (I_ADDR(15) = '1') then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(8) = '1') and (I_ADDR(15) = '1') then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(1 downto 0); + else + -- the interface one + if (I_ADDR(12) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(13) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(2 downto 1); + end if; + end process; + + p_ym_decode : process(cpu_rd_l, cpu_wr_l, cpu_iorq_l, cpu_addr, I_HWSEL_FROGGER) + variable rd_3c : std_logic; + variable wr_3c : std_logic; + variable ad_3c : std_logic; + -- + variable rd_3d : std_logic; + variable wr_3d : std_logic; + variable ad_3d : std_logic; + begin + + --bdir bc2 bc1 + -- 0 0 0 nop + -- 0 0 1 addr latch < WR_L AV4 / AV6 + -- 0 1 0 nop + -- 0 1 1 data read < RD_L AV5 / AV7 + + -- 1 0 0 addr latch + -- 1 0 1 nop + -- 1 1 0 data write < WR_L AV5 / AV7 + -- 1 1 1 addr latch + + + if not I_HWSEL_FROGGER then + rd_3c := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(5); + wr_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(5); + ad_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(4); + else + rd_3c := '0'; + wr_3c := '0'; + ad_3c := '0'; + end if; + + ym2149_3C_bdir <= wr_3c; + ym2149_3C_bc2 <= rd_3c or wr_3c; + ym2149_3C_bc1 <= rd_3c or ad_3c; + + + if not I_HWSEL_FROGGER then + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(7); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + else + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(6); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + end if; + + ym2149_3D_bdir <= wr_3d; + ym2149_3D_bc2 <= rd_3d or wr_3d; + ym2149_3D_bc1 <= rd_3d or ad_3d; + + end process; + + i8255_1E_pa(7) <= I_COIN1; + i8255_1E_pa(6) <= I_COIN2; + i8255_1E_pa(5) <= I_1P_CTRL(3); -- left + i8255_1E_pa(4) <= I_1P_CTRL(2); -- right + i8255_1E_pa(3) <= I_1P_CTRL(4); -- shoot1 + i8255_1E_pa(2) <= I_SERVICE; + i8255_1E_pa(1) <= I_1P_CTRL(5); -- shoot2 + i8255_1E_pa(0) <= I_2P_CTRL(1); -- up + + i8255_1E_pb(7) <= I_1P_CTRL(6); -- start + i8255_1E_pb(6) <= I_2P_CTRL(6); -- start + i8255_1E_pb(5) <= I_2P_CTRL(3); -- left + i8255_1E_pb(4) <= I_2P_CTRL(2); -- right + i8255_1E_pb(3) <= I_2P_CTRL(4); -- shoot1 + i8255_1E_pb(2) <= I_2P_CTRL(5); -- shoot2 + i8255_1E_pb(1) <= I_DIP(1); + i8255_1E_pb(0) <= I_DIP(2); + + i8255_1E_pc(7) <= net_1e10_i; + i8255_1E_pc(6) <= I_1P_CTRL(0); -- down + i8255_1E_pc(5) <= net_1e12_i; + i8255_1E_pc(4) <= I_1P_CTRL(1); -- up + i8255_1E_pc(3) <= I_DIP(3); + i8255_1E_pc(2) <= I_DIP(4); + i8255_1E_pc(1) <= I_DIP(5); + i8255_1E_pc(0) <= I_2P_CTRL(0); -- down + O_COIN_COUNTER <= not I_IOPC7; -- open drain actually + + -- + -- PIA CHIPS + -- + u_i8255_1D : entity work.I82C55 -- bus interface + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1D_data, + O_DATA_OE_L => i8255_1D_data_oe_l, + + I_CS_L => i8255_1D_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1D_pa_out, + O_PA => i8255_1D_pa_out, + O_PA_OE_L => open, + + I_PB => i8255_1D_pb_out, + O_PB => i8255_1D_pb_out, + O_PB_OE_L => open, + + I_PC => xbo, + O_PC => xb, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + u_i8255_1E : entity work.I82C55 -- push button + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1E_data, + O_DATA_OE_L => i8255_1E_data_oe_l, + + I_CS_L => i8255_1E_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1E_pa, + O_PA => open, + O_PA_OE_L => open, + + I_PB => i8255_1E_pb, + O_PB => open, + O_PB_OE_L => open, + + I_PC => i8255_1E_pc, + O_PC => open, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + p_i8255_1d_bus_control : process(i8255_1D_pa_out, i8255_1D_pb_out, ym2149_3D_ioa_out, ym2149_3D_ioa_oe_l) + begin + if (ym2149_3D_ioa_oe_l = '0') then + ym2149_3D_ioa_in <= ym2149_3D_ioa_out; + else + ym2149_3D_ioa_in <= i8255_1D_pa_out; + end if; + + ampm <= i8255_1D_pb_out(4); -- amp mute + sint <= i8255_1D_pb_out(3); -- set int + end process; + + p_drive_cpubus : process(i8255_1D_data, i8255_1D_data_oe_l, i8255_1E_data, i8255_1E_data_oe_l) + begin + O_DATA_OE_L <= '1'; + O_DATA <= (others => '0'); + -- + if (i8255_1D_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1D_data; + elsif (i8255_1E_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1E_data; + end if; + end process; + -- + -- AUDIO CHIPS + -- + p_audio_clockgen : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + audio_div_cnt <= audio_div_cnt - "1"; + ls90_clk <= not audio_div_cnt(8); + + if (audio_div_cnt(8 downto 0) = "000000000") then + if (ls90_cnt = x"9") then + ls90_cnt <= x"0"; + else + ls90_cnt <= ls90_cnt + "1"; + end if; + end if; + + ls90_op <= "0000"; + case ls90_cnt is --ls90 outputs DCBA + when x"0" => ls90_op <= "0000"; + when x"1" => ls90_op <= "0010"; + when x"2" => ls90_op <= "0100"; + when x"3" => ls90_op <= "0110"; + when x"4" => ls90_op <= "1000"; + when x"5" => ls90_op <= "0001"; + when x"6" => ls90_op <= "0011"; + when x"7" => ls90_op <= "0101"; + when x"8" => ls90_op <= "0111"; + when x"9" => ls90_op <= "1001"; + when others => ls90_op <= "0000"; + end case; + end if; + end process; + + p_ym2149_3d_iob_in : process(I_HWSEL_FROGGER, ls90_op, ls90_clk) + begin + if not I_HWSEL_FROGGER then + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & ls90_op(2) & ls90_clk & "1110"; + else + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & '1' & ls90_clk & ls90_op(2) & "110"; + end if; + end process; + + u_ym2149_3C : entity work.YM2149 -- not used for frogger + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3C_dv, + O_DA_OE_L => ym2149_3C_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3C_bdir, + I_BC2 => ym2149_3C_bc2, + I_BC1 => ym2149_3C_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3C_audio, + O_CHAN => ym2149_3C_chan, + -- port a + I_IOA => "11111111", + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => "11111111", + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + u_ym2149_3D : entity work.YM2149 + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3D_dv, + O_DA_OE_L => ym2149_3D_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3D_bdir, + I_BC2 => ym2149_3D_bc2, + I_BC1 => ym2149_3D_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3D_audio, + O_CHAN => ym2149_3D_chan, + -- port a + I_IOA => ym2149_3D_ioa_in, + O_IOA => ym2149_3D_ioa_out, + O_IOA_OE_L => ym2149_3D_ioa_oe_l, + -- port b + I_IOB => ym2149_3D_iob_in, + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + p_filter_coef : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + case ym2149_3C_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3C_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(5 downto 4))); + when "10" => -- chan 1 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(3 downto 2))); + when "01" => -- chan 0 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(1 downto 0))); + when others => null; + end case; + + case ym2149_3D_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3D_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg(11 downto 10))); + when "10" => -- chan 1 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 9 downto 8))); + when "01" => -- chan 0 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 7 downto 6))); + when others => null; + end case; + end if; + end process; + + + p_ym2149_audio_process : process(ym2149_3C_audio, ym2149_3C_audio_pipe, ym2149_3D_audio, ym2149_3D_audio_pipe) + begin + audio_in_m_out_3C <= (('0' & ym2149_3C_audio & "000000000"))- ym2149_3C_audio_pipe(3); -- signed + audio_in_m_out_3D <= (('0' & ym2149_3D_audio & "000000000"))- ym2149_3D_audio_pipe(3); -- signed + end process; + + mult_3C : work.MULT18X18 + port map + ( + P => audio_mult_3C,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3C, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3C_k + ); + + mult_3D : work.MULT18X18 + port map + ( + P => audio_mult_3D,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3D, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3D_k + ); + + p_ym2149_audio_pipe : process(I_RESET_L, CLK) + begin + if (I_RESET_L = '0') then + ym2149_3C_audio_pipe <= (others => (others => '0')); + ym2149_3D_audio_pipe <= (others => (others => '0')); + elsif rising_edge(CLK) then +-- audio_mult_3C <= audio_in_m_out_3C * ym2149_3C_k; +-- audio_mult_3D <= audio_in_m_out_3D * ym2149_3D_k; + if (ENA_1_79 = '1') then + -- we need some holding registers anyway, so lets just make it a shift and save a mux + ym2149_3C_audio_pipe(3 downto 1) <= ym2149_3C_audio_pipe(2 downto 0); + ym2149_3C_audio_pipe(0) <= audio_mult_3C(33 downto 16) + ym2149_3C_audio_pipe(3); -- bit 33 sign + + ym2149_3D_audio_pipe(3 downto 1) <= ym2149_3D_audio_pipe(2 downto 0); + ym2149_3D_audio_pipe(0) <= audio_mult_3D(33 downto 16) + ym2149_3D_audio_pipe(3); -- bit 33 sign + end if; + end if; + end process; + + p_ym2149_audio_mix : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + ym2149_3C_chan_t1 <= ym2149_3C_chan; + ym2149_3D_chan_t1 <= ym2149_3D_chan; + + if (ym2149_3C_chan_t1 = "11") then + audio_3C_mix <= (others => '0'); + audio_3C_final <= audio_3C_mix; + else + audio_3C_mix <= audio_3C_mix + ("00" & ym2149_3C_audio_pipe(0)(16 downto 9)); + end if; + + if (ym2149_3D_chan_t1(1 downto 0) = "11") then + audio_3D_mix <= (others => '0'); + audio_3D_final <= audio_3D_mix; + else + audio_3D_mix <= audio_3D_mix + ("00" & ym2149_3D_audio_pipe(0)(16 downto 9)); + end if; + + audio_final <= ('0' & audio_3C_final) + ('0' & audio_3D_final); + end if; + end process; + + p_audio_out : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + O_AUDIO <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + if (ampm = '1') then + O_AUDIO <= (others => '0'); + else + if (audio_final(10) = '1') then + O_AUDIO <= (others => '1'); + else + O_AUDIO <= audio_final(9 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_security_6J : process(xb) + begin + -- chip K10A PAL16L8 + -- equations from Mark @ http://www.leopardcats.com/ + xbo(3 downto 0) <= xb(3 downto 0); + xbo(4) <= not(xb(0) or xb(1) or xb(2) or xb(3)); + xbo(5) <= not((not xb(2) and not xb(0)) or (not xb(2) and not xb(1)) or (not xb(3) and not xb(0)) or (not xb(3) and not xb(1))); + + xbo(6) <= not(not xb(0) and not xb(3)); + xbo(7) <= not((not xb(1)) or xb(2)); + end process; + + p_security_count : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + security_count <= "000"; + elsif rising_edge(CLK) then + rd_l_t1 <= i_rd_l; + if (I_ADDR = x"8102") and (I_RD_L = '0') and (rd_l_t1 = '1') then + security_count <= security_count + "1"; + end if; + end if; + end process; + + p_security_2B : process(security_count) + begin + -- I am not sure what this chip does yet, but this gets us past the initial check for now. + case security_count is + when "000" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "001" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "010" => net_1e10_i <= '1'; net_1e12_i <= '0'; + when "011" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "100" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "101" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "110" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "111" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when others => null; + end case; + end process; + +end RTL; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd new file mode 100644 index 00000000..960fc642 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_top.vhd @@ -0,0 +1,201 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_TOP is +port ( + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + + O_AUDIO : out std_logic_vector(9 downto 0); + button_in1 : in std_logic_vector(6 downto 0); + button_in2 : in std_logic_vector(6 downto 0); + Coin_in : in std_logic; + Service_in : in std_logic; + RESET : in std_logic; + clk : in std_logic; -- 25 + ena_12 : in std_logic; -- 6.25 x 2 + ena_6 : in std_logic; -- 6.25 (inverted) + ena_6b : in std_logic; -- 6.25 + ena_1_79 : in std_logic -- 1.786 +); +end; + +architecture RTL of SCRAMBLE_TOP is +-- this MUST be set true for frogger +-- this MUST be set false for scramble, the_end, amidar +constant I_HWSEL_FROGGER : boolean := false; + +signal ip_dip_switch : std_logic_vector(5 downto 1); + +-- ties to audio board +signal audio_addr : std_logic_vector(15 downto 0); +signal audio_data_out : std_logic_vector(7 downto 0); +signal audio_data_in : std_logic_vector(7 downto 0); +signal audio_data_oe_l : std_logic; +signal audio_rd_l : std_logic; +signal audio_wr_l : std_logic; +signal audio_iopc7 : std_logic; +signal audio_reset_l : std_logic; + +begin + +u_scramble : entity work.SCRAMBLE +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + O_HSYNC => O_HSYNC, + O_VSYNC => O_VSYNC, + O_HBLANK => O_HBLANK, + O_VBLANK => O_VBLANK, + -- + -- to audio board + -- + O_ADDR => audio_addr, + O_DATA => audio_data_out, + I_DATA => audio_data_in, + I_DATA_OE_L => audio_data_oe_l, + O_RD_L => audio_rd_l, + O_WR_L => audio_wr_l, + O_IOPC7 => audio_iopc7, + O_RESET_WD_L => audio_reset_l, + -- + ENA => ena_6, + ENAB => ena_6b, + ENA_12 => ena_12, + -- + RESET => reset, + CLK => clk +); + +-- +-- +-- audio subsystem +-- +u_audio : entity work.SCRAMBLE_AUDIO +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_ADDR => audio_addr, + I_DATA => audio_data_out, + O_DATA => audio_data_in, + O_DATA_OE_L => audio_data_oe_l, + -- + I_RD_L => audio_rd_l, + I_WR_L => audio_wr_l, + I_IOPC7 => audio_iopc7, + -- + O_AUDIO => O_AUDIO, + + I_1P_CTRL => button_in1, + I_2P_CTRL => button_in2, + I_SERVICE => Service_in, + I_COIN1 => Coin_in, + I_COIN2 => Service_in,--'1', + O_COIN_COUNTER => open, + -- + I_DIP => ip_dip_switch, + -- + I_RESET_L => audio_reset_l, + ENA => ena_6, + ENA_1_79 => ena_1_79, + CLK => clk +); + +-- dip switch settings +scramble_dips : if (not I_HWSEL_FROGGER) generate +begin + --SW #1 SW #2 Rockets SW #3 Cabinet + ------- ----- --------- ----- -------- + --OFF OFF Unlimited OFF Table + --OFF ON 5 ON Up Right + --ON OFF 4 + --ON ON 3 + + + --SW #4 SW #5 Coins/Play + ------- ----- ---------- + --OFF OFF 4 + --OFF ON 3 + --ON OFF 2 + --ON ON 1 + + ip_dip_switch(5 downto 4) <= not "11"; -- 1 play/coin. + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "10"; +end generate; + +frogger_dips : if ( I_HWSEL_FROGGER) generate +begin + --1 2 3 4 5 Meaning + ------------------------------------------------------- + --On On 3 Frogs + --On Off 5 Frogs + --Off On 7 Frogs + --Off Off 256 Frogs (!) + -- + -- On Upright unit + -- Off Cocktail unit + -- + -- On On 1 coin 1 play + -- On Off 2 coins 1 play + -- Off On 3 coins 1 play + -- Off Off 1 coin 2 plays + + ip_dip_switch(5 downto 4) <= not "11"; + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "01"; +end generate; + +end RTL; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd new file mode 100644 index 00000000..47fd3641 --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/scramble_video.vhd @@ -0,0 +1,758 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_VIDEO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + I_VBLANK : in std_logic; + I_VSYNC : in std_logic; + + I_VCMA : in std_logic; + I_HCMA : in std_logic; + -- + I_CPU_ADDR : in std_logic_vector(15 downto 0); + I_CPU_DATA : in std_logic_vector(7 downto 0); + O_VRAM_DATA : out std_logic_vector(7 downto 0); + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L : in std_logic; + I_VRAMRD_L : in std_logic; + I_OBJRAMWR_L : in std_logic; + I_OBJRAMRD_L : in std_logic; + I_OBJEN_L : in std_logic; + -- + I_STARSON : in std_logic; + I_POUT1 : in std_logic; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + CLK : in std_logic + ); +end; + +-- chars stars vidout? shell/missile +-- +-- 220R B 100 B 390R B 100R R +-- 470R B 150 B 100R G +-- 220R G 100 G blue ? +-- 470R G 150 G +-- 1K G 100 R +-- 220R R 150 R +-- 470R R +-- 1K R +architecture RTL of SCRAMBLE_VIDEO is + + type array_3x5 is array (2 downto 0) of std_logic_vector(4 downto 0); + -- timing + signal ld : std_logic; + signal h256_l : std_logic; + signal h256 : std_logic; + signal cblank_s : std_logic; + signal hcmp1_s : std_logic; + signal hcmp2_s : std_logic; + signal hcmp1 : std_logic; + signal hcmp2 : std_logic; + signal cblank_l : std_logic; + signal h256_l_s : std_logic; + signal hcnt_f : std_logic_vector(7 downto 0); + signal vcnt_f : std_logic_vector(7 downto 0); + + -- load strobes + signal vpl_load : std_logic; + signal col_load : std_logic; + signal objdata_load : std_logic; + signal missile_load : std_logic; + signal missile_reg_l : std_logic; + + signal cntr_clr : std_logic; + signal cntr_load : std_logic; + signal sld_l : std_logic; + + -- video ram + signal vram_addr_sum : std_logic_vector(8 downto 0); -- extra bit for debug + signal msld_l : std_logic; + signal vram_addr_reg : std_logic_vector(7 downto 0); + signal vram_addr_xor : std_logic_vector(3 downto 0); + signal vram_addr : std_logic_vector(9 downto 0); + signal vram_dout : std_logic_vector(7 downto 0); + signal ldout : std_logic; + + -- object ram + signal obj_addr : std_logic_vector(7 downto 0); + signal hpla : std_logic_vector(7 downto 0); + signal objdata : std_logic_vector(7 downto 0); + + signal obj_rom_addr : std_logic_vector(10 downto 0); + signal obj_rom_0_dout : std_logic_vector(7 downto 0); + signal obj_rom_1_dout : std_logic_vector(7 downto 0); + -- + signal col_reg : std_logic_vector(2 downto 0); + signal cd : std_logic_vector(2 downto 0); + + signal shift_reg_1 : std_logic_vector(7 downto 0); + signal shift_reg_0 : std_logic_vector(7 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + signal gr : std_logic_vector(1 downto 0); + signal gc : std_logic_vector(2 downto 0); + + signal vid : std_logic_vector(1 downto 0); + signal col : std_logic_vector(2 downto 0); + + signal obj_video_out_reg : std_logic_vector(4 downto 0); + signal vidout_l : std_logic; + signal obj_lut_out : std_logic_vector(7 downto 0); + + signal cntr_addr : std_logic_vector(7 downto 0); + signal cntr_addr_xor : std_logic_vector(10 downto 0); + signal sprite_sel : std_logic; + signal sprite_ram_ip : std_logic_vector(7 downto 0); + signal sprite_ram_waddr : std_logic_vector(10 downto 0); + signal sprite_ram_op : std_logic_vector(7 downto 0); + -- shell + signal shell_cnt : std_logic_vector(7 downto 0); + signal shell_ena : std_logic; + signal shell : std_logic; + signal shell_reg : std_logic; + -- stars + signal star_reg_1 : std_logic; + signal star_reg_2 : std_logic; + signal star_cnt_div : std_logic_vector(22 downto 0); + signal star_cnt : std_logic_vector(1 downto 0); + signal star_shift : std_logic_vector(16 downto 0); + signal star_shift_t1 : std_logic_vector(16 downto 0); + signal star_on : std_logic; + signal star_out_reg : std_logic; + -- frogger blue bar + signal frogger_blue_reg : std_logic; + signal frogger_blue : std_logic; + signal frogger_blue_out_reg : std_logic; + -- scramble blue + signal pout1_reg : std_logic; + + +begin + p_hcnt_decode : process(I_HCNT) + begin + ld <= '0'; + if (I_HCNT(2 downto 0) = "111") then + ld <= '1'; + end if; + h256_l <= I_HCNT(8); + h256 <= not I_HCNT(8); + + end process; + + p_timing_decode : process(h256, h256_l, I_HCMA, I_VBLANK) + begin + cblank_s <= not (I_VBLANK or h256); -- active low + hcmp1_s <= h256_l and I_HCMA; + end process; + + p_reg : process + begin + wait until rising_edge(CLK); + + if (ENA = '1') then + if (ld = '1') then + hcmp1 <= hcmp1_s; + hcmp2 <= hcmp2_s; + cblank_l <= cblank_s; + h256_l_s <= h256_l; + + if not I_HWSEL_FROGGER then + cd <= col_reg; + else + cd <= col_reg(0) & col_reg(2 downto 1); + end if; + end if; + end if; + end process; + + p_load_decode : process(ld, I_HCNT, h256) + variable obj_load : std_logic; + begin + vpl_load <= '0'; + obj_load := '0'; + col_load <= '0'; + + if (I_HCNT(2 downto 0) = "001") then vpl_load <= '1'; end if; -- 1 clock later + if (I_HCNT(2 downto 0) = "011") then obj_load := '1'; end if; -- 1 later + if (I_HCNT(2 downto 0) = "101") then col_load <= '1'; end if; -- 1 later + + objdata_load <= obj_load and h256 and (not I_HCNT(3)); + missile_load <= obj_load and h256 and ( I_HCNT(3)); + + cntr_clr <= ld and (not h256) and (not I_HCNT(3)); + cntr_load <= ld and ( h256) and (not I_HCNT(3)); + + end process; + + p_hv_flip : process(I_HCNT, I_VCNT, I_VCMA, hcmp1_s) + begin + for i in 0 to 7 loop + vcnt_f(i) <= I_VCNT(i) xor I_VCMA; + hcnt_f(i) <= I_HCNT(i) xor hcmp1_s; + end loop; + end process; + + p_video_addr_calc : process(I_HWSEL_FROGGER, vcnt_f, hpla) + begin + if not I_HWSEL_FROGGER then + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(7 downto 0)); + else + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(3 downto 0) & hpla(7 downto 4)); + end if; + end process; + + p_msld : process(vram_addr_sum) + begin + msld_l <= '1'; + if (vram_addr_sum(7 downto 0) = "11111111") then + msld_l <= '0'; + end if; + end process; + + p_video_addr_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_VBLANK = '1') then -- was async + vram_addr_reg <= x"00"; + elsif (vpl_load = '1') then -- vpl_l + vram_addr_reg <= vram_addr_sum(7 downto 0); + end if; + end if; + end process; + + p_vram_xor : process(vram_addr_reg, objdata, h256) + variable flip : std_logic; + begin + flip := objdata(7) and h256; + for i in 0 to 3 loop + vram_addr_xor(i) <= vram_addr_reg(i) xor flip; + end loop; + end process; + + p_vram_addr : process(vram_addr_reg, cblank_s, ld, I_CPU_ADDR, vram_addr_xor, hcnt_f) + variable match : std_logic; + begin + match := '0'; + if (vram_addr_reg(7 downto 4) = "1111") then + match := '1'; + end if; + + if (cblank_s = '0') then + ldout <= match and ld; -- blanking, sprites + else + ldout <= ld; + end if; + + if (cblank_s = '0') then -- blanking, sprites + --vram_cs <= (not I_VRAMWR_L) or (not I_VRAMRD_L); + vram_addr <= I_CPU_ADDR(9 downto 0); -- let the cpu in + else + --vram_cs <= '1'; + vram_addr <= vram_addr_reg(7 downto 4) & vram_addr_xor(3) & hcnt_f(7 downto 3); + end if; + end process; + + u_vram : work.dpram generic map (10,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_VRAMWR_L, + + addr_a_i => vram_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => vram_addr, + data_b_o => vram_dout + ); + O_VRAM_DATA <= vram_dout; + + p_object_ram_addr : process(h256, I_HCMA, objdata, I_HCNT, hcnt_f, I_CPU_ADDR, I_OBJEN_L) + begin + -- I believe the object ram can only be written during vblank + + if (h256 = '0') then + hcmp2_s <= I_HCMA; + else + hcmp2_s <= objdata(6); + end if; + + if (I_OBJEN_L = '0') then + obj_addr <= I_CPU_ADDR(7 downto 0); + else + obj_addr(7) <= '0'; + obj_addr(6) <= h256; + + -- A + if (h256 = '0') then -- normal + obj_addr(5) <= hcnt_f(7); --128h'; + else -- sprite + obj_addr(5) <= hcnt_f(3) and I_HCNT(1);-- 8h' and 2h; + end if; + + obj_addr(4 downto 2) <= hcnt_f(6 downto 4); + + if (h256 = '0') then -- normal + obj_addr(1) <= hcnt_f(3); --8h' + obj_addr(0) <= I_HCNT(2); --4h + else + obj_addr(1) <= I_HCNT(2); --4h + obj_addr(0) <= I_HCNT(1); --2h + end if; + + end if; + end process; + + u_object_ram : work.dpram generic map (8,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_OBJRAMWR_L, + + addr_a_i => obj_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => obj_addr, + data_b_o => hpla + ); + + p_objdata_regs : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (col_load = '1') then -- colour load + col_reg <= hpla(2 downto 0); + end if; + + if (objdata_load = '1') then -- sprite load + objdata <= hpla; + end if; + + if (I_VBLANK = '1') then -- was async + missile_reg_l <= '1'; + elsif (missile_load = '1') then + missile_reg_l <= msld_l; + end if; + end if; + end process; + + p_obj_rom_addr : process(h256, vram_addr_xor, vram_dout, objdata, I_HCNT) + begin + obj_rom_addr( 2 downto 0) <= vram_addr_xor(2 downto 0); + if (h256 = '0') then + -- a + obj_rom_addr(10 downto 3) <= vram_dout; -- background objects + else + obj_rom_addr(10 downto 3) <= objdata(5 downto 0) & vram_addr_xor(3) & (objdata(6) xor I_HCNT(3)); -- sprites + end if; + end process; + + obj_rom0 : entity work.ROM_OBJ_0 -- 5H + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_0_dout); + obj_rom1 : entity work.ROM_OBJ_1 -- 5F + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_1_dout); + + p_obj_rom_shift : process + variable obj_rom_0_dout_s : std_logic_vector(7 downto 0); + begin + wait until rising_edge (CLK); + if not I_HWSEL_FROGGER then + obj_rom_0_dout_s := obj_rom_0_dout; + else -- swap bits 0 and 1 + obj_rom_0_dout_s := obj_rom_0_dout(7 downto 2) & obj_rom_0_dout(0) & obj_rom_0_dout(1); + end if; + + if (ENA = '1') then + case shift_sel is + when "00" => null; -- do nothing + + when "01" => shift_reg_1 <= '0' & shift_reg_1(7 downto 1); -- right + shift_reg_0 <= '0' & shift_reg_0(7 downto 1); + + when "10" => shift_reg_1 <= shift_reg_1(6 downto 0) & '0'; -- left + shift_reg_0 <= shift_reg_0(6 downto 0) & '0'; + + when "11" => shift_reg_1 <= obj_rom_1_dout (7 downto 0); -- load + shift_reg_0 <= obj_rom_0_dout_s(7 downto 0); + when others => null; + end case; + end if; + end process; + + p_obj_rom_shift_sel : process(hcmp2, ldout, shift_reg_1, shift_reg_0) + begin + if (hcmp2 = '0') then + + shift_sel(1) <= '1'; + shift_sel(0) <= ldout; + shift_op(1) <= shift_reg_1(7); + shift_op(0) <= shift_reg_0(7); + else + + shift_sel(1) <= ldout; + shift_sel(0) <= '1'; + shift_op(1) <= shift_reg_1(0); + shift_op(0) <= shift_reg_0(0); + end if; + end process; + + p_video_out_logic : process(shift_op, cd, gr, gc) + variable vidon : std_logic; + begin + vidon := shift_op(0) or shift_op(1); + + if (gr(1 downto 0) = "00") then + vid(1 downto 0) <= shift_op(1 downto 0); + else + vid(1 downto 0) <= gr(1 downto 0); + end if; + + if (gc(2 downto 0) = "000") and (vidon = '1') then + col(2 downto 0) <= cd(2 downto 0); + else + col(2 downto 0) <= gc(2 downto 0); + end if; + end process; + + p_shell_ld : process(ld, h256, I_HCNT, missile_reg_l) + begin + sld_l <= '1'; + if (ld = '1') and (h256 = '1') and (I_HCNT(3) = '1') then + if (missile_reg_l = '0') and (I_HCNT(6 downto 4) /= "111") then + sld_l <= '0'; + end if; + end if; + + end process; + + p_shell_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + if (sld_l = '0') then + shell_cnt <= hpla; + elsif (cblank_l = '1') then + shell_cnt <= shell_cnt + "1"; + else + shell_cnt <= shell_cnt; + end if; + + if (sld_l = '0') then + shell_ena <= '1'; + elsif (shell = '1') then + shell_ena <= '0'; + end if; + end if; + end process; + + p_shell_op : process(shell_cnt, shell_ena) + begin + -- note how T input is from QD on the bottom counter + -- we get a rc from xF8 to XFF + -- so the shell is set at count xFA (rc and bit 1) + shell <= '0'; + if (shell_cnt = x"F8") then -- minus 2 as delay wrong + shell <= shell_ena; + end if; + end process; + + p_cntr_cnt : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (cntr_clr = '1') and (h256_l_s = '0') then -- async + cntr_addr <= (others => '0'); + elsif (cntr_load = '1') then + cntr_addr <= hpla(7 downto 0); + else + cntr_addr <= cntr_addr + "1"; + end if; + end if; + end process; + + p_cntr_addr : process(cntr_addr, hcmp1) + begin + cntr_addr_xor(10 downto 8) <= (others => '0'); + for i in 0 to 7 loop + cntr_addr_xor(i) <= cntr_addr(i) xor hcmp1; + end loop; + end process; + + p_sprite_sel : process(h256_l_s, cntr_addr_xor) + begin + sprite_sel <= '0'; + if (h256_l_s = '0') and (cntr_addr_xor(7 downto 4) /= "0000") then + sprite_sel <= '1'; + end if; + end process; + + p_sprite_write : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- delay 1 clock + sprite_ram_ip <= (others => '0'); + if (sprite_sel = '1') then + sprite_ram_ip(4 downto 2) <= col(2 downto 0); + sprite_ram_ip(1 downto 0) <= vid(1 downto 0); + end if; + + sprite_ram_waddr <= cntr_addr_xor; + end if; + end process; + + u_sprite_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => '1', + + addr_a_i => sprite_ram_waddr, + data_a_i => sprite_ram_ip, + + clk_b_i => clk, + addr_b_i => cntr_addr_xor, + data_b_o => sprite_ram_op + ); + + gc(2 downto 0) <= sprite_ram_op(4 downto 2); + gr(1 downto 0) <= sprite_ram_op(1 downto 0); + + p_video_out_reg : process + variable vidout_l_int : std_logic; + begin + wait until rising_edge(CLK); + -- register all objects to match increased video delay + if (ENA = '1') then + star_shift_t1 <= star_shift; + + if (cblank_l = '0') then + -- logic around the clr workes out as a sync reset + obj_video_out_reg <= (others => '0'); + shell_reg <= '0'; + frogger_blue_out_reg <= '0'; + star_out_reg <= '0'; + pout1_reg <= '0'; + else + + obj_video_out_reg(4 downto 2) <= col(2 downto 0); + obj_video_out_reg(1 downto 0) <= vid(1 downto 0); + vidout_l <= not(vid(1) or vid(0)); + -- probably wider than the original, we must be a whole 6MHz clock here or the scan-doubler will loose it. + shell_reg <= shell; + frogger_blue_out_reg <= frogger_blue; + + star_out_reg <= '0'; + if (star_shift(7 downto 0) = x"FF") and (star_on = '1') then + star_out_reg <= (vcnt_f(0) xor hcnt_f(3)) and (not star_shift(16)); + end if; + + pout1_reg <= I_POUT1; + + end if; + end if; + end process; + +-- Non BRAM (LUT) Version +-- col_rom : entity work.ROM_LUT +-- port map( +-- ADDR => obj_video_out_reg(4 downto 0), +-- DATA => obj_lut_out +-- ); + +-- BRAM Version + col_rom : entity work.ROM_LUT + port map( + CLK => CLK, + ADDR => obj_video_out_reg(4 downto 0), + DATA => obj_lut_out + ); + + p_col_rom_ce : process + variable video : array_3x5; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + video(0)(4) := '0'; + video(1)(4) := '0'; + video(2)(4) := '0'; + video(0)(3) := '0'; -- b + video(1)(3) := '0'; -- g + video(2)(3) := '0'; -- r + + if (vidout_l = '0') then -- cs_l on col rom + + video(0)(2 downto 0) := obj_lut_out(7 downto 6) & '0'; + video(1)(2 downto 0) := obj_lut_out(5 downto 3); + video(2)(2 downto 0) := obj_lut_out(2 downto 0); + else + video(0)(2 downto 0) := "000"; + video(1)(2 downto 0) := "000"; + video(2)(2 downto 0) := "000"; + end if; + -- + -- end of direct assigns + -- + if I_HWSEL_FROGGER then + if (frogger_blue_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + "00010"; + end if; + end if; + + -- add stars, background and video + if not I_HWSEL_FROGGER then + if (star_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ( '0' & star_shift_t1(13 downto 12) & "00"); + video(1) := video(1) + ( '0' & star_shift_t1(11 downto 10) & "00"); + video(2) := video(2) + ( '0' & star_shift_t1( 9 downto 8) & "00"); + end if; + + if (pout1_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ("00011"); + end if; + end if; + -- check for clip + for i in 0 to 2 loop + if video(i)(4) = '1' or video(i)(3) = '1' then + video(i)(2 downto 0) := (others => '1'); + end if; + end loop; + + O_VIDEO_B <= video(0)(2 downto 0) & video(0)(2); + O_VIDEO_G <= video(1)(2 downto 0) & video(1)(2); + O_VIDEO_R <= video(2)(2 downto 0) & video(2)(2); + end if; + end process; + + p_frogger_blue_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_HCNT(7 downto 0) = x"87") then + frogger_blue_reg <= '1'; + elsif (I_HCNT(7 downto 0) = x"07") then + frogger_blue_reg <= '0'; + end if; + end if; + end process; + frogger_blue <= not (frogger_blue_reg xor I_HCMA); + + p_stars_timer : process + begin + wait until rising_edge(CLK); + -- 555 period 0.8316 seconds + -- ~ 4DF 666 + if (ENA = '1') then + if (star_cnt_div(22 downto 17) = "100111") then + star_cnt_div <= (others => '0'); + star_cnt <= star_cnt + "1"; + else + star_cnt_div <= star_cnt_div + "1"; + end if; + end if; + end process; + + p_stars_demux : process(star_cnt, I_VCNT, star_shift) + begin + case star_cnt is + when "00" => star_on <= star_shift(8); + when "01" => star_on <= star_shift(10); + when "10" => star_on <= I_VCNT(1); + when "11" => star_on <= '1'; + when others => null; + end case; + end process; + + p_stars : process + variable star_ena : std_logic; + variable star_shift_ena : std_logic; + variable fb : std_logic; + variable star_clear : std_logic; + begin + wait until rising_edge(CLK); + -- stars clocked off 12 MHz clock + star_ena := ENA_12 and (not I_VSYNC) and h256_l_s; + + if (ENA = '1') and (I_VSYNC = '1') then + star_reg_1 <= '0'; + star_reg_2 <= '0'; + elsif (star_ena = '1') then + star_reg_1 <= '1'; + star_reg_2 <= star_reg_1; + end if; + + star_shift_ena := (star_reg_2 or I_HCMA) and star_ena; + + star_clear := I_STARSON and (not I_VBLANK); + + fb := (not star_shift(16)) xor star_shift(4); + if (star_clear = '0') then + star_shift <= (others => '0'); + elsif (star_shift_ena = '1') then + star_shift(16 downto 0) <= star_shift(15 downto 0) & fb; + end if; + end process; + +end RTL; diff --git a/Arcade/Scramble Hardware/Amidar_MiST/rtl/video_mixer.sv b/Arcade/Scramble Hardware/Amidar_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Scramble Hardware/Amidar_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Scramble Hardware/Frogger_MiST/Frogger.qpf b/Arcade/Scramble Hardware/Frogger_MiST/Frogger.qpf new file mode 100644 index 00000000..72d664b7 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/Frogger.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Frogger" diff --git a/Arcade/Scramble Hardware/Frogger_MiST/Frogger.qsf b/Arcade/Scramble Hardware/Frogger_MiST/Frogger.qsf new file mode 100644 index 00000000..3486921b --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/Frogger.qsf @@ -0,0 +1,171 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 05:08:48 November 15, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Arcade-Frogger_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY FroggerMist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ---------------------- +# start ENTITY(Scramble) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Scramble) +# -------------------- +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_LUT.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd +set_global_assignment -name VHDL_FILE rtl/i82c55.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VERILOG_FILE rtl/build_id.v +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd +set_global_assignment -name VHDL_FILE rtl/scramble.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/FroggerMist.sv +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Frogger_MiST/Frogger.srf b/Arcade/Scramble Hardware/Frogger_MiST/Frogger.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/Frogger.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Scramble Hardware/Frogger_MiST/README.txt b/Arcade/Scramble Hardware/Frogger_MiST/README.txt new file mode 100644 index 00000000..aa348b1d --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/README.txt @@ -0,0 +1,22 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Frogger port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Frogger hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- diff --git a/Arcade/Scramble Hardware/Frogger_MiST/Release/Frogger.rbf b/Arcade/Scramble Hardware/Frogger_MiST/Release/Frogger.rbf new file mode 100644 index 00000000..9c55eb65 Binary files /dev/null and b/Arcade/Scramble Hardware/Frogger_MiST/Release/Frogger.rbf differ diff --git a/Arcade/Scramble Hardware/Frogger_MiST/clean.bat b/Arcade/Scramble Hardware/Frogger_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv b/Arcade/Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv new file mode 100644 index 00000000..5caf3f1b --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/FroggerMist.sv @@ -0,0 +1,201 @@ +//============================================================================ +// Arcade: Frogger +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module FroggerMist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Frogger;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6p, ce_6n, ce_12, ce_1p79; +always @(negedge clk_sys) begin + reg [1:0] div = 0; + reg [3:0] div179 = 0; + + div <= div + 1'd1; + + ce_12 <= div[0]; + ce_6p <= div[0] & ~div[1]; + ce_6n <= div[0] & div[1]; + + ce_1p79 <= 0; + div179 <= div179 - 1'd1; + if(!div179) begin + div179 <= 13; + ce_1p79 <= 1; + end +end + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +wire hsync,vsync; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [3:0] r,b,g; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6p), + .ce_pix_actual(ce_6p), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r[1:0]}), + .G({g,g[1:0]}), + .B({b,b[1:0]}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +scramble_top scramble +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .button_in(~{m_start2, m_fire, m_coin, m_start1, m_right, m_left, m_down, m_up}), + + .RESET(status[0] | status[6] | buttons[1]), + .clk(clk_sys), + .ena_12(ce_12), + .ena_6(ce_6p), + .ena_6b(ce_6n), + .ena_1_79(ce_1p79) +); +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule + diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd new file mode 100644 index 00000000..32535505 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/MULT18X18.vhd @@ -0,0 +1,53 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY MULT18X18 IS + PORT + ( + A : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); +END MULT18X18; + + +ARCHITECTURE SYN OF mult18x18 IS + + COMPONENT lpm_mult + GENERIC ( + lpm_hint : STRING; + lpm_representation : STRING; + lpm_type : STRING; + lpm_widtha : NATURAL; + lpm_widthb : NATURAL; + lpm_widthp : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + lpm_mult_component : lpm_mult + GENERIC MAP ( + lpm_hint => "MAXIMIZE_SPEED=5", + lpm_representation => "SIGNED", + lpm_type => "LPM_MULT", + lpm_widtha => 18, + lpm_widthb => 18, + lpm_widthp => 36 + ) + PORT MAP ( + dataa => A, + datab => B, + result => P + ); + +END SYN; + diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd new file mode 100644 index 00000000..57972287 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_LUT.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_LUT is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_LUT is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"07",X"C0",X"F6",X"00",X"F6",X"5E",X"5C",X"00",X"F0",X"3C",X"D7",X"00",X"C0",X"C4",X"07", + X"00",X"31",X"17",X"F0",X"00",X"31",X"C7",X"3F",X"00",X"F6",X"07",X"31",X"00",X"3F",X"07",X"C4"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd new file mode 100644 index 00000000..8a6388bf --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C1",X"81",X"85",X"7C",X"38",X"00",X"01",X"01",X"FD",X"FD",X"41",X"01",X"00",X"00", + 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00000000..745ead46 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_OBJ_1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + 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X"00",X"00",X"00",X"00",X"7F",X"00",X"00",X"00",X"02",X"02",X"02",X"02",X"FE",X"00",X"00",X"00", + X"00",X"00",X"00",X"60",X"61",X"00",X"06",X"07",X"00",X"00",X"00",X"00",X"C0",X"78",X"3C",X"3C", + X"07",X"06",X"00",X"21",X"20",X"00",X"00",X"00",X"3C",X"3C",X"78",X"C0",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd new file mode 100644 index 00000000..166a14d2 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_PGM.vhd @@ -0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"3A",X"00",X"40",X"FE",X"55",X"CA",X"01",X"40",X"3A",X"00",X"88",X"31",X"00",X"88",X"C3",X"B1", + X"02",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"4F",X"3A",X"FE",X"83",X"B7",X"C8",X"E5",X"21", + X"00",X"83",X"34",X"7E",X"6F",X"71",X"E1",X"C9",X"1A",X"77",X"7D",X"D6",X"20",X"6F",X"30",X"01", + X"25",X"13",X"10",X"F4",X"C9",X"FF",X"FF",X"FF",X"11",X"10",X"20",X"21",X"00",X"A8",X"06",X"20", + X"73",X"23",X"10",X"FC",X"0E",X"15",X"10",X"FE",X"0D",X"20",X"FB",X"15",X"20",X"F0",X"C9",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F5",X"E5",X"D5",X"C5",X"DD",X"E5",X"FD",X"E5",X"3A",X"00", + X"88",X"AF",X"32",X"08",X"B8",X"CD",X"00",X"3E",X"21",X"07",X"80",X"11",X"07",X"B0",X"7E",X"12", + X"2C",X"1C",X"06",X"1C",X"7E",X"0F",X"0F",X"0F",X"0F",X"12",X"2C",X"1C",X"7E",X"12",X"2C",X"1C", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd new file mode 100644 index 00000000..257b776b --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"05",X"00",X"22",X"00",X"40",X"C3",X"0B",X"02",X"D3",X"80",X"78",X"D3",X"40",X"CA",X"FF",X"FF", + X"C3",X"B7",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"7C",X"01",X"FF",X"FF",X"FF",X"FF",X"FF", + X"C3",X"C7",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"3C",X"01",X"FF",X"FF",X"FF",X"FF",X"FF", + X"C3",X"60",X"01",X"3D",X"FF",X"CA",X"FF",X"FF",X"08",X"DA",X"22",X"6E",X"00",X"E6",X"3D",X"0D", + X"CE",X"C2",X"01",X"B7",X"28",X"2B",X"57",X"FD",X"FF",X"20",X"02",X"C7",X"E5",X"0F",X"4F",X"79", + X"AA",X"28",X"07",X"7A",X"B7",X"28",X"03",X"79",X"18",X"3E",X"79",X"E5",X"0F",X"20",X"38",X"79", + X"C5",X"11",X"07",X"07",X"07",X"CB",X"7F",X"28",X"2D",X"CB",X"BF",X"18",X"13",X"DA",X"08",X"FB", + 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X"74",X"03",X"78",X"E5",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F",X"05",X"00",X"22",X"06",X"08",X"0A"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd new file mode 100644 index 00000000..faad7684 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"5E",X"23",X"56",X"D5",X"C9",X"15",X"08",X"2F",X"08",X"45",X"08",X"62",X"08",X"62",X"08",X"62", + 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00000000..84f07cb4 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ROM/ROM_SND_2.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_2 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"91",X"8D",X"92",X"8A",X"92",X"8D",X"92",X"8A",X"92",X"8D",X"91",X"88",X"91",X"8D",X"91", + X"88",X"91",X"8F",X"94",X"FF",X"E7",X"AF",X"32",X"C8",X"42",X"3E",X"19",X"32",X"A3",X"42",X"F7", + X"C3",X"61",X"09",X"E7",X"F7",X"C9",X"DD",X"21",X"80",X"42",X"C3",X"A1",X"07",X"DD",X"21",X"88", + X"42",X"C3",X"A1",X"07",X"1F",X"0B",X"3F",X"0C",X"5F",X"05",X"B4",X"91",X"8D",X"B9",X"98",X"96", + X"B4",X"99",X"91",X"8F",X"B4",X"80",X"80",X"94",X"94",X"94",X"94",X"91",X"8F",X"8D",X"80",X"99", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv new file mode 100644 index 00000000..a87e679a --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/ScrambleMist.sv @@ -0,0 +1,201 @@ +//============================================================================ +// Arcade: Scramble +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module ScrambleMist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Scramble;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6p, ce_6n, ce_12, ce_1p79; +always @(negedge clk_sys) begin + reg [1:0] div = 0; + reg [3:0] div179 = 0; + + div <= div + 1'd1; + + ce_12 <= div[0]; + ce_6p <= div[0] & ~div[1]; + ce_6n <= div[0] & div[1]; + + ce_1p79 <= 0; + div179 <= div179 - 1'd1; + if(!div179) begin + div179 <= 13; + ce_1p79 <= 1; + end +end + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +wire hsync,vsync; +assign LED = 1; + +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,g; +wire [1:0] b; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6p), + .ce_pix_actual(ce_6p), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R(r), + .G(g), + .B(b), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; + + +scramble_top scramble +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .button_in(~{m_start2, m_fire, m_coin, m_start1, m_right, m_left, m_down, m_up}), + + .RESET(status[0] | status[6] | buttons[1]), + .clk(clk_sys), + .ena_12(ce_12), + .ena_6(ce_6p), + .ena_6b(ce_6n), + .ena_1_79(ce_1p79) +); +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/build_id.tcl b/Arcade/Scramble Hardware/Frogger_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/build_id.v b/Arcade/Scramble Hardware/Frogger_MiST/rtl/build_id.v new file mode 100644 index 00000000..629dd9aa --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171117" +`define BUILD_TIME "105138" diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/dac.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/dpram.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/hq2x.sv b/Arcade/Scramble Hardware/Frogger_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd new file mode 100644 index 00000000..0aadc7e6 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/i82c55.vhd @@ -0,0 +1,686 @@ +-- +-- A simulation model of Frogger hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity I82C55 is + port ( + + I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_CS_L : in std_logic; + I_RD_L : in std_logic; + I_WR_L : in std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_PC : in std_logic_vector(7 downto 0); + O_PC : out std_logic_vector(7 downto 0); + O_PC_OE_L : out std_logic_vector(7 downto 0); + + RESET : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + CLK : in std_logic + ); +end; + +architecture RTL of I82C55 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(I_DATA) + begin + bit_mask <= x"01"; + case I_DATA(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and I_DATA(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (I_CS_L = '0') and (I_WR_L = '0') then + case I_ADDR is + when "00" => r_porta <= I_DATA; + when "01" => r_portb <= I_DATA; + when "10" => r_portc <= I_DATA; + + when "11" => if (I_DATA(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= I_DATA; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + p_oe : process(I_CS_L, I_RD_L) + begin + O_DATA_OE_L <= '1'; + if (I_CS_L = '0') and (I_RD_L = '0') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read) + begin + O_DATA <= x"00"; -- default + --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required + case I_ADDR is + when "00" => O_DATA <= porta_read; + when "01" => O_DATA <= portb_read; + when "10" => O_DATA <= portc_read; + when "11" => O_DATA <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (I_CS_L = '0') and (I_ADDR = "00") then + porta_we <= not I_WR_L; + porta_re <= not I_RD_L; + end if; + + if (I_CS_L = '0') and (I_ADDR = "01") then + portb_we <= not I_WR_L; + portb_re <= not I_RD_L; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= I_DATA(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= I_DATA(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= I_DATA(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + O_PA <= x"FF"; -- if not driven, float high + O_PA_OE_L <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= I_PA; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_control, groupb_mode, r_portb, I_PB, portb_ipreg) + begin + O_PB <= x"FF"; -- if not driven, float high + O_PB_OE_L <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= I_PB; + else -- strobed mode + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + O_PC <= x"FF"; -- if not driven, float high + O_PC_OE_L <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + O_PC (7 downto 4) <= r_portc(7 downto 4); + O_PC_OE_L(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + O_PC (5 downto 4) <= r_portc(5 downto 4); + O_PC_OE_L(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + O_PC (7 downto 6) <= r_portc(7 downto 6); + O_PC_OE_L(7 downto 6) <= "00"; + end if; + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + O_PC (3) <= r_portc(3); + O_PC_OE_L(3) <= '0'; + end if; + -- + else -- stolen + O_PC (3) <= a_intr; + O_PC_OE_L(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + O_PC (2 downto 0) <= r_portc(2 downto 0); + O_PC_OE_L(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + O_PC (1) <= b_obf_l; + O_PC_OE_L(1) <= '0'; + else -- input + O_PC (1) <= b_ibf; + O_PC_OE_L(1) <= '0'; + end if; + O_PC (0) <= b_intr; + O_PC_OE_L(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= I_PC(6); + else -- port a input + a_stb_l <= I_PC(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= I_PC(6); + a_stb_l <= I_PC(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= I_PC(2); + else -- input + b_stb_l <= I_PC(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= I_PC(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= I_PC(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= I_PA; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= I_PB; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/keyboard.v b/Arcade/Scramble Hardware/Frogger_MiST/rtl/keyboard.v new file mode 100644 index 00000000..89f7e34e --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[1] <= ~release_btn; // Left Alt + 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/mist_io.v b/Arcade/Scramble Hardware/Frogger_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/osd.v b/Arcade/Scramble Hardware/Frogger_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/pll.qip b/Arcade/Scramble Hardware/Frogger_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/pll.v b/Arcade/Scramble Hardware/Frogger_MiST/rtl/pll.v new file mode 100644 index 00000000..1d3529bd --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/scandoubler.v b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble.vhd new file mode 100644 index 00000000..e496ae76 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble.vhd @@ -0,0 +1,587 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE is + port ( + I_HWSEL_FROGGER : in boolean; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + -- to audio board + -- + O_ADDR : out std_logic_vector(15 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + I_DATA_OE_L : in std_logic; + O_RD_L : out std_logic; + O_WR_L : out std_logic; + O_IOPC7 : out std_logic; + O_RESET_WD_L : out std_logic; + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + -- + RESET : in std_logic; -- active high + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE is + + type array_4x8 is array (0 to 3) of std_logic_vector(7 downto 0); + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal reset_wd_l : std_logic; + + -- timing decode + signal do_hsync : boolean; + signal set_vblank : boolean; + signal vsync : std_logic; + signal hsync : std_logic; + signal vblank : std_logic; + signal hblank : std_logic; + -- + -- cpu + signal cpu_ena : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal page_4to7_l : std_logic; + + signal wren : std_logic; + + signal objen_l : std_logic; + signal waen_l : std_logic; + + signal objramrd_l : std_logic; + signal vramrd_l : std_logic; + + signal select_l : std_logic; + signal objramwr_l : std_logic; + signal vramwr_l : std_logic; + + -- control reg + signal control_reg : std_logic_vector(7 downto 0); + signal intst_l : std_logic; + signal iopc7 : std_logic; + signal pout1 : std_logic; + signal starson : std_logic; + signal hcma : std_logic; + signal vcma : std_logic; + + signal pgm_rom_dout : array_4x8; + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + signal ram_ena : std_logic; + + signal vram_data : std_logic_vector(7 downto 0); + +begin + + O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + set_vblank <= (vcnt = "111101111"); -- 1EF + end process; + + p_sync : process + begin + wait until rising_edge(CLK); + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + if (ENA = '1') then + if (hcnt = "010000001") then -- 081 + hblank <= '1'; + elsif (hcnt = "011111111") then -- 0f9 + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if set_vblank then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + p_video_timing_reg : process + begin + wait until rising_edge(CLK); + -- match output delay in video module + if (ENA = '1') then + O_HSYNC <= HSYNC; + O_VSYNC <= VSYNC; + end if; + end process; + + p_cpu_ena : process(hcnt, ENA) + begin + -- cpu clocked on rising edge of 1h, late + cpu_ena <= ENA and hcnt(0); -- 1h + end process; + -- + -- video + -- + u_video : entity work.SCRAMBLE_VIDEO + port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_HCNT => hcnt, + I_VCNT => vcnt, + I_VBLANK => vblank, + I_VSYNC => vsync, + + I_VCMA => vcma, + I_HCMA => hcma, + -- + I_CPU_ADDR => cpu_addr, + I_CPU_DATA => cpu_data_out, + O_VRAM_DATA => vram_data, + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L => vramwr_l, + I_VRAMRD_L => vramrd_l, + I_OBJRAMWR_L => objramwr_l, + I_OBJRAMRD_L => objramrd_l, + I_OBJEN_L => objen_l, + -- + I_STARSON => starson, + I_POUT1 => pout1, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + -- + ENA => ENA, + ENAB => ENAB, + ENA_12 => ENA_12, + CLK => CLK + ); + + -- other cpu signals + reset_wd_l <= not RESET; -- FIX + + p_cpu_wait : process(vblank, hblank, waen_l) + begin + -- this is done a bit differently, the original had a late + -- clock to the cpu, and as mreq came out a litle early it could assert + -- wait and then gate off the write strobe to vram/objram in time. + -- + -- we are a nice synchronous system therefore we need to do this combinatorially. + -- timing is still ok. + -- + if (vblank = '1') then + cpu_wait_l <='1'; + else + cpu_wait_l <= '1'; + if (hblank = '0') and (waen_l = '0') then + cpu_wait_l <= '0'; + end if; + end if; + end process; + wren <= cpu_wait_l; + + p_cpu_int : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (intst_l = '0') then + cpu_nmi_l <= '1'; + else + if do_hsync and set_vblank then + cpu_nmi_l <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => reset_wd_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => open, + MREQ_n => cpu_mreq_l, + IORQ_n => open, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode : process(cpu_rfsh_l, cpu_rd_l, cpu_wr_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + begin + -- Scramble map + --0000-3fff ROM + --4000-47ff RAM + --4800-4bff Video RAM + --5000-50ff Object RAM + --5000-503f screen attributes + --5040-505f sprites + --5060-507f bullets + --5080-50ff unused? + + --read: + --7000 Watchdog Reset (Scramble) + --8100 IN0 + --8101 IN1 + --8102 IN2 (bits 5 and 7 used for protection check in Scramble) + + --write: + --6800-6807 control reg + --8200 To AY-3-8910 port A (commands for the audio CPU) + --8201 bit 3 = interrupt trigger on audio CPU bit 4 = AMPM (?) + --8202 protection check control? + + -- Frogger map + --0000-3fff ROM + --8000-87ff RAM + --a800-abff Video RAM + --b000-b0ff Object RAM + --b000-b03f screen attributes + --b040-b05f sprites + --b060-b0ff unused? + + --read: + --8800 Watchdog Reset + --e000 IN0 + --e002 IN1 + --e004 IN2 + cpu_int_l <= '1'; + cpu_busrq_l <= '1'; + + page_4to7_l <= '1'; + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + + if I_HWSEL_FROGGER then + cpu_int_l <= '0'; + cpu_busrq_l <= cpu_addr(15); + end if; + + if not I_HWSEL_FROGGER then + if (cpu_addr(15 downto 14) = "01") then page_4to7_l <= '0'; end if; + else + if (cpu_addr(15 downto 14) = "10") then page_4to7_l <= '0'; end if; + end if; + end if; + + end process; + + p_mem_decode2 : process(I_HWSEL_FROGGER, cpu_addr, page_4to7_l, cpu_rfsh_l, cpu_rd_l, cpu_wr_l, wren) + begin + waen_l <= '1'; + objen_l <= '1'; + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "001") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objen_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "101") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objen_l <= '0'; end if; + end if; + end if; + + -- read decode + vramrd_l <= '1'; + objramrd_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "001") then vramrd_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramrd_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "101") then vramrd_l <= '0'; end if; + end if; + end if; + -- write decode + vramwr_l <= '1'; + objramwr_l <= '1'; + select_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "001") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "101") then select_l <= '0'; end if; -- control reg + end if; + else + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "101") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "111") then select_l <= '0'; end if; -- control reg + end if; + end if; + end process; + + p_control_reg : process + variable addr : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- scramble + --6801 interrupt enable + --6802 coin counter + --6803 ? (POUT1) + --6804 stars on + --6805 ? (POUT2) + --6806 screen vertical flip + --6807 screen horizontal flip + if not I_HWSEL_FROGGER then + addr := cpu_addr(2 downto 0); + else + addr := cpu_addr(4 downto 2); + end if; + + dec := "00000000"; + if (select_l = '0') then + case addr(2 downto 0) is + when "000" => dec := "00000001"; + when "001" => dec := "00000010"; + when "010" => dec := "00000100"; + when "011" => dec := "00001000"; + when "100" => dec := "00010000"; + when "101" => dec := "00100000"; + when "110" => dec := "01000000"; + when "111" => dec := "10000000"; + when others => null; + end case; + end if; + + if (reset_wd_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (dec(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_control_reg_assign : process(control_reg, I_HWSEL_FROGGER) + begin + if not I_HWSEL_FROGGER then + -- Scramble + intst_l <= control_reg(1); + iopc7 <= control_reg(2); + pout1 <= control_reg(3); + starson <= control_reg(4); + hcma <= control_reg(6); + vcma <= control_reg(7); + else + intst_l <= control_reg(2); + iopc7 <= control_reg(6); + pout1 <= control_reg(7); + starson <= '0'; + hcma <= control_reg(4); + vcma <= control_reg(3); + end if; + end process; + -- + -- + -- roms / rams + pgm_rom : entity work.ROM_PGM + port map (CLK => CLK, ADDR => cpu_addr(13 downto 0), DATA => rom_dout); +-- pgm_rom01 : entity work.ROM_PGM_01 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(0)); +-- pgm_rom23 : entity work.ROM_PGM_23 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(1)); +-- pgm_rom45 : entity work.ROM_PGM_45 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(2)); +-- pgm_rom56 : entity work.ROM_PGM_67 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(3)); + +-- p_rom_mux : process(cpu_addr, pgm_rom_dout) +-- begin +-- rom_dout <= (others => '0'); +-- case cpu_addr(13 downto 12) is +-- when "00" => rom_dout <= pgm_rom_dout(0); +-- when "01" => rom_dout <= pgm_rom_dout(1); +-- when "10" => rom_dout <= pgm_rom_dout(2); +-- when "11" => rom_dout <= pgm_rom_dout(3); +-- when others => null; +-- end case; +-- end process; + + u_cpu_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => ram_ena and (not cpu_wr_l), + + addr_a_i => cpu_addr(10 downto 0), + data_a_i => cpu_data_out, + + clk_b_i => clk, + addr_b_i => cpu_addr(10 downto 0), + data_b_o => ram_dout + ); + + p_ram_ctrl : process(cpu_addr, page_4to7_l) + begin + ram_ena <= '0'; + if (page_4to7_l = '0') and (cpu_addr(13 downto 11) = "000") then + ram_ena <= '1'; + end if; + end process; + + p_cpu_data_in_mux : process(I_HWSEL_FROGGER, cpu_addr, cpu_rd_l, cpu_mreq_l, cpu_rfsh_l, ram_dout, rom_dout, vramrd_l, vram_data, I_DATA_OE_L, I_DATA ) + variable ram_addr : std_logic_vector(1 downto 0); + begin + + if not I_HWSEL_FROGGER then + ram_addr := "01"; + else + ram_addr := "10"; + end if; + + cpu_data_in <= (others => '0'); + if (vramrd_l = '0') then + cpu_data_in <= vram_data; + -- + elsif (I_DATA_OE_L = '0') then + cpu_data_in <= I_DATA; + -- + elsif (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(15 downto 14) = "00") and (cpu_rd_l = '0') and (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + cpu_data_in <= rom_dout; + -- + elsif (cpu_addr(15 downto 14) = ram_addr) then + if (cpu_addr(13 downto 11) = "000") and (cpu_rd_l = '0') then + cpu_data_in <= ram_dout; + else + cpu_data_in <= x"FF"; + end if; + end if; + else + cpu_data_in <= x"FF"; + end if; + + end process; + + -- to audio + O_ADDR <= cpu_addr; + O_DATA <= cpu_data_out; + O_RD_L <= cpu_rd_l; + O_WR_L <= cpu_wr_l; + O_IOPC7 <= iopc7; + O_RESET_WD_L <= reset_wd_l; + +end RTL; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd new file mode 100644 index 00000000..82214404 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_audio.vhd @@ -0,0 +1,842 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_AUDIO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_ADDR : in std_logic_vector(15 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + O_DATA_OE_L : out std_logic; + -- + I_RD_L : in std_logic; + I_WR_L : in std_logic; + I_IOPC7 : in std_logic; + -- + O_AUDIO : out std_logic_vector( 9 downto 0); + -- + I_1P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_SERVICE : in std_logic; + I_COIN1 : in std_logic; + I_COIN2 : in std_logic; + O_COIN_COUNTER : out std_logic; + -- + I_DIP : in std_logic_vector( 5 downto 1); + -- + I_RESET_L : in std_logic; + ENA : in std_logic; -- 6 MHz + ENA_1_79 : in std_logic; -- 1.78975 MHz + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE_AUDIO is + + signal reset : std_logic; + signal cpu_ena : std_logic; + signal cpu_ena_gated : std_logic; + -- + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + -- + signal ram_cs : std_logic; + signal rom_oe : std_logic; + signal filter_load : std_logic; + signal filter_reg : std_logic_vector(11 downto 0); + -- + signal cpu_rom0_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom1_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom2_dout : std_logic_vectoR(7 downto 0); + signal rom_active : std_logic; + + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + -- + signal i8255_addr : std_logic_vector(1 downto 0); + signal i8255_1D_data : std_logic_vector(7 downto 0); + signal i8255_1D_data_oe_l : std_logic; + signal i8255_1D_cs_l : std_logic; + signal i8255_1D_pa_out : std_logic_vector(7 downto 0); + signal i8255_1D_pb_out : std_logic_vector(7 downto 0); + -- + signal i8255_1E_data : std_logic_vector(7 downto 0); + signal i8255_1E_data_oe_l : std_logic; + signal i8255_1E_cs_l : std_logic; + signal i8255_1E_pa : std_logic_vector(7 downto 0); + signal i8255_1E_pb : std_logic_vector(7 downto 0); + signal i8255_1E_pc : std_logic_vector(7 downto 0); + + -- security + signal net_1e10_i : std_logic; + signal net_1e12_i : std_logic; + signal xb : std_logic_vector(7 downto 0); + signal xbo : std_logic_vector(7 downto 0); + + signal audio_div_cnt : std_logic_vector( 8 downto 0) := (others => '0'); + signal ls90_op : std_logic_vector(3 downto 0); + signal ls90_clk : std_logic; + signal ls90_cnt : std_logic_vector( 3 downto 0) := (others => '0'); + -- ym2149 3C + signal ym2149_3C_dv : std_logic_vector(7 downto 0); + signal ym2149_3C_oe_l : std_logic; + signal ym2149_3C_bdir : std_logic; + signal ym2149_3C_bc2 : std_logic; + signal ym2149_3C_bc1 : std_logic; + signal ym2149_3C_audio : std_logic_vector(7 downto 0); + signal ym2149_3C_chan : std_logic_vector(1 downto 0); + signal ym2149_3C_chan_t1 : std_logic_vector(1 downto 0); + -- + -- ym2149 3D + signal ym2149_3D_dv : std_logic_vector(7 downto 0); + signal ym2149_3D_oe_l : std_logic; + signal ym2149_3D_bdir : std_logic; + signal ym2149_3D_bc2 : std_logic; + signal ym2149_3D_bc1 : std_logic; + signal ym2149_3D_audio : std_logic_vector(7 downto 0); + signal ym2149_3D_chan : std_logic_vector(1 downto 0); + signal ym2149_3D_chan_t1 : std_logic_vector(1 downto 0); + signal ym2149_3D_ioa_in : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_out : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_oe_l : std_logic; + signal ym2149_3D_iob_in : std_logic_vector(7 downto 0); + -- + signal ampm : std_logic; + signal sint : std_logic; + signal sint_t1 : std_logic; + -- + signal audio_3C_mix : std_logic_vector(9 downto 0); + signal audio_3C_final : std_logic_vector(9 downto 0); + signal audio_3D_mix : std_logic_vector(9 downto 0); + signal audio_3D_final : std_logic_vector(9 downto 0); + signal audio_final : std_logic_vector(10 downto 0); + + signal security_count : std_logic_vector(2 downto 0); + signal rd_l_t1 : std_logic; + -- filters + signal ym2149_3C_k : std_logic_vector(16 downto 0); + signal ym2149_3D_k : std_logic_vector(16 downto 0); + signal audio_in_m_out_3C : std_logic_vector(17 downto 0); + signal audio_in_m_out_3D : std_logic_vector(17 downto 0); + signal audio_mult_3C : std_logic_vector(35 downto 0); + signal audio_mult_3D : std_logic_vector(35 downto 0); + + + + type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0); + constant K_Filter : array_4of17 := ('0' & x"00A3", + '0' & x"00C6", + '0' & x"039D", + '1' & x"0000" ); + + type filter_pipe is array (3 downto 0) of std_logic_vector(17 downto 0); + signal ym2149_3C_audio_pipe : filter_pipe; + signal ym2149_3D_audio_pipe : filter_pipe; + -- LP filter out = in.k + out_t1.(1-k) + -- + -- = (in-out_t1).k + out_t1 + -- + -- using + -- -(Ts.2.PI.Fc) + -- k = 1-e + -- + -- sampling freq = 1.79 MHz + -- + -- cut off freqs bit 0 1 + -- + --0.267uf ~ 713 Hz 1 1 0.00249996 x 00A3 + --0.220uf ~ 865 Hz 1 0 0.00303210 x 00C6 + --0.047uf ~ 4050 Hz 0 1 0.01411753 x 039D + -- 0 0 x10000 + +begin + -- scramble + --0000-1fff ROM + --8000-83ff RAM + + -- frogger + --0000-17ff ROM + --4000-43ff RAM + + cpu_ena <= '1'; -- run at audio clock speed + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + cpu_wait_l <= '1'; + -- + cpu_ena_gated <= ENA_1_79 and cpu_ena; + u_cpu : entity work.T80sed + port map ( + RESET_n => I_RESET_L, + CLK_n => CLK, + CLKEN => cpu_ena_gated, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + p_cpu_int : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + cpu_int_l <= '1'; + sint_t1 <= '0'; + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + sint_t1 <= sint; + + if (cpu_m1_l = '0') and (cpu_iorq_l = '0') then + cpu_int_l <= '1'; + elsif (sint = '0') and (sint_t1 = '1') then + cpu_int_l <= '0'; + end if; + end if; + end if; + end process; + + p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + variable decode : std_logic; + begin + if not I_HWSEL_FROGGER then + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(12)); + else + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(14) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(13) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(13)); + end if; + + rom_oe <= '0'; + if not I_HWSEL_FROGGER then + if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + else + if (cpu_addr(14) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + end if; + + end process; + + u_rom_5c : entity work.ROM_SND_0 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom0_dout + ); + + u_rom_5d : entity work.ROM_SND_1 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom1_dout + ); + + u_rom_5e : entity work.ROM_SND_2 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom2_dout + ); + + p_rom_mux : process(I_HWSEL_FROGGER, cpu_rom0_dout, cpu_rom1_dout, cpu_rom2_dout, cpu_addr, rom_oe) + variable rom_oe_decode : std_logic; + variable cpu_rom0_dout_s : std_logic_vector(7 downto 0); + begin + if not I_HWSEL_FROGGER then + cpu_rom0_dout_s := cpu_rom0_dout; + else -- swap bits 0 and 1 + cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1); + end if; + + rom_dout <= (others => '0'); + rom_oe_decode := '0'; + case cpu_addr(13 downto 11) is + when "000" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1'; + when "001" => rom_dout <= cpu_rom1_dout; rom_oe_decode := '1'; + when "010" => rom_dout <= cpu_rom2_dout; rom_oe_decode := '1'; + when others => null; + end case; + + rom_active <= '0'; + if (rom_oe = '1') then + rom_active <= rom_oe_decode; + end if; + end process; + + u_ram_6c_6d : work.dpram generic map (10,8) + port map + ( + addr_a_i => cpu_addr(9 downto 0), + data_a_i => cpu_data_out, + clk_b_i => clk, + addr_b_i => cpu_addr(9 downto 0), + data_b_o => ram_dout, + we_i => ram_cs and (not cpu_wr_l), + en_a_i => ENA_1_79, + clk_a_i => clk + ); + + p_cpu_data_mux : process(rom_dout, rom_active, ram_dout, ym2149_3C_oe_l, ym2149_3C_dv, ym2149_3D_oe_l, ym2149_3D_dv, ram_cs, cpu_wr_l) + begin + if (rom_active = '1') then + cpu_data_in <= rom_dout; + elsif (ram_cs = '1') and (cpu_wr_l = '1') then + cpu_data_in <= ram_dout; + elsif (ym2149_3C_oe_l = '0') then + cpu_data_in <= ym2149_3C_dv; + elsif (ym2149_3D_oe_l = '0') then + cpu_data_in <= ym2149_3D_dv; + else + cpu_data_in <= (others => '1'); -- float high + end if; + end process; + + p_filter_reg : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + if (filter_load = '1') then + filter_reg <= cpu_addr(11 downto 0); + end if; + end if; + end process; + + p_8255_decode : process(I_RESET_L, I_ADDR, I_HWSEL_FROGGER) + begin + reset <= not I_RESET_L; + i8255_1D_cs_l <= '1'; + i8255_1E_cs_l <= '1'; + + if not I_HWSEL_FROGGER then + -- the interface one + if (I_ADDR(9) = '1') and (I_ADDR(15) = '1') then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(8) = '1') and (I_ADDR(15) = '1') then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(1 downto 0); + else + -- the interface one + if (I_ADDR(12) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(13) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(2 downto 1); + end if; + end process; + + p_ym_decode : process(cpu_rd_l, cpu_wr_l, cpu_iorq_l, cpu_addr, I_HWSEL_FROGGER) + variable rd_3c : std_logic; + variable wr_3c : std_logic; + variable ad_3c : std_logic; + -- + variable rd_3d : std_logic; + variable wr_3d : std_logic; + variable ad_3d : std_logic; + begin + + --bdir bc2 bc1 + -- 0 0 0 nop + -- 0 0 1 addr latch < WR_L AV4 / AV6 + -- 0 1 0 nop + -- 0 1 1 data read < RD_L AV5 / AV7 + + -- 1 0 0 addr latch + -- 1 0 1 nop + -- 1 1 0 data write < WR_L AV5 / AV7 + -- 1 1 1 addr latch + + + if not I_HWSEL_FROGGER then + rd_3c := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(5); + wr_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(5); + ad_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(4); + else + rd_3c := '0'; + wr_3c := '0'; + ad_3c := '0'; + end if; + + ym2149_3C_bdir <= wr_3c; + ym2149_3C_bc2 <= rd_3c or wr_3c; + ym2149_3C_bc1 <= rd_3c or ad_3c; + + + if not I_HWSEL_FROGGER then + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(7); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + else + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(6); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + end if; + + ym2149_3D_bdir <= wr_3d; + ym2149_3D_bc2 <= rd_3d or wr_3d; + ym2149_3D_bc1 <= rd_3d or ad_3d; + + end process; + + i8255_1E_pa(7) <= I_COIN1; + i8255_1E_pa(6) <= I_COIN2; + i8255_1E_pa(5) <= I_1P_CTRL(3); -- left + i8255_1E_pa(4) <= I_1P_CTRL(2); -- right + i8255_1E_pa(3) <= I_1P_CTRL(4); -- shoot1 + i8255_1E_pa(2) <= I_SERVICE; + i8255_1E_pa(1) <= I_1P_CTRL(5); -- shoot2 + i8255_1E_pa(0) <= I_2P_CTRL(1); -- up + + i8255_1E_pb(7) <= I_1P_CTRL(6); -- start + i8255_1E_pb(6) <= I_2P_CTRL(6); -- start + i8255_1E_pb(5) <= I_2P_CTRL(3); -- left + i8255_1E_pb(4) <= I_2P_CTRL(2); -- right + i8255_1E_pb(3) <= I_2P_CTRL(4); -- shoot1 + i8255_1E_pb(2) <= I_2P_CTRL(5); -- shoot2 + i8255_1E_pb(1) <= I_DIP(1); + i8255_1E_pb(0) <= I_DIP(2); + + i8255_1E_pc(7) <= net_1e10_i; + i8255_1E_pc(6) <= I_1P_CTRL(0); -- down + i8255_1E_pc(5) <= net_1e12_i; + i8255_1E_pc(4) <= I_1P_CTRL(1); -- up + i8255_1E_pc(3) <= I_DIP(3); + i8255_1E_pc(2) <= I_DIP(4); + i8255_1E_pc(1) <= I_DIP(5); + i8255_1E_pc(0) <= I_2P_CTRL(0); -- down + O_COIN_COUNTER <= not I_IOPC7; -- open drain actually + + -- + -- PIA CHIPS + -- + u_i8255_1D : entity work.I82C55 -- bus interface + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1D_data, + O_DATA_OE_L => i8255_1D_data_oe_l, + + I_CS_L => i8255_1D_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1D_pa_out, + O_PA => i8255_1D_pa_out, + O_PA_OE_L => open, + + I_PB => i8255_1D_pb_out, + O_PB => i8255_1D_pb_out, + O_PB_OE_L => open, + + I_PC => xbo, + O_PC => xb, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + u_i8255_1E : entity work.I82C55 -- push button + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1E_data, + O_DATA_OE_L => i8255_1E_data_oe_l, + + I_CS_L => i8255_1E_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1E_pa, + O_PA => open, + O_PA_OE_L => open, + + I_PB => i8255_1E_pb, + O_PB => open, + O_PB_OE_L => open, + + I_PC => i8255_1E_pc, + O_PC => open, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + p_i8255_1d_bus_control : process(i8255_1D_pa_out, i8255_1D_pb_out, ym2149_3D_ioa_out, ym2149_3D_ioa_oe_l) + begin + if (ym2149_3D_ioa_oe_l = '0') then + ym2149_3D_ioa_in <= ym2149_3D_ioa_out; + else + ym2149_3D_ioa_in <= i8255_1D_pa_out; + end if; + + ampm <= i8255_1D_pb_out(4); -- amp mute + sint <= i8255_1D_pb_out(3); -- set int + end process; + + p_drive_cpubus : process(i8255_1D_data, i8255_1D_data_oe_l, i8255_1E_data, i8255_1E_data_oe_l) + begin + O_DATA_OE_L <= '1'; + O_DATA <= (others => '0'); + -- + if (i8255_1D_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1D_data; + elsif (i8255_1E_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1E_data; + end if; + end process; + -- + -- AUDIO CHIPS + -- + p_audio_clockgen : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + audio_div_cnt <= audio_div_cnt - "1"; + ls90_clk <= not audio_div_cnt(8); + + if (audio_div_cnt(8 downto 0) = "000000000") then + if (ls90_cnt = x"9") then + ls90_cnt <= x"0"; + else + ls90_cnt <= ls90_cnt + "1"; + end if; + end if; + + ls90_op <= "0000"; + case ls90_cnt is --ls90 outputs DCBA + when x"0" => ls90_op <= "0000"; + when x"1" => ls90_op <= "0010"; + when x"2" => ls90_op <= "0100"; + when x"3" => ls90_op <= "0110"; + when x"4" => ls90_op <= "1000"; + when x"5" => ls90_op <= "0001"; + when x"6" => ls90_op <= "0011"; + when x"7" => ls90_op <= "0101"; + when x"8" => ls90_op <= "0111"; + when x"9" => ls90_op <= "1001"; + when others => ls90_op <= "0000"; + end case; + end if; + end process; + + p_ym2149_3d_iob_in : process(I_HWSEL_FROGGER, ls90_op, ls90_clk) + begin + if not I_HWSEL_FROGGER then + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & ls90_op(2) & ls90_clk & "1110"; + else + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & '1' & ls90_clk & ls90_op(2) & "110"; + end if; + end process; + + u_ym2149_3C : entity work.YM2149 -- not used for frogger + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3C_dv, + O_DA_OE_L => ym2149_3C_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3C_bdir, + I_BC2 => ym2149_3C_bc2, + I_BC1 => ym2149_3C_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3C_audio, + O_CHAN => ym2149_3C_chan, + -- port a + I_IOA => "11111111", + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => "11111111", + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + u_ym2149_3D : entity work.YM2149 + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3D_dv, + O_DA_OE_L => ym2149_3D_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3D_bdir, + I_BC2 => ym2149_3D_bc2, + I_BC1 => ym2149_3D_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3D_audio, + O_CHAN => ym2149_3D_chan, + -- port a + I_IOA => ym2149_3D_ioa_in, + O_IOA => ym2149_3D_ioa_out, + O_IOA_OE_L => ym2149_3D_ioa_oe_l, + -- port b + I_IOB => ym2149_3D_iob_in, + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + p_filter_coef : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + case ym2149_3C_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3C_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(5 downto 4))); + when "10" => -- chan 1 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(3 downto 2))); + when "01" => -- chan 0 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(1 downto 0))); + when others => null; + end case; + + case ym2149_3D_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3D_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg(11 downto 10))); + when "10" => -- chan 1 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 9 downto 8))); + when "01" => -- chan 0 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 7 downto 6))); + when others => null; + end case; + end if; + end process; + + + p_ym2149_audio_process : process(ym2149_3C_audio, ym2149_3C_audio_pipe, ym2149_3D_audio, ym2149_3D_audio_pipe) + begin + audio_in_m_out_3C <= (('0' & ym2149_3C_audio & "000000000"))- ym2149_3C_audio_pipe(3); -- signed + audio_in_m_out_3D <= (('0' & ym2149_3D_audio & "000000000"))- ym2149_3D_audio_pipe(3); -- signed + end process; + + mult_3C : work.MULT18X18 + port map + ( + P => audio_mult_3C,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3C, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3C_k + ); + + mult_3D : work.MULT18X18 + port map + ( + P => audio_mult_3D,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3D, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3D_k + ); + + p_ym2149_audio_pipe : process(I_RESET_L, CLK) + begin + if (I_RESET_L = '0') then + ym2149_3C_audio_pipe <= (others => (others => '0')); + ym2149_3D_audio_pipe <= (others => (others => '0')); + elsif rising_edge(CLK) then +-- audio_mult_3C <= audio_in_m_out_3C * ym2149_3C_k; +-- audio_mult_3D <= audio_in_m_out_3D * ym2149_3D_k; + if (ENA_1_79 = '1') then + -- we need some holding registers anyway, so lets just make it a shift and save a mux + ym2149_3C_audio_pipe(3 downto 1) <= ym2149_3C_audio_pipe(2 downto 0); + ym2149_3C_audio_pipe(0) <= audio_mult_3C(33 downto 16) + ym2149_3C_audio_pipe(3); -- bit 33 sign + + ym2149_3D_audio_pipe(3 downto 1) <= ym2149_3D_audio_pipe(2 downto 0); + ym2149_3D_audio_pipe(0) <= audio_mult_3D(33 downto 16) + ym2149_3D_audio_pipe(3); -- bit 33 sign + end if; + end if; + end process; + + p_ym2149_audio_mix : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + ym2149_3C_chan_t1 <= ym2149_3C_chan; + ym2149_3D_chan_t1 <= ym2149_3D_chan; + + if (ym2149_3C_chan_t1 = "11") then + audio_3C_mix <= (others => '0'); + audio_3C_final <= audio_3C_mix; + else + audio_3C_mix <= audio_3C_mix + ("00" & ym2149_3C_audio_pipe(0)(16 downto 9)); + end if; + + if (ym2149_3D_chan_t1(1 downto 0) = "11") then + audio_3D_mix <= (others => '0'); + audio_3D_final <= audio_3D_mix; + else + audio_3D_mix <= audio_3D_mix + ("00" & ym2149_3D_audio_pipe(0)(16 downto 9)); + end if; + + audio_final <= ('0' & audio_3C_final) + ('0' & audio_3D_final); + end if; + end process; + + p_audio_out : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + O_AUDIO <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + if (ampm = '1') then + O_AUDIO <= (others => '0'); + else + if (audio_final(10) = '1') then + O_AUDIO <= (others => '1'); + else + O_AUDIO <= audio_final(9 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_security_6J : process(xb) + begin + -- chip K10A PAL16L8 + -- equations from Mark @ http://www.leopardcats.com/ + xbo(3 downto 0) <= xb(3 downto 0); + xbo(4) <= not(xb(0) or xb(1) or xb(2) or xb(3)); + xbo(5) <= not((not xb(2) and not xb(0)) or (not xb(2) and not xb(1)) or (not xb(3) and not xb(0)) or (not xb(3) and not xb(1))); + + xbo(6) <= not(not xb(0) and not xb(3)); + xbo(7) <= not((not xb(1)) or xb(2)); + end process; + + p_security_count : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + security_count <= "000"; + elsif rising_edge(CLK) then + rd_l_t1 <= i_rd_l; + if (I_ADDR = x"8102") and (I_RD_L = '0') and (rd_l_t1 = '1') then + security_count <= security_count + "1"; + end if; + end if; + end process; + + p_security_2B : process(security_count) + begin + -- I am not sure what this chip does yet, but this gets us past the initial check for now. + case security_count is + when "000" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "001" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "010" => net_1e10_i <= '1'; net_1e12_i <= '0'; + when "011" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "100" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "101" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "110" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "111" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when others => null; + end case; + end process; + +end RTL; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd new file mode 100644 index 00000000..5e54037c --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_top.vhd @@ -0,0 +1,242 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_TOP is +port ( + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + + O_AUDIO : out std_logic_vector(9 downto 0); + + button_in : in std_logic_vector(7 downto 0); + + RESET : in std_logic; + clk : in std_logic; -- 25 + ena_12 : in std_logic; -- 6.25 x 2 + ena_6 : in std_logic; -- 6.25 (inverted) + ena_6b : in std_logic; -- 6.25 + ena_1_79 : in std_logic -- 1.786 +); +end; + +architecture RTL of SCRAMBLE_TOP is +-- this MUST be set true for frogger +-- this MUST be set false for scramble, the_end, amidar +constant I_HWSEL_FROGGER : boolean := true; + +-- ip registers +signal ip_1p : std_logic_vector(6 downto 0); +signal ip_2p : std_logic_vector(6 downto 0); +signal ip_service : std_logic; +signal ip_coin1 : std_logic; +signal ip_coin2 : std_logic; +signal ip_dip_switch : std_logic_vector(5 downto 1); + +-- ties to audio board +signal audio_addr : std_logic_vector(15 downto 0); +signal audio_data_out : std_logic_vector(7 downto 0); +signal audio_data_in : std_logic_vector(7 downto 0); +signal audio_data_oe_l : std_logic; +signal audio_rd_l : std_logic; +signal audio_wr_l : std_logic; +signal audio_iopc7 : std_logic; +signal audio_reset_l : std_logic; + +begin + +u_scramble : entity work.SCRAMBLE +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + O_HSYNC => O_HSYNC, + O_VSYNC => O_VSYNC, + O_HBLANK => O_HBLANK, + O_VBLANK => O_VBLANK, + -- + -- to audio board + -- + O_ADDR => audio_addr, + O_DATA => audio_data_out, + I_DATA => audio_data_in, + I_DATA_OE_L => audio_data_oe_l, + O_RD_L => audio_rd_l, + O_WR_L => audio_wr_l, + O_IOPC7 => audio_iopc7, + O_RESET_WD_L => audio_reset_l, + -- + ENA => ena_6, + ENAB => ena_6b, + ENA_12 => ena_12, + -- + RESET => reset, + CLK => clk +); + +-- +-- +-- audio subsystem +-- +u_audio : entity work.SCRAMBLE_AUDIO +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_ADDR => audio_addr, + I_DATA => audio_data_out, + O_DATA => audio_data_in, + O_DATA_OE_L => audio_data_oe_l, + -- + I_RD_L => audio_rd_l, + I_WR_L => audio_wr_l, + I_IOPC7 => audio_iopc7, + -- + O_AUDIO => O_AUDIO, + -- + I_1P_CTRL => ip_1p, -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL => ip_2p, -- start, shoot1, shoot2, left,right,up,down + I_SERVICE => ip_service, + I_COIN1 => ip_coin1, + I_COIN2 => ip_coin2, + O_COIN_COUNTER => open, + -- + I_DIP => ip_dip_switch, + -- + I_RESET_L => audio_reset_l, + ENA => ena_6, + ENA_1_79 => ena_1_79, + CLK => clk +); + +--button_in(0) = Joystick Up +--button_in(1) = Joystick Down +--button_in(2) = Joystick Left +--button_in(3) = Joystick Right +--button_in(4) = Button Left +--button_in(5) = Button Down +--button_in(6) = Joystick Fire +--button_in(7) = Button Right + +--Buttons are connected to ground and connect to 3.3V when pressed +--Joystick has internal pullup resistor and connects to ground when pressed + +--A '0' on the input is active. Inputs are active low. + +-- assign inputs +-- start, shoot1, shoot2, left,right,up,down +ip_1p(6) <= button_in(4); -- start 1 +ip_1p(5) <= button_in(6); -- shoot1 +ip_1p(4) <= button_in(6); -- shoot2 +ip_1p(3) <= button_in(2); -- p1 left +ip_1p(2) <= button_in(3); -- p1 right +ip_1p(1) <= button_in(0); -- p1 up +ip_1p(0) <= button_in(1); -- p1 down +-- +ip_2p(6) <= button_in(7); -- start 2 +ip_2p(5) <= button_in(6); +ip_2p(4) <= button_in(6); +ip_2p(3) <= button_in(2); -- p2 left +ip_2p(2) <= button_in(3); -- p2 right +ip_2p(1) <= button_in(0); -- p2 up +ip_2p(0) <= button_in(1); -- p2 down +-- +ip_service <= '1'; +ip_coin1 <= button_in(5); -- credit +ip_coin2 <= '1'; + +-- dip switch settings +scramble_dips : if (not I_HWSEL_FROGGER) generate +begin + --SW #1 SW #2 Rockets SW #3 Cabinet + ------- ----- --------- ----- -------- + --OFF OFF Unlimited OFF Table + --OFF ON 5 ON Up Right + --ON OFF 4 + --ON ON 3 + + + --SW #4 SW #5 Coins/Play + ------- ----- ---------- + --OFF OFF 4 + --OFF ON 3 + --ON OFF 2 + --ON ON 1 + + ip_dip_switch(5 downto 4) <= not "11"; -- 1 play/coin. + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "10"; +end generate; + +frogger_dips : if ( I_HWSEL_FROGGER) generate +begin + --1 2 3 4 5 Meaning + ------------------------------------------------------- + --On On 3 Frogs + --On Off 5 Frogs + --Off On 7 Frogs + --Off Off 256 Frogs (!) + -- + -- On Upright unit + -- Off Cocktail unit + -- + -- On On 1 coin 1 play + -- On Off 2 coins 1 play + -- Off On 3 coins 1 play + -- Off Off 1 coin 2 plays + + ip_dip_switch(5 downto 4) <= not "11"; + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "01"; +end generate; + +end RTL; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd new file mode 100644 index 00000000..47fd3641 --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/scramble_video.vhd @@ -0,0 +1,758 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_VIDEO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + I_VBLANK : in std_logic; + I_VSYNC : in std_logic; + + I_VCMA : in std_logic; + I_HCMA : in std_logic; + -- + I_CPU_ADDR : in std_logic_vector(15 downto 0); + I_CPU_DATA : in std_logic_vector(7 downto 0); + O_VRAM_DATA : out std_logic_vector(7 downto 0); + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L : in std_logic; + I_VRAMRD_L : in std_logic; + I_OBJRAMWR_L : in std_logic; + I_OBJRAMRD_L : in std_logic; + I_OBJEN_L : in std_logic; + -- + I_STARSON : in std_logic; + I_POUT1 : in std_logic; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + CLK : in std_logic + ); +end; + +-- chars stars vidout? shell/missile +-- +-- 220R B 100 B 390R B 100R R +-- 470R B 150 B 100R G +-- 220R G 100 G blue ? +-- 470R G 150 G +-- 1K G 100 R +-- 220R R 150 R +-- 470R R +-- 1K R +architecture RTL of SCRAMBLE_VIDEO is + + type array_3x5 is array (2 downto 0) of std_logic_vector(4 downto 0); + -- timing + signal ld : std_logic; + signal h256_l : std_logic; + signal h256 : std_logic; + signal cblank_s : std_logic; + signal hcmp1_s : std_logic; + signal hcmp2_s : std_logic; + signal hcmp1 : std_logic; + signal hcmp2 : std_logic; + signal cblank_l : std_logic; + signal h256_l_s : std_logic; + signal hcnt_f : std_logic_vector(7 downto 0); + signal vcnt_f : std_logic_vector(7 downto 0); + + -- load strobes + signal vpl_load : std_logic; + signal col_load : std_logic; + signal objdata_load : std_logic; + signal missile_load : std_logic; + signal missile_reg_l : std_logic; + + signal cntr_clr : std_logic; + signal cntr_load : std_logic; + signal sld_l : std_logic; + + -- video ram + signal vram_addr_sum : std_logic_vector(8 downto 0); -- extra bit for debug + signal msld_l : std_logic; + signal vram_addr_reg : std_logic_vector(7 downto 0); + signal vram_addr_xor : std_logic_vector(3 downto 0); + signal vram_addr : std_logic_vector(9 downto 0); + signal vram_dout : std_logic_vector(7 downto 0); + signal ldout : std_logic; + + -- object ram + signal obj_addr : std_logic_vector(7 downto 0); + signal hpla : std_logic_vector(7 downto 0); + signal objdata : std_logic_vector(7 downto 0); + + signal obj_rom_addr : std_logic_vector(10 downto 0); + signal obj_rom_0_dout : std_logic_vector(7 downto 0); + signal obj_rom_1_dout : std_logic_vector(7 downto 0); + -- + signal col_reg : std_logic_vector(2 downto 0); + signal cd : std_logic_vector(2 downto 0); + + signal shift_reg_1 : std_logic_vector(7 downto 0); + signal shift_reg_0 : std_logic_vector(7 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + signal gr : std_logic_vector(1 downto 0); + signal gc : std_logic_vector(2 downto 0); + + signal vid : std_logic_vector(1 downto 0); + signal col : std_logic_vector(2 downto 0); + + signal obj_video_out_reg : std_logic_vector(4 downto 0); + signal vidout_l : std_logic; + signal obj_lut_out : std_logic_vector(7 downto 0); + + signal cntr_addr : std_logic_vector(7 downto 0); + signal cntr_addr_xor : std_logic_vector(10 downto 0); + signal sprite_sel : std_logic; + signal sprite_ram_ip : std_logic_vector(7 downto 0); + signal sprite_ram_waddr : std_logic_vector(10 downto 0); + signal sprite_ram_op : std_logic_vector(7 downto 0); + -- shell + signal shell_cnt : std_logic_vector(7 downto 0); + signal shell_ena : std_logic; + signal shell : std_logic; + signal shell_reg : std_logic; + -- stars + signal star_reg_1 : std_logic; + signal star_reg_2 : std_logic; + signal star_cnt_div : std_logic_vector(22 downto 0); + signal star_cnt : std_logic_vector(1 downto 0); + signal star_shift : std_logic_vector(16 downto 0); + signal star_shift_t1 : std_logic_vector(16 downto 0); + signal star_on : std_logic; + signal star_out_reg : std_logic; + -- frogger blue bar + signal frogger_blue_reg : std_logic; + signal frogger_blue : std_logic; + signal frogger_blue_out_reg : std_logic; + -- scramble blue + signal pout1_reg : std_logic; + + +begin + p_hcnt_decode : process(I_HCNT) + begin + ld <= '0'; + if (I_HCNT(2 downto 0) = "111") then + ld <= '1'; + end if; + h256_l <= I_HCNT(8); + h256 <= not I_HCNT(8); + + end process; + + p_timing_decode : process(h256, h256_l, I_HCMA, I_VBLANK) + begin + cblank_s <= not (I_VBLANK or h256); -- active low + hcmp1_s <= h256_l and I_HCMA; + end process; + + p_reg : process + begin + wait until rising_edge(CLK); + + if (ENA = '1') then + if (ld = '1') then + hcmp1 <= hcmp1_s; + hcmp2 <= hcmp2_s; + cblank_l <= cblank_s; + h256_l_s <= h256_l; + + if not I_HWSEL_FROGGER then + cd <= col_reg; + else + cd <= col_reg(0) & col_reg(2 downto 1); + end if; + end if; + end if; + end process; + + p_load_decode : process(ld, I_HCNT, h256) + variable obj_load : std_logic; + begin + vpl_load <= '0'; + obj_load := '0'; + col_load <= '0'; + + if (I_HCNT(2 downto 0) = "001") then vpl_load <= '1'; end if; -- 1 clock later + if (I_HCNT(2 downto 0) = "011") then obj_load := '1'; end if; -- 1 later + if (I_HCNT(2 downto 0) = "101") then col_load <= '1'; end if; -- 1 later + + objdata_load <= obj_load and h256 and (not I_HCNT(3)); + missile_load <= obj_load and h256 and ( I_HCNT(3)); + + cntr_clr <= ld and (not h256) and (not I_HCNT(3)); + cntr_load <= ld and ( h256) and (not I_HCNT(3)); + + end process; + + p_hv_flip : process(I_HCNT, I_VCNT, I_VCMA, hcmp1_s) + begin + for i in 0 to 7 loop + vcnt_f(i) <= I_VCNT(i) xor I_VCMA; + hcnt_f(i) <= I_HCNT(i) xor hcmp1_s; + end loop; + end process; + + p_video_addr_calc : process(I_HWSEL_FROGGER, vcnt_f, hpla) + begin + if not I_HWSEL_FROGGER then + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(7 downto 0)); + else + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(3 downto 0) & hpla(7 downto 4)); + end if; + end process; + + p_msld : process(vram_addr_sum) + begin + msld_l <= '1'; + if (vram_addr_sum(7 downto 0) = "11111111") then + msld_l <= '0'; + end if; + end process; + + p_video_addr_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_VBLANK = '1') then -- was async + vram_addr_reg <= x"00"; + elsif (vpl_load = '1') then -- vpl_l + vram_addr_reg <= vram_addr_sum(7 downto 0); + end if; + end if; + end process; + + p_vram_xor : process(vram_addr_reg, objdata, h256) + variable flip : std_logic; + begin + flip := objdata(7) and h256; + for i in 0 to 3 loop + vram_addr_xor(i) <= vram_addr_reg(i) xor flip; + end loop; + end process; + + p_vram_addr : process(vram_addr_reg, cblank_s, ld, I_CPU_ADDR, vram_addr_xor, hcnt_f) + variable match : std_logic; + begin + match := '0'; + if (vram_addr_reg(7 downto 4) = "1111") then + match := '1'; + end if; + + if (cblank_s = '0') then + ldout <= match and ld; -- blanking, sprites + else + ldout <= ld; + end if; + + if (cblank_s = '0') then -- blanking, sprites + --vram_cs <= (not I_VRAMWR_L) or (not I_VRAMRD_L); + vram_addr <= I_CPU_ADDR(9 downto 0); -- let the cpu in + else + --vram_cs <= '1'; + vram_addr <= vram_addr_reg(7 downto 4) & vram_addr_xor(3) & hcnt_f(7 downto 3); + end if; + end process; + + u_vram : work.dpram generic map (10,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_VRAMWR_L, + + addr_a_i => vram_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => vram_addr, + data_b_o => vram_dout + ); + O_VRAM_DATA <= vram_dout; + + p_object_ram_addr : process(h256, I_HCMA, objdata, I_HCNT, hcnt_f, I_CPU_ADDR, I_OBJEN_L) + begin + -- I believe the object ram can only be written during vblank + + if (h256 = '0') then + hcmp2_s <= I_HCMA; + else + hcmp2_s <= objdata(6); + end if; + + if (I_OBJEN_L = '0') then + obj_addr <= I_CPU_ADDR(7 downto 0); + else + obj_addr(7) <= '0'; + obj_addr(6) <= h256; + + -- A + if (h256 = '0') then -- normal + obj_addr(5) <= hcnt_f(7); --128h'; + else -- sprite + obj_addr(5) <= hcnt_f(3) and I_HCNT(1);-- 8h' and 2h; + end if; + + obj_addr(4 downto 2) <= hcnt_f(6 downto 4); + + if (h256 = '0') then -- normal + obj_addr(1) <= hcnt_f(3); --8h' + obj_addr(0) <= I_HCNT(2); --4h + else + obj_addr(1) <= I_HCNT(2); --4h + obj_addr(0) <= I_HCNT(1); --2h + end if; + + end if; + end process; + + u_object_ram : work.dpram generic map (8,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_OBJRAMWR_L, + + addr_a_i => obj_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => obj_addr, + data_b_o => hpla + ); + + p_objdata_regs : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (col_load = '1') then -- colour load + col_reg <= hpla(2 downto 0); + end if; + + if (objdata_load = '1') then -- sprite load + objdata <= hpla; + end if; + + if (I_VBLANK = '1') then -- was async + missile_reg_l <= '1'; + elsif (missile_load = '1') then + missile_reg_l <= msld_l; + end if; + end if; + end process; + + p_obj_rom_addr : process(h256, vram_addr_xor, vram_dout, objdata, I_HCNT) + begin + obj_rom_addr( 2 downto 0) <= vram_addr_xor(2 downto 0); + if (h256 = '0') then + -- a + obj_rom_addr(10 downto 3) <= vram_dout; -- background objects + else + obj_rom_addr(10 downto 3) <= objdata(5 downto 0) & vram_addr_xor(3) & (objdata(6) xor I_HCNT(3)); -- sprites + end if; + end process; + + obj_rom0 : entity work.ROM_OBJ_0 -- 5H + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_0_dout); + obj_rom1 : entity work.ROM_OBJ_1 -- 5F + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_1_dout); + + p_obj_rom_shift : process + variable obj_rom_0_dout_s : std_logic_vector(7 downto 0); + begin + wait until rising_edge (CLK); + if not I_HWSEL_FROGGER then + obj_rom_0_dout_s := obj_rom_0_dout; + else -- swap bits 0 and 1 + obj_rom_0_dout_s := obj_rom_0_dout(7 downto 2) & obj_rom_0_dout(0) & obj_rom_0_dout(1); + end if; + + if (ENA = '1') then + case shift_sel is + when "00" => null; -- do nothing + + when "01" => shift_reg_1 <= '0' & shift_reg_1(7 downto 1); -- right + shift_reg_0 <= '0' & shift_reg_0(7 downto 1); + + when "10" => shift_reg_1 <= shift_reg_1(6 downto 0) & '0'; -- left + shift_reg_0 <= shift_reg_0(6 downto 0) & '0'; + + when "11" => shift_reg_1 <= obj_rom_1_dout (7 downto 0); -- load + shift_reg_0 <= obj_rom_0_dout_s(7 downto 0); + when others => null; + end case; + end if; + end process; + + p_obj_rom_shift_sel : process(hcmp2, ldout, shift_reg_1, shift_reg_0) + begin + if (hcmp2 = '0') then + + shift_sel(1) <= '1'; + shift_sel(0) <= ldout; + shift_op(1) <= shift_reg_1(7); + shift_op(0) <= shift_reg_0(7); + else + + shift_sel(1) <= ldout; + shift_sel(0) <= '1'; + shift_op(1) <= shift_reg_1(0); + shift_op(0) <= shift_reg_0(0); + end if; + end process; + + p_video_out_logic : process(shift_op, cd, gr, gc) + variable vidon : std_logic; + begin + vidon := shift_op(0) or shift_op(1); + + if (gr(1 downto 0) = "00") then + vid(1 downto 0) <= shift_op(1 downto 0); + else + vid(1 downto 0) <= gr(1 downto 0); + end if; + + if (gc(2 downto 0) = "000") and (vidon = '1') then + col(2 downto 0) <= cd(2 downto 0); + else + col(2 downto 0) <= gc(2 downto 0); + end if; + end process; + + p_shell_ld : process(ld, h256, I_HCNT, missile_reg_l) + begin + sld_l <= '1'; + if (ld = '1') and (h256 = '1') and (I_HCNT(3) = '1') then + if (missile_reg_l = '0') and (I_HCNT(6 downto 4) /= "111") then + sld_l <= '0'; + end if; + end if; + + end process; + + p_shell_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + if (sld_l = '0') then + shell_cnt <= hpla; + elsif (cblank_l = '1') then + shell_cnt <= shell_cnt + "1"; + else + shell_cnt <= shell_cnt; + end if; + + if (sld_l = '0') then + shell_ena <= '1'; + elsif (shell = '1') then + shell_ena <= '0'; + end if; + end if; + end process; + + p_shell_op : process(shell_cnt, shell_ena) + begin + -- note how T input is from QD on the bottom counter + -- we get a rc from xF8 to XFF + -- so the shell is set at count xFA (rc and bit 1) + shell <= '0'; + if (shell_cnt = x"F8") then -- minus 2 as delay wrong + shell <= shell_ena; + end if; + end process; + + p_cntr_cnt : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (cntr_clr = '1') and (h256_l_s = '0') then -- async + cntr_addr <= (others => '0'); + elsif (cntr_load = '1') then + cntr_addr <= hpla(7 downto 0); + else + cntr_addr <= cntr_addr + "1"; + end if; + end if; + end process; + + p_cntr_addr : process(cntr_addr, hcmp1) + begin + cntr_addr_xor(10 downto 8) <= (others => '0'); + for i in 0 to 7 loop + cntr_addr_xor(i) <= cntr_addr(i) xor hcmp1; + end loop; + end process; + + p_sprite_sel : process(h256_l_s, cntr_addr_xor) + begin + sprite_sel <= '0'; + if (h256_l_s = '0') and (cntr_addr_xor(7 downto 4) /= "0000") then + sprite_sel <= '1'; + end if; + end process; + + p_sprite_write : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- delay 1 clock + sprite_ram_ip <= (others => '0'); + if (sprite_sel = '1') then + sprite_ram_ip(4 downto 2) <= col(2 downto 0); + sprite_ram_ip(1 downto 0) <= vid(1 downto 0); + end if; + + sprite_ram_waddr <= cntr_addr_xor; + end if; + end process; + + u_sprite_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => '1', + + addr_a_i => sprite_ram_waddr, + data_a_i => sprite_ram_ip, + + clk_b_i => clk, + addr_b_i => cntr_addr_xor, + data_b_o => sprite_ram_op + ); + + gc(2 downto 0) <= sprite_ram_op(4 downto 2); + gr(1 downto 0) <= sprite_ram_op(1 downto 0); + + p_video_out_reg : process + variable vidout_l_int : std_logic; + begin + wait until rising_edge(CLK); + -- register all objects to match increased video delay + if (ENA = '1') then + star_shift_t1 <= star_shift; + + if (cblank_l = '0') then + -- logic around the clr workes out as a sync reset + obj_video_out_reg <= (others => '0'); + shell_reg <= '0'; + frogger_blue_out_reg <= '0'; + star_out_reg <= '0'; + pout1_reg <= '0'; + else + + obj_video_out_reg(4 downto 2) <= col(2 downto 0); + obj_video_out_reg(1 downto 0) <= vid(1 downto 0); + vidout_l <= not(vid(1) or vid(0)); + -- probably wider than the original, we must be a whole 6MHz clock here or the scan-doubler will loose it. + shell_reg <= shell; + frogger_blue_out_reg <= frogger_blue; + + star_out_reg <= '0'; + if (star_shift(7 downto 0) = x"FF") and (star_on = '1') then + star_out_reg <= (vcnt_f(0) xor hcnt_f(3)) and (not star_shift(16)); + end if; + + pout1_reg <= I_POUT1; + + end if; + end if; + end process; + +-- Non BRAM (LUT) Version +-- col_rom : entity work.ROM_LUT +-- port map( +-- ADDR => obj_video_out_reg(4 downto 0), +-- DATA => obj_lut_out +-- ); + +-- BRAM Version + col_rom : entity work.ROM_LUT + port map( + CLK => CLK, + ADDR => obj_video_out_reg(4 downto 0), + DATA => obj_lut_out + ); + + p_col_rom_ce : process + variable video : array_3x5; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + video(0)(4) := '0'; + video(1)(4) := '0'; + video(2)(4) := '0'; + video(0)(3) := '0'; -- b + video(1)(3) := '0'; -- g + video(2)(3) := '0'; -- r + + if (vidout_l = '0') then -- cs_l on col rom + + video(0)(2 downto 0) := obj_lut_out(7 downto 6) & '0'; + video(1)(2 downto 0) := obj_lut_out(5 downto 3); + video(2)(2 downto 0) := obj_lut_out(2 downto 0); + else + video(0)(2 downto 0) := "000"; + video(1)(2 downto 0) := "000"; + video(2)(2 downto 0) := "000"; + end if; + -- + -- end of direct assigns + -- + if I_HWSEL_FROGGER then + if (frogger_blue_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + "00010"; + end if; + end if; + + -- add stars, background and video + if not I_HWSEL_FROGGER then + if (star_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ( '0' & star_shift_t1(13 downto 12) & "00"); + video(1) := video(1) + ( '0' & star_shift_t1(11 downto 10) & "00"); + video(2) := video(2) + ( '0' & star_shift_t1( 9 downto 8) & "00"); + end if; + + if (pout1_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ("00011"); + end if; + end if; + -- check for clip + for i in 0 to 2 loop + if video(i)(4) = '1' or video(i)(3) = '1' then + video(i)(2 downto 0) := (others => '1'); + end if; + end loop; + + O_VIDEO_B <= video(0)(2 downto 0) & video(0)(2); + O_VIDEO_G <= video(1)(2 downto 0) & video(1)(2); + O_VIDEO_R <= video(2)(2 downto 0) & video(2)(2); + end if; + end process; + + p_frogger_blue_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_HCNT(7 downto 0) = x"87") then + frogger_blue_reg <= '1'; + elsif (I_HCNT(7 downto 0) = x"07") then + frogger_blue_reg <= '0'; + end if; + end if; + end process; + frogger_blue <= not (frogger_blue_reg xor I_HCMA); + + p_stars_timer : process + begin + wait until rising_edge(CLK); + -- 555 period 0.8316 seconds + -- ~ 4DF 666 + if (ENA = '1') then + if (star_cnt_div(22 downto 17) = "100111") then + star_cnt_div <= (others => '0'); + star_cnt <= star_cnt + "1"; + else + star_cnt_div <= star_cnt_div + "1"; + end if; + end if; + end process; + + p_stars_demux : process(star_cnt, I_VCNT, star_shift) + begin + case star_cnt is + when "00" => star_on <= star_shift(8); + when "01" => star_on <= star_shift(10); + when "10" => star_on <= I_VCNT(1); + when "11" => star_on <= '1'; + when others => null; + end case; + end process; + + p_stars : process + variable star_ena : std_logic; + variable star_shift_ena : std_logic; + variable fb : std_logic; + variable star_clear : std_logic; + begin + wait until rising_edge(CLK); + -- stars clocked off 12 MHz clock + star_ena := ENA_12 and (not I_VSYNC) and h256_l_s; + + if (ENA = '1') and (I_VSYNC = '1') then + star_reg_1 <= '0'; + star_reg_2 <= '0'; + elsif (star_ena = '1') then + star_reg_1 <= '1'; + star_reg_2 <= star_reg_1; + end if; + + star_shift_ena := (star_reg_2 or I_HCMA) and star_ena; + + star_clear := I_STARSON and (not I_VBLANK); + + fb := (not star_shift(16)) xor star_shift(4); + if (star_clear = '0') then + star_shift <= (others => '0'); + elsif (star_shift_ena = '1') then + star_shift(16 downto 0) <= star_shift(15 downto 0) & fb; + end if; + end process; + +end RTL; diff --git a/Arcade/Scramble Hardware/Frogger_MiST/rtl/video_mixer.sv b/Arcade/Scramble Hardware/Frogger_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Scramble Hardware/Frogger_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Scramble Hardware/Scramble_MiST/README.txt b/Arcade/Scramble Hardware/Scramble_MiST/README.txt new file mode 100644 index 00000000..c28042b7 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Scramble port to MiST by Gehstock +-- 10 November 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire+Bomb + +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + diff --git a/Arcade/Scramble Hardware/Scramble_MiST/Release/Scramble(PACE Code).rbf b/Arcade/Scramble Hardware/Scramble_MiST/Release/Scramble(PACE Code).rbf new file mode 100644 index 00000000..6d7ebdea Binary files /dev/null and b/Arcade/Scramble Hardware/Scramble_MiST/Release/Scramble(PACE Code).rbf differ diff --git a/Arcade/Scramble Hardware/Scramble_MiST/Release/Scramble.rbf b/Arcade/Scramble Hardware/Scramble_MiST/Release/Scramble.rbf new file mode 100644 index 00000000..74657581 Binary files /dev/null and b/Arcade/Scramble Hardware/Scramble_MiST/Release/Scramble.rbf differ diff --git a/Arcade/Scramble Hardware/Scramble_MiST/Scramble.qpf b/Arcade/Scramble Hardware/Scramble_MiST/Scramble.qpf new file mode 100644 index 00000000..75e0934b --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/Scramble.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Scramble" diff --git a/Arcade/Scramble Hardware/Scramble_MiST/Scramble.qsf b/Arcade/Scramble Hardware/Scramble_MiST/Scramble.qsf new file mode 100644 index 00000000..66a68871 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/Scramble.qsf @@ -0,0 +1,170 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 05:08:48 November 15, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Arcade-Scramble_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY ScrambleMist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ---------------------- +# start ENTITY(Scramble) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(Scramble) +# -------------------- +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_2.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_LUT.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd +set_global_assignment -name VHDL_FILE rtl/i82c55.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VERILOG_FILE rtl/build_id.v +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd +set_global_assignment -name VHDL_FILE rtl/scramble.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ScrambleMist.sv +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Scramble_MiST/Scramble.srf b/Arcade/Scramble Hardware/Scramble_MiST/Scramble.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/Scramble.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Scramble Hardware/Scramble_MiST/clean.bat b/Arcade/Scramble Hardware/Scramble_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd new file mode 100644 index 00000000..32535505 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/MULT18X18.vhd @@ -0,0 +1,53 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY MULT18X18 IS + PORT + ( + A : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); +END MULT18X18; + + +ARCHITECTURE SYN OF mult18x18 IS + + COMPONENT lpm_mult + GENERIC ( + lpm_hint : STRING; + lpm_representation : STRING; + lpm_type : STRING; + lpm_widtha : NATURAL; + lpm_widthb : NATURAL; + lpm_widthp : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + lpm_mult_component : lpm_mult + GENERIC MAP ( + lpm_hint => "MAXIMIZE_SPEED=5", + lpm_representation => "SIGNED", + lpm_type => "LPM_MULT", + lpm_widtha => 18, + lpm_widthb => 18, + lpm_widthp => 36 + ) + PORT MAP ( + dataa => A, + datab => B, + result => P + ); + +END SYN; + diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd new file mode 100644 index 00000000..5a3fb9a2 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_LUT.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_LUT is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_LUT is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"17",X"C7",X"F6",X"00",X"17",X"C0",X"3F",X"00",X"07",X"C0",X"3F",X"00",X"C0",X"C4",X"07", + X"00",X"C7",X"31",X"17",X"00",X"31",X"C7",X"3F",X"00",X"F6",X"07",X"F0",X"00",X"3F",X"07",X"C4"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd new file mode 100644 index 00000000..2d6b038f --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00", + X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00", + X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00", + X"1C",X"08",X"1C",X"14",X"36",X"36",X"00",X"00",X"08",X"1C",X"1C",X"08",X"3E",X"2A",X"3E",X"2A", + X"00",X"00",X"00",X"18",X"18",X"00",X"00",X"00",X"18",X"28",X"38",X"2C",X"38",X"28",X"18",X"00", + X"70",X"70",X"A8",X"F8",X"A8",X"70",X"77",X"00",X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd new file mode 100644 index 00000000..bd3fcb42 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_OBJ_1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_OBJ_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_OBJ_1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00", + X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00", + 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-0,0 +1,1046 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_PGM is +port ( + clk : in std_logic; + addr : in std_logic_vector(13 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_PGM is + type rom is array(0 to 16383) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"AF",X"32",X"01",X"68",X"C3",X"D1",X"00",X"FF",X"77",X"3C",X"23",X"77",X"3C",X"19",X"C9",X"FF", + X"77",X"23",X"10",X"FC",X"C9",X"FF",X"FF",X"FF",X"77",X"23",X"10",X"FC",X"0D",X"20",X"F9",X"C9", + X"85",X"6F",X"3E",X"00",X"8C",X"67",X"7E",X"C9",X"87",X"E1",X"5F",X"16",X"00",X"19",X"5E",X"23", + X"56",X"EB",X"E9",X"FF",X"FF",X"FF",X"FF",X"FF",X"E5",X"26",X"40",X"3A",X"A0",X"40",X"6F",X"CB", + X"7E",X"28",X"0E",X"72",X"2C",X"73",X"2C",X"7D",X"FE",X"C0",X"30",X"02",X"3E",X"C0",X"32",X"A0", + X"40",X"E1",X"C9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + 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Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd new file mode 100644 index 00000000..98fd886c --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"C3",X"72",X"02",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"08",X"D9",X"3E",X"0E",X"D3",X"40",X"DB",X"80", + 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X"10",X"80",X"FE",X"04",X"28",X"17",X"FE",X"05",X"28",X"18",X"FE",X"06",X"28",X"19",X"FE",X"01", + X"28",X"1A",X"FE",X"02",X"28",X"1B",X"11",X"00",X"0C",X"CD",X"F6",X"07",X"C9",X"11",X"03",X"00", + X"18",X"F7",X"11",X"0C",X"00",X"18",X"F2",X"11",X"30",X"00",X"18",X"ED",X"11",X"C0",X"00",X"18", + X"E8",X"11",X"00",X"03",X"18",X"E3",X"2A",X"0C",X"80",X"7A",X"B4",X"67",X"7B",X"B5",X"6F",X"22"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd new file mode 100644 index 00000000..adae5bd7 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"0C",X"80",X"77",X"C9",X"B7",X"C8",X"21",X"17",X"08",X"E5",X"87",X"5F",X"16",X"00",X"21",X"60", + X"08",X"19",X"5E",X"23",X"56",X"EB",X"E9",X"B7",X"C8",X"3A",X"10",X"80",X"FE",X"01",X"28",X"18", + X"FE",X"02",X"28",X"1C",X"FE",X"03",X"28",X"20",X"FE",X"04",X"28",X"24",X"FE",X"05",X"28",X"28", + X"AF",X"32",X"0A",X"80",X"32",X"0B",X"80",X"C9",X"AF",X"32",X"00",X"80",X"32",X"01",X"80",X"C9", + X"AF",X"32",X"02",X"80",X"32",X"03",X"80",X"C9",X"AF",X"32",X"04",X"80",X"32",X"05",X"80",X"C9", + X"AF",X"32",X"06",X"80",X"32",X"07",X"80",X"C9",X"AF",X"32",X"08",X"80",X"32",X"09",X"80",X"C9", + X"00",X"00",X"39",X"09",X"B5",X"09",X"31",X"0A",X"AD",X"0A",X"29",X"0B",X"1F",X"0D",X"4E",X"12", + X"CE",X"13",X"CE",X"0D",X"D4",X"0D",X"4A",X"10",X"51",X"10",X"58",X"10",X"C7",X"10",X"CE",X"10", + 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+process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd new file mode 100644 index 00000000..43e9cd64 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ROM/ROM_SND_2.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_SND_2 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_SND_2 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"88",X"8C",X"8F",X"8C",X"88",X"8C",X"88",X"8C",X"8F",X"8C",X"88",X"AF",X"FF",X"1F",X"0A",X"5F", + X"09",X"A8",X"80",X"68",X"68",X"A8",X"80",X"68",X"68",X"88",X"83",X"88",X"8C",X"88",X"83",X"88", + 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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv new file mode 100644 index 00000000..c0b2f69d --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/ScrambleMist.sv @@ -0,0 +1,200 @@ +//============================================================================ +// Arcade: Scramble +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module ScrambleMist +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Scramble;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6p, ce_6n, ce_12, ce_1p79; +always @(negedge clk_sys) begin + reg [1:0] div = 0; + reg [3:0] div179 = 0; + + div <= div + 1'd1; + + ce_12 <= div[0]; + ce_6p <= div[0] & ~div[1]; + ce_6n <= div[0] & div[1]; + + ce_1p79 <= 0; + div179 <= div179 - 1'd1; + if(!div179) begin + div179 <= 13; + ce_1p79 <= 1; + end +end + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +wire hsync,vsync; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [3:0] r,b,g; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6p), + .ce_pix_actual(ce_6p), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r[1:0]}), + .G({g,g[1:0]}), + .B({b,b[1:0]}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +wire m_bomb = kbjoy[8]; +wire m_Serv = kbjoy[9]; + +scramble_top scramble +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + + .O_AUDIO(audio), + + .button_in(~{m_start2, m_fire, m_coin, m_start1, m_right, m_left, m_down, m_up}), + .RESET(status[0] | status[6] | buttons[1]), + .clk(clk_sys), + .ena_12(ce_12), + .ena_6(ce_6p), + .ena_6b(ce_6n), + .ena_1_79(ce_1p79) +); +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/build_id.tcl b/Arcade/Scramble Hardware/Scramble_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/build_id.v b/Arcade/Scramble Hardware/Scramble_MiST/rtl/build_id.v new file mode 100644 index 00000000..fe075b4c --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "153907" diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/dac.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/dpram.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/hq2x.sv b/Arcade/Scramble Hardware/Scramble_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd new file mode 100644 index 00000000..d415d932 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/i82c55.vhd @@ -0,0 +1,686 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity I82C55 is + port ( + + I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_CS_L : in std_logic; + I_RD_L : in std_logic; + I_WR_L : in std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_PC : in std_logic_vector(7 downto 0); + O_PC : out std_logic_vector(7 downto 0); + O_PC_OE_L : out std_logic_vector(7 downto 0); + + RESET : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + CLK : in std_logic + ); +end; + +architecture RTL of I82C55 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(I_DATA) + begin + bit_mask <= x"01"; + case I_DATA(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and I_DATA(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (I_CS_L = '0') and (I_WR_L = '0') then + case I_ADDR is + when "00" => r_porta <= I_DATA; + when "01" => r_portb <= I_DATA; + when "10" => r_portc <= I_DATA; + + when "11" => if (I_DATA(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= I_DATA; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + p_oe : process(I_CS_L, I_RD_L) + begin + O_DATA_OE_L <= '1'; + if (I_CS_L = '0') and (I_RD_L = '0') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read) + begin + O_DATA <= x"00"; -- default + --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required + case I_ADDR is + when "00" => O_DATA <= porta_read; + when "01" => O_DATA <= portb_read; + when "10" => O_DATA <= portc_read; + when "11" => O_DATA <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (I_CS_L = '0') and (I_ADDR = "00") then + porta_we <= not I_WR_L; + porta_re <= not I_RD_L; + end if; + + if (I_CS_L = '0') and (I_ADDR = "01") then + portb_we <= not I_WR_L; + portb_re <= not I_RD_L; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= I_DATA(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= I_DATA(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= I_DATA(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + O_PA <= x"FF"; -- if not driven, float high + O_PA_OE_L <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= I_PA; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_control, groupb_mode, r_portb, I_PB, portb_ipreg) + begin + O_PB <= x"FF"; -- if not driven, float high + O_PB_OE_L <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= I_PB; + else -- strobed mode + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + O_PC <= x"FF"; -- if not driven, float high + O_PC_OE_L <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + O_PC (7 downto 4) <= r_portc(7 downto 4); + O_PC_OE_L(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + O_PC (5 downto 4) <= r_portc(5 downto 4); + O_PC_OE_L(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + O_PC (7 downto 6) <= r_portc(7 downto 6); + O_PC_OE_L(7 downto 6) <= "00"; + end if; + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + O_PC (3) <= r_portc(3); + O_PC_OE_L(3) <= '0'; + end if; + -- + else -- stolen + O_PC (3) <= a_intr; + O_PC_OE_L(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + O_PC (2 downto 0) <= r_portc(2 downto 0); + O_PC_OE_L(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + O_PC (1) <= b_obf_l; + O_PC_OE_L(1) <= '0'; + else -- input + O_PC (1) <= b_ibf; + O_PC_OE_L(1) <= '0'; + end if; + O_PC (0) <= b_intr; + O_PC_OE_L(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= I_PC(6); + else -- port a input + a_stb_l <= I_PC(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= I_PC(6); + a_stb_l <= I_PC(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= I_PC(2); + else -- input + b_stb_l <= I_PC(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= I_PC(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= I_PC(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= I_PA; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= I_PB; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/keyboard.v b/Arcade/Scramble Hardware/Scramble_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/mist_io.v b/Arcade/Scramble Hardware/Scramble_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/osd.v b/Arcade/Scramble Hardware/Scramble_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/pll.qip b/Arcade/Scramble Hardware/Scramble_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/pll.v b/Arcade/Scramble Hardware/Scramble_MiST/rtl/pll.v new file mode 100644 index 00000000..1d3529bd --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 78, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 71, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57627100" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/scandoubler.v b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble.vhd new file mode 100644 index 00000000..ff810859 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble.vhd @@ -0,0 +1,587 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE is + port ( + I_HWSEL_FROGGER : in boolean; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + -- to audio board + -- + O_ADDR : out std_logic_vector(15 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + I_DATA_OE_L : in std_logic; + O_RD_L : out std_logic; + O_WR_L : out std_logic; + O_IOPC7 : out std_logic; + O_RESET_WD_L : out std_logic; + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + -- + RESET : in std_logic; -- active high + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE is + + type array_4x8 is array (0 to 3) of std_logic_vector(7 downto 0); + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal reset_wd_l : std_logic; + + -- timing decode + signal do_hsync : boolean; + signal set_vblank : boolean; + signal vsync : std_logic; + signal hsync : std_logic; + signal vblank : std_logic; + signal hblank : std_logic; + -- + -- cpu + signal cpu_ena : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal page_4to7_l : std_logic; + + signal wren : std_logic; + + signal objen_l : std_logic; + signal waen_l : std_logic; + + signal objramrd_l : std_logic; + signal vramrd_l : std_logic; + + signal select_l : std_logic; + signal objramwr_l : std_logic; + signal vramwr_l : std_logic; + + -- control reg + signal control_reg : std_logic_vector(7 downto 0); + signal intst_l : std_logic; + signal iopc7 : std_logic; + signal pout1 : std_logic; + signal starson : std_logic; + signal hcma : std_logic; + signal vcma : std_logic; + + signal pgm_rom_dout : array_4x8; + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + signal ram_ena : std_logic; + + signal vram_data : std_logic_vector(7 downto 0); + +begin + + O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + set_vblank <= (vcnt = "111101111"); -- 1EF + end process; + + p_sync : process + begin + wait until rising_edge(CLK); + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + if (ENA = '1') then + if (hcnt = "010000001") then -- 081 + hblank <= '1'; + elsif (hcnt = "011111111") then -- 0f9 + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if set_vblank then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + p_video_timing_reg : process + begin + wait until rising_edge(CLK); + -- match output delay in video module + if (ENA = '1') then + O_HSYNC <= HSYNC; + O_VSYNC <= VSYNC; + end if; + end process; + + p_cpu_ena : process(hcnt, ENA) + begin + -- cpu clocked on rising edge of 1h, late + cpu_ena <= ENA and hcnt(0); -- 1h + end process; + -- + -- video + -- + u_video : entity work.SCRAMBLE_VIDEO + port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_HCNT => hcnt, + I_VCNT => vcnt, + I_VBLANK => vblank, + I_VSYNC => vsync, + + I_VCMA => vcma, + I_HCMA => hcma, + -- + I_CPU_ADDR => cpu_addr, + I_CPU_DATA => cpu_data_out, + O_VRAM_DATA => vram_data, + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L => vramwr_l, + I_VRAMRD_L => vramrd_l, + I_OBJRAMWR_L => objramwr_l, + I_OBJRAMRD_L => objramrd_l, + I_OBJEN_L => objen_l, + -- + I_STARSON => starson, + I_POUT1 => pout1, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + -- + ENA => ENA, + ENAB => ENAB, + ENA_12 => ENA_12, + CLK => CLK + ); + + -- other cpu signals + reset_wd_l <= not RESET; -- FIX + + p_cpu_wait : process(vblank, hblank, waen_l) + begin + -- this is done a bit differently, the original had a late + -- clock to the cpu, and as mreq came out a litle early it could assert + -- wait and then gate off the write strobe to vram/objram in time. + -- + -- we are a nice synchronous system therefore we need to do this combinatorially. + -- timing is still ok. + -- + if (vblank = '1') then + cpu_wait_l <='1'; + else + cpu_wait_l <= '1'; + if (hblank = '0') and (waen_l = '0') then + cpu_wait_l <= '0'; + end if; + end if; + end process; + wren <= cpu_wait_l; + + p_cpu_int : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (intst_l = '0') then + cpu_nmi_l <= '1'; + else + if do_hsync and set_vblank then + cpu_nmi_l <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => reset_wd_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => open, + MREQ_n => cpu_mreq_l, + IORQ_n => open, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode : process(cpu_rfsh_l, cpu_rd_l, cpu_wr_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + begin + -- Scramble map + --0000-3fff ROM + --4000-47ff RAM + --4800-4bff Video RAM + --5000-50ff Object RAM + --5000-503f screen attributes + --5040-505f sprites + --5060-507f bullets + --5080-50ff unused? + + --read: + --7000 Watchdog Reset (Scramble) + --8100 IN0 + --8101 IN1 + --8102 IN2 (bits 5 and 7 used for protection check in Scramble) + + --write: + --6800-6807 control reg + --8200 To AY-3-8910 port A (commands for the audio CPU) + --8201 bit 3 = interrupt trigger on audio CPU bit 4 = AMPM (?) + --8202 protection check control? + + -- Frogger map + --0000-3fff ROM + --8000-87ff RAM + --a800-abff Video RAM + --b000-b0ff Object RAM + --b000-b03f screen attributes + --b040-b05f sprites + --b060-b0ff unused? + + --read: + --8800 Watchdog Reset + --e000 IN0 + --e002 IN1 + --e004 IN2 + cpu_int_l <= '1'; + cpu_busrq_l <= '1'; + + page_4to7_l <= '1'; + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + + if I_HWSEL_FROGGER then + cpu_int_l <= '0'; + cpu_busrq_l <= cpu_addr(15); + end if; + + if not I_HWSEL_FROGGER then + if (cpu_addr(15 downto 14) = "01") then page_4to7_l <= '0'; end if; + else + if (cpu_addr(15 downto 14) = "10") then page_4to7_l <= '0'; end if; + end if; + end if; + + end process; + + p_mem_decode2 : process(I_HWSEL_FROGGER, cpu_addr, page_4to7_l, cpu_rfsh_l, cpu_rd_l, cpu_wr_l, wren) + begin + waen_l <= '1'; + objen_l <= '1'; + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "001") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objen_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "101") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objen_l <= '0'; end if; + end if; + end if; + + -- read decode + vramrd_l <= '1'; + objramrd_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "001") then vramrd_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramrd_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "101") then vramrd_l <= '0'; end if; + end if; + end if; + -- write decode + vramwr_l <= '1'; + objramwr_l <= '1'; + select_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "001") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "101") then select_l <= '0'; end if; -- control reg + end if; + else + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "101") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "111") then select_l <= '0'; end if; -- control reg + end if; + end if; + end process; + + p_control_reg : process + variable addr : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- scramble + --6801 interrupt enable + --6802 coin counter + --6803 ? (POUT1) + --6804 stars on + --6805 ? (POUT2) + --6806 screen vertical flip + --6807 screen horizontal flip + if not I_HWSEL_FROGGER then + addr := cpu_addr(2 downto 0); + else + addr := cpu_addr(4 downto 2); + end if; + + dec := "00000000"; + if (select_l = '0') then + case addr(2 downto 0) is + when "000" => dec := "00000001"; + when "001" => dec := "00000010"; + when "010" => dec := "00000100"; + when "011" => dec := "00001000"; + when "100" => dec := "00010000"; + when "101" => dec := "00100000"; + when "110" => dec := "01000000"; + when "111" => dec := "10000000"; + when others => null; + end case; + end if; + + if (reset_wd_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (dec(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_control_reg_assign : process(control_reg, I_HWSEL_FROGGER) + begin + if not I_HWSEL_FROGGER then + -- Scramble + intst_l <= control_reg(1); + iopc7 <= control_reg(2); + pout1 <= control_reg(3); + starson <= control_reg(4); + hcma <= control_reg(6); + vcma <= control_reg(7); + else + intst_l <= control_reg(2); + iopc7 <= control_reg(6); + pout1 <= control_reg(7); + starson <= '0'; + hcma <= control_reg(4); + vcma <= control_reg(3); + end if; + end process; + -- + -- + -- roms / rams + pgm_rom : entity work.ROM_PGM + port map (CLK => CLK, ADDR => cpu_addr(13 downto 0), DATA => rom_dout); +-- pgm_rom01 : entity work.ROM_PGM_01 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(0)); +-- pgm_rom23 : entity work.ROM_PGM_23 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(1)); +-- pgm_rom45 : entity work.ROM_PGM_45 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(2)); +-- pgm_rom56 : entity work.ROM_PGM_67 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(3)); + +-- p_rom_mux : process(cpu_addr, pgm_rom_dout) +-- begin +-- rom_dout <= (others => '0'); +-- case cpu_addr(13 downto 12) is +-- when "00" => rom_dout <= pgm_rom_dout(0); +-- when "01" => rom_dout <= pgm_rom_dout(1); +-- when "10" => rom_dout <= pgm_rom_dout(2); +-- when "11" => rom_dout <= pgm_rom_dout(3); +-- when others => null; +-- end case; +-- end process; + + u_cpu_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => ram_ena and (not cpu_wr_l), + + addr_a_i => cpu_addr(10 downto 0), + data_a_i => cpu_data_out, + + clk_b_i => clk, + addr_b_i => cpu_addr(10 downto 0), + data_b_o => ram_dout + ); + + p_ram_ctrl : process(cpu_addr, page_4to7_l) + begin + ram_ena <= '0'; + if (page_4to7_l = '0') and (cpu_addr(13 downto 11) = "000") then + ram_ena <= '1'; + end if; + end process; + + p_cpu_data_in_mux : process(I_HWSEL_FROGGER, cpu_addr, cpu_rd_l, cpu_mreq_l, cpu_rfsh_l, ram_dout, rom_dout, vramrd_l, vram_data, I_DATA_OE_L, I_DATA ) + variable ram_addr : std_logic_vector(1 downto 0); + begin + + if not I_HWSEL_FROGGER then + ram_addr := "01"; + else + ram_addr := "10"; + end if; + + cpu_data_in <= (others => '0'); + if (vramrd_l = '0') then + cpu_data_in <= vram_data; + -- + elsif (I_DATA_OE_L = '0') then + cpu_data_in <= I_DATA; + -- + elsif (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(15 downto 14) = "00") and (cpu_rd_l = '0') and (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + cpu_data_in <= rom_dout; + -- + elsif (cpu_addr(15 downto 14) = ram_addr) then + if (cpu_addr(13 downto 11) = "000") and (cpu_rd_l = '0') then + cpu_data_in <= ram_dout; + else + cpu_data_in <= x"FF"; + end if; + end if; + else + cpu_data_in <= x"FF"; + end if; + + end process; + + -- to audio + O_ADDR <= cpu_addr; + O_DATA <= cpu_data_out; + O_RD_L <= cpu_rd_l; + O_WR_L <= cpu_wr_l; + O_IOPC7 <= iopc7; + O_RESET_WD_L <= reset_wd_l; + +end RTL; \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd new file mode 100644 index 00000000..bfa13763 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_audio.vhd @@ -0,0 +1,842 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_AUDIO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_ADDR : in std_logic_vector(15 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + O_DATA_OE_L : out std_logic; + -- + I_RD_L : in std_logic; + I_WR_L : in std_logic; + I_IOPC7 : in std_logic; + -- + O_AUDIO : out std_logic_vector( 9 downto 0); + -- + I_1P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_SERVICE : in std_logic; + I_COIN1 : in std_logic; + I_COIN2 : in std_logic; + O_COIN_COUNTER : out std_logic; + -- + I_DIP : in std_logic_vector( 5 downto 1); + -- + I_RESET_L : in std_logic; + ENA : in std_logic; -- 6 MHz + ENA_1_79 : in std_logic; -- 1.78975 MHz + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE_AUDIO is + + signal reset : std_logic; + signal cpu_ena : std_logic; + signal cpu_ena_gated : std_logic; + -- + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + -- + signal ram_cs : std_logic; + signal rom_oe : std_logic; + signal filter_load : std_logic; + signal filter_reg : std_logic_vector(11 downto 0); + -- + signal cpu_rom0_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom1_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom2_dout : std_logic_vectoR(7 downto 0); + signal rom_active : std_logic; + + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + -- + signal i8255_addr : std_logic_vector(1 downto 0); + signal i8255_1D_data : std_logic_vector(7 downto 0); + signal i8255_1D_data_oe_l : std_logic; + signal i8255_1D_cs_l : std_logic; + signal i8255_1D_pa_out : std_logic_vector(7 downto 0); + signal i8255_1D_pb_out : std_logic_vector(7 downto 0); + -- + signal i8255_1E_data : std_logic_vector(7 downto 0); + signal i8255_1E_data_oe_l : std_logic; + signal i8255_1E_cs_l : std_logic; + signal i8255_1E_pa : std_logic_vector(7 downto 0); + signal i8255_1E_pb : std_logic_vector(7 downto 0); + signal i8255_1E_pc : std_logic_vector(7 downto 0); + + -- security + signal net_1e10_i : std_logic; + signal net_1e12_i : std_logic; + signal xb : std_logic_vector(7 downto 0); + signal xbo : std_logic_vector(7 downto 0); + + signal audio_div_cnt : std_logic_vector( 8 downto 0) := (others => '0'); + signal ls90_op : std_logic_vector(3 downto 0); + signal ls90_clk : std_logic; + signal ls90_cnt : std_logic_vector( 3 downto 0) := (others => '0'); + -- ym2149 3C + signal ym2149_3C_dv : std_logic_vector(7 downto 0); + signal ym2149_3C_oe_l : std_logic; + signal ym2149_3C_bdir : std_logic; + signal ym2149_3C_bc2 : std_logic; + signal ym2149_3C_bc1 : std_logic; + signal ym2149_3C_audio : std_logic_vector(7 downto 0); + signal ym2149_3C_chan : std_logic_vector(1 downto 0); + signal ym2149_3C_chan_t1 : std_logic_vector(1 downto 0); + -- + -- ym2149 3D + signal ym2149_3D_dv : std_logic_vector(7 downto 0); + signal ym2149_3D_oe_l : std_logic; + signal ym2149_3D_bdir : std_logic; + signal ym2149_3D_bc2 : std_logic; + signal ym2149_3D_bc1 : std_logic; + signal ym2149_3D_audio : std_logic_vector(7 downto 0); + signal ym2149_3D_chan : std_logic_vector(1 downto 0); + signal ym2149_3D_chan_t1 : std_logic_vector(1 downto 0); + signal ym2149_3D_ioa_in : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_out : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_oe_l : std_logic; + signal ym2149_3D_iob_in : std_logic_vector(7 downto 0); + -- + signal ampm : std_logic; + signal sint : std_logic; + signal sint_t1 : std_logic; + -- + signal audio_3C_mix : std_logic_vector(9 downto 0); + signal audio_3C_final : std_logic_vector(9 downto 0); + signal audio_3D_mix : std_logic_vector(9 downto 0); + signal audio_3D_final : std_logic_vector(9 downto 0); + signal audio_final : std_logic_vector(10 downto 0); + + signal security_count : std_logic_vector(2 downto 0); + signal rd_l_t1 : std_logic; + -- filters + signal ym2149_3C_k : std_logic_vector(16 downto 0); + signal ym2149_3D_k : std_logic_vector(16 downto 0); + signal audio_in_m_out_3C : std_logic_vector(17 downto 0); + signal audio_in_m_out_3D : std_logic_vector(17 downto 0); + signal audio_mult_3C : std_logic_vector(35 downto 0); + signal audio_mult_3D : std_logic_vector(35 downto 0); + + + + type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0); + constant K_Filter : array_4of17 := ('0' & x"00A3", + '0' & x"00C6", + '0' & x"039D", + '1' & x"0000" ); + + type filter_pipe is array (3 downto 0) of std_logic_vector(17 downto 0); + signal ym2149_3C_audio_pipe : filter_pipe; + signal ym2149_3D_audio_pipe : filter_pipe; + -- LP filter out = in.k + out_t1.(1-k) + -- + -- = (in-out_t1).k + out_t1 + -- + -- using + -- -(Ts.2.PI.Fc) + -- k = 1-e + -- + -- sampling freq = 1.79 MHz + -- + -- cut off freqs bit 0 1 + -- + --0.267uf ~ 713 Hz 1 1 0.00249996 x 00A3 + --0.220uf ~ 865 Hz 1 0 0.00303210 x 00C6 + --0.047uf ~ 4050 Hz 0 1 0.01411753 x 039D + -- 0 0 x10000 + +begin + -- scramble + --0000-1fff ROM + --8000-83ff RAM + + -- frogger + --0000-17ff ROM + --4000-43ff RAM + + cpu_ena <= '1'; -- run at audio clock speed + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + cpu_wait_l <= '1'; + -- + cpu_ena_gated <= ENA_1_79 and cpu_ena; + u_cpu : entity work.T80sed + port map ( + RESET_n => I_RESET_L, + CLK_n => CLK, + CLKEN => cpu_ena_gated, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + p_cpu_int : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + cpu_int_l <= '1'; + sint_t1 <= '0'; + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + sint_t1 <= sint; + + if (cpu_m1_l = '0') and (cpu_iorq_l = '0') then + cpu_int_l <= '1'; + elsif (sint = '0') and (sint_t1 = '1') then + cpu_int_l <= '0'; + end if; + end if; + end if; + end process; + + p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + variable decode : std_logic; + begin + if not I_HWSEL_FROGGER then + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(12)); + else + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(14) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(13) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(13)); + end if; + + rom_oe <= '0'; + if not I_HWSEL_FROGGER then + if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + else + if (cpu_addr(14) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + end if; + + end process; + + u_rom_5c : entity work.ROM_SND_0 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom0_dout + ); + + u_rom_5d : entity work.ROM_SND_1 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom1_dout + ); + + u_rom_5e : entity work.ROM_SND_2 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom2_dout + ); + + p_rom_mux : process(I_HWSEL_FROGGER, cpu_rom0_dout, cpu_rom1_dout, cpu_rom2_dout, cpu_addr, rom_oe) + variable rom_oe_decode : std_logic; + variable cpu_rom0_dout_s : std_logic_vector(7 downto 0); + begin + if not I_HWSEL_FROGGER then + cpu_rom0_dout_s := cpu_rom0_dout; + else -- swap bits 0 and 1 + cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1); + end if; + + rom_dout <= (others => '0'); + rom_oe_decode := '0'; + case cpu_addr(13 downto 11) is + when "000" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1'; + when "001" => rom_dout <= cpu_rom1_dout; rom_oe_decode := '1'; + when "010" => rom_dout <= cpu_rom2_dout; rom_oe_decode := '1'; + when others => null; + end case; + + rom_active <= '0'; + if (rom_oe = '1') then + rom_active <= rom_oe_decode; + end if; + end process; + + u_ram_6c_6d : work.dpram generic map (10,8) + port map + ( + addr_a_i => cpu_addr(9 downto 0), + data_a_i => cpu_data_out, + clk_b_i => clk, + addr_b_i => cpu_addr(9 downto 0), + data_b_o => ram_dout, + we_i => ram_cs and (not cpu_wr_l), + en_a_i => ENA_1_79, + clk_a_i => clk + ); + + p_cpu_data_mux : process(rom_dout, rom_active, ram_dout, ym2149_3C_oe_l, ym2149_3C_dv, ym2149_3D_oe_l, ym2149_3D_dv, ram_cs, cpu_wr_l) + begin + if (rom_active = '1') then + cpu_data_in <= rom_dout; + elsif (ram_cs = '1') and (cpu_wr_l = '1') then + cpu_data_in <= ram_dout; + elsif (ym2149_3C_oe_l = '0') then + cpu_data_in <= ym2149_3C_dv; + elsif (ym2149_3D_oe_l = '0') then + cpu_data_in <= ym2149_3D_dv; + else + cpu_data_in <= (others => '1'); -- float high + end if; + end process; + + p_filter_reg : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + if (filter_load = '1') then + filter_reg <= cpu_addr(11 downto 0); + end if; + end if; + end process; + + p_8255_decode : process(I_RESET_L, I_ADDR, I_HWSEL_FROGGER) + begin + reset <= not I_RESET_L; + i8255_1D_cs_l <= '1'; + i8255_1E_cs_l <= '1'; + + if not I_HWSEL_FROGGER then + -- the interface one + if (I_ADDR(9) = '1') and (I_ADDR(15) = '1') then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(8) = '1') and (I_ADDR(15) = '1') then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(1 downto 0); + else + -- the interface one + if (I_ADDR(12) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(13) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(2 downto 1); + end if; + end process; + + p_ym_decode : process(cpu_rd_l, cpu_wr_l, cpu_iorq_l, cpu_addr, I_HWSEL_FROGGER) + variable rd_3c : std_logic; + variable wr_3c : std_logic; + variable ad_3c : std_logic; + -- + variable rd_3d : std_logic; + variable wr_3d : std_logic; + variable ad_3d : std_logic; + begin + + --bdir bc2 bc1 + -- 0 0 0 nop + -- 0 0 1 addr latch < WR_L AV4 / AV6 + -- 0 1 0 nop + -- 0 1 1 data read < RD_L AV5 / AV7 + + -- 1 0 0 addr latch + -- 1 0 1 nop + -- 1 1 0 data write < WR_L AV5 / AV7 + -- 1 1 1 addr latch + + + if not I_HWSEL_FROGGER then + rd_3c := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(5); + wr_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(5); + ad_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(4); + else + rd_3c := '0'; + wr_3c := '0'; + ad_3c := '0'; + end if; + + ym2149_3C_bdir <= wr_3c; + ym2149_3C_bc2 <= rd_3c or wr_3c; + ym2149_3C_bc1 <= rd_3c or ad_3c; + + + if not I_HWSEL_FROGGER then + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(7); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + else + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(6); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + end if; + + ym2149_3D_bdir <= wr_3d; + ym2149_3D_bc2 <= rd_3d or wr_3d; + ym2149_3D_bc1 <= rd_3d or ad_3d; + + end process; + + i8255_1E_pa(7) <= I_COIN1; + i8255_1E_pa(6) <= I_COIN2; + i8255_1E_pa(5) <= I_1P_CTRL(3); -- left + i8255_1E_pa(4) <= I_1P_CTRL(2); -- right + i8255_1E_pa(3) <= I_1P_CTRL(4); -- shoot1 + i8255_1E_pa(2) <= I_SERVICE; + i8255_1E_pa(1) <= I_1P_CTRL(5); -- shoot2 + i8255_1E_pa(0) <= I_2P_CTRL(1); -- up + + i8255_1E_pb(7) <= I_1P_CTRL(6); -- start + i8255_1E_pb(6) <= I_2P_CTRL(6); -- start + i8255_1E_pb(5) <= I_2P_CTRL(3); -- left + i8255_1E_pb(4) <= I_2P_CTRL(2); -- right + i8255_1E_pb(3) <= I_2P_CTRL(4); -- shoot1 + i8255_1E_pb(2) <= I_2P_CTRL(5); -- shoot2 + i8255_1E_pb(1) <= I_DIP(1); + i8255_1E_pb(0) <= I_DIP(2); + + i8255_1E_pc(7) <= net_1e10_i; + i8255_1E_pc(6) <= I_1P_CTRL(0); -- down + i8255_1E_pc(5) <= net_1e12_i; + i8255_1E_pc(4) <= I_1P_CTRL(1); -- up + i8255_1E_pc(3) <= I_DIP(3); + i8255_1E_pc(2) <= I_DIP(4); + i8255_1E_pc(1) <= I_DIP(5); + i8255_1E_pc(0) <= I_2P_CTRL(0); -- down + O_COIN_COUNTER <= not I_IOPC7; -- open drain actually + + -- + -- PIA CHIPS + -- + u_i8255_1D : entity work.I82C55 -- bus interface + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1D_data, + O_DATA_OE_L => i8255_1D_data_oe_l, + + I_CS_L => i8255_1D_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1D_pa_out, + O_PA => i8255_1D_pa_out, + O_PA_OE_L => open, + + I_PB => i8255_1D_pb_out, + O_PB => i8255_1D_pb_out, + O_PB_OE_L => open, + + I_PC => xbo, + O_PC => xb, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + u_i8255_1E : entity work.I82C55 -- push button + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1E_data, + O_DATA_OE_L => i8255_1E_data_oe_l, + + I_CS_L => i8255_1E_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1E_pa, + O_PA => open, + O_PA_OE_L => open, + + I_PB => i8255_1E_pb, + O_PB => open, + O_PB_OE_L => open, + + I_PC => i8255_1E_pc, + O_PC => open, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + p_i8255_1d_bus_control : process(i8255_1D_pa_out, i8255_1D_pb_out, ym2149_3D_ioa_out, ym2149_3D_ioa_oe_l) + begin + if (ym2149_3D_ioa_oe_l = '0') then + ym2149_3D_ioa_in <= ym2149_3D_ioa_out; + else + ym2149_3D_ioa_in <= i8255_1D_pa_out; + end if; + + ampm <= i8255_1D_pb_out(4); -- amp mute + sint <= i8255_1D_pb_out(3); -- set int + end process; + + p_drive_cpubus : process(i8255_1D_data, i8255_1D_data_oe_l, i8255_1E_data, i8255_1E_data_oe_l) + begin + O_DATA_OE_L <= '1'; + O_DATA <= (others => '0'); + -- + if (i8255_1D_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1D_data; + elsif (i8255_1E_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1E_data; + end if; + end process; + -- + -- AUDIO CHIPS + -- + p_audio_clockgen : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + audio_div_cnt <= audio_div_cnt - "1"; + ls90_clk <= not audio_div_cnt(8); + + if (audio_div_cnt(8 downto 0) = "000000000") then + if (ls90_cnt = x"9") then + ls90_cnt <= x"0"; + else + ls90_cnt <= ls90_cnt + "1"; + end if; + end if; + + ls90_op <= "0000"; + case ls90_cnt is --ls90 outputs DCBA + when x"0" => ls90_op <= "0000"; + when x"1" => ls90_op <= "0010"; + when x"2" => ls90_op <= "0100"; + when x"3" => ls90_op <= "0110"; + when x"4" => ls90_op <= "1000"; + when x"5" => ls90_op <= "0001"; + when x"6" => ls90_op <= "0011"; + when x"7" => ls90_op <= "0101"; + when x"8" => ls90_op <= "0111"; + when x"9" => ls90_op <= "1001"; + when others => ls90_op <= "0000"; + end case; + end if; + end process; + + p_ym2149_3d_iob_in : process(I_HWSEL_FROGGER, ls90_op, ls90_clk) + begin + if not I_HWSEL_FROGGER then + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & ls90_op(2) & ls90_clk & "1110"; + else + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & '1' & ls90_clk & ls90_op(2) & "110"; + end if; + end process; + + u_ym2149_3C : entity work.YM2149 -- not used for frogger + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3C_dv, + O_DA_OE_L => ym2149_3C_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3C_bdir, + I_BC2 => ym2149_3C_bc2, + I_BC1 => ym2149_3C_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3C_audio, + O_CHAN => ym2149_3C_chan, + -- port a + I_IOA => "11111111", + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => "11111111", + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + u_ym2149_3D : entity work.YM2149 + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3D_dv, + O_DA_OE_L => ym2149_3D_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3D_bdir, + I_BC2 => ym2149_3D_bc2, + I_BC1 => ym2149_3D_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3D_audio, + O_CHAN => ym2149_3D_chan, + -- port a + I_IOA => ym2149_3D_ioa_in, + O_IOA => ym2149_3D_ioa_out, + O_IOA_OE_L => ym2149_3D_ioa_oe_l, + -- port b + I_IOB => ym2149_3D_iob_in, + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + p_filter_coef : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + case ym2149_3C_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3C_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(5 downto 4))); + when "10" => -- chan 1 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(3 downto 2))); + when "01" => -- chan 0 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(1 downto 0))); + when others => null; + end case; + + case ym2149_3D_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3D_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg(11 downto 10))); + when "10" => -- chan 1 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 9 downto 8))); + when "01" => -- chan 0 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 7 downto 6))); + when others => null; + end case; + end if; + end process; + + + p_ym2149_audio_process : process(ym2149_3C_audio, ym2149_3C_audio_pipe, ym2149_3D_audio, ym2149_3D_audio_pipe) + begin + audio_in_m_out_3C <= (('0' & ym2149_3C_audio & "000000000"))- ym2149_3C_audio_pipe(3); -- signed + audio_in_m_out_3D <= (('0' & ym2149_3D_audio & "000000000"))- ym2149_3D_audio_pipe(3); -- signed + end process; + + mult_3C : work.MULT18X18 + port map + ( + P => audio_mult_3C,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3C, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3C_k + ); + + mult_3D : work.MULT18X18 + port map + ( + P => audio_mult_3D,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3D, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3D_k + ); + + p_ym2149_audio_pipe : process(I_RESET_L, CLK) + begin + if (I_RESET_L = '0') then + ym2149_3C_audio_pipe <= (others => (others => '0')); + ym2149_3D_audio_pipe <= (others => (others => '0')); + elsif rising_edge(CLK) then +-- audio_mult_3C <= audio_in_m_out_3C * ym2149_3C_k; +-- audio_mult_3D <= audio_in_m_out_3D * ym2149_3D_k; + if (ENA_1_79 = '1') then + -- we need some holding registers anyway, so lets just make it a shift and save a mux + ym2149_3C_audio_pipe(3 downto 1) <= ym2149_3C_audio_pipe(2 downto 0); + ym2149_3C_audio_pipe(0) <= audio_mult_3C(33 downto 16) + ym2149_3C_audio_pipe(3); -- bit 33 sign + + ym2149_3D_audio_pipe(3 downto 1) <= ym2149_3D_audio_pipe(2 downto 0); + ym2149_3D_audio_pipe(0) <= audio_mult_3D(33 downto 16) + ym2149_3D_audio_pipe(3); -- bit 33 sign + end if; + end if; + end process; + + p_ym2149_audio_mix : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + ym2149_3C_chan_t1 <= ym2149_3C_chan; + ym2149_3D_chan_t1 <= ym2149_3D_chan; + + if (ym2149_3C_chan_t1 = "11") then + audio_3C_mix <= (others => '0'); + audio_3C_final <= audio_3C_mix; + else + audio_3C_mix <= audio_3C_mix + ("00" & ym2149_3C_audio_pipe(0)(16 downto 9)); + end if; + + if (ym2149_3D_chan_t1(1 downto 0) = "11") then + audio_3D_mix <= (others => '0'); + audio_3D_final <= audio_3D_mix; + else + audio_3D_mix <= audio_3D_mix + ("00" & ym2149_3D_audio_pipe(0)(16 downto 9)); + end if; + + audio_final <= ('0' & audio_3C_final) + ('0' & audio_3D_final); + end if; + end process; + + p_audio_out : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + O_AUDIO <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + if (ampm = '1') then + O_AUDIO <= (others => '0'); + else + if (audio_final(10) = '1') then + O_AUDIO <= (others => '1'); + else + O_AUDIO <= audio_final(9 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_security_6J : process(xb) + begin + -- chip K10A PAL16L8 + -- equations from Mark @ http://www.leopardcats.com/ + xbo(3 downto 0) <= xb(3 downto 0); + xbo(4) <= not(xb(0) or xb(1) or xb(2) or xb(3)); + xbo(5) <= not((not xb(2) and not xb(0)) or (not xb(2) and not xb(1)) or (not xb(3) and not xb(0)) or (not xb(3) and not xb(1))); + + xbo(6) <= not(not xb(0) and not xb(3)); + xbo(7) <= not((not xb(1)) or xb(2)); + end process; + + p_security_count : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + security_count <= "000"; + elsif rising_edge(CLK) then + rd_l_t1 <= i_rd_l; + if (I_ADDR = x"8102") and (I_RD_L = '0') and (rd_l_t1 = '1') then + security_count <= security_count + "1"; + end if; + end if; + end process; + + p_security_2B : process(security_count) + begin + -- I am not sure what this chip does yet, but this gets us past the initial check for now. + case security_count is + when "000" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "001" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "010" => net_1e10_i <= '1'; net_1e12_i <= '0'; + when "011" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "100" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "101" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "110" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "111" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when others => null; + end case; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd new file mode 100644 index 00000000..823bdf6f --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_top.vhd @@ -0,0 +1,242 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_TOP is +port ( + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + + O_AUDIO : out std_logic_vector(9 downto 0); + + button_in : in std_logic_vector(7 downto 0); + + RESET : in std_logic; + clk : in std_logic; -- 25 + ena_12 : in std_logic; -- 6.25 x 2 + ena_6 : in std_logic; -- 6.25 (inverted) + ena_6b : in std_logic; -- 6.25 + ena_1_79 : in std_logic -- 1.786 +); +end; + +architecture RTL of SCRAMBLE_TOP is +-- this MUST be set true for frogger +-- this MUST be set false for scramble, the_end, amidar +constant I_HWSEL_FROGGER : boolean := false; + +-- ip registers +signal ip_1p : std_logic_vector(6 downto 0); +signal ip_2p : std_logic_vector(6 downto 0); +signal ip_service : std_logic; +signal ip_coin1 : std_logic; +signal ip_coin2 : std_logic; +signal ip_dip_switch : std_logic_vector(5 downto 1); + +-- ties to audio board +signal audio_addr : std_logic_vector(15 downto 0); +signal audio_data_out : std_logic_vector(7 downto 0); +signal audio_data_in : std_logic_vector(7 downto 0); +signal audio_data_oe_l : std_logic; +signal audio_rd_l : std_logic; +signal audio_wr_l : std_logic; +signal audio_iopc7 : std_logic; +signal audio_reset_l : std_logic; + +begin + +u_scramble : entity work.SCRAMBLE +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + O_HSYNC => O_HSYNC, + O_VSYNC => O_VSYNC, + O_HBLANK => O_HBLANK, + O_VBLANK => O_VBLANK, + -- + -- to audio board + -- + O_ADDR => audio_addr, + O_DATA => audio_data_out, + I_DATA => audio_data_in, + I_DATA_OE_L => audio_data_oe_l, + O_RD_L => audio_rd_l, + O_WR_L => audio_wr_l, + O_IOPC7 => audio_iopc7, + O_RESET_WD_L => audio_reset_l, + -- + ENA => ena_6, + ENAB => ena_6b, + ENA_12 => ena_12, + -- + RESET => reset, + CLK => clk +); + +-- +-- +-- audio subsystem +-- +u_audio : entity work.SCRAMBLE_AUDIO +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_ADDR => audio_addr, + I_DATA => audio_data_out, + O_DATA => audio_data_in, + O_DATA_OE_L => audio_data_oe_l, + -- + I_RD_L => audio_rd_l, + I_WR_L => audio_wr_l, + I_IOPC7 => audio_iopc7, + -- + O_AUDIO => O_AUDIO, + -- + I_1P_CTRL => ip_1p, -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL => ip_2p, -- start, shoot1, shoot2, left,right,up,down + I_SERVICE => ip_service, + I_COIN1 => ip_coin1, + I_COIN2 => ip_coin2, + O_COIN_COUNTER => open, + -- + I_DIP => ip_dip_switch, + -- + I_RESET_L => audio_reset_l, + ENA => ena_6, + ENA_1_79 => ena_1_79, + CLK => clk +); + +--button_in(0) = Joystick Up +--button_in(1) = Joystick Down +--button_in(2) = Joystick Left +--button_in(3) = Joystick Right +--button_in(4) = Button Left +--button_in(5) = Button Down +--button_in(6) = Joystick Fire +--button_in(7) = Button Right + +--Buttons are connected to ground and connect to 3.3V when pressed +--Joystick has internal pullup resistor and connects to ground when pressed + +--A '0' on the input is active. Inputs are active low. + +-- assign inputs +-- start, shoot1, shoot2, left,right,up,down +ip_1p(6) <= button_in(4); -- start 1 +ip_1p(5) <= button_in(6); -- shoot1 +ip_1p(4) <= button_in(6); -- shoot2 +ip_1p(3) <= button_in(2); -- p1 left +ip_1p(2) <= button_in(3); -- p1 right +ip_1p(1) <= button_in(0); -- p1 up +ip_1p(0) <= button_in(1); -- p1 down +-- +ip_2p(6) <= button_in(7); -- start 2 +ip_2p(5) <= button_in(6); +ip_2p(4) <= button_in(6); +ip_2p(3) <= button_in(2); -- p2 left +ip_2p(2) <= button_in(3); -- p2 right +ip_2p(1) <= button_in(0); -- p2 up +ip_2p(0) <= button_in(1); -- p2 down +-- +ip_service <= '1'; +ip_coin1 <= button_in(5); -- credit +ip_coin2 <= '1'; + +-- dip switch settings +scramble_dips : if (not I_HWSEL_FROGGER) generate +begin + --SW #1 SW #2 Rockets SW #3 Cabinet + ------- ----- --------- ----- -------- + --OFF OFF Unlimited OFF Table + --OFF ON 5 ON Up Right + --ON OFF 4 + --ON ON 3 + + + --SW #4 SW #5 Coins/Play + ------- ----- ---------- + --OFF OFF 4 + --OFF ON 3 + --ON OFF 2 + --ON ON 1 + + ip_dip_switch(5 downto 4) <= not "11"; -- 1 play/coin. + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "10"; +end generate; + +frogger_dips : if ( I_HWSEL_FROGGER) generate +begin + --1 2 3 4 5 Meaning + ------------------------------------------------------- + --On On 3 Frogs + --On Off 5 Frogs + --Off On 7 Frogs + --Off Off 256 Frogs (!) + -- + -- On Upright unit + -- Off Cocktail unit + -- + -- On On 1 coin 1 play + -- On Off 2 coins 1 play + -- Off On 3 coins 1 play + -- Off Off 1 coin 2 plays + + ip_dip_switch(5 downto 4) <= not "11"; + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "01"; +end generate; + +end RTL; \ No newline at end of file diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd new file mode 100644 index 00000000..6c1dcf24 --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/scramble_video.vhd @@ -0,0 +1,763 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_VIDEO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + I_VBLANK : in std_logic; + I_VSYNC : in std_logic; + + I_VCMA : in std_logic; + I_HCMA : in std_logic; + -- + I_CPU_ADDR : in std_logic_vector(15 downto 0); + I_CPU_DATA : in std_logic_vector(7 downto 0); + O_VRAM_DATA : out std_logic_vector(7 downto 0); + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L : in std_logic; + I_VRAMRD_L : in std_logic; + I_OBJRAMWR_L : in std_logic; + I_OBJRAMRD_L : in std_logic; + I_OBJEN_L : in std_logic; + -- + I_STARSON : in std_logic; + I_POUT1 : in std_logic; + -- + O_VIDEO_R : out std_logic_vector(3 downto 0); + O_VIDEO_G : out std_logic_vector(3 downto 0); + O_VIDEO_B : out std_logic_vector(3 downto 0); + -- + ENA : in std_logic; + ENAB : in std_logic; + ENA_12 : in std_logic; + CLK : in std_logic + ); +end; + +-- chars stars vidout? shell/missile +-- +-- 220R B 100 B 390R B 100R R +-- 470R B 150 B 100R G +-- 220R G 100 G blue ? +-- 470R G 150 G +-- 1K G 100 R +-- 220R R 150 R +-- 470R R +-- 1K R +architecture RTL of SCRAMBLE_VIDEO is + + type array_3x5 is array (2 downto 0) of std_logic_vector(4 downto 0); + -- timing + signal ld : std_logic; + signal h256_l : std_logic; + signal h256 : std_logic; + signal cblank_s : std_logic; + signal hcmp1_s : std_logic; + signal hcmp2_s : std_logic; + signal hcmp1 : std_logic; + signal hcmp2 : std_logic; + signal cblank_l : std_logic; + signal h256_l_s : std_logic; + signal hcnt_f : std_logic_vector(7 downto 0); + signal vcnt_f : std_logic_vector(7 downto 0); + + -- load strobes + signal vpl_load : std_logic; + signal col_load : std_logic; + signal objdata_load : std_logic; + signal missile_load : std_logic; + signal missile_reg_l : std_logic; + + signal cntr_clr : std_logic; + signal cntr_load : std_logic; + signal sld_l : std_logic; + + -- video ram + signal vram_addr_sum : std_logic_vector(8 downto 0); -- extra bit for debug + signal msld_l : std_logic; + signal vram_addr_reg : std_logic_vector(7 downto 0); + signal vram_addr_xor : std_logic_vector(3 downto 0); + signal vram_addr : std_logic_vector(9 downto 0); + signal vram_dout : std_logic_vector(7 downto 0); + signal ldout : std_logic; + + -- object ram + signal obj_addr : std_logic_vector(7 downto 0); + signal hpla : std_logic_vector(7 downto 0); + signal objdata : std_logic_vector(7 downto 0); + + signal obj_rom_addr : std_logic_vector(10 downto 0); + signal obj_rom_0_dout : std_logic_vector(7 downto 0); + signal obj_rom_1_dout : std_logic_vector(7 downto 0); + -- + signal col_reg : std_logic_vector(2 downto 0); + signal cd : std_logic_vector(2 downto 0); + + signal shift_reg_1 : std_logic_vector(7 downto 0); + signal shift_reg_0 : std_logic_vector(7 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + signal gr : std_logic_vector(1 downto 0); + signal gc : std_logic_vector(2 downto 0); + + signal vid : std_logic_vector(1 downto 0); + signal col : std_logic_vector(2 downto 0); + + signal obj_video_out_reg : std_logic_vector(4 downto 0); + signal vidout_l : std_logic; + signal obj_lut_out : std_logic_vector(7 downto 0); + + signal cntr_addr : std_logic_vector(7 downto 0); + signal cntr_addr_xor : std_logic_vector(10 downto 0); + signal sprite_sel : std_logic; + signal sprite_ram_ip : std_logic_vector(7 downto 0); + signal sprite_ram_waddr : std_logic_vector(10 downto 0); + signal sprite_ram_op : std_logic_vector(7 downto 0); + -- shell + signal shell_cnt : std_logic_vector(7 downto 0); + signal shell_ena : std_logic; + signal shell : std_logic; + signal shell_reg : std_logic; + -- stars + signal star_reg_1 : std_logic; + signal star_reg_2 : std_logic; + signal star_cnt_div : std_logic_vector(22 downto 0); + signal star_cnt : std_logic_vector(1 downto 0); + signal star_shift : std_logic_vector(16 downto 0); + signal star_shift_t1 : std_logic_vector(16 downto 0); + signal star_on : std_logic; + signal star_out_reg : std_logic; + -- frogger blue bar + signal frogger_blue_reg : std_logic; + signal frogger_blue : std_logic; + signal frogger_blue_out_reg : std_logic; + -- scramble blue + signal pout1_reg : std_logic; + + +begin + p_hcnt_decode : process(I_HCNT) + begin + ld <= '0'; + if (I_HCNT(2 downto 0) = "111") then + ld <= '1'; + end if; + h256_l <= I_HCNT(8); + h256 <= not I_HCNT(8); + + end process; + + p_timing_decode : process(h256, h256_l, I_HCMA, I_VBLANK) + begin + cblank_s <= not (I_VBLANK or h256); -- active low + hcmp1_s <= h256_l and I_HCMA; + end process; + + p_reg : process + begin + wait until rising_edge(CLK); + + if (ENA = '1') then + if (ld = '1') then + hcmp1 <= hcmp1_s; + hcmp2 <= hcmp2_s; + cblank_l <= cblank_s; + h256_l_s <= h256_l; + + if not I_HWSEL_FROGGER then + cd <= col_reg; + else + cd <= col_reg(0) & col_reg(2 downto 1); + end if; + end if; + end if; + end process; + + p_load_decode : process(ld, I_HCNT, h256) + variable obj_load : std_logic; + begin + vpl_load <= '0'; + obj_load := '0'; + col_load <= '0'; + + if (I_HCNT(2 downto 0) = "001") then vpl_load <= '1'; end if; -- 1 clock later + if (I_HCNT(2 downto 0) = "011") then obj_load := '1'; end if; -- 1 later + if (I_HCNT(2 downto 0) = "101") then col_load <= '1'; end if; -- 1 later + + objdata_load <= obj_load and h256 and (not I_HCNT(3)); + missile_load <= obj_load and h256 and ( I_HCNT(3)); + + cntr_clr <= ld and (not h256) and (not I_HCNT(3)); + cntr_load <= ld and ( h256) and (not I_HCNT(3)); + + end process; + + p_hv_flip : process(I_HCNT, I_VCNT, I_VCMA, hcmp1_s) + begin + for i in 0 to 7 loop + vcnt_f(i) <= I_VCNT(i) xor I_VCMA; + hcnt_f(i) <= I_HCNT(i) xor hcmp1_s; + end loop; + end process; + + p_video_addr_calc : process(I_HWSEL_FROGGER, vcnt_f, hpla) + begin + if not I_HWSEL_FROGGER then + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(7 downto 0)); + else + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(3 downto 0) & hpla(7 downto 4)); + end if; + end process; + + p_msld : process(vram_addr_sum) + begin + msld_l <= '1'; + if (vram_addr_sum(7 downto 0) = "11111111") then + msld_l <= '0'; + end if; + end process; + + p_video_addr_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_VBLANK = '1') then -- was async + vram_addr_reg <= x"00"; + elsif (vpl_load = '1') then -- vpl_l + vram_addr_reg <= vram_addr_sum(7 downto 0); + end if; + end if; + end process; + + p_vram_xor : process(vram_addr_reg, objdata, h256) + variable flip : std_logic; + begin + flip := objdata(7) and h256; + for i in 0 to 3 loop + vram_addr_xor(i) <= vram_addr_reg(i) xor flip; + end loop; + end process; + + p_vram_addr : process(vram_addr_reg, cblank_s, ld, I_CPU_ADDR, vram_addr_xor, hcnt_f) + variable match : std_logic; + begin + match := '0'; + if (vram_addr_reg(7 downto 4) = "1111") then + match := '1'; + end if; + + if (cblank_s = '0') then + ldout <= match and ld; -- blanking, sprites + else + ldout <= ld; + end if; + + if (cblank_s = '0') then -- blanking, sprites + --vram_cs <= (not I_VRAMWR_L) or (not I_VRAMRD_L); + vram_addr <= I_CPU_ADDR(9 downto 0); -- let the cpu in + else + --vram_cs <= '1'; + vram_addr <= vram_addr_reg(7 downto 4) & vram_addr_xor(3) & hcnt_f(7 downto 3); + end if; + end process; + + u_vram : work.dpram generic map (10,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_VRAMWR_L, + + addr_a_i => vram_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => vram_addr, + data_b_o => vram_dout + ); + O_VRAM_DATA <= vram_dout; + + p_object_ram_addr : process(h256, I_HCMA, objdata, I_HCNT, hcnt_f, I_CPU_ADDR, I_OBJEN_L) + begin + -- I believe the object ram can only be written during vblank + + if (h256 = '0') then + hcmp2_s <= I_HCMA; + else + hcmp2_s <= objdata(6); + end if; + + if (I_OBJEN_L = '0') then + obj_addr <= I_CPU_ADDR(7 downto 0); + else + obj_addr(7) <= '0'; + obj_addr(6) <= h256; + + -- A + if (h256 = '0') then -- normal + obj_addr(5) <= hcnt_f(7); --128h'; + else -- sprite + obj_addr(5) <= hcnt_f(3) and I_HCNT(1);-- 8h' and 2h; + end if; + + obj_addr(4 downto 2) <= hcnt_f(6 downto 4); + + if (h256 = '0') then -- normal + obj_addr(1) <= hcnt_f(3); --8h' + obj_addr(0) <= I_HCNT(2); --4h + else + obj_addr(1) <= I_HCNT(2); --4h + obj_addr(0) <= I_HCNT(1); --2h + end if; + + end if; + end process; + + u_object_ram : work.dpram generic map (8,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_OBJRAMWR_L, + + addr_a_i => obj_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => obj_addr, + data_b_o => hpla + ); + + p_objdata_regs : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (col_load = '1') then -- colour load + col_reg <= hpla(2 downto 0); + end if; + + if (objdata_load = '1') then -- sprite load + objdata <= hpla; + end if; + + if (I_VBLANK = '1') then -- was async + missile_reg_l <= '1'; + elsif (missile_load = '1') then + missile_reg_l <= msld_l; + end if; + end if; + end process; + + p_obj_rom_addr : process(h256, vram_addr_xor, vram_dout, objdata, I_HCNT) + begin + obj_rom_addr( 2 downto 0) <= vram_addr_xor(2 downto 0); + if (h256 = '0') then + -- a + obj_rom_addr(10 downto 3) <= vram_dout; -- background objects + else + obj_rom_addr(10 downto 3) <= objdata(5 downto 0) & vram_addr_xor(3) & (objdata(6) xor I_HCNT(3)); -- sprites + end if; + end process; + + obj_rom0 : entity work.ROM_OBJ_0 -- 5H + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_0_dout); + obj_rom1 : entity work.ROM_OBJ_1 -- 5F + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_1_dout); + + p_obj_rom_shift : process + variable obj_rom_0_dout_s : std_logic_vector(7 downto 0); + begin + wait until rising_edge (CLK); + if not I_HWSEL_FROGGER then + obj_rom_0_dout_s := obj_rom_0_dout; + else -- swap bits 0 and 1 + obj_rom_0_dout_s := obj_rom_0_dout(7 downto 2) & obj_rom_0_dout(0) & obj_rom_0_dout(1); + end if; + + if (ENA = '1') then + case shift_sel is + when "00" => null; -- do nothing + + when "01" => shift_reg_1 <= '0' & shift_reg_1(7 downto 1); -- right + shift_reg_0 <= '0' & shift_reg_0(7 downto 1); + + when "10" => shift_reg_1 <= shift_reg_1(6 downto 0) & '0'; -- left + shift_reg_0 <= shift_reg_0(6 downto 0) & '0'; + + when "11" => shift_reg_1 <= obj_rom_1_dout (7 downto 0); -- load + shift_reg_0 <= obj_rom_0_dout_s(7 downto 0); + when others => null; + end case; + end if; + end process; + + p_obj_rom_shift_sel : process(hcmp2, ldout, shift_reg_1, shift_reg_0) + begin + if (hcmp2 = '0') then + + shift_sel(1) <= '1'; + shift_sel(0) <= ldout; + shift_op(1) <= shift_reg_1(7); + shift_op(0) <= shift_reg_0(7); + else + + shift_sel(1) <= ldout; + shift_sel(0) <= '1'; + shift_op(1) <= shift_reg_1(0); + shift_op(0) <= shift_reg_0(0); + end if; + end process; + + p_video_out_logic : process(shift_op, cd, gr, gc) + variable vidon : std_logic; + begin + vidon := shift_op(0) or shift_op(1); + + if (gr(1 downto 0) = "00") then + vid(1 downto 0) <= shift_op(1 downto 0); + else + vid(1 downto 0) <= gr(1 downto 0); + end if; + + if (gc(2 downto 0) = "000") and (vidon = '1') then + col(2 downto 0) <= cd(2 downto 0); + else + col(2 downto 0) <= gc(2 downto 0); + end if; + end process; + + p_shell_ld : process(ld, h256, I_HCNT, missile_reg_l) + begin + sld_l <= '1'; + if (ld = '1') and (h256 = '1') and (I_HCNT(3) = '1') then + if (missile_reg_l = '0') and (I_HCNT(6 downto 4) /= "111") then + sld_l <= '0'; + end if; + end if; + + end process; + + p_shell_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + if (sld_l = '0') then + shell_cnt <= hpla; + elsif (cblank_l = '1') then + shell_cnt <= shell_cnt + "1"; + else + shell_cnt <= shell_cnt; + end if; + + if (sld_l = '0') then + shell_ena <= '1'; + elsif (shell = '1') then + shell_ena <= '0'; + end if; + end if; + end process; + + p_shell_op : process(shell_cnt, shell_ena) + begin + -- note how T input is from QD on the bottom counter + -- we get a rc from xF8 to XFF + -- so the shell is set at count xFA (rc and bit 1) + shell <= '0'; + if (shell_cnt = x"F8") then -- minus 2 as delay wrong + shell <= shell_ena; + end if; + end process; + + p_cntr_cnt : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (cntr_clr = '1') and (h256_l_s = '0') then -- async + cntr_addr <= (others => '0'); + elsif (cntr_load = '1') then + cntr_addr <= hpla(7 downto 0); + else + cntr_addr <= cntr_addr + "1"; + end if; + end if; + end process; + + p_cntr_addr : process(cntr_addr, hcmp1) + begin + cntr_addr_xor(10 downto 8) <= (others => '0'); + for i in 0 to 7 loop + cntr_addr_xor(i) <= cntr_addr(i) xor hcmp1; + end loop; + end process; + + p_sprite_sel : process(h256_l_s, cntr_addr_xor) + begin + sprite_sel <= '0'; + if (h256_l_s = '0') and (cntr_addr_xor(7 downto 4) /= "0000") then + sprite_sel <= '1'; + end if; + end process; + + p_sprite_write : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- delay 1 clock + sprite_ram_ip <= (others => '0'); + if (sprite_sel = '1') then + sprite_ram_ip(4 downto 2) <= col(2 downto 0); + sprite_ram_ip(1 downto 0) <= vid(1 downto 0); + end if; + + sprite_ram_waddr <= cntr_addr_xor; + end if; + end process; + + u_sprite_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => '1', + + addr_a_i => sprite_ram_waddr, + data_a_i => sprite_ram_ip, + + clk_b_i => clk, + addr_b_i => cntr_addr_xor, + data_b_o => sprite_ram_op + ); + + gc(2 downto 0) <= sprite_ram_op(4 downto 2); + gr(1 downto 0) <= sprite_ram_op(1 downto 0); + + p_video_out_reg : process + variable vidout_l_int : std_logic; + begin + wait until rising_edge(CLK); + -- register all objects to match increased video delay + if (ENA = '1') then + star_shift_t1 <= star_shift; + + if (cblank_l = '0') then + -- logic around the clr workes out as a sync reset + obj_video_out_reg <= (others => '0'); + shell_reg <= '0'; + frogger_blue_out_reg <= '0'; + star_out_reg <= '0'; + pout1_reg <= '0'; + else + + obj_video_out_reg(4 downto 2) <= col(2 downto 0); + obj_video_out_reg(1 downto 0) <= vid(1 downto 0); + vidout_l <= not(vid(1) or vid(0)); + -- probably wider than the original, we must be a whole 6MHz clock here or the scan-doubler will loose it. + shell_reg <= shell; + frogger_blue_out_reg <= frogger_blue; + + star_out_reg <= '0'; + if (star_shift(7 downto 0) = x"FF") and (star_on = '1') then + star_out_reg <= (vcnt_f(0) xor hcnt_f(3)) and (not star_shift(16)); + end if; + + pout1_reg <= I_POUT1; + + end if; + end if; + end process; + +-- Non BRAM (LUT) Version +-- col_rom : entity work.ROM_LUT +-- port map( +-- ADDR => obj_video_out_reg(4 downto 0), +-- DATA => obj_lut_out +-- ); + +-- BRAM Version + col_rom : entity work.ROM_LUT + port map( + CLK => CLK, + ADDR => obj_video_out_reg(4 downto 0), + DATA => obj_lut_out + ); + + p_col_rom_ce : process + variable video : array_3x5; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + video(0)(4) := '0'; + video(1)(4) := '0'; + video(2)(4) := '0'; + video(0)(3) := '0'; -- b + video(1)(3) := '0'; -- g + video(2)(3) := '0'; -- r + + if (vidout_l = '0') then -- cs_l on col rom + + video(0)(2 downto 0) := obj_lut_out(7 downto 6) & '0'; + video(1)(2 downto 0) := obj_lut_out(5 downto 3); + video(2)(2 downto 0) := obj_lut_out(2 downto 0); + else + video(0)(2 downto 0) := "000"; + video(1)(2 downto 0) := "000"; + video(2)(2 downto 0) := "000"; + end if; + -- + -- end of direct assigns + -- + if I_HWSEL_FROGGER then + if (frogger_blue_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + "00010"; + end if; + end if; + + if not I_HWSEL_FROGGER then + video(1) := video(1) + ("00" & shell_reg & "00"); + video(2) := video(2) + ("00" & shell_reg & "00"); + end if; + + -- add stars, background and video + if not I_HWSEL_FROGGER then + if (star_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ( '0' & star_shift_t1(13 downto 12) & "00"); + video(1) := video(1) + ( '0' & star_shift_t1(11 downto 10) & "00"); + video(2) := video(2) + ( '0' & star_shift_t1( 9 downto 8) & "00"); + end if; + + if (pout1_reg = '1') and (vidout_l = '1') then + video(0) := video(0) + ("00011"); + end if; + end if; + -- check for clip + for i in 0 to 2 loop + if video(i)(4) = '1' or video(i)(3) = '1' then + video(i)(2 downto 0) := (others => '1'); + end if; + end loop; + + O_VIDEO_B <= video(0)(2 downto 0) & video(0)(2); + O_VIDEO_G <= video(1)(2 downto 0) & video(1)(2); + O_VIDEO_R <= video(2)(2 downto 0) & video(2)(2); + end if; + end process; + + p_frogger_blue_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_HCNT(7 downto 0) = x"87") then + frogger_blue_reg <= '1'; + elsif (I_HCNT(7 downto 0) = x"07") then + frogger_blue_reg <= '0'; + end if; + end if; + end process; + frogger_blue <= not (frogger_blue_reg xor I_HCMA); + + p_stars_timer : process + begin + wait until rising_edge(CLK); + -- 555 period 0.8316 seconds + -- ~ 4DF 666 + if (ENA = '1') then + if (star_cnt_div(22 downto 17) = "100111") then + star_cnt_div <= (others => '0'); + star_cnt <= star_cnt + "1"; + else + star_cnt_div <= star_cnt_div + "1"; + end if; + end if; + end process; + + p_stars_demux : process(star_cnt, I_VCNT, star_shift) + begin + case star_cnt is + when "00" => star_on <= star_shift(8); + when "01" => star_on <= star_shift(10); + when "10" => star_on <= I_VCNT(1); + when "11" => star_on <= '1'; + when others => null; + end case; + end process; + + p_stars : process + variable star_ena : std_logic; + variable star_shift_ena : std_logic; + variable fb : std_logic; + variable star_clear : std_logic; + begin + wait until rising_edge(CLK); + -- stars clocked off 12 MHz clock + star_ena := ENA_12 and (not I_VSYNC) and h256_l_s; + + if (ENA = '1') and (I_VSYNC = '1') then + star_reg_1 <= '0'; + star_reg_2 <= '0'; + elsif (star_ena = '1') then + star_reg_1 <= '1'; + star_reg_2 <= star_reg_1; + end if; + + star_shift_ena := (star_reg_2 or I_HCMA) and star_ena; + + star_clear := I_STARSON and (not I_VBLANK); + + fb := (not star_shift(16)) xor star_shift(4); + if (star_clear = '0') then + star_shift <= (others => '0'); + elsif (star_shift_ena = '1') then + star_shift(16 downto 0) <= star_shift(15 downto 0) & fb; + end if; + end process; + +end RTL; diff --git a/Arcade/Scramble Hardware/Scramble_MiST/rtl/video_mixer.sv b/Arcade/Scramble Hardware/Scramble_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Scramble Hardware/Scramble_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/README.txt b/Arcade/Scramble Hardware/TheEnd_MiST/README.txt new file mode 100644 index 00000000..68977f8c --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/README.txt @@ -0,0 +1,26 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: The End port to MiST by Gehstock +-- 17 December 2017 +-- +--------------------------------------------------------------------------------- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +--------------------------------------------------------------------------------- +-- +-- Only controls are rotated on VGA output. +-- +-- +-- Keyboard inputs : +-- +-- ESC : Coin +-- F2 : Start 2 players +-- F1 : Start 1 player +-- SPACE : Fire + +-- UP,DOWN,LEFT,RIGHT arrows : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf b/Arcade/Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf new file mode 100644 index 00000000..b645ca7f Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/Release/TheEnd.rbf differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.qpf b/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.qpf new file mode 100644 index 00000000..b2c68740 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "TheEnd" diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.qsf b/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.qsf new file mode 100644 index 00000000..1c65c75a --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.qsf @@ -0,0 +1,219 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 01:12:07 December 01, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TheEnd_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_1.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_0.vhd +set_global_assignment -name VHDL_FILE rtl/ROM/ROM_LUT.vhd +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd +set_global_assignment -name VHDL_FILE rtl/i82c55.vhd +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name VERILOG_FILE rtl/build_id.v +set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd +set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd +set_global_assignment -name VHDL_FILE rtl/scramble.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/TheEnd.sv +set_global_assignment -name VERILOG_FILE rtl/mist_io.v + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY TheEnd + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# -------------------- +# start ENTITY(TheEnd) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(TheEnd) +# ------------------ +set_global_assignment -name LL_ENABLED ON -section_id Region_0 +set_global_assignment -name LL_AUTO_SIZE OFF -section_id Region_0 +set_global_assignment -name LL_STATE LOCKED -section_id Region_0 +set_global_assignment -name LL_RESERVED OFF -section_id Region_0 +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id Region_0 +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id Region_0 +set_global_assignment -name LL_PR_REGION OFF -section_id Region_0 +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id Region_0 +set_global_assignment -name LL_WIDTH 4 -section_id Region_0 +set_global_assignment -name LL_HEIGHT 1 -section_id Region_0 +set_global_assignment -name LL_ORIGIN X28_Y23 -section_id Region_0 +set_global_assignment -name LL_ENABLED ON -section_id Region_1 +set_global_assignment -name LL_AUTO_SIZE OFF -section_id Region_1 +set_global_assignment -name LL_STATE LOCKED -section_id Region_1 +set_global_assignment -name LL_RESERVED OFF -section_id Region_1 +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id Region_1 +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id Region_1 +set_global_assignment -name LL_PR_REGION OFF -section_id Region_1 +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id Region_1 +set_global_assignment -name LL_WIDTH 5 -section_id Region_1 +set_global_assignment -name LL_HEIGHT 7 -section_id Region_1 +set_global_assignment -name LL_ORIGIN X7_Y23 -section_id Region_1 +set_global_assignment -name LL_ENABLED ON -section_id Region_2 +set_global_assignment -name LL_AUTO_SIZE OFF -section_id Region_2 +set_global_assignment -name LL_STATE LOCKED -section_id Region_2 +set_global_assignment -name LL_RESERVED OFF -section_id Region_2 +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id Region_2 +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id Region_2 +set_global_assignment -name LL_PR_REGION OFF -section_id Region_2 +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id Region_2 +set_global_assignment -name LL_WIDTH 2 -section_id Region_2 +set_global_assignment -name LL_HEIGHT 3 -section_id Region_2 +set_global_assignment -name LL_ORIGIN X6_Y30 -section_id Region_2 +set_global_assignment -name LL_ENABLED ON -section_id Region_3 +set_global_assignment -name LL_AUTO_SIZE OFF -section_id Region_3 +set_global_assignment -name LL_STATE LOCKED -section_id Region_3 +set_global_assignment -name LL_RESERVED OFF -section_id Region_3 +set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id Region_3 +set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id Region_3 +set_global_assignment -name LL_PR_REGION OFF -section_id Region_3 +set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id Region_3 +set_global_assignment -name LL_WIDTH 3 -section_id Region_3 +set_global_assignment -name LL_HEIGHT 8 -section_id Region_3 +set_global_assignment -name LL_ORIGIN X3_Y23 -section_id Region_3 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.srf b/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.srf new file mode 100644 index 00000000..a455f0f5 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/TheEnd.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/clean.bat b/Arcade/Scramble Hardware/TheEnd_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd new file mode 100644 index 00000000..32535505 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/MULT18X18.vhd @@ -0,0 +1,53 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY MULT18X18 IS + PORT + ( + A : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + B : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + P : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); +END MULT18X18; + + +ARCHITECTURE SYN OF mult18x18 IS + + COMPONENT lpm_mult + GENERIC ( + lpm_hint : STRING; + lpm_representation : STRING; + lpm_type : STRING; + lpm_widtha : NATURAL; + lpm_widthb : NATURAL; + lpm_widthp : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + lpm_mult_component : lpm_mult + GENERIC MAP ( + lpm_hint => "MAXIMIZE_SPEED=5", + lpm_representation => "SIGNED", + lpm_type => "LPM_MULT", + lpm_widtha => 18, + lpm_widthb => 18, + lpm_widthp => 36 + ) + PORT MAP ( + dataa => A, + datab => B, + result => P + ); + +END SYN; + diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/6331-1j.86 b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/6331-1j.86 new file mode 100644 index 00000000..74f9c119 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/6331-1j.86 differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/CPU1.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/CPU1.bin new file mode 100644 index 00000000..71d84b9d Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/CPU1.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/CPU2.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/CPU2.bin new file mode 100644 index 00000000..11053cc5 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/CPU2.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/GFX1.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/GFX1.bin new file mode 100644 index 00000000..e34304aa Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/GFX1.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/Load Jumpshot.bat b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/Load Jumpshot.bat new file mode 100644 index 00000000..baedf2ff --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/Load Jumpshot.bat @@ -0,0 +1,23 @@ +@echo off + + + + +copy /b ic13_1t.bin + ic14_2t.bin + ic15_3t.bin + ic16_4t.bin + ic17_5t.bin + ic18_6t.bin CPU1.bin +romgen.exe CPU1.bin ROM_PGM_0 14 a r > rom0.vhd + +copy /b ic56_1.bin ROM_SND_0.bin +romgen.exe ROM_SND_0.bin ROM_SND_0 11 a r > ROM_SND_0.vhd + +copy /b ic55_2.bin ROM_SND_1.bin +romgen.exe ROM_SND_1.bin ROM_SND_1 11 a r > ROM_SND_1.vhd + + +copy /b ic30_2c.bin ROM_OBJ_0.bin +romgen.exe ROM_OBJ_0.bin ROM_OBJ_0 11 a r > ROM_OBJ_0.vhd + +copy /b ic31_1c.bin ROM_OBJ_1.bin +romgen.exe ROM_OBJ_1.bin ROM_OBJ_1 11 a r > ROM_OBJ_1.vhd + + +pause diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd new file mode 100644 index 00000000..eae5cff1 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_LUT.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity ROM_LUT is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of ROM_LUT is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07", + X"00",X"C0",X"A0",X"0C",X"00",X"00",X"00",X"07",X"00",X"F6",X"07",X"F0",X"00",X"76",X"07",X"C6"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.bin new file mode 100644 index 00000000..9bd5d920 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd new file mode 100644 index 00000000..d4d12dcb --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_0.vhd @@ -0,0 +1,284 @@ +-- generated with romgen by MikeJ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ROM_OBJ_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_OBJ_0 is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"70",x"38",x"1C",x"1C",x"38",x"34",x"74",x"7E", -- 0x0180 + x"FB",x"FE",x"F4",x"F4",x"F8",x"B8",x"BC",x"BE", -- 0x0188 + x"FE",x"FF",x"FF",x"F1",x"F0",x"70",x"70",x"70", -- 0x0190 + x"70",x"70",x"70",x"F0",x"F1",x"FF",x"FF",x"FE", -- 0x0198 + x"BE",x"BC",x"B8",x"F8",x"F4",x"F4",x"FE",x"FB", -- 0x01A0 + x"7E",x"74",x"34",x"38",x"1C",x"1C",x"38",x"70", -- 0x01A8 + x"FE",x"FF",x"FF",x"F1",x"F0",x"70",x"70",x"70", -- 0x01B0 + x"70",x"70",x"70",x"F0",x"F1",x"FF",x"FF",x"FE", -- 0x01B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x01C8 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 + x"40",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x01E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"00", -- 0x01E8 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"40",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"80",x"A0",x"80", -- 0x0208 + x"07",x"00",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"60",x"C0",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"03", -- 0x0220 + x"00",x"00",x"00",x"00",x"40",x"20",x"20",x"E0", -- 0x0228 + x"01",x"02",x"05",x"01",x"00",x"00",x"00",x"00", -- 0x0230 + x"18",x"E0",x"D0",x"08",x"80",x"00",x"00",x"00", -- 0x0238 + x"00",x"00",x"00",x"00",x"08",x"08",x"08",x"06", -- 0x0240 + x"00",x"00",x"00",x"00",x"10",x"10",x"10",x"60", -- 0x0248 + x"13",x"0C",x"03",x"07",x"09",x"10",x"00",x"00", -- 0x0250 + x"C8",x"30",x"C0",x"E0",x"90",x"08",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 + x"00",x"00",x"C3",x"2C",x"10",x"11",x"00",x"00", -- 0x02A0 + x"00",x"00",x"00",x"80",x"40",x"20",x"10",x"10", -- 0x02A8 + x"00",x"FE",x"FF",x"FE",x"70",x"E0",x"FC",x"F0", -- 0x02B0 + x"08",x"08",x"14",x"14",x"38",x"48",x"10",x"20", -- 0x02B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"FF",x"81",x"81",x"81",x"81",x"81",x"81",x"FF", -- 0x02D8 + x"FC",x"E0",x"70",x"FE",x"FF",x"FE",x"00",x"00", -- 0x02E0 + x"40",x"40",x"00",x"00",x"00",x"40",x"40",x"80", -- 0x02E8 + x"00",x"5E",x"AE",x"7E",x"EE",x"7E",x"AE",x"5E", -- 0x02F0 + x"00",x"05",x"0A",x"07",x"0E",x"07",x"0A",x"05", -- 0x02F8 + x"00",x"00",x"00",x"00",x"00",x"03",x"1E",x"7C", -- 0x0300 + x"04",x"0C",x"18",x"38",x"FC",x"9E",x"06",x"03", -- 0x0308 + x"1E",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"06",x"9E",x"FC",x"38",x"18",x"0C",x"04",x"00", -- 0x0318 + x"80",x"E2",x"B3",x"22",x"02",x"8B",x"CE",x"88", -- 0x0320 + x"80",x"E2",x"B3",x"22",x"02",x"0B",x"0E",x"08", -- 0x0328 + x"00",x"22",x"33",x"22",x"02",x"0B",x"0E",x"08", -- 0x0330 + x"00",x"22",x"33",x"22",x"02",x"0B",x"0E",x"08", -- 0x0338 + x"00",x"02",x"03",x"02",x"02",x"0B",x"0E",x"08", -- 0x0340 + x"00",x"02",x"03",x"02",x"02",x"03",x"02",x"00", -- 0x0348 + x"00",x"02",x"03",x"02",x"02",x"03",x"02",x"00", -- 0x0350 + x"00",x"02",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0358 + x"00",x"22",x"33",x"22",x"02",x"8B",x"CE",x"88", -- 0x0360 + x"00",x"02",x"03",x"02",x"02",x"0B",x"0E",x"08", -- 0x0368 + x"00",x"02",x"03",x"02",x"02",x"0B",x"0E",x"08", -- 0x0370 + x"00",x"00",x"00",x"00",x"02",x"03",x"02",x"00", -- 0x0378 + x"00",x"00",x"01",x"00",x"0E",x"11",x"11",x"00", -- 0x0380 + x"00",x"00",x"08",x"88",x"50",x"50",x"F0",x"F8", -- 0x0388 + x"00",x"11",x"11",x"0E",x"00",x"01",x"00",x"00", -- 0x0390 + x"F8",x"F0",x"50",x"50",x"88",x"08",x"00",x"00", -- 0x0398 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x03A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x03A8 + x"01",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 + x"E0",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x03C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x03C8 + x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"03", -- 0x03E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"C0", -- 0x03E8 + x"03",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 + x"C0",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0400 + x"00",x"00",x"10",x"10",x"27",x"A8",x"D8",x"5C", -- 0x0408 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0410 + x"5C",x"D8",x"A8",x"27",x"10",x"10",x"00",x"00", -- 0x0418 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0420 + x"00",x"00",x"41",x"22",x"24",x"A8",x"D8",x"5C", -- 0x0428 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0430 + x"5C",x"D8",x"A8",x"24",x"22",x"41",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0440 + x"00",x"00",x"84",x"44",x"28",x"A8",x"D8",x"5C", -- 0x0448 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0450 + x"5C",x"D8",x"A8",x"28",x"44",x"84",x"00",x"00", -- 0x0458 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0460 + x"00",x"00",x"90",x"48",x"28",x"A8",x"D8",x"5C", -- 0x0468 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0470 + x"5C",x"D8",x"A8",x"28",x"48",x"90",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"0E",x"11",x"11",x"00", -- 0x0480 + x"00",x"00",x"88",x"88",x"50",x"50",x"B0",x"B8", -- 0x0488 + x"00",x"11",x"11",x"0E",x"00",x"00",x"00",x"00", -- 0x0490 + x"B8",x"B0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"07",x"08",x"00",x"00",x"10", -- 0x04A0 + x"00",x"00",x"00",x"20",x"A4",x"A4",x"A8",x"B8", -- 0x04A8 + x"20",x"13",x"0E",x"00",x"03",x"02",x"00",x"00", -- 0x04B0 + x"B0",x"B8",x"70",x"A0",x"20",x"20",x"20",x"00", -- 0x04B8 + x"00",x"00",x"03",x"04",x"00",x"10",x"20",x"20", -- 0x04C0 + x"00",x"00",x"00",x"80",x"50",x"50",x"90",x"E6", -- 0x04C8 + x"13",x"0D",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x04D0 + x"28",x"70",x"F0",x"70",x"80",x"00",x"00",x"00", -- 0x04D8 + x"00",x"00",x"00",x"01",x"08",x"10",x"10",x"10", -- 0x04E0 + x"00",x"00",x"80",x"40",x"20",x"20",x"60",x"4C", -- 0x04E8 + x"0F",x"00",x"1E",x"01",x"00",x"0C",x"00",x"00", -- 0x04F0 + x"F0",x"66",x"F8",x"E0",x"40",x"00",x"00",x"00", -- 0x04F8 + x"00",x"00",x"00",x"06",x"08",x"08",x"08",x"06", -- 0x0500 + x"00",x"00",x"00",x"60",x"10",x"10",x"10",x"60", -- 0x0508 + x"33",x"0C",x"03",x"07",x"31",x"00",x"00",x"00", -- 0x0510 + x"CC",x"30",x"C0",x"F0",x"8C",x"00",x"00",x"00", -- 0x0518 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0520 + x"00",x"00",x"10",x"10",x"27",x"A8",x"D8",x"5C", -- 0x0528 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0530 + x"5C",x"D8",x"A8",x"27",x"10",x"10",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"07",x"08",x"08", -- 0x0540 + x"00",x"00",x"41",x"22",x"24",x"A8",x"D8",x"5C", -- 0x0548 + x"08",x"08",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"5C",x"D8",x"A8",x"24",x"22",x"41",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"07",x"08",x"08",x"00", -- 0x0560 + x"00",x"00",x"84",x"44",x"28",x"A8",x"D8",x"5C", -- 0x0568 + x"00",x"08",x"08",x"07",x"00",x"00",x"00",x"00", -- 0x0570 + x"5C",x"D8",x"A8",x"28",x"44",x"84",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"07",x"08",x"08", -- 0x0580 + x"00",x"00",x"90",x"48",x"28",x"A8",x"D8",x"5C", -- 0x0588 + x"08",x"08",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0590 + x"5C",x"D8",x"A8",x"28",x"48",x"90",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"0E",x"11",x"11", -- 0x05A0 + x"00",x"00",x"88",x"88",x"50",x"50",x"B0",x"B8", -- 0x05A8 + x"11",x"11",x"0E",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 + x"B8",x"B0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"07",x"08",x"00",x"00",x"10", -- 0x05C0 + x"00",x"00",x"00",x"20",x"A4",x"A4",x"A8",x"B8", -- 0x05C8 + x"20",x"13",x"0E",x"00",x"03",x"02",x"00",x"00", -- 0x05D0 + x"B0",x"B8",x"70",x"A0",x"20",x"20",x"20",x"00", -- 0x05D8 + x"00",x"00",x"03",x"04",x"00",x"10",x"20",x"20", -- 0x05E0 + x"00",x"00",x"00",x"80",x"50",x"50",x"90",x"E6", -- 0x05E8 + x"13",x"0D",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x05F0 + x"28",x"70",x"F0",x"70",x"80",x"00",x"00",x"00", -- 0x05F8 + x"00",x"00",x"00",x"01",x"08",x"10",x"10",x"10", -- 0x0600 + x"00",x"00",x"80",x"40",x"20",x"20",x"60",x"4C", -- 0x0608 + x"0F",x"00",x"1E",x"01",x"00",x"0C",x"00",x"00", -- 0x0610 + x"F0",x"66",x"F8",x"E0",x"40",x"00",x"00",x"00", -- 0x0618 + x"00",x"00",x"00",x"06",x"08",x"08",x"08",x"06", -- 0x0620 + x"00",x"00",x"00",x"60",x"10",x"10",x"10",x"60", -- 0x0628 + x"33",x"0C",x"03",x"0F",x"31",x"00",x"00",x"00", -- 0x0630 + x"CC",x"30",x"C0",x"F0",x"8C",x"00",x"00",x"00", -- 0x0638 + x"00",x"EE",x"EE",x"EE",x"EE",x"EE",x"EE",x"EE", -- 0x0640 + x"00",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0648 + x"00",x"0E",x"0E",x"0E",x"0E",x"0E",x"0E",x"0E", -- 0x0650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658 + x"00",x"06",x"0C",x"36",x"E3",x"36",x"0C",x"06", -- 0x0660 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0668 + x"F8",x"F8",x"F8",x"F8",x"B8",x"58",x"F8",x"00", -- 0x0670 + x"12",x"6A",x"94",x"D4",x"94",x"6A",x"12",x"00", -- 0x0678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"02", -- 0x0690 + x"00",x"02",x"07",x"0C",x"28",x"C3",x"1F",x"FF", -- 0x0698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 + x"A4",x"7E",x"18",x"39",x"FC",x"FE",x"FE",x"FF", -- 0x06B0 + x"20",x"00",x"00",x"00",x"80",x"80",x"20",x"00", -- 0x06B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 + x"1F",x"C3",x"C8",x"0C",x"07",x"03",x"00",x"00", -- 0x06C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"FE",x"FE",x"FC",x"39",x"18",x"7E",x"A4",x"03", -- 0x06E0 + x"40",x"80",x"80",x"00",x"00",x"00",x"80",x"00", -- 0x06E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"02", -- 0x0700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0710 + x"00",x"00",x"06",x"0D",x"10",x"06",x"2D",x"B6", -- 0x0718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 + x"04",x"7E",x"18",x"58",x"80",x"96",x"BA",x"5B", -- 0x0730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 + x"00",x"03",x"00",x"00",x"00",x"00",x"02",x"00", -- 0x0740 + x"2D",x"06",x"10",x"0D",x"06",x"00",x"00",x"00", -- 0x0748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"BA",x"96",x"80",x"58",x"18",x"7E",x"04",x"00", -- 0x0760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"04",x"00",x"00",x"40",x"00",x"00",x"00",x"00", -- 0x0780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 + x"08",x"00",x"13",x"0C",x"00",x"23",x"31",x"4F", -- 0x0798 + x"00",x"00",x"00",x"00",x"00",x"10",x"00",x"00", -- 0x07A0 + x"01",x"00",x"00",x"00",x"00",x"04",x"00",x"00", -- 0x07A8 + x"00",x"08",x"C0",x"E8",x"80",x"40",x"A2",x"F0", -- 0x07B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 + x"27",x"31",x"01",x"00",x"91",x"10",x"09",x"04", -- 0x07C8 + x"00",x"00",x"00",x"00",x"10",x"00",x"00",x"00", -- 0x07D0 + x"00",x"00",x"20",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 + x"CE",x"A4",x"45",x"88",x"00",x"C2",x"00",x"00", -- 0x07E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"10", -- 0x07F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.bin new file mode 100644 index 00000000..26dd1a0c Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd new file mode 100644 index 00000000..6d6d9b9e --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_OBJ_1.vhd @@ -0,0 +1,284 @@ +-- generated with romgen by MikeJ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ROM_OBJ_1 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_OBJ_1 is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000 + x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008 + x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010 + x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018 + x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020 + x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028 + x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030 + x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038 + x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040 + x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080 + x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088 + x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090 + x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098 + x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0 + x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8 + x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0 + x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8 + x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0 + x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8 + x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0 + x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8 + x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0 + x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8 + x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0 + x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8 + x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100 + x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108 + x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110 + x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118 + x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120 + x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128 + x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130 + x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138 + x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140 + x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148 + x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150 + x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"00", -- 0x0158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0178 + x"00",x"00",x"00",x"00",x"00",x"04",x"04",x"0E", -- 0x0180 + x"0F",x"0E",x"44",x"44",x"40",x"50",x"50",x"58", -- 0x0188 + x"58",x"58",x"40",x"00",x"04",x"04",x"0F",x"0F", -- 0x0190 + x"0F",x"0F",x"04",x"04",x"00",x"40",x"58",x"58", -- 0x0198 + x"58",x"50",x"50",x"40",x"44",x"44",x"0E",x"0F", -- 0x01A0 + x"0E",x"04",x"04",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 + x"58",x"58",x"40",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 + x"00",x"00",x"00",x"00",x"00",x"40",x"58",x"58", -- 0x01B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x01C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 + x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"40",x"80", -- 0x01E8 + x"00",x"01",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 + x"80",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0200 + x"00",x"00",x"00",x"00",x"00",x"00",x"20",x"C0", -- 0x0208 + x"01",x"01",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x0210 + x"A0",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"0E", -- 0x0228 + x"01",x"03",x"04",x"01",x"00",x"00",x"00",x"00", -- 0x0230 + x"F8",x"00",x"10",x"08",x"80",x"00",x"00",x"00", -- 0x0238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0248 + x"13",x"0F",x"00",x"04",x"08",x"10",x"00",x"00", -- 0x0250 + x"C8",x"F0",x"00",x"20",x"10",x"08",x"00",x"00", -- 0x0258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 + x"00",x"00",x"00",x"00",x"01",x"07",x"00",x"00", -- 0x02A0 + x"00",x"00",x"00",x"00",x"80",x"80",x"C0",x"00", -- 0x02A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 + x"10",x"10",x"30",x"30",x"20",x"60",x"40",x"C0", -- 0x02B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 + x"FF",x"81",x"81",x"81",x"81",x"81",x"81",x"FF", -- 0x02D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 + x"80",x"80",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 + x"00",x"0E",x"1E",x"2E",x"0E",x"2E",x"1E",x"0E", -- 0x02F0 + x"00",x"00",x"01",x"02",x"00",x"02",x"01",x"00", -- 0x02F8 + x"00",x"00",x"00",x"00",x"00",x"03",x"1F",x"7F", -- 0x0300 + x"04",x"7C",x"18",x"38",x"F0",x"E0",x"F8",x"FC", -- 0x0308 + x"1F",x"03",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 + x"F8",x"E0",x"F0",x"38",x"18",x"7C",x"04",x"00", -- 0x0318 + x"88",x"CE",x"8B",x"02",x"20",x"38",x"2C",x"08", -- 0x0320 + x"88",x"CE",x"8B",x"02",x"20",x"38",x"2C",x"08", -- 0x0328 + x"08",x"0E",x"0B",x"02",x"20",x"38",x"2C",x"08", -- 0x0330 + x"08",x"0E",x"0B",x"02",x"00",x"08",x"0C",x"08", -- 0x0338 + x"08",x"0E",x"0B",x"02",x"00",x"08",x"0C",x"08", -- 0x0340 + x"08",x"0E",x"0B",x"02",x"00",x"00",x"00",x"00", -- 0x0348 + x"00",x"02",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0350 + x"00",x"02",x"03",x"02",x"00",x"00",x"00",x"00", -- 0x0358 + x"08",x"0E",x"0B",x"02",x"20",x"38",x"2C",x"08", -- 0x0360 + x"08",x"0E",x"0B",x"02",x"20",x"38",x"2C",x"08", -- 0x0368 + x"00",x"02",x"03",x"02",x"00",x"08",x"0C",x"08", -- 0x0370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 + x"02",x"0C",x"10",x"20",x"40",x"80",x"80",x"40", -- 0x0380 + x"34",x"42",x"01",x"01",x"02",x"02",x"00",x"61", -- 0x0388 + x"40",x"80",x"80",x"40",x"20",x"10",x"0C",x"02", -- 0x0390 + x"61",x"00",x"02",x"02",x"01",x"01",x"42",x"34", -- 0x0398 + x"00",x"00",x"00",x"02",x"05",x"08",x"0C",x"18", -- 0x03A0 + x"00",x"00",x"00",x"40",x"D0",x"28",x"04",x"06", -- 0x03A8 + x"18",x"0C",x"08",x"05",x"02",x"00",x"00",x"00", -- 0x03B0 + x"06",x"04",x"28",x"D0",x"40",x"00",x"00",x"00", -- 0x03B8 + x"0B",x"36",x"22",x"20",x"40",x"20",x"62",x"80", -- 0x03C0 + x"50",x"B8",x"88",x"12",x"02",x"05",x"41",x"82", -- 0x03C8 + x"80",x"62",x"20",x"40",x"20",x"22",x"36",x"0B", -- 0x03D0 + x"82",x"41",x"05",x"02",x"12",x"88",x"B8",x"50", -- 0x03D8 + x"01",x"40",x"0A",x"00",x"12",x"00",x"24",x"81", -- 0x03E0 + x"00",x"02",x"A0",x"00",x"48",x"00",x"24",x"81", -- 0x03E8 + x"11",x"44",x"10",x"05",x"10",x"02",x"40",x"00", -- 0x03F0 + x"18",x"22",x"08",x"20",x"08",x"40",x"02",x"80", -- 0x03F8 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0400 + x"00",x"00",x"10",x"10",x"27",x"28",x"60",x"60", -- 0x0408 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0410 + x"60",x"60",x"28",x"27",x"10",x"10",x"00",x"00", -- 0x0418 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0420 + x"00",x"00",x"41",x"22",x"24",x"28",x"60",x"60", -- 0x0428 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0430 + x"60",x"60",x"28",x"24",x"22",x"41",x"00",x"00", -- 0x0438 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0440 + x"00",x"00",x"84",x"44",x"28",x"28",x"60",x"60", -- 0x0448 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0450 + x"60",x"60",x"28",x"28",x"44",x"84",x"00",x"00", -- 0x0458 + x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07", -- 0x0460 + x"00",x"00",x"90",x"48",x"28",x"28",x"60",x"60", -- 0x0468 + x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00", -- 0x0470 + x"60",x"60",x"28",x"28",x"48",x"90",x"00",x"00", -- 0x0478 + x"00",x"00",x"00",x"00",x"00",x"0E",x"0E",x"0E", -- 0x0480 + x"00",x"00",x"88",x"88",x"50",x"50",x"C0",x"C0", -- 0x0488 + x"0E",x"0E",x"0E",x"00",x"00",x"00",x"00",x"00", -- 0x0490 + x"C0",x"C0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x0498 + x"00",x"00",x"00",x"00",x"07",x"07",x"0F",x"0E", -- 0x04A0 + x"00",x"00",x"00",x"20",x"24",x"24",x"28",x"C8", -- 0x04A8 + x"1E",x"0D",x"00",x"00",x"03",x"02",x"00",x"00", -- 0x04B0 + x"C0",x"C0",x"80",x"A0",x"20",x"20",x"20",x"00", -- 0x04B8 + x"00",x"00",x"00",x"03",x"07",x"0F",x"1F",x"1E", -- 0x04C0 + x"00",x"00",x"00",x"00",x"90",x"90",x"10",x"E6", -- 0x04C8 + x"0D",x"01",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x04D0 + x"C8",x"80",x"00",x"00",x"80",x"00",x"00",x"00", -- 0x04D8 + x"00",x"00",x"00",x"00",x"03",x"0F",x"0F",x"0E", -- 0x04E0 + x"00",x"00",x"00",x"80",x"C0",x"C0",x"80",x"4C", -- 0x04E8 + x"01",x"01",x"1F",x"00",x"03",x"0C",x"00",x"00", -- 0x04F0 + x"B0",x"86",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 + x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"00", -- 0x0500 + x"00",x"00",x"00",x"00",x"E0",x"E0",x"E0",x"00", -- 0x0508 + x"33",x"0F",x"00",x"0C",x"30",x"00",x"00",x"00", -- 0x0510 + x"CC",x"F0",x"00",x"30",x"0C",x"00",x"00",x"00", -- 0x0518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 + x"00",x"00",x"10",x"10",x"27",x"28",x"60",x"60", -- 0x0528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 + x"60",x"60",x"28",x"27",x"10",x"10",x"00",x"00", -- 0x0538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 + x"00",x"00",x"41",x"22",x"24",x"28",x"60",x"60", -- 0x0548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 + x"60",x"60",x"28",x"24",x"22",x"41",x"00",x"00", -- 0x0558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 + x"00",x"00",x"84",x"44",x"28",x"28",x"60",x"60", -- 0x0568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 + x"60",x"60",x"28",x"28",x"44",x"84",x"00",x"00", -- 0x0578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 + x"00",x"00",x"90",x"48",x"28",x"28",x"60",x"60", -- 0x0588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 + x"60",x"60",x"28",x"28",x"48",x"90",x"00",x"00", -- 0x0598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 + x"00",x"00",x"88",x"88",x"50",x"50",x"C0",x"C0", -- 0x05A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 + x"C0",x"C0",x"50",x"50",x"88",x"88",x"00",x"00", -- 0x05B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 + x"00",x"00",x"00",x"20",x"24",x"24",x"28",x"C8", -- 0x05C8 + x"00",x"01",x"00",x"00",x"03",x"02",x"00",x"00", -- 0x05D0 + x"C0",x"C0",x"80",x"A0",x"20",x"20",x"20",x"00", -- 0x05D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 + x"00",x"00",x"00",x"00",x"10",x"10",x"10",x"E6", -- 0x05E8 + x"01",x"01",x"01",x"06",x"08",x"01",x"01",x"00", -- 0x05F0 + x"C8",x"80",x"00",x"00",x"80",x"00",x"00",x"00", -- 0x05F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"4C", -- 0x0608 + x"01",x"01",x"1F",x"00",x"03",x"0C",x"00",x"00", -- 0x0610 + x"B0",x"86",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 + x"33",x"0F",x"00",x"0C",x"30",x"00",x"00",x"00", -- 0x0630 + x"CC",x"F0",x"00",x"30",x"0C",x"00",x"00",x"00", -- 0x0638 + x"00",x"EE",x"EE",x"EE",x"EE",x"EE",x"EE",x"EE", -- 0x0640 + x"00",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0648 + x"00",x"0E",x"0E",x"0E",x"0E",x"0E",x"0E",x"0E", -- 0x0650 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0658 + x"00",x"1E",x"0C",x"38",x"FC",x"38",x"0C",x"1E", -- 0x0660 + x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0668 + x"50",x"50",x"50",x"50",x"F0",x"F0",x"F7",x"00", -- 0x0670 + x"12",x"0A",x"08",x"C8",x"08",x"0A",x"12",x"00", -- 0x0678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"03", -- 0x0688 + x"00",x"00",x"00",x"01",x"02",x"02",x"0C",x"12", -- 0x0690 + x"0C",x"32",x"C7",x"0C",x"28",x"C0",x"01",x"03", -- 0x0698 + x"00",x"00",x"00",x"00",x"02",x"46",x"B9",x"03", -- 0x06A0 + x"00",x"00",x"00",x"00",x"00",x"C0",x"40",x"20", -- 0x06A8 + x"A0",x"00",x"00",x"09",x"00",x"60",x"F8",x"FC", -- 0x06B0 + x"A0",x"40",x"60",x"18",x"88",x"90",x"60",x"10", -- 0x06B8 + x"0C",x"02",x"02",x"01",x"00",x"00",x"00",x"00", -- 0x06C0 + x"01",x"C0",x"C8",x"0C",x"C7",x"33",x"0C",x"03", -- 0x06C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 + x"F8",x"60",x"00",x"01",x"00",x"00",x"A0",x"03", -- 0x06E0 + x"60",x"90",x"88",x"18",x"60",x"40",x"A0",x"20", -- 0x06E8 + x"B9",x"46",x"02",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 + x"40",x"C0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"1C", -- 0x0708 + x"00",x"01",x"02",x"04",x"01",x"01",x"04",x"08", -- 0x0710 + x"21",x"80",x"26",x"CC",x"90",x"00",x"01",x"00", -- 0x0718 + x"00",x"00",x"00",x"00",x"00",x"00",x"46",x"61", -- 0x0720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 + x"80",x"00",x"00",x"03",x"01",x"10",x"B8",x"18", -- 0x0730 + x"00",x"80",x"40",x"40",x"10",x"90",x"20",x"30", -- 0x0738 + x"04",x"01",x"01",x"04",x"02",x"01",x"00",x"01", -- 0x0740 + x"00",x"00",x"90",x"CC",x"26",x"80",x"21",x"1C", -- 0x0748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 + x"B8",x"10",x"01",x"03",x"00",x"00",x"80",x"61", -- 0x0760 + x"20",x"90",x"10",x"40",x"40",x"80",x"00",x"00", -- 0x0768 + x"46",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"03", -- 0x0780 + x"00",x"31",x"43",x"88",x"00",x"60",x"C0",x"01", -- 0x0788 + x"02",x"30",x"10",x"20",x"23",x"42",x"40",x"00", -- 0x0790 + x"01",x"06",x"30",x"60",x"C2",x"AD",x"18",x"1D", -- 0x0798 + x"00",x"00",x"80",x"40",x"02",x"03",x"00",x"00", -- 0x07A0 + x"00",x"00",x"00",x"00",x"00",x"80",x"80",x"40", -- 0x07A8 + x"C0",x"68",x"50",x"82",x"F1",x"10",x"28",x"B0", -- 0x07B0 + x"40",x"08",x"04",x"02",x"82",x"C2",x"84",x"00", -- 0x07B8 + x"01",x"19",x"10",x"10",x"88",x"88",x"C4",x"40", -- 0x07C0 + x"05",x"98",x"86",x"47",x"05",x"00",x"40",x"64", -- 0x07C8 + x"60",x"20",x"00",x"04",x"03",x"00",x"00",x"00", -- 0x07D0 + x"3C",x"08",x"00",x"00",x"86",x"C1",x"00",x"00", -- 0x07D8 + x"88",x"10",x"70",x"E0",x"00",x"08",x"18",x"80", -- 0x07E0 + x"00",x"11",x"21",x"C3",x"01",x"11",x"32",x"60", -- 0x07E8 + x"00",x"00",x"04",x"08",x"70",x"C0",x"00",x"00", -- 0x07F0 + x"20",x"40",x"08",x"30",x"40",x"00",x"00",x"00" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd new file mode 100644 index 00000000..b832742c --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_PGM.vhd @@ -0,0 +1,2076 @@ +-- generated with romgen by MikeJ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ROM_PGM is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(13 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_PGM is + + + type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"AF",x"32",x"01",x"68",x"C3",x"69",x"00",x"FF", -- 0x0000 + x"77",x"3C",x"23",x"77",x"3C",x"19",x"C9",x"FF", -- 0x0008 + x"77",x"23",x"10",x"FC",x"C9",x"FF",x"FF",x"FF", -- 0x0010 + x"77",x"23",x"10",x"FC",x"0D",x"18",x"F9",x"C9", -- 0x0018 + x"85",x"6F",x"3E",x"00",x"8C",x"67",x"7E",x"C9", -- 0x0020 + x"87",x"E1",x"5F",x"16",x"00",x"19",x"5E",x"23", -- 0x0028 + x"56",x"EB",x"E9",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0030 + x"E5",x"26",x"40",x"3A",x"A0",x"40",x"6F",x"CB", -- 0x0038 + x"7E",x"28",x"0E",x"72",x"2C",x"73",x"2C",x"7D", -- 0x0040 + x"FE",x"C0",x"30",x"02",x"3E",x"C0",x"32",x"A0", -- 0x0048 + x"40",x"E1",x"C9",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0050 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0058 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"C3",x"CF", -- 0x0060 + x"07",x"21",x"00",x"40",x"11",x"01",x"40",x"01", -- 0x0068 + x"00",x"08",x"36",x"00",x"ED",x"B0",x"3E",x"93", -- 0x0070 + x"32",x"03",x"81",x"3E",x"88",x"32",x"03",x"82", -- 0x0078 + x"31",x"00",x"48",x"21",x"C0",x"40",x"06",x"40", -- 0x0080 + x"3E",x"FF",x"D7",x"3A",x"00",x"70",x"AF",x"32", -- 0x0088 + x"01",x"68",x"32",x"05",x"70",x"32",x"06",x"68", -- 0x0090 + x"32",x"07",x"68",x"21",x"C0",x"C0",x"22",x"A0", -- 0x0098 + x"40",x"3C",x"32",x"04",x"68",x"21",x"00",x"48", -- 0x00A0 + x"22",x"0B",x"40",x"3E",x"20",x"32",x"08",x"40", -- 0x00A8 + x"3E",x"05",x"32",x"17",x"40",x"3A",x"02",x"81", -- 0x00B0 + x"0F",x"47",x"E6",x"03",x"32",x"00",x"40",x"78", -- 0x00B8 + x"0F",x"0F",x"E6",x"01",x"32",x"0F",x"40",x"3A", -- 0x00C0 + x"01",x"81",x"E6",x"03",x"FE",x"03",x"28",x"05", -- 0x00C8 + x"C6",x"03",x"32",x"07",x"40",x"CD",x"C3",x"27", -- 0x00D0 + x"21",x"00",x"00",x"2B",x"3A",x"00",x"70",x"7D", -- 0x00D8 + x"B4",x"00",x"00",x"CD",x"CF",x"27",x"00",x"00", -- 0x00E0 + x"00",x"00",x"00",x"C3",x"C9",x"28",x"26",x"40", -- 0x00E8 + x"3A",x"A1",x"40",x"6F",x"7E",x"87",x"30",x"05", -- 0x00F0 + x"CD",x"31",x"01",x"18",x"F1",x"E6",x"0F",x"4F", -- 0x00F8 + x"06",x"00",x"36",x"FF",x"23",x"5E",x"36",x"FF", -- 0x0100 + x"2C",x"7D",x"FE",x"C0",x"30",x"02",x"3E",x"C0", -- 0x0108 + x"32",x"A1",x"40",x"7B",x"21",x"21",x"01",x"09", -- 0x0110 + x"5E",x"23",x"56",x"21",x"EE",x"00",x"E5",x"EB", -- 0x0118 + x"E9",x"C3",x"02",x"DE",x"02",x"EF",x"02",x"4B", -- 0x0120 + x"03",x"D7",x"03",x"F3",x"03",x"3A",x"04",x"F7", -- 0x0128 + x"06",x"3A",x"5F",x"42",x"47",x"E6",x"0F",x"CA", -- 0x0130 + x"55",x"01",x"21",x"81",x"42",x"CB",x"46",x"C0", -- 0x0138 + x"E6",x"03",x"CA",x"79",x"02",x"FE",x"01",x"28", -- 0x0140 + x"53",x"FE",x"02",x"28",x"76",x"3A",x"00",x"41", -- 0x0148 + x"A7",x"C8",x"C3",x"C3",x"02",x"11",x"E0",x"FF", -- 0x0150 + x"21",x"E0",x"48",x"3A",x"0E",x"40",x"A7",x"28", -- 0x0158 + x"22",x"36",x"02",x"CD",x"8D",x"01",x"21",x"40", -- 0x0160 + x"4B",x"CD",x"8B",x"01",x"3A",x"0D",x"40",x"A7", -- 0x0168 + x"21",x"40",x"4B",x"28",x"03",x"21",x"E0",x"48", -- 0x0170 + x"CB",x"60",x"C8",x"3A",x"06",x"40",x"0F",x"D0", -- 0x0178 + x"C3",x"94",x"01",x"21",x"E0",x"48",x"CD",x"94", -- 0x0180 + x"01",x"18",x"DB",x"36",x"01",x"19",x"36",x"25", -- 0x0188 + x"19",x"36",x"20",x"C9",x"3E",x"10",x"77",x"19", -- 0x0190 + x"77",x"19",x"77",x"C9",x"21",x"7A",x"4B",x"11", -- 0x0198 + x"4F",x"41",x"06",x"02",x"CD",x"11",x"02",x"01", -- 0x01A0 + x"E2",x"FF",x"09",x"7B",x"FE",x"3F",x"28",x"09", -- 0x01A8 + x"FE",x"2F",x"28",x"0A",x"FE",x"1F",x"20",x"EA", -- 0x01B0 + x"C9",x"21",x"3A",x"4A",x"18",x"E4",x"21",x"FA", -- 0x01B8 + x"48",x"18",x"DF",x"21",x"68",x"48",x"11",x"50", -- 0x01C0 + x"41",x"06",x"03",x"CD",x"EA",x"01",x"01",x"1D", -- 0x01C8 + x"00",x"09",x"7B",x"FE",x"80",x"28",x"09",x"FE", -- 0x01D0 + x"B0",x"28",x"0A",x"FE",x"E0",x"C8",x"18",x"E9", -- 0x01D8 + x"21",x"88",x"49",x"18",x"E4",x"21",x"A8",x"4A", -- 0x01E0 + x"18",x"DF",x"1A",x"F5",x"13",x"1A",x"4F",x"F1", -- 0x01E8 + x"CB",x"4F",x"28",x"10",x"79",x"CB",x"4F",x"28", -- 0x01F0 + x"07",x"36",x"C8",x"23",x"13",x"10",x"EB",x"C9", -- 0x01F8 + x"36",x"C9",x"18",x"F7",x"79",x"CB",x"4F",x"28", -- 0x0200 + x"04",x"36",x"CA",x"18",x"EE",x"36",x"10",x"18", -- 0x0208 + x"EA",x"E5",x"D5",x"1A",x"CB",x"4F",x"28",x"25", -- 0x0210 + x"CB",x"57",x"20",x"28",x"CB",x"5F",x"20",x"2B", -- 0x0218 + x"1D",x"1A",x"CB",x"4F",x"28",x"30",x"CB",x"57", -- 0x0220 + x"20",x"30",x"CB",x"5F",x"20",x"36",x"36",x"C8", -- 0x0228 + x"2D",x"1D",x"10",x"DF",x"D1",x"E1",x"2D",x"2D", -- 0x0230 + x"7B",x"D6",x"04",x"5F",x"C9",x"36",x"10",x"2D", -- 0x0238 + x"36",x"10",x"18",x"F0",x"CD",x"71",x"02",x"36", -- 0x0240 + x"5E",x"18",x"F4",x"D6",x"10",x"12",x"E6",x"70", -- 0x0248 + x"20",x"F5",x"1A",x"CB",x"9F",x"12",x"36",x"CA", -- 0x0250 + x"18",x"E5",x"CD",x"71",x"02",x"36",x"C8",x"2D", -- 0x0258 + x"36",x"5F",x"18",x"D0",x"D6",x"10",x"12",x"E6", -- 0x0260 + x"70",x"20",x"F2",x"1A",x"CB",x"9F",x"12",x"18", -- 0x0268 + x"CE",x"CB",x"97",x"CB",x"DF",x"F6",x"70",x"12", -- 0x0270 + x"C9",x"3A",x"BA",x"40",x"0F",x"D0",x"78",x"E6", -- 0x0278 + x"08",x"21",x"AB",x"02",x"28",x"03",x"21",x"B7", -- 0x0280 + x"02",x"06",x"06",x"11",x"20",x"00",x"DD",x"21", -- 0x0288 + x"AC",x"49",x"7E",x"DD",x"77",x"00",x"23",x"DD", -- 0x0290 + x"19",x"10",x"F7",x"06",x"06",x"DD",x"21",x"AD", -- 0x0298 + x"49",x"7E",x"DD",x"77",x"00",x"23",x"DD",x"19", -- 0x02A0 + x"10",x"F7",x"C9",x"10",x"10",x"10",x"10",x"10", -- 0x02A8 + x"10",x"30",x"31",x"32",x"33",x"34",x"35",x"10", -- 0x02B0 + x"10",x"10",x"10",x"10",x"10",x"30",x"31",x"36", -- 0x02B8 + x"37",x"34",x"35",x"21",x"A5",x"49",x"11",x"1F", -- 0x02C0 + x"00",x"DD",x"21",x"04",x"41",x"06",x"06",x"DD", -- 0x02C8 + x"7E",x"00",x"77",x"23",x"DD",x"7E",x"06",x"77", -- 0x02D0 + x"19",x"DD",x"23",x"10",x"F2",x"C9",x"21",x"A5", -- 0x02D8 + x"49",x"11",x"1F",x"00",x"06",x"06",x"3E",x"10", -- 0x02E0 + x"77",x"23",x"77",x"19",x"10",x"FA",x"C9",x"A7", -- 0x02E8 + x"28",x"39",x"3D",x"28",x"22",x"3D",x"87",x"87", -- 0x02F0 + x"87",x"87",x"2F",x"E6",x"30",x"C6",x"C0",x"21", -- 0x02F8 + x"DB",x"49",x"CD",x"38",x"03",x"21",x"DD",x"49", -- 0x0300 + x"CD",x"38",x"03",x"21",x"1B",x"4A",x"CD",x"38", -- 0x0308 + x"03",x"21",x"1D",x"4A",x"C3",x"38",x"03",x"21", -- 0x0310 + x"DB",x"49",x"11",x"1C",x"00",x"0E",x"04",x"06", -- 0x0318 + x"04",x"36",x"10",x"23",x"10",x"FB",x"19",x"0D", -- 0x0320 + x"20",x"F5",x"C9",x"CD",x"17",x"03",x"3E",x"60", -- 0x0328 + x"21",x"FC",x"49",x"C3",x"38",x"03",x"3E",x"10", -- 0x0330 + x"D5",x"11",x"1F",x"00",x"CF",x"CF",x"D1",x"C9", -- 0x0338 + x"3E",x"10",x"D5",x"11",x"DF",x"FF",x"CF",x"C6", -- 0x0340 + x"FC",x"18",x"F2",x"A7",x"28",x"48",x"4F",x"CD", -- 0x0348 + x"A1",x"03",x"87",x"81",x"4F",x"06",x"00",x"21", -- 0x0350 + x"B0",x"03",x"09",x"A7",x"06",x"03",x"1A",x"8E", -- 0x0358 + x"27",x"12",x"13",x"23",x"10",x"F8",x"D5",x"3A", -- 0x0360 + x"0D",x"40",x"0F",x"30",x"02",x"3E",x"01",x"CD", -- 0x0368 + x"F3",x"03",x"D1",x"1B",x"21",x"AA",x"40",x"06", -- 0x0370 + x"03",x"1A",x"BE",x"D8",x"20",x"05",x"1B",x"2B", -- 0x0378 + x"10",x"F7",x"C9",x"CD",x"A1",x"03",x"21",x"A8", -- 0x0380 + x"40",x"06",x"03",x"1A",x"77",x"13",x"23",x"10", -- 0x0388 + x"FA",x"3E",x"02",x"C3",x"F3",x"03",x"CD",x"A1", -- 0x0390 + x"03",x"21",x"AB",x"40",x"A7",x"06",x"03",x"18", -- 0x0398 + x"BD",x"F5",x"3A",x"0D",x"40",x"11",x"A2",x"40", -- 0x03A0 + x"0F",x"30",x"03",x"11",x"A5",x"40",x"F1",x"C9", -- 0x03A8 + x"00",x"00",x"00",x"20",x"00",x"00",x"40",x"00", -- 0x03B0 + x"00",x"60",x"00",x"00",x"80",x"00",x"00",x"00", -- 0x03B8 + x"01",x"00",x"20",x"01",x"00",x"40",x"01",x"00", -- 0x03C0 + x"60",x"01",x"00",x"80",x"01",x"00",x"00",x"02", -- 0x03C8 + x"00",x"00",x"04",x"00",x"00",x"06",x"00",x"F5", -- 0x03D0 + x"21",x"A2",x"40",x"A7",x"28",x"09",x"21",x"A5", -- 0x03D8 + x"40",x"3D",x"28",x"03",x"21",x"A8",x"40",x"36", -- 0x03E0 + x"00",x"23",x"36",x"00",x"23",x"36",x"00",x"F1", -- 0x03E8 + x"C3",x"F3",x"03",x"21",x"A4",x"40",x"DD",x"21", -- 0x03F0 + x"81",x"4B",x"A7",x"28",x"11",x"21",x"A7",x"40", -- 0x03F8 + x"DD",x"21",x"21",x"49",x"3D",x"28",x"07",x"21", -- 0x0400 + x"AA",x"40",x"DD",x"21",x"41",x"4A",x"11",x"E0", -- 0x0408 + x"FF",x"06",x"03",x"0E",x"04",x"7E",x"0F",x"0F", -- 0x0410 + x"0F",x"0F",x"CD",x"25",x"04",x"7E",x"CD",x"25", -- 0x0418 + x"04",x"2B",x"10",x"F1",x"C9",x"E6",x"0F",x"28", -- 0x0420 + x"08",x"0E",x"00",x"DD",x"77",x"00",x"DD",x"19", -- 0x0428 + x"C9",x"79",x"A7",x"28",x"F6",x"3E",x"10",x"0D", -- 0x0430 + x"18",x"F1",x"87",x"F5",x"21",x"A7",x"04",x"E6", -- 0x0438 + x"3F",x"5F",x"16",x"00",x"19",x"5E",x"23",x"56", -- 0x0440 + x"EB",x"5E",x"23",x"56",x"23",x"EB",x"01",x"E0", -- 0x0448 + x"FF",x"F1",x"38",x"0E",x"FA",x"6C",x"04",x"1A", -- 0x0450 + x"FE",x"3F",x"C8",x"D6",x"30",x"77",x"13",x"09", -- 0x0458 + x"18",x"F5",x"1A",x"FE",x"3F",x"C8",x"36",x"10", -- 0x0460 + x"13",x"09",x"18",x"F6",x"22",x"B5",x"40",x"ED", -- 0x0468 + x"53",x"B3",x"40",x"EB",x"7B",x"E6",x"1F",x"47", -- 0x0470 + x"87",x"C6",x"20",x"6F",x"26",x"40",x"22",x"B1", -- 0x0478 + x"40",x"CB",x"3B",x"CB",x"3B",x"7A",x"E6",x"03", -- 0x0480 + x"0F",x"0F",x"B3",x"E6",x"F8",x"4F",x"21",x"00", -- 0x0488 + x"48",x"78",x"85",x"6F",x"11",x"20",x"00",x"43", -- 0x0490 + x"36",x"10",x"19",x"10",x"FB",x"2A",x"B1",x"40", -- 0x0498 + x"71",x"3E",x"01",x"32",x"B0",x"40",x"C9",x"E7", -- 0x04A0 + x"04",x"F4",x"04",x"08",x"05",x"15",x"05",x"22", -- 0x04A8 + x"05",x"2F",x"05",x"4D",x"05",x"5D",x"05",x"66", -- 0x04B0 + x"05",x"74",x"05",x"80",x"05",x"88",x"05",x"8F", -- 0x04B8 + x"05",x"9D",x"05",x"B7",x"05",x"C7",x"05",x"D7", -- 0x04C0 + x"05",x"E7",x"05",x"F8",x"05",x"09",x"06",x"1A", -- 0x04C8 + x"06",x"2B",x"06",x"3C",x"06",x"4D",x"06",x"57", -- 0x04D0 + x"06",x"69",x"06",x"7E",x"06",x"98",x"06",x"AB", -- 0x04D8 + x"06",x"BE",x"06",x"D1",x"06",x"E4",x"06",x"96", -- 0x04E0 + x"4A",x"47",x"41",x"4D",x"45",x"40",x"40",x"4F", -- 0x04E8 + x"56",x"45",x"52",x"3F",x"F1",x"4A",x"50",x"55", -- 0x04F0 + x"53",x"48",x"40",x"53",x"54",x"41",x"52",x"54", -- 0x04F8 + x"40",x"42",x"55",x"54",x"54",x"4F",x"4E",x"3F", -- 0x0500 + x"94",x"4A",x"50",x"4C",x"41",x"59",x"45",x"52", -- 0x0508 + x"40",x"4F",x"4E",x"45",x"3F",x"94",x"4A",x"50", -- 0x0510 + x"4C",x"41",x"59",x"45",x"52",x"40",x"54",x"57", -- 0x0518 + x"4F",x"3F",x"80",x"4A",x"48",x"49",x"47",x"48", -- 0x0520 + x"40",x"53",x"43",x"4F",x"52",x"45",x"3F",x"9F", -- 0x0528 + x"4B",x"40",x"43",x"52",x"45",x"44",x"49",x"54", -- 0x0530 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0538 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x0540 + x"40",x"40",x"40",x"40",x"3F",x"D1",x"4A",x"49", -- 0x0548 + x"4E",x"53",x"45",x"52",x"54",x"40",x"40",x"43", -- 0x0550 + x"4F",x"49",x"4E",x"53",x"3F",x"1E",x"49",x"40", -- 0x0558 + x"40",x"40",x"40",x"40",x"40",x"3F",x"5F",x"4A", -- 0x0560 + x"43",x"48",x"41",x"4E",x"43",x"45",x"40",x"54", -- 0x0568 + x"49",x"4D",x"45",x"3F",x"94",x"4A",x"46",x"49", -- 0x0570 + x"52",x"45",x"40",x"40",x"55",x"46",x"4F",x"3F", -- 0x0578 + x"4D",x"4A",x"40",x"40",x"40",x"40",x"40",x"3F", -- 0x0580 + x"26",x"4A",x"50",x"4C",x"41",x"59",x"3F",x"89", -- 0x0588 + x"4A",x"5B",x"40",x"54",x"48",x"45",x"40",x"45", -- 0x0590 + x"4E",x"44",x"40",x"5B",x"3F",x"4F",x"4B",x"5B", -- 0x0598 + x"40",x"53",x"43",x"4F",x"52",x"45",x"40",x"41", -- 0x05A0 + x"44",x"56",x"41",x"4E",x"43",x"45",x"40",x"54", -- 0x05A8 + x"41",x"42",x"4C",x"45",x"40",x"5B",x"3F",x"92", -- 0x05B0 + x"4A",x"34",x"30",x"40",x"40",x"40",x"40",x"40", -- 0x05B8 + x"40",x"40",x"40",x"40",x"38",x"30",x"3F",x"95", -- 0x05C0 + x"4A",x"36",x"30",x"40",x"40",x"40",x"40",x"40", -- 0x05C8 + x"40",x"40",x"40",x"31",x"32",x"30",x"3F",x"98", -- 0x05D0 + x"4A",x"31",x"30",x"30",x"40",x"40",x"40",x"40", -- 0x05D8 + x"40",x"40",x"40",x"32",x"30",x"30",x"3F",x"BC", -- 0x05E0 + x"4A",x"FD",x"40",x"4B",x"4F",x"4E",x"41",x"4D", -- 0x05E8 + x"49",x"40",x"40",x"31",x"39",x"38",x"30",x"3F", -- 0x05F0 + x"D5",x"4A",x"31",x"40",x"43",x"4F",x"49",x"4E", -- 0x05F8 + x"40",x"40",x"31",x"40",x"50",x"4C",x"41",x"59", -- 0x0600 + x"3F",x"D5",x"4A",x"32",x"40",x"43",x"4F",x"49", -- 0x0608 + x"4E",x"53",x"40",x"31",x"40",x"50",x"4C",x"41", -- 0x0610 + x"59",x"3F",x"D5",x"4A",x"33",x"40",x"43",x"4F", -- 0x0618 + x"49",x"4E",x"53",x"40",x"31",x"40",x"50",x"4C", -- 0x0620 + x"41",x"59",x"3F",x"D5",x"4A",x"31",x"40",x"43", -- 0x0628 + x"4F",x"49",x"4E",x"40",x"40",x"32",x"40",x"50", -- 0x0630 + x"4C",x"41",x"59",x"3F",x"78",x"4B",x"42",x"4F", -- 0x0638 + x"4E",x"55",x"53",x"40",x"53",x"48",x"49",x"50", -- 0x0640 + x"40",x"40",x"40",x"40",x"3F",x"58",x"49",x"30", -- 0x0648 + x"30",x"30",x"40",x"50",x"54",x"53",x"3F",x"D4", -- 0x0650 + x"4A",x"4F",x"4E",x"45",x"40",x"50",x"4C",x"41", -- 0x0658 + x"59",x"45",x"52",x"40",x"4F",x"4E",x"4C",x"59", -- 0x0660 + x"3F",x"F4",x"4A",x"4F",x"4E",x"45",x"40",x"4F", -- 0x0668 + x"52",x"40",x"54",x"57",x"4F",x"40",x"50",x"4C", -- 0x0670 + x"41",x"59",x"45",x"52",x"53",x"3F",x"4D",x"4B", -- 0x0678 + x"5B",x"40",x"53",x"43",x"4F",x"52",x"45",x"40", -- 0x0680 + x"52",x"41",x"4E",x"4B",x"49",x"4E",x"47",x"40", -- 0x0688 + x"54",x"41",x"42",x"4C",x"45",x"40",x"5B",x"3F", -- 0x0690 + x"F0",x"4A",x"31",x"53",x"54",x"40",x"40",x"40", -- 0x0698 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"50", -- 0x06A0 + x"54",x"53",x"3F",x"F2",x"4A",x"32",x"4E",x"44", -- 0x06A8 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x06B0 + x"40",x"40",x"50",x"54",x"53",x"3F",x"F4",x"4A", -- 0x06B8 + x"33",x"52",x"44",x"40",x"40",x"40",x"40",x"40", -- 0x06C0 + x"40",x"40",x"40",x"40",x"40",x"50",x"54",x"53", -- 0x06C8 + x"3F",x"F6",x"4A",x"34",x"54",x"48",x"40",x"40", -- 0x06D0 + x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x06D8 + x"50",x"54",x"53",x"3F",x"F8",x"4A",x"35",x"54", -- 0x06E0 + x"48",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x06E8 + x"40",x"40",x"40",x"50",x"54",x"53",x"3F",x"A7", -- 0x06F0 + x"CA",x"06",x"07",x"3D",x"CA",x"29",x"07",x"3D", -- 0x06F8 + x"CA",x"84",x"07",x"C3",x"67",x"07",x"21",x"9F", -- 0x0700 + x"4B",x"11",x"E0",x"FF",x"3A",x"10",x"41",x"FE", -- 0x0708 + x"15",x"38",x"02",x"3E",x"14",x"47",x"A7",x"28", -- 0x0710 + x"06",x"36",x"CE",x"19",x"3D",x"20",x"F7",x"3E", -- 0x0718 + x"14",x"90",x"47",x"36",x"10",x"19",x"10",x"FB", -- 0x0720 + x"C9",x"3E",x"05",x"CD",x"3A",x"04",x"3A",x"02", -- 0x0728 + x"40",x"FE",x"63",x"38",x"02",x"3E",x"63",x"CD", -- 0x0730 + x"4D",x"07",x"47",x"E6",x"F0",x"28",x"07",x"0F", -- 0x0738 + x"0F",x"0F",x"0F",x"32",x"9F",x"4A",x"78",x"E6", -- 0x0740 + x"0F",x"32",x"7F",x"4A",x"C9",x"47",x"E6",x"0F", -- 0x0748 + x"C6",x"00",x"27",x"4F",x"78",x"E6",x"F0",x"28", -- 0x0750 + x"0B",x"0F",x"0F",x"0F",x"0F",x"47",x"AF",x"C6", -- 0x0758 + x"16",x"27",x"10",x"FB",x"81",x"27",x"C9",x"3A", -- 0x0760 + x"1D",x"41",x"47",x"4F",x"21",x"7F",x"48",x"11", -- 0x0768 + x"20",x"00",x"A7",x"28",x"05",x"36",x"CC",x"19", -- 0x0770 + x"10",x"FB",x"3E",x"06",x"91",x"47",x"36",x"10", -- 0x0778 + x"19",x"10",x"FB",x"C9",x"DD",x"21",x"CE",x"43", -- 0x0780 + x"FD",x"21",x"38",x"4A",x"0E",x"05",x"06",x"03", -- 0x0788 + x"11",x"E0",x"FF",x"26",x"04",x"DD",x"7E",x"00", -- 0x0790 + x"0F",x"0F",x"0F",x"0F",x"CD",x"B2",x"07",x"DD", -- 0x0798 + x"7E",x"00",x"CD",x"B2",x"07",x"DD",x"2B",x"10", -- 0x07A0 + x"EC",x"11",x"BE",x"00",x"FD",x"19",x"0D",x"20", -- 0x07A8 + x"DD",x"C9",x"E6",x"0F",x"6F",x"7C",x"A7",x"20", -- 0x07B0 + x"06",x"FD",x"75",x"00",x"FD",x"19",x"C9",x"7D", -- 0x07B8 + x"A7",x"20",x"04",x"25",x"FD",x"19",x"C9",x"26", -- 0x07C0 + x"00",x"FD",x"75",x"00",x"FD",x"19",x"C9",x"F5", -- 0x07C8 + x"C5",x"D5",x"E5",x"DD",x"E5",x"FD",x"E5",x"AF", -- 0x07D0 + x"32",x"01",x"68",x"21",x"20",x"40",x"11",x"00", -- 0x07D8 + x"50",x"01",x"80",x"00",x"ED",x"B0",x"3A",x"00", -- 0x07E0 + x"70",x"3A",x"15",x"40",x"32",x"16",x"40",x"3A", -- 0x07E8 + x"13",x"40",x"32",x"15",x"40",x"2A",x"10",x"40", -- 0x07F0 + x"22",x"13",x"40",x"21",x"12",x"40",x"3A",x"02", -- 0x07F8 + x"81",x"2F",x"77",x"2B",x"3A",x"01",x"81",x"2F", -- 0x0800 + x"77",x"2B",x"3A",x"00",x"81",x"2F",x"77",x"21", -- 0x0808 + x"5F",x"42",x"35",x"CD",x"39",x"08",x"CD",x"DF", -- 0x0810 + x"27",x"21",x"2B",x"08",x"E5",x"3A",x"05",x"40", -- 0x0818 + x"EF",x"E9",x"08",x"AB",x"09",x"DD",x"0D",x"FD", -- 0x0820 + x"0F",x"21",x"10",x"FD",x"E1",x"DD",x"E1",x"E1", -- 0x0828 + x"D1",x"C1",x"3E",x"01",x"32",x"01",x"68",x"F1", -- 0x0830 + x"C9",x"21",x"18",x"40",x"7E",x"A7",x"28",x"03", -- 0x0838 + x"35",x"3E",x"80",x"32",x"02",x"81",x"21",x"10", -- 0x0840 + x"40",x"7E",x"2C",x"2C",x"2C",x"B6",x"2C",x"2C", -- 0x0848 + x"2F",x"A6",x"2C",x"A6",x"E6",x"C4",x"28",x"24", -- 0x0850 + x"E6",x"C0",x"28",x"05",x"3E",x"06",x"32",x"18", -- 0x0858 + x"40",x"CD",x"B8",x"08",x"CD",x"2E",x"28",x"21", -- 0x0860 + x"02",x"40",x"34",x"7E",x"FE",x"63",x"38",x"02", -- 0x0868 + x"36",x"63",x"3A",x"06",x"40",x"0F",x"38",x"04", -- 0x0870 + x"11",x"01",x"07",x"FF",x"21",x"03",x"40",x"5E", -- 0x0878 + x"16",x"06",x"1A",x"1C",x"73",x"23",x"86",x"3D", -- 0x0880 + x"77",x"3A",x"B0",x"40",x"0F",x"D0",x"2A",x"B1", -- 0x0888 + x"40",x"7E",x"E6",x"07",x"20",x"1B",x"EB",x"2A", -- 0x0890 + x"B3",x"40",x"7E",x"FE",x"3F",x"28",x"11",x"23", -- 0x0898 + x"22",x"B3",x"40",x"D6",x"30",x"2A",x"B5",x"40", -- 0x08A0 + x"77",x"01",x"E0",x"FF",x"09",x"22",x"B5",x"40", -- 0x08A8 + x"EB",x"35",x"C0",x"AF",x"32",x"B0",x"40",x"C9", -- 0x08B0 + x"21",x"02",x"40",x"3A",x"07",x"40",x"A7",x"20", -- 0x08B8 + x"03",x"36",x"63",x"C9",x"3A",x"00",x"40",x"A7", -- 0x08C0 + x"C8",x"3D",x"28",x"05",x"3D",x"28",x"0E",x"34", -- 0x08C8 + x"C9",x"35",x"2D",x"34",x"7E",x"FE",x"02",x"C0", -- 0x08D0 + x"36",x"00",x"2C",x"34",x"C9",x"35",x"2D",x"34", -- 0x08D8 + x"7E",x"FE",x"03",x"C0",x"36",x"00",x"2C",x"34", -- 0x08E0 + x"C9",x"2A",x"0B",x"40",x"06",x"20",x"3E",x"10", -- 0x08E8 + x"D7",x"22",x"0B",x"40",x"21",x"08",x"40",x"35", -- 0x08F0 + x"C0",x"2D",x"2D",x"36",x"00",x"2D",x"36",x"01", -- 0x08F8 + x"AF",x"32",x"0A",x"40",x"21",x"2B",x"09",x"CD", -- 0x0900 + x"1A",x"09",x"11",x"04",x"06",x"FF",x"11",x"00", -- 0x0908 + x"05",x"FF",x"1E",x"02",x"FF",x"AF",x"32",x"80", -- 0x0910 + x"42",x"C9",x"11",x"21",x"40",x"06",x"20",x"7E", -- 0x0918 + x"12",x"23",x"1C",x"EB",x"36",x"00",x"EB",x"1C", -- 0x0920 + x"10",x"F5",x"C9",x"00",x"05",x"00",x"00",x"00", -- 0x0928 + x"01",x"06",x"00",x"03",x"03",x"03",x"01",x"01", -- 0x0930 + x"01",x"01",x"00",x"00",x"00",x"00",x"05",x"05", -- 0x0938 + x"05",x"05",x"05",x"06",x"06",x"06",x"06",x"06", -- 0x0940 + x"06",x"06",x"06",x"00",x"05",x"00",x"00",x"01", -- 0x0948 + x"01",x"06",x"03",x"03",x"04",x"04",x"04",x"04", -- 0x0950 + x"00",x"00",x"00",x"06",x"06",x"06",x"00",x"00", -- 0x0958 + x"00",x"05",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x0960 + x"06",x"06",x"06",x"00",x"05",x"02",x"02",x"02", -- 0x0968 + x"02",x"06",x"02",x"00",x"00",x"02",x"01",x"01", -- 0x0970 + x"01",x"01",x"05",x"06",x"06",x"06",x"06",x"06", -- 0x0978 + x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"00", -- 0x0980 + x"06",x"06",x"06",x"00",x"05",x"00",x"00",x"00", -- 0x0988 + x"00",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 + x"00",x"00",x"00",x"05",x"05",x"02",x"02",x"06", -- 0x0998 + x"06",x"07",x"07",x"04",x"04",x"00",x"00",x"00", -- 0x09A0 + x"06",x"06",x"06",x"21",x"C1",x"0D",x"E5",x"3A", -- 0x09A8 + x"80",x"42",x"EF",x"D3",x"09",x"11",x"0A",x"4B", -- 0x09B0 + x"0A",x"6C",x"0A",x"9E",x"0A",x"B2",x"0A",x"CF", -- 0x09B8 + x"0A",x"10",x"0B",x"39",x"0B",x"3A",x"0B",x"3B", -- 0x09C0 + x"0B",x"55",x"0B",x"D1",x"0B",x"21",x"0C",x"3C", -- 0x09C8 + x"0C",x"3D",x"0C",x"CD",x"69",x"28",x"21",x"20", -- 0x09D0 + x"40",x"11",x"21",x"40",x"01",x"7F",x"00",x"36", -- 0x09D8 + x"00",x"ED",x"B0",x"21",x"00",x"41",x"11",x"01", -- 0x09E0 + x"41",x"01",x"FF",x"01",x"36",x"00",x"ED",x"B0", -- 0x09E8 + x"21",x"A0",x"42",x"11",x"A1",x"42",x"01",x"FF", -- 0x09F0 + x"00",x"36",x"00",x"ED",x"B0",x"21",x"02",x"48", -- 0x09F8 + x"22",x"0B",x"40",x"21",x"09",x"40",x"36",x"20", -- 0x0A00 + x"21",x"80",x"42",x"34",x"AF",x"32",x"06",x"40", -- 0x0A08 + x"C9",x"2A",x"0B",x"40",x"06",x"1E",x"3E",x"10", -- 0x0A10 + x"D7",x"11",x"02",x"00",x"19",x"22",x"0B",x"40", -- 0x0A18 + x"21",x"09",x"40",x"35",x"C0",x"21",x"6B",x"09", -- 0x0A20 + x"CD",x"1A",x"09",x"AF",x"32",x"06",x"68",x"32", -- 0x0A28 + x"07",x"68",x"21",x"80",x"42",x"34",x"2C",x"36", -- 0x0A30 + x"01",x"2C",x"36",x"0B",x"2C",x"36",x"1E",x"11", -- 0x0A38 + x"01",x"07",x"FF",x"11",x"11",x"06",x"FF",x"1E", -- 0x0A40 + x"07",x"FF",x"C9",x"21",x"83",x"42",x"35",x"C0", -- 0x0A48 + x"36",x"1E",x"2D",x"5E",x"34",x"16",x"06",x"FF", -- 0x0A50 + x"7B",x"FE",x"0E",x"C0",x"2D",x"2D",x"34",x"21", -- 0x0A58 + x"F8",x"0A",x"22",x"84",x"42",x"21",x"60",x"40", -- 0x0A60 + x"22",x"86",x"42",x"C9",x"21",x"83",x"42",x"35", -- 0x0A68 + x"C0",x"36",x"1E",x"2D",x"5E",x"34",x"16",x"06", -- 0x0A70 + x"FF",x"2A",x"84",x"42",x"ED",x"5B",x"86",x"42", -- 0x0A78 + x"01",x"08",x"00",x"ED",x"B0",x"22",x"84",x"42", -- 0x0A80 + x"ED",x"53",x"86",x"42",x"3A",x"82",x"42",x"FE", -- 0x0A88 + x"12",x"C0",x"21",x"80",x"42",x"34",x"2C",x"2C", -- 0x0A90 + x"36",x"0C",x"2C",x"36",x"1E",x"C9",x"21",x"83", -- 0x0A98 + x"42",x"35",x"C0",x"36",x"0F",x"11",x"0E",x"06", -- 0x0AA0 + x"FF",x"1C",x"FF",x"1C",x"FF",x"2D",x"2D",x"2D", -- 0x0AA8 + x"34",x"C9",x"21",x"83",x"42",x"35",x"C0",x"36", -- 0x0AB0 + x"0F",x"11",x"8E",x"06",x"FF",x"1C",x"FF",x"1C", -- 0x0AB8 + x"FF",x"2D",x"35",x"28",x"04",x"2D",x"2D",x"35", -- 0x0AC0 + x"C9",x"36",x"14",x"2D",x"2D",x"34",x"C9",x"21", -- 0x0AC8 + x"82",x"42",x"35",x"C0",x"36",x"96",x"11",x"8D", -- 0x0AD0 + x"06",x"FF",x"21",x"60",x"40",x"11",x"61",x"40", -- 0x0AD8 + x"01",x"1F",x"00",x"36",x"00",x"ED",x"B0",x"3A", -- 0x0AE0 + x"00",x"40",x"C6",x"12",x"5F",x"16",x"06",x"FF", -- 0x0AE8 + x"1E",x"06",x"FF",x"21",x"80",x"42",x"34",x"C9", -- 0x0AF0 + x"34",x"EB",x"07",x"8B",x"8B",x"22",x"07",x"8B", -- 0x0AF8 + x"34",x"EB",x"03",x"A3",x"8B",x"22",x"03",x"A3", -- 0x0B00 + x"34",x"EB",x"01",x"BB",x"8B",x"22",x"01",x"BB", -- 0x0B08 + x"21",x"82",x"42",x"35",x"C0",x"21",x"8B",x"09", -- 0x0B10 + x"CD",x"1A",x"09",x"11",x"92",x"06",x"FF",x"1E", -- 0x0B18 + x"86",x"FF",x"1E",x"1A",x"06",x"06",x"FF",x"1C", -- 0x0B20 + x"10",x"FC",x"11",x"02",x"07",x"FF",x"21",x"80", -- 0x0B28 + x"42",x"34",x"34",x"34",x"2C",x"2C",x"36",x"DC", -- 0x0B30 + x"C9",x"C9",x"C9",x"3A",x"5F",x"42",x"0F",x"D8", -- 0x0B38 + x"21",x"82",x"42",x"35",x"C0",x"3E",x"20",x"32", -- 0x0B40 + x"09",x"40",x"21",x"02",x"48",x"22",x"0B",x"40", -- 0x0B48 + x"21",x"80",x"42",x"34",x"C9",x"2A",x"0B",x"40", -- 0x0B50 + x"06",x"1D",x"3E",x"10",x"D7",x"11",x"03",x"00", -- 0x0B58 + x"19",x"22",x"0B",x"40",x"21",x"09",x"40",x"35", -- 0x0B60 + x"C0",x"21",x"2B",x"09",x"CD",x"1A",x"09",x"21", -- 0x0B68 + x"C0",x"0B",x"22",x"07",x"42",x"AF",x"32",x"5F", -- 0x0B70 + x"42",x"32",x"06",x"68",x"32",x"07",x"68",x"32", -- 0x0B78 + x"0D",x"40",x"21",x"1D",x"0F",x"11",x"00",x"41", -- 0x0B80 + x"01",x"E0",x"00",x"ED",x"B0",x"21",x"3E",x"0C", -- 0x0B88 + x"11",x"50",x"41",x"01",x"90",x"00",x"ED",x"B0", -- 0x0B90 + x"3E",x"01",x"32",x"00",x"41",x"3E",x"0A",x"32", -- 0x0B98 + x"1A",x"41",x"21",x"01",x"00",x"22",x"00",x"42", -- 0x0BA0 + x"3E",x"7F",x"32",x"02",x"42",x"AF",x"32",x"58", -- 0x0BA8 + x"40",x"32",x"5A",x"40",x"11",x"00",x"02",x"FF", -- 0x0BB0 + x"21",x"80",x"42",x"34",x"2C",x"36",x"00",x"C9", -- 0x0BB8 + x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x0BC0 + x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x0BC8 + x"FF",x"CD",x"38",x"1A",x"CD",x"5E",x"1A",x"CD", -- 0x0BD0 + x"53",x"16",x"CD",x"66",x"16",x"3A",x"16",x"41", -- 0x0BD8 + x"A7",x"CC",x"93",x"1A",x"CD",x"CE",x"0C",x"CD", -- 0x0BE0 + x"F7",x"15",x"CD",x"E3",x"16",x"CD",x"45",x"0D", -- 0x0BE8 + x"CD",x"35",x"18",x"3A",x"8B",x"42",x"A7",x"CC", -- 0x0BF0 + x"A4",x"19",x"CD",x"0B",x"19",x"3A",x"1A",x"41", -- 0x0BF8 + x"A7",x"28",x"07",x"3A",x"11",x"41",x"A7",x"28", -- 0x0C00 + x"01",x"C9",x"21",x"80",x"42",x"34",x"2C",x"2C", -- 0x0C08 + x"36",x"B4",x"AF",x"32",x"90",x"42",x"CD",x"70", -- 0x0C10 + x"10",x"11",x"00",x"06",x"FF",x"1E",x"02",x"FF", -- 0x0C18 + x"C9",x"CD",x"5E",x"1A",x"CD",x"53",x"16",x"CD", -- 0x0C20 + x"66",x"16",x"CD",x"AD",x"13",x"3A",x"5F",x"42", -- 0x0C28 + x"0F",x"D8",x"21",x"82",x"42",x"35",x"C0",x"2D", -- 0x0C30 + x"2D",x"36",x"00",x"C9",x"C9",x"C9",x"00",x"03", -- 0x0C38 + x"03",x"03",x"01",x"00",x"00",x"03",x"03",x"03", -- 0x0C40 + x"01",x"00",x"03",x"00",x"00",x"00",x"00",x"01", -- 0x0C48 + x"03",x"00",x"00",x"00",x"00",x"01",x"03",x"00", -- 0x0C50 + x"00",x"00",x"00",x"01",x"03",x"00",x"00",x"00", -- 0x0C58 + x"00",x"01",x"03",x"03",x"03",x"03",x"01",x"01", -- 0x0C60 + x"03",x"03",x"03",x"03",x"01",x"01",x"03",x"03", -- 0x0C68 + x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0C70 + x"03",x"03",x"00",x"00",x"00",x"00",x"03",x"03", -- 0x0C78 + x"00",x"00",x"00",x"03",x"03",x"00",x"00",x"00", -- 0x0C80 + x"03",x"03",x"00",x"00",x"00",x"03",x"03",x"00", -- 0x0C88 + x"00",x"00",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0C90 + x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"00", -- 0x0C98 + x"00",x"00",x"00",x"03",x"03",x"00",x"03",x"03", -- 0x0CA0 + x"00",x"03",x"03",x"00",x"03",x"03",x"00",x"03", -- 0x0CA8 + x"03",x"00",x"03",x"03",x"00",x"03",x"03",x"00", -- 0x0CB0 + x"03",x"03",x"00",x"03",x"03",x"00",x"03",x"03", -- 0x0CB8 + x"00",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0CC0 + x"03",x"03",x"03",x"03",x"03",x"03",x"3A",x"16", -- 0x0CC8 + x"41",x"A7",x"C8",x"3A",x"88",x"42",x"EF",x"DD", -- 0x0CD0 + x"0C",x"F3",x"0C",x"16",x"0D",x"ED",x"5F",x"0F", -- 0x0CD8 + x"3E",x"68",x"38",x"02",x"3E",x"B8",x"21",x"88", -- 0x0CE0 + x"42",x"34",x"2C",x"77",x"2C",x"36",x"28",x"2C", -- 0x0CE8 + x"36",x"01",x"C9",x"21",x"02",x"42",x"3A",x"89", -- 0x0CF0 + x"42",x"BE",x"28",x"11",x"38",x"03",x"34",x"18", -- 0x0CF8 + x"01",x"35",x"7E",x"2F",x"C6",x"80",x"32",x"58", -- 0x0D00 + x"40",x"32",x"5A",x"40",x"C9",x"21",x"88",x"42", -- 0x0D08 + x"34",x"AF",x"32",x"8B",x"42",x"C9",x"21",x"64", -- 0x0D10 + x"42",x"CB",x"46",x"C8",x"2C",x"3A",x"02",x"42", -- 0x0D18 + x"C6",x"08",x"96",x"D8",x"FE",x"10",x"D0",x"2C", -- 0x0D20 + x"2C",x"7E",x"FE",x"B8",x"D8",x"21",x"02",x"42", -- 0x0D28 + x"35",x"7E",x"2F",x"C6",x"80",x"32",x"58",x"40", -- 0x0D30 + x"32",x"5A",x"40",x"21",x"8A",x"42",x"35",x"C0", -- 0x0D38 + x"2D",x"2D",x"36",x"00",x"C9",x"3A",x"7C",x"42", -- 0x0D40 + x"0F",x"D8",x"DD",x"21",x"A0",x"42",x"11",x"20", -- 0x0D48 + x"00",x"06",x"08",x"D9",x"CD",x"5D",x"0D",x"D9", -- 0x0D50 + x"DD",x"19",x"10",x"F7",x"C9",x"DD",x"CB",x"00", -- 0x0D58 + x"46",x"C8",x"DD",x"CB",x"08",x"46",x"C8",x"DD", -- 0x0D60 + x"CB",x"09",x"46",x"C0",x"DD",x"7E",x"0B",x"FE", -- 0x0D68 + x"80",x"D0",x"DD",x"7E",x"03",x"FE",x"60",x"D8", -- 0x0D70 + x"FE",x"C0",x"D0",x"DD",x"4E",x"06",x"DD",x"46", -- 0x0D78 + x"08",x"3A",x"02",x"42",x"05",x"28",x"09",x"B9", -- 0x0D80 + x"D8",x"4F",x"DD",x"7E",x"04",x"91",x"18",x"05", -- 0x0D88 + x"B9",x"D0",x"DD",x"96",x"04",x"D8",x"47",x"3E", -- 0x0D90 + x"E0",x"DD",x"96",x"03",x"DD",x"CB",x"19",x"46", -- 0x0D98 + x"20",x"13",x"DD",x"4E",x"16",x"0D",x"28",x"0D", -- 0x0DA0 + x"0F",x"0F",x"0F",x"E6",x"1F",x"B8",x"C0",x"3E", -- 0x0DA8 + x"01",x"32",x"7C",x"42",x"C9",x"0F",x"0F",x"E6", -- 0x0DB0 + x"3F",x"B8",x"C0",x"3E",x"01",x"32",x"7C",x"42", -- 0x0DB8 + x"C9",x"3A",x"02",x"40",x"A7",x"C8",x"21",x"05", -- 0x0DC0 + x"40",x"34",x"AF",x"32",x"0A",x"40",x"32",x"81", -- 0x0DC8 + x"42",x"21",x"21",x"0F",x"11",x"04",x"41",x"01", -- 0x0DD0 + x"0C",x"00",x"ED",x"B0",x"C9",x"21",x"75",x"0E", -- 0x0DD8 + x"E5",x"3A",x"0A",x"40",x"EF",x"EB",x"0D",x"21", -- 0x0DE0 + x"0E",x"67",x"0E",x"AF",x"32",x"00",x"41",x"11", -- 0x0DE8 + x"00",x"01",x"FF",x"21",x"4B",x"09",x"CD",x"1A", -- 0x0DF0 + x"09",x"21",x"60",x"40",x"06",x"40",x"AF",x"D7", -- 0x0DF8 + x"21",x"60",x"42",x"D7",x"06",x"40",x"D7",x"21", -- 0x0E00 + x"20",x"41",x"06",x"C0",x"D7",x"32",x"B0",x"40", -- 0x0E08 + x"32",x"06",x"40",x"21",x"02",x"48",x"22",x"0B", -- 0x0E10 + x"40",x"21",x"09",x"40",x"36",x"10",x"2C",x"34", -- 0x0E18 + x"C9",x"2A",x"0B",x"40",x"06",x"1D",x"3E",x"10", -- 0x0E20 + x"D7",x"11",x"03",x"00",x"19",x"06",x"1D",x"D7", -- 0x0E28 + x"19",x"22",x"0B",x"40",x"21",x"09",x"40",x"35", -- 0x0E30 + x"C0",x"2C",x"34",x"AF",x"32",x"06",x"68",x"32", -- 0x0E38 + x"07",x"68",x"32",x"0D",x"40",x"11",x"01",x"07", -- 0x0E40 + x"FF",x"11",x"01",x"06",x"FF",x"1E",x"16",x"FF", -- 0x0E48 + x"1C",x"FF",x"3A",x"17",x"40",x"47",x"E6",x"0F", -- 0x0E50 + x"32",x"78",x"49",x"78",x"E6",x"F0",x"C8",x"0F", -- 0x0E58 + x"0F",x"0F",x"0F",x"32",x"98",x"49",x"C9",x"3A", -- 0x0E60 + x"02",x"40",x"A7",x"C8",x"3D",x"11",x"18",x"06", -- 0x0E68 + x"28",x"01",x"1C",x"FF",x"C9",x"3A",x"11",x"40", -- 0x0E70 + x"CB",x"7F",x"C2",x"07",x"0F",x"CB",x"77",x"C8", -- 0x0E78 + x"3A",x"02",x"40",x"FE",x"02",x"D8",x"D6",x"02", -- 0x0E80 + x"32",x"02",x"40",x"21",x"00",x"01",x"22",x"0D", -- 0x0E88 + x"40",x"AF",x"32",x"0A",x"40",x"3E",x"03",x"32", -- 0x0E90 + x"05",x"40",x"3E",x"01",x"32",x"06",x"40",x"11", -- 0x0E98 + x"04",x"06",x"FF",x"21",x"1D",x"0F",x"11",x"00", -- 0x0EA0 + x"41",x"01",x"E0",x"00",x"ED",x"B0",x"21",x"1D", -- 0x0EA8 + x"0F",x"11",x"E0",x"41",x"01",x"20",x"00",x"ED", -- 0x0EB0 + x"B0",x"DD",x"21",x"20",x"41",x"21",x"10",x"42", -- 0x0EB8 + x"0E",x"30",x"06",x"04",x"CB",x"26",x"CB",x"26", -- 0x0EC0 + x"DD",x"CB",x"00",x"46",x"28",x"02",x"CB",x"C6", -- 0x0EC8 + x"DD",x"CB",x"00",x"4E",x"28",x"02",x"CB",x"CE", -- 0x0ED0 + x"DD",x"23",x"10",x"E8",x"23",x"0D",x"20",x"E2", -- 0x0ED8 + x"3E",x"01",x"32",x"00",x"41",x"32",x"E0",x"41", -- 0x0EE0 + x"3A",x"07",x"40",x"32",x"1D",x"41",x"32",x"FD", -- 0x0EE8 + x"41",x"AF",x"32",x"52",x"40",x"32",x"54",x"40", -- 0x0EF0 + x"CD",x"36",x"28",x"11",x"00",x"04",x"FF",x"3A", -- 0x0EF8 + x"0E",x"40",x"0F",x"D0",x"1C",x"FF",x"C9",x"3A", -- 0x0F00 + x"02",x"40",x"A7",x"28",x"0A",x"3D",x"32",x"02", -- 0x0F08 + x"40",x"21",x"00",x"00",x"C3",x"8E",x"0E",x"3E", -- 0x0F10 + x"01",x"32",x"05",x"40",x"C9",x"00",x"80",x"00", -- 0x0F18 + x"06",x"6C",x"64",x"64",x"64",x"64",x"65",x"30", -- 0x0F20 + x"31",x"32",x"33",x"34",x"35",x"00",x"2E",x"00", -- 0x0F28 + x"00",x"00",x"00",x"00",x"1C",x"20",x"24",x"5E", -- 0x0F30 + x"30",x"00",x"03",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x0F68 + x"01",x"01",x"00",x"00",x"01",x"01",x"01",x"01", -- 0x0F70 + x"00",x"01",x"00",x"00",x"00",x"00",x"01",x"01", -- 0x0F78 + x"00",x"00",x"00",x"00",x"01",x"01",x"00",x"00", -- 0x0F80 + x"00",x"00",x"01",x"01",x"00",x"00",x"00",x"00", -- 0x0F88 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0F90 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0F98 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0FA0 + x"01",x"00",x"00",x"00",x"00",x"01",x"01",x"00", -- 0x0FA8 + x"00",x"00",x"01",x"01",x"00",x"00",x"00",x"01", -- 0x0FB0 + x"01",x"00",x"00",x"00",x"01",x"01",x"00",x"00", -- 0x0FB8 + x"00",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0FC0 + x"01",x"01",x"01",x"01",x"01",x"01",x"00",x"00", -- 0x0FC8 + x"00",x"00",x"01",x"01",x"00",x"01",x"01",x"00", -- 0x0FD0 + x"01",x"01",x"00",x"01",x"01",x"00",x"01",x"01", -- 0x0FD8 + x"00",x"01",x"01",x"00",x"01",x"01",x"00",x"01", -- 0x0FE0 + x"01",x"00",x"01",x"01",x"00",x"01",x"01",x"00", -- 0x0FE8 + x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0FF0 + x"01",x"01",x"01",x"01",x"01",x"CD",x"38",x"1A", -- 0x0FF8 + x"CD",x"5E",x"1A",x"CD",x"53",x"16",x"CD",x"66", -- 0x1000 + x"16",x"3A",x"0A",x"40",x"EF",x"45",x"10",x"7F", -- 0x1008 + x"10",x"98",x"10",x"00",x"11",x"0E",x"11",x"48", -- 0x1010 + x"11",x"D7",x"11",x"08",x"12",x"66",x"13",x"97", -- 0x1018 + x"13",x"CD",x"38",x"1A",x"CD",x"5E",x"1A",x"CD", -- 0x1020 + x"53",x"16",x"CD",x"66",x"16",x"3A",x"0A",x"40", -- 0x1028 + x"EF",x"45",x"10",x"7F",x"10",x"CC",x"10",x"00", -- 0x1030 + x"11",x"0E",x"11",x"48",x"11",x"4A",x"12",x"6C", -- 0x1038 + x"12",x"66",x"13",x"97",x"13",x"CD",x"69",x"28", -- 0x1040 + x"AF",x"32",x"81",x"42",x"21",x"00",x"42",x"06", -- 0x1048 + x"10",x"D7",x"21",x"60",x"42",x"D7",x"06",x"40", -- 0x1050 + x"D7",x"CD",x"70",x"10",x"21",x"53",x"19",x"22", -- 0x1058 + x"07",x"42",x"21",x"0A",x"40",x"34",x"2D",x"36", -- 0x1060 + x"20",x"21",x"00",x"48",x"22",x"0B",x"40",x"C9", -- 0x1068 + x"21",x"60",x"40",x"06",x"40",x"AF",x"D7",x"AF", -- 0x1070 + x"32",x"52",x"40",x"32",x"54",x"40",x"C9",x"2A", -- 0x1078 + x"0B",x"40",x"06",x"20",x"3E",x"10",x"D7",x"22", -- 0x1080 + x"0B",x"40",x"21",x"09",x"40",x"35",x"C0",x"2C", -- 0x1088 + x"34",x"21",x"2B",x"09",x"CD",x"1A",x"09",x"C9", -- 0x1090 + x"AF",x"32",x"5F",x"42",x"32",x"06",x"68",x"32", -- 0x1098 + x"07",x"68",x"32",x"0D",x"40",x"21",x"0A",x"40", -- 0x10A0 + x"34",x"2D",x"36",x"96",x"3A",x"0E",x"40",x"0F", -- 0x10A8 + x"38",x"14",x"11",x"00",x"05",x"FF",x"1E",x"02", -- 0x10B0 + x"FF",x"14",x"FF",x"1E",x"04",x"FF",x"11",x"03", -- 0x10B8 + x"07",x"FF",x"1E",x"00",x"FF",x"C9",x"11",x"01", -- 0x10C0 + x"05",x"FF",x"18",x"E6",x"AF",x"32",x"5F",x"42", -- 0x10C8 + x"3A",x"0F",x"40",x"0F",x"30",x"08",x"3E",x"01", -- 0x10D0 + x"32",x"06",x"68",x"32",x"07",x"68",x"3E",x"01", -- 0x10D8 + x"32",x"0D",x"40",x"21",x"0A",x"40",x"34",x"2D", -- 0x10E0 + x"36",x"96",x"11",x"00",x"05",x"FF",x"1C",x"FF", -- 0x10E8 + x"1C",x"FF",x"11",x"03",x"06",x"FF",x"1C",x"FF", -- 0x10F0 + x"11",x"03",x"07",x"FF",x"1E",x"00",x"FF",x"C9", -- 0x10F8 + x"21",x"09",x"40",x"35",x"C0",x"36",x"14",x"2C", -- 0x1100 + x"34",x"11",x"82",x"06",x"FF",x"C9",x"21",x"09", -- 0x1108 + x"40",x"35",x"C0",x"36",x"0A",x"2C",x"34",x"21", -- 0x1110 + x"60",x"42",x"06",x"20",x"AF",x"D7",x"21",x"01", -- 0x1118 + x"00",x"22",x"00",x"42",x"3E",x"80",x"32",x"02", -- 0x1120 + x"42",x"AF",x"32",x"58",x"40",x"32",x"5A",x"40", -- 0x1128 + x"3A",x"07",x"40",x"A7",x"20",x"05",x"3E",x"02", -- 0x1130 + x"32",x"1D",x"41",x"21",x"1D",x"41",x"35",x"11", -- 0x1138 + x"03",x"07",x"FF",x"11",x"00",x"02",x"FF",x"C9", -- 0x1140 + x"CD",x"78",x"27",x"CD",x"56",x"15",x"CD",x"53", -- 0x1148 + x"13",x"CD",x"8D",x"15",x"CD",x"A3",x"15",x"CD", -- 0x1150 + x"F7",x"15",x"CD",x"E3",x"16",x"CD",x"B4",x"16", -- 0x1158 + x"CD",x"35",x"18",x"CD",x"D6",x"18",x"CD",x"6C", -- 0x1160 + x"19",x"CD",x"A4",x"19",x"CD",x"17",x"1A",x"CD", -- 0x1168 + x"0B",x"19",x"3A",x"1A",x"41",x"A7",x"28",x"29", -- 0x1170 + x"3A",x"11",x"41",x"A7",x"28",x"31",x"21",x"00", -- 0x1178 + x"42",x"CB",x"46",x"C0",x"23",x"CB",x"46",x"C0", -- 0x1180 + x"3A",x"7C",x"42",x"0F",x"D8",x"3A",x"60",x"42", -- 0x1188 + x"47",x"3A",x"64",x"42",x"4F",x"3A",x"68",x"42", -- 0x1190 + x"B0",x"B1",x"0F",x"D8",x"21",x"0A",x"40",x"34", -- 0x1198 + x"C9",x"3A",x"01",x"42",x"0F",x"D8",x"AF",x"32", -- 0x11A0 + x"1D",x"41",x"21",x"0A",x"40",x"34",x"C9",x"21", -- 0x11A8 + x"00",x"42",x"CB",x"46",x"20",x"06",x"2C",x"CB", -- 0x11B0 + x"46",x"C0",x"18",x"CC",x"AF",x"21",x"60",x"42", -- 0x11B8 + x"06",x"20",x"D7",x"21",x"80",x"40",x"06",x"20", -- 0x11C0 + x"D7",x"21",x"B7",x"40",x"36",x"00",x"23",x"36", -- 0x11C8 + x"00",x"3E",x"08",x"32",x"0A",x"40",x"C9",x"3A", -- 0x11D0 + x"1D",x"41",x"A7",x"20",x"14",x"11",x"00",x"06", -- 0x11D8 + x"FF",x"1E",x"02",x"FF",x"21",x"0A",x"40",x"36", -- 0x11E0 + x"09",x"2B",x"36",x"B4",x"AF",x"32",x"90",x"42", -- 0x11E8 + x"C9",x"3A",x"0E",x"40",x"0F",x"38",x"09",x"21", -- 0x11F0 + x"0A",x"40",x"36",x"04",x"2B",x"36",x"64",x"C9", -- 0x11F8 + x"21",x"0A",x"40",x"34",x"2D",x"36",x"64",x"C9", -- 0x1200 + x"21",x"09",x"40",x"35",x"C0",x"3A",x"1D",x"41", -- 0x1208 + x"A7",x"20",x"0C",x"3A",x"0E",x"40",x"0F",x"38", -- 0x1210 + x"15",x"3E",x"01",x"32",x"05",x"40",x"C9",x"3A", -- 0x1218 + x"FD",x"41",x"A7",x"20",x"15",x"21",x"0A",x"40", -- 0x1220 + x"36",x"04",x"2B",x"36",x"01",x"C9",x"3A",x"FD", -- 0x1228 + x"41",x"A7",x"20",x"06",x"3E",x"01",x"32",x"05", -- 0x1230 + x"40",x"C9",x"CD",x"A2",x"12",x"CD",x"E3",x"12", -- 0x1238 + x"AF",x"32",x"0A",x"40",x"3E",x"04",x"32",x"05", -- 0x1240 + x"40",x"C9",x"3A",x"1D",x"41",x"A7",x"20",x"14", -- 0x1248 + x"11",x"00",x"06",x"FF",x"1E",x"03",x"FF",x"21", -- 0x1250 + x"0A",x"40",x"36",x"09",x"2B",x"36",x"B4",x"AF", -- 0x1258 + x"32",x"90",x"42",x"C9",x"21",x"0A",x"40",x"34", -- 0x1260 + x"2D",x"36",x"64",x"C9",x"21",x"09",x"40",x"35", -- 0x1268 + x"C0",x"3A",x"1D",x"41",x"A7",x"20",x"0C",x"3A", -- 0x1270 + x"FD",x"41",x"A7",x"20",x"15",x"3E",x"01",x"32", -- 0x1278 + x"05",x"40",x"C9",x"3A",x"FD",x"41",x"A7",x"20", -- 0x1280 + x"09",x"21",x"0A",x"40",x"36",x"04",x"2B",x"36", -- 0x1288 + x"01",x"C9",x"CD",x"A2",x"12",x"CD",x"E3",x"12", -- 0x1290 + x"AF",x"32",x"0A",x"40",x"3E",x"03",x"32",x"05", -- 0x1298 + x"40",x"C9",x"AF",x"21",x"A0",x"42",x"11",x"20", -- 0x12A0 + x"00",x"06",x"08",x"CB",x"46",x"28",x"01",x"3C", -- 0x12A8 + x"19",x"10",x"F8",x"47",x"21",x"12",x"41",x"7E", -- 0x12B0 + x"90",x"77",x"21",x"21",x"0F",x"11",x"04",x"41", -- 0x12B8 + x"01",x"0C",x"00",x"ED",x"B0",x"3A",x"12",x"41", -- 0x12C0 + x"A7",x"C8",x"47",x"16",x"00",x"DD",x"21",x"C3", -- 0x12C8 + x"1D",x"21",x"04",x"41",x"DD",x"5E",x"00",x"19", -- 0x12D0 + x"DD",x"7E",x"01",x"77",x"1E",x"05",x"DD",x"19", -- 0x12D8 + x"10",x"EF",x"C9",x"21",x"00",x"41",x"DD",x"21", -- 0x12E0 + x"E0",x"41",x"06",x"20",x"DD",x"7E",x"00",x"4E", -- 0x12E8 + x"DD",x"71",x"00",x"77",x"DD",x"23",x"23",x"10", -- 0x12F0 + x"F3",x"DD",x"21",x"20",x"41",x"FD",x"21",x"10", -- 0x12F8 + x"42",x"06",x"30",x"FD",x"4E",x"00",x"3E",x"03", -- 0x1300 + x"A1",x"6F",x"CB",x"09",x"CB",x"09",x"3E",x"03", -- 0x1308 + x"A1",x"67",x"CB",x"09",x"CB",x"09",x"3E",x"03", -- 0x1310 + x"A1",x"5F",x"CB",x"09",x"CB",x"09",x"3E",x"03", -- 0x1318 + x"A1",x"57",x"FD",x"23",x"0E",x"04",x"CB",x"27", -- 0x1320 + x"CB",x"27",x"DD",x"CB",x"00",x"4E",x"28",x"02", -- 0x1328 + x"CB",x"CF",x"DD",x"CB",x"00",x"46",x"28",x"02", -- 0x1330 + x"CB",x"C7",x"DD",x"23",x"0D",x"20",x"E7",x"DD", -- 0x1338 + x"72",x"FC",x"DD",x"73",x"FD",x"DD",x"74",x"FE", -- 0x1340 + x"DD",x"75",x"FF",x"FD",x"77",x"FF",x"05",x"C2", -- 0x1348 + x"03",x"13",x"C9",x"3A",x"1C",x"41",x"0F",x"D0", -- 0x1350 + x"3A",x"5F",x"42",x"E6",x"10",x"11",x"08",x"06", -- 0x1358 + x"28",x"02",x"1E",x"88",x"FF",x"C9",x"3A",x"16", -- 0x1360 + x"41",x"A7",x"CC",x"93",x"1A",x"3A",x"B7",x"40", -- 0x1368 + x"EF",x"FD",x"23",x"4C",x"24",x"73",x"24",x"7E", -- 0x1370 + x"24",x"91",x"24",x"A5",x"24",x"DE",x"24",x"DF", -- 0x1378 + x"24",x"24",x"25",x"57",x"25",x"8B",x"25",x"00", -- 0x1380 + x"26",x"28",x"26",x"36",x"26",x"50",x"26",x"5D", -- 0x1388 + x"26",x"7F",x"26",x"8E",x"26",x"F4",x"26",x"CD", -- 0x1390 + x"AD",x"13",x"3A",x"5F",x"42",x"0F",x"D8",x"21", -- 0x1398 + x"09",x"40",x"35",x"C0",x"36",x"0A",x"2C",x"36", -- 0x13A0 + x"07",x"CD",x"03",x"15",x"C9",x"CD",x"BE",x"13", -- 0x13A8 + x"3A",x"90",x"42",x"EF",x"F7",x"13",x"12",x"14", -- 0x13B0 + x"6A",x"14",x"B9",x"14",x"D6",x"14",x"3A",x"5F", -- 0x13B8 + x"42",x"E6",x"07",x"C0",x"21",x"9B",x"42",x"7E", -- 0x13C0 + x"3C",x"FE",x"06",x"20",x"01",x"AF",x"77",x"21", -- 0x13C8 + x"FD",x"14",x"4F",x"06",x"00",x"09",x"7E",x"32", -- 0x13D0 + x"31",x"40",x"32",x"33",x"40",x"32",x"35",x"40", -- 0x13D8 + x"C9",x"21",x"4C",x"48",x"22",x"92",x"42",x"22", -- 0x13E0 + x"96",x"42",x"21",x"5E",x"48",x"22",x"94",x"42", -- 0x13E8 + x"21",x"AC",x"4B",x"22",x"98",x"42",x"C9",x"CD", -- 0x13F0 + x"70",x"10",x"CD",x"E1",x"13",x"21",x"90",x"42", -- 0x13F8 + x"34",x"2C",x"36",x"32",x"21",x"9A",x"42",x"36", -- 0x1400 + x"07",x"2C",x"36",x"00",x"2C",x"36",x"00",x"C3", -- 0x1408 + x"C1",x"28",x"21",x"91",x"42",x"35",x"C0",x"36", -- 0x1410 + x"01",x"2D",x"34",x"21",x"39",x"40",x"D9",x"06", -- 0x1418 + x"00",x"3A",x"9C",x"42",x"4F",x"21",x"65",x"14", -- 0x1420 + x"09",x"7E",x"D9",x"06",x"19",x"77",x"2C",x"2C", -- 0x1428 + x"10",x"FB",x"3E",x"01",x"32",x"81",x"42",x"AF", -- 0x1430 + x"06",x"18",x"21",x"30",x"40",x"77",x"2C",x"2C", -- 0x1438 + x"10",x"FB",x"21",x"4C",x"48",x"0E",x"1C",x"06", -- 0x1440 + x"13",x"36",x"10",x"23",x"10",x"FB",x"11",x"0D", -- 0x1448 + x"00",x"19",x"0D",x"20",x"F2",x"11",x"00",x"06", -- 0x1450 + x"FF",x"3A",x"0D",x"40",x"1E",x"02",x"0F",x"D2", -- 0x1458 + x"38",x"00",x"1C",x"FF",x"C9",x"06",x"02",x"03", -- 0x1460 + x"07",x"00",x"21",x"91",x"42",x"35",x"C0",x"36", -- 0x1468 + x"03",x"06",x"13",x"3E",x"C8",x"2A",x"96",x"42", -- 0x1470 + x"ED",x"5B",x"98",x"42",x"77",x"12",x"13",x"23", -- 0x1478 + x"10",x"FA",x"06",x"28",x"2A",x"92",x"42",x"11", -- 0x1480 + x"20",x"00",x"77",x"19",x"10",x"FC",x"2A",x"94", -- 0x1488 + x"42",x"06",x"1C",x"77",x"19",x"10",x"FC",x"21", -- 0x1490 + x"92",x"42",x"34",x"2C",x"2C",x"35",x"2A",x"96", -- 0x1498 + x"42",x"19",x"22",x"96",x"42",x"2A",x"98",x"42", -- 0x14A0 + x"11",x"E0",x"FF",x"19",x"22",x"98",x"42",x"21", -- 0x14A8 + x"9A",x"42",x"35",x"C0",x"21",x"90",x"42",x"34", -- 0x14B0 + x"C9",x"CD",x"E1",x"13",x"21",x"90",x"42",x"36", -- 0x14B8 + x"01",x"2C",x"36",x"0A",x"21",x"9A",x"42",x"36", -- 0x14C0 + x"07",x"2C",x"2C",x"34",x"7E",x"FE",x"05",x"C0", -- 0x14C8 + x"3E",x"04",x"32",x"90",x"42",x"C9",x"3A",x"5F", -- 0x14D0 + x"42",x"E6",x"07",x"C0",x"3A",x"9B",x"42",x"2E", -- 0x14D8 + x"13",x"11",x"39",x"40",x"06",x"00",x"D6",x"01", -- 0x14E0 + x"30",x"02",x"3E",x"05",x"4F",x"E5",x"F5",x"21", -- 0x14E8 + x"FD",x"14",x"09",x"7E",x"12",x"1C",x"1C",x"F1", -- 0x14F0 + x"E1",x"2D",x"20",x"EA",x"C9",x"00",x"03",x"02", -- 0x14F8 + x"06",x"07",x"04",x"11",x"FD",x"FF",x"DD",x"21", -- 0x1500 + x"A4",x"40",x"3A",x"0D",x"40",x"0F",x"30",x"04", -- 0x1508 + x"DD",x"21",x"A7",x"40",x"FD",x"21",x"CE",x"43", -- 0x1510 + x"06",x"05",x"FD",x"7E",x"00",x"DD",x"BE",x"00", -- 0x1518 + x"20",x"0F",x"FD",x"7E",x"FF",x"DD",x"BE",x"FF", -- 0x1520 + x"20",x"07",x"FD",x"7E",x"FE",x"DD",x"BE",x"FE", -- 0x1528 + x"C8",x"30",x"04",x"FD",x"19",x"10",x"E3",x"3E", -- 0x1530 + x"05",x"90",x"C8",x"21",x"CE",x"43",x"11",x"D1", -- 0x1538 + x"43",x"47",x"87",x"80",x"06",x"00",x"4F",x"ED", -- 0x1540 + x"B8",x"2C",x"EB",x"DD",x"E5",x"E1",x"2D",x"2D", -- 0x1548 + x"01",x"03",x"00",x"ED",x"B0",x"C9",x"3A",x"1E", -- 0x1550 + x"41",x"0F",x"D8",x"21",x"A4",x"40",x"3A",x"0D", -- 0x1558 + x"40",x"0F",x"30",x"03",x"21",x"A7",x"40",x"3A", -- 0x1560 + x"17",x"40",x"47",x"7E",x"E6",x"0F",x"07",x"07", -- 0x1568 + x"07",x"07",x"4F",x"2D",x"7E",x"E6",x"F0",x"0F", -- 0x1570 + x"0F",x"0F",x"0F",x"B1",x"B8",x"D8",x"CD",x"47", -- 0x1578 + x"28",x"21",x"1D",x"41",x"34",x"11",x"03",x"07", -- 0x1580 + x"FF",x"2C",x"36",x"01",x"C9",x"3A",x"16",x"41", -- 0x1588 + x"A7",x"C0",x"21",x"1C",x"41",x"7E",x"0F",x"D2", -- 0x1590 + x"93",x"1A",x"11",x"88",x"06",x"FF",x"36",x"00", -- 0x1598 + x"C3",x"93",x"1A",x"21",x"00",x"42",x"CB",x"46", -- 0x15A0 + x"28",x"34",x"2C",x"2C",x"3A",x"0D",x"40",x"0F", -- 0x15A8 + x"38",x"3F",x"3A",x"10",x"40",x"47",x"CB",x"67", -- 0x15B0 + x"28",x"07",x"7E",x"FE",x"17",x"38",x"02",x"35", -- 0x15B8 + x"35",x"CB",x"68",x"28",x"07",x"7E",x"FE",x"E9", -- 0x15C0 + x"30",x"02",x"34",x"34",x"7E",x"2F",x"C6",x"80", -- 0x15C8 + x"0E",x"06",x"21",x"56",x"40",x"06",x"04",x"77", -- 0x15D0 + x"2C",x"71",x"2C",x"10",x"FA",x"C9",x"2C",x"CB", -- 0x15D8 + x"46",x"20",x"05",x"2C",x"36",x"00",x"18",x"E4", -- 0x15E0 + x"2C",x"7E",x"2F",x"C6",x"80",x"0E",x"07",x"18", -- 0x15E8 + x"E1",x"3A",x"11",x"40",x"47",x"18",x"BE",x"21", -- 0x15F0 + x"7C",x"42",x"CB",x"46",x"23",x"23",x"23",x"28", -- 0x15F8 + x"0C",x"7E",x"D6",x"05",x"77",x"FE",x"34",x"30", -- 0x1600 + x"16",x"AF",x"32",x"7C",x"42",x"36",x"DF",x"2D", -- 0x1608 + x"2D",x"3A",x"00",x"42",x"0F",x"30",x"06",x"3A", -- 0x1610 + x"02",x"42",x"77",x"18",x"02",x"36",x"00",x"DD", -- 0x1618 + x"21",x"9D",x"40",x"FD",x"21",x"7D",x"42",x"3A", -- 0x1620 + x"0F",x"40",x"0F",x"30",x"06",x"3A",x"0D",x"40", -- 0x1628 + x"0F",x"38",x"11",x"FD",x"7E",x"02",x"2F",x"C6", -- 0x1630 + x"FC",x"DD",x"77",x"02",x"FD",x"7E",x"00",x"2F", -- 0x1638 + x"DD",x"77",x"00",x"C9",x"FD",x"7E",x"02",x"3D", -- 0x1640 + x"DD",x"77",x"02",x"FD",x"7E",x"00",x"2F",x"DD", -- 0x1648 + x"77",x"00",x"C9",x"DD",x"21",x"A0",x"42",x"11", -- 0x1650 + x"20",x"00",x"06",x"08",x"D9",x"CD",x"D5",x"1A", -- 0x1658 + x"D9",x"DD",x"19",x"10",x"F7",x"C9",x"DD",x"21", -- 0x1660 + x"A0",x"42",x"FD",x"21",x"60",x"40",x"01",x"08", -- 0x1668 + x"08",x"DD",x"CB",x"00",x"46",x"28",x"27",x"DD", -- 0x1670 + x"7E",x"16",x"FD",x"77",x"02",x"DD",x"7E",x"03", -- 0x1678 + x"91",x"FD",x"77",x"03",x"DD",x"7E",x"04",x"2F", -- 0x1680 + x"91",x"FD",x"77",x"00",x"DD",x"7E",x"12",x"FD", -- 0x1688 + x"77",x"01",x"11",x"20",x"00",x"DD",x"19",x"1E", -- 0x1690 + x"04",x"FD",x"19",x"10",x"D4",x"C9",x"DD",x"CB", -- 0x1698 + x"01",x"46",x"28",x"06",x"FD",x"36",x"02",x"07", -- 0x16A0 + x"18",x"CD",x"FD",x"36",x"03",x"F8",x"FD",x"36", -- 0x16A8 + x"00",x"F8",x"18",x"DE",x"3A",x"00",x"42",x"0F", -- 0x16B0 + x"D0",x"3A",x"7C",x"42",x"0F",x"D8",x"3A",x"0D", -- 0x16B8 + x"40",x"0F",x"38",x"15",x"3A",x"13",x"40",x"2F", -- 0x16C0 + x"47",x"3A",x"10",x"40",x"A0",x"E6",x"08",x"C8", -- 0x16C8 + x"3E",x"01",x"32",x"7C",x"42",x"CD",x"32",x"28", -- 0x16D0 + x"C9",x"3A",x"14",x"40",x"2F",x"47",x"3A",x"11", -- 0x16D8 + x"40",x"18",x"E9",x"CD",x"59",x"17",x"CD",x"AC", -- 0x16E0 + x"17",x"CD",x"CB",x"17",x"CD",x"0E",x"18",x"C3", -- 0x16E8 + x"F2",x"16",x"06",x"08",x"21",x"60",x"42",x"CB", -- 0x16F0 + x"46",x"20",x"07",x"2C",x"2C",x"2C",x"2C",x"10", -- 0x16F8 + x"F6",x"C9",x"2C",x"2C",x"2C",x"7E",x"C6",x"38", -- 0x1700 + x"D6",x"10",x"30",x"F2",x"2D",x"2D",x"7E",x"C6", -- 0x1708 + x"E0",x"D6",x"20",x"30",x"05",x"11",x"20",x"41", -- 0x1710 + x"18",x"14",x"D6",x"30",x"D6",x"20",x"30",x"05", -- 0x1718 + x"11",x"30",x"41",x"18",x"09",x"D6",x"30",x"D6", -- 0x1720 + x"20",x"30",x"D1",x"11",x"40",x"41",x"C6",x"20", -- 0x1728 + x"E6",x"F8",x"1F",x"83",x"5F",x"2C",x"2C",x"7E", -- 0x1730 + x"D6",x"C8",x"E6",x"0C",x"1F",x"1F",x"83",x"5F", -- 0x1738 + x"1A",x"CB",x"4F",x"28",x"B9",x"4F",x"7D",x"FE", -- 0x1740 + x"7C",x"79",x"30",x"03",x"CB",x"D7",x"12",x"0E", -- 0x1748 + x"04",x"AF",x"77",x"2D",x"0D",x"20",x"FB",x"18", -- 0x1750 + x"A2",x"DD",x"21",x"60",x"42",x"11",x"04",x"00", -- 0x1758 + x"06",x"04",x"CD",x"6A",x"17",x"DD",x"19",x"10", -- 0x1760 + x"F9",x"C9",x"DD",x"CB",x"00",x"46",x"28",x"2B", -- 0x1768 + x"DD",x"CB",x"02",x"4E",x"28",x"18",x"DD",x"34", -- 0x1770 + x"01",x"DD",x"CB",x"02",x"46",x"28",x"0F",x"DD", -- 0x1778 + x"35",x"01",x"DD",x"35",x"01",x"DD",x"7E",x"01", -- 0x1780 + x"C6",x"10",x"D6",x"21",x"38",x"0D",x"DD",x"7E", -- 0x1788 + x"03",x"C6",x"02",x"DD",x"77",x"03",x"FE",x"F8", -- 0x1790 + x"30",x"01",x"C9",x"DD",x"36",x"00",x"00",x"DD", -- 0x1798 + x"36",x"01",x"00",x"DD",x"36",x"02",x"00",x"DD", -- 0x17A0 + x"36",x"03",x"00",x"C9",x"DD",x"21",x"68",x"42", -- 0x17A8 + x"DD",x"CB",x"00",x"46",x"28",x"E5",x"3A",x"10", -- 0x17B0 + x"41",x"FE",x"05",x"30",x"03",x"AF",x"18",x"02", -- 0x17B8 + x"3E",x"02",x"DD",x"86",x"03",x"DD",x"77",x"03", -- 0x17C0 + x"C3",x"96",x"17",x"DD",x"21",x"60",x"42",x"11", -- 0x17C8 + x"04",x"00",x"06",x"03",x"CD",x"DC",x"17",x"DD", -- 0x17D0 + x"19",x"10",x"F9",x"C9",x"DD",x"CB",x"00",x"46", -- 0x17D8 + x"C8",x"DD",x"7E",x"03",x"C6",x"1F",x"D6",x"05", -- 0x17E0 + x"38",x"17",x"D6",x"09",x"D0",x"3A",x"02",x"42", -- 0x17E8 + x"DD",x"96",x"01",x"C6",x"06",x"D6",x"0D",x"D0", -- 0x17F0 + x"CD",x"9B",x"17",x"3E",x"01",x"32",x"04",x"42", -- 0x17F8 + x"C9",x"3A",x"02",x"42",x"DD",x"96",x"01",x"C6", -- 0x1800 + x"02",x"D6",x"05",x"D0",x"18",x"EA",x"21",x"81", -- 0x1808 + x"40",x"11",x"61",x"42",x"06",x"03",x"1A",x"2F", -- 0x1810 + x"77",x"2C",x"2C",x"1C",x"1C",x"1A",x"77",x"3A", -- 0x1818 + x"0F",x"40",x"0F",x"30",x"06",x"3A",x"0D",x"40", -- 0x1820 + x"0F",x"38",x"03",x"7E",x"2F",x"77",x"2C",x"2C", -- 0x1828 + x"1C",x"1C",x"10",x"E2",x"C9",x"3A",x"7C",x"42", -- 0x1830 + x"0F",x"D0",x"DD",x"21",x"A0",x"42",x"11",x"20", -- 0x1838 + x"00",x"06",x"08",x"D9",x"CD",x"4D",x"18",x"D9", -- 0x1840 + x"DD",x"19",x"10",x"F7",x"C9",x"DD",x"CB",x"00", -- 0x1848 + x"46",x"C8",x"3A",x"7F",x"42",x"6F",x"3A",x"7D", -- 0x1850 + x"42",x"67",x"DD",x"7E",x"03",x"95",x"C6",x"02", -- 0x1858 + x"FE",x"06",x"D0",x"DD",x"7E",x"04",x"94",x"C6", -- 0x1860 + x"05",x"FE",x"0C",x"D0",x"DD",x"36",x"00",x"00", -- 0x1868 + x"DD",x"36",x"01",x"01",x"DD",x"36",x"02",x"00", -- 0x1870 + x"3A",x"06",x"40",x"0F",x"30",x"30",x"DD",x"CB", -- 0x1878 + x"19",x"46",x"28",x"05",x"CD",x"43",x"28",x"18", -- 0x1880 + x"03",x"CD",x"8A",x"28",x"16",x"03",x"DD",x"7E", -- 0x1888 + x"16",x"FE",x"07",x"28",x"06",x"FE",x"03",x"28", -- 0x1890 + x"06",x"18",x"08",x"1E",x"02",x"18",x"06",x"1E", -- 0x1898 + x"03",x"18",x"02",x"1E",x"05",x"DD",x"7E",x"19", -- 0x18A0 + x"0F",x"30",x"02",x"CB",x"23",x"FF",x"AF",x"32", -- 0x18A8 + x"7C",x"42",x"21",x"11",x"41",x"35",x"DD",x"7E", -- 0x18B0 + x"18",x"DD",x"36",x"18",x"00",x"3D",x"28",x"04", -- 0x18B8 + x"3D",x"28",x"0C",x"C9",x"DD",x"7E",x"17",x"C6", -- 0x18C0 + x"20",x"6F",x"26",x"41",x"CB",x"BE",x"C9",x"DD", -- 0x18C8 + x"7E",x"17",x"C6",x"50",x"18",x"F3",x"21",x"04", -- 0x18D0 + x"42",x"CB",x"46",x"28",x"16",x"36",x"00",x"21", -- 0x18D8 + x"00",x"01",x"22",x"00",x"42",x"21",x"0A",x"04", -- 0x18E0 + x"22",x"05",x"42",x"11",x"03",x"02",x"FF",x"CD", -- 0x18E8 + x"3F",x"28",x"C9",x"3A",x"01",x"42",x"0F",x"D0", -- 0x18F0 + x"21",x"05",x"42",x"35",x"C0",x"36",x"0A",x"23", -- 0x18F8 + x"16",x"02",x"5E",x"FF",x"35",x"C0",x"AF",x"32", -- 0x1900 + x"01",x"42",x"C9",x"3A",x"12",x"41",x"FE",x"2E", -- 0x1908 + x"C8",x"3A",x"00",x"42",x"0F",x"D0",x"3A",x"16", -- 0x1910 + x"41",x"A7",x"C8",x"3A",x"5F",x"42",x"E6",x"07", -- 0x1918 + x"C0",x"3A",x"5F",x"42",x"A7",x"20",x"0E",x"2A", -- 0x1920 + x"07",x"42",x"23",x"7E",x"3C",x"20",x"03",x"21", -- 0x1928 + x"53",x"19",x"22",x"07",x"42",x"2A",x"07",x"42", -- 0x1930 + x"46",x"21",x"A0",x"42",x"11",x"1F",x"00",x"7E", -- 0x1938 + x"23",x"B6",x"0F",x"30",x"04",x"19",x"10",x"F7", -- 0x1940 + x"C9",x"23",x"36",x"00",x"2B",x"36",x"00",x"2B", -- 0x1948 + x"36",x"01",x"C9",x"08",x"08",x"04",x"04",x"04", -- 0x1950 + x"05",x"05",x"05",x"06",x"06",x"06",x"07",x"07", -- 0x1958 + x"07",x"08",x"08",x"08",x"08",x"08",x"08",x"04", -- 0x1960 + x"04",x"04",x"04",x"FF",x"3A",x"10",x"41",x"FE", -- 0x1968 + x"04",x"D8",x"3A",x"00",x"42",x"0F",x"D0",x"21", -- 0x1970 + x"B8",x"42",x"11",x"20",x"00",x"06",x"08",x"CB", -- 0x1978 + x"46",x"20",x"04",x"19",x"10",x"F9",x"C9",x"7D", -- 0x1980 + x"D6",x"15",x"6F",x"3A",x"60",x"42",x"0F",x"D8", -- 0x1988 + x"7E",x"2C",x"46",x"FE",x"C8",x"D0",x"FE",x"60", -- 0x1990 + x"D8",x"21",x"60",x"42",x"36",x"01",x"2C",x"70", -- 0x1998 + x"2C",x"2C",x"77",x"C9",x"3A",x"00",x"42",x"0F", -- 0x19A0 + x"D0",x"3A",x"02",x"42",x"4F",x"26",x"FF",x"2E", -- 0x19A8 + x"00",x"DD",x"21",x"A0",x"42",x"11",x"20",x"00", -- 0x19B0 + x"06",x"08",x"DD",x"CB",x"00",x"46",x"28",x"12", -- 0x19B8 + x"DD",x"7E",x"04",x"B9",x"30",x"06",x"79",x"DD", -- 0x19C0 + x"96",x"04",x"18",x"01",x"91",x"BC",x"30",x"02", -- 0x19C8 + x"67",x"68",x"DD",x"19",x"10",x"E4",x"7D",x"A7", -- 0x19D0 + x"C8",x"3E",x"08",x"95",x"21",x"A0",x"42",x"A7", -- 0x19D8 + x"28",x"04",x"3D",x"19",x"18",x"F9",x"2C",x"2C", -- 0x19E0 + x"2C",x"DD",x"21",x"64",x"42",x"DD",x"CB",x"00", -- 0x19E8 + x"46",x"C0",x"7E",x"FE",x"60",x"D8",x"47",x"3A", -- 0x19F0 + x"10",x"41",x"0E",x"A8",x"A7",x"28",x"07",x"0E", -- 0x19F8 + x"B8",x"3D",x"28",x"02",x"0E",x"C8",x"78",x"B9", -- 0x1A00 + x"D0",x"DD",x"36",x"00",x"01",x"7E",x"DD",x"77", -- 0x1A08 + x"03",x"2C",x"7E",x"DD",x"77",x"01",x"C9",x"3A", -- 0x1A10 + x"00",x"42",x"0F",x"D0",x"3A",x"00",x"41",x"0F", -- 0x1A18 + x"D0",x"3A",x"10",x"41",x"FE",x"02",x"D8",x"21", -- 0x1A20 + x"68",x"42",x"CB",x"46",x"C0",x"34",x"2C",x"3A", -- 0x1A28 + x"01",x"41",x"77",x"2C",x"2C",x"36",x"38",x"C9", -- 0x1A30 + x"21",x"DF",x"41",x"1E",x"06",x"0E",x"06",x"06", -- 0x1A38 + x"18",x"CB",x"4E",x"20",x"0C",x"7D",x"93",x"6F", -- 0x1A40 + x"10",x"F7",x"7D",x"C6",x"8F",x"6F",x"0D",x"20", -- 0x1A48 + x"EE",x"3E",x"40",x"41",x"0E",x"04",x"04",x"81", -- 0x1A50 + x"10",x"FD",x"32",x"1B",x"41",x"C9",x"3A",x"00", -- 0x1A58 + x"41",x"A7",x"C8",x"3A",x"5F",x"42",x"E6",x"01", -- 0x1A60 + x"C8",x"21",x"02",x"41",x"7E",x"2D",x"0F",x"38", -- 0x1A68 + x"12",x"7E",x"FE",x"27",x"38",x"15",x"3D",x"77", -- 0x1A70 + x"2F",x"C6",x"80",x"21",x"2A",x"40",x"77",x"2C", -- 0x1A78 + x"2C",x"77",x"C9",x"7E",x"FE",x"D9",x"30",x"07", -- 0x1A80 + x"3C",x"18",x"EC",x"2C",x"36",x"01",x"C9",x"2C", -- 0x1A88 + x"36",x"00",x"C9",x"3A",x"52",x"40",x"A7",x"20", -- 0x1A90 + x"0E",x"3E",x"30",x"32",x"52",x"40",x"32",x"54", -- 0x1A98 + x"40",x"21",x"20",x"41",x"C3",x"CC",x"1A",x"21", -- 0x1AA0 + x"52",x"40",x"34",x"23",x"23",x"34",x"7E",x"FE", -- 0x1AA8 + x"80",x"21",x"30",x"41",x"CA",x"CC",x"1A",x"FE", -- 0x1AB0 + x"D0",x"21",x"40",x"41",x"CA",x"CC",x"1A",x"A7", -- 0x1AB8 + x"C0",x"3E",x"10",x"21",x"13",x"41",x"06",x"03", -- 0x1AC0 + x"D7",x"36",x"30",x"C9",x"06",x"10",x"3E",x"02", -- 0x1AC8 + x"77",x"23",x"10",x"FC",x"C9",x"DD",x"CB",x"01", -- 0x1AD0 + x"46",x"C2",x"19",x"1B",x"DD",x"CB",x"00",x"46", -- 0x1AD8 + x"C8",x"DD",x"7E",x"02",x"EF",x"56",x"1D",x"0F", -- 0x1AE0 + x"1F",x"3E",x"1F",x"50",x"1F",x"5A",x"1F",x"87", -- 0x1AE8 + x"1F",x"AB",x"1F",x"B5",x"1F",x"C4",x"1F",x"42", -- 0x1AF0 + x"21",x"4C",x"21",x"5A",x"21",x"64",x"21",x"91", -- 0x1AF8 + x"21",x"9B",x"21",x"A5",x"21",x"AF",x"21",x"BC", -- 0x1B00 + x"21",x"BF",x"21",x"C9",x"21",x"D8",x"21",x"89", -- 0x1B08 + x"23",x"93",x"23",x"A1",x"23",x"AB",x"23",x"D8", -- 0x1B10 + x"23",x"DD",x"7E",x"02",x"EF",x"21",x"1B",x"31", -- 0x1B18 + x"1B",x"DD",x"36",x"10",x"04",x"DD",x"36",x"11", -- 0x1B20 + x"04",x"DD",x"36",x"12",x"1C",x"DD",x"34",x"02", -- 0x1B28 + x"C9",x"DD",x"35",x"10",x"C0",x"DD",x"36",x"10", -- 0x1B30 + x"04",x"DD",x"34",x"12",x"DD",x"35",x"11",x"C0", -- 0x1B38 + x"DD",x"36",x"01",x"00",x"C9",x"DD",x"7E",x"04", -- 0x1B40 + x"DD",x"BE",x"06",x"28",x"4A",x"DD",x"7E",x"03", -- 0x1B48 + x"DD",x"BE",x"05",x"28",x"58",x"DD",x"CB",x"09", -- 0x1B50 + x"46",x"28",x"1E",x"DD",x"7E",x"07",x"DD",x"86", -- 0x1B58 + x"03",x"DD",x"77",x"03",x"DD",x"7E",x"0B",x"DD", -- 0x1B60 + x"86",x"0A",x"DD",x"77",x"0A",x"D0",x"DD",x"7E", -- 0x1B68 + x"08",x"DD",x"86",x"04",x"DD",x"77",x"04",x"A7", -- 0x1B70 + x"C9",x"DD",x"7E",x"08",x"DD",x"86",x"04",x"DD", -- 0x1B78 + x"77",x"04",x"DD",x"7E",x"0B",x"DD",x"86",x"0A", -- 0x1B80 + x"DD",x"77",x"0A",x"D0",x"DD",x"7E",x"07",x"DD", -- 0x1B88 + x"86",x"03",x"DD",x"77",x"03",x"A7",x"C9",x"DD", -- 0x1B90 + x"7E",x"03",x"DD",x"BE",x"05",x"28",x"0C",x"30", -- 0x1B98 + x"05",x"DD",x"34",x"03",x"A7",x"C9",x"DD",x"35", -- 0x1BA0 + x"03",x"A7",x"C9",x"37",x"C9",x"DD",x"7E",x"04", -- 0x1BA8 + x"DD",x"BE",x"06",x"30",x"05",x"DD",x"34",x"04", -- 0x1BB0 + x"A7",x"C9",x"DD",x"35",x"04",x"A7",x"C9",x"DD", -- 0x1BB8 + x"35",x"0E",x"C0",x"DD",x"6E",x"0C",x"DD",x"66", -- 0x1BC0 + x"0D",x"7E",x"FE",x"FF",x"20",x"06",x"23",x"5E", -- 0x1BC8 + x"23",x"56",x"EB",x"7E",x"DD",x"77",x"12",x"23", -- 0x1BD0 + x"7E",x"DD",x"77",x"0E",x"23",x"DD",x"75",x"0C", -- 0x1BD8 + x"DD",x"74",x"0D",x"C9",x"8E",x"0A",x"8F",x"0A", -- 0x1BE0 + x"90",x"0A",x"91",x"0A",x"92",x"0A",x"F1",x"05", -- 0x1BE8 + x"F0",x"05",x"EF",x"05",x"EE",x"05",x"ED",x"05", -- 0x1BF0 + x"FF",x"12",x"1C",x"0E",x"0A",x"0F",x"0A",x"10", -- 0x1BF8 + x"0A",x"11",x"0A",x"12",x"0A",x"71",x"05",x"70", -- 0x1C00 + x"05",x"6F",x"05",x"6E",x"05",x"6D",x"05",x"FF", -- 0x1C08 + x"12",x"1C",x"E9",x"05",x"EA",x"05",x"EB",x"05", -- 0x1C10 + x"EC",x"05",x"FF",x"12",x"1C",x"6E",x"05",x"6F", -- 0x1C18 + x"05",x"6E",x"05",x"6D",x"05",x"E9",x"05",x"EA", -- 0x1C20 + x"05",x"EB",x"05",x"EC",x"05",x"ED",x"05",x"EE", -- 0x1C28 + x"05",x"EF",x"05",x"EE",x"05",x"ED",x"05",x"FF", -- 0x1C30 + x"12",x"1C",x"E4",x"03",x"E5",x"03",x"E6",x"03", -- 0x1C38 + x"E7",x"03",x"E8",x"03",x"A7",x"03",x"A6",x"03", -- 0x1C40 + x"A5",x"03",x"A4",x"03",x"FF",x"4F",x"1C",x"20", -- 0x1C48 + x"05",x"21",x"05",x"22",x"05",x"23",x"05",x"FF", -- 0x1C50 + x"4F",x"1C",x"25",x"05",x"26",x"05",x"25",x"05", -- 0x1C58 + x"24",x"05",x"20",x"05",x"21",x"05",x"22",x"05", -- 0x1C60 + x"23",x"05",x"A4",x"05",x"A5",x"05",x"A6",x"05", -- 0x1C68 + x"A5",x"05",x"A4",x"05",x"FF",x"4F",x"1C",x"2D", -- 0x1C70 + x"03",x"2E",x"03",x"2F",x"03",x"30",x"03",x"31", -- 0x1C78 + x"03",x"70",x"03",x"6F",x"03",x"6E",x"03",x"6D", -- 0x1C80 + x"03",x"FF",x"12",x"1C",x"DD",x"E5",x"E1",x"3E", -- 0x1C88 + x"07",x"85",x"6F",x"DD",x"36",x"0A",x"00",x"DD", -- 0x1C90 + x"7E",x"05",x"DD",x"BE",x"03",x"28",x"04",x"38", -- 0x1C98 + x"1E",x"18",x"56",x"DD",x"7E",x"06",x"DD",x"BE", -- 0x1CA0 + x"04",x"28",x"0E",x"38",x"06",x"36",x"00",x"2C", -- 0x1CA8 + x"36",x"01",x"C9",x"36",x"00",x"2C",x"36",x"FF", -- 0x1CB0 + x"C9",x"36",x"00",x"2C",x"36",x"00",x"C9",x"DD", -- 0x1CB8 + x"7E",x"06",x"DD",x"BE",x"04",x"28",x"2C",x"38", -- 0x1CC0 + x"15",x"36",x"FF",x"2C",x"36",x"01",x"DD",x"7E", -- 0x1CC8 + x"03",x"DD",x"96",x"05",x"47",x"DD",x"7E",x"06", -- 0x1CD0 + x"DD",x"96",x"04",x"4F",x"18",x"55",x"36",x"FF", -- 0x1CD8 + x"2C",x"36",x"FF",x"DD",x"7E",x"03",x"DD",x"96", -- 0x1CE0 + x"05",x"47",x"DD",x"7E",x"04",x"DD",x"96",x"06", -- 0x1CE8 + x"4F",x"18",x"40",x"36",x"FF",x"2C",x"36",x"00", -- 0x1CF0 + x"C9",x"DD",x"7E",x"06",x"DD",x"BE",x"04",x"28", -- 0x1CF8 + x"2C",x"38",x"15",x"36",x"01",x"2C",x"36",x"01", -- 0x1D00 + x"DD",x"7E",x"05",x"DD",x"96",x"03",x"47",x"DD", -- 0x1D08 + x"7E",x"06",x"DD",x"96",x"04",x"4F",x"18",x"1B", -- 0x1D10 + x"36",x"01",x"2C",x"36",x"FF",x"DD",x"7E",x"05", -- 0x1D18 + x"DD",x"96",x"03",x"47",x"DD",x"7E",x"04",x"DD", -- 0x1D20 + x"96",x"06",x"4F",x"18",x"06",x"36",x"01",x"2C", -- 0x1D28 + x"36",x"00",x"C9",x"79",x"B8",x"28",x"16",x"38", -- 0x1D30 + x"0B",x"DD",x"36",x"09",x"00",x"CD",x"E4",x"23", -- 0x1D38 + x"DD",x"77",x"0B",x"C9",x"DD",x"36",x"09",x"01", -- 0x1D40 + x"78",x"41",x"4F",x"18",x"F0",x"DD",x"36",x"09", -- 0x1D48 + x"01",x"DD",x"36",x"0B",x"FF",x"C9",x"DD",x"36", -- 0x1D50 + x"18",x"00",x"DD",x"36",x"19",x"00",x"21",x"A7", -- 0x1D58 + x"1E",x"DD",x"75",x"13",x"DD",x"74",x"14",x"DD", -- 0x1D60 + x"36",x"10",x"30",x"DD",x"36",x"0E",x"01",x"21", -- 0x1D68 + x"12",x"41",x"7E",x"34",x"47",x"87",x"87",x"80", -- 0x1D70 + x"5F",x"16",x"00",x"21",x"C1",x"1D",x"19",x"3E", -- 0x1D78 + x"30",x"86",x"DD",x"77",x"03",x"23",x"3A",x"01", -- 0x1D80 + x"41",x"86",x"DD",x"77",x"04",x"23",x"5E",x"23", -- 0x1D88 + x"46",x"23",x"7E",x"DD",x"77",x"16",x"21",x"04", -- 0x1D90 + x"41",x"19",x"70",x"DD",x"36",x"12",x"0B",x"3A", -- 0x1D98 + x"01",x"41",x"FE",x"80",x"30",x"11",x"DD",x"36", -- 0x1DA0 + x"15",x"00",x"21",x"E4",x"1B",x"DD",x"75",x"0C", -- 0x1DA8 + x"DD",x"74",x"0D",x"DD",x"34",x"02",x"C9",x"DD", -- 0x1DB0 + x"36",x"15",x"01",x"21",x"FB",x"1B",x"C3",x"AD", -- 0x1DB8 + x"1D",x"F1",x"EF",x"00",x"66",x"07",x"F1",x"12", -- 0x1DC0 + x"05",x"66",x"07",x"F3",x"EB",x"00",x"6D",x"07", -- 0x1DC8 + x"F3",x"16",x"05",x"67",x"07",x"F3",x"EE",x"00", -- 0x1DD0 + x"68",x"07",x"F3",x"13",x"05",x"68",x"07",x"F5", -- 0x1DD8 + x"EA",x"00",x"6E",x"07",x"F5",x"17",x"05",x"69", -- 0x1DE0 + x"07",x"F5",x"EF",x"00",x"6A",x"03",x"F5",x"12", -- 0x1DE8 + x"05",x"6A",x"03",x"F7",x"EB",x"00",x"6F",x"01", -- 0x1DF0 + x"F7",x"16",x"05",x"6B",x"01",x"F7",x"EE",x"00", -- 0x1DF8 + x"10",x"07",x"F7",x"13",x"05",x"10",x"03",x"F1", -- 0x1E00 + x"F2",x"01",x"6C",x"01",x"F1",x"0F",x"04",x"65", -- 0x1E08 + x"07",x"F1",x"F7",x"01",x"66",x"03",x"F1",x"0A", -- 0x1E10 + x"04",x"66",x"01",x"F3",x"F3",x"01",x"6D",x"07", -- 0x1E18 + x"F3",x"0E",x"04",x"67",x"03",x"F3",x"F6",x"01", -- 0x1E20 + x"68",x"01",x"F3",x"0B",x"04",x"68",x"07",x"F5", -- 0x1E28 + x"F2",x"01",x"6E",x"03",x"F5",x"0F",x"04",x"69", -- 0x1E30 + x"01",x"F5",x"F7",x"01",x"6A",x"07",x"F5",x"0A", -- 0x1E38 + x"04",x"6A",x"03",x"F7",x"F3",x"01",x"6F",x"03", -- 0x1E40 + x"F7",x"0E",x"04",x"6B",x"07",x"F7",x"F6",x"01", -- 0x1E48 + x"10",x"03",x"F7",x"0B",x"04",x"10",x"03",x"F1", -- 0x1E50 + x"FA",x"02",x"6C",x"07",x"F1",x"07",x"03",x"65", -- 0x1E58 + x"03",x"F1",x"FF",x"02",x"66",x"01",x"F1",x"02", -- 0x1E60 + x"03",x"66",x"07",x"F3",x"FB",x"02",x"6D",x"03", -- 0x1E68 + x"F3",x"06",x"03",x"67",x"01",x"F3",x"FE",x"02", -- 0x1E70 + x"68",x"07",x"F3",x"03",x"03",x"68",x"03",x"F5", -- 0x1E78 + x"FA",x"02",x"6E",x"03",x"F5",x"07",x"03",x"69", -- 0x1E80 + x"07",x"F5",x"FF",x"02",x"6A",x"03",x"F5",x"02", -- 0x1E88 + x"03",x"6A",x"03",x"F7",x"FB",x"02",x"6F",x"07", -- 0x1E90 + x"F7",x"06",x"03",x"6B",x"03",x"F7",x"FE",x"02", -- 0x1E98 + x"10",x"03",x"F7",x"03",x"03",x"10",x"07",x"FF", -- 0x1EA0 + x"00",x"FF",x"00",x"FF",x"00",x"FF",x"01",x"FF", -- 0x1EA8 + x"00",x"FF",x"00",x"FF",x"01",x"FF",x"00",x"FF", -- 0x1EB0 + x"01",x"FF",x"00",x"00",x"01",x"FF",x"00",x"FF", -- 0x1EB8 + x"01",x"00",x"01",x"FF",x"00",x"00",x"01",x"FF", -- 0x1EC0 + x"01",x"00",x"01",x"FF",x"01",x"00",x"01",x"00", -- 0x1EC8 + x"01",x"FF",x"01",x"00",x"01",x"00",x"01",x"00", -- 0x1ED0 + x"01",x"00",x"01",x"00",x"01",x"00",x"01",x"01", -- 0x1ED8 + x"01",x"00",x"01",x"00",x"01",x"01",x"01",x"00", -- 0x1EE0 + x"01",x"01",x"01",x"00",x"01",x"01",x"00",x"00", -- 0x1EE8 + x"01",x"01",x"01",x"01",x"00",x"00",x"01",x"01", -- 0x1EF0 + x"00",x"01",x"01",x"01",x"00",x"01",x"01",x"01", -- 0x1EF8 + x"00",x"01",x"00",x"01",x"01",x"01",x"00",x"01", -- 0x1F00 + x"00",x"01",x"00",x"01",x"00",x"01",x"00",x"DD", -- 0x1F08 + x"35",x"10",x"28",x"27",x"DD",x"6E",x"13",x"DD", -- 0x1F10 + x"66",x"14",x"DD",x"7E",x"03",x"86",x"DD",x"77", -- 0x1F18 + x"03",x"23",x"7E",x"23",x"DD",x"75",x"13",x"DD", -- 0x1F20 + x"74",x"14",x"DD",x"CB",x"15",x"46",x"28",x"02", -- 0x1F28 + x"ED",x"44",x"DD",x"86",x"04",x"DD",x"77",x"04", -- 0x1F30 + x"C3",x"BF",x"1B",x"DD",x"34",x"02",x"3A",x"1B", -- 0x1F38 + x"41",x"DD",x"77",x"05",x"DD",x"7E",x"04",x"DD", -- 0x1F40 + x"77",x"06",x"CD",x"8C",x"1C",x"DD",x"34",x"02", -- 0x1F48 + x"CD",x"BF",x"1B",x"CD",x"45",x"1B",x"D0",x"DD", -- 0x1F50 + x"34",x"02",x"3A",x"1C",x"41",x"0F",x"3E",x"01", -- 0x1F58 + x"30",x"1F",x"3E",x"03",x"18",x"1B",x"3A",x"04", -- 0x1F60 + x"40",x"47",x"3A",x"10",x"41",x"A7",x"28",x"07", -- 0x1F68 + x"3D",x"28",x"0A",x"3E",x"01",x"18",x"0A",x"3E", -- 0x1F70 + x"03",x"A0",x"3C",x"18",x"04",x"3E",x"01",x"A0", -- 0x1F78 + x"3C",x"DD",x"77",x"10",x"DD",x"34",x"02",x"3A", -- 0x1F80 + x"04",x"40",x"47",x"E6",x"70",x"FE",x"60",x"38", -- 0x1F88 + x"02",x"D6",x"20",x"C6",x"58",x"DD",x"77",x"05", -- 0x1F90 + x"78",x"FE",x"D0",x"38",x"02",x"D6",x"80",x"C6", -- 0x1F98 + x"18",x"DD",x"77",x"06",x"CD",x"8C",x"1C",x"DD", -- 0x1FA0 + x"34",x"02",x"C9",x"CD",x"BF",x"1B",x"CD",x"45", -- 0x1FA8 + x"1B",x"D0",x"DD",x"34",x"02",x"DD",x"35",x"10", -- 0x1FB0 + x"28",x"07",x"DD",x"35",x"02",x"DD",x"35",x"02", -- 0x1FB8 + x"C9",x"DD",x"34",x"02",x"DD",x"36",x"02",x"04", -- 0x1FC0 + x"3A",x"00",x"42",x"0F",x"D0",x"3A",x"16",x"41", -- 0x1FC8 + x"A7",x"C8",x"ED",x"5F",x"E6",x"03",x"28",x"13", -- 0x1FD0 + x"3D",x"28",x"44",x"3D",x"28",x"72",x"3A",x"02", -- 0x1FD8 + x"42",x"FE",x"58",x"38",x"6B",x"FE",x"A8",x"38", -- 0x1FE0 + x"02",x"18",x"34",x"21",x"20",x"41",x"CD",x"AA", -- 0x1FE8 + x"20",x"DA",x"81",x"20",x"21",x"2C",x"41",x"CD", -- 0x1FF0 + x"C6",x"20",x"DA",x"81",x"20",x"21",x"30",x"41", -- 0x1FF8 + x"CD",x"AA",x"20",x"DA",x"81",x"20",x"21",x"3C", -- 0x2000 + x"41",x"CD",x"C6",x"20",x"38",x"73",x"21",x"40", -- 0x2008 + x"41",x"CD",x"AA",x"20",x"38",x"6B",x"21",x"4C", -- 0x2010 + x"41",x"CD",x"C6",x"20",x"38",x"63",x"C9",x"21", -- 0x2018 + x"3C",x"41",x"CD",x"C6",x"20",x"38",x"5A",x"21", -- 0x2020 + x"30",x"41",x"CD",x"AA",x"20",x"38",x"52",x"21", -- 0x2028 + x"4C",x"41",x"CD",x"C6",x"20",x"38",x"4A",x"21", -- 0x2030 + x"40",x"41",x"CD",x"AA",x"20",x"38",x"42",x"21", -- 0x2038 + x"20",x"41",x"CD",x"AA",x"20",x"38",x"3A",x"21", -- 0x2040 + x"2C",x"41",x"CD",x"C6",x"20",x"38",x"32",x"C9", -- 0x2048 + x"21",x"40",x"41",x"CD",x"AA",x"20",x"38",x"29", -- 0x2050 + x"21",x"4C",x"41",x"CD",x"C6",x"20",x"38",x"21", -- 0x2058 + x"21",x"20",x"41",x"CD",x"AA",x"20",x"38",x"19", -- 0x2060 + x"21",x"2C",x"41",x"CD",x"C6",x"20",x"38",x"11", -- 0x2068 + x"21",x"30",x"41",x"CD",x"AA",x"20",x"38",x"09", -- 0x2070 + x"21",x"3C",x"41",x"CD",x"C6",x"20",x"38",x"01", -- 0x2078 + x"C9",x"CB",x"FE",x"7D",x"D6",x"20",x"DD",x"77", -- 0x2080 + x"17",x"DD",x"36",x"18",x"01",x"87",x"5F",x"16", -- 0x2088 + x"00",x"21",x"E2",x"20",x"19",x"7E",x"D6",x"10", -- 0x2090 + x"DD",x"77",x"05",x"23",x"7E",x"DD",x"77",x"06", -- 0x2098 + x"CD",x"8C",x"1C",x"DD",x"36",x"02",x"09",x"C3", -- 0x20A0 + x"42",x"21",x"11",x"0F",x"04",x"4A",x"42",x"CB", -- 0x20A8 + x"4E",x"20",x"0D",x"7D",x"82",x"6F",x"10",x"F7", -- 0x20B0 + x"7D",x"93",x"6F",x"0D",x"20",x"F0",x"A7",x"C9", -- 0x20B8 + x"A7",x"CB",x"7E",x"C0",x"37",x"C9",x"11",x"11", -- 0x20C0 + x"04",x"4A",x"42",x"CB",x"4E",x"20",x"0D",x"7D", -- 0x20C8 + x"92",x"6F",x"10",x"F7",x"7D",x"83",x"6F",x"0D", -- 0x20D0 + x"20",x"F0",x"A7",x"C9",x"A7",x"CB",x"7E",x"C0", -- 0x20D8 + x"37",x"C9",x"C8",x"24",x"CC",x"24",x"D0",x"24", -- 0x20E0 + x"D4",x"24",x"C8",x"2C",x"CC",x"2C",x"D0",x"2C", -- 0x20E8 + x"D4",x"2C",x"C8",x"34",x"CC",x"34",x"D0",x"34", -- 0x20F0 + x"D4",x"34",x"C8",x"3C",x"CC",x"3C",x"D0",x"3C", -- 0x20F8 + x"D4",x"3C",x"C8",x"74",x"CC",x"74",x"D0",x"74", -- 0x2100 + x"D4",x"74",x"C8",x"7C",x"CC",x"7C",x"D0",x"7C", -- 0x2108 + x"D4",x"7C",x"C8",x"84",x"CC",x"84",x"D0",x"84", -- 0x2110 + x"D4",x"84",x"C8",x"8C",x"CC",x"8C",x"D0",x"8C", -- 0x2118 + x"D4",x"8C",x"C8",x"C4",x"CC",x"C4",x"D0",x"C4", -- 0x2120 + x"D4",x"C4",x"C8",x"CC",x"CC",x"CC",x"D0",x"CC", -- 0x2128 + x"D4",x"CC",x"C8",x"D4",x"CC",x"D4",x"D0",x"D4", -- 0x2130 + x"D4",x"D4",x"C8",x"DC",x"CC",x"DC",x"D0",x"DC", -- 0x2138 + x"D4",x"DC",x"CD",x"BF",x"1B",x"CD",x"45",x"1B", -- 0x2140 + x"D0",x"DD",x"34",x"02",x"DD",x"7E",x"05",x"C6", -- 0x2148 + x"10",x"DD",x"77",x"05",x"CD",x"8C",x"1C",x"DD", -- 0x2150 + x"34",x"02",x"CD",x"BF",x"1B",x"CD",x"45",x"1B", -- 0x2158 + x"D0",x"DD",x"34",x"02",x"CD",x"9E",x"28",x"21", -- 0x2160 + x"3A",x"1C",x"DD",x"75",x"0C",x"DD",x"74",x"0D", -- 0x2168 + x"DD",x"36",x"0E",x"01",x"DD",x"36",x"10",x"0F", -- 0x2170 + x"DD",x"36",x"18",x"00",x"DD",x"36",x"19",x"01", -- 0x2178 + x"DD",x"7E",x"17",x"C6",x"20",x"6F",x"26",x"41", -- 0x2180 + x"36",x"00",x"21",x"16",x"41",x"35",x"DD",x"34", -- 0x2188 + x"02",x"CD",x"BF",x"1B",x"DD",x"35",x"10",x"C0", -- 0x2190 + x"DD",x"34",x"02",x"DD",x"36",x"05",x"B8",x"CD", -- 0x2198 + x"8C",x"1C",x"DD",x"34",x"02",x"CD",x"BF",x"1B", -- 0x21A0 + x"CD",x"45",x"1B",x"D0",x"DD",x"34",x"02",x"3A", -- 0x21A8 + x"04",x"40",x"E6",x"03",x"3E",x"01",x"DD",x"77", -- 0x21B0 + x"10",x"DD",x"34",x"02",x"CD",x"87",x"1F",x"CD", -- 0x21B8 + x"BF",x"1B",x"CD",x"45",x"1B",x"D0",x"DD",x"34", -- 0x21C0 + x"02",x"DD",x"35",x"10",x"28",x"07",x"DD",x"35", -- 0x21C8 + x"02",x"DD",x"35",x"02",x"C9",x"DD",x"34",x"02", -- 0x21D0 + x"3A",x"04",x"40",x"E6",x"03",x"21",x"50",x"41", -- 0x21D8 + x"3D",x"28",x"09",x"21",x"80",x"41",x"3D",x"28", -- 0x21E0 + x"03",x"21",x"B0",x"41",x"CD",x"14",x"22",x"DD", -- 0x21E8 + x"36",x"02",x"10",x"D0",x"DD",x"6E",x"17",x"26", -- 0x21F0 + x"00",x"29",x"EB",x"21",x"69",x"22",x"19",x"7E", -- 0x21F8 + x"C6",x"10",x"DD",x"77",x"05",x"23",x"7E",x"DD", -- 0x2200 + x"77",x"06",x"CD",x"8C",x"1C",x"DD",x"36",x"02", -- 0x2208 + x"15",x"C3",x"89",x"23",x"08",x"3E",x"01",x"08", -- 0x2210 + x"16",x"06",x"ED",x"5F",x"E6",x"07",x"4F",x"87", -- 0x2218 + x"47",x"87",x"80",x"85",x"6F",x"1E",x"08",x"7B", -- 0x2220 + x"91",x"47",x"7E",x"CB",x"46",x"20",x"24",x"7D", -- 0x2228 + x"C6",x"06",x"6F",x"1D",x"10",x"F4",x"7B",x"A7", -- 0x2230 + x"28",x"0A",x"7D",x"D6",x"30",x"6F",x"43",x"08", -- 0x2238 + x"AF",x"08",x"18",x"E6",x"08",x"A7",x"28",x"04", -- 0x2240 + x"7D",x"D6",x"30",x"6F",x"08",x"2C",x"15",x"20", -- 0x2248 + x"D4",x"A7",x"C9",x"CB",x"4E",x"20",x"D8",x"A7", -- 0x2250 + x"CB",x"7E",x"C0",x"CB",x"FE",x"7D",x"D6",x"50", -- 0x2258 + x"DD",x"77",x"17",x"DD",x"36",x"18",x"02",x"37", -- 0x2260 + x"C9",x"44",x"1C",x"48",x"1C",x"4C",x"1C",x"50", -- 0x2268 + x"1C",x"54",x"1C",x"58",x"1C",x"44",x"24",x"48", -- 0x2270 + x"24",x"4C",x"24",x"50",x"24",x"54",x"24",x"58", -- 0x2278 + x"24",x"44",x"2C",x"48",x"2C",x"4C",x"2C",x"50", -- 0x2280 + x"2C",x"54",x"2C",x"58",x"2C",x"44",x"34",x"48", -- 0x2288 + x"34",x"4C",x"34",x"50",x"34",x"54",x"34",x"58", -- 0x2290 + x"34",x"44",x"3C",x"48",x"3C",x"4C",x"3C",x"50", -- 0x2298 + x"3C",x"54",x"3C",x"58",x"3C",x"44",x"44",x"48", -- 0x22A0 + x"44",x"4C",x"44",x"50",x"44",x"54",x"44",x"58", -- 0x22A8 + x"44",x"44",x"4C",x"48",x"4C",x"4C",x"4C",x"50", -- 0x22B0 + x"4C",x"54",x"4C",x"58",x"4C",x"44",x"54",x"48", -- 0x22B8 + x"54",x"4C",x"54",x"50",x"54",x"54",x"54",x"58", -- 0x22C0 + x"54",x"44",x"64",x"48",x"64",x"4C",x"64",x"50", -- 0x22C8 + x"64",x"54",x"64",x"58",x"64",x"44",x"6C",x"48", -- 0x22D0 + x"6C",x"4C",x"6C",x"50",x"6C",x"54",x"6C",x"58", -- 0x22D8 + x"6C",x"44",x"74",x"48",x"74",x"4C",x"74",x"50", -- 0x22E0 + x"74",x"54",x"74",x"58",x"74",x"44",x"7C",x"48", -- 0x22E8 + x"7C",x"4C",x"7C",x"50",x"7C",x"54",x"7C",x"58", -- 0x22F0 + x"7C",x"44",x"84",x"48",x"84",x"4C",x"84",x"50", -- 0x22F8 + x"84",x"54",x"84",x"58",x"84",x"44",x"8C",x"48", -- 0x2300 + x"8C",x"4C",x"8C",x"50",x"8C",x"54",x"8C",x"58", -- 0x2308 + x"8C",x"44",x"94",x"48",x"94",x"4C",x"94",x"50", -- 0x2310 + x"94",x"54",x"94",x"58",x"94",x"44",x"9C",x"48", -- 0x2318 + x"9C",x"4C",x"9C",x"50",x"9C",x"54",x"9C",x"58", -- 0x2320 + x"9C",x"44",x"AC",x"48",x"AC",x"4C",x"AC",x"50", -- 0x2328 + x"AC",x"54",x"AC",x"58",x"AC",x"44",x"B4",x"48", -- 0x2330 + x"B4",x"4C",x"B4",x"50",x"B4",x"54",x"B4",x"58", -- 0x2338 + x"B4",x"44",x"BC",x"48",x"BC",x"4C",x"BC",x"50", -- 0x2340 + x"BC",x"54",x"BC",x"58",x"BC",x"44",x"C4",x"48", -- 0x2348 + x"C4",x"4C",x"C4",x"50",x"C4",x"54",x"C4",x"58", -- 0x2350 + x"C4",x"44",x"CC",x"48",x"CC",x"4C",x"CC",x"50", -- 0x2358 + x"CC",x"54",x"CC",x"58",x"CC",x"44",x"D4",x"48", -- 0x2360 + x"D4",x"4C",x"D4",x"50",x"D4",x"54",x"D4",x"58", -- 0x2368 + x"D4",x"44",x"DC",x"48",x"DC",x"4C",x"DC",x"50", -- 0x2370 + x"DC",x"54",x"DC",x"58",x"DC",x"44",x"E4",x"48", -- 0x2378 + x"E4",x"4C",x"E4",x"50",x"E4",x"54",x"E4",x"58", -- 0x2380 + x"E4",x"CD",x"BF",x"1B",x"CD",x"45",x"1B",x"D0", -- 0x2388 + x"DD",x"34",x"02",x"DD",x"7E",x"05",x"D6",x"10", -- 0x2390 + x"DD",x"77",x"05",x"CD",x"8C",x"1C",x"DD",x"34", -- 0x2398 + x"02",x"CD",x"BF",x"1B",x"CD",x"45",x"1B",x"D0", -- 0x23A0 + x"DD",x"34",x"02",x"CD",x"A8",x"28",x"21",x"77", -- 0x23A8 + x"1C",x"DD",x"75",x"0C",x"DD",x"74",x"0D",x"DD", -- 0x23B0 + x"36",x"0E",x"01",x"DD",x"7E",x"17",x"C6",x"50", -- 0x23B8 + x"6F",x"26",x"41",x"36",x"03",x"DD",x"36",x"18", -- 0x23C0 + x"00",x"DD",x"36",x"19",x"00",x"21",x"1A",x"41", -- 0x23C8 + x"35",x"DD",x"36",x"10",x"0F",x"DD",x"34",x"02", -- 0x23D0 + x"CD",x"BF",x"1B",x"DD",x"35",x"10",x"C0",x"DD", -- 0x23D8 + x"36",x"02",x"02",x"C9",x"AF",x"67",x"68",x"57", -- 0x23E0 + x"59",x"06",x"08",x"CB",x"FF",x"07",x"29",x"A7", -- 0x23E8 + x"ED",x"52",x"38",x"03",x"10",x"F5",x"C9",x"19", -- 0x23F0 + x"CB",x"87",x"10",x"EF",x"C9",x"CD",x"69",x"28", -- 0x23F8 + x"21",x"B8",x"40",x"35",x"C0",x"2D",x"3A",x"1C", -- 0x2400 + x"41",x"47",x"0F",x"38",x"17",x"3A",x"1A",x"41", -- 0x2408 + x"FE",x"2C",x"30",x"36",x"78",x"A7",x"20",x"32", -- 0x2410 + x"3E",x"01",x"32",x"1C",x"41",x"11",x"08",x"06", -- 0x2418 + x"FF",x"36",x"02",x"C9",x"AF",x"32",x"1C",x"41", -- 0x2420 + x"11",x"88",x"06",x"FF",x"36",x"07",x"26",x"40", -- 0x2428 + x"2E",x"AE",x"36",x"20",x"2E",x"BF",x"36",x"12", -- 0x2430 + x"7C",x"C6",x"42",x"67",x"2E",x"02",x"36",x"0A", -- 0x2438 + x"7E",x"E6",x"F0",x"C8",x"26",x"40",x"2E",x"A1", -- 0x2440 + x"34",x"C9",x"34",x"C9",x"21",x"10",x"41",x"34", -- 0x2448 + x"11",x"00",x"07",x"FF",x"21",x"21",x"0F",x"11", -- 0x2450 + x"04",x"41",x"01",x"0C",x"00",x"ED",x"B0",x"21", -- 0x2458 + x"11",x"41",x"36",x"2E",x"23",x"36",x"00",x"3E", -- 0x2460 + x"05",x"32",x"0A",x"40",x"21",x"53",x"19",x"22", -- 0x2468 + x"07",x"42",x"C9",x"21",x"B7",x"40",x"34",x"2C", -- 0x2470 + x"36",x"06",x"23",x"36",x"0A",x"C9",x"21",x"B9", -- 0x2478 + x"40",x"35",x"C0",x"36",x"0A",x"21",x"20",x"41", -- 0x2480 + x"AF",x"06",x"30",x"D7",x"21",x"B7",x"40",x"34", -- 0x2488 + x"C9",x"21",x"B9",x"40",x"35",x"C0",x"36",x"0A", -- 0x2490 + x"21",x"20",x"41",x"3E",x"02",x"06",x"30",x"D7", -- 0x2498 + x"21",x"B7",x"40",x"34",x"C9",x"21",x"B8",x"40", -- 0x24A0 + x"35",x"20",x"29",x"2D",x"36",x"00",x"3E",x"30", -- 0x24A8 + x"32",x"16",x"41",x"21",x"10",x"41",x"34",x"11", -- 0x24B0 + x"00",x"07",x"FF",x"21",x"D8",x"24",x"11",x"04", -- 0x24B8 + x"41",x"01",x"06",x"00",x"ED",x"B0",x"21",x"11", -- 0x24C0 + x"41",x"36",x"18",x"2C",x"36",x"16",x"3E",x"05", -- 0x24C8 + x"32",x"0A",x"40",x"C9",x"2D",x"36",x"03",x"C9", -- 0x24D0 + x"10",x"68",x"64",x"64",x"68",x"10",x"C9",x"21", -- 0x24D8 + x"00",x"41",x"36",x"00",x"2C",x"34",x"7E",x"47", -- 0x24E0 + x"2F",x"C6",x"80",x"32",x"2A",x"40",x"32",x"2C", -- 0x24E8 + x"40",x"78",x"FE",x"FF",x"C0",x"36",x"80",x"21", -- 0x24F0 + x"B7",x"40",x"34",x"16",x"01",x"FF",x"23",x"36", -- 0x24F8 + x"19",x"26",x"40",x"2E",x"AE",x"7E",x"34",x"C6", -- 0x2500 + x"62",x"67",x"16",x"40",x"1E",x"BF",x"1A",x"D6", -- 0x2508 + x"10",x"6F",x"C6",x"0A",x"77",x"3D",x"77",x"AF", -- 0x2510 + x"86",x"E6",x"F0",x"C6",x"E0",x"C8",x"3E",x"01", -- 0x2518 + x"32",x"0A",x"40",x"C9",x"21",x"B8",x"40",x"35", -- 0x2520 + x"C0",x"3E",x"F7",x"32",x"BB",x"40",x"2F",x"32", -- 0x2528 + x"38",x"40",x"32",x"3A",x"40",x"21",x"B7",x"40", -- 0x2530 + x"34",x"CD",x"8F",x"28",x"11",x"09",x"06",x"FF", -- 0x2538 + x"26",x"40",x"2E",x"AE",x"7E",x"C6",x"61",x"67", -- 0x2540 + x"2E",x"02",x"36",x"0C",x"36",x"06",x"7E",x"E6", -- 0x2548 + x"F0",x"C8",x"21",x"1A",x"41",x"34",x"C9",x"21", -- 0x2550 + x"BA",x"40",x"36",x"01",x"2C",x"35",x"7E",x"47", -- 0x2558 + x"2F",x"C6",x"80",x"32",x"38",x"40",x"32",x"3A", -- 0x2560 + x"40",x"78",x"FE",x"80",x"C0",x"11",x"89",x"06", -- 0x2568 + x"FF",x"16",x"40",x"23",x"1E",x"BF",x"36",x"00", -- 0x2570 + x"21",x"B7",x"40",x"34",x"1A",x"C6",x"70",x"67", -- 0x2578 + x"D6",x"80",x"6F",x"C6",x"0A",x"77",x"3C",x"77", -- 0x2580 + x"3D",x"77",x"C9",x"CD",x"A3",x"15",x"CD",x"F7", -- 0x2588 + x"15",x"CD",x"B4",x"16",x"21",x"BC",x"40",x"7E", -- 0x2590 + x"2D",x"0F",x"38",x"08",x"35",x"7E",x"FE",x"27", -- 0x2598 + x"38",x"13",x"18",x"06",x"34",x"7E",x"FE",x"D9", -- 0x25A0 + x"30",x"0B",x"2F",x"C6",x"80",x"32",x"38",x"40", -- 0x25A8 + x"32",x"3A",x"40",x"18",x"02",x"2C",x"34",x"CD", -- 0x25B0 + x"E6",x"25",x"38",x"13",x"3A",x"BC",x"40",x"FE", -- 0x25B8 + x"0A",x"C0",x"AF",x"32",x"9D",x"40",x"11",x"89", -- 0x25C0 + x"06",x"FF",x"21",x"B7",x"40",x"34",x"C9",x"CD", -- 0x25C8 + x"4B",x"28",x"AF",x"32",x"9D",x"40",x"11",x"89", -- 0x25D0 + x"06",x"FF",x"21",x"B7",x"40",x"36",x"0D",x"2C", -- 0x25D8 + x"36",x"0A",x"2C",x"36",x"06",x"C9",x"21",x"7C", -- 0x25E0 + x"42",x"7E",x"0F",x"D0",x"23",x"3A",x"BB",x"40", -- 0x25E8 + x"C6",x"02",x"96",x"FE",x"05",x"D0",x"2C",x"2C", -- 0x25F0 + x"7E",x"FE",x"6E",x"D0",x"FE",x"69",x"3F",x"C9", -- 0x25F8 + x"CD",x"94",x"28",x"AF",x"32",x"BA",x"40",x"32", -- 0x2600 + x"7C",x"42",x"21",x"BB",x"40",x"35",x"7E",x"47", -- 0x2608 + x"2F",x"C6",x"80",x"32",x"38",x"40",x"32",x"3A", -- 0x2610 + x"40",x"78",x"FE",x"08",x"C0",x"CD",x"0E",x"27", -- 0x2618 + x"21",x"B7",x"40",x"34",x"2C",x"36",x"64",x"C9", -- 0x2620 + x"21",x"B8",x"40",x"35",x"C0",x"3E",x"01",x"32", -- 0x2628 + x"00",x"41",x"32",x"B7",x"40",x"C9",x"CD",x"94", -- 0x2630 + x"28",x"21",x"B8",x"40",x"35",x"C0",x"CD",x"4B", -- 0x2638 + x"28",x"AF",x"32",x"BA",x"40",x"32",x"7C",x"42", -- 0x2640 + x"36",x"0A",x"CD",x"0E",x"27",x"2D",x"34",x"C9", -- 0x2648 + x"21",x"B8",x"40",x"35",x"C0",x"36",x"0A",x"CD", -- 0x2650 + x"21",x"27",x"2D",x"34",x"C9",x"21",x"B9",x"40", -- 0x2658 + x"35",x"20",x"17",x"CD",x"0E",x"27",x"11",x"AB", -- 0x2660 + x"40",x"AF",x"12",x"1C",x"12",x"1C",x"12",x"E5", -- 0x2668 + x"CD",x"AC",x"26",x"E1",x"36",x"64",x"2D",x"2D", -- 0x2670 + x"34",x"C9",x"2D",x"2D",x"36",x"0D",x"C9",x"21", -- 0x2678 + x"B9",x"40",x"35",x"C0",x"11",x"8A",x"06",x"FF", -- 0x2680 + x"36",x"0A",x"2D",x"2D",x"34",x"C9",x"21",x"B9", -- 0x2688 + x"40",x"35",x"C0",x"36",x"0A",x"CD",x"47",x"27", -- 0x2690 + x"38",x"09",x"CD",x"AC",x"26",x"CD",x"59",x"27", -- 0x2698 + x"C3",x"99",x"28",x"21",x"B7",x"40",x"34",x"2C", -- 0x26A0 + x"2C",x"36",x"46",x"C9",x"3A",x"BC",x"40",x"47", -- 0x26A8 + x"3E",x"0A",x"90",x"07",x"07",x"07",x"07",x"E6", -- 0x26B0 + x"F0",x"00",x"00",x"21",x"AB",x"40",x"86",x"27", -- 0x26B8 + x"77",x"23",x"3E",x"00",x"8E",x"27",x"77",x"2D", -- 0x26C0 + x"7E",x"E6",x"0F",x"32",x"CD",x"49",x"7E",x"0F", -- 0x26C8 + x"0F",x"0F",x"0F",x"E6",x"0F",x"32",x"ED",x"49", -- 0x26D0 + x"2C",x"7E",x"E6",x"F0",x"28",x"0E",x"0F",x"0F", -- 0x26D8 + x"0F",x"0F",x"32",x"2D",x"4A",x"7E",x"E6",x"0F", -- 0x26E0 + x"32",x"0D",x"4A",x"C9",x"7E",x"E6",x"0F",x"C8", -- 0x26E8 + x"32",x"0D",x"4A",x"C9",x"21",x"B9",x"40",x"35", -- 0x26F0 + x"C0",x"11",x"8A",x"06",x"FF",x"11",x"00",x"03", -- 0x26F8 + x"FF",x"2D",x"2D",x"3E",x"01",x"77",x"32",x"00", -- 0x2700 + x"41",x"AF",x"32",x"16",x"41",x"C9",x"E5",x"06", -- 0x2708 + x"06",x"21",x"AC",x"49",x"11",x"1F",x"00",x"36", -- 0x2710 + x"10",x"23",x"36",x"10",x"19",x"10",x"F8",x"E1", -- 0x2718 + x"C9",x"E5",x"06",x"06",x"21",x"AC",x"49",x"11", -- 0x2720 + x"20",x"00",x"DD",x"21",x"AB",x"02",x"DD",x"7E", -- 0x2728 + x"00",x"77",x"19",x"DD",x"23",x"10",x"F7",x"06", -- 0x2730 + x"06",x"21",x"AD",x"49",x"DD",x"7E",x"00",x"77", -- 0x2738 + x"19",x"DD",x"23",x"10",x"F7",x"E1",x"C9",x"06", -- 0x2740 + x"30",x"21",x"20",x"41",x"CB",x"4E",x"20",x"05", -- 0x2748 + x"23",x"10",x"F9",x"37",x"C9",x"CB",x"8E",x"A7", -- 0x2750 + x"C9",x"21",x"55",x"41",x"11",x"06",x"00",x"4B", -- 0x2758 + x"06",x"18",x"CB",x"4E",x"20",x"0B",x"19",x"10", -- 0x2760 + x"F9",x"7D",x"D6",x"91",x"6F",x"0D",x"20",x"F0", -- 0x2768 + x"C9",x"36",x"01",x"21",x"1A",x"41",x"34",x"C9", -- 0x2770 + x"21",x"A0",x"42",x"11",x"20",x"00",x"06",x"08", -- 0x2778 + x"AF",x"B6",x"19",x"10",x"FC",x"0F",x"D0",x"3A", -- 0x2780 + x"1A",x"41",x"FE",x"04",x"38",x"0B",x"FE",x"07", -- 0x2788 + x"38",x"15",x"FE",x"0B",x"38",x"1F",x"C3",x"4F", -- 0x2790 + x"28",x"21",x"09",x"42",x"CB",x"46",x"C0",x"CD", -- 0x2798 + x"69",x"28",x"36",x"01",x"C3",x"AD",x"28",x"21", -- 0x27A0 + x"0A",x"42",x"CB",x"46",x"C0",x"CD",x"69",x"28", -- 0x27A8 + x"36",x"01",x"C3",x"B2",x"28",x"21",x"0B",x"42", -- 0x27B0 + x"CB",x"46",x"C0",x"CD",x"69",x"28",x"36",x"01", -- 0x27B8 + x"C3",x"B7",x"28",x"3E",x"18",x"32",x"A0",x"43", -- 0x27C0 + x"32",x"01",x"82",x"AF",x"C3",x"14",x"28",x"AF", -- 0x27C8 + x"CD",x"14",x"28",x"3A",x"A0",x"43",x"E6",x"EF", -- 0x27D0 + x"32",x"A0",x"43",x"32",x"01",x"82",x"C9",x"21", -- 0x27D8 + x"A2",x"43",x"7E",x"A7",x"C8",x"35",x"3A",x"A3", -- 0x27E0 + x"43",x"47",x"3A",x"06",x"40",x"0F",x"78",x"DC", -- 0x27E8 + x"14",x"28",x"21",x"A4",x"43",x"11",x"A3",x"43", -- 0x27F0 + x"01",x"0C",x"00",x"ED",x"B0",x"C9",x"E5",x"C5", -- 0x27F8 + x"47",x"21",x"A2",x"43",x"7E",x"FE",x"0D",x"30", -- 0x2800 + x"08",x"34",x"7E",x"C6",x"A2",x"6F",x"26",x"43", -- 0x2808 + x"70",x"C1",x"E1",x"C9",x"32",x"00",x"82",x"3A", -- 0x2810 + x"A0",x"43",x"E6",x"10",x"32",x"01",x"82",x"00", -- 0x2818 + x"00",x"00",x"00",x"3A",x"A0",x"43",x"E6",x"10", -- 0x2820 + x"F6",x"48",x"32",x"01",x"82",x"C9",x"3E",x"01", -- 0x2828 + x"18",x"E2",x"3E",x"02",x"18",x"C8",x"AF",x"CD", -- 0x2830 + x"FE",x"27",x"3E",x"04",x"C3",x"FE",x"27",x"3E", -- 0x2838 + x"05",x"18",x"BB",x"3E",x"0A",x"18",x"B7",x"3E", -- 0x2840 + x"08",x"18",x"B3",x"3E",x"09",x"18",x"AF",x"21", -- 0x2848 + x"A1",x"43",x"CB",x"46",x"C0",x"21",x"09",x"42", -- 0x2850 + x"AF",x"B6",x"2C",x"B6",x"2C",x"B6",x"C0",x"3E", -- 0x2858 + x"01",x"32",x"A1",x"43",x"3E",x"30",x"C3",x"FE", -- 0x2860 + x"27",x"AF",x"32",x"A1",x"43",x"32",x"09",x"42", -- 0x2868 + x"32",x"0A",x"42",x"32",x"0B",x"42",x"3E",x"40", -- 0x2870 + x"CD",x"FE",x"27",x"3E",x"60",x"CD",x"FE",x"27", -- 0x2878 + x"3E",x"80",x"CD",x"FE",x"27",x"3E",x"A0",x"C3", -- 0x2880 + x"FE",x"27",x"3E",x"06",x"C3",x"FE",x"27",x"3E", -- 0x2888 + x"10",x"C3",x"FE",x"27",x"3E",x"20",x"C3",x"FE", -- 0x2890 + x"27",x"3E",x"0B",x"C3",x"FE",x"27",x"3E",x"03", -- 0x2898 + x"C3",x"FE",x"27",x"3E",x"07",x"C3",x"FE",x"27", -- 0x28A0 + x"3E",x"0C",x"C3",x"FE",x"27",x"3E",x"90",x"C3", -- 0x28A8 + x"FE",x"27",x"3E",x"70",x"C3",x"FE",x"27",x"3E", -- 0x28B0 + x"07",x"CD",x"FE",x"27",x"3E",x"50",x"C3",x"FE", -- 0x28B8 + x"27",x"CD",x"69",x"28",x"3E",x"0D",x"C3",x"FE", -- 0x28C0 + x"27",x"21",x"00",x"50",x"01",x"00",x"01",x"16", -- 0x28C8 + x"00",x"72",x"23",x"0B",x"78",x"B1",x"20",x"F9", -- 0x28D0 + x"16",x"5B",x"21",x"00",x"48",x"01",x"00",x"08", -- 0x28D8 + x"72",x"3A",x"00",x"70",x"23",x"0B",x"78",x"B1", -- 0x28E0 + x"20",x"F6",x"CD",x"01",x"29",x"30",x"0D",x"CD", -- 0x28E8 + x"01",x"29",x"30",x"08",x"3E",x"01",x"32",x"01", -- 0x28F0 + x"68",x"C3",x"EE",x"00",x"3A",x"00",x"70",x"18", -- 0x28F8 + x"FB",x"0B",x"3A",x"00",x"70",x"3A",x"01",x"81", -- 0x2900 + x"07",x"D0",x"78",x"B1",x"20",x"F3",x"37",x"C9", -- 0x2908 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2910 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2918 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2920 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2928 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2930 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2938 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2940 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2948 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2950 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2958 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2960 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2968 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2970 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2978 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2980 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2988 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2990 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2998 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29A0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29A8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29B0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x29F8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2A98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2AF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2B98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2BF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2C98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2CF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2D98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2DF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2E98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2ED8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2EF8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F00 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F08 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F10 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F18 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F20 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F28 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F30 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F38 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F40 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F48 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F50 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F58 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F60 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F68 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F70 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F78 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F80 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F88 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F90 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2F98 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FA8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FB8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FC8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FD8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FE8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x2FF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3000 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3008 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3010 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3018 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3020 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3028 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3030 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3038 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3040 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3048 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3050 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3058 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3060 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3068 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3070 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3078 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3080 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3088 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3090 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3098 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x30F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3100 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3108 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3110 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3118 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3120 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3128 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3130 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3138 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3140 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3148 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3150 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3158 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3160 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3168 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3170 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3178 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3180 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3188 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3190 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3198 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x31F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3200 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3208 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3210 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3218 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3220 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3228 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3230 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3238 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3240 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3248 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3250 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3258 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3260 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3268 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3270 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3278 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3280 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3288 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3290 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3298 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x32F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3300 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3308 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3310 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3318 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3320 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3328 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3330 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3338 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3340 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3348 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3350 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3358 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3360 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3368 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3370 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3378 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3380 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3388 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3390 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3398 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x33F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3400 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3408 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3410 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3418 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3420 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3428 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3430 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3438 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3440 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3448 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3450 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3458 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3460 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3468 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3470 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3478 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3480 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3488 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3490 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3498 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x34F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3500 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3508 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3510 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3518 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3520 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3528 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3530 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3538 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3540 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3548 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3550 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3558 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3560 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3568 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3570 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3578 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3580 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3588 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3590 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3598 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x35F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3600 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3608 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3610 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3618 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3620 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3628 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3630 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3638 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3640 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3648 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3650 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3658 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3660 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3668 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3670 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3678 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3680 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3688 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3690 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3698 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x36F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3700 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3708 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3710 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3718 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3720 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3728 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3730 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3738 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3740 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3748 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3750 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3758 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3760 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3768 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3770 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3778 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3780 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3788 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3790 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3798 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x37F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3800 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3808 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3810 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3818 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3820 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3828 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3830 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3838 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3840 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3848 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3850 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3858 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3860 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3868 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3870 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3878 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3880 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3888 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3890 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3898 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x38F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3900 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3908 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3910 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3918 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3920 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3928 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3930 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3938 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3940 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3948 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3950 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3958 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3960 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3968 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3970 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3978 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3980 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3988 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3990 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3998 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39A8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39B8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39C8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39D8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39E8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x39F8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3A98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3AF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3B98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3BF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3CF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3D98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3DF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3E98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3ED8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3EF8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F00 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F08 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F10 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F18 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F20 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F28 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F30 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F38 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F40 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F48 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F50 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F58 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F60 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F68 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F70 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F78 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F80 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F88 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F90 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F98 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FA8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FB8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FC8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FE8 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FF0 + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x3FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.bin new file mode 100644 index 00000000..c7acec5e Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd new file mode 100644 index 00000000..8d55c20e --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_0.vhd @@ -0,0 +1,284 @@ +-- generated with romgen by MikeJ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ROM_SND_0 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_SND_0 is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"C3",x"CE",x"01",x"01",x"F7",x"00",x"01",x"DC", -- 0x0000 + x"00",x"01",x"15",x"01",x"01",x"F7",x"00",x"01", -- 0x0008 + x"DC",x"00",x"01",x"D0",x"00",x"01",x"F7",x"00", -- 0x0010 + x"01",x"DC",x"00",x"01",x"D0",x"00",x"01",x"B9", -- 0x0018 + x"00",x"01",x"DC",x"00",x"01",x"D0",x"00",x"01", -- 0x0020 + x"00",x"00",x"01",x"68",x"00",x"FF",x"FF",x"FF", -- 0x0028 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0030 + x"08",x"D9",x"3E",x"0E",x"D3",x"40",x"DB",x"80", -- 0x0038 + x"B7",x"28",x"32",x"57",x"E6",x"0F",x"20",x"3B", -- 0x0040 + x"7A",x"FE",x"10",x"28",x"3E",x"FE",x"20",x"28", -- 0x0048 + x"43",x"FE",x"30",x"28",x"48",x"FE",x"40",x"28", -- 0x0050 + x"4D",x"FE",x"50",x"28",x"52",x"FE",x"60",x"28", -- 0x0058 + x"57",x"FE",x"70",x"28",x"5C",x"FE",x"80",x"28", -- 0x0060 + x"61",x"FE",x"90",x"28",x"66",x"FE",x"A0",x"28", -- 0x0068 + x"6B",x"D9",x"08",x"FB",x"C9",x"06",x"06",x"21", -- 0x0070 + x"00",x"80",x"77",x"23",x"05",x"20",x"FB",x"D9", -- 0x0078 + x"08",x"FB",x"C9",x"7A",x"CD",x"01",x"01",x"D9", -- 0x0080 + x"08",x"FB",x"C9",x"3E",x"11",x"CD",x"01",x"01", -- 0x0088 + x"D9",x"08",x"FB",x"C9",x"3E",x"11",x"CD",x"E5", -- 0x0090 + x"00",x"D9",x"08",x"FB",x"C9",x"3E",x"12",x"CD", -- 0x0098 + x"01",x"01",x"D9",x"08",x"FB",x"C9",x"3E",x"12", -- 0x00A0 + x"CD",x"E5",x"00",x"D9",x"08",x"FB",x"C9",x"3E", -- 0x00A8 + x"13",x"CD",x"01",x"01",x"D9",x"08",x"FB",x"C9", -- 0x00B0 + x"3E",x"13",x"CD",x"E5",x"00",x"D9",x"08",x"FB", -- 0x00B8 + x"C9",x"3E",x"14",x"CD",x"01",x"01",x"D9",x"08", -- 0x00C0 + x"FB",x"C9",x"3E",x"14",x"CD",x"E5",x"00",x"D9", -- 0x00C8 + x"08",x"FB",x"C9",x"3E",x"15",x"CD",x"01",x"01", -- 0x00D0 + x"D9",x"08",x"FB",x"C9",x"3E",x"15",x"CD",x"E5", -- 0x00D8 + x"00",x"D9",x"08",x"FB",x"C9",x"CD",x"99",x"01", -- 0x00E0 + x"B7",x"C8",x"FE",x"01",x"28",x"09",x"FE",x"02", -- 0x00E8 + x"28",x"0A",x"AF",x"32",x"04",x"80",x"C9",x"AF", -- 0x00F0 + x"32",x"00",x"80",x"C9",x"AF",x"32",x"02",x"80", -- 0x00F8 + x"C9",x"32",x"06",x"80",x"CD",x"99",x"01",x"B7", -- 0x0100 + x"C0",x"AF",x"CD",x"99",x"01",x"B7",x"20",x"41", -- 0x0108 + x"3A",x"00",x"80",x"CD",x"BC",x"01",x"32",x"07", -- 0x0110 + x"80",x"3A",x"02",x"80",x"CD",x"BC",x"01",x"32", -- 0x0118 + x"08",x"80",x"3A",x"04",x"80",x"CD",x"BC",x"01", -- 0x0120 + x"32",x"09",x"80",x"3A",x"06",x"80",x"CD",x"BC", -- 0x0128 + x"01",x"32",x"0A",x"80",x"3A",x"07",x"80",x"21", -- 0x0130 + x"08",x"80",x"BE",x"FA",x"6E",x"01",x"3A",x"09", -- 0x0138 + x"80",x"BE",x"FA",x"8D",x"01",x"3A",x"0A",x"80", -- 0x0140 + x"BE",x"F8",x"21",x"02",x"80",x"CD",x"C5",x"01", -- 0x0148 + x"C9",x"FE",x"01",x"28",x"0B",x"FE",x"02",x"28", -- 0x0150 + x"0E",x"3A",x"06",x"80",x"32",x"04",x"80",x"C9", -- 0x0158 + x"3A",x"06",x"80",x"32",x"00",x"80",x"C9",x"3A", -- 0x0160 + x"06",x"80",x"32",x"02",x"80",x"C9",x"21",x"09", -- 0x0168 + x"80",x"BE",x"FA",x"81",x"01",x"3A",x"0A",x"80", -- 0x0170 + x"BE",x"F8",x"21",x"04",x"80",x"CD",x"C5",x"01", -- 0x0178 + x"C9",x"21",x"0A",x"80",x"BE",x"F0",x"21",x"00", -- 0x0180 + x"80",x"CD",x"C5",x"01",x"C9",x"21",x"0A",x"80", -- 0x0188 + x"BE",x"F0",x"21",x"04",x"80",x"CD",x"C5",x"01", -- 0x0190 + x"C9",x"06",x"00",x"21",x"00",x"80",x"BE",x"28", -- 0x0198 + x"0C",x"23",x"23",x"BE",x"28",x"0C",x"23",x"23", -- 0x01A0 + x"BE",x"28",x"0C",x"AF",x"C9",x"23",x"70",x"3E", -- 0x01A8 + x"01",x"C9",x"23",x"70",x"3E",x"02",x"C9",x"23", -- 0x01B0 + x"70",x"3E",x"03",x"C9",x"21",x"A1",x"04",x"5F", -- 0x01B8 + x"16",x"00",x"19",x"7E",x"C9",x"3A",x"06",x"80", -- 0x01C0 + x"77",x"3E",x"00",x"23",x"77",x"C9",x"06",x"00", -- 0x01C8 + x"21",x"00",x"80",x"70",x"23",x"7C",x"FE",x"84", -- 0x01D0 + x"20",x"F9",x"31",x"00",x"84",x"ED",x"56",x"3E", -- 0x01D8 + x"07",x"D3",x"40",x"3E",x"3F",x"32",x"0C",x"80", -- 0x01E0 + x"D3",x"80",x"CD",x"FA",x"03",x"CD",x"02",x"04", -- 0x01E8 + x"CD",x"0A",x"04",x"FB",x"3E",x"0F",x"D3",x"40", -- 0x01F0 + x"DB",x"80",x"E6",x"80",x"20",x"F6",x"3E",x"0F", -- 0x01F8 + x"D3",x"40",x"DB",x"80",x"E6",x"80",x"28",x"F6", -- 0x0200 + x"F3",x"3E",x"01",x"32",x"0B",x"80",x"3A",x"01", -- 0x0208 + x"80",x"B7",x"28",x"34",x"3A",x"00",x"80",x"CD", -- 0x0210 + x"2B",x"03",x"FB",x"00",x"00",x"00",x"F3",x"3E", -- 0x0218 + x"02",x"32",x"0B",x"80",x"3A",x"03",x"80",x"B7", -- 0x0220 + x"28",x"26",x"3A",x"02",x"80",x"CD",x"2B",x"03", -- 0x0228 + x"FB",x"00",x"00",x"00",x"F3",x"3E",x"03",x"32", -- 0x0230 + x"0B",x"80",x"3A",x"05",x"80",x"B7",x"28",x"18", -- 0x0238 + x"3A",x"04",x"80",x"CD",x"2B",x"03",x"18",x"AB", -- 0x0240 + x"3A",x"00",x"80",x"CD",x"60",x"02",x"18",x"CA", -- 0x0248 + x"3A",x"02",x"80",x"CD",x"60",x"02",x"18",x"D8", -- 0x0250 + x"3A",x"04",x"80",x"CD",x"60",x"02",x"18",x"93", -- 0x0258 + x"FE",x"01",x"28",x"5C",x"FE",x"02",x"28",x"5D", -- 0x0260 + x"FE",x"03",x"28",x"5E",x"FE",x"04",x"28",x"5F", -- 0x0268 + x"FE",x"05",x"28",x"60",x"FE",x"06",x"28",x"61", -- 0x0270 + x"FE",x"07",x"28",x"62",x"FE",x"08",x"28",x"63", -- 0x0278 + x"FE",x"09",x"28",x"64",x"FE",x"0A",x"28",x"65", -- 0x0280 + x"FE",x"0B",x"28",x"66",x"FE",x"0C",x"28",x"67", -- 0x0288 + x"FE",x"0D",x"28",x"68",x"FE",x"0E",x"28",x"69", -- 0x0290 + x"FE",x"11",x"28",x"6A",x"FE",x"12",x"28",x"6B", -- 0x0298 + x"FE",x"13",x"28",x"6C",x"FE",x"14",x"28",x"6D", -- 0x02A0 + x"FE",x"15",x"28",x"6E",x"CD",x"B7",x"04",x"3A", -- 0x02A8 + x"0B",x"80",x"FE",x"01",x"28",x"69",x"FE",x"02", -- 0x02B0 + x"28",x"6B",x"3E",x"01",x"32",x"05",x"80",x"C9", -- 0x02B8 + x"CD",x"2A",x"05",x"18",x"EA",x"CD",x"90",x"05", -- 0x02C0 + x"18",x"E5",x"CD",x"D8",x"05",x"18",x"E0",x"CD", -- 0x02C8 + x"3A",x"06",x"18",x"DB",x"CD",x"F7",x"08",x"18", -- 0x02D0 + x"D6",x"CD",x"68",x"09",x"18",x"D1",x"CD",x"53", -- 0x02D8 + x"0F",x"18",x"CC",x"CD",x"AE",x"09",x"18",x"C7", -- 0x02E0 + x"CD",x"38",x"0A",x"18",x"C2",x"CD",x"0F",x"0B", -- 0x02E8 + x"18",x"BD",x"CD",x"78",x"0B",x"18",x"B8",x"CD", -- 0x02F0 + x"A3",x"0B",x"18",x"B3",x"CD",x"05",x"0C",x"18", -- 0x02F8 + x"AE",x"CD",x"BA",x"07",x"18",x"A9",x"CD",x"6E", -- 0x0300 + x"0C",x"18",x"A4",x"CD",x"CE",x"0C",x"18",x"9F", -- 0x0308 + x"CD",x"32",x"0E",x"18",x"9A",x"CD",x"F5",x"0E", -- 0x0310 + x"18",x"95",x"CD",x"24",x"0F",x"18",x"90",x"3E", -- 0x0318 + x"01",x"32",x"01",x"80",x"C9",x"3E",x"01",x"32", -- 0x0320 + x"03",x"80",x"C9",x"FE",x"01",x"28",x"49",x"FE", -- 0x0328 + x"02",x"28",x"4A",x"FE",x"03",x"28",x"4B",x"FE", -- 0x0330 + x"04",x"28",x"4C",x"FE",x"05",x"28",x"4D",x"FE", -- 0x0338 + x"06",x"28",x"4E",x"FE",x"07",x"28",x"4F",x"FE", -- 0x0340 + x"08",x"28",x"50",x"FE",x"09",x"28",x"6A",x"FE", -- 0x0348 + x"0A",x"28",x"4D",x"FE",x"0B",x"28",x"4E",x"FE", -- 0x0350 + x"0C",x"28",x"4F",x"FE",x"0D",x"28",x"50",x"FE", -- 0x0358 + x"0E",x"28",x"51",x"FE",x"11",x"28",x"57",x"FE", -- 0x0360 + x"12",x"28",x"58",x"FE",x"13",x"28",x"59",x"FE", -- 0x0368 + x"14",x"28",x"5A",x"FE",x"15",x"28",x"5B",x"C9", -- 0x0370 + x"CD",x"4D",x"05",x"18",x"58",x"CD",x"A4",x"05", -- 0x0378 + x"18",x"53",x"CD",x"EF",x"05",x"18",x"4E",x"CD", -- 0x0380 + x"67",x"06",x"18",x"49",x"CD",x"21",x"09",x"18", -- 0x0388 + x"44",x"CD",x"7C",x"09",x"18",x"3F",x"CD",x"76", -- 0x0390 + x"0F",x"18",x"3A",x"CD",x"D0",x"09",x"18",x"35", -- 0x0398 + x"CD",x"2C",x"0B",x"18",x"30",x"CD",x"8C",x"0B", -- 0x03A0 + x"18",x"2B",x"CD",x"BA",x"0B",x"18",x"26",x"CD", -- 0x03A8 + x"22",x"0C",x"18",x"21",x"CD",x"E0",x"07",x"18", -- 0x03B0 + x"1C",x"CD",x"5E",x"0A",x"18",x"17",x"CD",x"8C", -- 0x03B8 + x"0C",x"18",x"12",x"CD",x"E3",x"0C",x"18",x"0D", -- 0x03C0 + x"CD",x"5E",x"0E",x"18",x"08",x"CD",x"21",x"0F", -- 0x03C8 + x"18",x"03",x"CD",x"50",x"0F",x"B7",x"C8",x"3A", -- 0x03D0 + x"0B",x"80",x"FE",x"01",x"28",x"0C",x"FE",x"02", -- 0x03D8 + x"28",x"10",x"AF",x"32",x"04",x"80",x"32",x"05", -- 0x03E0 + x"80",x"C9",x"AF",x"32",x"00",x"80",x"32",x"01", -- 0x03E8 + x"80",x"C9",x"AF",x"32",x"02",x"80",x"32",x"03", -- 0x03F0 + x"80",x"C9",x"3E",x"08",x"D3",x"40",x"AF",x"D3", -- 0x03F8 + x"80",x"C9",x"3E",x"09",x"D3",x"40",x"AF",x"D3", -- 0x0400 + x"80",x"C9",x"3E",x"0A",x"D3",x"40",x"AF",x"D3", -- 0x0408 + x"80",x"C9",x"3A",x"0B",x"80",x"FE",x"01",x"28", -- 0x0410 + x"14",x"FE",x"02",x"28",x"14",x"06",x"04",x"78", -- 0x0418 + x"D3",x"40",x"7D",x"D3",x"80",x"04",x"78",x"D3", -- 0x0420 + x"40",x"7C",x"D3",x"80",x"C9",x"06",x"00",x"18", -- 0x0428 + x"EE",x"06",x"02",x"18",x"EA",x"3A",x"0B",x"80", -- 0x0430 + x"FE",x"01",x"28",x"14",x"FE",x"02",x"28",x"14", -- 0x0438 + x"06",x"04",x"78",x"D3",x"40",x"DB",x"80",x"6F", -- 0x0440 + x"04",x"78",x"D3",x"40",x"DB",x"80",x"67",x"C9", -- 0x0448 + x"06",x"00",x"18",x"EE",x"06",x"02",x"18",x"EA", -- 0x0450 + x"3A",x"0B",x"80",x"FE",x"01",x"28",x"0C",x"FE", -- 0x0458 + x"02",x"28",x"0E",x"06",x"FB",x"1E",x"20",x"CD", -- 0x0460 + x"77",x"04",x"C9",x"06",x"FE",x"1E",x"08",x"18", -- 0x0468 + x"F6",x"06",x"FD",x"1E",x"10",x"18",x"F0",x"3E", -- 0x0470 + x"07",x"D3",x"40",x"3A",x"0C",x"80",x"A0",x"B3", -- 0x0478 + x"32",x"0C",x"80",x"D3",x"80",x"C9",x"3A",x"0B", -- 0x0480 + x"80",x"FE",x"01",x"28",x"0C",x"FE",x"02",x"28", -- 0x0488 + x"0C",x"3E",x"0A",x"D3",x"40",x"78",x"D3",x"80", -- 0x0490 + x"C9",x"3E",x"08",x"18",x"F6",x"3E",x"09",x"18", -- 0x0498 + x"F2",x"00",x"0B",x"06",x"01",x"0C",x"08",x"04", -- 0x04A0 + x"09",x"07",x"0A",x"05",x"03",x"02",x"0D",x"0E", -- 0x04A8 + x"0F",x"10",x"11",x"12",x"13",x"14",x"15",x"3A", -- 0x04B0 + x"0B",x"80",x"FE",x"01",x"28",x"0D",x"FE",x"02", -- 0x04B8 + x"28",x"12",x"06",x"24",x"CD",x"DD",x"04",x"CD", -- 0x04C0 + x"0A",x"04",x"C9",x"06",x"09",x"CD",x"DD",x"04", -- 0x04C8 + x"CD",x"FA",x"03",x"C9",x"06",x"12",x"CD",x"DD", -- 0x04D0 + x"04",x"CD",x"02",x"04",x"C9",x"3E",x"07",x"D3", -- 0x04D8 + x"40",x"3A",x"0C",x"80",x"B0",x"32",x"0C",x"80", -- 0x04E0 + x"D3",x"80",x"C9",x"3A",x"0B",x"80",x"FE",x"01", -- 0x04E8 + x"28",x"0C",x"FE",x"02",x"28",x"0E",x"06",x"DF", -- 0x04F0 + x"1E",x"04",x"CD",x"77",x"04",x"C9",x"06",x"F7", -- 0x04F8 + x"1E",x"01",x"18",x"F6",x"06",x"EF",x"1E",x"02", -- 0x0500 + x"18",x"F0",x"D3",x"40",x"78",x"D3",x"80",x"C9", -- 0x0508 + x"3A",x"0B",x"80",x"FE",x"01",x"28",x"0B",x"FE", -- 0x0510 + x"02",x"28",x"0B",x"3E",x"0A",x"D3",x"40",x"DB", -- 0x0518 + x"80",x"C9",x"3E",x"08",x"18",x"F7",x"3E",x"09", -- 0x0520 + x"18",x"F3",x"3E",x"02",x"32",x"10",x"80",x"21", -- 0x0528 + x"00",x"01",x"22",x"11",x"80",x"3E",x"01",x"32", -- 0x0530 + x"13",x"80",x"AF",x"32",x"14",x"80",x"21",x"C0", -- 0x0538 + x"00",x"CD",x"12",x"04",x"CD",x"58",x"04",x"06", -- 0x0540 + x"0F",x"CD",x"86",x"04",x"C9",x"21",x"10",x"80", -- 0x0548 + x"35",x"20",x"0A",x"3E",x"02",x"77",x"CD",x"35", -- 0x0550 + x"04",x"2B",x"CD",x"12",x"04",x"3A",x"14",x"80", -- 0x0558 + x"FE",x"00",x"28",x"15",x"21",x"13",x"80",x"35", -- 0x0560 + x"20",x"0D",x"3E",x"01",x"77",x"CD",x"10",x"05", -- 0x0568 + x"3D",x"28",x"1A",x"47",x"CD",x"86",x"04",x"AF", -- 0x0570 + x"C9",x"2A",x"11",x"80",x"2B",x"7C",x"B5",x"28", -- 0x0578 + x"05",x"22",x"11",x"80",x"18",x"F1",x"3E",x"01", -- 0x0580 + x"32",x"14",x"80",x"18",x"EA",x"3E",x"FF",x"C9", -- 0x0588 + x"3E",x"10",x"32",x"16",x"80",x"21",x"80",x"00", -- 0x0590 + x"CD",x"12",x"04",x"CD",x"58",x"04",x"06",x"0F", -- 0x0598 + x"CD",x"86",x"04",x"C9",x"21",x"16",x"80",x"35", -- 0x05A0 + x"28",x"1A",x"CD",x"35",x"04",x"11",x"04",x"00", -- 0x05A8 + x"19",x"11",x"00",x"01",x"7C",x"BA",x"20",x"07", -- 0x05B0 + x"7D",x"BB",x"20",x"03",x"21",x"80",x"00",x"CD", -- 0x05B8 + x"12",x"04",x"AF",x"C9",x"3E",x"10",x"32",x"16", -- 0x05C0 + x"80",x"CD",x"10",x"05",x"3D",x"28",x"06",x"47", -- 0x05C8 + x"CD",x"86",x"04",x"18",x"D5",x"3E",x"FF",x"C9", -- 0x05D0 + x"3E",x"01",x"32",x"18",x"80",x"3E",x"08",x"32", -- 0x05D8 + x"19",x"80",x"AF",x"32",x"1A",x"80",x"CD",x"58", -- 0x05E0 + x"04",x"06",x"00",x"CD",x"86",x"04",x"C9",x"3A", -- 0x05E8 + x"1A",x"80",x"FE",x"00",x"28",x"24",x"FE",x"01", -- 0x05F0 + x"28",x"31",x"CD",x"35",x"04",x"01",x"40",x"00", -- 0x05F8 + x"B7",x"ED",x"42",x"CD",x"12",x"04",x"21",x"19", -- 0x0600 + x"80",x"35",x"20",x"0C",x"36",x"08",x"CD",x"10", -- 0x0608 + x"05",x"3D",x"28",x"23",x"47",x"CD",x"86",x"04", -- 0x0610 + x"AF",x"C9",x"21",x"00",x"04",x"CD",x"12",x"04", -- 0x0618 + x"06",x"0F",x"CD",x"86",x"04",x"21",x"1A",x"80", -- 0x0620 + x"34",x"18",x"ED",x"21",x"18",x"80",x"35",x"20", -- 0x0628 + x"E7",x"21",x"1A",x"80",x"34",x"18",x"E1",x"3E", -- 0x0630 + x"FF",x"C9",x"3E",x"0B",x"32",x"1C",x"80",x"32", -- 0x0638 + x"1D",x"80",x"21",x"18",x"07",x"22",x"1E",x"80", -- 0x0640 + x"AF",x"32",x"20",x"80",x"32",x"21",x"80",x"21", -- 0x0648 + x"8A",x"00",x"CD",x"12",x"04",x"CD",x"58",x"04", -- 0x0650 + x"06",x"0F",x"CD",x"86",x"04",x"3E",x"0E",x"32", -- 0x0658 + x"04",x"80",x"AF",x"32",x"05",x"80",x"C9",x"3A", -- 0x0660 + x"20",x"80",x"FE",x"01",x"28",x"14",x"FE",x"02", -- 0x0668 + x"28",x"24",x"3A",x"21",x"80",x"FE",x"44",x"28", -- 0x0670 + x"3E",x"E6",x"01",x"20",x"49",x"CD",x"F0",x"06", -- 0x0678 + x"AF",x"C9",x"CD",x"10",x"05",x"C6",x"05",x"FE", -- 0x0680 + x"0F",x"20",x"05",x"21",x"20",x"80",x"36",x"00", -- 0x0688 + x"47",x"CD",x"86",x"04",x"18",x"EA",x"CD",x"10", -- 0x0690 + x"05",x"D6",x"05",x"20",x"05",x"21",x"20",x"80", -- 0x0698 + x"36",x"00",x"47",x"CD",x"86",x"04",x"3A",x"20", -- 0x06A0 + x"80",x"FE",x"00",x"20",x"D3",x"3A",x"21",x"80", -- 0x06A8 + x"FE",x"44",x"20",x"CC",x"3E",x"FF",x"C9",x"CD", -- 0x06B0 + x"04",x"07",x"B7",x"20",x"02",x"18",x"C1",x"21", -- 0x06B8 + x"20",x"80",x"36",x"02",x"18",x"BA",x"CD",x"CB", -- 0x06C0 + x"06",x"18",x"B5",x"CD",x"04",x"07",x"B7",x"C8", -- 0x06C8 + x"ED",x"5B",x"1E",x"80",x"1A",x"32",x"1D",x"80", -- 0x06D0 + x"13",x"1A",x"6F",x"13",x"1A",x"67",x"13",x"ED", -- 0x06D8 + x"53",x"1E",x"80",x"CD",x"12",x"04",x"21",x"21", -- 0x06E0 + x"80",x"34",x"21",x"20",x"80",x"36",x"01",x"C9", -- 0x06E8 + x"CD",x"04",x"07",x"B7",x"C8",x"3E",x"01",x"32", -- 0x06F0 + x"1D",x"80",x"21",x"21",x"80",x"34",x"21",x"20", -- 0x06F8 + x"80",x"36",x"02",x"C9",x"21",x"1C",x"80",x"35", -- 0x0700 + x"20",x"0C",x"3E",x"0B",x"77",x"21",x"1D",x"80", -- 0x0708 + x"35",x"20",x"03",x"3E",x"FF",x"C9",x"AF",x"C9", -- 0x0710 + x"01",x"8A",x"00",x"01",x"8A",x"00",x"0B",x"8A", -- 0x0718 + x"00",x"01",x"8A",x"00",x"01",x"8A",x"00",x"03", -- 0x0720 + x"8A",x"00",x"03",x"A5",x"00",x"03",x"D0",x"00", -- 0x0728 + x"03",x"A5",x"00",x"03",x"8A",x"00",x"03",x"A5", -- 0x0730 + x"00",x"03",x"8A",x"00",x"03",x"68",x"00",x"03", -- 0x0738 + x"8A",x"00",x"03",x"A5",x"00",x"03",x"D0",x"00", -- 0x0740 + x"03",x"A5",x"00",x"03",x"8A",x"00",x"03",x"A5", -- 0x0748 + x"00",x"03",x"8A",x"00",x"03",x"68",x"00",x"0B", -- 0x0750 + x"8A",x"00",x"01",x"8A",x"00",x"01",x"8A",x"00", -- 0x0758 + x"0B",x"8A",x"00",x"01",x"8A",x"00",x"01",x"8A", -- 0x0760 + x"00",x"0B",x"8A",x"00",x"01",x"8A",x"00",x"01", -- 0x0768 + x"8A",x"00",x"0B",x"8A",x"00",x"01",x"8A",x"00", -- 0x0770 + x"01",x"8A",x"00",x"20",x"8A",x"00",x"01",x"8A", -- 0x0778 + x"00",x"01",x"8A",x"00",x"03",x"8A",x"00",x"03", -- 0x0780 + x"8A",x"00",x"03",x"8A",x"00",x"01",x"8A",x"00", -- 0x0788 + x"01",x"8A",x"00",x"03",x"8A",x"00",x"03",x"8A", -- 0x0790 + x"00",x"03",x"8A",x"00",x"01",x"8A",x"00",x"01", -- 0x0798 + x"8A",x"00",x"03",x"8A",x"00",x"03",x"8A",x"00", -- 0x07A0 + x"03",x"8A",x"00",x"01",x"8A",x"00",x"01",x"8A", -- 0x07A8 + x"00",x"03",x"8A",x"00",x"03",x"8A",x"00",x"20", -- 0x07B0 + x"8A",x"00",x"3E",x"0B",x"32",x"22",x"80",x"3E", -- 0x07B8 + x"0D",x"32",x"23",x"80",x"21",x"91",x"08",x"22", -- 0x07C0 + x"24",x"80",x"AF",x"32",x"26",x"80",x"32",x"27", -- 0x07C8 + x"80",x"21",x"15",x"01",x"CD",x"12",x"04",x"CD", -- 0x07D0 + x"58",x"04",x"06",x"0F",x"CD",x"86",x"04",x"C9", -- 0x07D8 + x"3A",x"26",x"80",x"FE",x"01",x"28",x"14",x"FE", -- 0x07E0 + x"02",x"28",x"24",x"3A",x"27",x"80",x"FE",x"44", -- 0x07E8 + x"28",x"3E",x"E6",x"01",x"20",x"49",x"CD",x"69", -- 0x07F0 + x"08",x"AF",x"C9",x"CD",x"10",x"05",x"C6",x"05" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.bin new file mode 100644 index 00000000..7cb06c57 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd new file mode 100644 index 00000000..6a72782a --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ROM_SND_1.vhd @@ -0,0 +1,284 @@ +-- generated with romgen by MikeJ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ROM_SND_1 is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(10 downto 0); + DATA : out std_logic_vector(7 downto 0) + ); +end; + +architecture RTL of ROM_SND_1 is + + + type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0); + constant ROM : ROM_ARRAY := ( + x"FE",x"0F",x"20",x"05",x"21",x"26",x"80",x"36", -- 0x0000 + x"00",x"47",x"CD",x"86",x"04",x"18",x"EA",x"CD", -- 0x0008 + x"10",x"05",x"D6",x"05",x"20",x"05",x"21",x"26", -- 0x0010 + x"80",x"36",x"00",x"47",x"CD",x"86",x"04",x"3A", -- 0x0018 + x"26",x"80",x"FE",x"00",x"20",x"D3",x"3A",x"27", -- 0x0020 + x"80",x"FE",x"44",x"20",x"CC",x"3E",x"FF",x"C9", -- 0x0028 + x"CD",x"7D",x"08",x"B7",x"20",x"02",x"18",x"C1", -- 0x0030 + x"21",x"26",x"80",x"36",x"02",x"18",x"BA",x"CD", -- 0x0038 + x"44",x"08",x"18",x"B5",x"CD",x"7D",x"08",x"B7", -- 0x0040 + x"C8",x"ED",x"5B",x"24",x"80",x"1A",x"32",x"23", -- 0x0048 + x"80",x"13",x"1A",x"6F",x"13",x"1A",x"67",x"13", -- 0x0050 + x"ED",x"53",x"24",x"80",x"CD",x"12",x"04",x"21", -- 0x0058 + x"27",x"80",x"34",x"21",x"26",x"80",x"36",x"01", -- 0x0060 + x"C9",x"CD",x"7D",x"08",x"B7",x"C8",x"3E",x"01", -- 0x0068 + x"32",x"23",x"80",x"21",x"27",x"80",x"34",x"21", -- 0x0070 + x"26",x"80",x"36",x"02",x"C9",x"21",x"22",x"80", -- 0x0078 + x"35",x"20",x"0C",x"3E",x"0B",x"77",x"21",x"23", -- 0x0080 + x"80",x"35",x"20",x"03",x"3E",x"FF",x"C9",x"AF", -- 0x0088 + x"C9",x"01",x"15",x"01",x"01",x"15",x"01",x"0B", -- 0x0090 + x"15",x"01",x"01",x"15",x"01",x"01",x"15",x"01", -- 0x0098 + x"03",x"15",x"01",x"03",x"4A",x"01",x"03",x"A0", -- 0x00A0 + x"01",x"03",x"4A",x"01",x"03",x"15",x"01",x"03", -- 0x00A8 + x"4A",x"01",x"03",x"15",x"01",x"03",x"D0",x"00", -- 0x00B0 + x"03",x"15",x"01",x"03",x"4A",x"01",x"03",x"A0", -- 0x00B8 + x"01",x"03",x"4A",x"01",x"03",x"15",x"01",x"03", -- 0x00C0 + x"4A",x"01",x"03",x"15",x"01",x"03",x"D0",x"00", -- 0x00C8 + x"0B",x"15",x"01",x"01",x"15",x"01",x"01",x"15", -- 0x00D0 + x"01",x"0B",x"15",x"01",x"01",x"15",x"01",x"01", -- 0x00D8 + x"15",x"01",x"0B",x"15",x"01",x"01",x"15",x"01", -- 0x00E0 + x"01",x"15",x"01",x"0B",x"15",x"01",x"01",x"15", -- 0x00E8 + x"01",x"01",x"15",x"01",x"20",x"15",x"01",x"3E", -- 0x00F0 + x"20",x"32",x"29",x"80",x"3E",x"08",x"32",x"2A", -- 0x00F8 + x"80",x"3E",x"FF",x"32",x"2B",x"80",x"AF",x"32", -- 0x0100 + x"2C",x"80",x"3E",x"0B",x"06",x"00",x"CD",x"0A", -- 0x0108 + x"05",x"3E",x"0C",x"06",x"20",x"CD",x"0A",x"05", -- 0x0110 + x"CD",x"EB",x"04",x"06",x"10",x"CD",x"86",x"04", -- 0x0118 + x"C9",x"3E",x"06",x"06",x"12",x"CD",x"0A",x"05", -- 0x0120 + x"3A",x"2C",x"80",x"FE",x"00",x"28",x"0C",x"FE", -- 0x0128 + x"01",x"28",x"16",x"21",x"2B",x"80",x"35",x"28", -- 0x0130 + x"2C",x"AF",x"C9",x"3E",x"0D",x"06",x"09",x"CD", -- 0x0138 + x"0A",x"05",x"3E",x"01",x"32",x"2C",x"80",x"18", -- 0x0140 + x"F0",x"21",x"29",x"80",x"35",x"20",x"EA",x"3E", -- 0x0148 + x"20",x"77",x"21",x"2A",x"80",x"35",x"20",x"07", -- 0x0150 + x"3E",x"02",x"32",x"2C",x"80",x"18",x"DA",x"AF", -- 0x0158 + x"32",x"2C",x"80",x"18",x"D4",x"3E",x"FF",x"C9", -- 0x0160 + x"3E",x"10",x"32",x"2E",x"80",x"21",x"F0",x"00", -- 0x0168 + x"CD",x"12",x"04",x"CD",x"58",x"04",x"06",x"0F", -- 0x0170 + x"CD",x"86",x"04",x"C9",x"21",x"2E",x"80",x"35", -- 0x0178 + x"20",x"0D",x"3E",x"10",x"77",x"CD",x"10",x"05", -- 0x0180 + x"3D",x"28",x"20",x"47",x"CD",x"86",x"04",x"CD", -- 0x0188 + x"35",x"04",x"B7",x"11",x"08",x"00",x"ED",x"52", -- 0x0190 + x"11",x"10",x"00",x"7C",x"BA",x"20",x"07",x"7D", -- 0x0198 + x"BB",x"20",x"03",x"21",x"F0",x"00",x"CD",x"12", -- 0x01A0 + x"04",x"AF",x"C9",x"3E",x"FF",x"C9",x"3E",x"08", -- 0x01A8 + x"32",x"30",x"80",x"3E",x"05",x"32",x"31",x"80", -- 0x01B0 + x"3E",x"0C",x"32",x"32",x"80",x"AF",x"32",x"33", -- 0x01B8 + x"80",x"21",x"50",x"00",x"CD",x"12",x"04",x"CD", -- 0x01C0 + x"58",x"04",x"06",x"00",x"CD",x"86",x"04",x"C9", -- 0x01C8 + x"3A",x"33",x"80",x"FE",x"00",x"28",x"18",x"FE", -- 0x01D0 + x"01",x"28",x"26",x"FE",x"02",x"28",x"27",x"FE", -- 0x01D8 + x"03",x"28",x"33",x"21",x"32",x"80",x"35",x"28", -- 0x01E0 + x"32",x"AF",x"32",x"33",x"80",x"AF",x"C9",x"CD", -- 0x01E8 + x"10",x"05",x"3C",x"FE",x"0F",x"20",x"04",x"21", -- 0x01F0 + x"33",x"80",x"34",x"47",x"CD",x"86",x"04",x"18", -- 0x01F8 + x"EC",x"CD",x"1E",x"0A",x"18",x"E7",x"CD",x"10", -- 0x0200 + x"05",x"3D",x"20",x"04",x"21",x"33",x"80",x"34", -- 0x0208 + x"47",x"CD",x"86",x"04",x"18",x"D7",x"CD",x"2B", -- 0x0210 + x"0A",x"18",x"D2",x"3E",x"FF",x"C9",x"21",x"30", -- 0x0218 + x"80",x"35",x"C0",x"3E",x"08",x"77",x"21",x"33", -- 0x0220 + x"80",x"34",x"C9",x"21",x"31",x"80",x"35",x"C0", -- 0x0228 + x"3E",x"05",x"77",x"21",x"33",x"80",x"34",x"C9", -- 0x0230 + x"3E",x"08",x"32",x"35",x"80",x"3E",x"01",x"32", -- 0x0238 + x"36",x"80",x"21",x"03",x"00",x"22",x"37",x"80", -- 0x0240 + x"AF",x"32",x"39",x"80",x"32",x"3A",x"80",x"21", -- 0x0248 + x"15",x"01",x"CD",x"12",x"04",x"CD",x"58",x"04", -- 0x0250 + x"06",x"0F",x"CD",x"86",x"04",x"C9",x"3A",x"39", -- 0x0258 + x"80",x"FE",x"01",x"28",x"14",x"FE",x"02",x"28", -- 0x0260 + x"24",x"3A",x"3A",x"80",x"FE",x"1C",x"28",x"3E", -- 0x0268 + x"E6",x"01",x"20",x"49",x"CD",x"E7",x"0A",x"AF", -- 0x0270 + x"C9",x"CD",x"10",x"05",x"C6",x"05",x"FE",x"0F", -- 0x0278 + x"20",x"05",x"21",x"39",x"80",x"36",x"00",x"47", -- 0x0280 + x"CD",x"86",x"04",x"18",x"EA",x"CD",x"10",x"05", -- 0x0288 + x"D6",x"01",x"20",x"05",x"21",x"39",x"80",x"36", -- 0x0290 + x"00",x"47",x"CD",x"86",x"04",x"3A",x"39",x"80", -- 0x0298 + x"FE",x"00",x"20",x"D3",x"3A",x"3A",x"80",x"FE", -- 0x02A0 + x"1C",x"20",x"CC",x"3E",x"FF",x"C9",x"CD",x"FB", -- 0x02A8 + x"0A",x"B7",x"20",x"02",x"18",x"C1",x"21",x"39", -- 0x02B0 + x"80",x"36",x"02",x"18",x"BA",x"CD",x"C2",x"0A", -- 0x02B8 + x"18",x"B5",x"CD",x"FB",x"0A",x"B7",x"C8",x"ED", -- 0x02C0 + x"5B",x"37",x"80",x"1A",x"32",x"36",x"80",x"13", -- 0x02C8 + x"1A",x"6F",x"13",x"1A",x"67",x"13",x"ED",x"53", -- 0x02D0 + x"37",x"80",x"CD",x"12",x"04",x"21",x"3A",x"80", -- 0x02D8 + x"34",x"21",x"39",x"80",x"36",x"01",x"C9",x"CD", -- 0x02E0 + x"FB",x"0A",x"B7",x"C8",x"3E",x"01",x"32",x"36", -- 0x02E8 + x"80",x"21",x"3A",x"80",x"34",x"21",x"39",x"80", -- 0x02F0 + x"36",x"02",x"C9",x"21",x"35",x"80",x"35",x"20", -- 0x02F8 + x"0C",x"3E",x"08",x"77",x"21",x"36",x"80",x"35", -- 0x0300 + x"20",x"03",x"3E",x"FF",x"C9",x"AF",x"C9",x"3E", -- 0x0308 + x"40",x"32",x"3C",x"80",x"3E",x"20",x"32",x"3D", -- 0x0310 + x"80",x"AF",x"32",x"3E",x"80",x"21",x"00",x"08", -- 0x0318 + x"CD",x"12",x"04",x"CD",x"58",x"04",x"06",x"0F", -- 0x0320 + x"CD",x"86",x"04",x"C9",x"3A",x"3E",x"80",x"FE", -- 0x0328 + x"00",x"28",x"20",x"FE",x"01",x"28",x"29",x"CD", -- 0x0330 + x"35",x"04",x"B7",x"11",x"20",x"00",x"ED",x"52", -- 0x0338 + x"11",x"00",x"02",x"7C",x"BA",x"20",x"07",x"7D", -- 0x0340 + x"BB",x"20",x"03",x"21",x"00",x"08",x"CD",x"12", -- 0x0348 + x"04",x"AF",x"C9",x"21",x"3C",x"80",x"35",x"20", -- 0x0350 + x"DE",x"3E",x"01",x"32",x"3E",x"80",x"18",x"D7", -- 0x0358 + x"21",x"3D",x"80",x"35",x"20",x"D1",x"3E",x"20", -- 0x0360 + x"77",x"CD",x"10",x"05",x"3D",x"28",x"06",x"47", -- 0x0368 + x"CD",x"86",x"04",x"18",x"C2",x"3E",x"FF",x"C9", -- 0x0370 + x"3E",x"05",x"32",x"40",x"80",x"21",x"50",x"00", -- 0x0378 + x"CD",x"12",x"04",x"CD",x"58",x"04",x"06",x"0F", -- 0x0380 + x"CD",x"86",x"04",x"C9",x"21",x"40",x"80",x"35", -- 0x0388 + x"20",x"0C",x"36",x"05",x"CD",x"10",x"05",x"3D", -- 0x0390 + x"28",x"06",x"47",x"CD",x"86",x"04",x"AF",x"C9", -- 0x0398 + x"3E",x"FF",x"C9",x"3E",x"04",x"32",x"42",x"80", -- 0x03A0 + x"3E",x"03",x"32",x"43",x"80",x"AF",x"32",x"44", -- 0x03A8 + x"80",x"CD",x"58",x"04",x"06",x"00",x"CD",x"86", -- 0x03B0 + x"04",x"C9",x"3A",x"44",x"80",x"FE",x"00",x"28", -- 0x03B8 + x"24",x"FE",x"01",x"28",x"31",x"CD",x"35",x"04", -- 0x03C0 + x"01",x"20",x"00",x"B7",x"09",x"CD",x"12",x"04", -- 0x03C8 + x"21",x"43",x"80",x"35",x"20",x"0D",x"36",x"03", -- 0x03D0 + x"CD",x"10",x"05",x"D6",x"03",x"28",x"23",x"47", -- 0x03D8 + x"CD",x"86",x"04",x"AF",x"C9",x"21",x"10",x"00", -- 0x03E0 + x"CD",x"12",x"04",x"06",x"0F",x"CD",x"86",x"04", -- 0x03E8 + x"21",x"44",x"80",x"34",x"18",x"ED",x"21",x"42", -- 0x03F0 + x"80",x"35",x"20",x"E7",x"21",x"44",x"80",x"34", -- 0x03F8 + x"18",x"E1",x"3E",x"FF",x"C9",x"3E",x"02",x"32", -- 0x0400 + x"46",x"80",x"3E",x"20",x"32",x"47",x"80",x"AF", -- 0x0408 + x"32",x"48",x"80",x"21",x"10",x"00",x"CD",x"12", -- 0x0410 + x"04",x"CD",x"58",x"04",x"06",x"00",x"CD",x"86", -- 0x0418 + x"04",x"C9",x"21",x"46",x"80",x"35",x"20",x"09", -- 0x0420 + x"36",x"02",x"CD",x"35",x"04",x"23",x"CD",x"12", -- 0x0428 + x"04",x"3A",x"48",x"80",x"FE",x"00",x"28",x"11", -- 0x0430 + x"FE",x"01",x"28",x"1F",x"21",x"47",x"80",x"35", -- 0x0438 + x"28",x"29",x"21",x"48",x"80",x"36",x"00",x"AF", -- 0x0440 + x"C9",x"CD",x"10",x"05",x"3C",x"FE",x"0F",x"20", -- 0x0448 + x"04",x"21",x"48",x"80",x"34",x"47",x"CD",x"86", -- 0x0450 + x"04",x"18",x"EC",x"CD",x"10",x"05",x"3D",x"20", -- 0x0458 + x"04",x"21",x"48",x"80",x"34",x"47",x"CD",x"86", -- 0x0460 + x"04",x"18",x"DC",x"3E",x"FF",x"C9",x"3E",x"03", -- 0x0468 + x"32",x"4A",x"80",x"21",x"00",x"04",x"22",x"4C", -- 0x0470 + x"80",x"AF",x"32",x"4B",x"80",x"21",x"00",x"02", -- 0x0478 + x"CD",x"12",x"04",x"CD",x"58",x"04",x"06",x"0A", -- 0x0480 + x"CD",x"86",x"04",x"C9",x"21",x"4A",x"80",x"35", -- 0x0488 + x"20",x"2E",x"36",x"03",x"CD",x"35",x"04",x"11", -- 0x0490 + x"20",x"00",x"19",x"ED",x"5B",x"4C",x"80",x"7C", -- 0x0498 + x"BA",x"20",x"18",x"7D",x"BB",x"20",x"14",x"3A", -- 0x04A0 + x"4B",x"80",x"B7",x"20",x"15",x"21",x"00",x"08", -- 0x04A8 + x"22",x"4C",x"80",x"3E",x"FF",x"32",x"4B",x"80", -- 0x04B0 + x"21",x"00",x"02",x"CD",x"12",x"04",x"AF",x"C9", -- 0x04B8 + x"AF",x"C9",x"21",x"00",x"04",x"22",x"4C",x"80", -- 0x04C0 + x"AF",x"32",x"4B",x"80",x"18",x"EA",x"3E",x"10", -- 0x04C8 + x"32",x"4F",x"80",x"AF",x"32",x"50",x"80",x"32", -- 0x04D0 + x"51",x"80",x"CD",x"58",x"04",x"06",x"00",x"CD", -- 0x04D8 + x"86",x"04",x"C9",x"3A",x"51",x"80",x"FE",x"00", -- 0x04E0 + x"CA",x"51",x"0D",x"FE",x"01",x"CA",x"5E",x"0D", -- 0x04E8 + x"FE",x"02",x"CA",x"69",x"0D",x"FE",x"03",x"CA", -- 0x04F0 + x"6F",x"0D",x"FE",x"04",x"CA",x"7A",x"0D",x"FE", -- 0x04F8 + x"05",x"CA",x"80",x"0D",x"FE",x"06",x"CA",x"8D", -- 0x0500 + x"0D",x"FE",x"07",x"CA",x"98",x"0D",x"FE",x"08", -- 0x0508 + x"CA",x"9E",x"0D",x"FE",x"09",x"CA",x"A9",x"0D", -- 0x0510 + x"FE",x"0A",x"CA",x"AF",x"0D",x"FE",x"0B",x"CA", -- 0x0518 + x"BC",x"0D",x"FE",x"0C",x"CA",x"C7",x"0D",x"FE", -- 0x0520 + x"0D",x"CA",x"CD",x"0D",x"FE",x"0E",x"CA",x"D8", -- 0x0528 + x"0D",x"FE",x"0F",x"CA",x"DE",x"0D",x"FE",x"10", -- 0x0530 + x"CA",x"EB",x"0D",x"FE",x"11",x"CA",x"F6",x"0D", -- 0x0538 + x"FE",x"12",x"CA",x"FC",x"0D",x"FE",x"13",x"CA", -- 0x0540 + x"07",x"0E",x"21",x"51",x"80",x"36",x"00",x"AF", -- 0x0548 + x"C9",x"21",x"E7",x"0B",x"CD",x"12",x"04",x"21", -- 0x0550 + x"51",x"80",x"34",x"C3",x"4F",x"0D",x"CD",x"0D", -- 0x0558 + x"0E",x"21",x"50",x"80",x"36",x"05",x"C3",x"4F", -- 0x0560 + x"0D",x"CD",x"21",x"0E",x"C3",x"4F",x"0D",x"CD", -- 0x0568 + x"17",x"0E",x"21",x"50",x"80",x"36",x"01",x"C3", -- 0x0570 + x"4F",x"0D",x"CD",x"21",x"0E",x"C3",x"4F",x"0D", -- 0x0578 + x"21",x"00",x"0A",x"CD",x"12",x"04",x"21",x"51", -- 0x0580 + x"80",x"34",x"C3",x"4F",x"0D",x"CD",x"0D",x"0E", -- 0x0588 + x"21",x"50",x"80",x"36",x"05",x"C3",x"4F",x"0D", -- 0x0590 + x"CD",x"21",x"0E",x"C3",x"4F",x"0D",x"CD",x"17", -- 0x0598 + x"0E",x"21",x"50",x"80",x"36",x"01",x"C3",x"4F", -- 0x05A0 + x"0D",x"CD",x"21",x"0E",x"C3",x"4F",x"0D",x"21", -- 0x05A8 + x"99",x"0A",x"CD",x"12",x"04",x"21",x"51",x"80", -- 0x05B0 + x"34",x"C3",x"4F",x"0D",x"CD",x"0D",x"0E",x"21", -- 0x05B8 + x"50",x"80",x"36",x"05",x"C3",x"4F",x"0D",x"CD", -- 0x05C0 + x"21",x"0E",x"C3",x"4F",x"0D",x"CD",x"17",x"0E", -- 0x05C8 + x"21",x"50",x"80",x"36",x"01",x"C3",x"4F",x"0D", -- 0x05D0 + x"CD",x"21",x"0E",x"C3",x"4F",x"0D",x"21",x"3B", -- 0x05D8 + x"0B",x"CD",x"12",x"04",x"21",x"51",x"80",x"34", -- 0x05E0 + x"C3",x"4F",x"0D",x"CD",x"0D",x"0E",x"21",x"50", -- 0x05E8 + x"80",x"36",x"05",x"C3",x"4F",x"0D",x"CD",x"21", -- 0x05F0 + x"0E",x"C3",x"4F",x"0D",x"CD",x"17",x"0E",x"21", -- 0x05F8 + x"50",x"80",x"36",x"01",x"C3",x"4F",x"0D",x"CD", -- 0x0600 + x"21",x"0E",x"C3",x"4F",x"0D",x"06",x"0A",x"CD", -- 0x0608 + x"86",x"04",x"21",x"51",x"80",x"34",x"C9",x"06", -- 0x0610 + x"00",x"CD",x"86",x"04",x"21",x"51",x"80",x"34", -- 0x0618 + x"C9",x"21",x"4F",x"80",x"35",x"C0",x"36",x"10", -- 0x0620 + x"21",x"50",x"80",x"35",x"C0",x"21",x"51",x"80", -- 0x0628 + x"34",x"C9",x"21",x"40",x"01",x"22",x"53",x"80", -- 0x0630 + x"11",x"01",x"00",x"ED",x"53",x"55",x"80",x"3E", -- 0x0638 + x"03",x"32",x"57",x"80",x"3E",x"20",x"32",x"58", -- 0x0640 + x"80",x"3E",x"40",x"32",x"59",x"80",x"32",x"5A", -- 0x0648 + x"80",x"AF",x"32",x"5B",x"80",x"CD",x"58",x"04", -- 0x0650 + x"06",x"00",x"CD",x"86",x"04",x"C9",x"3A",x"5B", -- 0x0658 + x"80",x"FE",x"00",x"28",x"29",x"FE",x"01",x"28", -- 0x0660 + x"31",x"FE",x"02",x"28",x"40",x"FE",x"03",x"28", -- 0x0668 + x"4F",x"FE",x"04",x"28",x"70",x"21",x"59",x"80", -- 0x0670 + x"35",x"20",x"11",x"3A",x"5A",x"80",x"32",x"59", -- 0x0678 + x"80",x"11",x"01",x"00",x"ED",x"53",x"55",x"80", -- 0x0680 + x"AF",x"32",x"5B",x"80",x"AF",x"C9",x"2A",x"53", -- 0x0688 + x"80",x"CD",x"12",x"04",x"21",x"5B",x"80",x"34", -- 0x0690 + x"18",x"F2",x"CD",x"10",x"05",x"C6",x"02",x"FE", -- 0x0698 + x"08",x"20",x"04",x"21",x"5B",x"80",x"34",x"47", -- 0x06A0 + x"CD",x"86",x"04",x"18",x"DF",x"CD",x"35",x"04", -- 0x06A8 + x"B7",x"ED",x"5B",x"55",x"80",x"ED",x"52",x"CD", -- 0x06B0 + x"12",x"04",x"21",x"5B",x"80",x"34",x"18",x"CC", -- 0x06B8 + x"21",x"57",x"80",x"35",x"20",x"0B",x"36",x"03", -- 0x06C0 + x"ED",x"5B",x"55",x"80",x"13",x"ED",x"53",x"55", -- 0x06C8 + x"80",x"21",x"58",x"80",x"35",x"20",x"08",x"36", -- 0x06D0 + x"20",x"21",x"5B",x"80",x"34",x"18",x"AD",x"21", -- 0x06D8 + x"5B",x"80",x"35",x"18",x"A7",x"CD",x"10",x"05", -- 0x06E0 + x"3D",x"20",x"04",x"21",x"5B",x"80",x"34",x"47", -- 0x06E8 + x"CD",x"86",x"04",x"18",x"97",x"21",x"20",x"01", -- 0x06F0 + x"22",x"53",x"80",x"11",x"01",x"00",x"ED",x"53", -- 0x06F8 + x"55",x"80",x"3E",x"03",x"32",x"57",x"80",x"3E", -- 0x0700 + x"20",x"32",x"58",x"80",x"3E",x"30",x"32",x"59", -- 0x0708 + x"80",x"32",x"5A",x"80",x"AF",x"32",x"5B",x"80", -- 0x0710 + x"CD",x"58",x"04",x"06",x"00",x"CD",x"86",x"04", -- 0x0718 + x"C9",x"C3",x"5E",x"0E",x"21",x"00",x"01",x"22", -- 0x0720 + x"53",x"80",x"11",x"01",x"00",x"ED",x"53",x"55", -- 0x0728 + x"80",x"3E",x"03",x"32",x"57",x"80",x"3E",x"20", -- 0x0730 + x"32",x"58",x"80",x"3E",x"20",x"32",x"59",x"80", -- 0x0738 + x"32",x"5A",x"80",x"AF",x"32",x"5B",x"80",x"CD", -- 0x0740 + x"58",x"04",x"06",x"00",x"CD",x"86",x"04",x"C9", -- 0x0748 + x"C3",x"5E",x"0E",x"3E",x"10",x"32",x"5D",x"80", -- 0x0750 + x"3E",x"03",x"32",x"5E",x"80",x"AF",x"32",x"5F", -- 0x0758 + x"80",x"21",x"E3",x"0F",x"22",x"60",x"80",x"21", -- 0x0760 + x"15",x"01",x"CD",x"12",x"04",x"CD",x"58",x"04", -- 0x0768 + x"06",x"0F",x"CD",x"86",x"04",x"C9",x"3A",x"5F", -- 0x0770 + x"80",x"FE",x"0A",x"20",x"08",x"CD",x"AA",x"0F", -- 0x0778 + x"B7",x"20",x"10",x"AF",x"C9",x"E6",x"01",x"28", -- 0x0780 + x"05",x"CD",x"BE",x"0F",x"18",x"F5",x"CD",x"96", -- 0x0788 + x"0F",x"18",x"F0",x"3E",x"FF",x"C9",x"CD",x"AA", -- 0x0790 + x"0F",x"B7",x"C8",x"3E",x"01",x"32",x"5E",x"80", -- 0x0798 + x"21",x"5F",x"80",x"34",x"06",x"00",x"CD",x"86", -- 0x07A0 + x"04",x"C9",x"21",x"5D",x"80",x"35",x"20",x"0C", -- 0x07A8 + x"3E",x"10",x"77",x"21",x"5E",x"80",x"35",x"20", -- 0x07B0 + x"03",x"3E",x"FF",x"C9",x"AF",x"C9",x"CD",x"AA", -- 0x07B8 + x"0F",x"B7",x"C8",x"ED",x"5B",x"60",x"80",x"1A", -- 0x07C0 + x"32",x"5E",x"80",x"13",x"1A",x"6F",x"13",x"1A", -- 0x07C8 + x"67",x"13",x"ED",x"53",x"60",x"80",x"CD",x"12", -- 0x07D0 + x"04",x"21",x"5F",x"80",x"34",x"06",x"0F",x"CD", -- 0x07D8 + x"86",x"04",x"C9",x"01",x"15",x"01",x"08",x"D0", -- 0x07E0 + x"00",x"03",x"15",x"01",x"01",x"D0",x"00",x"08", -- 0x07E8 + x"A5",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF" -- 0x07F8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR))); + end process; +end RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic13_1t.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic13_1t.bin new file mode 100644 index 00000000..c59be147 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic13_1t.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic14_2t.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic14_2t.bin new file mode 100644 index 00000000..9afe3845 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic14_2t.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic15_3t.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic15_3t.bin new file mode 100644 index 00000000..e74e9ee7 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic15_3t.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic16_4t.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic16_4t.bin new file mode 100644 index 00000000..3eb48ce8 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic16_4t.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic17_5t.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic17_5t.bin new file mode 100644 index 00000000..6c42a736 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic17_5t.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic18_6t.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic18_6t.bin new file mode 100644 index 00000000..c92fe220 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic18_6t.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic30_2c.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic30_2c.bin new file mode 100644 index 00000000..9bd5d920 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic30_2c.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic31_1c.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic31_1c.bin new file mode 100644 index 00000000..26dd1a0c Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic31_1c.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic55_2.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic55_2.bin new file mode 100644 index 00000000..7cb06c57 Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic55_2.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic56_1.bin b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic56_1.bin new file mode 100644 index 00000000..c7acec5e Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/ic56_1.bin differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/romgen.exe b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/romgen.exe new file mode 100644 index 00000000..4536903c Binary files /dev/null and b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/ROM/romgen.exe differ diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv new file mode 100644 index 00000000..7680c5ff --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/TheEnd.sv @@ -0,0 +1,198 @@ +//============================================================================ +// Arcade: The End +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module TheEnd +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "TheEnd;;", + "O2,Joystick Control,Upright,Normal;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +//////////////////// CLOCKS /////////////////// + +wire clk_sys; +wire pll_locked; + +pll pll +( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_sys), + .locked(pll_locked) +); + +reg ce_6, ce_star, ce_1p79; +always @(negedge clk_sys) begin + reg [2:0] div = 0; + reg [4:0] div179 = 0; + + div <= div + 1'd1; + if(div == 5) div <= 0; + + ce_6 <= (div == 0); + ce_star <= ((div == 3) | (div == 5)); + + ce_1p79 <= 0; + div179 <= div179 + 1'd1; + if(div179 == 19) begin + div179 <= 0; + ce_1p79 <= 1; + end +end + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [9:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [9:0] audio; +wire hsync,vsync; +assign LED = 1; +wire blankn = ~(hblank | vblank); +wire hblank, vblank; +wire hs, vs; +wire [2:0] r,b,g; + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_6), + .ce_pix_actual(ce_6), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r}), + .G({g,g}), + .B({b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + + + +keyboard keyboard( + .clk(clk_sys), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + +wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3]; +wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2]; +wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1]; +wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0]; + +wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4]; +wire m_start1 = kbjoy[1]; +wire m_start2 = kbjoy[2]; +wire m_coin = kbjoy[3]; +//wire m_bomb = kbjoy[8]; +//wire m_Serv = kbjoy[9]; + +scramble_top theend +( + .O_VIDEO_R(r), + .O_VIDEO_G(g), + .O_VIDEO_B(b), + .O_HSYNC(hs), + .O_VSYNC(vs), + .O_HBLANK(hblank), + .O_VBLANK(vblank), + .O_AUDIO(audio), + .button_in(~{m_start2, m_fire, m_coin, m_start1, m_right, m_left, m_down, m_up}), + .RESET(status[0] | status[6] | buttons[1]), + .clk(clk_sys), + .ena_star(ce_star), + .ena_6(ce_6), + .ena_1_79(ce_1p79) +); + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + + +endmodule diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd new file mode 100644 index 00000000..6ed2498a --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/YM2149_linmix_sep.vhd @@ -0,0 +1,574 @@ +-- changes for seperate audio outputs and enable now enables cpu access as well +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + O_CHAN : out std_logic_vector(1 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal cnt_div_t1 : std_logic_vector(3 downto 0); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process(RESET_L, CLK) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA = '1') then + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end if; + end process; + + p_wdata : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + elsif rising_edge(CLK) then + if (ENA = '1') then + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, reg, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + cnt_div_t1 <= cnt_div; + end if; + end process; + + p_audio_output : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_AUDIO <= (others => '0'); + O_CHAN <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + O_AUDIO <= dac_amp(7 downto 0); + O_CHAN <= cnt_div_t1(1 downto 0); + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then -- resync + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end if; + end process; +end architecture RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/build_id.v b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/build_id.v new file mode 100644 index 00000000..4e62f060 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171217" +`define BUILD_TIME "232358" diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd new file mode 100644 index 00000000..da01f6b4 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80.vhd @@ -0,0 +1,1080 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd new file mode 100644 index 00000000..43cea1b5 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_MCode.vhd @@ -0,0 +1,1944 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd new file mode 100644 index 00000000..42cf6105 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Pack.vhd @@ -0,0 +1,217 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd new file mode 100644 index 00000000..0c28ec21 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/cpu/T80sed.vhd @@ -0,0 +1,179 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0238 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80sed is + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80sed; + +architecture rtl of T80sed is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => 0, + IOWait => 1) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if ((TState = "001") or (TState = "010")) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/dac.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/dac.vhd new file mode 100644 index 00000000..47b2185e --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 10 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd new file mode 100644 index 00000000..78823ec4 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/dpram.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $ +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dpram is + +generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 +); +port ( + clk_a_i : in std_logic; + en_a_i : in std_logic; + we_i : in std_logic; + addr_a_i : in std_logic_vector(addr_width_g-1 downto 0); + data_a_i : in std_logic_vector(data_width_g-1 downto 0); + data_a_o : out std_logic_vector(data_width_g-1 downto 0); + clk_b_i : in std_logic; + addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_o : out std_logic_vector(data_width_g-1 downto 0) +); + +end dpram; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dpram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t; + +begin + + mem_a: process (clk_a_i) + begin + if rising_edge(clk_a_i) then + if we_i = '1' and en_a_i = '1' then + ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i; + data_a_o <= data_a_i; + else + data_a_o <= ram_q(to_integer(unsigned(addr_a_i))); + end if; + end if; + end process mem_a; + + mem_b: process (clk_b_i) + begin + if rising_edge(clk_b_i) then + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + end if; + end process mem_b; + +end rtl; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/hq2x.sv b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd new file mode 100644 index 00000000..d415d932 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/i82c55.vhd @@ -0,0 +1,686 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +entity I82C55 is + port ( + + I_ADDR : in std_logic_vector(1 downto 0); -- A1-A0 + I_DATA : in std_logic_vector(7 downto 0); -- D7-D0 + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_CS_L : in std_logic; + I_RD_L : in std_logic; + I_WR_L : in std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_PC : in std_logic_vector(7 downto 0); + O_PC : out std_logic_vector(7 downto 0); + O_PC_OE_L : out std_logic_vector(7 downto 0); + + RESET : in std_logic; + ENA : in std_logic; -- (CPU) clk enable + CLK : in std_logic + ); +end; + +architecture RTL of I82C55 is + + -- registers + signal bit_mask : std_logic_vector(7 downto 0); + signal r_porta : std_logic_vector(7 downto 0); + signal r_portb : std_logic_vector(7 downto 0); + signal r_portc : std_logic_vector(7 downto 0); + signal r_control : std_logic_vector(7 downto 0); + -- + signal porta_we : std_logic; + signal portb_we : std_logic; + signal porta_re : std_logic; + signal portb_re : std_logic; + -- + signal porta_we_t1 : std_logic; + signal portb_we_t1 : std_logic; + signal porta_re_t1 : std_logic; + signal portb_re_t1 : std_logic; + -- + signal porta_we_rising : boolean; + signal portb_we_rising : boolean; + signal porta_re_rising : boolean; + signal portb_re_rising : boolean; + -- + signal groupa_mode : std_logic_vector(1 downto 0); -- port a/c upper + signal groupb_mode : std_logic; -- port b/c lower + -- + signal porta_read : std_logic_vector(7 downto 0); + signal portb_read : std_logic_vector(7 downto 0); + signal portc_read : std_logic_vector(7 downto 0); + signal control_read : std_logic_vector(7 downto 0); + signal mode_clear : std_logic; + -- + signal a_inte1 : std_logic; + signal a_inte2 : std_logic; + signal b_inte : std_logic; + -- + signal a_intr : std_logic; + signal a_obf_l : std_logic; + signal a_ibf : std_logic; + signal a_ack_l : std_logic; + signal a_stb_l : std_logic; + signal a_ack_l_t1 : std_logic; + signal a_stb_l_t1 : std_logic; + -- + signal b_intr : std_logic; + signal b_obf_l : std_logic; + signal b_ibf : std_logic; + signal b_ack_l : std_logic; + signal b_stb_l : std_logic; + signal b_ack_l_t1 : std_logic; + signal b_stb_l_t1 : std_logic; + -- + signal a_ack_l_rising : boolean; + signal a_stb_l_rising : boolean; + signal b_ack_l_rising : boolean; + signal b_stb_l_rising : boolean; + -- + signal porta_ipreg : std_logic_vector(7 downto 0); + signal portb_ipreg : std_logic_vector(7 downto 0); +begin + -- + -- mode 0 - basic input/output + -- mode 1 - strobed input/output + -- mode 2/3 - bi-directional bus + -- + -- control word (write) + -- + -- D7 mode set flag 1 = active + -- D6..5 GROUPA mode selection (mode 0,1,2) + -- D4 GROUPA porta 1 = input, 0 = output + -- D3 GROUPA portc upper 1 = input, 0 = output + -- D2 GROUPB mode selection (mode 0 ,1) + -- D1 GROUPB portb 1 = input, 0 = output + -- D0 GROUPB portc lower 1 = input, 0 = output + -- + -- D7 bit set/reset 0 = active + -- D6..4 x + -- D3..1 bit select + -- d0 1 = set, 0 - reset + -- + -- all output registers including status are reset when mode is changed + --1. Port A: + --All Modes: Output data is cleared, input data is not cleared. + + --2. Port B: + --Mode 0: Output data is cleared, input data is not cleared. + --Mode 1 and 2: Both output and input data are cleared. + + --3. Port C: + --Mode 0:Output data is cleared, input data is not cleared. + --Mode 1 and 2: IBF and INTR are cleared and OBF# is set. + --Outputs in Port C which are not used for handshaking or interrupt signals are cleared. + --Inputs such as STB#, ACK#, or "spare" inputs are not affected. The interrupts for Ports A and B are disabled. + + p_bit_mask : process(I_DATA) + begin + bit_mask <= x"01"; + case I_DATA(3 downto 1) is + when "000" => bit_mask <= x"01"; + when "001" => bit_mask <= x"02"; + when "010" => bit_mask <= x"04"; + when "011" => bit_mask <= x"08"; + when "100" => bit_mask <= x"10"; + when "101" => bit_mask <= x"20"; + when "110" => bit_mask <= x"40"; + when "111" => bit_mask <= x"80"; + when others => null; + end case; + end process; + + p_write_reg_reset : process(RESET, CLK) + variable r_portc_masked : std_logic_vector(7 downto 0); + variable r_portc_setclr : std_logic_vector(7 downto 0); + begin + if (RESET = '1') then + r_porta <= x"00"; + r_portb <= x"00"; + r_portc <= x"00"; + r_control <= x"9B"; -- 10011011 + mode_clear <= '1'; + elsif rising_edge(CLK) then + + r_portc_masked := (not bit_mask) and r_portc; + for i in 0 to 7 loop + r_portc_setclr(i) := bit_mask(i) and I_DATA(0); + end loop; + + if (ENA = '1') then + mode_clear <= '0'; + if (I_CS_L = '0') and (I_WR_L = '0') then + case I_ADDR is + when "00" => r_porta <= I_DATA; + when "01" => r_portb <= I_DATA; + when "10" => r_portc <= I_DATA; + + when "11" => if (I_DATA(7) = '0') then -- set/clr + r_portc <= r_portc_masked or r_portc_setclr; + else + --mode_clear <= '1'; + --r_porta <= x"00"; + --r_portb <= x"00"; -- clear port b input reg + --r_portc <= x"00"; -- clear control sigs + r_control <= I_DATA; -- load new mode + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_decode_control : process(r_control) + begin + groupa_mode <= r_control(6 downto 5); + groupb_mode <= r_control(2); + end process; + + p_oe : process(I_CS_L, I_RD_L) + begin + O_DATA_OE_L <= '1'; + if (I_CS_L = '0') and (I_RD_L = '0') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(I_ADDR, porta_read, portb_read, portc_read, control_read) + begin + O_DATA <= x"00"; -- default + --if (I_CS_L = '0') and (I_RD_L = '0') then -- not required + case I_ADDR is + when "00" => O_DATA <= porta_read; + when "01" => O_DATA <= portb_read; + when "10" => O_DATA <= portc_read; + when "11" => O_DATA <= control_read; + when others => null; + end case; + --end if; + end process; + control_read(7) <= '1'; -- always 1 + control_read(6 downto 0) <= r_control(6 downto 0); + + p_rw_control : process(I_CS_L, I_RD_L, I_WR_L, I_ADDR) + begin + porta_we <= '0'; + portb_we <= '0'; + porta_re <= '0'; + portb_re <= '0'; + + if (I_CS_L = '0') and (I_ADDR = "00") then + porta_we <= not I_WR_L; + porta_re <= not I_RD_L; + end if; + + if (I_CS_L = '0') and (I_ADDR = "01") then + portb_we <= not I_WR_L; + portb_re <= not I_RD_L; + end if; + end process; + + p_rw_control_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + porta_we_t1 <= porta_we; + portb_we_t1 <= portb_we; + porta_re_t1 <= porta_re; + portb_re_t1 <= portb_re; + + a_stb_l_t1 <= a_stb_l; + a_ack_l_t1 <= a_ack_l; + b_stb_l_t1 <= b_stb_l; + b_ack_l_t1 <= b_ack_l; + end if; + end process; + + porta_we_rising <= (porta_we = '0') and (porta_we_t1 = '1'); -- falling as inverted + portb_we_rising <= (portb_we = '0') and (portb_we_t1 = '1'); -- " + porta_re_rising <= (porta_re = '0') and (porta_re_t1 = '1'); -- falling as inverted + portb_re_rising <= (portb_re = '0') and (portb_re_t1 = '1'); -- " + -- + a_stb_l_rising <= (a_stb_l = '1') and (a_stb_l_t1 = '0'); + a_ack_l_rising <= (a_ack_l = '1') and (a_ack_l_t1 = '0'); + b_stb_l_rising <= (b_stb_l = '1') and (b_stb_l_t1 = '0'); + b_ack_l_rising <= (b_ack_l = '1') and (b_ack_l_t1 = '0'); + -- + -- GROUP A + -- in mode 1 + -- + -- d4=1 (porta = input) + -- pc7,6 io (d3=1 input, d3=0 output) + -- pc5 output a_ibf + -- pc4 input a_stb_l + -- pc3 output a_intr + -- + -- d4=0 (porta = output) + -- pc7 output a_obf_l + -- pc6 input a_ack_l + -- pc5,4 io (d3=1 input, d3=0 output) + -- pc3 output a_intr + -- + -- GROUP B + -- in mode 1 + -- d1=1 (portb = input) + -- pc2 input b_stb_l + -- pc1 output b_ibf + -- pc0 output b_intr + -- + -- d1=0 (portb = output) + -- pc2 input b_ack_l + -- pc1 output b_obf_l + -- pc0 output b_intr + + + -- WHEN AN INPUT + -- + -- stb_l a low on this input latches input data + -- ibf a high on this output indicates data latched. set by stb_l and reset by rising edge of RD_L + -- intr a high on this output indicates interrupt. set by stb_l high, ibf high and inte high. reset by falling edge of RD_L + -- inte A controlled by bit/set PC4 + -- inte B controlled by bit/set PC2 + + -- WHEN AN OUTPUT + -- + -- obf_l output will go low when cpu has written data + -- ack_l input - a low on this clears obf_l + -- intr output set when ack_l is high, obf_l is high and inte is one. reset by falling edge of WR_L + -- inte A controlled by bit/set PC6 + -- inte B controlled by bit/set PC2 + + -- GROUP A + -- in mode 2 + -- + -- porta = IO + -- + -- control bits 2..0 still control groupb/c lower 2..0 + -- + -- + -- PC7 output a_obf + -- PC6 input a_ack_l + -- PC5 output a_ibf + -- PC4 input a_stb_l + -- PC3 is still interrupt out + p_control_flags : process(RESET, CLK) + variable we : boolean; + variable set1 : boolean; + variable set2 : boolean; + begin + if (RESET = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + elsif rising_edge(CLK) then + we := (I_CS_L = '0') and (I_WR_L = '0') and (I_ADDR = "11") and (I_DATA(7) = '0'); + + if (ENA = '1') then + if (mode_clear = '1') then + a_obf_l <= '1'; + a_inte1 <= '0'; + a_ibf <= '0'; + a_inte2 <= '0'; + a_intr <= '0'; + -- + b_inte <= '0'; + b_obf_l <= '1'; + b_ibf <= '0'; + b_intr <= '0'; + else + if (bit_mask(7) = '1') and we then + a_obf_l <= I_DATA(0); + else + if porta_we_rising then + a_obf_l <= '0'; + elsif (a_ack_l = '0') then + a_obf_l <= '1'; + end if; + end if; + -- + if (bit_mask(6) = '1') and we then a_inte1 <= I_DATA(0); end if; -- bus set when mode1 & input? + -- + if (bit_mask(5) = '1') and we then + a_ibf <= I_DATA(0); + else + if porta_re_rising then + a_ibf <= '0'; + elsif (a_stb_l = '0') then + a_ibf <= '1'; + end if; + end if; + -- + if (bit_mask(4) = '1') and we then a_inte2 <= I_DATA(0); end if; -- bus set when mode1 & output? + -- + set1 := a_ack_l_rising and (a_obf_l = '1') and (a_inte1 = '1'); + set2 := a_stb_l_rising and (a_ibf = '1') and (a_inte2 = '1'); + -- + if (bit_mask(3) = '1') and we then + a_intr <= I_DATA(0); + else + if (groupa_mode(1) = '1') then + if (porta_we = '1') or (porta_re = '1') then + a_intr <= '0'; + elsif set1 or set2 then + a_intr <= '1'; + end if; + else + if (r_control(4) = '0') then -- output + if (porta_we = '1') then -- falling ? + a_intr <= '0'; + elsif set1 then + a_intr <= '1'; + end if; + elsif (r_control(4) = '1') then -- input + if (porta_re = '1') then -- falling ? + a_intr <= '0'; + elsif set2 then + a_intr <= '1'; + end if; + end if; + end if; + end if; + -- + if (bit_mask(2) = '1') and we then b_inte <= I_DATA(0); end if; -- bus set? + + if (bit_mask(1) = '1') and we then + b_obf_l <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if portb_we_rising then + b_obf_l <= '0'; + elsif (b_ack_l = '0') then + b_obf_l <= '1'; + end if; + else + if portb_re_rising then + b_ibf <= '0'; + elsif (b_stb_l = '0') then + b_ibf <= '1'; + end if; + end if; + end if; + + if (bit_mask(0) = '1') and we then + b_intr <= I_DATA(0); + else + if (r_control(1) = '0') then -- output + if (portb_we = '1') then -- falling ? + b_intr <= '0'; + elsif b_ack_l_rising and (b_obf_l = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + else + if (portb_re = '1') then -- falling ? + b_intr <= '0'; + elsif b_stb_l_rising and (b_ibf = '1') and (b_inte = '1') then + b_intr <= '1'; + end if; + end if; + end if; + + end if; + end if; + end if; + end process; + + p_porta : process(r_control, groupa_mode, r_porta, I_PA, porta_ipreg, a_ack_l) + begin + -- D4 GROUPA porta 1 = input, 0 = output + O_PA <= x"FF"; -- if not driven, float high + O_PA_OE_L <= x"FF"; + porta_read <= x"00"; + + if (groupa_mode = "00") then -- simple io + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= I_PA; + elsif (groupa_mode = "01") then -- strobed + if (r_control(4) = '0') then -- output + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; + else -- if (groupa_mode(1) = '1') then -- bi dir + if (a_ack_l = '0') then -- output enable + O_PA <= r_porta; + O_PA_OE_L <= x"00"; + end if; + porta_read <= porta_ipreg; -- latched data + end if; + + end process; + + p_portb : process(r_control, groupb_mode, r_portb, I_PB, portb_ipreg) + begin + O_PB <= x"FF"; -- if not driven, float high + O_PB_OE_L <= x"FF"; + portb_read <= x"00"; + + if (groupb_mode = '0') then -- simple io + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= I_PB; + else -- strobed mode + if (r_control(1) = '0') then -- output + O_PB <= r_portb; + O_PB_OE_L <= x"00"; + end if; + portb_read <= portb_ipreg; + end if; + end process; + + p_portc_out : process(r_portc, r_control, groupa_mode, groupb_mode, + a_obf_l, a_ibf, a_intr,b_obf_l, b_ibf, b_intr) + begin + O_PC <= x"FF"; -- if not driven, float high + O_PC_OE_L <= x"FF"; + + -- bits 7..4 + if (groupa_mode = "00") then -- simple io + if (r_control(3) = '0') then -- output + O_PC (7 downto 4) <= r_portc(7 downto 4); + O_PC_OE_L(7 downto 4) <= x"0"; + end if; + elsif (groupa_mode = "01") then -- mode1 + + if (r_control(4) = '0') then -- port a output + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + if (r_control(3) = '0') then -- port c output + O_PC (5 downto 4) <= r_portc(5 downto 4); + O_PC_OE_L(5 downto 4) <= "00"; + end if; + else -- port a input + if (r_control(3) = '0') then -- port c output + O_PC (7 downto 6) <= r_portc(7 downto 6); + O_PC_OE_L(7 downto 6) <= "00"; + end if; + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + else -- if (groupa_mode(1) = '1') then -- mode2 + O_PC (7) <= a_obf_l; + O_PC_OE_L(7) <= '0'; + -- 6 is ack_l input + O_PC (5) <= a_ibf; + O_PC_OE_L(5) <= '0'; + -- 4 is stb_l input + end if; + + -- bit 3 (controlled by group a) + if (groupa_mode = "00") then -- group a steals this bit + --if (groupb_mode = '0') then -- we will let bit 3 be driven, data sheet is a bit confused about this + if (r_control(0) = '0') then -- ouput (note, groupb control bit) + O_PC (3) <= r_portc(3); + O_PC_OE_L(3) <= '0'; + end if; + -- + else -- stolen + O_PC (3) <= a_intr; + O_PC_OE_L(3) <= '0'; + end if; + + -- bits 2..0 + if (groupb_mode = '0') then -- simple io + if (r_control(0) = '0') then -- output + O_PC (2 downto 0) <= r_portc(2 downto 0); + O_PC_OE_L(2 downto 0) <= "000"; + end if; + else + -- mode 1 + -- 2 is input + if (r_control(1) = '0') then -- output + O_PC (1) <= b_obf_l; + O_PC_OE_L(1) <= '0'; + else -- input + O_PC (1) <= b_ibf; + O_PC_OE_L(1) <= '0'; + end if; + O_PC (0) <= b_intr; + O_PC_OE_L(0) <= '0'; + end if; + end process; + + p_portc_in : process(r_portc, I_PC, r_control, groupa_mode, groupb_mode, a_ibf, b_obf_l, + a_obf_l, a_inte1, a_inte2, a_intr, b_inte, b_ibf, b_intr) + begin + portc_read <= x"00"; + + a_stb_l <= '1'; + a_ack_l <= '1'; + b_stb_l <= '1'; + b_ack_l <= '1'; + + if (groupa_mode = "01") then -- mode1 or 2 + if (r_control(4) = '0') then -- port a output + a_ack_l <= I_PC(6); + else -- port a input + a_stb_l <= I_PC(4); + end if; + elsif (groupa_mode(1) = '1') then -- mode 2 + a_ack_l <= I_PC(6); + a_stb_l <= I_PC(4); + end if; + + if (groupb_mode = '1') then + if (r_control(1) = '0') then -- output + b_ack_l <= I_PC(2); + else -- input + b_stb_l <= I_PC(2); + end if; + end if; + + if (groupa_mode = "00") then -- simple io + portc_read(7 downto 3) <= I_PC(7 downto 3); + elsif (groupa_mode = "01") then + if (r_control(4) = '0') then -- port a output + portc_read(7 downto 3) <= a_obf_l & a_inte1 & I_PC(5 downto 4) & a_intr; + else -- input + portc_read(7 downto 3) <= I_PC(7 downto 6) & a_ibf & a_inte2 & a_intr; + end if; + else -- mode 2 + portc_read(7 downto 3) <= a_obf_l & a_inte1 & a_ibf & a_inte2 & a_intr; + end if; + + if (groupb_mode = '0') then -- simple io + portc_read(2 downto 0) <= I_PC(2 downto 0); + else + if (r_control(1) = '0') then -- output + portc_read(2 downto 0) <= b_inte & b_obf_l & b_intr; + else -- input + portc_read(2 downto 0) <= b_inte & b_ibf & b_intr; + end if; + end if; + end process; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- pc4 input a_stb_l + -- pc2 input b_stb_l + + if (ENA = '1') then + if (a_stb_l = '0') then + porta_ipreg <= I_PA; + end if; + + if (mode_clear = '1') then + portb_ipreg <= (others => '0'); + elsif (b_stb_l = '0') then + portb_ipreg <= I_PB; + end if; + end if; + end process; + +end architecture RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/keyboard.v b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/keyboard.v new file mode 100644 index 00000000..c2b7b86e --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[9:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space + 'h11: joystick[8] <= ~release_btn; // Left Alt + 'h0d: joystick[9] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/mist_io.v b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/osd.v b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/pll.qip b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/pll.v b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/pll.v new file mode 100644 index 00000000..4bec713f --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 3, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 4, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scandoubler.v b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..36e71ed2 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scandoubler.v @@ -0,0 +1,194 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd new file mode 100644 index 00000000..dcca3248 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble.vhd @@ -0,0 +1,585 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE is + port ( + I_HWSEL_FROGGER : in boolean; + -- + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(2 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + -- + -- to audio board + -- + O_ADDR : out std_logic_vector(15 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + I_DATA_OE_L : in std_logic; + O_RD_L : out std_logic; + O_WR_L : out std_logic; + O_IOPC7 : out std_logic; + O_RESET_WD_L : out std_logic; + -- + ENA : in std_logic; + ENA_STAR : in std_logic; + -- + RESET : in std_logic; -- active high + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE is + + type array_4x8 is array (0 to 3) of std_logic_vector(7 downto 0); + -- timing + signal hcnt : std_logic_vector(8 downto 0) := "010000000"; -- 80 + signal vcnt : std_logic_vector(8 downto 0) := "011111000"; -- 0F8 + + signal reset_wd_l : std_logic; + + -- timing decode + signal do_hsync : boolean; + signal set_vblank : boolean; + signal vsync : std_logic; + signal hsync : std_logic; + signal vblank : std_logic; + signal hblank : std_logic; + -- + -- cpu + signal cpu_ena : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + + signal page_4to7_l : std_logic; + + signal wren : std_logic; + + signal objen_l : std_logic; + signal waen_l : std_logic; + + signal objramrd_l : std_logic; + signal vramrd_l : std_logic; + + signal select_l : std_logic; + signal objramwr_l : std_logic; + signal vramwr_l : std_logic; + + -- control reg + signal control_reg : std_logic_vector(7 downto 0); + signal intst_l : std_logic; + signal iopc7 : std_logic; + signal pout1 : std_logic; + signal starson : std_logic; + signal hcma : std_logic; + signal vcma : std_logic; + + signal pgm_rom_dout : array_4x8; + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + signal ram_ena : std_logic; + + signal vram_data : std_logic_vector(7 downto 0); + +begin + + O_HBLANK <= hblank; + O_VBLANK <= vblank; + + -- + -- video timing + -- + p_hvcnt : process + variable hcarry,vcarry : boolean; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + hcarry := (hcnt = "111111111"); + if hcarry then + hcnt <= "010000000"; -- 080 + else + hcnt <= hcnt +"1"; + end if; + -- hcnt 8 on circuit is 256H_L + vcarry := (vcnt = "111111111"); + if do_hsync then + if vcarry then + vcnt <= "011111000"; -- 0F8 + else + vcnt <= vcnt +"1"; + end if; + end if; + end if; + end process; + + p_sync_comb : process(hcnt, vcnt) + begin + vsync <= not vcnt(8); + do_hsync <= (hcnt = "010101111"); -- 0AF + set_vblank <= (vcnt = "111101111"); -- 1EF + end process; + + p_sync : process + begin + wait until rising_edge(CLK); + -- Timing hardware is coded differently to the real hw + -- to avoid the use of multiple clocks. Result is identical. + if (ENA = '1') then + if (hcnt = "010001001") then -- 081 + hblank <= '1'; + elsif (hcnt = "011111111") then -- 0f9 + hblank <= '0'; + end if; + + if do_hsync then + hsync <= '1'; + elsif (hcnt = "011001111") then -- 0CF + hsync <= '0'; + end if; + + if do_hsync then + if set_vblank then -- 1EF + vblank <= '1'; + elsif (vcnt = "100001111") then -- 10F + vblank <= '0'; + end if; + end if; + end if; + end process; + + p_video_timing_reg : process + begin + wait until rising_edge(CLK); + -- match output delay in video module + if (ENA = '1') then + O_HSYNC <= HSYNC; + O_VSYNC <= VSYNC; + end if; + end process; + + p_cpu_ena : process(hcnt, ENA) + begin + -- cpu clocked on rising edge of 1h, late + cpu_ena <= ENA and hcnt(0); -- 1h + end process; + -- + -- video + -- + u_video : entity work.SCRAMBLE_VIDEO + port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_HCNT => hcnt, + I_VCNT => vcnt, + I_VBLANK => vblank, + I_VSYNC => vsync, + + I_VCMA => vcma, + I_HCMA => hcma, + -- + I_CPU_ADDR => cpu_addr, + I_CPU_DATA => cpu_data_out, + O_VRAM_DATA => vram_data, + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L => vramwr_l, + I_VRAMRD_L => vramrd_l, + I_OBJRAMWR_L => objramwr_l, + I_OBJRAMRD_L => objramrd_l, + I_OBJEN_L => objen_l, + -- + I_STARSON => starson, + I_POUT1 => pout1, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + -- + ENA => ENA, + ENA_STAR => ENA_STAR, + CLK => CLK + ); + + -- other cpu signals + reset_wd_l <= not RESET; -- FIX + + p_cpu_wait : process(vblank, hblank, waen_l) + begin + -- this is done a bit differently, the original had a late + -- clock to the cpu, and as mreq came out a litle early it could assert + -- wait and then gate off the write strobe to vram/objram in time. + -- + -- we are a nice synchronous system therefore we need to do this combinatorially. + -- timing is still ok. + -- + if (vblank = '1') then + cpu_wait_l <='1'; + else + cpu_wait_l <= '1'; + if (hblank = '0') and (waen_l = '0') then + cpu_wait_l <= '0'; + end if; + end if; + end process; + wren <= cpu_wait_l; + + p_cpu_int : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (intst_l = '0') then + cpu_nmi_l <= '1'; + else + if do_hsync and set_vblank then + cpu_nmi_l <= '0'; + end if; + end if; + end if; + end process; + + u_cpu : entity work.T80sed + port map ( + RESET_n => reset_wd_l, + CLK_n => clk, + CLKEN => cpu_ena, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => open, + MREQ_n => cpu_mreq_l, + IORQ_n => open, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + -- + -- primary addr decode + -- + p_mem_decode : process(cpu_rfsh_l, cpu_rd_l, cpu_wr_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + begin + -- Scramble map + --0000-3fff ROM + --4000-47ff RAM + --4800-4bff Video RAM + --5000-50ff Object RAM + --5000-503f screen attributes + --5040-505f sprites + --5060-507f bullets + --5080-50ff unused? + + --read: + --7000 Watchdog Reset (Scramble) + --8100 IN0 + --8101 IN1 + --8102 IN2 (bits 5 and 7 used for protection check in Scramble) + + --write: + --6800-6807 control reg + --8200 To AY-3-8910 port A (commands for the audio CPU) + --8201 bit 3 = interrupt trigger on audio CPU bit 4 = AMPM (?) + --8202 protection check control? + + -- Frogger map + --0000-3fff ROM + --8000-87ff RAM + --a800-abff Video RAM + --b000-b0ff Object RAM + --b000-b03f screen attributes + --b040-b05f sprites + --b060-b0ff unused? + + --read: + --8800 Watchdog Reset + --e000 IN0 + --e002 IN1 + --e004 IN2 + cpu_int_l <= '1'; + cpu_busrq_l <= '1'; + + page_4to7_l <= '1'; + if (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + + if I_HWSEL_FROGGER then + cpu_int_l <= '0'; + cpu_busrq_l <= cpu_addr(15); + end if; + + if not I_HWSEL_FROGGER then + if (cpu_addr(15 downto 14) = "01") then page_4to7_l <= '0'; end if; + else + if (cpu_addr(15 downto 14) = "10") then page_4to7_l <= '0'; end if; + end if; + end if; + + end process; + + p_mem_decode2 : process(I_HWSEL_FROGGER, cpu_addr, page_4to7_l, cpu_rfsh_l, cpu_rd_l, cpu_wr_l, wren) + begin + waen_l <= '1'; + objen_l <= '1'; + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "001") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objen_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(13 downto 11) = "101") then waen_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objen_l <= '0'; end if; + end if; + end if; + + -- read decode + vramrd_l <= '1'; + objramrd_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "001") then vramrd_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramrd_l <= '0'; end if; + end if; + else + if (page_4to7_l = '0') and (cpu_rd_l = '0') then + if (cpu_addr(13 downto 11) = "101") then vramrd_l <= '0'; end if; + end if; + end if; + -- write decode + vramwr_l <= '1'; + objramwr_l <= '1'; + select_l <= '1'; + + if not I_HWSEL_FROGGER then + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "001") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "010") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "101") then select_l <= '0'; end if; -- control reg + end if; + else + if (page_4to7_l = '0') and (cpu_wr_l = '0') and (wren = '1') then + if (cpu_addr(13 downto 11) = "101") then vramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "110") then objramwr_l <= '0'; end if; + if (cpu_addr(13 downto 11) = "111") then select_l <= '0'; end if; -- control reg + end if; + end if; + end process; + + p_control_reg : process + variable addr : std_logic_vector(2 downto 0); + variable dec : std_logic_vector(7 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- scramble + --6801 interrupt enable + --6802 coin counter + --6803 ? (POUT1) + --6804 stars on + --6805 ? (POUT2) + --6806 screen vertical flip + --6807 screen horizontal flip + if not I_HWSEL_FROGGER then + addr := cpu_addr(2 downto 0); + else + addr := cpu_addr(4 downto 2); + end if; + + dec := "00000000"; + if (select_l = '0') then + case addr(2 downto 0) is + when "000" => dec := "00000001"; + when "001" => dec := "00000010"; + when "010" => dec := "00000100"; + when "011" => dec := "00001000"; + when "100" => dec := "00010000"; + when "101" => dec := "00100000"; + when "110" => dec := "01000000"; + when "111" => dec := "10000000"; + when others => null; + end case; + end if; + + if (reset_wd_l = '0') then + control_reg <= (others => '0'); + else + for i in 0 to 7 loop + if (dec(i) = '1') then + control_reg(i) <= cpu_data_out(0); + end if; + end loop; + end if; + end if; + end process; + + p_control_reg_assign : process(control_reg, I_HWSEL_FROGGER) + begin + if not I_HWSEL_FROGGER then + -- Scramble + intst_l <= control_reg(1); + iopc7 <= control_reg(2); + pout1 <= control_reg(3); + starson <= control_reg(4); + hcma <= control_reg(6); + vcma <= control_reg(7); + else + intst_l <= control_reg(2); + iopc7 <= control_reg(6); + pout1 <= control_reg(7); + starson <= '0'; + hcma <= control_reg(4); + vcma <= control_reg(3); + end if; + end process; + -- + -- + -- roms / rams + pgm_rom : entity work.ROM_PGM + port map (CLK => CLK, ADDR => cpu_addr(13 downto 0), DATA => rom_dout); +-- pgm_rom01 : entity work.ROM_PGM_01 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(0)); +-- pgm_rom23 : entity work.ROM_PGM_23 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(1)); +-- pgm_rom45 : entity work.ROM_PGM_45 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(2)); +-- pgm_rom56 : entity work.ROM_PGM_67 +-- port map (CLK => CLK, ENA => ENA, ADDR => cpu_addr(11 downto 0), DATA => pgm_rom_dout(3)); + +-- p_rom_mux : process(cpu_addr, pgm_rom_dout) +-- begin +-- rom_dout <= (others => '0'); +-- case cpu_addr(13 downto 12) is +-- when "00" => rom_dout <= pgm_rom_dout(0); +-- when "01" => rom_dout <= pgm_rom_dout(1); +-- when "10" => rom_dout <= pgm_rom_dout(2); +-- when "11" => rom_dout <= pgm_rom_dout(3); +-- when others => null; +-- end case; +-- end process; + + u_cpu_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => ram_ena and (not cpu_wr_l), + + addr_a_i => cpu_addr(10 downto 0), + data_a_i => cpu_data_out, + + clk_b_i => clk, + addr_b_i => cpu_addr(10 downto 0), + data_b_o => ram_dout + ); + + p_ram_ctrl : process(cpu_addr, page_4to7_l) + begin + ram_ena <= '0'; + if (page_4to7_l = '0') and (cpu_addr(13 downto 11) = "000") then + ram_ena <= '1'; + end if; + end process; + + p_cpu_data_in_mux : process(I_HWSEL_FROGGER, cpu_addr, cpu_rd_l, cpu_mreq_l, cpu_rfsh_l, ram_dout, rom_dout, vramrd_l, vram_data, I_DATA_OE_L, I_DATA ) + variable ram_addr : std_logic_vector(1 downto 0); + begin + + if not I_HWSEL_FROGGER then + ram_addr := "01"; + else + ram_addr := "10"; + end if; + + cpu_data_in <= (others => '0'); + if (vramrd_l = '0') then + cpu_data_in <= vram_data; + -- + elsif (I_DATA_OE_L = '0') then + cpu_data_in <= I_DATA; + -- + elsif (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + if (cpu_addr(15 downto 14) = "00") and (cpu_rd_l = '0') and (cpu_mreq_l = '0') and (cpu_rfsh_l = '1') then + cpu_data_in <= rom_dout; + -- + elsif (cpu_addr(15 downto 14) = ram_addr) then + if (cpu_addr(13 downto 11) = "000") and (cpu_rd_l = '0') then + cpu_data_in <= ram_dout; + else + cpu_data_in <= x"FF"; + end if; + end if; + else + cpu_data_in <= x"FF"; + end if; + + end process; + + -- to audio + O_ADDR <= cpu_addr; + O_DATA <= cpu_data_out; + O_RD_L <= cpu_rd_l; + O_WR_L <= cpu_wr_l; + O_IOPC7 <= iopc7; + O_RESET_WD_L <= reset_wd_l; + +end RTL; \ No newline at end of file diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd new file mode 100644 index 00000000..57684539 --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_audio.vhd @@ -0,0 +1,842 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_AUDIO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_ADDR : in std_logic_vector(15 downto 0); + I_DATA : in std_logic_vector( 7 downto 0); + O_DATA : out std_logic_vector( 7 downto 0); + O_DATA_OE_L : out std_logic; + -- + I_RD_L : in std_logic; + I_WR_L : in std_logic; + I_IOPC7 : in std_logic; + -- + O_AUDIO : out std_logic_vector( 9 downto 0); + -- + I_1P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL : in std_logic_vector( 6 downto 0); -- start, shoot1, shoot2, left,right,up,down + I_SERVICE : in std_logic; + I_COIN1 : in std_logic; + I_COIN2 : in std_logic; + O_COIN_COUNTER : out std_logic; + -- + I_DIP : in std_logic_vector( 5 downto 1); + -- + I_RESET_L : in std_logic; + ENA : in std_logic; -- 6 MHz + ENA_1_79 : in std_logic; -- 1.78975 MHz + CLK : in std_logic + ); +end; + +architecture RTL of SCRAMBLE_AUDIO is + + signal reset : std_logic; + signal cpu_ena : std_logic; + signal cpu_ena_gated : std_logic; + -- + signal cpu_m1_l : std_logic; + signal cpu_mreq_l : std_logic; + signal cpu_iorq_l : std_logic; + signal cpu_rd_l : std_logic; + signal cpu_wr_l : std_logic; + signal cpu_rfsh_l : std_logic; + signal cpu_wait_l : std_logic; + signal cpu_int_l : std_logic; + signal cpu_nmi_l : std_logic; + signal cpu_busrq_l : std_logic; + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_data_out : std_logic_vector(7 downto 0); + signal cpu_data_in : std_logic_vector(7 downto 0); + -- + signal ram_cs : std_logic; + signal rom_oe : std_logic; + signal filter_load : std_logic; + signal filter_reg : std_logic_vector(11 downto 0); + -- + signal cpu_rom0_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom1_dout : std_logic_vectoR(7 downto 0); + signal cpu_rom2_dout : std_logic_vectoR(7 downto 0); + signal rom_active : std_logic; + + signal rom_dout : std_logic_vector(7 downto 0); + signal ram_dout : std_logic_vector(7 downto 0); + -- + signal i8255_addr : std_logic_vector(1 downto 0); + signal i8255_1D_data : std_logic_vector(7 downto 0); + signal i8255_1D_data_oe_l : std_logic; + signal i8255_1D_cs_l : std_logic; + signal i8255_1D_pa_out : std_logic_vector(7 downto 0); + signal i8255_1D_pb_out : std_logic_vector(7 downto 0); + -- + signal i8255_1E_data : std_logic_vector(7 downto 0); + signal i8255_1E_data_oe_l : std_logic; + signal i8255_1E_cs_l : std_logic; + signal i8255_1E_pa : std_logic_vector(7 downto 0); + signal i8255_1E_pb : std_logic_vector(7 downto 0); + signal i8255_1E_pc : std_logic_vector(7 downto 0); + + -- security + signal net_1e10_i : std_logic; + signal net_1e12_i : std_logic; + signal xb : std_logic_vector(7 downto 0); + signal xbo : std_logic_vector(7 downto 0); + + signal audio_div_cnt : std_logic_vector( 8 downto 0) := (others => '0'); + signal ls90_op : std_logic_vector(3 downto 0); + signal ls90_clk : std_logic; + signal ls90_cnt : std_logic_vector( 3 downto 0) := (others => '0'); + -- ym2149 3C + signal ym2149_3C_dv : std_logic_vector(7 downto 0); + signal ym2149_3C_oe_l : std_logic; + signal ym2149_3C_bdir : std_logic; + signal ym2149_3C_bc2 : std_logic; + signal ym2149_3C_bc1 : std_logic; + signal ym2149_3C_audio : std_logic_vector(7 downto 0); + signal ym2149_3C_chan : std_logic_vector(1 downto 0); + signal ym2149_3C_chan_t1 : std_logic_vector(1 downto 0); + -- + -- ym2149 3D + signal ym2149_3D_dv : std_logic_vector(7 downto 0); + signal ym2149_3D_oe_l : std_logic; + signal ym2149_3D_bdir : std_logic; + signal ym2149_3D_bc2 : std_logic; + signal ym2149_3D_bc1 : std_logic; + signal ym2149_3D_audio : std_logic_vector(7 downto 0); + signal ym2149_3D_chan : std_logic_vector(1 downto 0); + signal ym2149_3D_chan_t1 : std_logic_vector(1 downto 0); + signal ym2149_3D_ioa_in : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_out : std_logic_vector(7 downto 0); + signal ym2149_3D_ioa_oe_l : std_logic; + signal ym2149_3D_iob_in : std_logic_vector(7 downto 0); + -- + signal ampm : std_logic; + signal sint : std_logic; + signal sint_t1 : std_logic; + -- + signal audio_3C_mix : std_logic_vector(9 downto 0); + signal audio_3C_final : std_logic_vector(9 downto 0); + signal audio_3D_mix : std_logic_vector(9 downto 0); + signal audio_3D_final : std_logic_vector(9 downto 0); + signal audio_final : std_logic_vector(10 downto 0); + + signal security_count : std_logic_vector(2 downto 0); + signal rd_l_t1 : std_logic; + -- filters + signal ym2149_3C_k : std_logic_vector(16 downto 0); + signal ym2149_3D_k : std_logic_vector(16 downto 0); + signal audio_in_m_out_3C : std_logic_vector(17 downto 0); + signal audio_in_m_out_3D : std_logic_vector(17 downto 0); + signal audio_mult_3C : std_logic_vector(35 downto 0); + signal audio_mult_3D : std_logic_vector(35 downto 0); + + + + type array_4of17 is array (3 downto 0) of std_logic_vector(16 downto 0); + constant K_Filter : array_4of17 := ('0' & x"00A3", + '0' & x"00C6", + '0' & x"039D", + '1' & x"0000" ); + + type filter_pipe is array (3 downto 0) of std_logic_vector(17 downto 0); + signal ym2149_3C_audio_pipe : filter_pipe; + signal ym2149_3D_audio_pipe : filter_pipe; + -- LP filter out = in.k + out_t1.(1-k) + -- + -- = (in-out_t1).k + out_t1 + -- + -- using + -- -(Ts.2.PI.Fc) + -- k = 1-e + -- + -- sampling freq = 1.79 MHz + -- + -- cut off freqs bit 0 1 + -- + --0.267uf ~ 713 Hz 1 1 0.00249996 x 00A3 + --0.220uf ~ 865 Hz 1 0 0.00303210 x 00C6 + --0.047uf ~ 4050 Hz 0 1 0.01411753 x 039D + -- 0 0 x10000 + +begin + -- scramble + --0000-1fff ROM + --8000-83ff RAM + + -- frogger + --0000-17ff ROM + --4000-43ff RAM + + cpu_ena <= '1'; -- run at audio clock speed + -- other cpu signals + cpu_busrq_l <= '1'; + cpu_nmi_l <= '1'; + cpu_wait_l <= '1'; + -- + cpu_ena_gated <= ENA_1_79 and cpu_ena; + u_cpu : entity work.T80sed + port map ( + RESET_n => I_RESET_L, + CLK_n => CLK, + CLKEN => cpu_ena_gated, + WAIT_n => cpu_wait_l, + INT_n => cpu_int_l, + NMI_n => cpu_nmi_l, + BUSRQ_n => cpu_busrq_l, + M1_n => cpu_m1_l, + MREQ_n => cpu_mreq_l, + IORQ_n => cpu_iorq_l, + RD_n => cpu_rd_l, + WR_n => cpu_wr_l, + RFSH_n => cpu_rfsh_l, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_data_in, + DO => cpu_data_out + ); + + p_cpu_int : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + cpu_int_l <= '1'; + sint_t1 <= '0'; + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + sint_t1 <= sint; + + if (cpu_m1_l = '0') and (cpu_iorq_l = '0') then + cpu_int_l <= '1'; + elsif (sint = '0') and (sint_t1 = '1') then + cpu_int_l <= '0'; + end if; + end if; + end if; + end process; + + p_mem_decode_comb : process(cpu_rfsh_l, cpu_wr_l, cpu_rd_l, cpu_mreq_l, cpu_addr, I_HWSEL_FROGGER) + variable decode : std_logic; + begin + if not I_HWSEL_FROGGER then + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(15) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(12) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(12)); + else + decode := '0'; + if (cpu_rfsh_l = '1') and (cpu_mreq_l = '0') and (cpu_addr(14) = '1') then + decode := '1'; + end if; + + filter_load <= decode and cpu_addr(13) and (not cpu_wr_l); + ram_cs <= decode and (not cpu_addr(13)); + end if; + + rom_oe <= '0'; + if not I_HWSEL_FROGGER then + if (cpu_addr(15) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + else + if (cpu_addr(14) = '0') and (cpu_mreq_l = '0') and (cpu_rd_l = '0') then + rom_oe <= '1'; + end if; + end if; + + end process; + + u_rom_5c : entity work.ROM_SND_0 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom0_dout + ); + + u_rom_5d : entity work.ROM_SND_1 + port map ( + CLK => CLK, + ADDR => cpu_addr(10 downto 0), + DATA => cpu_rom1_dout + ); + + --u_rom_5e : entity work.ROM_SND_2 + -- port map ( + -- CLK => CLK, + -- ADDR => cpu_addr(10 downto 0), + -- DATA => cpu_rom2_dout + -- ); + + p_rom_mux : process(I_HWSEL_FROGGER, cpu_rom0_dout, cpu_rom1_dout, cpu_rom2_dout, cpu_addr, rom_oe) + variable rom_oe_decode : std_logic; + variable cpu_rom0_dout_s : std_logic_vector(7 downto 0); + begin + if not I_HWSEL_FROGGER then + cpu_rom0_dout_s := cpu_rom0_dout; + else -- swap bits 0 and 1 + cpu_rom0_dout_s := cpu_rom0_dout(7 downto 2) & cpu_rom0_dout(0) & cpu_rom0_dout(1); + end if; + + rom_dout <= (others => '0'); + rom_oe_decode := '0'; + case cpu_addr(13 downto 11) is + when "000" => rom_dout <= cpu_rom0_dout_s; rom_oe_decode := '1'; + when "001" => rom_dout <= cpu_rom1_dout; rom_oe_decode := '1'; + when "010" => rom_dout <= cpu_rom2_dout; rom_oe_decode := '1'; + when others => null; + end case; + + rom_active <= '0'; + if (rom_oe = '1') then + rom_active <= rom_oe_decode; + end if; + end process; + + u_ram_6c_6d : work.dpram generic map (10,8) + port map + ( + addr_a_i => cpu_addr(9 downto 0), + data_a_i => cpu_data_out, + clk_b_i => clk, + addr_b_i => cpu_addr(9 downto 0), + data_b_o => ram_dout, + we_i => ram_cs and (not cpu_wr_l), + en_a_i => ENA_1_79, + clk_a_i => clk + ); + + p_cpu_data_mux : process(rom_dout, rom_active, ram_dout, ym2149_3C_oe_l, ym2149_3C_dv, ym2149_3D_oe_l, ym2149_3D_dv, ram_cs, cpu_wr_l) + begin + if (rom_active = '1') then + cpu_data_in <= rom_dout; + elsif (ram_cs = '1') and (cpu_wr_l = '1') then + cpu_data_in <= ram_dout; + elsif (ym2149_3C_oe_l = '0') then + cpu_data_in <= ym2149_3C_dv; + elsif (ym2149_3D_oe_l = '0') then + cpu_data_in <= ym2149_3D_dv; + else + cpu_data_in <= (others => '1'); -- float high + end if; + end process; + + p_filter_reg : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + if (filter_load = '1') then + filter_reg <= cpu_addr(11 downto 0); + end if; + end if; + end process; + + p_8255_decode : process(I_RESET_L, I_ADDR, I_HWSEL_FROGGER) + begin + reset <= not I_RESET_L; + i8255_1D_cs_l <= '1'; + i8255_1E_cs_l <= '1'; + + if not I_HWSEL_FROGGER then + -- the interface one + if (I_ADDR(9) = '1') and (I_ADDR(15) = '1') then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(8) = '1') and (I_ADDR(15) = '1') then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(1 downto 0); + else + -- the interface one + if (I_ADDR(12) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1D_cs_l <= '0'; + end if; + + -- the button one + if (I_ADDR(13) = '1') and (I_ADDR(15 downto 14) = "11") then + i8255_1E_cs_l <= '0'; + end if; + i8255_addr <= I_ADDR(2 downto 1); + end if; + end process; + + p_ym_decode : process(cpu_rd_l, cpu_wr_l, cpu_iorq_l, cpu_addr, I_HWSEL_FROGGER) + variable rd_3c : std_logic; + variable wr_3c : std_logic; + variable ad_3c : std_logic; + -- + variable rd_3d : std_logic; + variable wr_3d : std_logic; + variable ad_3d : std_logic; + begin + + --bdir bc2 bc1 + -- 0 0 0 nop + -- 0 0 1 addr latch < WR_L AV4 / AV6 + -- 0 1 0 nop + -- 0 1 1 data read < RD_L AV5 / AV7 + + -- 1 0 0 addr latch + -- 1 0 1 nop + -- 1 1 0 data write < WR_L AV5 / AV7 + -- 1 1 1 addr latch + + + if not I_HWSEL_FROGGER then + rd_3c := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(5); + wr_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(5); + ad_3c := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(4); + else + rd_3c := '0'; + wr_3c := '0'; + ad_3c := '0'; + end if; + + ym2149_3C_bdir <= wr_3c; + ym2149_3C_bc2 <= rd_3c or wr_3c; + ym2149_3C_bc1 <= rd_3c or ad_3c; + + + if not I_HWSEL_FROGGER then + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(7); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + else + rd_3d := (not cpu_rd_l) and (not cpu_iorq_l) and cpu_addr(6); + wr_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(6); + ad_3d := (not cpu_wr_l) and (not cpu_iorq_l) and cpu_addr(7); + end if; + + ym2149_3D_bdir <= wr_3d; + ym2149_3D_bc2 <= rd_3d or wr_3d; + ym2149_3D_bc1 <= rd_3d or ad_3d; + + end process; + + i8255_1E_pa(7) <= I_COIN1; + i8255_1E_pa(6) <= I_COIN2; + i8255_1E_pa(5) <= I_1P_CTRL(3); -- left + i8255_1E_pa(4) <= I_1P_CTRL(2); -- right + i8255_1E_pa(3) <= I_1P_CTRL(4); -- shoot1 + i8255_1E_pa(2) <= I_SERVICE; + i8255_1E_pa(1) <= I_1P_CTRL(5); -- shoot2 + i8255_1E_pa(0) <= I_2P_CTRL(1); -- up + + i8255_1E_pb(7) <= I_1P_CTRL(6); -- start + i8255_1E_pb(6) <= I_2P_CTRL(6); -- start + i8255_1E_pb(5) <= I_2P_CTRL(3); -- left + i8255_1E_pb(4) <= I_2P_CTRL(2); -- right + i8255_1E_pb(3) <= I_2P_CTRL(4); -- shoot1 + i8255_1E_pb(2) <= I_2P_CTRL(5); -- shoot2 + i8255_1E_pb(1) <= I_DIP(1); + i8255_1E_pb(0) <= I_DIP(2); + + i8255_1E_pc(7) <= net_1e10_i; + i8255_1E_pc(6) <= I_1P_CTRL(0); -- down + i8255_1E_pc(5) <= net_1e12_i; + i8255_1E_pc(4) <= I_1P_CTRL(1); -- up + i8255_1E_pc(3) <= I_DIP(3); + i8255_1E_pc(2) <= I_DIP(4); + i8255_1E_pc(1) <= I_DIP(5); + i8255_1E_pc(0) <= I_2P_CTRL(0); -- down + O_COIN_COUNTER <= not I_IOPC7; -- open drain actually + + -- + -- PIA CHIPS + -- + u_i8255_1D : entity work.I82C55 -- bus interface + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1D_data, + O_DATA_OE_L => i8255_1D_data_oe_l, + + I_CS_L => i8255_1D_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1D_pa_out, + O_PA => i8255_1D_pa_out, + O_PA_OE_L => open, + + I_PB => i8255_1D_pb_out, + O_PB => i8255_1D_pb_out, + O_PB_OE_L => open, + + I_PC => xbo, + O_PC => xb, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + u_i8255_1E : entity work.I82C55 -- push button + port map ( + I_ADDR => i8255_addr, + I_DATA => I_DATA, + O_DATA => i8255_1E_data, + O_DATA_OE_L => i8255_1E_data_oe_l, + + I_CS_L => i8255_1E_cs_l, + I_RD_L => I_RD_L, + I_WR_L => I_WR_L, + + I_PA => i8255_1E_pa, + O_PA => open, + O_PA_OE_L => open, + + I_PB => i8255_1E_pb, + O_PB => open, + O_PB_OE_L => open, + + I_PC => i8255_1E_pc, + O_PC => open, + O_PC_OE_L => open, + + RESET => reset, + ENA => ENA, + CLK => CLK + ); + + p_i8255_1d_bus_control : process(i8255_1D_pa_out, i8255_1D_pb_out, ym2149_3D_ioa_out, ym2149_3D_ioa_oe_l) + begin + if (ym2149_3D_ioa_oe_l = '0') then + ym2149_3D_ioa_in <= ym2149_3D_ioa_out; + else + ym2149_3D_ioa_in <= i8255_1D_pa_out; + end if; + + ampm <= i8255_1D_pb_out(4); -- amp mute + sint <= i8255_1D_pb_out(3); -- set int + end process; + + p_drive_cpubus : process(i8255_1D_data, i8255_1D_data_oe_l, i8255_1E_data, i8255_1E_data_oe_l) + begin + O_DATA_OE_L <= '1'; + O_DATA <= (others => '0'); + -- + if (i8255_1D_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1D_data; + elsif (i8255_1E_data_oe_l = '0') then + -- + O_DATA_OE_L <= '0'; + O_DATA <= i8255_1E_data; + end if; + end process; + -- + -- AUDIO CHIPS + -- + p_audio_clockgen : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + audio_div_cnt <= audio_div_cnt - "1"; + ls90_clk <= not audio_div_cnt(8); + + if (audio_div_cnt(8 downto 0) = "000000000") then + if (ls90_cnt = x"9") then + ls90_cnt <= x"0"; + else + ls90_cnt <= ls90_cnt + "1"; + end if; + end if; + + ls90_op <= "0000"; + case ls90_cnt is --ls90 outputs DCBA + when x"0" => ls90_op <= "0000"; + when x"1" => ls90_op <= "0010"; + when x"2" => ls90_op <= "0100"; + when x"3" => ls90_op <= "0110"; + when x"4" => ls90_op <= "1000"; + when x"5" => ls90_op <= "0001"; + when x"6" => ls90_op <= "0011"; + when x"7" => ls90_op <= "0101"; + when x"8" => ls90_op <= "0111"; + when x"9" => ls90_op <= "1001"; + when others => ls90_op <= "0000"; + end case; + end if; + end process; + + p_ym2149_3d_iob_in : process(I_HWSEL_FROGGER, ls90_op, ls90_clk) + begin + if not I_HWSEL_FROGGER then + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & ls90_op(2) & ls90_clk & "1110"; + else + ym2149_3D_iob_in <= ls90_op(0) & ls90_op(3) & '1' & ls90_clk & ls90_op(2) & "110"; + end if; + end process; + + u_ym2149_3C : entity work.YM2149 -- not used for frogger + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3C_dv, + O_DA_OE_L => ym2149_3C_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3C_bdir, + I_BC2 => ym2149_3C_bc2, + I_BC1 => ym2149_3C_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3C_audio, + O_CHAN => ym2149_3C_chan, + -- port a + I_IOA => "11111111", + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => "11111111", + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + u_ym2149_3D : entity work.YM2149 + port map ( + -- data bus + I_DA => cpu_data_out, + O_DA => ym2149_3D_dv, + O_DA_OE_L => ym2149_3D_oe_l, + -- control + I_A9_L => '0', + I_A8 => '1', + I_BDIR => ym2149_3D_bdir, + I_BC2 => ym2149_3D_bc2, + I_BC1 => ym2149_3D_bc1, + I_SEL_L => '1', + + O_AUDIO => ym2149_3D_audio, + O_CHAN => ym2149_3D_chan, + -- port a + I_IOA => ym2149_3D_ioa_in, + O_IOA => ym2149_3D_ioa_out, + O_IOA_OE_L => ym2149_3D_ioa_oe_l, + -- port b + I_IOB => ym2149_3D_iob_in, + O_IOB => open, + O_IOB_OE_L => open, + + ENA => ENA_1_79, + RESET_L => I_RESET_L, + CLK => CLK + ); + + p_filter_coef : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + case ym2149_3C_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3C_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(5 downto 4))); + when "10" => -- chan 1 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(3 downto 2))); + when "01" => -- chan 0 + ym2149_3C_k <= K_FILTER(conv_integer(filter_reg(1 downto 0))); + when others => null; + end case; + + case ym2149_3D_chan is -- -1 as reg here + when "00" => -- chan 3 + ym2149_3D_k <= (others => '0'); + when "11" => -- chan 2 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg(11 downto 10))); + when "10" => -- chan 1 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 9 downto 8))); + when "01" => -- chan 0 + ym2149_3D_k <= K_FILTER(conv_integer(filter_reg( 7 downto 6))); + when others => null; + end case; + end if; + end process; + + + p_ym2149_audio_process : process(ym2149_3C_audio, ym2149_3C_audio_pipe, ym2149_3D_audio, ym2149_3D_audio_pipe) + begin + audio_in_m_out_3C <= (('0' & ym2149_3C_audio & "000000000"))- ym2149_3C_audio_pipe(3); -- signed + audio_in_m_out_3D <= (('0' & ym2149_3D_audio & "000000000"))- ym2149_3D_audio_pipe(3); -- signed + end process; + + mult_3C : work.MULT18X18 + port map + ( + P => audio_mult_3C,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3C, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3C_k + ); + + mult_3D : work.MULT18X18 + port map + ( + P => audio_mult_3D,-- 35..0 -- audio 8bit on 32..25 33 sign bit, + A => audio_in_m_out_3D, --17..0 + B(17) => '0', + B(16 downto 0) => ym2149_3D_k + ); + + p_ym2149_audio_pipe : process(I_RESET_L, CLK) + begin + if (I_RESET_L = '0') then + ym2149_3C_audio_pipe <= (others => (others => '0')); + ym2149_3D_audio_pipe <= (others => (others => '0')); + elsif rising_edge(CLK) then +-- audio_mult_3C <= audio_in_m_out_3C * ym2149_3C_k; +-- audio_mult_3D <= audio_in_m_out_3D * ym2149_3D_k; + if (ENA_1_79 = '1') then + -- we need some holding registers anyway, so lets just make it a shift and save a mux + ym2149_3C_audio_pipe(3 downto 1) <= ym2149_3C_audio_pipe(2 downto 0); + ym2149_3C_audio_pipe(0) <= audio_mult_3C(33 downto 16) + ym2149_3C_audio_pipe(3); -- bit 33 sign + + ym2149_3D_audio_pipe(3 downto 1) <= ym2149_3D_audio_pipe(2 downto 0); + ym2149_3D_audio_pipe(0) <= audio_mult_3D(33 downto 16) + ym2149_3D_audio_pipe(3); -- bit 33 sign + end if; + end if; + end process; + + p_ym2149_audio_mix : process + begin + wait until rising_edge(CLK); + if (ENA_1_79 = '1') then + ym2149_3C_chan_t1 <= ym2149_3C_chan; + ym2149_3D_chan_t1 <= ym2149_3D_chan; + + if (ym2149_3C_chan_t1 = "11") then + audio_3C_mix <= (others => '0'); + audio_3C_final <= audio_3C_mix; + else + audio_3C_mix <= audio_3C_mix + ("00" & ym2149_3C_audio_pipe(0)(16 downto 9)); + end if; + + if (ym2149_3D_chan_t1(1 downto 0) = "11") then + audio_3D_mix <= (others => '0'); + audio_3D_final <= audio_3D_mix; + else + audio_3D_mix <= audio_3D_mix + ("00" & ym2149_3D_audio_pipe(0)(16 downto 9)); + end if; + + audio_final <= ('0' & audio_3C_final) + ('0' & audio_3D_final); + end if; + end process; + + p_audio_out : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + O_AUDIO <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA_1_79 = '1') then + if (ampm = '1') then + O_AUDIO <= (others => '0'); + else + if (audio_final(10) = '1') then + O_AUDIO <= (others => '1'); + else + O_AUDIO <= audio_final(9 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_security_6J : process(xb) + begin + -- chip K10A PAL16L8 + -- equations from Mark @ http://www.leopardcats.com/ + xbo(3 downto 0) <= xb(3 downto 0); + xbo(4) <= not(xb(0) or xb(1) or xb(2) or xb(3)); + xbo(5) <= not((not xb(2) and not xb(0)) or (not xb(2) and not xb(1)) or (not xb(3) and not xb(0)) or (not xb(3) and not xb(1))); + + xbo(6) <= not(not xb(0) and not xb(3)); + xbo(7) <= not((not xb(1)) or xb(2)); + end process; + + p_security_count : process(CLK, I_RESET_L) + begin + if (I_RESET_L = '0') then + security_count <= "000"; + elsif rising_edge(CLK) then + rd_l_t1 <= i_rd_l; + if (I_ADDR = x"8102") and (I_RD_L = '0') and (rd_l_t1 = '1') then + security_count <= security_count + "1"; + end if; + end if; + end process; + + p_security_2B : process(security_count) + begin + -- I am not sure what this chip does yet, but this gets us past the initial check for now. + case security_count is + when "000" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "001" => net_1e10_i <= '0'; net_1e12_i <= '1'; + when "010" => net_1e10_i <= '1'; net_1e12_i <= '0'; + when "011" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "100" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "101" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "110" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when "111" => net_1e10_i <= '1'; net_1e12_i <= '1'; + when others => null; + end case; + end process; + +end RTL; \ No newline at end of file diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd new file mode 100644 index 00000000..d0e257bb --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_top.vhd @@ -0,0 +1,240 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_TOP is +port ( + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(2 downto 0); + O_HSYNC : out std_logic; + O_VSYNC : out std_logic; + O_HBLANK : out std_logic; + O_VBLANK : out std_logic; + + O_AUDIO : out std_logic_vector(9 downto 0); + + button_in : in std_logic_vector(7 downto 0); + + RESET : in std_logic; + clk : in std_logic; -- 25 + ena_star : in std_logic; + ena_6 : in std_logic; -- 6.25 + ena_1_79 : in std_logic -- 1.786 +); +end; + +architecture RTL of SCRAMBLE_TOP is +-- this MUST be set true for frogger +-- this MUST be set false for scramble, the_end, amidar +constant I_HWSEL_FROGGER : boolean := false; + +-- ip registers +signal ip_1p : std_logic_vector(6 downto 0); +signal ip_2p : std_logic_vector(6 downto 0); +signal ip_service : std_logic; +signal ip_coin1 : std_logic; +signal ip_coin2 : std_logic; +signal ip_dip_switch : std_logic_vector(5 downto 1); + +-- ties to audio board +signal audio_addr : std_logic_vector(15 downto 0); +signal audio_data_out : std_logic_vector(7 downto 0); +signal audio_data_in : std_logic_vector(7 downto 0); +signal audio_data_oe_l : std_logic; +signal audio_rd_l : std_logic; +signal audio_wr_l : std_logic; +signal audio_iopc7 : std_logic; +signal audio_reset_l : std_logic; + +begin + +u_scramble : entity work.SCRAMBLE +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + O_VIDEO_R => O_VIDEO_R, + O_VIDEO_G => O_VIDEO_G, + O_VIDEO_B => O_VIDEO_B, + O_HSYNC => O_HSYNC, + O_VSYNC => O_VSYNC, + O_HBLANK => O_HBLANK, + O_VBLANK => O_VBLANK, + -- + -- to audio board + -- + O_ADDR => audio_addr, + O_DATA => audio_data_out, + I_DATA => audio_data_in, + I_DATA_OE_L => audio_data_oe_l, + O_RD_L => audio_rd_l, + O_WR_L => audio_wr_l, + O_IOPC7 => audio_iopc7, + O_RESET_WD_L => audio_reset_l, + -- + ENA => ena_6, + ENA_STAR => ena_star, + -- + RESET => reset, + CLK => clk +); + +-- +-- +-- audio subsystem +-- +u_audio : entity work.SCRAMBLE_AUDIO +port map ( + I_HWSEL_FROGGER => I_HWSEL_FROGGER, + -- + I_ADDR => audio_addr, + I_DATA => audio_data_out, + O_DATA => audio_data_in, + O_DATA_OE_L => audio_data_oe_l, + -- + I_RD_L => audio_rd_l, + I_WR_L => audio_wr_l, + I_IOPC7 => audio_iopc7, + -- + O_AUDIO => O_AUDIO, + -- + I_1P_CTRL => ip_1p, -- start, shoot1, shoot2, left,right,up,down + I_2P_CTRL => ip_2p, -- start, shoot1, shoot2, left,right,up,down + I_SERVICE => ip_service, + I_COIN1 => ip_coin1, + I_COIN2 => ip_coin2, + O_COIN_COUNTER => open, + -- + I_DIP => ip_dip_switch, + -- + I_RESET_L => audio_reset_l, + ENA => ena_6, + ENA_1_79 => ena_1_79, + CLK => clk +); + +--button_in(0) = Joystick Up +--button_in(1) = Joystick Down +--button_in(2) = Joystick Left +--button_in(3) = Joystick Right +--button_in(4) = Button Left +--button_in(5) = Button Down +--button_in(6) = Joystick Fire +--button_in(7) = Button Right + +--Buttons are connected to ground and connect to 3.3V when pressed +--Joystick has internal pullup resistor and connects to ground when pressed + +--A '0' on the input is active. Inputs are active low. + +-- assign inputs +-- start, shoot1, shoot2, left,right,up,down +ip_1p(6) <= button_in(4); -- start 1 +ip_1p(5) <= button_in(6); -- shoot1 +ip_1p(4) <= button_in(6); -- shoot2 +ip_1p(3) <= button_in(2); -- p1 left +ip_1p(2) <= button_in(3); -- p1 right +ip_1p(1) <= button_in(0); -- p1 up +ip_1p(0) <= button_in(1); -- p1 down +-- +ip_2p(6) <= button_in(7); -- start 2 +ip_2p(5) <= button_in(6); +ip_2p(4) <= button_in(6); +ip_2p(3) <= button_in(2); -- p2 left +ip_2p(2) <= button_in(3); -- p2 right +ip_2p(1) <= button_in(0); -- p2 up +ip_2p(0) <= button_in(1); -- p2 down +-- +ip_service <= '1'; +ip_coin1 <= button_in(5); -- credit +ip_coin2 <= '1'; + +-- dip switch settings +scramble_dips : if (not I_HWSEL_FROGGER) generate +begin + --SW #1 SW #2 Rockets SW #3 Cabinet + ------- ----- --------- ----- -------- + --OFF OFF Unlimited OFF Table + --OFF ON 5 ON Up Right + --ON OFF 4 + --ON ON 3 + + + --SW #4 SW #5 Coins/Play + ------- ----- ---------- + --OFF OFF 4 + --OFF ON 3 + --ON OFF 2 + --ON ON 1 + + ip_dip_switch(5 downto 4) <= not "11"; -- 1 play/coin. + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "10"; +end generate; + +frogger_dips : if ( I_HWSEL_FROGGER) generate +begin + --1 2 3 4 5 Meaning + ------------------------------------------------------- + --On On 3 Frogs + --On Off 5 Frogs + --Off On 7 Frogs + --Off Off 256 Frogs (!) + -- + -- On Upright unit + -- Off Cocktail unit + -- + -- On On 1 coin 1 play + -- On Off 2 coins 1 play + -- Off On 3 coins 1 play + -- Off Off 1 coin 2 plays + + ip_dip_switch(5 downto 4) <= not "11"; + ip_dip_switch(3) <= not '1'; + ip_dip_switch(2 downto 1) <= not "01"; +end generate; + +end RTL; \ No newline at end of file diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd new file mode 100644 index 00000000..f6fd981a --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/scramble_video.vhd @@ -0,0 +1,848 @@ +-- +-- A simulation model of Scramble hardware +-- Copyright (c) MikeJ - Feb 2007 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity SCRAMBLE_VIDEO is + port ( + I_HWSEL_FROGGER : in boolean; + -- + I_HCNT : in std_logic_vector(8 downto 0); + I_VCNT : in std_logic_vector(8 downto 0); + I_VBLANK : in std_logic; + I_VSYNC : in std_logic; + + I_VCMA : in std_logic; + I_HCMA : in std_logic; + -- + I_CPU_ADDR : in std_logic_vector(15 downto 0); + I_CPU_DATA : in std_logic_vector(7 downto 0); + O_VRAM_DATA : out std_logic_vector(7 downto 0); + -- note, looks like the real hardware cannot read from object ram + -- + I_VRAMWR_L : in std_logic; + I_VRAMRD_L : in std_logic; + I_OBJRAMWR_L : in std_logic; + I_OBJRAMRD_L : in std_logic; + I_OBJEN_L : in std_logic; + -- + I_STARSON : in std_logic; + I_POUT1 : in std_logic; + -- + O_VIDEO_R : out std_logic_vector(2 downto 0); + O_VIDEO_G : out std_logic_vector(2 downto 0); + O_VIDEO_B : out std_logic_vector(2 downto 0); + -- + ENA : in std_logic; + ENA_STAR : in std_logic; + CLK : in std_logic + ); +end; + +-- chars stars vidout? shell/missile +-- +-- 220R B 100 B 390R B 100R R +-- 470R B 150 B 100R G +-- 220R G 100 G blue ? +-- 470R G 150 G +-- 1K G 100 R +-- 220R R 150 R +-- 470R R +-- 1K R +architecture RTL of SCRAMBLE_VIDEO is + + type array_3x5 is array (2 downto 0) of std_logic_vector(2 downto 0); + -- timing + signal ld : std_logic; + signal h256_l : std_logic; + signal h256 : std_logic; + signal cblank_s : std_logic; + signal hcmp1_s : std_logic; + signal hcmp2_s : std_logic; + signal hcmp1 : std_logic; + signal hcmp2 : std_logic; + signal cblank_l : std_logic; + signal h256_l_s : std_logic; + signal hcnt_f : std_logic_vector(7 downto 0); + signal vcnt_f : std_logic_vector(7 downto 0); + + -- load strobes + signal vpl_load : std_logic; + signal col_load : std_logic; + signal objdata_load : std_logic; + signal missile_load : std_logic; + signal missile_reg_l : std_logic; + + signal cntr_clr : std_logic; + signal cntr_load : std_logic; + signal sld_l : std_logic; + signal mld_l : std_logic; + + -- video ram + signal vram_addr_sum : std_logic_vector(8 downto 0); -- extra bit for debug + signal msld_l : std_logic; + signal vram_addr_reg : std_logic_vector(7 downto 0); + signal vram_addr_xor : std_logic_vector(3 downto 0); + signal vram_addr : std_logic_vector(9 downto 0); + signal vram_dout : std_logic_vector(7 downto 0); + signal ldout : std_logic; + + -- object ram + signal obj_addr : std_logic_vector(7 downto 0); + signal hpla : std_logic_vector(7 downto 0); + signal objdata : std_logic_vector(7 downto 0); + + signal obj_rom_addr : std_logic_vector(10 downto 0); + signal obj_rom_0_dout : std_logic_vector(7 downto 0); + signal obj_rom_1_dout : std_logic_vector(7 downto 0); + -- + signal col_reg : std_logic_vector(2 downto 0); + signal cd : std_logic_vector(2 downto 0); + + signal shift_reg_1 : std_logic_vector(7 downto 0); + signal shift_reg_0 : std_logic_vector(7 downto 0); + signal shift_op : std_logic_vector(1 downto 0); + signal shift_sel : std_logic_vector(1 downto 0); + signal gr : std_logic_vector(1 downto 0); + signal gc : std_logic_vector(2 downto 0); + + signal vid : std_logic_vector(1 downto 0); + signal col : std_logic_vector(2 downto 0); + + signal obj_video_out_reg : std_logic_vector(4 downto 0); + signal vidout_l : std_logic; + signal obj_lut_out : std_logic_vector(7 downto 0); + + signal cntr_addr : std_logic_vector(7 downto 0); + signal cntr_addr_xor : std_logic_vector(10 downto 0); + signal sprite_sel : std_logic; + signal sprite_ram_ip : std_logic_vector(7 downto 0); + signal sprite_ram_waddr : std_logic_vector(10 downto 0); + signal sprite_ram_op : std_logic_vector(7 downto 0); + -- shell + signal shell_cnt : std_logic_vector(7 downto 0); + signal shell_ena : std_logic; + signal shell : std_logic; + signal shell_reg : std_logic; + -- missile + signal missile_cnt : std_logic_vector(7 downto 0); + signal missile_ena : std_logic; + signal missile : std_logic; + signal missile_reg : std_logic; + -- stars + signal star_r : std_logic_vector(1 downto 0); + signal star_g : std_logic_vector(1 downto 0); + signal star_b : std_logic_vector(1 downto 0); + -- frogger blue bar + signal frogger_blue_reg : std_logic; + signal frogger_blue : std_logic; + signal frogger_blue_out_reg : std_logic; + -- scramble blue + signal pout1_reg : std_logic; + + +begin + p_hcnt_decode : process(I_HCNT) + begin + ld <= '0'; + if (I_HCNT(2 downto 0) = "111") then + ld <= '1'; + end if; + h256_l <= I_HCNT(8); + h256 <= not I_HCNT(8); + + end process; + + p_timing_decode : process(h256, h256_l, I_HCMA, I_VBLANK) + begin + cblank_s <= not (I_VBLANK or h256); -- active low + hcmp1_s <= h256_l and I_HCMA; + end process; + + p_reg : process + begin + wait until rising_edge(CLK); + + if (ENA = '1') then + if (ld = '1') then + hcmp1 <= hcmp1_s; + hcmp2 <= hcmp2_s; + cblank_l <= cblank_s; + h256_l_s <= h256_l; + + if not I_HWSEL_FROGGER then + cd <= col_reg; + else + cd <= col_reg(0) & col_reg(2 downto 1); + end if; + end if; + end if; + end process; + + p_load_decode : process(ld, I_HCNT, h256) + variable obj_load : std_logic; + begin + vpl_load <= '0'; + obj_load := '0'; + col_load <= '0'; + + if (I_HCNT(2 downto 0) = "001") then vpl_load <= '1'; end if; -- 1 clock later + if (I_HCNT(2 downto 0) = "011") then obj_load := '1'; end if; -- 1 later + if (I_HCNT(2 downto 0) = "101") then col_load <= '1'; end if; -- 1 later + + objdata_load <= obj_load and h256 and (not I_HCNT(3)); + missile_load <= obj_load and h256 and ( I_HCNT(3)); + + cntr_clr <= ld and (not h256) and (not I_HCNT(3)); + cntr_load <= ld and ( h256) and (not I_HCNT(3)); + + end process; + + p_hv_flip : process(I_HCNT, I_VCNT, I_VCMA, hcmp1_s) + begin + for i in 0 to 7 loop + vcnt_f(i) <= I_VCNT(i) xor I_VCMA; + hcnt_f(i) <= I_HCNT(i) xor hcmp1_s; + end loop; + end process; + + p_video_addr_calc : process(I_HWSEL_FROGGER, vcnt_f, hpla) + begin + if not I_HWSEL_FROGGER then + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(7 downto 0)); + else + vram_addr_sum <= ('0' & vcnt_f(7 downto 0)) + ('0' & hpla(3 downto 0) & hpla(7 downto 4)); + end if; + end process; + + p_msld : process(vram_addr_sum) + begin + msld_l <= '1'; + if (vram_addr_sum(7 downto 0) = "11111111") then + msld_l <= '0'; + end if; + end process; + + p_video_addr_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_VBLANK = '1') then -- was async + vram_addr_reg <= x"00"; + elsif (vpl_load = '1') then -- vpl_l + vram_addr_reg <= vram_addr_sum(7 downto 0); + end if; + end if; + end process; + + p_vram_xor : process(vram_addr_reg, objdata, h256) + variable flip : std_logic; + begin + flip := objdata(7) and h256; + for i in 0 to 3 loop + vram_addr_xor(i) <= vram_addr_reg(i) xor flip; + end loop; + end process; + + p_vram_addr : process(vram_addr_reg, cblank_s, ld, I_CPU_ADDR, vram_addr_xor, hcnt_f) + variable match : std_logic; + begin + match := '0'; + if (vram_addr_reg(7 downto 4) = "1111") then + match := '1'; + end if; + + if (cblank_s = '0') then + ldout <= match and ld; -- blanking, sprites + else + ldout <= ld; + end if; + + if (cblank_s = '0') then -- blanking, sprites + --vram_cs <= (not I_VRAMWR_L) or (not I_VRAMRD_L); + vram_addr <= I_CPU_ADDR(9 downto 0); -- let the cpu in + else + --vram_cs <= '1'; + vram_addr <= vram_addr_reg(7 downto 4) & vram_addr_xor(3) & hcnt_f(7 downto 3); + end if; + end process; + + u_vram : work.dpram generic map (10,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_VRAMWR_L, + + addr_a_i => vram_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => vram_addr, + data_b_o => vram_dout + ); + O_VRAM_DATA <= vram_dout; + + p_object_ram_addr : process(h256, I_HCMA, objdata, I_HCNT, hcnt_f, I_CPU_ADDR, I_OBJEN_L) + begin + -- I believe the object ram can only be written during vblank + + if (h256 = '0') then + hcmp2_s <= I_HCMA; + else + hcmp2_s <= objdata(6); + end if; + + if (I_OBJEN_L = '0') then + obj_addr <= I_CPU_ADDR(7 downto 0); + else + obj_addr(7) <= '0'; + obj_addr(6) <= h256; + + -- A + if (h256 = '0') then -- normal + obj_addr(5) <= hcnt_f(7); --128h'; + else -- sprite + obj_addr(5) <= hcnt_f(3) and I_HCNT(1);-- 8h' and 2h; + end if; + + obj_addr(4 downto 2) <= hcnt_f(6 downto 4); + + if (h256 = '0') then -- normal + obj_addr(1) <= hcnt_f(3); --8h' + obj_addr(0) <= I_HCNT(2); --4h + else + obj_addr(1) <= I_HCNT(2); --4h + obj_addr(0) <= I_HCNT(1); --2h + end if; + + end if; + end process; + + u_object_ram : work.dpram generic map (8,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => not I_OBJRAMWR_L, + + addr_a_i => obj_addr, + data_a_i => I_CPU_DATA, -- only cpu can write + + clk_b_i => clk, + addr_b_i => obj_addr, + data_b_o => hpla + ); + + p_objdata_regs : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (col_load = '1') then -- colour load + col_reg <= hpla(2 downto 0); + end if; + + if (objdata_load = '1') then -- sprite load + objdata <= hpla; + end if; + + if (I_VBLANK = '1') then -- was async + missile_reg_l <= '1'; + elsif (missile_load = '1') then + missile_reg_l <= msld_l; + end if; + end if; + end process; + + p_obj_rom_addr : process(h256, vram_addr_xor, vram_dout, objdata, I_HCNT) + begin + obj_rom_addr( 2 downto 0) <= vram_addr_xor(2 downto 0); + if (h256 = '0') then + -- a + obj_rom_addr(10 downto 3) <= vram_dout; -- background objects + else + obj_rom_addr(10 downto 3) <= objdata(5 downto 0) & vram_addr_xor(3) & (objdata(6) xor I_HCNT(3)); -- sprites + end if; + end process; + + obj_rom0 : entity work.ROM_OBJ_0 -- 5H + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_0_dout); + obj_rom1 : entity work.ROM_OBJ_1 -- 5F + port map (CLK => CLK, ADDR => obj_rom_addr, DATA => obj_rom_1_dout); + + p_obj_rom_shift : process + variable obj_rom_0_dout_s : std_logic_vector(7 downto 0); + begin + wait until rising_edge (CLK); + if not I_HWSEL_FROGGER then + obj_rom_0_dout_s := obj_rom_0_dout; + else -- swap bits 0 and 1 + obj_rom_0_dout_s := obj_rom_0_dout(7 downto 2) & obj_rom_0_dout(0) & obj_rom_0_dout(1); + end if; + + if (ENA = '1') then + case shift_sel is + when "00" => null; -- do nothing + + when "01" => shift_reg_1 <= '0' & shift_reg_1(7 downto 1); -- right + shift_reg_0 <= '0' & shift_reg_0(7 downto 1); + + when "10" => shift_reg_1 <= shift_reg_1(6 downto 0) & '0'; -- left + shift_reg_0 <= shift_reg_0(6 downto 0) & '0'; + + when "11" => shift_reg_1 <= obj_rom_1_dout (7 downto 0); -- load + shift_reg_0 <= obj_rom_0_dout_s(7 downto 0); + when others => null; + end case; + end if; + end process; + + p_obj_rom_shift_sel : process(hcmp2, ldout, shift_reg_1, shift_reg_0) + begin + if (hcmp2 = '0') then + + shift_sel(1) <= '1'; + shift_sel(0) <= ldout; + shift_op(1) <= shift_reg_1(7); + shift_op(0) <= shift_reg_0(7); + else + + shift_sel(1) <= ldout; + shift_sel(0) <= '1'; + shift_op(1) <= shift_reg_1(0); + shift_op(0) <= shift_reg_0(0); + end if; + end process; + + p_video_out_logic : process(shift_op, cd, gr, gc) + variable vidon : std_logic; + begin + vidon := shift_op(0) or shift_op(1); + + if (gr(1 downto 0) = "00") then + vid(1 downto 0) <= shift_op(1 downto 0); + else + vid(1 downto 0) <= gr(1 downto 0); + end if; + + if (gc(2 downto 0) = "000") and (vidon = '1') then + col(2 downto 0) <= cd(2 downto 0); + else + col(2 downto 0) <= gc(2 downto 0); + end if; + end process; + + p_shell_ld : process(ld, h256, I_HCNT, missile_reg_l) + begin + sld_l <= '1'; + mld_l <= '1'; + if (ld = '1') and (h256 = '1') and (I_HCNT(3) = '1') then --4D:Y3 + if (missile_reg_l = '0') and (I_HCNT(6 downto 3) /= "1111") then -- tweak to mimic galaxian hw ! + sld_l <= '0'; + end if; + + if (missile_reg_l = '0') and (I_HCNT(6 downto 3) = "1111") then -- tweak to mimic galaxian hw ! + mld_l <= '0'; + end if; + + end if; + + end process; + + p_shell_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + if (sld_l = '0') then + shell_cnt <= hpla; + elsif (cblank_l = '1') then + shell_cnt <= shell_cnt + "1"; + else + shell_cnt <= shell_cnt; + end if; + + if (sld_l = '0') then + shell_ena <= '1'; + elsif (shell_cnt = "11111110") then + shell_ena <= '0'; + end if; + end if; + end process; + + p_shell_op : process(shell_cnt, shell_ena) + begin + -- note how T input is from QD on the bottom counter + -- we get a rc from xF8 to XFF + -- so the shell is set at count xFA (rc and bit 1) + shell <= '0'; + if (shell_cnt > x"F8") then -- minus 2 as delay wrong + shell <= shell_ena; + end if; + end process; + + p_missile_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + if (mld_l = '0') then + missile_cnt <= hpla; + elsif (cblank_l = '1') then + missile_cnt <= missile_cnt + "1"; + else + missile_cnt <= missile_cnt; + end if; + + if (mld_l = '0') then + missile_ena <= '1'; + elsif (missile_cnt = "11111110") then + missile_ena <= '0'; + end if; + end if; + end process; + + p_missile_op : process(missile_cnt, missile_ena) + begin + -- note how T input is from QD on the bottom counter + -- we get a rc from xF8 to XFF + -- so the shell is set at count xFA (rc and bit 1) + missile <= '0'; + if (missile_cnt > x"F8") then -- minus 2 as delay wrong + missile <= missile_ena; + end if; + end process; + + p_cntr_cnt : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (cntr_clr = '1') and (h256_l_s = '0') then -- async + cntr_addr <= (others => '0'); + elsif (cntr_load = '1') then + cntr_addr <= hpla(7 downto 0); + else + cntr_addr <= cntr_addr + "1"; + end if; + end if; + end process; + + p_cntr_addr : process(cntr_addr, hcmp1) + begin + cntr_addr_xor(10 downto 8) <= (others => '0'); + for i in 0 to 7 loop + cntr_addr_xor(i) <= cntr_addr(i) xor hcmp1; + end loop; + end process; + + p_sprite_sel : process(h256_l_s, cntr_addr_xor) + begin + sprite_sel <= '0'; + if (h256_l_s = '0') and (cntr_addr_xor(7 downto 4) /= "0000") then + sprite_sel <= '1'; + end if; + end process; + + p_sprite_write : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + -- delay 1 clock + sprite_ram_ip <= (others => '0'); + if (sprite_sel = '1') then + sprite_ram_ip(4 downto 2) <= col(2 downto 0); + sprite_ram_ip(1 downto 0) <= vid(1 downto 0); + end if; + + sprite_ram_waddr <= cntr_addr_xor; + end if; + end process; + + + u_sprite_ram : work.dpram generic map (11,8) + port map + ( + clk_a_i => clk, + en_a_i => ena, + we_i => '1', + + addr_a_i => sprite_ram_waddr, + data_a_i => sprite_ram_ip, + + clk_b_i => clk, + addr_b_i => cntr_addr_xor, + data_b_o => sprite_ram_op + ); + + gc(2 downto 0) <= sprite_ram_op(4 downto 2); + gr(1 downto 0) <= sprite_ram_op(1 downto 0); + + p_video_out_reg : process + variable vidout_l_int : std_logic; + begin + wait until rising_edge(CLK); + -- register all objects to match increased video delay + if (ENA = '1') then + + if (cblank_l = '0') then + -- logic around the clr workes out as a sync reset + obj_video_out_reg <= (others => '0'); + shell_reg <= '0'; + frogger_blue_out_reg <= '0'; + pout1_reg <= '0'; + else + + obj_video_out_reg(4 downto 2) <= col(2 downto 0); + obj_video_out_reg(1 downto 0) <= vid(1 downto 0); + vidout_l <= not(vid(1) or vid(0)); + -- probably wider than the original, we must be a whole 6MHz clock here or the scan-doubler will loose it. + shell_reg <= shell; + missile_reg <= missile; + frogger_blue_out_reg <= frogger_blue; + + pout1_reg <= I_POUT1; + + end if; + end if; + end process; + +-- Non BRAM (LUT) Version +-- col_rom : entity work.ROM_LUT +-- port map( +-- ADDR => obj_video_out_reg(4 downto 0), +-- DATA => obj_lut_out +-- ); + +-- BRAM Version + col_rom : entity work.ROM_LUT + port map( + CLK => CLK, + ADDR => obj_video_out_reg(4 downto 0), + DATA => obj_lut_out + ); + + p_col_rom_ce : process + variable video : array_3x5; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (vidout_l = '0') then -- cs_l on col rom + video(0)(2 downto 0) := obj_lut_out(7 downto 6) & '0'; -- b + video(1)(2 downto 0) := obj_lut_out(5 downto 3); -- g + video(2)(2 downto 0) := obj_lut_out(2 downto 0); -- r + else + video(0)(2 downto 0) := "000"; + video(1)(2 downto 0) := "000"; + video(2)(2 downto 0) := "000"; + end if; + -- + -- end of direct assigns + -- + if I_HWSEL_FROGGER then + if (frogger_blue_out_reg = '1') and (vidout_l = '1') then + video(0) := video(0) or "010"; + end if; + end if; + + if not I_HWSEL_FROGGER then + if shell_reg = '1' then + video(0) := "110"; -- b + video(1) := "110"; -- g + video(2) := "110"; -- r + elsif missile_reg = '1' then + video(0) := "110"; -- b + video(1) := "000"; -- g + video(2) := "110"; -- r + end if; + end if; + + -- add stars, background and video + if not I_HWSEL_FROGGER then + video(0) := video(0) or ( star_b & '0'); + video(1) := video(1) or ( star_g & '0'); + video(2) := video(2) or ( star_r & '0'); + + if (pout1_reg = '1') and (vidout_l = '1') then + video(0) := video(0) or ("011"); + end if; + end if; + + O_VIDEO_B <= video(0); + O_VIDEO_G <= video(1); + O_VIDEO_R <= video(2); + end if; + end process; + + stars : work.MC_STARS + port map ( + I_CLK => CLK, + I_ENA => ENA_STAR, + I_H_FLIP => '0', + I_V_SYNC => I_VSYNC, + I_8HF => I_HCNT(3), + I_256HnX => h256_l, + I_1VF => I_VCNT(0), + I_2V => I_VCNT(1), + I_STARS_ON => I_STARSON, + I_STARS_OFFn => '1', + + O_R => star_r, + O_G => star_g, + O_B => star_b + ); + + p_frogger_blue_reg : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + if (I_HCNT(7 downto 0) = x"87") then + frogger_blue_reg <= '1'; + elsif (I_HCNT(7 downto 0) = x"07") then + frogger_blue_reg <= '0'; + end if; + end if; + end process; + frogger_blue <= not (frogger_blue_reg xor I_HCMA); + +end RTL; + +------------------------------------------------------------------------------ +-- FPGA STARS +-- +-- Version : 2.00 +-- +-- Copyright(c) 2004 Katsumi Degawa , All rights reserved +-- +-- Important ! +-- +-- This program is freeware for non-commercial use. +-- The author does not guarantee this program. +-- You can use this at your own risk. +-- +------------------------------------------------------------------------------ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity MC_STARS is + port ( + I_CLK : in std_logic; + I_ENA : in std_logic; + I_H_FLIP : in std_logic; + I_V_SYNC : in std_logic; + I_8HF : in std_logic; + I_256HnX : in std_logic; + I_1VF : in std_logic; + I_2V : in std_logic; + I_STARS_ON : in std_logic; + I_STARS_OFFn : in std_logic; + + O_R : out std_logic_vector(1 downto 0); + O_G : out std_logic_vector(1 downto 0); + O_B : out std_logic_vector(1 downto 0); + O_NOISE : out std_logic + ); +end; + +architecture RTL of MC_STARS is + signal CLK_1C : std_logic := '0'; + signal CLK_1Cd : std_logic := '0'; + signal W_2D_Qn : std_logic := '0'; + + signal W_3B : std_logic := '0'; + signal noise : std_logic := '0'; + signal W_2A : std_logic := '0'; + signal W_4P : std_logic := '0'; + signal CLK_1AB : std_logic := '0'; + signal CLK_1ABd : std_logic := '0'; + signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0'); + signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0'); +begin + O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0' and I_256HnX = '1') else (others => '0'); + O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0' and I_256HnX = '1') else (others => '0'); + O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0' and I_256HnX = '1') else (others => '0'); + + CLK_1C <= not (I_ENA and (not I_V_SYNC) and I_256HnX); + CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1)))); + W_3B <= W_2D_Qn xor W_1AB_Q(4); + + W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1'; + W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn); + + O_NOISE <= noise ; + + process(I_2V) + begin + if rising_edge(I_2V) then + noise <= W_2D_Qn; + end if; + end process; + + process(I_CLK, I_V_SYNC) + begin + if(I_V_SYNC = '1') then + W_1C_Q <= (others => '0'); + elsif rising_edge(I_CLK) then + CLK_1Cd <= CLK_1C; + if CLK_1Cd = '0' and CLK_1C = '1' then + W_1C_Q <= W_1C_Q(0) & '1'; + end if; + end if; + end process; + + process(I_CLK, I_STARS_ON) + begin + if(I_STARS_ON = '0') then + W_1AB_Q <= (others => '0'); + W_2D_Qn <= '1'; + elsif rising_edge(I_CLK) then + CLK_1ABd <= CLK_1AB; + if CLK_1ABd = '0' and CLK_1AB = '1' then + W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B; + W_2D_Qn <= not W_1AB_Q(15); + end if; + end if; + end process; +end RTL; diff --git a/Arcade/Scramble Hardware/TheEnd_MiST/rtl/video_mixer.sv b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Arcade/Scramble Hardware/TheEnd_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Commodore - 64_Mist/C64_mist.qpf b/Commodore - 64_Mist/C64_mist.qpf new file mode 100644 index 00000000..6c07b7e4 --- /dev/null +++ b/Commodore - 64_Mist/C64_mist.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 09:30:37 July 09, 2015 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "09:30:37 July 09, 2015" + +# Revisions + +PROJECT_REVISION = "C64_mist" diff --git a/Commodore - 64_Mist/C64_mist.qsf b/Commodore - 64_Mist/C64_mist.qsf new file mode 100644 index 00000000..51757546 --- /dev/null +++ b/Commodore - 64_Mist/C64_mist.qsf @@ -0,0 +1,370 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# Date created = 01:27:30 May 03, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# C64_MiST_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY c64_mist +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON +set_global_assignment -name SAVE_DISK_SPACE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "FAST FIT" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------ +# start ENTITY(C64_MiST) + +# Pin & Location Assignments +# ========================== +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] + +# Fitter Assignments +# ================== +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 + +# start DESIGN_PARTITION(Top) +# --------------------------- + +# Incremental Compilation Assignments +# =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +# end DESIGN_PARTITION(Top) +# ------------------------- + +# end ENTITY(C64_MiST) +# ---------------------- +set_global_assignment -name VHDL_FILE rtl/c64_mist.vhd +set_global_assignment -name VHDL_FILE rtl/sid/wave_map.vhd +set_global_assignment -name VHDL_FILE rtl/sid/sid_top.vhd +set_global_assignment -name VHDL_FILE rtl/sid/sid_regs.vhd +set_global_assignment -name VHDL_FILE rtl/sid/sid_mixer.vhd +set_global_assignment -name VHDL_FILE rtl/sid/sid_filter.vhd +set_global_assignment -name VHDL_FILE rtl/sid/sid_debug_pkg.vhd +set_global_assignment -name VHDL_FILE rtl/sid/sid_ctrl.vhd +set_global_assignment -name VHDL_FILE rtl/sid/Q_table.vhd +set_global_assignment -name VHDL_FILE rtl/sid/oscillator.vhd +set_global_assignment -name VHDL_FILE rtl/sid/my_math_pkg.vhd +set_global_assignment -name VHDL_FILE rtl/sid/mult_acc.vhd +set_global_assignment -name VHDL_FILE rtl/sid/adsr_multi.vhd +set_global_assignment -name VHDL_FILE rtl/video_vicII_656x_e.vhd +set_global_assignment -name VHDL_FILE rtl/video_vicII_656x_a.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/trkbuf.v +set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v +set_global_assignment -name VERILOG_FILE rtl/sdram.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sd_card.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/rom_C1541.vhd +set_global_assignment -name VHDL_FILE rtl/rom_c64_chargen.vhd +set_global_assignment -name VHDL_FILE rtl/rom_C64.vhd +set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VHDL_FILE rtl/m6522.vhd +set_global_assignment -name VHDL_FILE rtl/io_ps2_keyboard.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name VHDL_FILE rtl/gcr_floppy.vhd +set_global_assignment -name VHDL_FILE rtl/fpga64_sid_iec.vhd +set_global_assignment -name VHDL_FILE rtl/fpga64_rgbcolor.vhd +set_global_assignment -name VHDL_FILE rtl/fpga64_keyboard_matrix_mark_mcdougall.vhd +set_global_assignment -name VHDL_FILE rtl/fpga64_bustiming.vhd +set_global_assignment -name VHDL_FILE rtl/fpga64_buslogic_roms_mmu.vhd +set_global_assignment -name VHDL_FILE rtl/cpu65xx_fast.vhd +set_global_assignment -name VHDL_FILE rtl/cpu65xx_e.vhd +set_global_assignment -name VHDL_FILE rtl/cpu_6510.vhd +set_global_assignment -name VHDL_FILE rtl/composite_sync.vhd +set_global_assignment -name VHDL_FILE rtl/cia6526.vhd +set_global_assignment -name VERILOG_FILE rtl/cartridge.v +set_global_assignment -name VHDL_FILE rtl/c1541_sd.vhd +set_global_assignment -name VHDL_FILE rtl/c1541_logic.vhd +set_global_assignment -name VHDL_FILE rtl/rom_GS64.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Commodore - 64_Mist/README.txt b/Commodore - 64_Mist/README.txt new file mode 100644 index 00000000..e43d2daf --- /dev/null +++ b/Commodore - 64_Mist/README.txt @@ -0,0 +1,56 @@ +--------------------------------------------------------------------------------- +-- FPGA64_027 and 1541_SD by Dar (darfpga@aol.fr) release 0001- 26/07/2015 +-- +-- http://darfpga.blogspot.fr +-- +-- FPGA64 is Copyrighted 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Main features +-- 15KHz(TV) / 31Khz(VGA) +-- PAL(50Hz) / NTSC(60Hz) +-- PS2 keyboard input with portA / portB joystick emulation +-- SID sound output +-- +-- +-- Internal emulated 1541 on raw SD card (READ ONLY) : D64 images start at 256KB boundaries +-- Use hexadecimal disk editor such as HxD (www.mh-nexus.de) to build SD card. +-- Cut D64 file and paste at 0x00000 (first), 0x40000 (second), 0x80000 (third), +-- 0xC0000(fourth), 0x100000(fith), 0x140000 (sixth) and so on. +-- BE CAREFUL NOT WRITING ON YOUR OWN HARDDRIVE +-- +-- Use only SIMPLE D64 files : 174 848 octets (without disk error management) +-- +--------------------------------------------------------------------------------- +-- +-- c1541_sd reads D64 data from raw SD card, produces GCR data, feeds c1541_logic +-- Raw SD data : each D64 image must start on 256KB boundaries +-- disk_num allow to select D64 image +-- +-- c1541_logic from : Mark McDougall +-- spi_controller from : Michel Stempin, Stephen A. Edwards +-- via6522 from : Arnim Laeuger, Mark McDougall, MikeJ +-- T65 from : Daniel Wallner, MikeJ, ehenciak +-- +-- c1541_logic modified for : slow down CPU (EOI ack missed by real c64) +-- : remove IEC internal OR wired +-- : synched atn_in (sometime no IRQ to CPU with real c64) +-- spi_controller modified for : sector start and size adapted + busy signal +-- via6522 modified for : no modification +-- +--------------------------------------------------------------------------------- + +FPGA64_027 Keyboard specific keys : + + Escape : run stop + [ : @ + ] : * + \ : up arrow + ' : semi colon + ` : left arrow + F9 : £ + F10 : + + Left Alt : commodore key + + +END diff --git a/Commodore - 64_Mist/c64_mist.sdc b/Commodore - 64_Mist/c64_mist.sdc new file mode 100644 index 00000000..3eba3b05 --- /dev/null +++ b/Commodore - 64_Mist/c64_mist.sdc @@ -0,0 +1,33 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# +#************************************************************ + +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] +create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty diff --git a/Commodore - 64_Mist/clean.bat b/Commodore - 64_Mist/clean.bat new file mode 100644 index 00000000..d76d65c1 --- /dev/null +++ b/Commodore - 64_Mist/clean.bat @@ -0,0 +1,13 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +pause diff --git a/Commodore - 64_Mist/release/C64GS_mist.rbf b/Commodore - 64_Mist/release/C64GS_mist.rbf new file mode 100644 index 00000000..db2383f0 Binary files /dev/null and b/Commodore - 64_Mist/release/C64GS_mist.rbf differ diff --git a/Commodore - 64_Mist/release/C64_mist.rbf b/Commodore - 64_Mist/release/C64_mist.rbf new file mode 100644 index 00000000..0a012e95 Binary files /dev/null and b/Commodore - 64_Mist/release/C64_mist.rbf differ diff --git a/Commodore - 64_Mist/rtl/c1541_logic.vhd b/Commodore - 64_Mist/rtl/c1541_logic.vhd new file mode 100644 index 00000000..82364fe2 --- /dev/null +++ b/Commodore - 64_Mist/rtl/c1541_logic.vhd @@ -0,0 +1,366 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +--use work.platform_pkg.all; +--use work.project_pkg.all; + +-- +-- Model 1541B +-- + +entity c1541_logic is +port +( + clk_32M : in std_logic; + reset : in std_logic; + + -- serial bus + sb_data_oe : out std_logic; + sb_data_in : in std_logic; + sb_clk_oe : out std_logic; + sb_clk_in : in std_logic; + sb_atn_oe : out std_logic; + sb_atn_in : in std_logic; + + c1541rom_addr : in std_logic_vector(13 downto 0); + c1541rom_data : in std_logic_vector(7 downto 0); + c1541rom_wr : in std_logic; + + -- drive-side interface + ds : in std_logic_vector(1 downto 0); -- device select + di : in std_logic_vector(7 downto 0); -- disk read data + do : out std_logic_vector(7 downto 0); -- disk write data + mode : out std_logic; -- read/write + stp : out std_logic_vector(1 downto 0); -- stepper motor control + mtr : out std_logic; -- stepper motor on/off + freq : out std_logic_vector(1 downto 0); -- motor frequency + sync_n : in std_logic; -- reading SYNC bytes + byte_n : in std_logic; -- byte ready + wps_n : in std_logic; -- write-protect sense + tr00_sense_n : in std_logic; -- track 0 sense (unused?) + act : out std_logic -- activity LED +); +end c1541_logic; + +architecture SYN of c1541_logic is + + -- clocks, reset + signal reset_n : std_logic; + signal clk_4M_en : std_logic; + signal p2_h : std_logic; + signal clk_1M_pulse : std_logic; + + -- cpu signals + signal cpu_a : unsigned(15 downto 0); + signal cpu_di : unsigned(7 downto 0); + signal cpu_do : unsigned(7 downto 0); + signal cpu_a_l : std_logic_vector(23 downto 0); + signal cpu_do_l : std_logic_vector(7 downto 0); + signal cpu_rw : std_logic; + signal cpu_rw_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_so_n : std_logic; + + -- rom signals + signal rom_cs : std_logic; + signal rom_do : std_logic_vector(cpu_di'range); + + -- ram signals + signal ram_cs : std_logic; + signal ram_wr : std_logic; + signal ram_do : std_logic_vector(cpu_di'range); + + -- UC1 (VIA6522) signals + signal uc1_do : std_logic_vector(7 downto 0); + signal uc1_cs1 : std_logic; + signal uc1_cs2_n : std_logic; + signal uc1_irq_n : std_logic; + signal uc1_ca1_i : std_logic; + signal uc1_pa_i : std_logic_vector(7 downto 0); + signal uc1_pb_i : std_logic_vector(7 downto 0) := (others => '0'); + signal uc1_pb_o : std_logic_vector(7 downto 0); + signal uc1_pb_oe_n : std_logic_vector(7 downto 0); + + -- UC3 (VIA6522) signals + signal uc3_do : std_logic_vector(7 downto 0); + signal uc3_cs1 : std_logic; + signal uc3_cs2_n : std_logic; + signal uc3_irq_n : std_logic; + signal uc3_ca1_i : std_logic; + signal uc3_ca2_o : std_logic; + signal uc3_ca2_oe_n : std_logic; + signal uc3_pa_i : std_logic_vector(7 downto 0); + signal uc3_pa_o : std_logic_vector(7 downto 0); + signal uc3_cb2_o : std_logic; + signal uc3_cb2_oe_n : std_logic; + signal uc3_pa_oe_n : std_logic_vector(7 downto 0); + signal uc3_pb_i : std_logic_vector(7 downto 0); + signal uc3_pb_o : std_logic_vector(7 downto 0); + signal uc3_pb_oe_n : std_logic_vector(7 downto 0); + + -- internal signals + signal atna : std_logic; -- ATN ACK - input gate array + signal atn : std_logic; -- attention + signal soe : std_logic; -- set overflow enable + + type t_byte_array is array(2047 downto 0) of std_logic_vector(7 downto 0); + signal ram : t_byte_array; + +begin + + reset_n <= not reset; + + process (clk_32M, reset) + variable count : std_logic_vector(8 downto 0) := (others => '0'); + alias hcnt : std_logic_vector(1 downto 0) is count(4 downto 3); + begin + if rising_edge(clk_32M) then + -- generate 1MHz pulse + clk_1M_pulse <= '0'; + --if count(4 downto 0) = "00111" then + if count(4 downto 0) = "01000" then + clk_1M_pulse <= '1'; + end if; + -- if count = "000100000" then -- DAR divide by 33 (otherwise real c64 miss EOI acknowledge) + if count = "000011111" then -- TH: divide by 32 + count := (others => '0'); -- DAR + else -- DAR + count := std_logic_vector(unsigned(count) + 1); + end if; -- DAR + end if; + p2_h <= not hcnt(1); + + -- for original m6522 design that requires a real clock +-- clk_4M_en <= not count(2); + + -- for version 002 with clock enable + if count(2 downto 0) = "111" then + clk_4M_en <= '1'; + else + clk_4M_en <= '0'; + end if; + end process; + + -- decode logic + -- RAM $0000-$07FF (2KB) + ram_cs <= '1' when STD_MATCH(cpu_a(15 downto 0), "00000-----------") else '0'; + -- UC1 (VIA6522) $1800-$180F + uc1_cs2_n <= '0' when STD_MATCH(cpu_a(15 downto 0), "000110000000----") else '1'; + -- UC3 (VIA6522) $1C00-$1C0F + uc3_cs2_n <= '0' when STD_MATCH(cpu_a(15 downto 0), "000111000000----") else '1'; + -- ROM $C000-$FFFF (16KB) + rom_cs <= '1' when STD_MATCH(cpu_a(15 downto 0), "11--------------") else '0'; + + -- qualified write signals + ram_wr <= '1' when ram_cs = '1' and cpu_rw = '1' else '0'; + + -- + -- hook up UC1 ports + -- + + uc1_cs1 <= cpu_a(11); + --uc1_cs2_n: see decode logic above + -- CA1 + --uc1_ca1_i <= not sb_atn_in; -- DAR comment : synched with clk_4M_en see below + -- PA + uc1_pa_i(0) <= tr00_sense_n; + uc1_pa_i(7 downto 1) <= (others => '0'); -- NC + -- PB + uc1_pb_i(0) <= '1' when sb_data_in = '0' else + '1' when (uc1_pb_o(1) = '1' and uc1_pb_oe_n(1) = '0') else -- DAR comment : external OR wired + '1' when atn = '1' else -- DAR comment : external OR wired + '0'; + sb_data_oe <= '1' when (uc1_pb_o(1) = '1' and uc1_pb_oe_n(1) = '0') else + '1' when atn = '1' else + '0'; + uc1_pb_i(2) <= '1' when sb_clk_in = '0' else + '1' when (uc1_pb_o(3) = '1' and uc1_pb_oe_n(3) = '0') else -- DAR comment : external OR wired + '0'; + sb_clk_oe <= '1' when (uc1_pb_o(3) = '1' and uc1_pb_oe_n(3) = '0') else '0'; + + atna <= uc1_pb_o(4); -- when uc1_pc_oe = '1' + uc1_pb_i(6 downto 5) <= ds; -- allows override + uc1_pb_i(7) <= not sb_atn_in; + + -- + -- hook up UC3 ports + -- + + uc3_cs1 <= cpu_a(11); + --uc3_cs2_n: see decode logic above + -- CA1 + uc3_ca1_i <= cpu_so_n; -- byte ready gated with soe + -- CA2 + soe <= uc3_ca2_o or uc3_ca2_oe_n; + -- PA + uc3_pa_i <= di; + do <= uc3_pa_o or uc3_pa_oe_n; + -- CB2 + mode <= uc3_cb2_o or uc3_cb2_oe_n; + -- PB + stp(1) <= uc3_pb_o(0) or uc3_pb_oe_n(0); + stp(0) <= uc3_pb_o(1) or uc3_pb_oe_n(1); + mtr <= uc3_pb_o(2) or uc3_pb_oe_n(2); + act <= uc3_pb_o(3) or uc3_pb_oe_n(3); + freq <= uc3_pb_o(6 downto 5) or uc3_pb_oe_n(6 downto 5); + uc3_pb_i <= sync_n & "11" & wps_n & "1111"; + + -- + -- CPU connections + -- + cpu_di <= unsigned(rom_do) when rom_cs = '1' else + unsigned(ram_do) when ram_cs = '1' else + unsigned(uc1_do) when (uc1_cs1 = '1' and uc1_cs2_n = '0') else + unsigned(uc3_do) when (uc3_cs1 = '1' and uc3_cs2_n = '0') else + (others => '1'); + cpu_irq_n <= uc1_irq_n and uc3_irq_n; + cpu_so_n <= byte_n or not soe; + + -- internal connections + atn <= atna xor (not sb_atn_in); + + -- external connections + -- ATN never driven by the 1541 + sb_atn_oe <= '0'; + + + -- DAR + process (clk_32M) + begin + if rising_edge(clk_32M) then + if clk_4M_en = '1' then + uc1_ca1_i <= not sb_atn_in; -- DAR sample external atn to ensure not missing edge within VIA + end if; + end if; + end process; + + cpu: entity work.cpu65xx + generic map ( + pipelineOpcode => false, + pipelineAluMux => false, + pipelineAluOut => false + ) + port map ( + clk => clk_32M, + enable => clk_1M_pulse, + reset => reset, + nmi_n => '1', + irq_n => cpu_irq_n, + so_n => cpu_so_n, + di => cpu_di, + do => cpu_do, + addr => cpu_a, + we => cpu_rw + ); + + rom_inst: entity work.rom_C1541 + port map ( + clock => clk_32M, + + wren => c1541rom_wr, + data => c1541rom_data, + wraddress => c1541rom_addr, + + rdaddress => std_logic_vector(cpu_a(13 downto 0)), + q => rom_do + ); + + process (clk_32M) + begin + if rising_edge(clk_32M) then + ram_do <= ram(to_integer(cpu_a(13 downto 0))); + if ram_wr = '1' then + ram(to_integer(cpu_a(13 downto 0))) <= std_logic_vector(cpu_do); + end if; + end if; + end process; + + + uc1_via6522_inst : entity work.M6522 + port map + ( + I_RS => std_logic_vector(cpu_a(3 downto 0)), + I_DATA => std_logic_vector(cpu_do), + O_DATA => uc1_do, + O_DATA_OE_L => open, + + I_RW_L => not cpu_rw, + I_CS1 => uc1_cs1, + I_CS2_L => uc1_cs2_n, + + O_IRQ_L => uc1_irq_n, + + -- port a + I_CA1 => uc1_ca1_i, + I_CA2 => '0', + O_CA2 => open, + O_CA2_OE_L => open, + + I_PA => uc1_pa_i, + O_PA => open, + O_PA_OE_L => open, + + -- port b + I_CB1 => '0', + O_CB1 => open, + O_CB1_OE_L => open, + + I_CB2 => '0', + O_CB2 => open, + O_CB2_OE_L => open, + + I_PB => uc1_pb_i, + O_PB => uc1_pb_o, + O_PB_OE_L => uc1_pb_oe_n, + + RESET_L => reset_n, + CLK => clk_32M, + I_P2_H => p2_h, -- high for phase 2 clock ____----__ + ENA_4 => clk_4M_en -- 4x system clock (4MHZ) _-_-_-_-_- + ); + + uc3_via6522_inst : entity work.M6522 + port map + ( + I_RS => std_logic_vector(cpu_a(3 downto 0)), + I_DATA => std_logic_vector(cpu_do), + O_DATA => uc3_do, + O_DATA_OE_L => open, + + I_RW_L => not cpu_rw, + I_CS1 => cpu_a(11), + I_CS2_L => uc3_cs2_n, + + O_IRQ_L => uc3_irq_n, + + -- port a + I_CA1 => uc3_ca1_i, + I_CA2 => '0', + O_CA2 => uc3_ca2_o, + O_CA2_OE_L => uc3_ca2_oe_n, + + I_PA => uc3_pa_i, + O_PA => uc3_pa_o, + O_PA_OE_L => uc3_pa_oe_n, + + -- port b + I_CB1 => '0', + O_CB1 => open, + O_CB1_OE_L => open, + + I_CB2 => '0', + O_CB2 => uc3_cb2_o, + O_CB2_OE_L => uc3_cb2_oe_n, + + I_PB => uc3_pb_i, + O_PB => uc3_pb_o, + O_PB_OE_L => uc3_pb_oe_n, + + RESET_L => reset_n, + CLK => clk_32M, + I_P2_H => p2_h, -- high for phase 2 clock ____----__ + ENA_4 => clk_4M_en -- 4x system clock (4MHZ) _-_-_-_-_- + ); + +end SYN; diff --git a/Commodore - 64_Mist/rtl/c1541_sd.vhd b/Commodore - 64_Mist/rtl/c1541_sd.vhd new file mode 100644 index 00000000..d2ed45c0 --- /dev/null +++ b/Commodore - 64_Mist/rtl/c1541_sd.vhd @@ -0,0 +1,266 @@ +--------------------------------------------------------------------------------- +-- Commodore 1541 to SD card (read only) by Dar (darfpga@aol.fr) 02-April-2015 +-- http://darfpga.blogspot.fr +-- +-- c1541_sd reads D64 data from raw SD card, produces GCR data, feeds c1541_logic +-- Raw SD data : each D64 image must start on 256KB boundaries +-- disk_num allow to select D64 image +-- +-- c1541_logic from : Mark McDougall +-- spi_controller from : Michel Stempin, Stephen A. Edwards +-- via6522 from : Arnim Laeuger, Mark McDougall, MikeJ +-- +-- c1541_logic modified for : slow down CPU (EOI ack missed by real c64) +-- : remove iec internal OR wired +-- : synched atn_in (sometime no IRQ with real c64) +-- spi_controller modified for : sector start and size adapted + busy signal +-- via6522 modified for : no modification +-- +-- +-- Input clk 32MHz +-- +--------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.all; + +entity c1541_sd is +port +( + clk32 : in std_logic; + reset : in std_logic; + + disk_change : in std_logic; + disk_readonly : in std_logic; + + iec_atn_i : in std_logic; + iec_data_i : in std_logic; + iec_clk_i : in std_logic; + + iec_atn_o : out std_logic; + iec_data_o : out std_logic; + iec_clk_o : out std_logic; + + sd_lba : out std_logic_vector(31 downto 0); + sd_rd : out std_logic; + sd_wr : out std_logic; + sd_ack : in std_logic; + sd_ack_conf : in std_logic; + + sd_sdhc : out std_logic; + sd_conf : out std_logic; + sd_buff_addr : in std_logic_vector(8 downto 0); + sd_buff_dout : in std_logic_vector(7 downto 0); + sd_buff_din : out std_logic_vector(7 downto 0); + sd_buff_wr : in std_logic; + + led : out std_logic; + + c1541rom_addr : in std_logic_vector(13 downto 0); + c1541rom_data : in std_logic_vector(7 downto 0); + c1541rom_wr : in std_logic +); +end c1541_sd; + +architecture struct of c1541_sd is + + component sd_card port + ( + sd_lba : out std_logic_vector(31 downto 0); + sd_rd : out std_logic; + sd_wr : out std_logic; + sd_ack : in std_logic; + sd_ack_conf : in std_logic; + sd_sdhc : out std_logic; + sd_conf : out std_logic; + + sd_buff_addr : in std_logic_vector(8 downto 0); + sd_buff_dout : in std_logic_vector(7 downto 0); + sd_buff_din : out std_logic_vector(7 downto 0); + sd_buff_wr : in std_logic; + + buff_addr : in std_logic_vector(7 downto 0); + buff_dout : out std_logic_vector(7 downto 0); + buff_din : in std_logic_vector(7 downto 0); + buff_we : in std_logic; + + save_track : in std_logic; + + change : in std_logic; -- Force reload as disk may have changed + track : in std_logic_vector(5 downto 0); -- Track number (0-34) + sector : in std_logic_vector(4 downto 0); -- Sector number (0-20) + busy : out std_logic; + + clk : in std_logic; -- System clock + reset : in std_logic + ); + end component sd_card; + + signal buff_dout : std_logic_vector(7 downto 0); + signal buff_din : std_logic_vector(7 downto 0); + signal buff_we : std_logic; + signal do : std_logic_vector(7 downto 0); -- disk read data + signal di : std_logic_vector(7 downto 0); -- disk write data + signal mode : std_logic; -- read/write + signal stp : std_logic_vector(1 downto 0); -- stepper motor control + signal stp_r : std_logic_vector(1 downto 0); -- stepper motor control + signal mtr : std_logic ; -- stepper motor on/off + signal sync_n : std_logic; -- reading SYNC bytes + signal byte_n : std_logic; -- byte ready + signal act : std_logic; -- activity LED + signal act_r : std_logic; -- activity LED + signal sd_busy : std_logic; + signal sector : std_logic_vector(4 downto 0); + signal byte_addr : std_logic_vector(7 downto 0); + signal track_num_dbl : std_logic_vector(6 downto 0); + signal track : std_logic_vector(5 downto 0); + + signal tr00_sense_n : std_logic; + signal save_track : std_logic; + signal track_modified : std_logic; + +begin + + tr00_sense_n <= '1' when (track > "000000") else '0'; + + c1541 : entity work.c1541_logic + port map + ( + clk_32M => clk32, + reset => reset, + + -- serial bus + sb_data_oe => iec_data_o, + sb_clk_oe => iec_clk_o, + sb_atn_oe => iec_atn_o, + + sb_data_in => not iec_data_i, + sb_clk_in => not iec_clk_i, + sb_atn_in => not iec_atn_i, + + c1541rom_addr => c1541rom_addr, + c1541rom_data => c1541rom_data, + c1541rom_wr => c1541rom_wr, + + -- drive-side interface + ds => "00", -- device select + di => do, -- disk read data + do => di, -- disk write data + mode => mode, -- read/write + stp => stp, -- stepper motor control + mtr => mtr, -- motor on/off + freq => open, -- motor frequency + sync_n => sync_n, -- reading SYNC bytes + byte_n => byte_n, -- byte ready + wps_n => not disk_readonly, -- write-protect sense + tr00_sense_n => tr00_sense_n, -- track 0 sense (unused?) + act => act -- activity LED + ); + + floppy : entity work.gcr_floppy + port map + ( + clk32 => clk32, + + dout => do, -- disk read data + din => di, + mode => mode, + mtr => mtr, -- stepper motor on/off + sync_n => sync_n, -- reading SYNC bytes + byte_n => byte_n, -- byte ready + + track => track, + sector => sector, + + byte_addr => byte_addr, + + ram_do => buff_dout, + ram_di => buff_din, + ram_we => buff_we, + + ram_ready => not sd_busy + ); + + sd : sd_card + port map + ( + sd_lba => sd_lba, + sd_rd => sd_rd, + sd_wr => sd_wr, + sd_ack => sd_ack, + sd_conf => sd_conf, + sd_sdhc => sd_sdhc, + sd_ack_conf => sd_ack_conf, + + sd_buff_addr => sd_buff_addr, + sd_buff_dout => sd_buff_dout, + sd_buff_din => sd_buff_din, + sd_buff_wr => sd_buff_wr, + + buff_addr => byte_addr, + buff_dout => buff_dout, + buff_din => buff_din, + buff_we => buff_we, + + save_track => save_track, + change => disk_change, + track => track, + sector => sector, + + clk => clk32, + reset => reset, + busy => sd_busy + ); + + led <= act or sd_busy; + + process (clk32) + begin + if rising_edge(clk32) then + stp_r <= stp; + act_r <= act; + save_track <= '0'; + track <= track_num_dbl(6 downto 1); + + if buff_we = '1' then track_modified <= '1'; end if; + if disk_change = '1' then track_modified <= '0'; end if; + + if reset = '1' then + track_num_dbl <= "0100100";--"0000010"; + track_modified <= '0'; + else + if mtr = '1' then + if( (stp_r = "00" and stp = "10") + or (stp_r = "10" and stp = "01") + or (stp_r = "01" and stp = "11") + or (stp_r = "11" and stp = "00")) then + if track_num_dbl < "1010000" then + track_num_dbl <= track_num_dbl + '1'; + end if; + save_track <= track_modified; + track_modified <= '0'; + end if; + + if( (stp_r = "00" and stp = "11") + or (stp_r = "10" and stp = "00") + or (stp_r = "01" and stp = "10") + or (stp_r = "11" and stp = "01")) then + if track_num_dbl > "0000001" then + track_num_dbl <= track_num_dbl - '1'; + end if; + save_track <= track_modified; + track_modified <= '0'; + end if; + end if; + + if act_r = '1' and act = '0' then -- stopping activity + save_track <= track_modified; + track_modified <= '0'; + end if; + end if; + end if; -- rising edge clock + end process; + +end struct; diff --git a/Commodore - 64_Mist/rtl/c64_mist.vhd b/Commodore - 64_Mist/rtl/c64_mist.vhd new file mode 100644 index 00000000..ece31cac --- /dev/null +++ b/Commodore - 64_Mist/rtl/c64_mist.vhd @@ -0,0 +1,1012 @@ +--------------------------------------------------------------------------------- +-- DE2-35 Top level for FPGA64_027 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- +-- FPGA64 is Copyrighted 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Main features +-- 15KHz(TV) / 31Khz(VGA) : board switch(0) +-- PAL(50Hz) / NTSC(60Hz) : board switch(1) and F12 key +-- PS2 keyboard input with portA / portB joystick emulation : F11 key +-- wm8731 sound output +-- 64Ko of board SRAM used +-- External IEC bus available at gpio_1 (for drive 1541 or IEC/SD ...) +-- activated by switch(5) (activated with no hardware will stuck IEC bus) +-- +-- Internal emulated 1541 on raw SD card : D64 images start at 25x6KB boundaries +-- Use hexidecimal disk editor such as HxD (www.mh-nexus.de) to build SD card. +-- Cut D64 file and paste at 0x00000 (first), 0x40000 (second), 0x80000 (third), +-- 0xC0000(fourth), 0x100000(fith), 0x140000 (sixth) and so on. +-- BE CAREFUL NOT WRITING ON YOUR OWN HARDDRIVE +-- +-- Uses only one pll for 32MHz and 18MHz generation from 50MHz +-- DE1 and DE0 nano Top level also available +-- +--------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.all; + +entity c64_mist is port +( + -- Clocks + CLOCK_27 : in std_logic; + + -- LED + LED : out std_logic; + + -- VGA + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0); + VGA_HS : out std_logic; + VGA_VS : out std_logic; + + -- SDRAM + SDRAM_A : out std_logic_vector(12 downto 0); + SDRAM_DQ : inout std_logic_vector(15 downto 0); + SDRAM_DQML : out std_logic; + SDRAM_DQMH : out std_logic; + SDRAM_nWE : out std_logic; + SDRAM_nCAS : out std_logic; + SDRAM_nRAS : out std_logic; + SDRAM_nCS : out std_logic; + SDRAM_BA : out std_logic_vector(1 downto 0); + SDRAM_CLK : out std_logic; + SDRAM_CKE : out std_logic; + + -- AUDIO + AUDIO_L : out std_logic; + AUDIO_R : out std_logic; + + -- SPI interface to io controller + SPI_SCK : in std_logic; + SPI_DO : inout std_logic; + SPI_DI : in std_logic; + SPI_SS2 : in std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic +); +end c64_mist; + +architecture struct of c64_mist is + +component sdram is port +( + -- interface to the MT48LC16M16 chip + sd_addr : out std_logic_vector(12 downto 0); + sd_cs : out std_logic; + sd_ba : out std_logic_vector(1 downto 0); + sd_we : out std_logic; + sd_ras : out std_logic; + sd_cas : out std_logic; + + -- system interface + clk : in std_logic; + init : in std_logic; + + -- cpu/chipset interface + addr : in std_logic_vector(24 downto 0); + refresh : in std_logic; + we : in std_logic; + ce : in std_logic +); +end component; + +component sram is port +( + init : in std_logic; + clk : in std_logic; + SDRAM_DQ : inout std_logic_vector(15 downto 0); + SDRAM_A : out std_logic_vector(12 downto 0); + SDRAM_DQML : out std_logic; + SDRAM_DQMH : out std_logic; + SDRAM_BA : out std_logic_vector(1 downto 0); + SDRAM_nCS : out std_logic; + SDRAM_nWE : out std_logic; + SDRAM_nRAS : out std_logic; + SDRAM_nCAS : out std_logic; + SDRAM_CKE : out std_logic; + + wtbt : in std_logic_vector(1 downto 0); + addr : in std_logic_vector(24 downto 0); + dout : out std_logic_vector(15 downto 0); + din : in std_logic_vector(15 downto 0); + we : in std_logic; + rd : in std_logic; + ready : out std_logic +); +end component; + +--------- +-- Mist IO +--------- + +-- config string used by the io controller to fill the OSD +--constant CONF_STR : string := "C64;PRG;S1,D64;O2,Video standard,PAL,NTSC;O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;O3,Joysticks,normal,swapped;O6,Audio filter,On,Off;T5,Reset;V0,v0.27.33"; +constant CONF_STR : string := "C64;;"& +"S,D64,Mount Disk;"& +"F,PRG,Load File;"& +"F,CRT,Load Cartridge;" & +"O2,Video standard,PAL,NTSC;"& +"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"& +"O3,Joysticks,normal,swapped;"& +"O6,Audio filter,On,Off;"& +--"OB,BIOS,C64,C64GS;" & +--"T5,Reset;"& +"V0,v0.30.30"; + +-- convert string to std_logic_vector to be given to user_io +function to_slv(s: string) return std_logic_vector is + constant ss: string(1 to s'length) := s; + variable rval: std_logic_vector(1 to 8 * s'length); + variable p: integer; + variable c: integer; +begin + for i in ss'range loop + p := 8 * i; + c := character'pos(ss(i)); + rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); + end loop; + return rval; +end function; + + +component mist_io generic(STRLEN : integer := 0 ); port +( + clk_sys : in std_logic; + + SPI_SCK : in std_logic; + CONF_DATA0 : in std_logic; + SPI_SS2 : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + conf_str : in std_logic_vector(8*STRLEN-1 downto 0); + + switches : out std_logic_vector(1 downto 0); + buttons : out std_logic_vector(1 downto 0); + scandoubler_disable : out std_logic; + ypbpr : out std_logic; + + joystick_0 : out std_logic_vector(7 downto 0); + joystick_1 : out std_logic_vector(7 downto 0); + joystick_analog_0 : out std_logic_vector(15 downto 0); + joystick_analog_1 : out std_logic_vector(15 downto 0); + status : out std_logic_vector(31 downto 0); + + sd_lba : in std_logic_vector(31 downto 0); + sd_rd : in std_logic; + sd_wr : in std_logic; + sd_ack : out std_logic; + sd_ack_conf : out std_logic; + sd_conf : in std_logic; + sd_sdhc : in std_logic; + img_mounted : out std_logic; + + sd_buff_addr : out std_logic_vector(8 downto 0); + sd_buff_dout : out std_logic_vector(7 downto 0); + sd_buff_din : in std_logic_vector(7 downto 0); + sd_buff_wr : out std_logic; + + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic; + + ps2_mouse_clk : out std_logic; + ps2_mouse_data : out std_logic; + + ioctl_force_erase : in std_logic; + ioctl_download : out std_logic; + ioctl_erasing : out std_logic; + ioctl_index : out std_logic_vector(7 downto 0); + ioctl_wr : out std_logic; + ioctl_addr : out std_logic_vector(24 downto 0); + ioctl_dout : out std_logic_vector(7 downto 0) + ); +end component mist_io; + +component video_mixer + generic ( LINE_LENGTH : integer := 512; HALF_DEPTH : integer := 0 ); + port ( + clk_sys, ce_pix, ce_pix_actual : in std_logic; + SPI_SCK, SPI_SS3, SPI_DI : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; + + R, G, B : in std_logic_vector(5 downto 0); + HSync, VSync, line_start, mono : in std_logic; + + VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); + VGA_VS, VGA_HS : out std_logic + ); +end component video_mixer; + +--------- +-- OSD +--------- + +component osd generic ( OSD_COLOR : std_logic_vector(2 downto 0)); port +( + clk_sys : in std_logic; + ce_pix : in std_logic; + + SPI_SCK : in std_logic; + SPI_SS3 : in std_logic; + SPI_DI : in std_logic; + + -- VGA signals coming from core + VGA_Rx : in std_logic_vector(5 downto 0); + VGA_Gx : in std_logic_vector(5 downto 0); + VGA_Bx : in std_logic_vector(5 downto 0); + OSD_HS : in std_logic; + OSD_VS : in std_logic; + + -- VGA signals going to video connector + VGA_R : out std_logic_vector(5 downto 0); + VGA_G : out std_logic_vector(5 downto 0); + VGA_B : out std_logic_vector(5 downto 0) +); +end component osd; + +--------- +-- Scan doubler +--------- +component scandoubler is port +( + clk_sys : in std_logic; + ce_x2 : in std_logic; + ce_x1 : in std_logic; + scanlines : in std_logic_vector(1 downto 0); + + -- c64 input + r_in : in std_logic_vector(5 downto 0); + g_in : in std_logic_vector(5 downto 0); + b_in : in std_logic_vector(5 downto 0); + hs_in : in std_logic; + vs_in : in std_logic; + + -- vga output + r_out : out std_logic_vector(5 downto 0); + g_out : out std_logic_vector(5 downto 0); + b_out : out std_logic_vector(5 downto 0); + hs_out : out std_logic; + vs_out : out std_logic +); +end component; + +--------- +-- audio +--------- + +component sigma_delta_dac port +( + CLK : in std_logic; + RESET : in std_logic; + DACin : in std_logic_vector(14 downto 0); + DACout : out std_logic +); + +end component sigma_delta_dac; + + +-------------------------- +-- cartridge - LCA mar17 - +-------------------------- +component cartridge port +( + romL : in std_logic; -- romL signal in + romH : in std_logic; -- romH signal in + UMAXromH : in std_logic; -- VIC II ultimax read access flag + mem_write : in std_logic; -- memory write active + mem_ce : in std_logic; + mem_ce_out : out std_logic; + IOE : in std_logic; -- IOE signal &DE00 + IOF : in std_logic; -- IOF signal &DF00 + + clk32 : in std_logic; -- 32mhz clock source + reset : in std_logic; -- reset signal + reset_out : out std_logic; -- reset signal + + cart_id : in std_logic_vector(15 downto 0); -- cart ID or cart type + cart_exrom : in std_logic_vector(7 downto 0); -- CRT file EXROM status + cart_game : in std_logic_vector(7 downto 0); -- CRT file GAME status + + cart_bank_laddr : in std_logic_vector(15 downto 0); -- 1st bank loading address + cart_bank_size : in std_logic_vector(15 downto 0); -- length of each bank + cart_bank_num : in std_logic_vector(15 downto 0); + cart_bank_type : in std_logic_vector(7 downto 0); + cart_bank_raddr : in std_logic_vector(24 downto 0); -- chip packet address + cart_bank_wr : in std_logic; + + cart_attached: in std_logic; -- FLAG to say cart has been loaded + cart_loading : in std_logic; + + c64_mem_address_in: in std_logic_vector(15 downto 0); -- address from cpu + c64_data_out: in std_logic_vector(7 downto 0); -- data from cpu going to sdram + + sdram_address_out: out std_logic_vector(24 downto 0); -- translated address output + exrom : out std_logic; -- exrom line + game : out std_logic; -- game line + IOE_ena : out std_logic; + IOF_ena : out std_logic; + max_ram : out std_logic; + freeze_key : in std_logic; + nmi : out std_logic; + nmi_ack : in std_logic +); + +end component cartridge; + + signal pll_locked_in: std_logic_vector(1 downto 0); + signal pll_locked: std_logic; + signal c1541_reset: std_logic; + signal idle: std_logic; + signal ces: std_logic_vector(3 downto 0); + signal iec_cycle: std_logic; + signal iec_cycleD: std_logic; + signal buttons: std_logic_vector(1 downto 0); + + -- signals to connect "data_io" for direct PRG injection + signal ioctl_wr: std_logic; + signal ioctl_addr: std_logic_vector(24 downto 0); + signal ioctl_data: std_logic_vector(7 downto 0); + signal ioctl_index: std_logic_vector(7 downto 0); + signal ioctl_ram_addr: std_logic_vector(24 downto 0); + signal ioctl_ram_data: std_logic_vector(7 downto 0); + signal ioctl_load_addr : std_logic_vector(24 downto 0); + signal ioctl_ram_wr: std_logic; + signal ioctl_iec_cycle_used: std_logic; + signal ioctl_force_erase: std_logic; + signal ioctl_erasing: std_logic; + signal ioctl_download: std_logic; + signal c64_addr: std_logic_vector(15 downto 0); + signal c64_data_in: std_logic_vector(7 downto 0); + signal c64_data_out: std_logic_vector(7 downto 0); + signal sdram_addr: std_logic_vector(24 downto 0); + signal sdram_data_out: std_logic_vector(7 downto 0); + + + +-- cartridge signals LCA + signal cart_id : std_logic_vector(15 downto 0); -- cart ID or cart type + signal cart_bank_laddr : std_logic_vector(15 downto 0) := (others => '0'); -- 1st bank loading address + signal cart_bank_size : std_logic_vector(15 downto 0) := (others => '0'); -- length of each bank + signal cart_bank_num : std_logic_vector(15 downto 0) := (others => '0'); -- bank number + signal cart_bank_type : std_logic_vector(7 downto 0) := (others => '0'); -- bank type + signal cart_exrom : std_logic_vector(7 downto 0); -- CRT file EXROM status + signal cart_game : std_logic_vector(7 downto 0); -- CRT file GAME status + signal cart_attached : std_logic; + signal game : std_logic; -- game line to cpu + signal exrom : std_logic; -- exrom line to cpu + signal IOE_rom : std_logic; + signal IOF_rom : std_logic; + signal max_ram : std_logic; + signal cart_loading : std_logic; + + signal cart_hdr_wr : std_logic; + + signal IOE : std_logic; -- IOE signal + signal IOF : std_logic; -- IOF signal + signal cartridge_reset : std_logic; -- FLAG to reset once cart loaded + signal reset_crt : std_logic; + signal romL : std_logic; -- cart romL from buslogic LCA + signal romH : std_logic; -- cart romH from buslogic LCA + signal UMAXromH : std_logic; -- VIC II Ultimax access - LCA + + signal CPU_hasbus : std_logic; + + signal c1541rom_wr : std_logic; + signal c64rom_wr : std_logic; + + signal joyA : std_logic_vector(7 downto 0); + signal joyB : std_logic_vector(7 downto 0); + signal joyA_int : std_logic_vector(6 downto 0); + signal joyB_int : std_logic_vector(6 downto 0); + signal joyA_c64 : std_logic_vector(6 downto 0); + signal joyB_c64 : std_logic_vector(6 downto 0); + signal reset_key : std_logic; + signal cart_detach_key :std_logic; -- cartridge detach key CTRL-D - LCA + + signal c64_r : std_logic_vector(5 downto 0); + signal c64_g : std_logic_vector(5 downto 0); + signal c64_b : std_logic_vector(5 downto 0); + + signal status : std_logic_vector(31 downto 0); + signal scanlines : std_logic_vector(1 downto 0); + signal hq2x : std_logic; + signal ce_pix_actual : std_logic; + signal sd_lba : std_logic_vector(31 downto 0); + signal sd_rd : std_logic; + signal sd_wr : std_logic; + signal sd_ack : std_logic; + signal sd_ack_conf : std_logic; + signal sd_conf : std_logic; + signal sd_sdhc : std_logic; + signal sd_buff_addr : std_logic_vector(8 downto 0); + signal sd_buff_dout : std_logic_vector(7 downto 0); + signal sd_buff_din : std_logic_vector(7 downto 0); + signal sd_buff_wr : std_logic; + signal sd_change : std_logic; + signal disk_readonly : std_logic; + signal old_download : std_logic; + -- these need to be redirected to the SDRAM + signal sdram_we : std_logic; + signal sdram_ce : std_logic; + + signal ps2_clk : std_logic; + signal ps2_dat : std_logic; + + signal c64_iec_atn_i : std_logic; + signal c64_iec_clk_o : std_logic; + signal c64_iec_data_o : std_logic; + signal c64_iec_atn_o : std_logic; + signal c64_iec_data_i : std_logic; + signal c64_iec_clk_i : std_logic; + + signal c1541_iec_atn_i : std_logic; + signal c1541_iec_clk_o : std_logic; + signal c1541_iec_data_o : std_logic; + signal c1541_iec_atn_o : std_logic; + signal c1541_iec_data_i : std_logic; + signal c1541_iec_clk_i : std_logic; + + signal tv15Khz_mode : std_logic; + signal ypbpr : std_logic; + signal ntsc_init_mode : std_logic; + + alias c64_addr_int : unsigned is unsigned(c64_addr); + alias c64_data_in_int : unsigned is unsigned(c64_data_in); + signal c64_data_in16: std_logic_vector(15 downto 0); + alias c64_data_out_int : unsigned is unsigned(c64_data_out); + + signal clk_ram : std_logic; + signal clk32 : std_logic; + signal clk16 : std_logic; + signal ce_8 : std_logic; + signal ce_4 : std_logic; + signal hq2x160 : std_logic; + signal osdclk : std_logic; + signal clkdiv : std_logic_vector(9 downto 0); + + signal ram_ce : std_logic; + signal ram_we : std_logic; + signal r : unsigned(7 downto 0); + signal g : unsigned(7 downto 0); + signal b : unsigned(7 downto 0); + signal hsync : std_logic; + signal vsync : std_logic; + signal blank : std_logic; + + signal old_vsync : std_logic; + signal hsync_out : std_logic; + signal vsync_out : std_logic; + + signal audio_data : std_logic_vector(17 downto 0); + + signal reset_counter : integer; + signal reset_n : std_logic; + signal led_disk : std_logic; + signal freeze_key : std_logic; + signal nmi : std_logic; + signal nmi_ack : std_logic; + signal erasing : std_logic; +-- temporary signal to extend c64_addr to 24bit LCA + signal c64_addr_temp : std_logic_vector(24 downto 0); + signal cart_blk_len : std_logic_vector(31 downto 0); + signal cart_hdr_cnt : std_logic_vector(3 downto 0); + signal erase_cram : std_logic := '0'; + signal force_erase : std_logic; + signal erase_to : std_logic_vector(4 downto 0) := (others => '0'); + signal mem_ce : std_logic; +begin + + -- 1541 activity led + LED <= not led_disk; + + iec_cycle <= '1' when ces = "1011" else '0'; + + -- User io + mist_io_d : mist_io + generic map (STRLEN => CONF_STR'length) + port map ( + clk_sys => clk32, + + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_SS2 => SPI_SS2, + SPI_DO => SPI_DO, + SPI_DI => SPI_DI, + + joystick_0 => joyA, + joystick_1 => joyB, + + conf_str => to_slv(CONF_STR), + + status => status, + buttons => buttons, + scandoubler_disable => tv15Khz_mode, + ypbpr => ypbpr, + + sd_lba => sd_lba, + sd_rd => sd_rd, + sd_wr => sd_wr, + sd_ack => sd_ack, + sd_ack_conf => sd_ack_conf, + sd_conf => sd_conf, + sd_sdhc => sd_sdhc, + sd_buff_addr => sd_buff_addr, + sd_buff_dout => sd_buff_dout, + sd_buff_din => sd_buff_din, + sd_buff_wr => sd_buff_wr, + img_mounted => sd_change, + ps2_kbd_clk => ps2_clk, + ps2_kbd_data => ps2_dat, + ioctl_download => ioctl_download, + ioctl_force_erase => ioctl_force_erase, + ioctl_erasing => ioctl_erasing, + ioctl_index => ioctl_index, + ioctl_wr => ioctl_wr, + ioctl_addr => ioctl_addr, + ioctl_dout => ioctl_data +); + + + cart_loading <= '1' when ioctl_download = '1' and ioctl_index = 3 else '0'; + + cart : cartridge + port map ( + romL => romL, + romH => romH, + UMAXromH => UMAXromH, + IOE => IOE, + IOF => IOF, + mem_write => not ram_we, + mem_ce => not ram_ce, + mem_ce_out => mem_ce, + + clk32 => clk32, + reset => reset_n, + reset_out => reset_crt, + + cart_id => cart_id, + cart_exrom => cart_exrom, + cart_game => cart_game, + + cart_bank_laddr => cart_bank_laddr, + cart_bank_size => cart_bank_size, + cart_bank_num => cart_bank_num, + cart_bank_type => cart_bank_type, + cart_bank_raddr => ioctl_load_addr, + cart_bank_wr => cart_hdr_wr, + + cart_attached => cart_attached, + cart_loading => cart_loading, + + c64_mem_address_in => c64_addr, + c64_data_out => c64_data_out, + + sdram_address_out => c64_addr_temp, + exrom => exrom, + game => game, + IOE_ena => ioE_rom, + IOF_ena => ioF_rom, + max_ram => max_ram, + freeze_key => freeze_key, + nmi => nmi, + nmi_ack => nmi_ack + ); + + -- rearrange joystick contacta for c64 + joyA_int <= joyA(6 downto 4) & joyA(0) & joyA(1) & joyA(2) & joyA(3); + joyB_int <= joyB(6 downto 4) & joyB(0) & joyB(1) & joyB(2) & joyB(3); + + -- swap joysticks if requested + joyA_c64 <= joyB_int when status(3)='1' else joyA_int; + joyB_c64 <= joyA_int when status(3)='1' else joyB_int; + + sdram_addr <= c64_addr_temp when iec_cycle='0' else ioctl_ram_addr; + sdram_data_out <= c64_data_out when iec_cycle='0' else ioctl_ram_data; + + -- ram_we and ce are active low + sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used; + sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used; + + process(clk32) + begin + if falling_edge(clk32) then + + old_download <= ioctl_download; + iec_cycleD <= iec_cycle; + cart_hdr_wr <= '0'; + + if(iec_cycle='1' and iec_cycleD='0' and ioctl_ram_wr='1') then + ioctl_ram_wr <= '0'; + ioctl_iec_cycle_used <= '1'; + ioctl_ram_addr <= ioctl_load_addr; + ioctl_load_addr <= ioctl_load_addr + "1"; + if erasing = '1' then + ioctl_ram_data <= (others => '0'); + else + ioctl_ram_data <= ioctl_data; + end if; + else + if(iec_cycle='0') then + ioctl_iec_cycle_used <= '0'; + end if; + end if; + + if ioctl_wr='1' then + if ioctl_index = 2 then + if ioctl_addr = 0 then + ioctl_load_addr(7 downto 0) <= ioctl_data; + elsif(ioctl_addr = 1) then + ioctl_load_addr(15 downto 8) <= ioctl_data; + else + ioctl_ram_wr <= '1'; + end if; + end if; + + if ioctl_index = 3 then--CRT, e0(MAX) + if ioctl_addr = 0 then + ioctl_load_addr <= '0' & X"100000"; + cart_blk_len <= (others => '0'); + cart_hdr_cnt <= (others => '0'); + end if; + + if(ioctl_addr = X"16") then cart_id(15 downto 8) <= ioctl_data; end if; + if(ioctl_addr = X"17") then cart_id(7 downto 0) <= ioctl_data; end if; + if(ioctl_addr = X"18") then cart_exrom(7 downto 0)<= ioctl_data; end if; + if(ioctl_addr = X"19") then cart_game(7 downto 0) <= ioctl_data; end if; + + if(ioctl_addr >= X"40") then + if cart_blk_len = 0 and cart_hdr_cnt = 0 then + cart_hdr_cnt <= X"1"; + if ioctl_load_addr(12 downto 0) /= 0 then + -- align to 8KB boundary + ioctl_load_addr(12 downto 0) <= '0' & X"000"; + ioctl_load_addr(24 downto 13) <= ioctl_load_addr(24 downto 13) + "1"; + end if; + elsif cart_hdr_cnt /= 0 then + cart_hdr_cnt <= cart_hdr_cnt + "1"; + if(cart_hdr_cnt = 4) then cart_blk_len(31 downto 24) <= ioctl_data; end if; + if(cart_hdr_cnt = 5) then cart_blk_len(23 downto 16) <= ioctl_data; end if; + if(cart_hdr_cnt = 6) then cart_blk_len(15 downto 8) <= ioctl_data; end if; + if(cart_hdr_cnt = 7) then cart_blk_len(7 downto 0) <= ioctl_data; end if; + if(cart_hdr_cnt = 8) then cart_blk_len <= cart_blk_len - X"10"; end if; + if(cart_hdr_cnt = 9) then cart_bank_type <= ioctl_data; end if; + if(cart_hdr_cnt = 10) then cart_bank_num(15 downto 8) <= ioctl_data; end if; + if(cart_hdr_cnt = 11) then cart_bank_num(7 downto 0) <= ioctl_data; end if; + if(cart_hdr_cnt = 12) then cart_bank_laddr(15 downto 8)<= ioctl_data; end if; + if(cart_hdr_cnt = 13) then cart_bank_laddr(7 downto 0) <= ioctl_data; end if; + if(cart_hdr_cnt = 14) then cart_bank_size(15 downto 8) <= ioctl_data; end if; + if(cart_hdr_cnt = 15) then cart_bank_size(7 downto 0) <= ioctl_data; end if; + if(cart_hdr_cnt = 15) then cart_hdr_wr <= '1'; end if; + else + cart_blk_len <= cart_blk_len - "1"; + ioctl_ram_wr <= '1'; + end if; + end if; + end if; + end if; + + if old_download /= ioctl_download and ioctl_index = 3 then + cart_attached <= old_download; + erase_cram <= '1'; + end if; + + if status(5)='1' or buttons(1)='1' then + cart_attached <= '0'; + end if; + + if erasing='0' and force_erase = '1' then + erasing <='1'; + ioctl_load_addr <= (others => '0'); + end if; + + if erasing = '1' and ioctl_ram_wr = '0' then + erase_to <= erase_to + "1"; + if erase_to = "11111" then + if ioctl_load_addr < (erase_cram & X"FFFF") then + ioctl_ram_wr <= '1'; + else + erasing <= '0'; + erase_cram <= '0'; + end if; + end if; + end if; + end if; + end process; + + c64rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '0') and (ioctl_download = '1') else '0'; + c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0'; + + process(clk32) + begin + if rising_edge(clk32) then + clk16 <= not clk16; + clkdiv <= std_logic_vector(unsigned(clkdiv)+1); + if(clkdiv(1 downto 0) = "00") then + ce_8 <= '1'; + else + ce_8 <= '0'; + end if; + if(clkdiv(2 downto 0) = "000") then + ce_4 <= '1'; + else + ce_4 <= '0'; + end if; + end if; + end process; + + ntsc_init_mode <= status(2); + + -- second to generate 64mhz clock and phase shifted ram clock + pll : entity work.pll + port map( + inclk0 => CLOCK_27, + c0 => clk_ram, + c1 => SDRAM_CLK, + c2 => clk32, + locked => pll_locked + ); + + process(clk32) + begin + if rising_edge(clk32) then + -- Reset by: + -- Button at device, IO controller reboot, OSD or FPGA startup + if status(0)='1' or pll_locked = '0' then + reset_counter <= 1000000; + reset_n <= '0'; + elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or (ioctl_download='1' and ioctl_index = 3) then + reset_counter <= 255; + reset_n <= '0'; + elsif ioctl_download ='1' then + elsif erasing ='1' then + force_erase <= '0'; + else + if reset_counter = 0 then + reset_n <= '1'; + else + reset_counter <= reset_counter - 1; + if reset_counter = 100 then + force_erase <='1'; + end if; + end if; + end if; + end if; + end process; + + SDRAM_DQ(15 downto 8) <= (others => 'Z') when sdram_we='0' else (others => '0'); + SDRAM_DQ(7 downto 0) <= (others => 'Z') when sdram_we='0' else sdram_data_out; + + -- read from sdram + c64_data_in <= SDRAM_DQ(7 downto 0); + -- clock is always enabled and memory is never masked as we only + -- use one byte + SDRAM_CKE <= '1'; + SDRAM_DQML <= '0'; + SDRAM_DQMH <= '0'; + + sdr: sdram port map( + sd_addr => SDRAM_A, + sd_ba => SDRAM_BA, + sd_cs => SDRAM_nCS, + sd_we => SDRAM_nWE, + sd_ras => SDRAM_nRAS, + sd_cas => SDRAM_nCAS, + + clk => clk_ram, + addr => sdram_addr, + init => not pll_locked, + we => sdram_we, + refresh => idle, + ce => sdram_ce + ); + + + -- decode audio + dac_l : sigma_delta_dac + port map ( + CLK => clk32, + DACin => not audio_data(17) & audio_data(16 downto 3), + DACout => AUDIO_L, + RESET => '0' + ); + + dac_r : sigma_delta_dac + port map ( + CLK => clk32, + DACin => not audio_data(17) & audio_data(16 downto 3), + DACout => AUDIO_R, + RESET => '0' + ); + + fpga64 : entity work.fpga64_sid_iec + port map( + clk32 => clk32, + reset_n => reset_n, + c64gs => status(11), + kbd_clk => not ps2_clk, + kbd_dat => ps2_dat, + ramAddr => c64_addr_int, + ramDataOut => c64_data_out_int, + ramDataIn => c64_data_in_int, + ramCE => ram_ce, + ramWe => ram_we, + ntscInitMode => ntsc_init_mode, + hsync => hsync, + vsync => vsync, + r => r, + g => g, + b => b, + game => game, + exrom => exrom, + UMAXromH => UMAXromH, + CPU_hasbus => CPU_hasbus, + ioE_rom => ioE_rom, + ioF_rom => ioF_rom, + max_ram => max_ram, + irq_n => '1', + nmi_n => not nmi, + nmi_ack => nmi_ack, + freeze_key => freeze_key, + dma_n => '1', + romL => romL, + romH => romH, + IOE => IOE, + IOF => IOF, + ba => open, + joyA => unsigned(joyA_c64), + joyB => unsigned(joyB_c64), + serioclk => open, + ces => ces, + SIDclk => open, + still => open, + idle => idle, + audio_data => audio_data, + extfilter_en => not status(6), + iec_data_o => c64_iec_data_o, + iec_atn_o => c64_iec_atn_o, + iec_clk_o => c64_iec_clk_o, + iec_data_i => not c64_iec_data_i, + iec_clk_i => not c64_iec_clk_i, + iec_atn_i => not c64_iec_atn_i, + disk_num => open, + c64rom_addr => ioctl_addr(13 downto 0), + c64rom_data => ioctl_data, + c64rom_wr => c64rom_wr, + cart_detach_key => cart_detach_key, + reset_key => reset_key + ); + + + c64_iec_atn_i <= not ((not c64_iec_atn_o) and (not c1541_iec_atn_o) ); + c64_iec_data_i <= not ((not c64_iec_data_o) and (not c1541_iec_data_o)); + c64_iec_clk_i <= not ((not c64_iec_clk_o) and (not c1541_iec_clk_o) ); + + c1541_iec_atn_i <= c64_iec_atn_i; + c1541_iec_data_i <= c64_iec_data_i; + c1541_iec_clk_i <= c64_iec_clk_i; + + process(clk32, reset_n) + variable reset_cnt : integer range 0 to 32000000; + begin + if reset_n = '0' then + reset_cnt := 100000; + elsif rising_edge(clk32) then + if reset_cnt /= 0 then + reset_cnt := reset_cnt - 1; + end if; + end if; + + if reset_cnt = 0 then + c1541_reset <= '0'; + else + c1541_reset <= '1'; + end if; + end process; + + c1541_sd : entity work.c1541_sd + port map + ( + clk32 => clk32, + reset => c1541_reset, + + c1541rom_addr => ioctl_addr(13 downto 0), + c1541rom_data => ioctl_data, + c1541rom_wr => c1541rom_wr, + + disk_change => sd_change, + disk_readonly => disk_readonly, + + iec_atn_i => c1541_iec_atn_i, + iec_data_i => c1541_iec_data_i, + iec_clk_i => c1541_iec_clk_i, + + iec_atn_o => c1541_iec_atn_o, + iec_data_o => c1541_iec_data_o, + iec_clk_o => c1541_iec_clk_o, + + sd_lba => sd_lba, + sd_rd => sd_rd, + sd_wr => sd_wr, + sd_ack => sd_ack, + sd_ack_conf => sd_ack_conf, + sd_conf => sd_conf, + sd_sdhc => sd_sdhc, + sd_buff_addr => sd_buff_addr, + sd_buff_dout => sd_buff_dout, + sd_buff_din => sd_buff_din, + sd_buff_wr => sd_buff_wr, + + led => led_disk + ); + + comp_sync : entity work.composite_sync + port map( + clk32 => clk32, + hsync => hsync, + vsync => vsync, + ntsc => ntsc_init_mode, + hsync_out => hsync_out, + vsync_out => vsync_out, + blank => blank + ); + + c64_r <= (others => '0') when blank = '1' else std_logic_vector(r(7 downto 2)); + c64_g <= (others => '0') when blank = '1' else std_logic_vector(g(7 downto 2)); + c64_b <= (others => '0') when blank = '1' else std_logic_vector(b(7 downto 2)); + + scanlines <= status(10 downto 9); + hq2x <= status(9) xor status(8); + ce_pix_actual <= ce_4 when hq2x160='1' else ce_8; + + process(clk32) + begin + if rising_edge(clk32) then + if((old_vsync = '0') and (vsync_out = '1')) then + if(status(10 downto 8)="010") then + hq2x160 <= '1'; + else + hq2x160 <= '0'; + end if; + end if; + old_vsync <= vsync_out; + end if; + end process; + + vmixer : video_mixer + port map ( + clk_sys => clk_ram, + ce_pix => ce_8, + ce_pix_actual => ce_pix_actual, + + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, + + scanlines => scanlines, + scandoubler_disable => tv15Khz_mode, + hq2x => hq2x, + ypbpr => ypbpr, + ypbpr_full => '1', + + R => c64_r, + G => c64_g, + B => c64_b, + HSync => hsync_out, + VSync => vsync_out, + line_start => '0', + mono => '0', + + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B, + VGA_VS => VGA_VS, + VGA_HS => VGA_HS + ); + +end struct; diff --git a/Commodore - 64_Mist/rtl/cartridge.v b/Commodore - 64_Mist/rtl/cartridge.v new file mode 100644 index 00000000..f8b4f3b2 --- /dev/null +++ b/Commodore - 64_Mist/rtl/cartridge.v @@ -0,0 +1,566 @@ +module cartridge +( + input romL, // romL signal in + input romH, // romH signal in + input UMAXromH, // romH VIC II address signal + input IOE, // IOE control signal + input IOF, // IOF control signal + input mem_write, // memory write active + input mem_ce, + output mem_ce_out, + + input clk32, // 32mhz clock source + input reset, // reset signal + output reg reset_out, // reset signal + + input [15:0] cart_id, // cart ID or cart type + input [7:0] cart_exrom, // CRT file EXROM status + input [7:0] cart_game, // CRT file GAME status + + input [15:0] cart_bank_laddr, // bank loading address + input [15:0] cart_bank_size, // length of each bank + input [15:0] cart_bank_num, + input [7:0] cart_bank_type, + input [24:0] cart_bank_raddr, // chip packet address + input cart_bank_wr, + + input cart_attached, // FLAG to say cart has been loaded + input cart_loading, + + input [15:0] c64_mem_address_in, // address from cpu + input [7:0] c64_data_out, // data from cpu going to sdram + + output [24:0] sdram_address_out, // translated address output + output exrom, // exrom line + output game, // game line + output reg IOE_ena, // FLAG to enable IOE address relocation + output reg IOF_ena, // FLAG to enable IOF address relocation + output reg max_ram, // Enable whole C64 RAM in Ultimax mode + + input freeze_key, + output reg nmi, + input nmi_ack +); + +reg [24:0] addr_out; +assign sdram_address_out = addr_out; + +reg [6:0] bank_lo; +reg [6:0] bank_hi; +reg [12:0] mask_lo; + +reg [6:0] IOE_bank; +reg [6:0] IOF_bank; +reg IOE_wr_ena; +reg IOF_wr_ena; + +reg exrom_overide; +reg game_overide; +assign exrom = ~cart_attached | exrom_overide; +assign game = ~cart_attached | game_overide; + +(* ramstyle = "logic" *) reg [6:0] lobanks[0:63]; +(* ramstyle = "logic" *) reg [6:0] hibanks[0:63]; + +reg [7:0] bank_cnt; +always @(posedge clk32) begin + reg old_loading; + old_loading <= cart_loading; + + if(~old_loading & cart_loading) bank_cnt <= 0; + if(cart_bank_wr) begin + bank_cnt <= bank_cnt + 1'd1; + if(cart_bank_num<64) begin + if(cart_bank_laddr <= 'h8000) begin + lobanks[cart_bank_num[5:0]] <= cart_bank_raddr[19:13]; + if(cart_bank_size > 'h2000) hibanks[cart_bank_num[5:0]] <= cart_bank_raddr[19:13]+1'd1; + end + else hibanks[cart_bank_num[5:0]] <= cart_bank_raddr[19:13]; + end + end +end + +reg romL_we = 0; +reg romH_we = 0; + +reg old_ioe, old_iof; +always @(posedge clk32) begin + old_ioe <= IOE; + old_iof <= IOF; +end + +wire stb_ioe = (~old_ioe & IOE); +wire stb_iof = (~old_iof & IOF); + +wire ioe_wr = stb_ioe & mem_write; +wire ioe_rd = stb_ioe & ~mem_write; + +wire iof_wr = stb_iof & mem_write; +//wire iof_rd = stb_iof & ~mem_write; + +reg old_freeze = 0; +wire freeze_req = (~old_freeze & freeze_key); + +reg old_nmiack = 0; +wire freeze_ack = (nmi & ~old_nmiack & nmi_ack); + +// 0018 - EXROM line status +// 0019 - GAME line status + +always @(posedge clk32) begin + reg init_n = 0; + reg allow_freeze = 0; + reg saved_d6 = 0; + reg [15:0] count; + reg count_ena; + reg cart_disable = 0; + + old_freeze <= freeze_key; + if(freeze_req & allow_freeze) nmi <= 1; + + old_nmiack <= nmi_ack; + if(freeze_ack) nmi <= 0; + + if(!reset) begin + cart_disable <= 0; + bank_lo <= 0; + bank_hi <= 0; + IOE_ena <= 0; + IOF_ena <= 0; + IOE_wr_ena <= 0; + IOF_wr_ena <= 0; + romL_we <= 0; + romH_we <= 0; + reset_out <= 0; + init_n <= 0; + allow_freeze <= 1; + nmi <= 0; + saved_d6 <= 0; + mask_lo <= 13'h1FFF; + exrom_overide <= 1; + game_overide <= 1; + max_ram <= 0; + end + else + case(cart_id) + + // Generic 8k(exrom=0,game=1), 16k(exrom=0,game=0), ULTIMAX(exrom=1,game=0) + 0: begin + exrom_overide <= cart_exrom[0]; + game_overide <= cart_game[0]; + bank_lo <= lobanks[0]; + bank_hi <= hibanks[0]; + end + + // Action Replay v4+ - (32k 4x8k banks + 8K RAM) + // controlled by DE00 + 1: begin + if(nmi) allow_freeze <= 0; + if(!init_n || freeze_ack) begin + cart_disable <= 0; + exrom_overide <= 1; + game_overide <= 0; + romL_we <= 0; + bank_lo <= 0; + bank_hi <= 0; + IOF_bank <= 0; + IOF_wr_ena <= 0; + IOF_ena <= 1; + if(~init_n) begin + init_n <= 1; + exrom_overide <= 0; + game_overide <= 1; + end + end + else if(cart_disable) begin + exrom_overide <= 1; + game_overide <= 1; + IOF_ena <= 0; + IOF_wr_ena <= 0; + romL_we <= 0; + allow_freeze <= 1; + end else begin + if(ioe_wr) begin + cart_disable <= c64_data_out[2]; + bank_lo <= c64_data_out[4:3]; + bank_hi <= c64_data_out[4:3]; + IOF_bank <= c64_data_out[4:3]; + + if(c64_data_out[6] | allow_freeze) begin + allow_freeze <= 1; + game_overide <= ~c64_data_out[0]; + exrom_overide <= c64_data_out[1]; + IOF_wr_ena <= c64_data_out[5]; + romL_we <= c64_data_out[5]; + if(c64_data_out[5]) begin + bank_lo <= 0; + IOF_bank<= 0; + end + end + end + end + end + + // Final Cart III - (64k 4x16k banks) + // all banks @ $8000-$BFFF - switching by $DFFF + 3: begin + if(!init_n) begin + init_n <= 1; + game_overide <= 0; + exrom_overide<= 0; + cart_disable <= 0; + bank_lo <= 0; + bank_hi <= 1; + IOE_ena <= 1; + IOE_bank<= 0; + IOF_ena <= 1; + IOF_bank<= 0; + end + else if(!cart_disable) begin + if(iof_wr && &c64_mem_address_in[7:0]) begin + bank_lo <= {c64_data_out[1:0],1'd0}; + bank_hi <= {c64_data_out[1:0],1'd1}; + IOE_bank<= {c64_data_out[1:0],1'd0}; + IOF_bank<= {c64_data_out[1:0],1'd0}; + exrom_overide <= c64_data_out[4]; + game_overide <= c64_data_out[5]; + saved_d6 <= c64_data_out[6]; + if(~freeze_key & saved_d6 & ~c64_data_out[6]) nmi <= 1; + if(c64_data_out[6]) allow_freeze <= 1; + cart_disable <= c64_data_out[7]; + end + end + if(freeze_ack) begin + cart_disable <= 0; + game_overide <= 0; + allow_freeze <= 0; + end + end + + // Simons Basic - (game=0, exrom=0, 2 banks by 8k) + // Read to IOE switches 8k config + // Write to IOE switches 16k config + 4: begin + if(!init_n) begin + init_n <= 1; + exrom_overide <= 0; + game_overide <= 0; + bank_lo <= 0; + bank_hi <= 1; + end + if(ioe_wr) game_overide <= 0; + if(ioe_rd) game_overide <= 1; + end + + // Ocean Type 1 - (game=0, exrom=0, 128k,256k or 512k in 8k banks) + // BANK is written to lower 6 bits of $DE00 - bit 8 is always set + // best to mirror banks at $8000 and $A000 + 5: begin + exrom_overide <= 0; + game_overide <= 0; + if(ioe_wr) begin + bank_lo <= c64_data_out[5:0]; + bank_hi <= c64_data_out[5:0]; + end + end + + // PowerPlay, FunPlay + 7: begin + if(~init_n) begin + init_n <= 1; + exrom_overide <= 0; + game_overide <= 1; + end + + if(ioe_wr) begin + bank_lo <= {c64_data_out[0],c64_data_out[5:3]}; + if({c64_data_out[7:6],c64_data_out[2:1]} == 'b1011) exrom_overide <= 1; + if({c64_data_out[7:6],c64_data_out[2:1]} == 'b0000) exrom_overide <= 0; + end + end + + // "Super Games" + 8: begin + if(~init_n) begin + init_n <= 1; + exrom_overide <= 0; + game_overide <= 0; + bank_lo <= 0; + bank_hi <= 1; + end + + if(~cart_disable & iof_wr) begin + bank_lo <= {c64_data_out[1:0],1'd0}; + bank_hi <= {c64_data_out[1:0],1'd1}; + game_overide <= c64_data_out[2]; + exrom_overide <= c64_data_out[2]; + cart_disable <= c64_data_out[3]; + end + end + + // Epyx Fastload - (game=1, exrom=0, 8k bank) + // any access to romL or $DE00 charges a capacitor + // Once discharged the exrom drops to ON disabling cart + 10: begin + if(!init_n) count_ena <= 0; + if(IOE || romL) count_ena <= 1; + + if(!init_n || IOE || romL) begin + init_n <= 1; + game_overide <= 1; + exrom_overide <= 0; + count <= 16384; + IOF_ena <= 1; + IOF_bank<= 0; + end + else + if(count_ena) begin + if(count) count <= count - 1'd1; + else exrom_overide <= 1; + end + end + + // FINAL CARTRIDGE 1,2 + // 16k rom - IOE turns off rom / IOF turns rom on + 13: begin + if(!init_n) begin + init_n <= 1; + + bank_lo <= 0; + bank_hi <= 1; + game_overide <= 0; + exrom_overide <= 0; + + // Last 2 pages visible at IOE / IOF + IOE_bank <= 0; + IOF_bank <= 0; + IOE_ena <= 1; + IOF_ena <= 1; + end + + if(freeze_ack) begin + game_overide <= 0; + allow_freeze <= 0; + end + + if(IOE) begin + game_overide <= 1; + exrom_overide <= 1; + allow_freeze <= 1; + end + + if(IOF) begin + game_overide <= 0; + exrom_overide <= 0; + end + end + + // C64GS - (game=1, exrom=0, 64 banks by 8k) + // 8k config + // Reading from IOE ($DE00 $DEFF) switches to bank 0 + 15: begin + game_overide <= 1; + exrom_overide <= 0; + if(ioe_rd) bank_lo <= 0; + if(ioe_wr) bank_lo <= c64_mem_address_in[5:0]; + end + + // Dinamic - (game=1, exrom=0, 16 banks by 8k) + 17: begin + game_overide <= 1; + exrom_overide <= 0; + if(ioe_rd) bank_lo <= c64_mem_address_in[3:0]; + end + + // Zaxxon, Super Zaxxon (game=0, exrom=0 - 4Kb + 2x8KB) + 18: begin + mask_lo <= 'hFFF; + game_overide <= 0; + exrom_overide <= 0; + if(romL & mem_ce & ~c64_mem_address_in[12]) bank_hi <= 1; + if(romL & mem_ce & c64_mem_address_in[12]) bank_hi <= 2; + end + + // Magic Desk - (game=1, exrom=0 = 4/8/16 8k banks) + 19: begin + if(!init_n) begin + init_n <= 1; + game_overide <= 1; + exrom_overide <= 0; + bank_lo <= 0; + end + + if(ioe_wr) begin + bank_lo <= c64_data_out[3:0]; + exrom_overide <= c64_data_out[7]; + end + end + + // Super Snapshot v5 -(64k rom 8*8k banks/4*16k banks, 32k ram 4*8k banks) + 20: begin + if(!init_n || freeze_ack) begin + init_n <= 1; + romL_we <= 1; + bank_lo <= 0; + bank_hi <= 1; + game_overide <= 0; + exrom_overide <= 1; + IOE_bank <= 0; + IOE_ena <= 1; + cart_disable <= 0; + end + else + if(~cart_disable & ioe_wr) begin + game_overide <= c64_data_out[0] | c64_data_out[3]; + exrom_overide<= ~c64_data_out[1] | c64_data_out[3]; + bank_lo <= {c64_data_out[4], c64_data_out[2], 1'b0}; + bank_hi <= {c64_data_out[4], c64_data_out[2], 1'b1}; + IOE_bank<= {c64_data_out[4], c64_data_out[2], 1'b0}; + cart_disable <= c64_data_out[3]; + IOE_ena <= ~c64_data_out[3]; + + //RAM overlay + if(~c64_data_out[1]) bank_lo <= {c64_data_out[4], c64_data_out[2]}; + romL_we <= ~c64_data_out[1]; + end + end + + // Comal80 - (game=0, exrom=0, 4 banks by 16k) + 21: begin + if(!init_n) begin + init_n <= 1; + bank_lo <= 0; + bank_hi <= 1; + game_overide <= 0; + exrom_overide <= 0; + end + if(ioe_wr) begin + case(c64_data_out[7:5]) + 'b010: + begin + exrom_overide <= 0; + game_overide <= 1; + end + 'b111: + begin + exrom_overide <= 1; + game_overide <= 1; + end + default: + begin + exrom_overide <= 0; + game_overide <= 0; + end + endcase + + bank_lo <= {c64_data_out[1:0], 1'b0}; + bank_hi <= {c64_data_out[1:0], 1'b1}; + end + end + + // Mikro Assembler - (game=1, exrom=0, 8k) + 28: begin + game_overide <= 1; + exrom_overide <= 0; + IOE_bank <= 0; + IOE_ena <= 1; + IOF_bank <= 0; + IOF_ena <= 1; + end + + // EASYFLASH - 1mb 128x8k/64x16k, XBank format(33) looks the same + // upd: original Easyflash(32) boots in ultimax mode. + // Only one XBank(33) cart has been found: soulless-xbank. It doesn't boot in ultimax mode. + 32, + 33: begin + if(!init_n) begin + init_n <= 1; + IOF_bank<= 0; + IOF_ena <= 1; + IOF_wr_ena <= 1; + exrom_overide <= (cart_id==32); + game_overide <= 0; + bank_lo <= lobanks[0]; + bank_hi <= hibanks[0]; + end + + if(ioe_wr) begin + if(c64_mem_address_in[1]) begin + game_overide <= ~c64_data_out[0] & c64_data_out[2]; //assume jumper in boot position bit2=0 -> game=0 + exrom_overide <= ~c64_data_out[1]; + end + else begin + bank_lo <= lobanks[c64_data_out[5:0]]; + bank_hi <= hibanks[c64_data_out[5:0]]; + end + end + end + + // Kingsoft Business Basic + 54: begin + max_ram <= 1; + + if(!init_n || ioe_rd) begin + init_n <= 1; + game_overide <= 0; + exrom_overide <= 0; + bank_lo <= 0; + bank_hi <= 1; + end + + if(ioe_wr) begin + game_overide <= 0; + exrom_overide <= 1; + bank_lo <= 0; + bank_hi <= 2; + end + end + + // RGCD (game=1, exrom=0, 8 banks by 8k) + 57: begin + if(!init_n) begin + init_n <= 1; + game_overide <= 1; + exrom_overide <= 0; + bank_lo <= 0; + end + + if(~cart_disable & ioe_wr) begin + bank_lo <= c64_data_out[2:0]; + if(c64_data_out[3]) begin + cart_disable <= 1; + game_overide <= 1; + exrom_overide <= 1; + end + end + end + endcase +end + +// ************************************************************************************************************ +// ****** Address handling - Redirection to SDRAM CRT file +// ************************************************************************************************************ + +wire ioe_ce = (IOE && (mem_write ? IOE_wr_ena : IOE_ena)); +wire iof_ce = (IOF && (mem_write ? IOF_wr_ena : IOF_ena)); + +assign mem_ce_out = mem_ce | ioe_ce | iof_ce; + +//RAM banks are remapped to 64K-128K space +always @(*) begin + addr_out = c64_mem_address_in; + if(cart_attached) begin + if(romH & (romH_we | ~mem_write)) addr_out[24:13] = romH_we ? {1'b1, bank_hi[2:0]} : {1'b1, bank_hi}; + if(romL & (romL_we | ~mem_write)) begin + addr_out[24:13] = romL_we ? {1'b1, bank_lo[2:0]} : {1'b1, bank_lo}; + addr_out[12:0] = c64_mem_address_in[12:0] & mask_lo; + end + + if(ioe_ce) addr_out[24:13] = IOE_wr_ena ? {1'b1, IOE_bank[2:0]} : {1'b1, IOE_bank}; // read/write to DExx + if(iof_ce) addr_out[24:13] = IOF_wr_ena ? {1'b1, IOF_bank[2:0]} : {1'b1, IOF_bank}; // read/write to DFxx + + if(UMAXromH && !mem_write) addr_out[24:12] = {1'b1, bank_hi, 1'b1}; // ULTIMAX CharROM + end +end + +endmodule diff --git a/Commodore - 64_Mist/rtl/cia6526.vhd b/Commodore - 64_Mist/rtl/cia6526.vhd new file mode 100644 index 00000000..25eb4255 --- /dev/null +++ b/Commodore - 64_Mist/rtl/cia6526.vhd @@ -0,0 +1,782 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- 6526 Complex Interface Adapter +-- +-- rev 1 - june17 / TOD alarms +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cia6526 is + generic ( + todEnabled : std_logic := '1' + ); + port ( + clk: in std_logic; + todClk: in std_logic; + reset: in std_logic; + enable: in std_logic; + cs: in std_logic; + we: in std_logic; -- Write strobe + rd: in std_logic; -- Read strobe + + addr: in unsigned(3 downto 0); + di: in unsigned(7 downto 0); + do: out unsigned(7 downto 0); + + ppai: in unsigned(7 downto 0); + ppao: out unsigned(7 downto 0); + ppad: out unsigned(7 downto 0); + + ppbi: in unsigned(7 downto 0); + ppbo: out unsigned(7 downto 0); + ppbd: out unsigned(7 downto 0); + + flag_n: in std_logic; + + irq_n: out std_logic + ); +end cia6526; + +-- ----------------------------------------------------------------------- + +architecture Behavioral of cia6526 is + -- IO ports + signal pra: unsigned(7 downto 0); + signal prb: unsigned(7 downto 0); + signal ddra: unsigned(7 downto 0); + signal ddrb: unsigned(7 downto 0); + + -- Timer to IO ports + signal timerAPulse : std_logic; + signal timerAToggle : std_logic; + signal timerBPulse : std_logic; + signal timerBToggle : std_logic; + + -- Timer A reload registers + signal talo: unsigned(7 downto 0) := (others => '1'); + signal tahi: unsigned(7 downto 0) := (others => '1'); + + -- Timer B reload registers + signal tblo: unsigned(7 downto 0) := (others => '1'); + signal tbhi: unsigned(7 downto 0) := (others => '1'); + + -- Timer A and B internal registers + signal timerA : unsigned(15 downto 0); + signal forceTimerA : std_logic; + signal loadTimerA : std_logic; + signal clkTimerA : std_logic; -- internal timer clock + + signal timerB: unsigned(15 downto 0); + signal forceTimerB : std_logic; + signal loadTimerB : std_logic; + signal clkTimerB : std_logic; -- internal timer clock + + signal WR_Delay_offset : std_logic; -- adjustable WR signal delay - LCA jun17 + + -- Config register A + signal cra_start : std_logic; + signal cra_pbon : std_logic; + signal cra_outmode : std_logic; + signal cra_runmode : std_logic; + signal cra_runmode_reg : std_logic; + signal cra_inmode : std_logic; + signal cra_spmode : std_logic; + signal cra_todin : std_logic; + + -- Config register B + signal crb_start : std_logic; + signal crb_pbon : std_logic; + signal crb_outmode : std_logic; + signal crb_runmode : std_logic; + signal crb_runmode_reg : std_logic; + signal crb_inmode5 : std_logic; + signal crb_inmode6 : std_logic; + signal crb_alarm : std_logic; + + -- TOD 50/60 hz clock + signal todTick : std_logic; + signal oldTodClk : std_logic; + signal tod_clkcnt: unsigned(2 downto 0); + + -- TOD counters + signal tod_running: std_logic; + signal tod_10ths: unsigned(3 downto 0); + signal tod_secs: unsigned(6 downto 0); + signal tod_mins: unsigned(6 downto 0); + signal tod_hrs: unsigned(7 downto 0); + signal tod_pm: std_logic; + + -- TOD latches + signal tod_latched: std_logic; + signal tod_latch_10ths: unsigned(3 downto 0); + signal tod_latch_secs: unsigned(6 downto 0); + signal tod_latch_mins: unsigned(6 downto 0); + signal tod_latch_hrs: unsigned(7 downto 0); + constant tod_latch_pm: std_logic := '0'; + + -- TOD alarms - LCA + signal tod_10ths_alarm: unsigned(3 downto 0); + signal tod_secs_alarm: unsigned(6 downto 0); + signal tod_mins_alarm: unsigned(6 downto 0); + signal tod_hrs_alarm: unsigned(7 downto 0); + signal tod_pm_alarm: std_logic; + + -- Interrupt processing + signal resetIrq : boolean; + signal intr_flagn : std_logic; + signal intr_serial : std_logic; + signal intr_alarm : std_logic; -- LCA + signal intr_timerA : std_logic; + signal intr_timerB : std_logic; + signal mask_timerA : std_logic; + signal mask_timerB : std_logic; + signal mask_alarm : std_logic; -- LCA + signal mask_serial : std_logic; + signal mask_flagn : std_logic; + signal ir: std_logic; + + signal prevFlag_n: std_logic; + + signal myWr : std_logic; + signal myRd : std_logic; +begin +-- ----------------------------------------------------------------------- +-- chip-select signals +-- ----------------------------------------------------------------------- + myWr <= cs and we; + myRd <= cs and rd; + +-- ----------------------------------------------------------------------- +-- I/O ports +-- ----------------------------------------------------------------------- + -- Port A + process(pra, ddra) + begin + ppad <= ddra; + ppao <= pra or (not ddra); + end process; + + -- Port B + process(prb, ddrb, cra_pbon, cra_outmode, crb_pbon, crb_outmode, timerAPulse, timerAToggle, timerBPulse, timerBToggle) + begin + ppbd <= ddrb; + ppbo <= prb or (not ddrb); + if cra_pbon = '1' then + ppbo(6) <= timerAPulse or (not ddrb(6)); + if cra_outmode = '1' then + ppbo(6) <= timerAToggle or (not ddrb(6)); + end if; + end if; + if crb_pbon = '1' then + ppbo(7) <= timerBPulse or (not ddrb(7)); + if crb_outmode = '1' then + ppbo(7) <= timerBToggle or (not ddrb(7)); + end if; + end if; + end process; + + -- I/O port registers + process(clk) + begin + if rising_edge(clk) then + if myWr = '1' then + case addr is + when X"0" => pra <= di; + when X"1" => prb <= di; + when X"2" => ddra <= di; + when X"3" => ddrb <= di; + when others => null; + end case; + end if; + if reset = '1' then + pra <= (others => '0'); + prb <= (others => '0'); + ddra <= (others => '0'); + ddrb <= (others => '0'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- TOD - time of day +-- ----------------------------------------------------------------------- + process(clk) + begin + -- Process rising edge on the todClk. + -- There is a prescaler of 5 or 6 to get 10ths of seconds from + -- 50 Hz or 60 Hz line frequency. + -- + -- Output is a 'todTick' signal synchronished with enable signal (@ 1Mhz). + if rising_edge(clk) then + if todEnabled = '1' then + if enable = '1' then + todTick <= '0'; + end if; + + if todClk = '1' and oldTodClk = '0' then + -- Divide by 5 or 6 dependng on 50/60 Hz flag. + if tod_clkcnt /= "000" then + tod_clkcnt <= tod_clkcnt - 1; + else + todTick <= tod_running; + tod_clkcnt <= "101"; -- 60 Hz + if cra_todin = '1' then + tod_clkcnt <= "100"; -- 50 Hz + end if; + end if; + end if; + oldTodClk <= todClk; + else + todTick <= '0'; + end if; + end if; + end process; + + process(clk) + variable new_10ths : unsigned(3 downto 0); + variable new_secsL : unsigned(3 downto 0); + variable new_secsH : unsigned(2 downto 0); + variable new_minsL : unsigned(3 downto 0); + variable new_minsH : unsigned(2 downto 0); + variable new_hrsL : unsigned(3 downto 0); + variable new_hrsH : std_logic; + variable new_hrs_byte : unsigned(7 downto 0); -- LCA am/pm and hours + begin + if rising_edge(clk) then + new_10ths := tod_10ths; + new_secsL := tod_secs(3 downto 0); + new_secsH := tod_secs(6 downto 4); + new_minsL := tod_mins(3 downto 0); + new_minsH := tod_mins(6 downto 4); +-- new_hrsL := tod_hrs(3 downto 0); +-- new_hrsH := tod_hrs(4); + new_hrs_byte := tod_hrs (7 downto 0); -- LCA am/pm and hours +-- new_hrs_byte := new_hrsH & new_hrsL; + + if enable = '1' + and todTick = '1' then + if new_10ths /= "1001" then + new_10ths := new_10ths + 1; + else + new_10ths := "0000"; + if new_secsL /= "1001" then + new_secsL := new_secsL + 1; + else + new_secsL := "0000"; + if new_secsH /= "101" then + new_secsH := new_secsH + 1; + else + new_secsH := "000"; + if new_minsL /= "1001" then + new_minsL := new_minsL + 1; + else + new_minsL := "0000"; + if new_minsH /= "101" then + new_minsH := new_minsH + 1; + else + new_minsH := "000"; + -- hrs were missing jun17 LCA + -- I mean completely absent from code :) !!!!!! + -- case to lookup then handles oddities in others + -- retarded am/pm flag flip madness handled at register load below (REG B) + + case tod_hrs is -- case state to set hours and am/pm + when "00010010" => + new_hrs_byte := "00000001"; -- 1 am set + when "00000001" => + new_hrs_byte := "00000010"; + when "00000010" => + new_hrs_byte := "00000011"; + when "00000011" => + new_hrs_byte := "00000100"; + when "00000100" => + new_hrs_byte := "00000101"; + when "00000101" => + new_hrs_byte := "00000110"; + when "00000110" => + new_hrs_byte := "00000111"; + when "00000111" => + new_hrs_byte := "00001000"; + when "00001000" => + new_hrs_byte := "00001001"; + when "00001001" => + new_hrs_byte := "00010000"; + when "00010000" => + new_hrs_byte := "00010001"; -- 11am set + when "00010001" => + new_hrs_byte := "10010010"; -- 12pm set + when "10010010" => + new_hrs_byte := "10000001"; -- 1 pm set + + when "10000001" => + new_hrs_byte := "10000010"; + when "10000010" => + new_hrs_byte := "10000011"; + when "10000011" => + new_hrs_byte := "10000100"; + when "10000100" => + new_hrs_byte := "10000101"; + when "10000101" => + new_hrs_byte := "10000110"; + when "10000110" => + new_hrs_byte := "10000111"; + when "10000111" => + new_hrs_byte := "10001000"; + when "10001000" => + new_hrs_byte := "10001001"; + when "10001001" => + new_hrs_byte := "10010000"; -- 10pm set + when "10010000" => + new_hrs_byte := "10010001"; -- 11pm set + when "10010001" => + new_hrs_byte := "00010010"; -- 12am set (midnight) + when others => + new_hrs_byte (3 downto 0) := new_hrs_byte (3 downto 0) + 1; + --null; + end case; + + end if; + end if; + end if; + end if; + end if; + end if; + + if myWr = '1' then + if crb_alarm = '0' then + case addr is + when X"8" => + new_10ths := di(3 downto 0); + tod_running <= '1'; + when X"9" => + new_secsL := di(3 downto 0); + new_secsH := di(6 downto 4); + when X"A" => + new_minsL := di(3 downto 0); + new_minsH := di(6 downto 4); + when X"B" => + new_hrs_byte := di(7) & "00" & di(4 downto 0); -- LCA + tod_running <= '0'; + if di(7 downto 0) = "10010010" or di(7 downto 0) = "00010010" then -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!) + new_hrs_byte(7) := not new_hrs_byte(7); -- This P.O.S. now mimics real commodore 64 !!!!! LCA + end if; + when others => + null; + end case; + else -- TOD ALARM UPDATE + case addr is + when X"8" => + tod_10ths_alarm <= di(3 downto 0); + when X"9" => + tod_secs_alarm <= di(6 downto 0); + when X"A" => + tod_mins_alarm <= di(6 downto 0); + when X"B" => +-- tod_hrs_alarm <= di(4 downto 0); +-- tod_pm_alarm <= di(7); + tod_hrs_alarm <= di(7) & "00" & di(4 downto 0); -- LCA + if di(7 downto 0) = "10010010" or di(7 downto 0) = "00010010" then -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!) + tod_hrs_alarm(7) <= not tod_hrs_alarm(7); -- This P.O.S. now mimics real commodore 64 !!!!! LCA + end if; + when others => + null; + end case; + end if; + end if; + + -- Update state + tod_10ths <= new_10ths; + tod_secs <= new_secsH & new_secsL; + tod_mins <= new_minsH & new_minsL; + tod_hrs <= new_hrs_byte; -- LCA + + if tod_latched = '0' then + tod_latch_10ths <= new_10ths; + tod_latch_secs <= new_secsH & new_secsL; + tod_latch_mins <= new_minsH & new_minsL; + tod_latch_hrs <= new_hrs_byte; -- LCA + end if; + + -- TOD ALARM test for match - LCA + if (tod_10ths = tod_10ths_alarm) and + (tod_secs = tod_secs_alarm) and + (tod_mins = tod_mins_alarm) and + (tod_hrs = tod_hrs_alarm) and + (crb_alarm = '1') then + intr_alarm <= '1' ; + end if; + + if reset = '1' then + tod_running <= '0'; + tod_10ths_alarm <= "0000" ; + tod_secs_alarm <= "0000000" ; + tod_mins_alarm <= "0000000" ; + tod_hrs_alarm <= "00000000" ; + tod_pm_alarm <= '0' ; + end if; + + if resetIrq then + intr_alarm <= '0' ; + end if; + end if; + end process; + + -- Control TOD output latch + -- Reading the hours latches the output until + -- the 10ths of seconds are read. While latched the + -- clock continues to run in the bankground. + process(clk) + begin + if rising_edge(clk) then + if myRd = '1' then + case addr is + when X"8" => tod_latched <= '0'; + when X"B" => tod_latched <= '1'; + when others => null; + end case; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Timer A and B +-- ----------------------------------------------------------------------- + + +-- adjustable time delay jun17 - LCA + +-- ----------------------------------------------------------------------- +-- ----------------------------------------------------------------------- + + process(clk) + variable WR_delay : unsigned(15 downto 0); + begin + if rising_edge(clk) then + if (myWr = '0' or reset = '1') then + WR_delay := "0000000000000000"; + WR_Delay_offset <= '0'; +-- end if; + elsif (myWr = '1' and (WR_delay < 31)) then + WR_delay := WR_delay + 1; +-- end if; + elsif (WR_delay > 8) then -- adds a (1/32mhz * value) qualifier to WR signal in timers - LCA jun17 + WR_Delay_offset <= '1'; + else + WR_Delay_offset <= '0'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- + + process(clk) + variable newTimerA : unsigned(15 downto 0); + variable nextClkTimerA : std_logic; + variable timerBInput : std_logic; + variable newTimerB : unsigned(15 downto 0); + variable nextClkTimerB : std_logic; + variable new_cra_runmode : std_logic; + variable new_crb_runmode : std_logic; + begin + if rising_edge(clk) then + loadTimerA <= '0'; + loadTimerB <= '0'; + new_cra_runmode := cra_runmode; + new_crb_runmode := crb_runmode; + + if resetIrq then + intr_timerA <= '0'; + intr_timerB <= '0'; + end if; + + if myWr = '1' then +-- if (myWr = '1' and WR_Delay_offset = '1') then -- x/32mhz offset to qualify WR signal LCA jun17 + case addr is + when X"4" => + talo <= di; + when X"5" => + tahi <= di; + if cra_start = '0' then + loadTimerA <= '1'; + end if; + when X"6" => + tblo <= di; + when X"7" => + tbhi <= di; + if crb_start = '0' then + loadTimerB <= '1'; + end if; + when X"E" => + if cra_start = '0' then + -- Only set on rising edge + timerAToggle <= timerAToggle or di(0); + end if; + cra_start <= di(0); + new_cra_runmode := di(3); + when X"F" => + if crb_start = '0' then + -- Only set on rising edge + timerBToggle <= timerBToggle or di(0); + end if; + crb_start <= di(0); + new_crb_runmode := di(3); + when others => null; + end case; + end if; + + if reset = '1' then + new_cra_runmode := '0'; + new_crb_runmode := '0'; + end if; + + cra_runmode <= new_cra_runmode; + crb_runmode <= new_crb_runmode; + + if enable = '1' then + -- + -- process timer A + -- + timerAPulse <= '0'; + newTimerA := timerA; + + -- CNT is not emulated so don't count when inmode = 1 + nextClkTimerA := cra_start and (not cra_inmode); + if clkTimerA = '1' then + newTimerA := newTimerA - 1; + end if; + if nextClkTimerA = '1' + and newTimerA = 0 then + intr_timerA <= '1'; + loadTimerA <= '1'; + timerAPulse <= '1'; + timerAToggle <= not timerAToggle; + if (new_cra_runmode or cra_runmode) = '1' then + cra_start <= '0'; + end if; + end if; + if forceTimerA = '1' then + loadTimerA <= '1'; + end if; + clkTimerA <= nextClkTimerA; + timerA <= newTimerA; + + -- + -- process timer B + -- + timerBPulse <= '0'; + newTimerB := timerB; + + if crb_inmode6 = '1' then + -- count timerA underflows + timerBInput := timerAPulse; + elsif crb_inmode5 = '0' then + -- count clock pulses + timerBInput := '1'; + else + -- CNT is not emulated so don't count + timerBInput := '0'; + end if; + nextClkTimerB := timerBInput and crb_start; + if clkTimerB = '1' then + newTimerB := newTimerB - 1; + end if; + if nextClkTimerB = '1' + and newTimerB = 0 then + intr_timerB <= '1'; + loadTimerB <= '1'; + timerBPulse <= '1'; + timerBToggle <= not timerBToggle; + if (new_crb_runmode or crb_runmode) = '1' then + crb_start <= '0'; + end if; + end if; + if forceTimerB = '1' then + loadTimerB <= '1'; + end if; + clkTimerB <= nextClkTimerB; + timerB <= newTimerB; + end if; + + if loadTimerA = '1' then + timerA <= tahi & talo; + clkTimerA <= '0'; + end if; + + if loadTimerB = '1' then + timerB <= tbhi & tblo; + clkTimerB <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Interrupts +-- ----------------------------------------------------------------------- + resetIrq <= ((myRd = '1') and (addr = X"D")) or (reset = '1'); + irq_n <= not(ir); + intr_serial <= '0'; + + process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + ir <= ir + or (intr_timerA and mask_timerA) + or (intr_timerB and mask_timerB) + or (intr_alarm and mask_alarm) + or (intr_serial and mask_serial) + or (intr_flagn and mask_flagn); + end if; + + if myWr = '1' then + case addr is + when X"D" => + if di(7) ='0' then + mask_timerA <= mask_timerA and (not di(0)); + mask_timerB <= mask_timerB and (not di(1)); + mask_alarm <= mask_alarm and (not di(2)); -- LCA + mask_serial <= mask_serial and (not di(3)); + mask_flagn <= mask_flagn and (not di(4)); + else + mask_timerA <= mask_timerA or di(0); + mask_timerB <= mask_timerB or di(1); + mask_alarm <= mask_alarm or di(2); -- LCA + mask_serial <= mask_serial or di(3); + mask_flagn <= mask_flagn or di(4); + end if; + when others => + null; + end case; + end if; + + if resetIrq then + ir <= '0'; + end if; + + if reset = '1' then + mask_timerA <= '0'; + mask_timerB <= '0'; + mask_alarm <= '0' ; + mask_serial <= '0'; + mask_flagn <= '0'; + end if; + end if; + end process; + + + + +-- ----------------------------------------------------------------------- +-- FLAG_N input +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + prevFlag_n <= flag_n; + if (flag_n = '0') and (prevFlag_n = '1') then + intr_flagn <= '1'; + end if; + if resetIrq then + intr_flagn <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Write registers +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then +-- resetIrq <= '0'; + if enable = '1' then + forceTimerA <= '0'; + forceTimerB <= '0'; +-- cra_runmode_reg <= cra_runmode; +-- crb_runmode_reg <= crb_runmode; + end if; + if myWr = '1' then + case addr is + when X"E" => + cra_pbon <= di(1); + cra_outmode <= di(2); +-- cra_runmode <= di(3); + forceTimerA <= di(4); + cra_inmode <= di(5); + cra_spmode <= di(6); + cra_todin <= di(7); + when X"F" => + crb_pbon <= di(1); + crb_outmode <= di(2); +-- crb_runmode <= di(3); + forceTimerB <= di(4); + crb_inmode5 <= di(5); + crb_inmode6 <= di(6); + crb_alarm <= di(7); + when others => null; + end case; + end if; + if reset = '1' then + cra_pbon <= '0'; + cra_outmode <= '0'; +-- cra_runmode <= '0'; + cra_inmode <= '0'; + cra_spmode <= '0'; + cra_todin <= '0'; + crb_pbon <= '0'; + crb_outmode <= '0'; +-- crb_runmode <= '0'; + crb_inmode5 <= '0'; + crb_inmode6 <= '0'; + crb_alarm <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Read registers +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + case addr is + when X"0" => do <= ppai; + when X"1" => do <= ppbi; + when X"2" => do <= DDRA; + when X"3" => do <= DDRB; + when X"4" => do <= timera(7 downto 0); + when X"5" => do <= timera(15 downto 8); + when X"6" => do <= timerb(7 downto 0); + when X"7" => do <= timerb(15 downto 8); + when X"8" => do <= "0000" & tod_latch_10ths; + when X"9" => do <= "0" & tod_latch_secs; + when X"A" => do <= "0" & tod_latch_mins; +-- when X"B" => do <= tod_latch_pm & "00" & tod_latch_hrs; + when X"B" => do <= tod_latch_hrs; -- LCA + when X"C" => do <= (others => '0'); + when X"D" => do <= ir & "00" & intr_flagn & intr_serial & intr_alarm & intr_timerB & intr_timerA; + when X"E" => do <= cra_todin & cra_spmode & cra_inmode & '0' & cra_runmode & cra_outmode & cra_pbon & cra_start; + when X"F" => do <= crb_alarm & crb_inmode6 & crb_inmode5 & '0' & crb_runmode & crb_outmode & crb_pbon & crb_start; + when others => do <= (others => '-'); + end case; + end if; + end process; +end Behavioral; diff --git a/Commodore - 64_Mist/rtl/composite_sync.vhd b/Commodore - 64_Mist/rtl/composite_sync.vhd new file mode 100644 index 00000000..216cece4 --- /dev/null +++ b/Commodore - 64_Mist/rtl/composite_sync.vhd @@ -0,0 +1,96 @@ +--------------------------------------------------------------------------------- +-- composite_sync by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- +-- Generate composite sync and blank for tv mode from h/v syncs +-- +--------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity composite_sync is +port( + clk32 : in std_logic; + hsync : in std_logic; + vsync : in std_logic; + ntsc : in std_logic; + hsync_out : out std_logic; + vsync_out : out std_logic; + blank : out std_logic +); +end composite_sync ; + +architecture struct of composite_sync is + + signal clk_cnt : std_logic_vector(1 downto 0); + signal vsync_r : std_logic; + signal hsync_r : std_logic; + signal hsync_r0 : std_logic; + signal vblank : std_logic; + signal hblank : std_logic; + +begin + +blank <= hblank or vblank; + +process(clk32) + variable dot_count : integer range 0 to 1023 := 0; + variable line_count : integer range 0 to 511 := 0; + begin + if falling_edge(clk32) then + hsync_r0 <= hsync; + if hsync_r0 = '0' and hsync = '1' then + clk_cnt <= "00"; + else + clk_cnt <= clk_cnt + '1'; + end if; + end if; + + if rising_edge(clk32) then + if clk_cnt = "00" then + vsync_r <= vsync; + hsync_r <= hsync; + + if hsync_r = '0' and hsync = '1' then + dot_count := 0; + line_count := line_count + 1; + else + dot_count := dot_count + 1; + end if; + + if vsync_r = '0' and vsync = '1' then + line_count := 0; + end if; + + if ntsc = '1' then + if dot_count = 510 then hblank <= '1'; end if; + if dot_count = 010 then hsync_out <= '1'; end if; + if dot_count = 048 then hsync_out <= '0'; end if; + if dot_count = 096 then hblank <= '0'; end if; + + if line_count = 260 then vblank <= '1'; end if; + if line_count = 262 then vsync_out <= '1'; end if; + if line_count = 008 then vsync_out <= '0'; end if; + if line_count = 010 then vblank <= '0'; end if; + else + if dot_count = 495 then hblank <= '1'; end if; + if dot_count = 010 then hsync_out <= '1'; end if; + if dot_count = 048 then hsync_out <= '0'; end if; + if dot_count = 094 then hblank <= '0'; end if; + + if line_count = 306 then vblank <= '1'; end if; + if line_count = 308 then vsync_out <= '1'; end if; + if line_count = 004 then vsync_out <= '0'; end if; + if line_count = 006 then vblank <= '0'; end if; + end if; + + end if; + end if; +end process; + + + +end architecture; \ No newline at end of file diff --git a/Commodore - 64_Mist/rtl/cpu65xx_e.vhd b/Commodore - 64_Mist/rtl/cpu65xx_e.vhd new file mode 100644 index 00000000..27166e7a --- /dev/null +++ b/Commodore - 64_Mist/rtl/cpu65xx_e.vhd @@ -0,0 +1,49 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Interface to 6502/6510 core +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cpu65xx is + generic ( + pipelineOpcode : boolean; + pipelineAluMux : boolean; + pipelineAluOut : boolean + ); + port ( + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + nmi_n : in std_logic; + nmi_ack : out std_logic; + irq_n : in std_logic; + so_n : in std_logic := '1'; + + di : in unsigned(7 downto 0); + do : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic; + + debugOpcode : out unsigned(7 downto 0); + debugPc : out unsigned(15 downto 0); + debugA : out unsigned(7 downto 0); + debugX : out unsigned(7 downto 0); + debugY : out unsigned(7 downto 0); + debugS : out unsigned(7 downto 0) + ); +end cpu65xx; \ No newline at end of file diff --git a/Commodore - 64_Mist/rtl/cpu65xx_fast.vhd b/Commodore - 64_Mist/rtl/cpu65xx_fast.vhd new file mode 100644 index 00000000..a387b37d --- /dev/null +++ b/Commodore - 64_Mist/rtl/cpu65xx_fast.vhd @@ -0,0 +1,1565 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Table driven, cycle exact 6502/6510 core +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +-- Store Zp (3) => fetch, cycle2, cycleEnd +-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd +-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2 +-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd +-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd +-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd +-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd +-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump +-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump +-- Jmp abs (-) => fetch, cycle2, .., cycleJump +-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump +-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4 +-- ----------------------------------------------------------------------- + +architecture fast of cpu65xx is +-- Statemachine + type cpuCycles is ( + opcodeFetch, -- New opcode is read and registers updated + cycle2, + cycle3, + cyclePreIndirect, + cycleIndirect, + cycleBranchTaken, + cycleBranchPage, + cyclePreRead, -- Cycle before read while doing zeropage indexed addressing. + cycleRead, -- Read cycle + cycleRead2, -- Second read cycle after page-boundary crossing. + cycleRmw, -- Calculate ALU output for read-modify-write instr. + cyclePreWrite, -- Cycle before write when doing indexed addressing. + cycleWrite, -- Write cycle for zeropage or absolute addressing. + cycleStack1, + cycleStack2, + cycleStack3, + cycleStack4, + cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr. + cycleEnd + ); + signal theCpuCycle : cpuCycles; + signal nextCpuCycle : cpuCycles; + signal updateRegisters : boolean; + signal processIrq : std_logic; + signal nmiReg: std_logic; + signal nmiEdge: std_logic; + signal irqReg : std_logic; -- Delay IRQ input with one clock cycle. + signal soReg : std_logic; -- SO pin edge detection + +-- Opcode decoding + constant opcUpdateA : integer := 0; + constant opcUpdateX : integer := 1; + constant opcUpdateY : integer := 2; + constant opcUpdateS : integer := 3; + constant opcUpdateN : integer := 4; + constant opcUpdateV : integer := 5; + constant opcUpdateD : integer := 6; + constant opcUpdateI : integer := 7; + constant opcUpdateZ : integer := 8; + constant opcUpdateC : integer := 9; + + constant opcSecondByte : integer := 10; + constant opcAbsolute : integer := 11; + constant opcZeroPage : integer := 12; + constant opcIndirect : integer := 13; + constant opcStackAddr : integer := 14; -- Push/Pop address + constant opcStackData : integer := 15; -- Push/Pop status/data + constant opcJump : integer := 16; + constant opcBranch : integer := 17; + constant indexX : integer := 18; + constant indexY : integer := 19; + constant opcStackUp : integer := 20; + constant opcWrite : integer := 21; + constant opcRmw : integer := 22; + constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS) + constant opcRti : integer := 24; + constant opcIRQ : integer := 25; + + constant opcInA : integer := 26; + constant opcInE : integer := 27; + constant opcInX : integer := 28; + constant opcInY : integer := 29; + constant opcInS : integer := 30; + constant opcInT : integer := 31; + constant opcInH : integer := 32; + constant opcInClear : integer := 33; + constant aluMode1From : integer := 34; + -- + constant aluMode1To : integer := 37; + constant aluMode2From : integer := 38; + -- + constant aluMode2To : integer := 40; + -- + constant opcInCmp : integer := 41; + constant opcInCpx : integer := 42; + constant opcInCpy : integer := 43; + + + subtype addrDef is unsigned(0 to 15); + -- + -- is Interrupt -----------------+ + -- instruction is RTI ----------------+| + -- PC++ on last cycle (RTS) ---------------+|| + -- RMW --------------+||| + -- Write -------------+|||| + -- Pop/Stack up -------------+||||| + -- Branch ---------+ |||||| + -- Jump ----------+| |||||| + -- Push or Pop data -------+|| |||||| + -- Push or Pop addr ------+||| |||||| + -- Indirect -----+|||| |||||| + -- ZeroPage ----+||||| |||||| + -- Absolute ---+|||||| |||||| + -- PC++ on cycle2 --+||||||| |||||| + -- |AZI||JBXY|WM||| + constant immediate : addrDef := "1000000000000000"; + constant implied : addrDef := "0000000000000000"; + -- Zero page + constant readZp : addrDef := "1010000000000000"; + constant writeZp : addrDef := "1010000000010000"; + constant rmwZp : addrDef := "1010000000001000"; + -- Zero page indexed + constant readZpX : addrDef := "1010000010000000"; + constant writeZpX : addrDef := "1010000010010000"; + constant rmwZpX : addrDef := "1010000010001000"; + constant readZpY : addrDef := "1010000001000000"; + constant writeZpY : addrDef := "1010000001010000"; + constant rmwZpY : addrDef := "1010000001001000"; + -- Zero page indirect + constant readIndX : addrDef := "1001000010000000"; + constant writeIndX : addrDef := "1001000010010000"; + constant rmwIndX : addrDef := "1001000010001000"; + constant readIndY : addrDef := "1001000001000000"; + constant writeIndY : addrDef := "1001000001010000"; + constant rmwIndY : addrDef := "1001000001001000"; + -- |AZI||JBXY|WM|| + -- Absolute + constant readAbs : addrDef := "1100000000000000"; + constant writeAbs : addrDef := "1100000000010000"; + constant rmwAbs : addrDef := "1100000000001000"; + constant readAbsX : addrDef := "1100000010000000"; + constant writeAbsX : addrDef := "1100000010010000"; + constant rmwAbsX : addrDef := "1100000010001000"; + constant readAbsY : addrDef := "1100000001000000"; + constant writeAbsY : addrDef := "1100000001010000"; + constant rmwAbsY : addrDef := "1100000001001000"; + -- PHA PHP + constant push : addrDef := "0000010000000000"; + -- PLA PLP + constant pop : addrDef := "0000010000100000"; + -- Jumps + constant jsr : addrDef := "1000101000000000"; + constant jumpAbs : addrDef := "1000001000000000"; + constant jumpInd : addrDef := "1100001000000000"; + constant relative : addrDef := "1000000100000000"; + -- Specials + constant rts : addrDef := "0000101000100100"; + constant rti : addrDef := "0000111000100010"; + constant brk : addrDef := "1000111000000001"; +-- constant : unsigned(0 to 0) := "0"; + constant xxxxxxxx : addrDef := "----------0---00"; + + -- A = accu + -- E = Accu | 0xEE (for ANE, LXA) + -- X = index X + -- Y = index Y + -- S = Stack pointer + -- H = indexH + -- + -- AEXYSTHc + constant aluInA : unsigned(0 to 7) := "10000000"; + constant aluInE : unsigned(0 to 7) := "01000000"; + constant aluInEXT : unsigned(0 to 7) := "01100100"; + constant aluInET : unsigned(0 to 7) := "01000100"; + constant aluInX : unsigned(0 to 7) := "00100000"; + constant aluInXH : unsigned(0 to 7) := "00100010"; + constant aluInY : unsigned(0 to 7) := "00010000"; + constant aluInYH : unsigned(0 to 7) := "00010010"; + constant aluInS : unsigned(0 to 7) := "00001000"; + constant aluInT : unsigned(0 to 7) := "00000100"; + constant aluInAX : unsigned(0 to 7) := "10100000"; + constant aluInAXH : unsigned(0 to 7) := "10100010"; + constant aluInAT : unsigned(0 to 7) := "10000100"; + constant aluInXT : unsigned(0 to 7) := "00100100"; + constant aluInST : unsigned(0 to 7) := "00001100"; + constant aluInSet : unsigned(0 to 7) := "00000000"; + constant aluInClr : unsigned(0 to 7) := "00000001"; + constant aluInXXX : unsigned(0 to 7) := "--------"; + + -- Most of the aluModes are just like the opcodes. + -- aluModeInp -> input is output. calculate N and Z + -- aluModeCmp -> Compare for CMP, CPX, CPY + -- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV + -- aluModeInc -> for INC but also INX, INY + -- aluModeDec -> for DEC but also DEX, DEY + + subtype aluMode1 is unsigned(0 to 3); + subtype aluMode2 is unsigned(0 to 2); + subtype aluMode is unsigned(0 to 9); + + -- Logic/Shift ALU + constant aluModeInp : aluMode1 := "0000"; + constant aluModeP : aluMode1 := "0001"; + constant aluModeInc : aluMode1 := "0010"; + constant aluModeDec : aluMode1 := "0011"; + constant aluModeFlg : aluMode1 := "0100"; + constant aluModeBit : aluMode1 := "0101"; + -- 0110 + -- 0111 + constant aluModeLsr : aluMode1 := "1000"; + constant aluModeRor : aluMode1 := "1001"; + constant aluModeAsl : aluMode1 := "1010"; + constant aluModeRol : aluMode1 := "1011"; + -- 1100 + -- 1101 + -- 1110 + constant aluModeAnc : aluMode1 := "1111"; + + -- Arithmetic ALU + constant aluModePss : aluMode2 := "000"; + constant aluModeCmp : aluMode2 := "001"; + constant aluModeAdc : aluMode2 := "010"; + constant aluModeSbc : aluMode2 := "011"; + constant aluModeAnd : aluMode2 := "100"; + constant aluModeOra : aluMode2 := "101"; + constant aluModeEor : aluMode2 := "110"; + constant aluModeArr : aluMode2 := "111"; + + + constant aluInp : aluMode := aluModeInp & aluModePss & "---"; + constant aluP : aluMode := aluModeP & aluModePss & "---"; + constant aluInc : aluMode := aluModeInc & aluModePss & "---"; + constant aluDec : aluMode := aluModeDec & aluModePss & "---"; + constant aluFlg : aluMode := aluModeFlg & aluModePss & "---"; + constant aluBit : aluMode := aluModeBit & aluModeAnd & "---"; + constant aluRor : aluMode := aluModeRor & aluModePss & "---"; + constant aluLsr : aluMode := aluModeLsr & aluModePss & "---"; + constant aluRol : aluMode := aluModeRol & aluModePss & "---"; + constant aluAsl : aluMode := aluModeAsl & aluModePss & "---"; + + constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100"; + constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010"; + constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001"; + constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---"; + constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---"; + constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---"; + constant aluOra : aluMode := aluModeInp & aluModeOra & "---"; + constant aluEor : aluMode := aluModeInp & aluModeEor & "---"; + + constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---"; + constant aluSre : aluMode := aluModeLsr & aluModeEor & "---"; + constant aluRra : aluMode := aluModeRor & aluModeAdc & "---"; + constant aluRla : aluMode := aluModeRol & aluModeAnd & "---"; + constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100"; + constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---"; + constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---"; + constant aluArr : aluMode := aluModeRor & aluModeArr & "---"; + constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110"; + + constant aluXXX : aluMode := (others => '-'); + + + -- Stack operations. Push/Pop/None + constant stackInc : unsigned(0 to 0) := "0"; + constant stackDec : unsigned(0 to 0) := "1"; + constant stackXXX : unsigned(0 to 0) := "-"; + + subtype decodedBitsDef is unsigned(0 to 43); + type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef; + constant opcodeInfoTable : opcodeInfoTableDef := ( + -- +------- Update register A + -- |+------ Update register X + -- ||+----- Update register Y + -- |||+---- Update register S + -- |||| +-- Update Flags + -- |||| | + -- |||| _|__ + -- |||| / \ + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK + "1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp + "1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp + "0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp + "1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp + "0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP + "1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm + "1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm + "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs + "1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs + "0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs + "1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL + "1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x + "0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x + "0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC + "1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR + "1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x) + "0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp + "1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp + "0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp + "1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp + "0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP + "1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm + "1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm + "0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs + "1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs + "0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs + "1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI + "1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x + "0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC + "1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI + "1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp + "1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp + "0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp + "1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp + "0000" & "000000" & push & aluInA & aluInp, -- 48 PHA + "1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm + "1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu + "1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm + "0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs + "1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs + "0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs + "1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC + "1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x + "0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x + "0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI + "1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS + "1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM *** + "1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp + "1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp + "0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp + "1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp + "1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA + "1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm + "1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu + "1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm + "0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect + "1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs + "0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs + "1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS + "1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x + "1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x + "0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI + "1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm + "0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm + "0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x) + "0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp + "0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp + "0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp + "0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp + "0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm + "1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA + "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm + "0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs + "0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs + "0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs + "0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC + "0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM *** + "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y + "0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x + "0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x + "0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y + "0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y + "1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA + "0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y + "0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS + "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y + "0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x + "0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x + "0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y + "0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm + "1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x) + "0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm + "1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x) + "0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp + "1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp + "0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp + "1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp + "0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY + "1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm + "0100" & "100010" & implied & aluInA & aluInp, -- AA TAX + "1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm + "0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs + "1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs + "0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs + "1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS + "1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM *** + "1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y + "0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x + "1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x + "0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y + "1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y + "0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV + "1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y + "0100" & "100010" & implied & aluInS & aluInp, -- BA TSX + "1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y + "0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x + "1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x + "0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y + "1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm + "0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm + "0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp + "0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp + "0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp + "0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp + "0010" & "100010" & implied & aluInY & aluInc, -- C8 INY + "0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm + "0100" & "100010" & implied & aluInX & aluDec, -- CA DEX + "0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm + "0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs + "0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs + "0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs + "0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE + "0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM *** + "0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x + "0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x + "0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x + "0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD + "0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied + "0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x + "0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm + "1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm + "1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp + "1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp + "0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp + "1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp + "0100" & "100010" & implied & aluInX & aluInc, -- E8 INX + "1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm + "0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP + "1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc) + "0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs + "1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs + "0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs + "1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ + "1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x + "0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x + "1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x + "0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED + "1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x + ); + signal opcInfo : decodedBitsDef; + signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded) + signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined + signal theOpcode : unsigned(7 downto 0); + signal nextOpcode : unsigned(7 downto 0); + +-- Program counter + signal PC : unsigned(15 downto 0); -- Program counter + +-- Address generation + type nextAddrDef is ( + nextAddrHold, + nextAddrIncr, + nextAddrIncrL, -- Increment low bits only (zeropage accesses) + nextAddrIncrH, -- Increment high bits only (page-boundary) + nextAddrDecrH, -- Decrement high bits (branch backwards) + nextAddrPc, + nextAddrIrq, + nextAddrReset, + nextAddrAbs, + nextAddrAbsIndexed, + nextAddrZeroPage, + nextAddrZPIndexed, + nextAddrStack, + nextAddrRelative + ); + signal nextAddr : nextAddrDef; + signal myAddr : unsigned(15 downto 0); + signal myAddrIncr : unsigned(15 downto 0); + signal myAddrIncrH : unsigned(7 downto 0); + signal myAddrDecrH : unsigned(7 downto 0); + signal theWe : std_logic; + + signal irqActive : std_logic; + +-- Output register + signal doReg : unsigned(7 downto 0); + +-- Buffer register + signal T : unsigned(7 downto 0); + +-- General registers + signal A: unsigned(7 downto 0); -- Accumulator + signal X: unsigned(7 downto 0); -- Index X + signal Y: unsigned(7 downto 0); -- Index Y + signal S: unsigned(7 downto 0); -- stack pointer + +-- Status register + signal C: std_logic; -- Carry + signal Z: std_logic; -- Zero flag + signal I: std_logic; -- Interrupt flag + signal D: std_logic; -- Decimal mode + signal V: std_logic; -- Overflow + signal N: std_logic; -- Negative + +-- ALU + -- ALU input + signal aluInput : unsigned(7 downto 0); + signal aluCmpInput : unsigned(7 downto 0); + -- ALU output + signal aluRegisterOut : unsigned(7 downto 0); + signal aluRmwOut : unsigned(7 downto 0); + signal aluC : std_logic; + signal aluZ : std_logic; + signal aluV : std_logic; + signal aluN : std_logic; + -- Pipeline registers + signal aluInputReg : unsigned(7 downto 0); + signal aluCmpInputReg : unsigned(7 downto 0); + signal aluRmwReg : unsigned(7 downto 0); + signal aluNineReg : unsigned(7 downto 0); + signal aluCReg : std_logic; + signal aluZReg : std_logic; + signal aluVReg : std_logic; + signal aluNReg : std_logic; + +-- Indexing + signal indexOut : unsigned(8 downto 0); + +begin +processAluInput: process(clk, opcInfo, A, X, Y, T, S) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInA) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInE) = '1' then + temp := temp and (A or X"EE"); + end if; + if opcInfo(opcInX) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInY) = '1' then + temp := temp and Y; + end if; + if opcInfo(opcInS) = '1' then + temp := temp and S; + end if; + if opcInfo(opcInT) = '1' then + temp := temp and T; + end if; + if opcInfo(opcInClear) = '1' then + temp := (others => '0'); + end if; + if rising_edge(clk) then + aluInputReg <= temp; + end if; + + aluInput <= temp; + if pipelineAluMux then + aluInput <= aluInputReg; + end if; + end process; + +processCmpInput: process(clk, opcInfo, A, X, Y) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInCmp) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInCpx) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInCpy) = '1' then + temp := temp and Y; + end if; + if rising_edge(clk) then + aluCmpInputReg <= temp; + end if; + + aluCmpInput <= temp; + if pipelineAluMux then + aluCmpInput <= aluCmpInputReg; + end if; + end process; + + -- ALU consists of two parts + -- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL + -- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA + -- Some instructions are both RMW and accumulator so for most + -- instructions the rmw results are routed through accu alu too. +processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C) + variable lowBits: unsigned(5 downto 0); + variable nineBits: unsigned(8 downto 0); + variable rmwBits: unsigned(8 downto 0); + + variable varC : std_logic; + variable varZ : std_logic; + variable varV : std_logic; + variable varN : std_logic; + begin + lowBits := (others => '-'); + nineBits := (others => '-'); + rmwBits := (others => '-'); + varV := aluInput(6); -- Default for BIT / PLP / RTI + + -- Shift unit + case opcInfo(aluMode1From to aluMode1To) is + when aluModeInp => + rmwBits := C & aluInput; + when aluModeP => + rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C; + when aluModeInc => + rmwBits := C & (aluInput + 1); + when aluModeDec => + rmwBits := C & (aluInput - 1); + when aluModeAsl => + rmwBits := aluInput & "0"; + when aluModeFlg => + rmwBits := aluInput(0) & aluInput; + when aluModeLsr => + rmwBits := aluInput(0) & "0" & aluInput(7 downto 1); + when aluModeRol => + rmwBits := aluInput & C; + when aluModeRoR => + rmwBits := aluInput(0) & C & aluInput(7 downto 1); + when aluModeAnc => + rmwBits := (aluInput(7) and A(7)) & aluInput; + when others => + rmwBits := C & aluInput; + end case; + + -- ALU + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1"); + ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8)); + when aluModeSbc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1"); + ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8)); + when aluModeCmp => + ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001"; + when aluModeAnd => + ninebits := rmwBits(8) & (A and rmwBits(7 downto 0)); + when aluModeEor => + ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0)); + when aluModeOra => + ninebits := rmwBits(8) & (A or rmwBits(7 downto 0)); + when others => + ninebits := rmwBits; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varZ := rmwBits(1); + elsif ninebits(7 downto 0) = X"00" then + varZ := '1'; + else + varZ := '0'; + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode low bits correction, is done after setting Z flag. + if D = '1' then + if lowBits(5 downto 1) > 9 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + if lowBits(5) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) + 1; + end if; + end if; + end if; + when others => + null; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) + or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varN := rmwBits(7); + else + varN := nineBits(7); + end if; + varC := ninebits(8); + if opcInfo(aluMode2From to aluMode2To) = aluModeArr then + varC := aluInput(7); + varV := aluInput(7) xor aluInput(6); + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode high bits correction, is done after setting Z and N flags + varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7)); + if D = '1' then + if ninebits(8 downto 4) > 9 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + end if; + end if; + when aluModeSbc => + varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7)); + if D = '1' then + -- Check for borrow (lower 4 bits) + if lowBits(5) = '0' then + ninebits(3 downto 0) := ninebits(3 downto 0) - 6; + end if; + -- Check for borrow (upper 4 bits) + if ninebits(8) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) - 6; + end if; + end if; + when aluModeArr => + if D = '1' then + if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + end if; + if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + else + varC := '0'; + end if; + end if; + when others => + null; + end case; + + if rising_edge(clk) then + aluRmwReg <= rmwBits(7 downto 0); + aluNineReg <= ninebits(7 downto 0); + aluCReg <= varC; + aluZReg <= varZ; + aluVReg <= varV; + aluNReg <= varN; + end if; + + aluRmwOut <= rmwBits(7 downto 0); + aluRegisterOut <= ninebits(7 downto 0); + aluC <= varC; + aluZ <= varZ; + aluV <= varV; + aluN <= varN; + if pipelineAluOut then + aluRmwOut <= aluRmwReg; + aluRegisterOut <= aluNineReg; + aluC <= aluCReg; + aluZ <= aluZReg; + aluV <= aluVReg; + aluN <= aluNReg; + end if; + end process; + +calcInterrupt: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = cycleStack4 + or reset = '1' then + nmiReg <= '1'; + end if; + + if nextCpuCycle /= cycleBranchTaken + and nextCpuCycle /= opcodeFetch then + irqReg <= irq_n; + nmiEdge <= nmi_n; + if (nmiEdge = '1') and (nmi_n = '0') then + nmiReg <= '0'; + end if; + end if; + -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ. + -- Presumably this is done in the real 6502/6510 to prevent a double IRQ. + processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ)); + end if; + end if; + end process; + +calcNextOpcode: process(clk, di, reset, processIrq) + variable myNextOpcode : unsigned(7 downto 0); + begin + -- Next opcode is read from input unless a reset or IRQ is pending. + myNextOpcode := di; + if reset = '1' then + myNextOpcode := X"4C"; + elsif processIrq = '1' then + myNextOpcode := X"00"; + end if; + + nextOpcode <= myNextOpcode; + end process; + + nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode)); + process(clk) + begin + if rising_edge(clk) then + nextOpcInfoReg <= nextOpcInfo; + end if; + end process; + + -- Read bits and flags from opcodeInfoTable and store in opcInfo. + -- This info is used to control the execution of the opcode. +calcOpcInfo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if (reset = '1') or (theCpuCycle = opcodeFetch) then + opcInfo <= nextOpcInfo; + if pipelineOpcode then + opcInfo <= nextOpcInfoReg; + end if; + end if; + end if; + end if; + end process; + +calcTheOpcode: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = opcodeFetch then + irqActive <= '0'; + if processIrq = '1' then + irqActive <= '1'; + end if; + -- Fetch opcode + theOpcode <= nextOpcode; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- State machine +-- ----------------------------------------------------------------------- + process(enable, theCpuCycle, opcInfo) + begin + updateRegisters <= false; + if enable = '1' then + if opcInfo(opcRti) = '1' then + if theCpuCycle = cycleRead then + updateRegisters <= true; + end if; + elsif theCpuCycle = opcodeFetch then + updateRegisters <= true; + end if; + end if; + end process; + + debugOpcode <= theOpcode; + process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theCpuCycle <= nextCpuCycle; + end if; + if reset = '1' then + theCpuCycle <= cycle2; + end if; + end if; + end process; + + -- Determine the next cpu cycle. After the last cycle we always + -- go to opcodeFetch to get the next opcode. +calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z) + begin + nextCpuCycle <= opcodeFetch; + + case theCpuCycle is + when opcodeFetch => + nextCpuCycle <= cycle2; + when cycle2 => + if opcInfo(opcBranch) = '1' then + if (N = theOpcode(5) and theOpcode(7 downto 6) = "00") + or (V = theOpcode(5) and theOpcode(7 downto 6) = "01") + or (C = theOpcode(5) and theOpcode(7 downto 6) = "10") + or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then + -- Branch condition is true + nextCpuCycle <= cycleBranchTaken; + end if; + elsif (opcInfo(opcStackUp) = '1') then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackAddr) = '1' + and opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleStack2; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleWrite; + elsif opcInfo(opcAbsolute) = '1' then + nextCpuCycle <= cycle3; + elsif opcInfo(opcIndirect) = '1' then + if opcInfo(indexX) = '1' then + nextCpuCycle <= cyclePreIndirect; + else + nextCpuCycle <= cycleIndirect; + end if; + elsif opcInfo(opcZeroPage) = '1' then + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + else + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreRead; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + elsif opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycle3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + end if; + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + if opcInfo(opcWrite) = '1' then + nextCpuCycle <= cycleWrite; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + when cyclePreIndirect => + nextCpuCycle <= cycleIndirect; + when cycleIndirect => + nextCpuCycle <= cycle3; + when cycleBranchTaken => + if indexOut(8) /= T(7) then + -- Page boundary crossing during branch. + nextCpuCycle <= cycleBranchPage; + end if; + when cyclePreRead => + if opcInfo(opcZeroPage) = '1' then + nextCpuCycle <= cycleRead2; + end if; + when cycleRead => + if opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + elsif indexOut(8) = '1' then + -- Page boundary crossing while indexed addressing. + nextCpuCycle <= cycleRead2; + elsif opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + if opcInfo(indexX) = '1' + or opcInfo(indexY) = '1' then + -- 6510 needs extra cycle for indexed addressing + -- combined with RMW indexing + nextCpuCycle <= cycleRead2; + end if; + end if; + when cycleRead2 => + if opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + end if; + when cycleRmw => + nextCpuCycle <= cycleWrite; + when cyclePreWrite => + nextCpuCycle <= cycleWrite; + when cycleStack1 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack2; + end if; + when cycleStack2 => + nextCpuCycle <= cycleStack3; + if opcInfo(opcRti) = '1' then + nextCpuCycle <= cycleRead; + end if; + if opcInfo(opcStackData) = '0' + and opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycleStack3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackData) = '0' + or opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack4; + end if; + when cycleStack4 => + nextCpuCycle <= cycleRead; + when cycleJump => + if opcInfo(opcIncrAfter) = '1' then + -- Insert extra cycle + nextCpuCycle <= cycleEnd; + end if; + when others => + null; + end case; + end process; + +-- ----------------------------------------------------------------------- +-- T register +-- ----------------------------------------------------------------------- +calcT: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when cycle2 => + T <= di; + when cycleStack1 | cycleStack2 => + if opcInfo(opcStackUp) = '1' then + -- Read from stack + T <= di; + end if; + when cycleIndirect | cycleRead | cycleRead2 => + T <= di; + when others => + null; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- A register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateA) = '1' then + A <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- X register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateX) = '1' then + X <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Y register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateY) = '1' then + Y <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- C flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateC) = '1' then + C <= aluC; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Z flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateZ) = '1' then + Z <= aluZ; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- I flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateI) = '1' then + I <= aluInput(2); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- D flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateD) = '1' then + D <= aluInput(3); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- V flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateV) = '1' then + V <= aluV; + end if; + end if; + if enable = '1' then + if soReg = '1' and so_n = '0' then + V <= '1'; + end if; + soReg <= so_n; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- N flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateN) = '1' then + N <= aluN; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Stack pointer +-- ----------------------------------------------------------------------- + process(clk) + variable sIncDec : unsigned(7 downto 0); + variable updateFlag : boolean; + begin + if rising_edge(clk) then + + if opcInfo(opcStackUp) = '1' then + sIncDec := S + 1; + else + sIncDec := S - 1; + end if; + + if enable = '1' then + updateFlag := false; + case nextCpuCycle is + when cycleStack1 => + if (opcInfo(opcStackUp) = '1') + or (opcInfo(opcStackData) = '1') then + updateFlag := true; + end if; + when cycleStack2 => + updateFlag := true; + when cycleStack3 => + updateFlag := true; + when cycleStack4 => + updateFlag := true; + when cycleRead => + if opcInfo(opcRti) = '1' then + updateFlag := true; + end if; + when cycleWrite => + if opcInfo(opcStackData) = '1' then + updateFlag := true; + end if; + when others => + null; + end case; + if updateFlag then + S <= sIncDec; + end if; + end if; + if updateRegisters then + if opcInfo(opcUpdateS) = '1' then + S <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Data out +-- ----------------------------------------------------------------------- +--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T) +calcDo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + doReg <= aluRmwOut; + if opcInfo(opcInH) = '1' then + -- For illegal opcodes SHA, SHX, SHY, SHS + doReg <= aluRmwOut and myAddrIncrH; + end if; + + case nextCpuCycle is + when cycleStack2 => + if opcInfo(opcIRQ) = '1' + and irqActive = '0' then + doReg <= myAddrIncr(15 downto 8); + else + doReg <= PC(15 downto 8); + end if; + when cycleStack3 => + doReg <= PC(7 downto 0); + when cycleRmw => +-- do <= T; -- Read-modify-write write old value first. + doReg <= di; -- Read-modify-write write old value first. + when others => null; + end case; + end if; + end if; + end process; + do <= doReg; + + + +-- ----------------------------------------------------------------------- +-- Write enable +-- ----------------------------------------------------------------------- +calcWe: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theWe <= '0'; + case nextCpuCycle is + when cycleStack1 => + if opcInfo(opcStackUp) = '0' + and ((opcInfo(opcStackAddr) = '0') + or (opcInfo(opcStackData) = '1')) then + theWe <= '1'; + end if; + when cycleStack2 | cycleStack3 | cycleStack4 => + if opcInfo(opcStackUp) = '0' then + theWe <= '1'; + end if; + when cycleRmw => + theWe <= '1'; + when cycleWrite => + theWe <= '1'; + when others => + null; + end case; + end if; + end if; + end process; + we <= theWe; + +-- ----------------------------------------------------------------------- +-- Program counter +-- ----------------------------------------------------------------------- +calcPC: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when opcodeFetch => + PC <= myAddr; + when cycle2 => + if irqActive = '0' then + if opcInfo(opcSecondByte) = '1' then + PC <= myAddrIncr; + else + PC <= myAddr; + end if; + end if; + when cycle3 => + if opcInfo(opcAbsolute) = '1' then + PC <= myAddrIncr; + end if; + when others => + null; + end case; + end if; + end if; + end process; + debugPc <= PC; + +-- ----------------------------------------------------------------------- +-- Address generation +-- ----------------------------------------------------------------------- +calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset) + begin + nextAddr <= nextAddrIncr; + case theCpuCycle is + when cycle2 => + if opcInfo(opcStackAddr) = '1' + or opcInfo(opcStackData) = '1' then + nextAddr <= nextAddrStack; + elsif opcInfo(opcAbsolute) = '1' then + nextAddr <= nextAddrIncr; + elsif opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcIndirect) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcSecondByte) = '1' then + nextAddr <= nextAddrIncr; + else + nextAddr <= nextAddrHold; + end if; + when cycle3 => + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + nextAddr <= nextAddrAbs; + else + nextAddr <= nextAddrAbsIndexed; + end if; + when cyclePreIndirect => + nextAddr <= nextAddrZPIndexed; + when cycleIndirect => + nextAddr <= nextAddrIncrL; + when cycleBranchTaken => + nextAddr <= nextAddrRelative; + when cycleBranchPage => + if T(7) = '0' then + nextAddr <= nextAddrIncrH; + else + nextAddr <= nextAddrDecrH; + end if; + when cyclePreRead => + nextAddr <= nextAddrZPIndexed; + when cycleRead => + nextAddr <= nextAddrPc; + if opcInfo(opcJump) = '1' then + -- Emulate 6510 bug, jmp(xxFF) fetches from same page. + -- Replace with nextAddrIncr if emulating 65C02 or later cpu. + nextAddr <= nextAddrIncrL; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + elsif opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRead2 => + nextAddr <= nextAddrPc; + if opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRmw => + nextAddr <= nextAddrHold; + when cyclePreWrite => + nextAddr <= nextAddrHold; + if opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZPIndexed; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + end if; + when cycleWrite => + nextAddr <= nextAddrPc; + when cycleStack1 => + nextAddr <= nextAddrStack; + when cycleStack2 => + nextAddr <= nextAddrStack; + when cycleStack3 => + nextAddr <= nextAddrStack; + if opcInfo(opcStackData) = '0' then + nextAddr <= nextAddrPc; + end if; + when cycleStack4 => + nextAddr <= nextAddrIrq; + when cycleJump => + nextAddr <= nextAddrAbs; + when others => + null; + end case; + if reset = '1' then + nextAddr <= nextAddrReset; + end if; + end process; + +indexAlu: process(opcInfo, myAddr, T, X, Y) + begin + if opcInfo(indexX) = '1' then + indexOut <= (B"0" & T) + (B"0" & X); + elsif opcInfo(indexY) = '1' then + indexOut <= (B"0" & T) + (B"0" & Y); + elsif opcInfo(opcBranch) = '1' then + indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0)); + else + indexOut <= B"0" & T; + end if; + end process; + +calcAddr: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case nextAddr is + when nextAddrIncr => myAddr <= myAddrIncr; + when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0); + when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH; + when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH; + when nextAddrPc => myAddr <= PC; + when nextAddrIrq => + myAddr <= X"FFFE"; + if nmiReg = '0' then + myAddr <= X"FFFA"; + end if; + when nextAddrReset => myAddr <= X"FFFC"; + when nextAddrAbs => myAddr <= di & T; + when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0); + when nextAddrZeroPage => myAddr <= "00000000" & di; + when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0); + when nextAddrStack => myAddr <= "00000001" & S; + when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0); + when others => null; + end case; + end if; + end if; + end process; + + myAddrIncr <= myAddr + 1; + myAddrIncrH <= myAddr(15 downto 8) + 1; + myAddrDecrH <= myAddr(15 downto 8) - 1; + + addr <= myAddr; + + debugA <= A; + debugX <= X; + debugY <= Y; + debugS <= S; + +end architecture; + + diff --git a/Commodore - 64_Mist/rtl/cpu_6510.vhd b/Commodore - 64_Mist/rtl/cpu_6510.vhd new file mode 100644 index 00000000..a1a8d2ba --- /dev/null +++ b/Commodore - 64_Mist/rtl/cpu_6510.vhd @@ -0,0 +1,150 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- 6510 wrapper for 65xx core +-- Adds 8 bit I/O port mapped at addresses $0000 to $0001 +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cpu_6510 is + generic ( + pipelineOpcode : boolean; + pipelineAluMux : boolean; + pipelineAluOut : boolean + ); + port ( + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + nmi_n : in std_logic; + nmi_ack : out std_logic; + irq_n : in std_logic; + + di : in unsigned(7 downto 0); + do : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic; + + diIO : in unsigned(7 downto 0); + doIO : out unsigned(7 downto 0); + + debugOpcode : out unsigned(7 downto 0); + debugPc : out unsigned(15 downto 0); + debugA : out unsigned(7 downto 0); + debugX : out unsigned(7 downto 0); + debugY : out unsigned(7 downto 0); + debugS : out unsigned(7 downto 0) + ); +end cpu_6510; + +-- ----------------------------------------------------------------------- + +architecture rtl of cpu_6510 is + signal localA : unsigned(15 downto 0); + signal localDi : unsigned(7 downto 0); + signal localDo : unsigned(7 downto 0); + signal localWe : std_logic; + + signal currentIO : unsigned(7 downto 0); + signal ioDir : unsigned(7 downto 0); + signal ioData : unsigned(7 downto 0); + + signal accessIO : std_logic; +begin + cpuInstance: entity work.cpu65xx(fast) + generic map ( + pipelineOpcode => pipelineOpcode, + pipelineAluMux => pipelineAluMux, + pipelineAluOut => pipelineAluOut + ) + port map ( + clk => clk, + enable => enable, + reset => reset, + nmi_n => nmi_n, + nmi_ack => nmi_ack, + irq_n => irq_n, + + di => localDi, + do => localDo, + addr => localA, + we => localWe, + + debugOpcode => debugOpcode, + debugPc => debugPc, + debugA => debugA, + debugX => debugX, + debugY => debugY, + debugS => debugS + ); + + process(localA) + begin + accessIO <= '0'; + if localA(15 downto 1) = 0 then + accessIO <= '1'; + end if; + end process; + + process(di, localA, ioDir, currentIO, accessIO) + begin + localDi <= di; + if accessIO = '1' then + if localA(0) = '0' then + localDi <= ioDir; + else + localDi <= currentIO; + end if; + end if; + end process; + + process(clk) + begin + if rising_edge(clk) then + if accessIO = '1' then + if localWe = '1' + and enable = '1' then + if localA(0) = '0' then + ioDir <= localDo; + else + ioData <= localDo; + end if; + end if; + end if; + if reset = '1' then + ioDir <= (others => '0'); + end if; + end if; + end process; + + process(ioDir, ioData, diIO) + begin + for i in 0 to 7 loop + if ioDir(i) = '0' then + currentIO(i) <= diIO(i); + else + currentIO(i) <= ioData(i); + end if; + end loop; + end process; + + -- Cunnect zee wires + addr <= localA; + do <= localDo; + we <= localWe; + doIO <= currentIO; +end architecture; diff --git a/Commodore - 64_Mist/rtl/fpga64_buslogic_roms_mmu.vhd b/Commodore - 64_Mist/rtl/fpga64_buslogic_roms_mmu.vhd new file mode 100644 index 00000000..933c436e --- /dev/null +++ b/Commodore - 64_Mist/rtl/fpga64_buslogic_roms_mmu.vhd @@ -0,0 +1,339 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- + +-- ----------------------------------------------------------------------- +-- Dar 08/03/2014 +-- +-- Based on mixing both fpga64_buslogic_roms and fpga64_buslogic_nommu +-- RAM should be external SRAM +-- Basic, Char and Kernel ROMs are included +-- Original Kernel replaced by JiffyDos +-- ----------------------------------------------------------------------- + +library IEEE; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +entity fpga64_buslogic is + port ( + clk : in std_logic; + reset : in std_logic; + c64gs : in std_logic; + + cpuHasBus : in std_logic; + + ramData: in unsigned(7 downto 0); + + -- 2 CHAREN + -- 1 HIRAM + -- 0 LORAM + bankSwitch: in unsigned(2 downto 0); + + -- From cartridge port + game : in std_logic; + exrom : in std_logic; + ioE_rom : in std_logic; + ioF_rom : in std_logic; + max_ram : in std_logic; + + c64rom_addr: in std_logic_vector(13 downto 0); + c64rom_data: in std_logic_vector(7 downto 0); + c64rom_wr: in std_logic; + + cpuWe: in std_logic; + cpuAddr: in unsigned(15 downto 0); + cpuData: in unsigned(7 downto 0); + vicAddr: in unsigned(15 downto 0); + vicData: in unsigned(7 downto 0); + sidData: in unsigned(7 downto 0); + colorData: in unsigned(3 downto 0); + cia1Data: in unsigned(7 downto 0); + cia2Data: in unsigned(7 downto 0); + lastVicData : in unsigned(7 downto 0); + + systemWe: out std_logic; + systemAddr: out unsigned(15 downto 0); + dataToCpu : out unsigned(7 downto 0); + dataToVic : out unsigned(7 downto 0); + + cs_vic: out std_logic; + cs_sid: out std_logic; + cs_color : out std_logic; + cs_cia1: out std_logic; + cs_cia2: out std_logic; + cs_ram: out std_logic; + + -- To catridge port + cs_ioE: out std_logic; + cs_ioF: out std_logic; + cs_romL : out std_logic; + cs_romH : out std_logic; + cs_UMAXromH : out std_logic + ); +end fpga64_buslogic; + +-- ----------------------------------------------------------------------- + +architecture rtl of fpga64_buslogic is + component fpga64_colorram is + port ( + clk: in std_logic; + cs: in std_logic; + we: in std_logic; + + addr: in unsigned(9 downto 0); + di: in unsigned(3 downto 0); + do: out unsigned(3 downto 0) + ); + end component; + + signal charData: unsigned(7 downto 0); + signal basicData: unsigned(7 downto 0); + signal romData: std_logic_vector(7 downto 0); + signal romData_c64: std_logic_vector(7 downto 0); + signal romData_c64gs: std_logic_vector(7 downto 0); + signal c64gs_ena : std_logic := '0'; + + signal cs_CharReg : std_logic; + signal cs_romReg : std_logic; + signal vicCharReg : std_logic; + + signal cs_ramReg : std_logic; + signal cs_vicReg : std_logic; + signal cs_sidReg : std_logic; + signal cs_colorReg : std_logic; + signal cs_cia1Reg : std_logic; + signal cs_cia2Reg : std_logic; + signal cs_ioEReg : std_logic; + signal cs_ioFReg : std_logic; + signal cs_romLReg : std_logic; + signal cs_romHReg : std_logic; + signal cs_UMAXromHReg : std_logic; + signal ultimax : std_logic; + + signal currentAddr: unsigned(15 downto 0); + +begin + charrom: entity work.rom_c64_chargen + port map ( + clk => clk, + addr => currentAddr(11 downto 0), + do => charData + ); + + kernelrom: entity work.rom_C64 + port map + ( + clock => clk, + + wren => c64rom_wr, + data => c64rom_data, + wraddress => c64rom_addr, + + rdaddress => std_logic_vector(cpuAddr(14) & cpuAddr(12 downto 0)), + q => romData_c64 + ); + +-- kernelromGS: entity work.rom_GS64 +-- port map +-- ( +-- clock => clk, + +-- wren => '0', +-- data => (others => '0'), +-- wraddress => (others => '0'), + +-- rdaddress => std_logic_vector(cpuAddr(14) & cpuAddr(12 downto 0)), +-- q => romData_c64gs +-- ); + + + romData <= romData_c64gs when c64gs_ena = '1' else romData_c64; + process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + c64gs_ena <= c64gs; + end if; + end if; + end process; + + -- + --begin + process(ramData, vicData, sidData, colorData, + cia1Data, cia2Data, charData, romData, + cs_romHReg, cs_romLReg, cs_romReg, cs_CharReg, + cs_ramReg, cs_vicReg, cs_sidReg, cs_colorReg, + cs_cia1Reg, cs_cia2Reg, lastVicData, + cs_ioEReg, cs_ioFReg, ioE_rom, ioF_rom) + begin + -- If no hardware is addressed the bus is floating. + -- It will contain the last data read by the VIC. (if a C64 is shielded correctly) + dataToCpu <= lastVicData; + if cs_CharReg = '1' then + dataToCpu <= charData; + elsif cs_romReg = '1' then + dataToCpu <= unsigned(romData); + elsif cs_ramReg = '1' then + dataToCpu <= ramData; + elsif cs_vicReg = '1' then + dataToCpu <= vicData; + elsif cs_sidReg = '1' then + dataToCpu <= sidData; + elsif cs_colorReg = '1' then + dataToCpu(3 downto 0) <= colorData; + elsif cs_cia1Reg = '1' then + dataToCpu <= cia1Data; + elsif cs_cia2Reg = '1' then + dataToCpu <= cia2Data; + elsif cs_romLReg = '1' then + dataToCpu <= ramData; + elsif cs_romHReg = '1' then + dataToCpu <= ramData; + elsif cs_ioEReg = '1' and ioE_rom = '1' then + dataToCpu <= ramData; + elsif cs_ioFReg = '1' and ioF_rom = '1' then + dataToCpu <= ramData; + end if; + end process; + + ultimax <= exrom and (not game); + + process(clk) + begin + if rising_edge(clk) then + currentAddr <= (others => '1'); -- Prevent generation of a latch when neither vic or cpu is using the bus. + + systemWe <= '0'; + vicCharReg <= '0'; + cs_CharReg <= '0'; + cs_romReg <= '0'; + cs_ramReg <= '0'; + cs_vicReg <= '0'; + cs_sidReg <= '0'; + cs_colorReg <= '0'; + cs_cia1Reg <= '0'; + cs_cia2Reg <= '0'; + cs_ioEReg <= '0'; + cs_ioFReg <= '0'; + cs_romLReg <= '0'; + cs_romHReg <= '0'; + cs_UMAXromHReg <= '0'; -- Ultimax flag for the VIC access - LCA + + if (cpuHasBus = '1') then + -- The 6502 CPU has the bus. + currentAddr <= cpuAddr; + case cpuAddr(15 downto 12) is + when X"E" | X"F" => + if ultimax = '1' and cpuWe = '0' then + -- ULTIMAX MODE - drop out the kernal - LCA + cs_romHReg <= '1'; + elsif cpuWe = '0' and bankSwitch(1) = '1' then + -- Read kernal + cs_romReg <= '1'; + else + -- 64Kbyte RAM layout + cs_ramReg <= '1'; + end if; + when X"D" => + if (ultimax = '0' or max_ram = '1') and bankSwitch(1) = '0' and bankSwitch(0) = '0' then + -- 64Kbyte RAM layout + cs_ramReg <= '1'; + elsif ultimax = '1' or bankSwitch(2) = '1' then + case cpuAddr(11 downto 8) is + when X"0" | X"1" | X"2" | X"3" => + cs_vicReg <= '1'; + when X"4" | X"5" | X"6" | X"7" => + cs_sidReg <= '1'; + when X"8" | X"9" | X"A" | X"B" => + cs_colorReg <= '1'; + when X"C" => + cs_cia1Reg <= '1'; + when X"D" => + cs_cia2Reg <= '1'; + when X"E" => + cs_ioEReg <= '1'; + when X"F" => + cs_ioFReg <= '1'; + when others => + null; + end case; + else + -- I/O space turned off. Read from charrom or write to RAM. + if cpuWe = '0' then + cs_CharReg <= '1'; + else + cs_ramReg <= '1'; + end if; + end if; + when X"A" | X"B" => + if exrom = '0' and game = '0' and cpuWe = '0' and bankSwitch(1) = '1' then + -- Access cartridge with romH + cs_romHReg <= '1'; + elsif ultimax = '0' and cpuWe = '0' and bankSwitch(1) = '1' and bankSwitch(0) = '1' then + -- Access basic rom + -- May need turning off if kernal banked out LCA + cs_romReg <= '1'; + elsif ultimax = '0' or max_ram = '1' then + -- If not in Ultimax mode access ram + cs_ramReg <= '1'; + end if; + when X"8" | X"9" => + if ultimax = '1' then + -- Ultimax access with romL + cs_romLReg <= '1'; + elsif exrom = '0' and bankSwitch(1) = '1' and bankSwitch(0) = '1' then + -- Access cartridge with romL + cs_romLReg <= '1'; + else + cs_ramReg <= '1'; + end if; + when X"0" => + cs_ramReg <= '1'; + when others => + -- If not in Ultimax mode access ram + if ultimax = '0' or max_ram = '1' then + cs_ramReg <= '1'; + end if; + end case; + + systemWe <= cpuWe; + else + -- The VIC-II has the bus. + currentAddr <= vicAddr; + + if ultimax = '0' and vicAddr(14 downto 12)="001" then + vicCharReg <= '1'; + elsif ultimax = '1' and vicAddr(13 downto 12)="11" then + -- ultimax mode changes vic addressing - LCA + cs_UMAXromHReg <= '1'; + else + cs_ramReg <= '1'; + end if; + end if; + end if; + end process; + + cs_ram <= cs_ramReg or cs_romLReg or cs_romHReg or cs_UMAXromHReg; -- need to keep ram active for cartridges LCA + cs_vic <= cs_vicReg; + cs_sid <= cs_sidReg; + cs_color <= cs_colorReg; + cs_cia1 <= cs_cia1Reg; + cs_cia2 <= cs_cia2Reg; + cs_ioE <= cs_ioEReg; + cs_ioF <= cs_ioFReg; + cs_romL <= cs_romLReg; + cs_romH <= cs_romHReg; + cs_UMAXromH <= cs_UMAXromHReg; + + dataToVic <= charData when vicCharReg = '1' else ramData; + systemAddr <= currentAddr; +end architecture; diff --git a/Commodore - 64_Mist/rtl/fpga64_bustiming.vhd b/Commodore - 64_Mist/rtl/fpga64_bustiming.vhd new file mode 100644 index 00000000..715020b6 --- /dev/null +++ b/Commodore - 64_Mist/rtl/fpga64_bustiming.vhd @@ -0,0 +1,74 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Reset circuit +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.all; + +entity fpga64_busTiming is + generic ( + resetCycles: integer := 15; + noofBusCycles : integer := 52 + ); + port ( + clkIn : in std_logic; + rstIn : in std_logic; + rstOut : out std_logic; + endOfCycle : out std_logic; -- Signal is 1 on last count of current cycle. + busCycle : out unsigned(5 downto 0) + ); +end fpga64_busTiming; + +-- ----------------------------------------------------------------------- + +architecture rtl of fpga64_busTiming is +signal clk33 : std_logic; +signal nextCycle : std_logic; +signal resetCycleCounter : integer range 0 to resetCycles := 0; +signal busCycleCounter : unsigned(5 downto 0) := (others => '0'); +begin + clk33 <= clkIn; + + process(clk33) + begin + if rising_edge(clk33) then + if (busCycleCounter = (noofBusCycles - 2) ) then + nextCycle <= '1'; + else + nextCycle <= '0'; + end if; + if nextCycle = '1' then + busCycleCounter <= (others => '0'); + else + busCycleCounter <= busCycleCounter + 1; + end if; + if resetCycleCounter = resetCycles then + rstOut <= '0'; + else + rstOut <= '1'; + if nextCycle = '1' then + resetCycleCounter <= resetCycleCounter + 1; + end if; + end if; + if rstIn = '1' then +-- nextCycle <= '0'; + resetCycleCounter <= 0; + end if; + end if; + end process; + busCycle <= busCycleCounter; + endOfCycle <= nextCycle; +end architecture; diff --git a/Commodore - 64_Mist/rtl/fpga64_keyboard_matrix_mark_mcdougall.vhd b/Commodore - 64_Mist/rtl/fpga64_keyboard_matrix_mark_mcdougall.vhd new file mode 100644 index 00000000..ae1ebc0a --- /dev/null +++ b/Commodore - 64_Mist/rtl/fpga64_keyboard_matrix_mark_mcdougall.vhd @@ -0,0 +1,475 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- 'Joystick emulation on keypad' additions by +-- Mark McDougall (msmcdoug@iinet.net.au) +-- ----------------------------------------------------------------------- +-- +-- VIC20/C64 Keyboard matrix +-- +-- Hardware huh? +-- In original machine if a key is pressed a contact is made. +-- Bidirectional reading is possible on real hardware, which is difficult +-- to emulate. (set backwardsReadingEnabled to '1' if you want this enabled). +-- Then we have the joysticks, one of which is normally connected +-- to a OUTPUT pin. +-- +-- Emulation: +-- All pins are high except when one is driven low and there is a +-- connection. This is consistent with joysticks that force a line +-- low too. CIA will put '1's when set to input to help this emulation. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.ALL; + +entity fpga64_keyboard_matrix is + port ( + clk: in std_logic; + theScanCode: in unsigned(7 downto 0); + newScanCode: in std_logic; + + joyA: in unsigned(4 downto 0); + joyB: in unsigned(4 downto 0); + + pai: in unsigned(7 downto 0); + pbi: in unsigned(7 downto 0); + pao: out unsigned(7 downto 0); + pbo: out unsigned(7 downto 0); + + reset_key : out std_logic; + restore_key : out std_logic; + videoKey : out std_logic; + traceKey : out std_logic; + trace2Key : out std_logic; + disk_num : out std_logic_vector(7 downto 0); + + cart_detach_key : out std_logic; -- CTRL D - remove active cartridge signal - LCA + + -- Config + -- backwardsReadingEnabled = 1 allows reversal of PIA registers to still work. + -- not needed for kernel/normal operation only for some specific programs. + -- set to 0 to save some hardware. + backwardsReadingEnabled : in std_logic + ); +end fpga64_keyboard_matrix; + +architecture rtl of fpga64_keyboard_matrix is + signal extendedFlag: std_logic := '0'; + signal releaseFlag: std_logic := '0'; + + signal key_del: std_logic := '0'; + signal key_return: std_logic := '0'; + signal key_left: std_logic := '0'; + signal key_right: std_logic := '0'; + signal key_f7: std_logic := '0'; + signal key_f1: std_logic := '0'; + signal key_f3: std_logic := '0'; + signal key_f5: std_logic := '0'; + signal key_up: std_logic := '0'; + signal key_down: std_logic := '0'; + + signal key_3: std_logic := '0'; + signal key_W: std_logic := '0'; + signal key_A: std_logic := '0'; + signal key_4: std_logic := '0'; + signal key_Z: std_logic := '0'; + signal key_S: std_logic := '0'; + signal key_E: std_logic := '0'; + signal key_shiftl: std_logic := '0'; + + signal key_5: std_logic := '0'; + signal key_R: std_logic := '0'; + signal key_D: std_logic := '0'; + signal key_6: std_logic := '0'; + signal key_C: std_logic := '0'; + signal key_F: std_logic := '0'; + signal key_T: std_logic := '0'; + signal key_X: std_logic := '0'; + + signal key_7: std_logic := '0'; + signal key_Y: std_logic := '0'; + signal key_G: std_logic := '0'; + signal key_8: std_logic := '0'; + signal key_B: std_logic := '0'; + signal key_H: std_logic := '0'; + signal key_U: std_logic := '0'; + signal key_V: std_logic := '0'; + + signal key_9: std_logic := '0'; + signal key_I: std_logic := '0'; + signal key_J: std_logic := '0'; + signal key_0: std_logic := '0'; + signal key_M: std_logic := '0'; + signal key_K: std_logic := '0'; + signal key_O: std_logic := '0'; + signal key_N: std_logic := '0'; + + signal key_plus: std_logic := '0'; + signal key_P: std_logic := '0'; + signal key_L: std_logic := '0'; + signal key_minus: std_logic := '0'; + signal key_dot: std_logic := '0'; + signal key_colon: std_logic := '0'; + signal key_at: std_logic := '0'; + signal key_comma: std_logic := '0'; + + signal key_pound: std_logic := '0'; + signal key_star: std_logic := '0'; + signal key_semicolon: std_logic := '0'; + signal key_home: std_logic := '0'; + signal key_shiftr: std_logic := '0'; + signal key_equal: std_logic := '0'; + signal key_arrowup: std_logic := '0'; + signal key_slash: std_logic := '0'; + + signal key_1: std_logic := '0'; + signal key_arrowleft: std_logic := '0'; + signal key_ctrl: std_logic := '0'; + signal key_2: std_logic := '0'; + signal key_space: std_logic := '0'; + signal key_commodore: std_logic := '0'; + signal key_Q: std_logic := '0'; + signal key_runstop: std_logic := '0'; + + -- for joystick emulation on PS2 + signal joySelKey : std_logic; + signal joyKeys : std_logic_vector(joyA'range); -- active high + signal joyA_s : unsigned(joyA'range); -- active low + signal joyB_s : unsigned(joyB'range); -- active low + signal joySel : std_logic_vector(1 downto 0) := "00"; + + -- for disk image selection + signal diskChgKey : std_logic; + signal disk_nb : std_logic_vector(7 downto 0); + +begin + + process (clk) + begin + if rising_edge(clk) then + if diskChgKey = '1' then + if key_shiftl = '1' then + disk_nb <= disk_nb - 1; + else + disk_nb <= disk_nb + 1; + end if; + end if; + end if; + end process; + + disk_num <= disk_nb; + -- + -- cycle though joystick emulation options on + -- + -- "00" - PORTA = JOYA or JOYKEYS, PORTB = JOYB + -- "01" - PORTA = JOYA, PORTB = JOYB or JOYKEYS + -- "10" - PORTA = JOYA, PORTB = JOYKEYS + -- "11" - PORTA = JOYKEYS, PORTB = JOYA + + process (clk) --, reset) + begin + if rising_edge(clk) then + if joySelKey = '1' then + joySel <= joySel + 1; + end if; + end if; + end process; + + joyA_s <= joyA and not unsigned(joyKeys) when joySel = "00" else + not unsigned(joyKeys) when joySel = "11" else + joyA; + joyB_s <= joyB when joySel = "00" else + joyB and not unsigned(joyKeys) when joySel = "01" else + not unsigned(joyKeys) when joySel = "10" else + joyA; + + matrix: process(clk) + begin + --if reset = '1' then + -- joySelKey <= '0'; + -- joyKeys <= (others => '0'); + if rising_edge(clk) then + -- reading A, scan pattern on B + pao(0) <= pai(0) and joyA_s(0) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_del) and + (pbi(1) or not key_return) and + (pbi(2) or not (key_left or key_right)) and + (pbi(3) or not key_f7) and + (pbi(4) or not key_f1) and + (pbi(5) or not key_f3) and + (pbi(6) or not key_f5) and + (pbi(7) or not (key_up or key_down)))); + pao(1) <= pai(1) and joyA_s(1) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_3) and + (pbi(1) or not key_W) and + (pbi(2) or not key_A) and + (pbi(3) or not key_4) and + (pbi(4) or not key_Z) and + (pbi(5) or not key_S) and + (pbi(6) or not key_E) and + (pbi(7) or not (key_left or key_up or key_shiftL)))); + pao(2) <= pai(2) and joyA_s(2) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_5) and + (pbi(1) or not key_R) and + (pbi(2) or not key_D) and + (pbi(3) or not key_6) and + (pbi(4) or not key_C) and + (pbi(5) or not key_F) and + (pbi(6) or not key_T) and + (pbi(7) or not key_X))); + pao(3) <= pai(3) and joyA_s(3) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_7) and + (pbi(1) or not key_Y) and + (pbi(2) or not key_G) and + (pbi(3) or not key_8) and + (pbi(4) or not key_B) and + (pbi(5) or not key_H) and + (pbi(6) or not key_U) and + (pbi(7) or not key_V))); + pao(4) <= pai(4) and joyA_s(4) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_9) and + (pbi(1) or not key_I) and + (pbi(2) or not key_J) and + (pbi(3) or not key_0) and + (pbi(4) or not key_M) and + (pbi(5) or not key_K) and + (pbi(6) or not key_O) and + (pbi(7) or not key_N))); + pao(5) <= pai(5) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_plus) and + (pbi(1) or not key_P) and + (pbi(2) or not key_L) and + (pbi(3) or not key_minus) and + (pbi(4) or not key_dot) and + (pbi(5) or not key_colon) and + (pbi(6) or not key_at) and + (pbi(7) or not key_comma))); + pao(6) <= pai(6) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_pound) and + (pbi(1) or not key_star) and + (pbi(2) or not key_semicolon) and + (pbi(3) or not key_home) and + (pbi(4) or not key_shiftr) and + (pbi(5) or not key_equal) and + (pbi(6) or not key_arrowup) and + (pbi(7) or not key_slash))); + pao(7) <= pai(7) and + ((not backwardsReadingEnabled) or + ((pbi(0) or not key_1) and + (pbi(1) or not key_arrowleft) and + (pbi(2) or not key_ctrl) and + (pbi(3) or not key_2) and + (pbi(4) or not key_space) and + (pbi(5) or not key_commodore) and + (pbi(6) or not key_Q) and + (pbi(7) or not key_runstop))); + + -- reading B, scan pattern on A + pbo(0) <= pbi(0) and joyB_s(0) and + (pai(0) or not key_del) and + (pai(1) or not key_3) and + (pai(2) or not key_5) and + (pai(3) or not key_7) and + (pai(4) or not key_9) and + (pai(5) or not key_plus) and + (pai(6) or not key_pound) and + (pai(7) or not key_1); + pbo(1) <= pbi(1) and joyB_s(1) and + (pai(0) or not key_return) and + (pai(1) or not key_W) and + (pai(2) or not key_R) and + (pai(3) or not key_Y) and + (pai(4) or not key_I) and + (pai(5) or not key_P) and + (pai(6) or not key_star) and + (pai(7) or not key_arrowleft); + pbo(2) <= pbi(2) and joyB_s(2) and + (pai(0) or not (key_left or key_right)) and + (pai(1) or not key_A) and + (pai(2) or not key_D) and + (pai(3) or not key_G) and + (pai(4) or not key_J) and + (pai(5) or not key_L) and + (pai(6) or not key_semicolon) and + (pai(7) or not key_ctrl); + pbo(3) <= pbi(3) and joyB_s(3) and + (pai(0) or not key_F7) and + (pai(1) or not key_4) and + (pai(2) or not key_6) and + (pai(3) or not key_8) and + (pai(4) or not key_0) and + (pai(5) or not key_minus) and + (pai(6) or not key_home) and + (pai(7) or not key_2); + pbo(4) <= pbi(4) and joyB_s(4) and + (pai(0) or not key_F1) and + (pai(1) or not key_Z) and + (pai(2) or not key_C) and + (pai(3) or not key_B) and + (pai(4) or not key_M) and + (pai(5) or not key_dot) and + (pai(6) or not key_shiftr) and + (pai(7) or not key_space); + pbo(5) <= pbi(5) and + (pai(0) or not key_F3) and + (pai(1) or not key_S) and + (pai(2) or not key_F) and + (pai(3) or not key_H) and + (pai(4) or not key_K) and + (pai(5) or not key_colon) and + (pai(6) or not key_equal) and + (pai(7) or not key_commodore); + pbo(6) <= pbi(6) and + (pai(0) or not key_F5) and + (pai(1) or not key_E) and + (pai(2) or not key_T) and + (pai(3) or not key_U) and + (pai(4) or not key_O) and + (pai(5) or not key_at) and + (pai(6) or not key_arrowup) and + (pai(7) or not key_Q); + pbo(7) <= pbi(7) and + (pai(0) or not (key_up or key_down)) and + (pai(1) or not (key_left or key_up or key_shiftL)) and + (pai(2) or not key_X) and + (pai(3) or not key_V) and + (pai(4) or not key_N) and + (pai(5) or not key_comma) and + (pai(6) or not key_slash) and + (pai(7) or not key_runstop); + + traceKey <= '0'; + trace2Key <= '0'; + videoKey <= '0'; + joySelKey <= '0'; + diskChgKey <= '0'; + cart_detach_key <= '0'; + if newScanCode = '1' then + if theScanCode=X"F0" then + releaseFlag <= '1'; + elsif theScanCode=X"E0" then + extendedFlag <= '1'; + else + releaseFlag <= '0'; + extendedFlag <= '0'; + case theScanCode is + when X"01" => key_pound <= not releaseFlag; + when X"03" => key_F5 <= not releaseFlag; + when X"04" => key_F3 <= not releaseFlag; + when X"05" => key_F1 <= not releaseFlag; + when X"06" => -- F2 + if releaseFlag = '0' then + traceKey <= '1'; + end if; + when X"09" => key_plus <= not releaseFlag; + when X"0A" => -- F8 + if releaseFlag = '0' then + diskChgKey <= '1'; + end if; + when X"0B" => -- F6 + if releaseFlag = '0' then + trace2Key <= '1'; + end if; + when X"0C" => restore_key <= not releaseFlag; -- F4 + when X"83" => key_F7 <= not releaseFlag; + when X"0E" => key_arrowleft <= not releaseFlag; + when X"11" => key_commodore <= not releaseFlag; + when X"12" => if extendedFlag = '0' then key_shiftl <= not releaseFlag; end if; + when X"14" => key_ctrl <= not releaseFlag; + when X"15" => key_Q <= not releaseFlag; + when X"16" => key_1 <= not releaseFlag; + when X"1A" => key_Z <= not releaseFlag; + when X"1B" => key_S <= not releaseFlag; + when X"1C" => key_A <= not releaseFlag; + when X"1D" => key_W <= not releaseFlag; + when X"1E" => key_2 <= not releaseFlag; + when X"21" => key_C <= not releaseFlag; + when X"22" => key_X <= not releaseFlag; + when X"23" => -- key_D - if CTRL-D the detach cartridge else its a "D" - LCA + if key_ctrl = '1' then + cart_detach_key <= '1'; + else +-- if releaseFlag = '0' then + key_D <= not releaseFlag; +-- end if; + end if; + when X"24" => key_E <= not releaseFlag; + when X"25" => key_4 <= not releaseFlag; + when X"26" => key_3 <= not releaseFlag; + when X"29" => key_space <= not releaseFlag; + when X"2A" => key_V <= not releaseFlag; + when X"2B" => key_F <= not releaseFlag; + when X"2C" => key_T <= not releaseFlag; + when X"2D" => key_R <= not releaseFlag; + when X"2E" => key_5 <= not releaseFlag; + when X"31" => key_N <= not releaseFlag; + when X"32" => key_B <= not releaseFlag; + when X"33" => key_H <= not releaseFlag; + when X"34" => key_G <= not releaseFlag; + when X"35" => key_Y <= not releaseFlag; + when X"36" => key_6 <= not releaseFlag; + when X"3A" => key_M <= not releaseFlag; + when X"3B" => key_J <= not releaseFlag; + when X"3C" => key_U <= not releaseFlag; + when X"3D" => key_7 <= not releaseFlag; + when X"3E" => key_8 <= not releaseFlag; + when X"41" => key_comma <= not releaseFlag; + when X"42" => key_K <= not releaseFlag; + when X"43" => key_I <= not releaseFlag; + when X"44" => key_O <= not releaseFlag; + when X"45" => key_0 <= not releaseFlag; + when X"46" => key_9 <= not releaseFlag; + when X"49" => key_dot <= not releaseFlag; + when X"4A" => key_slash <= not releaseFlag; + when X"4B" => key_L <= not releaseFlag; + when X"4C" => key_colon <= not releaseFlag; + when X"4D" => key_P <= not releaseFlag; + when X"4E" => key_minus <= not releaseFlag; + when X"52" => key_semicolon <= not releaseFlag; + when X"54" => key_at <= not releaseFlag; + when X"55" => key_equal <= not releaseFlag; + when X"59" => if extendedFlag = '0' then key_shiftr <= not releaseFlag; end if; + when X"5A" => key_Return <= not releaseFlag; + when X"5B" => key_star <= not releaseFlag; + when X"5D" => key_arrowup <= not releaseFlag; + when X"6B" => if extendedFlag = '0' then joyKeys(2) <= not releaseFlag; else key_left <= not releaseFlag; end if; + when X"6C" => key_home <= not releaseFlag; + when X"66" => key_del <= not releaseFlag; + when X"70" => if extendedFlag = '0' then joyKeys(4) <= not releaseFlag; end if; + when X"72" => if extendedFlag = '0' then joyKeys(1) <= not releaseFlag; else key_down <= not releaseFlag; end if; + when X"74" => if extendedFlag = '0' then joyKeys(3) <= not releaseFlag; else key_right <= not releaseFlag; end if; + when X"75" => if extendedFlag = '0' then joyKeys(0) <= not releaseFlag; else key_up <= not releaseFlag; end if; + when X"76" => key_runstop <= not releaseFlag; + when X"78" => -- F11 + if key_ctrl = '1' then + reset_key <= not releaseFlag; + else + if releaseFlag = '0' then + joySelKey <= '1'; + end if; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; +end architecture; diff --git a/Commodore - 64_Mist/rtl/fpga64_rgbcolor.vhd b/Commodore - 64_Mist/rtl/fpga64_rgbcolor.vhd new file mode 100644 index 00000000..1fc4eb9a --- /dev/null +++ b/Commodore - 64_Mist/rtl/fpga64_rgbcolor.vhd @@ -0,0 +1,56 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- C64 palette index to 24 bit RGB color +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +-- ----------------------------------------------------------------------- + +entity fpga64_rgbcolor is + port ( + index: in unsigned(3 downto 0); + r: out unsigned(7 downto 0); + g: out unsigned(7 downto 0); + b: out unsigned(7 downto 0) + ); +end fpga64_rgbcolor; + +-- ----------------------------------------------------------------------- + +architecture Behavioral of fpga64_rgbcolor is +begin + process(index) + begin + case index is + when X"0" => r <= X"00"; g <= X"00"; b <= X"00"; + when X"1" => r <= X"FF"; g <= X"FF"; b <= X"FF"; + when X"2" => r <= X"68"; g <= X"37"; b <= X"2B"; + when X"3" => r <= X"70"; g <= X"A4"; b <= X"B2"; + when X"4" => r <= X"6F"; g <= X"3D"; b <= X"86"; + when X"5" => r <= X"58"; g <= X"8D"; b <= X"43"; + when X"6" => r <= X"35"; g <= X"28"; b <= X"79"; + when X"7" => r <= X"B8"; g <= X"C7"; b <= X"6F"; + when X"8" => r <= X"6F"; g <= X"4F"; b <= X"25"; + when X"9" => r <= X"43"; g <= X"39"; b <= X"00"; + when X"A" => r <= X"9A"; g <= X"67"; b <= X"59"; + when X"B" => r <= X"44"; g <= X"44"; b <= X"44"; + when X"C" => r <= X"6C"; g <= X"6C"; b <= X"6C"; + when X"D" => r <= X"9A"; g <= X"D2"; b <= X"84"; + when X"E" => r <= X"6C"; g <= X"5E"; b <= X"B5"; + when X"F" => r <= X"95"; g <= X"95"; b <= X"95"; + end case; + end process; +end Behavioral; diff --git a/Commodore - 64_Mist/rtl/fpga64_sid_iec.vhd b/Commodore - 64_Mist/rtl/fpga64_sid_iec.vhd new file mode 100644 index 00000000..29787b61 --- /dev/null +++ b/Commodore - 64_Mist/rtl/fpga64_sid_iec.vhd @@ -0,0 +1,824 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- System runs on 32 Mhz (derived from a 50MHz clock). +-- The VIC-II runs in the first 4 cycles of 32 Mhz clock. +-- The CPU runs in the last 16 cycles. Effective cpu speed is 1 Mhz. +-- 4 additional cycles are used to interface with the C-One IEC port. +-- +-- ----------------------------------------------------------------------- +-- Dar 08/03/2014 +-- +-- Based on fpga64_cone +-- add external selection for 15KHz(TV)/31KHz(VGA) +-- add external selection for power on NTSC(60Hz)/PAL(50Hz) +-- add external conection in/out for IEC signal +-- add sid entity +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.all; + +-- ----------------------------------------------------------------------- + +entity fpga64_sid_iec is + generic ( + resetCycles : integer := 4095 + ); + port( + clk32 : in std_logic; + reset_n : in std_logic; + c64gs : in std_logic; + -- keyboard interface (use any ordinairy PS2 keyboard) + kbd_clk : in std_logic; + kbd_dat : in std_logic; + reset_key : out std_logic; + cart_detach_key : out std_logic; + + -- external memory + ramAddr : out unsigned(15 downto 0); + ramDataIn : in unsigned(7 downto 0); + ramDataOut : out unsigned(7 downto 0); + + ramCE : out std_logic; + ramWe : out std_logic; + + idle : out std_logic; + + -- VGA/SCART interface + ntscInitMode: in std_logic; + hsync : out std_logic; + vsync : out std_logic; + r : out unsigned(7 downto 0); + g : out unsigned(7 downto 0); + b : out unsigned(7 downto 0); + + -- cartridge port + game : in std_logic; + exrom : in std_logic; + ioE_rom : in std_logic; + ioF_rom : in std_logic; + max_ram : in std_logic; + irq_n : inout std_logic; + nmi_n : in std_logic; + nmi_ack : out std_logic; + dma_n : in std_logic; + ba : out std_logic; + romL : out std_logic; -- cart signals LCA + romH : out std_logic; -- cart signals LCA + UMAXromH : out std_logic; -- cart signals LCA + IOE : out std_logic; -- cart signals LCA + IOF : out std_logic; -- cart signals LCA + CPU_hasbus : out std_logic; -- CPU has the bus STROBE + freeze_key : out std_logic; + + -- joystick interface + joyA : in unsigned(6 downto 0); + joyB : in unsigned(6 downto 0); + + -- serial port, for connection to pheripherals + serioclk : out std_logic; + ces : out std_logic_vector(3 downto 0); + + --Connector to the SID + SIDclk : out std_logic; + still : out unsigned(15 downto 0); + audio_data : out std_logic_vector(17 downto 0); + extfilter_en: in std_logic; + + -- IEC + iec_data_o : out std_logic; + iec_data_i : in std_logic; + iec_clk_o : out std_logic; + iec_clk_i : in std_logic; + iec_atn_o : out std_logic; + iec_atn_i : in std_logic; + + disk_num : out std_logic_vector(7 downto 0); + + c64rom_addr : in std_logic_vector(13 downto 0); + c64rom_data : in std_logic_vector(7 downto 0); + c64rom_wr : in std_logic +); +end fpga64_sid_iec; + +-- ----------------------------------------------------------------------- + +architecture rtl of fpga64_sid_iec is + -- System state machine + type sysCycleDef is ( + CYCLE_IDLE0, CYCLE_IDLE1, CYCLE_IDLE2, CYCLE_IDLE3, + CYCLE_IDLE4, CYCLE_IDLE5, CYCLE_IDLE6, CYCLE_IDLE7, + CYCLE_IDLE8, + CYCLE_IEC0, CYCLE_IEC1, CYCLE_IEC2, CYCLE_IEC3, + CYCLE_VIC0, CYCLE_VIC1, CYCLE_VIC2, CYCLE_VIC3, + CYCLE_CPU0, CYCLE_CPU1, CYCLE_CPU2, CYCLE_CPU3, + CYCLE_CPU4, CYCLE_CPU5, CYCLE_CPU6, CYCLE_CPU7, + CYCLE_CPUP, CYCLE_CPUQ, + CYCLE_CPU8, CYCLE_CPU9, CYCLE_CPUA, CYCLE_CPUB, + CYCLE_CPUC, CYCLE_CPUD, CYCLE_CPUE, CYCLE_CPUF + ); + + signal sysCycle : sysCycleDef := sysCycleDef'low; + signal sysCycleCnt : unsigned(2 downto 0); + signal phi0_cpu : std_logic; + signal phi0_vic : std_logic; + signal cpuHasBus : std_logic; + + signal cycleRestart : std_logic; + signal cycleRestartReg1 : std_logic; + signal cycleRestartReg2 : std_logic; + signal cycleRestartEdge : std_logic; + + signal baLoc: std_logic; + signal irqLoc: std_logic; + signal nmiLoc: std_logic; + + signal enableCpu: std_logic; + signal enableVic : std_logic; + signal enablePixel : std_logic; + + signal irq_cia1: std_logic; + signal irq_cia2: std_logic; + signal irq_vic: std_logic; + + signal systemWe: std_logic; + signal pulseWrRam: std_logic; + signal pulseWrIo: std_logic; + signal pulseRd: std_logic; + signal colorWe : std_logic; + signal systemAddr: unsigned(15 downto 0); + signal ramDataReg : unsigned(7 downto 0); + + signal cs_vic: std_logic; + signal cs_sid: std_logic; + signal cs_color: std_logic; + signal cs_cia1: std_logic; + signal cs_cia2: std_logic; + signal cs_ram: std_logic; + signal cs_ioE: std_logic; + signal cs_ioF: std_logic; + signal cs_romL: std_logic; + signal cs_romH: std_logic; + signal cs_UMAXromH: std_logic; -- romH VIC II read flag + + signal reset: std_logic := '1'; + signal reset_cnt: integer range 0 to resetCycles := 0; + + signal bankSwitch: unsigned(2 downto 0); + + -- SID signals + signal sid_do : std_logic_vector(7 downto 0); + + -- CIA signals + signal enableCia : std_logic; + signal cia1Do: unsigned(7 downto 0); + signal cia2Do: unsigned(7 downto 0); + +-- keyboard + signal newScanCode: std_logic; + signal theScanCode: unsigned(7 downto 0); + + -- I/O + signal cia1_pai: unsigned(7 downto 0); + signal cia1_pao: unsigned(7 downto 0); + signal cia1_pad: unsigned(7 downto 0); + signal cia1_pbi: unsigned(7 downto 0); + signal cia1_pbo: unsigned(7 downto 0); + signal cia1_pbd: unsigned(7 downto 0); + signal cia2_pai: unsigned(7 downto 0); + signal cia2_pao: unsigned(7 downto 0); + signal cia2_pad: unsigned(7 downto 0); + signal cia2_pbi: unsigned(7 downto 0); + signal cia2_pbo: unsigned(7 downto 0); + signal cia2_pbd: unsigned(7 downto 0); + + signal debugWE: std_logic := '0'; + signal debugData: unsigned(7 downto 0) := (others => '0'); + signal debugAddr: integer range 2047 downto 0 := 0; + + signal cpuWe: std_logic; + signal cpuAddr: unsigned(15 downto 0); + signal cpuDi: unsigned(7 downto 0); + signal cpuDo: unsigned(7 downto 0); + signal cpuIO: unsigned(7 downto 0); + + signal vicDi: unsigned(7 downto 0); + signal vicAddr: unsigned(15 downto 0); + signal vicData: unsigned(7 downto 0); + signal lastVicDi : unsigned(7 downto 0); + + signal colorQ : unsigned(3 downto 0); + signal colorData : unsigned(3 downto 0); + + signal cpuStep : std_logic; + signal traceKey : std_logic; + signal trace2Key : std_logic; + + -- video + signal vicColorIndex : unsigned(3 downto 0); + signal vicHSync : std_logic; + signal vicVSync : std_logic; + + signal vgaColorIndex : unsigned(3 downto 0); + alias vgaColorIndex_int : std_logic_vector is std_logic_vector(vgaColorIndex); + signal vgaR : unsigned(7 downto 0); + signal vgaG : unsigned(7 downto 0); + signal vgaB : unsigned(7 downto 0); + signal vgaVSync : std_logic; + signal vgaHSync : std_logic; + signal debuggerOn : std_logic; + signal traceStep : std_logic; + signal scanline : std_logic; + + -- config + signal videoKey : std_logic; + signal ntscMode : std_logic; + signal ntscModeInvert : std_logic := '0' ; + signal restore_key : std_logic; + + signal clk_1MHz : std_logic_vector(31 downto 0); + signal voice_volume : signed(17 downto 0); +begin +-- ----------------------------------------------------------------------- +-- Local signal to outside world +-- ----------------------------------------------------------------------- + ba <= baLoc; + + idle <= '1' when + (sysCycle = CYCLE_IDLE0) or (sysCycle = CYCLE_IDLE1) or + (sysCycle = CYCLE_IDLE2) or (sysCycle = CYCLE_IDLE3) or + (sysCycle = CYCLE_IDLE4) or (sysCycle = CYCLE_IDLE5) or + (sysCycle = CYCLE_IDLE6) or (sysCycle = CYCLE_IDLE7) or + (sysCycle = CYCLE_IDLE8) else '0'; + +-- ----------------------------------------------------------------------- +-- System state machine, controls bus accesses +-- and triggers enables of other components +-- ----------------------------------------------------------------------- + process(clk32) + begin + if rising_edge(clk32) then + if sysCycle = sysCycleDef'high then + sysCycle <= sysCycleDef'low; + elsif sysCycle = CYCLE_CPU6 then + sysCycle <= CYCLE_CPU8; + else + sysCycle <= sysCycleDef'succ(sysCycle); + end if; + end if; + end process; + + iecClock: process(clk32) + begin + if rising_edge(clk32) then + serioclk <= '1'; + if sysCycle = CYCLE_IEC0 + or sysCycle = CYCLE_IEC1 then + serioclk <= '0'; --for iec write + end if; + end if; + end process; + + sidClock: process(clk32) + begin + if rising_edge(clk32) then + -- Toggle SIDclk early to compensate for the delay caused by the gbridge + if sysCycle = CYCLE_VIC3 then + SIDclk <= '1'; + end if; + if sysCycle = CYCLE_CPUD then + SIDclk <= '0'; + end if; + end if; + end process; + + -- PHI0/2-clock emulation + process(clk32) + begin + if rising_edge(clk32) then + if sysCycle = sysCycleDef'pred(CYCLE_CPU0) then + phi0_cpu <= '1'; + if baLoc = '1' or cpuWe = '1' then + cpuHasBus <= '1'; + end if; + end if; + if sysCycle = sysCycleDef'high then + phi0_cpu <= '0'; + cpuHasBus <= '0'; + end if; + if sysCycle = sysCycleDef'pred(CYCLE_VIC0) then + phi0_vic <= '1'; + end if; + if sysCycle = CYCLE_VIC3 then + phi0_vic <= '0'; + end if; + end if; + end process; + + process(clk32) + begin + if rising_edge(clk32) then + enableVic <= '0'; + enableCia <= '0'; + enableCpu <= '0'; + + case sysCycle is + when CYCLE_VIC2 => + enableVic <= '1'; + when CYCLE_CPUE => + enableCia <= '1'; + enableVic <= '1'; + if baLoc = '1' + or cpuWe = '1' then + enableCpu <= '1'; + end if; + when others => + null; + end case; + end if; + end process; + + hSync <= vicHSync; + vSync <= vicVSync; + + c64colors: entity work.fpga64_rgbcolor + port map ( + index => vicColorIndex, + r => r, + g => g, + b => b + ); +-- ----------------------------------------------------------------------- +-- Color RAM +-- ----------------------------------------------------------------------- + colorram: entity work.gen_ram + generic map ( + dWidth => 4, + aWidth => 10 + ) + port map ( + clk => clk32, + we => colorWe, + addr => systemAddr(9 downto 0), + d => cpuDo(3 downto 0), + q => colorQ + ); + + process(clk32) + begin + if rising_edge(clk32) then + colorWe <= (cs_color and pulseWrRam); + colorData <= colorQ; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- PLA and bus-switches +-- ----------------------------------------------------------------------- + buslogic: entity work.fpga64_buslogic + port map ( + clk => clk32, + reset => reset, + c64gs => c64gs, + cpuHasBus => cpuHasBus, + + bankSwitch => cpuIO(2 downto 0), + + game => game, + exrom => exrom, + ioE_rom => ioE_rom, + ioF_rom => ioF_rom, + max_ram => max_ram, + + ramData => ramDataReg, + + cpuWe => cpuWe, + cpuAddr => cpuAddr, + cpuData => cpuDo, + vicAddr => vicAddr, + vicData => vicData, + sidData => unsigned(sid_do), + colorData => colorData, + cia1Data => cia1Do, + cia2Data => cia2Do, + lastVicData => lastVicDi, + + systemWe => systemWe, + systemAddr => systemAddr, + dataToCpu => cpuDi, + dataToVic => vicDi, + + cs_vic => cs_vic, + cs_sid => cs_sid, + cs_color => cs_color, + cs_cia1 => cs_cia1, + cs_cia2 => cs_cia2, + cs_ram => cs_ram, + cs_ioE => cs_ioE, + cs_ioF => cs_ioF, + cs_romL => cs_romL, + cs_romH => cs_romH, + cs_UMAXromH => cs_UMAXromH, + + c64rom_addr => c64rom_addr, + c64rom_data => c64rom_data, + c64rom_wr => c64rom_wr + ); + + process(clk32) + begin + if rising_edge(clk32) then + pulseWrRam <= '0'; + pulseWrIo <= '0'; + pulseRd <= '0'; + if cpuWe = '1' then + if sysCycle = CYCLE_CPUC then + pulseWrRam <= '1'; + end if; + if sysCycle = CYCLE_CPUC then + pulseWrIo <= '1'; + end if; + else + if sysCycle = CYCLE_CPUE then + pulseRd <= '1'; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- VIC-II video interface chip +-- ----------------------------------------------------------------------- + vic: entity work.video_vicii_656x + generic map ( + registeredAddress => false, + emulateRefresh => false, + emulateLightpen => true, + emulateGraphics => true + ) + port map ( + clk => clk32, + reset => reset, + enaPixel => enablePixel, + enaData => enableVic, + phi => phi0_cpu, + + baSync => '0', + ba => baLoc, + + mode6569 => (not ntscMode), + mode6567old => '0', + mode6567R8 => ntscMode, + mode6572 => '0', + + cs => cs_vic, + we => pulseWrIo, + rd => pulseRd, + lp_n => cia1_pbi(4), + + aRegisters => cpuAddr(5 downto 0), + diRegisters => cpuDo, + di => vicDi, + diColor => colorData, + do => vicData, + + vicAddr => vicAddr(13 downto 0), + + hsync => vicHSync, + vsync => vicVSync, + colorIndex => vicColorIndex, + + irq_n => irq_vic + ); + + -- Pixel timing + process(clk32) + begin + if rising_edge(clk32) then + enablePixel <= '0'; + if sysCycle = CYCLE_VIC2 + or sysCycle = CYCLE_IDLE3 -- IDLE2 + or sysCycle = CYCLE_IDLE7 -- IDLE6 + or sysCycle = CYCLE_IEC2 + or sysCycle = CYCLE_CPU2 + or sysCycle = CYCLE_CPU6 + or sysCycle = CYCLE_CPUB -- CPUA + or sysCycle = CYCLE_CPUF then -- CPUE + enablePixel <= '1'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- SID +-- ----------------------------------------------------------------------- + div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID) + begin + if (rising_edge(clk32)) then + if (reset = '1') then + clk_1MHz <= "00000000000000000000000000000001"; + else + clk_1MHz(31 downto 1) <= clk_1MHz(30 downto 0); + clk_1MHz(0) <= clk_1MHz(31); + end if; + end if; + end process; + + audio_data <= std_logic_vector(voice_volume); + + sid: entity work.sid_top + port map ( + clock => clk32, + reset => reset, + + addr => "000" & cpuAddr(4 downto 0), + wren => pulseWrRam and phi0_cpu and cs_sid, + wdata => std_logic_vector(cpuDo), + rdata => sid_do, + + potx => not std_logic((cia1_pao(7) and JoyA(5)) or (cia1_pao(6) and JoyB(5))), + poty => not std_logic((cia1_pao(7) and JoyA(6)) or (cia1_pao(6) and JoyB(6))), + comb_wave_l => '0', + comb_wave_r => '0', + + extfilter_en => extfilter_en, + + start_iter => clk_1MHz(31), + sample_left => voice_volume, + sample_right => open + ); + +-- ----------------------------------------------------------------------- +-- CIAs +-- ----------------------------------------------------------------------- + cia1: entity work.cia6526 + port map ( + clk => clk32, + todClk => vicVSync, + reset => reset, + enable => enableCia, + cs => cs_cia1, + we => pulseWrIo, + rd => pulseRd, + + addr => cpuAddr(3 downto 0), + di => cpuDo, + do => cia1Do, + + ppai => cia1_pai, + ppao => cia1_pao, + ppbi => cia1_pbi, + ppbo => cia1_pbo, + + flag_n => '1', + + irq_n => irq_cia1 + ); + + cia2: entity work.cia6526 + port map ( + clk => clk32, + todClk => vicVSync, + reset => reset, + enable => enableCia, + cs => cs_cia2, + we => pulseWrIo, + rd => pulseRd, + + addr => cpuAddr(3 downto 0), + di => cpuDo, + do => cia2Do, + + ppai => cia2_pai, + ppao => cia2_pao, + ppbi => cia2_pbi, + ppbo => cia2_pbo, + + flag_n => '1', + + irq_n => irq_cia2 + ); + +-- ----------------------------------------------------------------------- +-- 6510 CPU +-- ----------------------------------------------------------------------- + cpu: entity work.cpu_6510 + generic map ( + pipelineOpcode => false, + pipelineAluMux => false, + pipelineAluOut => false + ) + port map ( + clk => clk32, + reset => reset, + enable => enableCpu, + nmi_n => nmiLoc, + nmi_ack => nmi_ack, + irq_n => irqLoc, + + di => cpuDi, + addr => cpuAddr, + do => cpuDo, + we => cpuWe, + + diIO => "00010111", + doIO => cpuIO, + + debugOpcode => open, + debugPc => open, + debugA => open, + debugX => open, + debugY => open, + debugS => open + ); + +-- ----------------------------------------------------------------------- +-- Keyboard +-- ----------------------------------------------------------------------- + myKeyboard: entity work.io_ps2_keyboard + port map ( + clk => clk32, + kbd_clk => kbd_clk, + kbd_dat => kbd_dat, + interrupt => newScanCode, + scanCode => theScanCode + ); + + myKeyboardMatrix: entity work.fpga64_keyboard_matrix + port map ( + clk => clk32, + theScanCode => theScanCode, + newScanCode => newScanCode, + + joyA => (not joyA(4 downto 0)), + joyB => (not joyB(4 downto 0)), + pai => cia1_pao, + pbi => cia1_pbo, + pao => cia1_pai, + pbo => cia1_pbi, + + videoKey => videoKey, + traceKey => open, + trace2Key => trace2Key, + reset_key => reset_key, + restore_key => restore_key, + cart_detach_key => cart_detach_key, -- cartridge detach key CTRL-D - LCA + disk_num => disk_num, + + backwardsReadingEnabled => '1' + ); + +-- ----------------------------------------------------------------------- +-- Reset button +-- ----------------------------------------------------------------------- + calcReset: process(clk32) + begin + if rising_edge(clk32) then + if sysCycle = sysCycleDef'high then + if reset_cnt = resetCycles then + reset <= '0'; + else + reset <= '1'; + reset_cnt <= reset_cnt + 1; + end if; + end if; + if reset_n = '0' + or dma_n = '0' then -- temp reset fix + reset_cnt <= 0; + end if; + end if; + end process; + + -- Video modes + ntscMode <= ntscInitMode xor ntscModeInvert; + process(clk32) + begin + if rising_edge(clk32) then + if videoKey = '1' then + ntscModeInvert <= not ntscModeInvert; + end if; + end if; + end process; + + iec_data_o <= cia2_pao(5); + iec_clk_o <= cia2_pao(4); + iec_atn_o <= cia2_pao(3); + ramDataOut <= "00" & cia2_pao(5 downto 3) & "000" when sysCycle >= CYCLE_IEC0 and sysCycle <= CYCLE_IEC3 else cpuDo; + ramAddr <= systemAddr when (phi0_cpu = '1') or (phi0_vic = '1') else (others => '0'); + ramWe <= '0' when sysCycle = CYCLE_IEC2 or sysCycle = CYCLE_IEC3 else not systemWe; + ramCE <= '0' when sysCycle /= CYCLE_IDLE0 and sysCycle /= CYCLE_IDLE1 and sysCycle /= CYCLE_IDLE2 and + sysCycle /= CYCLE_IDLE3 and sysCycle /= CYCLE_IDLE4 and sysCycle /= CYCLE_IDLE5 and + sysCycle /= CYCLE_IDLE6 and sysCycle /= CYCLE_IDLE7 and sysCycle /= CYCLE_IDLE8 and + sysCycle /= CYCLE_IEC0 and sysCycle /= CYCLE_IEC1 and sysCycle /= CYCLE_IEC2 and + sysCycle /= CYCLE_IEC3 and sysCycle /= CYCLE_CPU0 and sysCycle /= CYCLE_CPU1 and sysCycle /= CYCLE_CPUF and + cs_ram = '1' else '1'; + + process(clk32) + begin + if rising_edge(clk32) then + if sysCycle = CYCLE_CPUD + or sysCycle = CYCLE_VIC2 then + ramDataReg <= unsigned(ramDataIn); + end if; + end if; + end process; + +--serialBus and SID + serialBus: process(clk32, sysCycle, cs_sid, cs_ioE, cs_ioF, cs_romL, cs_romH, cpuWe) + begin + ces <= "1111"; + if sysCycle = CYCLE_IEC0 + or sysCycle = CYCLE_IEC1 + or sysCycle = CYCLE_IEC2 + or sysCycle = CYCLE_IEC3 then + ces <= "1011";--iec port + end if; + if cs_sid = '1' then + ces <= "0011"; --SID 1 + end if; + if cs_romL = '1' then + ces <= "0000"; + end if; + if cs_romH = '1' then + ces <= "0100"; + end if; + if sysCycle /= CYCLE_CPU0 + and sysCycle /= CYCLE_CPU1 + and sysCycle /= CYCLE_CPUF then + if cs_ioE = '1' then + ces <= "0101"; + end if; + if cs_ioF = '1' then + ces <= "0001"; + end if; + end if; + if rising_edge(clk32) then + if sysCycle = CYCLE_IEC1 then + cia2_pai(7) <= iec_data_i; + cia2_pai(6) <= iec_clk_i; + end if; + end if; + end process; + + process(clk32) + begin + if rising_edge(clk32) then + if phi0_vic = '1' then + lastVicDi <= vicDi; + end if; + end if; + end process; + + process(clk32) + begin + if rising_edge(clk32) then + if trace2Key = '1' then + debuggerOn <= not debuggerOn; + end if; + end if; + end process; + + cia2_pai(5 downto 0) <= cia2_pao(5 downto 0); + cia2_pbi(7 downto 0) <= cia2_pbo; + +-- ----------------------------------------------------------------------- +-- VIC bank to address lines +-- ----------------------------------------------------------------------- + vicAddr(14) <= (not cia2_pao(0)); + vicAddr(15) <= (not cia2_pao(1)); + +-- ----------------------------------------------------------------------- +-- Interrupt lines +-- ----------------------------------------------------------------------- + irq_n <= 'Z'; + irqLoc <= irq_cia1 and irq_vic and irq_n; + nmiLoc <= irq_cia2 and nmi_n; + freeze_key <= restore_key; + +-- ----------------------------------------------------------------------- +-- Dummy silence audio output +-- ----------------------------------------------------------------------- + still <= X"4000"; + + +-- ----------------------------------------------------------------------- +-- Cartridge port lines LCA +-- ----------------------------------------------------------------------- + romL <= cs_romL; + romH <= cs_romH; + IOE <= cs_ioE; + IOF <= cs_ioF; + UMAXromH <= cs_UMAXromH; + CPU_hasbus <= cpuHasBus; +end architecture; diff --git a/Commodore - 64_Mist/rtl/gcr_floppy.vhd b/Commodore - 64_Mist/rtl/gcr_floppy.vhd new file mode 100644 index 00000000..b25229f3 --- /dev/null +++ b/Commodore - 64_Mist/rtl/gcr_floppy.vhd @@ -0,0 +1,316 @@ +--------------------------------------------------------------------------------- +-- Commodore 1541 gcr floppy (read/write) by Dar (darfpga@aol.fr) 23-May-2017 +-- http://darfpga.blogspot.fr +-- +-- produces GCR data, byte(ready) and sync signal to feed c1541_logic from current +-- track buffer ram which contains D64 data +-- +-- gets GCR data from c1541_logic, while producing byte(ready) signal. Data feed +-- track buffer ram after conversion +-- +-- Input clk 32MHz +-- +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity gcr_floppy is +port( + clk32 : in std_logic; + dout : out std_logic_vector(7 downto 0); -- data from ram to 1541 logic + din : in std_logic_vector(7 downto 0); -- data from 1541 logic to ram + mode : in std_logic; -- read/write + mtr : in std_logic; -- stepper motor on/off + sync_n : out std_logic; -- reading SYNC bytes + byte_n : out std_logic; -- byte ready + + track : in std_logic_vector(5 downto 0); + sector : out std_logic_vector(4 downto 0); + byte_addr : out std_logic_vector(7 downto 0); + + ram_do : in std_logic_vector(7 downto 0); + ram_di : buffer std_logic_vector(7 downto 0); + ram_we : out std_logic; + ram_ready : in std_logic +); +end gcr_floppy; + +architecture struct of gcr_floppy is + +signal bit_clk_en : std_logic; +signal sync_cnt : std_logic_vector(5 downto 0) := (others => '0'); +signal byte_cnt : std_logic_vector(8 downto 0) := (others => '0'); +signal nibble : std_logic := '0'; +signal gcr_bit_cnt : std_logic_vector(3 downto 0) := (others => '0'); +signal bit_cnt : std_logic_vector(2 downto 0) := (others => '0'); + +signal sync_in_n : std_logic; +signal byte_in_n : std_logic; + +signal sector_dbl : std_logic_vector(4 downto 0) := (others => '0'); +signal state : std_logic := '0'; + +signal data_header : std_logic_vector(7 downto 0); +signal data_body : std_logic_vector(7 downto 0); +signal data : std_logic_vector(7 downto 0); +signal data_cks : std_logic_vector(7 downto 0); +signal gcr_nibble : std_logic_vector(4 downto 0); +signal gcr_bit : std_logic; +signal gcr_byte : std_logic_vector(7 downto 0); + +signal mode_r1 : std_logic; +signal mode_r2 : std_logic; + +type gcr_array is array(0 to 15) of std_logic_vector(4 downto 0); + +signal gcr_lut : gcr_array := + ("01010","11010","01001","11001", + "01110","11110","01101","11101", + "10010","10011","01011","11011", + "10110","10111","01111","10101"); + +signal sector_max : std_logic_vector(4 downto 0); + +signal gcr_byte_out : std_logic_vector(7 downto 0); +signal gcr_bit_out : std_logic; +signal gcr_nibble_out : std_logic_vector(4 downto 0); +signal nibble_out : std_logic_vector(3 downto 0); + +signal autorise_write : std_logic; +signal autorise_count : std_logic; + +begin + +sync_n <= sync_in_n when mtr = '1' and ram_ready = '1' else '1'; + +sector <= sector_dbl; + +with byte_cnt select + data_header <= + X"08" when "000000000", + "00"&track xor "000"§or_dbl when "000000001", + "000"§or_dbl when "000000010", + "00"&track when "000000011", + X"20" when "000000100", + X"20" when "000000101", + X"0F" when others; + +with byte_cnt select + data_body <= + X"07" when "000000000", + data_cks when "100000001", + X"00" when "100000010", + X"00" when "100000011", + X"0F" when "100000100", + X"0F" when "100000101", + X"0F" when "100000110", + X"0F" when "100000111", + X"0F" when "100001000", + X"0F" when "100001001", + X"0F" when "100001010", + X"0F" when "100001011", + X"0F" when "100001100", + X"0F" when "100001101", + X"0F" when "100001110", + X"0F" when "100001111", + X"0F" when "100010000", + X"0F" when "100010001", + ram_do when others; +with state select + data <= data_header when '0', data_body when others; + +with nibble select + gcr_nibble <= + gcr_lut(to_integer(unsigned(data(7 downto 4)))) when '0', + gcr_lut(to_integer(unsigned(data(3 downto 0)))) when others; + +gcr_bit <= gcr_nibble(to_integer(unsigned(gcr_bit_cnt))); + +sector_max <= "10100" when track < std_logic_vector(to_unsigned(18,6)) else + "10010" when track < std_logic_vector(to_unsigned(25,6)) else + "10001" when track < std_logic_vector(to_unsigned(31,6)) else + "10000" ; + +gcr_bit_out <= gcr_byte_out(to_integer(unsigned(not bit_cnt))); + +with gcr_nibble_out select + nibble_out <= X"0" when "01010",--"01010", + X"1" when "01011",--"11010", + X"2" when "10010",--"01001", + X"3" when "10011",--"11001", + X"4" when "01110",--"01110", + X"5" when "01111",--"11110", + X"6" when "10110",--"01101", + X"7" when "10111",--"11101", + X"8" when "01001",--"10010", + X"9" when "11001",--"10011", + X"A" when "11010",--"01011", + X"B" when "11011",--"11011", + X"C" when "01101",--"10110", + X"D" when "11101",--"10111", + X"E" when "11110",--"01111", + X"F" when others; --"10101", + +process (clk32) + variable bit_clk_cnt : std_logic_vector(7 downto 0) := (others => '0'); +begin + if rising_edge(clk32) then + + mode_r1 <= mode; + + if (mode_r1 xor mode) = '1' then -- read <-> write change + bit_clk_cnt := (others => '0'); + byte_n <= '1'; + bit_clk_en <= '0'; + else + + bit_clk_en <= '0'; + if bit_clk_cnt = X"6F" then + bit_clk_en <= '1'; + bit_clk_cnt := (others => '0'); + else + bit_clk_cnt := bit_clk_cnt + '1'; + end if; + + byte_n <= '1'; + if byte_in_n = '0' and mtr = '1' and ram_ready = '1' then + if bit_clk_cnt > X"10" then + if bit_clk_cnt < X"5E" then + byte_n <= '0'; + end if; + end if; + end if; + + end if; + + end if; +end process; + +read_write_process : process (clk32, bit_clk_en) +begin + if rising_edge(clk32) then + + ram_we <= '0'; + if bit_clk_en = '1' then + mode_r2 <= mode; + if mode = '1' then autorise_write <= '0'; end if; + + if (mode xor mode_r2) = '1' then + if mode = '1' then -- leaving write mode + sync_in_n <= '0'; + sync_cnt <= (others => '0'); + state <= '0'; + else -- entering write mode + byte_cnt <= (others => '0'); + nibble <= '0'; + gcr_bit_cnt <= (others => '0'); + bit_cnt <= (others => '0'); + gcr_byte <= (others => '0'); + data_cks <= (others => '0'); + end if; + end if; + + if sync_in_n = '0' and mode = '1' then + + byte_cnt <= (others => '0'); + nibble <= '0'; + gcr_bit_cnt <= (others => '0'); + bit_cnt <= (others => '0'); + dout <= (others => '0'); + gcr_byte <= (others => '0'); + data_cks <= (others => '0'); + + if sync_cnt = X"31" then + sync_cnt <= (others => '0'); + sync_in_n <= '1'; + else + sync_cnt <= sync_cnt + '1'; + + end if; + + end if; + + if sync_in_n = '1' or mode = '0' then + + gcr_bit_cnt <= gcr_bit_cnt + '1'; + if gcr_bit_cnt = X"4" then + gcr_bit_cnt <= (others => '0'); + if nibble = '1' then + nibble <= '0'; + byte_addr <= byte_cnt(7 downto 0); + if byte_cnt = "000000000" then + data_cks <= (others => '0'); + else + data_cks <= data_cks xor data; + end if; + if mode = '1' or (mode = '0' and autorise_count = '1') then + byte_cnt <= byte_cnt + '1'; + end if; + else + nibble <= '1'; + if mode = '0' and ram_di = X"07" then + autorise_write <= '1'; + autorise_count <= '1'; + end if; + if byte_cnt >= "100000000" then + autorise_write <= '0'; + autorise_count <= '0'; + end if; + end if; + end if; + + bit_cnt <= bit_cnt + '1'; + byte_in_n <= '1'; + if bit_cnt = X"7" then + byte_in_n <= '0'; + gcr_byte_out <= din; + end if; + + if state = '0' then + if byte_cnt = "000010000" then + sync_in_n <= '0'; + state<= '1'; + end if; + else + if byte_cnt = "100010001" then + sync_in_n <= '0'; + state <= '0'; + if sector_dbl = sector_max then + sector_dbl <= (others=>'0'); + else + sector_dbl <= sector_dbl + '1'; + end if; + end if; + end if; + -- demux byte from floppy (ram) + gcr_byte <= gcr_byte(6 downto 0) & gcr_bit; + if bit_cnt = X"7" then + dout <= gcr_byte(6 downto 0) & gcr_bit; + end if; + + -- serialise/convert byte to floppy (ram) + gcr_nibble_out <= gcr_nibble_out(3 downto 0) & gcr_bit_out; + + if gcr_bit_cnt = X"0" then + if nibble = '0' then + ram_di(3 downto 0) <= nibble_out; + else + ram_di(7 downto 4) <= nibble_out; + end if; + end if; + + if gcr_bit_cnt = X"1" and nibble = '0' then + if autorise_write = '1' then + ram_we <= '1'; + end if; + end if; + + end if; + end if; + end if; + +end process; + +end struct; diff --git a/Commodore - 64_Mist/rtl/gen_ram.vhd b/Commodore - 64_Mist/rtl/gen_ram.vhd new file mode 100644 index 00000000..21f24dde --- /dev/null +++ b/Commodore - 64_Mist/rtl/gen_ram.vhd @@ -0,0 +1,76 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in unsigned((aWidth-1) downto 0); + d : in unsigned((dWidth-1) downto 0); + q : out unsigned((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of unsigned((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : unsigned((aWidth-1) downto 0); + signal qReg : unsigned((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- + q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(addr)) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + qReg <= ram(to_integer(rAddrReg)); + rAddrReg <= addr; + end if; + end process; +end architecture; + diff --git a/Commodore - 64_Mist/rtl/hq2x.sv b/Commodore - 64_Mist/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Commodore - 64_Mist/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Commodore - 64_Mist/rtl/io_ps2_keyboard.vhd b/Commodore - 64_Mist/rtl/io_ps2_keyboard.vhd new file mode 100644 index 00000000..38285c50 --- /dev/null +++ b/Commodore - 64_Mist/rtl/io_ps2_keyboard.vhd @@ -0,0 +1,77 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity io_ps2_keyboard is + port ( + clk: in std_logic; + kbd_clk: in std_logic; + kbd_dat: in std_logic; + + interrupt: out std_logic; + scanCode: out unsigned(7 downto 0) + ); +end io_ps2_keyboard; + +architecture Behavioral of io_ps2_keyboard is + signal clk_reg: std_logic; + signal clk_waitNextBit: std_logic; + signal clk_filter: integer range 0 to 15; + signal shift_reg: unsigned(10 downto 0) := (others => '0'); + + signal bitsCount: integer range 0 to 10 := 0; + signal timeout: integer range 0 to 5000 := 0; -- 2* 50 us at 50 Mhz +begin + process(clk) + begin + if rising_edge(clk) then + -- Interrupt is edge triggered. Only 1 clock high. + interrupt <= '0'; + + -- Timeout if keyboard does not send anymore. + if timeout /= 0 then + timeout <= timeout - 1; + else + bitsCount <= 0; + end if; + + -- Filter glitches on the clock + if (clk_reg /= kbd_clk) then + clk_filter <= 15; -- Wait 15 ticks + clk_reg <= kbd_clk; -- Store clock edge to detect changes + clk_waitNextBit <= '0'; -- Next bit comming up... + elsif (clk_filter /= 0) then + -- Wait for clock to stabilise + -- Clock must be stable before we sample the data line. + clk_filter <= clk_filter - 1; + elsif (clk_reg = '1') and (clk_waitNextBit = '0') then + -- We have a stable clock, so assume stable data too. + clk_waitNextBit <= '1'; + + -- Move data into shift register + shift_reg <= kbd_dat & shift_reg(10 downto 1); + timeout <= 5000; + if bitsCount < 10 then + bitsCount <= bitsCount + 1; + else + -- 10 bits received. Output new scancode + bitsCount <= 0; + interrupt <= '1'; + scanCode <= shift_reg(9 downto 2); + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/Commodore - 64_Mist/rtl/m6522.vhd b/Commodore - 64_Mist/rtl/m6522.vhd new file mode 100644 index 00000000..e9bd0603 --- /dev/null +++ b/Commodore - 64_Mist/rtl/m6522.vhd @@ -0,0 +1,919 @@ + -- + -- A simulation model of VIC20 hardware - VIA implementation + -- Copyright (c) MikeJ - March 2003 + -- + -- All rights reserved + -- + -- Redistribution and use in source and synthezised forms, with or without + -- modification, are permitted provided that the following conditions are met: + -- + -- Redistributions of source code must retain the above copyright notice, + -- this list of conditions and the following disclaimer. + -- + -- Redistributions in synthesized form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- + -- Neither the name of the author nor the names of other contributors may + -- be used to endorse or promote products derived from this software without + -- specific prior written permission. + -- + -- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE + -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + -- POSSIBILITY OF SUCH DAMAGE. + -- + -- You are responsible for any legal issues arising from your use of this code. + -- + -- The latest version of this file can be found at: www.fpgaarcade.com + -- + -- Email vic20@fpgaarcade.com + -- + -- + -- Revision list + -- + -- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation + -- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS) + -- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger + -- version 002 fix from Mark McDougall, untested + -- version 001 initial release + -- not very sure about the shift register, documentation is a bit light. + + library ieee ; + use ieee.std_logic_1164.all ; + use ieee.numeric_std.all; + + entity M6522 is + port ( + + I_RS : in std_logic_vector(3 downto 0); + I_DATA : in std_logic_vector(7 downto 0); + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_RW_L : in std_logic; + I_CS1 : in std_logic; + I_CS2_L : in std_logic; + + O_IRQ_L : out std_logic; -- note, not open drain + -- port a + I_CA1 : in std_logic; + I_CA2 : in std_logic; + O_CA2 : out std_logic; + O_CA2_OE_L : out std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + -- port b + I_CB1 : in std_logic; + O_CB1 : out std_logic; + O_CB1_OE_L : out std_logic; + + I_CB2 : in std_logic; + O_CB2 : out std_logic; + O_CB2_OE_L : out std_logic; + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_P2_H : in std_logic; -- high for phase 2 clock ____----__ + RESET_L : in std_logic; + ENA_4 : in std_logic; -- clk enable + CLK : in std_logic + ); + end; + + architecture RTL of M6522 is + + signal phase : std_logic_vector(1 downto 0):="00"; + signal p2_h_t1 : std_logic; + signal cs : std_logic; + + -- registers + signal r_ddra : std_logic_vector(7 downto 0); + signal r_ora : std_logic_vector(7 downto 0); + signal r_ira : std_logic_vector(7 downto 0); + + signal r_ddrb : std_logic_vector(7 downto 0); + signal r_orb : std_logic_vector(7 downto 0); + signal r_irb : std_logic_vector(7 downto 0); + + signal r_t1l_l : std_logic_vector(7 downto 0); + signal r_t1l_h : std_logic_vector(7 downto 0); + signal r_t2l_l : std_logic_vector(7 downto 0); + signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip + signal r_sr : std_logic_vector(7 downto 0); + signal r_acr : std_logic_vector(7 downto 0); + signal r_pcr : std_logic_vector(7 downto 0); + signal r_ifr : std_logic_vector(7 downto 0); + signal r_ier : std_logic_vector(6 downto 0); + + signal sr_write_ena : boolean; + signal sr_read_ena : boolean; + signal ifr_write_ena : boolean; + signal ier_write_ena : boolean; + signal clear_irq : std_logic_vector(7 downto 0); + signal load_data : std_logic_vector(7 downto 0); + + -- timer 1 + signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... + signal t1c_active : boolean; + signal t1c_done : boolean; + signal t1_w_reset_int : boolean; + signal t1_r_reset_int : boolean; + signal t1_load_counter : boolean; + signal t1_reload_counter : boolean; + signal t1_toggle : std_logic; + signal t1_irq : std_logic := '0'; + + -- timer 2 + signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... + signal t2c_active : boolean; + signal t2c_done : boolean; + signal t2_pb6 : std_logic; + signal t2_pb6_t1 : std_logic; + signal t2_w_reset_int : boolean; + signal t2_r_reset_int : boolean; + signal t2_load_counter : boolean; + signal t2_reload_counter : boolean; + signal t2_irq : std_logic := '0'; + signal t2_sr_ena : boolean; + + -- shift reg + signal sr_cnt : std_logic_vector(3 downto 0); + signal sr_cb1_oe_l : std_logic; + signal sr_cb1_out : std_logic; + signal sr_drive_cb2 : std_logic; + signal sr_strobe : std_logic; + signal sr_strobe_t1 : std_logic; + signal sr_strobe_falling : boolean; + signal sr_strobe_rising : boolean; + signal sr_irq : std_logic; + signal sr_out : std_logic; + signal sr_off_delay : std_logic; + + -- io + signal w_orb_hs : std_logic; + signal w_ora_hs : std_logic; + signal r_irb_hs : std_logic; + signal r_ira_hs : std_logic; + + signal ca_hs_sr : std_logic; + signal ca_hs_pulse : std_logic; + signal cb_hs_sr : std_logic; + signal cb_hs_pulse : std_logic; + + signal cb1_in_mux : std_logic; + signal ca1_ip_reg : std_logic; + signal cb1_ip_reg : std_logic; + signal ca1_int : boolean; + signal cb1_int : boolean; + signal ca1_irq : std_logic; + signal cb1_irq : std_logic; + + signal ca2_ip_reg : std_logic; + signal cb2_ip_reg : std_logic; + signal ca2_int : boolean; + signal cb2_int : boolean; + signal ca2_irq : std_logic; + signal cb2_irq : std_logic; + + signal final_irq : std_logic; + begin + + p_phase : process + begin + -- internal clock phase + wait until rising_edge(CLK); + if (ENA_4 = '1') then + p2_h_t1 <= I_P2_H; + if (p2_h_t1 = '0') and (I_P2_H = '1') then + phase <= "11"; + else + phase <= std_logic_vector(unsigned(phase) + 1); + end if; + end if; + end process; + + p_cs : process(I_CS1, I_CS2_L, I_P2_H) + begin + cs <= '0'; + if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then + cs <= '1'; + end if; + end process; + + -- peripheral control reg (pcr) + -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) + -- 3..1 ca2 operation + -- 000 input -ve edge + -- 001 independend interrupt input -ve edge + -- 010 input +ve edge + -- 011 independend interrupt input +ve edge + -- 100 handshake output + -- 101 pulse output + -- 110 low output + -- 111 high output + -- 7..4 as 3..0 for cb1,cb2 + + -- auxiliary control reg (acr) + -- 0 input latch PA (0 disable, 1 enable) + -- 1 input latch PB (0 disable, 1 enable) + -- 4..2 shift reg control + -- 000 disable + -- 001 shift in using t2 + -- 010 shift in using o2 + -- 011 shift in using ext clk + -- 100 shift out free running t2 rate + -- 101 shift out using t2 + -- 101 shift out using o2 + -- 101 shift out using ext clk + -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) + -- 7..6 t1 timer control + -- 00 timed interrupt each time t1 is loaded pb7 disable + -- 01 continuous interrupts pb7 disable + -- 00 timed interrupt each time t1 is loaded pb7 one shot output + -- 01 continuous interrupts pb7 square wave output + -- + + p_write_reg_reset : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + r_ora <= x"00"; r_orb <= x"00"; + r_ddra <= x"00"; r_ddrb <= x"00"; + r_acr <= x"00"; r_pcr <= x"00"; + + w_orb_hs <= '0'; + w_ora_hs <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + w_orb_hs <= '0'; + w_ora_hs <= '0'; + if (cs = '1') and (I_RW_L = '0') then + case I_RS is + when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; + when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; + when x"2" => r_ddrb <= I_DATA; + when x"3" => r_ddra <= I_DATA; + + when x"B" => r_acr <= I_DATA; + when x"C" => r_pcr <= I_DATA; + when x"F" => r_ora <= I_DATA; + + when others => null; + end case; + end if; + + if r_acr(7) = '1' then + -- DMB: Forgetting to clear B7 broke Acornsoft Planetoid + if t1_load_counter then + r_orb(7) <= '0'; -- writing T1C-H resets bit 7 + elsif t1_toggle = '1' then + r_orb(7) <= not r_orb(7); -- toggle + end if; + end if; + end if; + end if; + end process; + + p_write_reg : process (RESET_L, CLK) is + begin + if (RESET_L = '0') then + -- The spec says, this is not reset. + -- Fact is that the 1541 VIA1 timer won't work, + -- as the firmware ONLY sets the r_t1l_h latch!!!! + r_t1l_l <= (others => '0'); + r_t1l_h <= (others => '0'); + r_t2l_l <= (others => '0'); + r_t2l_h <= (others => '0'); + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + t1_w_reset_int <= false; + t1_load_counter <= false; + + t2_w_reset_int <= false; + t2_load_counter <= false; + + load_data <= x"00"; + sr_write_ena <= false; + ifr_write_ena <= false; + ier_write_ena <= false; + + if (cs = '1') and (I_RW_L = '0') then + load_data <= I_DATA; + case I_RS is + when x"4" => r_t1l_l <= I_DATA; + when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; + t1_load_counter <= true; + + when x"6" => r_t1l_l <= I_DATA; + when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; + + when x"8" => r_t2l_l <= I_DATA; + when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; + t2_load_counter <= true; + + when x"A" => sr_write_ena <= true; + when x"D" => ifr_write_ena <= true; + when x"E" => ier_write_ena <= true; + + when others => null; + end case; + end if; + end if; + end if; + end process; + + p_oe : process(cs, I_RW_L) + begin + O_DATA_OE_L <= '1'; + if (cs = '1') and (I_RW_L = '1') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, + r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb) + begin + t1_r_reset_int <= false; + t2_r_reset_int <= false; + sr_read_ena <= false; + r_irb_hs <= '0'; + r_ira_hs <= '0'; + O_DATA <= x"00"; -- default + if (cs = '1') and (I_RW_L = '1') then + case I_RS is + --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; + -- fix from Mark McDougall, untested + when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; + when x"1" => O_DATA <= (r_ira and not r_ddra) or (r_ora and r_ddra); r_ira_hs <= '1'; + when x"2" => O_DATA <= r_ddrb; + when x"3" => O_DATA <= r_ddra; + when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; + when x"5" => O_DATA <= t1c(15 downto 8); + when x"6" => O_DATA <= r_t1l_l; + when x"7" => O_DATA <= r_t1l_h; + when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; + when x"9" => O_DATA <= t2c(15 downto 8); + when x"A" => O_DATA <= r_sr; sr_read_ena <= true; + when x"B" => O_DATA <= r_acr; + when x"C" => O_DATA <= r_pcr; + when x"D" => O_DATA <= r_ifr; + when x"E" => O_DATA <= ('0' & r_ier); + when x"F" => O_DATA <= r_ira; + when others => null; + end case; + end if; + + end process; + -- + -- IO + -- + p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) + begin + -- if the shift register is enabled, cb1 may be an output + -- in this case, we should listen to the CB1_OUT for the interrupt + if (sr_cb1_oe_l = '1') then + cb1_in_mux <= I_CB1; + else + cb1_in_mux <= sr_cb1_out; + end if; + end process; + + p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) + begin + if (r_pcr(0) = '0') then -- ca1 control + -- negative edge + ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); + else + -- positive edge + ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); + end if; + + if (r_pcr(4) = '0') then -- cb1 control + -- negative edge + cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); + else + -- positive edge + cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); + end if; + end process; + + p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) + begin + ca2_int <= false; + if (r_pcr(3) = '0') then -- ca2 input + if (r_pcr(2) = '0') then -- ca2 edge + -- negative edge + ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); + else + -- positive edge + ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); + end if; + end if; + + cb2_int <= false; + if (r_pcr(7) = '0') then -- cb2 input + if (r_pcr(6) = '0') then -- cb2 edge + -- negative edge + cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); + else + -- positive edge + cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); + end if; + end if; + end process; + + p_ca2_cb2 : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_CA2 <= '0'; + O_CA2_OE_L <= '1'; + O_CB2 <= '0'; + O_CB2_OE_L <= '1'; + + ca_hs_sr <= '0'; + ca_hs_pulse <= '0'; + cb_hs_sr <= '0'; + cb_hs_pulse <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- ca + if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then + ca_hs_sr <= '1'; + elsif ca1_int then + ca_hs_sr <= '0'; + end if; + + if (phase = "00") then + ca_hs_pulse <= w_ora_hs or r_ira_hs; + end if; + + O_CA2_OE_L <= not r_pcr(3); -- ca2 output + case r_pcr(3 downto 1) is + when "000" => O_CA2 <= '0'; -- input + when "001" => O_CA2 <= '0'; -- input + when "010" => O_CA2 <= '0'; -- input + when "011" => O_CA2 <= '0'; -- input + when "100" => O_CA2 <= not (ca_hs_sr); -- handshake + when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse + when "110" => O_CA2 <= '0'; -- low + when "111" => O_CA2 <= '1'; -- high + when others => null; + end case; + + -- cb + if (phase = "00") and (w_orb_hs = '1') then + cb_hs_sr <= '1'; + elsif cb1_int then + cb_hs_sr <= '0'; + end if; + + if (phase = "00") then + cb_hs_pulse <= w_orb_hs; + end if; + + O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial + if (sr_drive_cb2 = '1') then -- serial output + O_CB2 <= sr_out; + else + case r_pcr(7 downto 5) is + when "000" => O_CB2 <= '0'; -- input + when "001" => O_CB2 <= '0'; -- input + when "010" => O_CB2 <= '0'; -- input + when "011" => O_CB2 <= '0'; -- input + when "100" => O_CB2 <= not (cb_hs_sr); -- handshake + when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse + when "110" => O_CB2 <= '0'; -- low + when "111" => O_CB2 <= '1'; -- high + when others => null; + end case; + end if; + end if; + end if; + end process; + O_CB1 <= sr_cb1_out; + O_CB1_OE_L <= sr_cb1_oe_l; + + p_ca_cb_irq : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + ca1_irq <= '0'; + ca2_irq <= '0'; + cb1_irq <= '0'; + cb2_irq <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- not pretty + if ca1_int then + ca1_irq <= '1'; + elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then + ca1_irq <= '0'; + end if; + + if ca2_int then + ca2_irq <= '1'; + else + if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or + (clear_irq(0) = '1') then + ca2_irq <= '0'; + end if; + end if; + + if cb1_int then + cb1_irq <= '1'; + elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then + cb1_irq <= '0'; + end if; + + if cb2_int then + cb2_irq <= '1'; + else + if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or + (clear_irq(3) = '1') then + cb2_irq <= '0'; + end if; + end if; + end if; + end if; + end process; + + p_input_reg : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + ca1_ip_reg <= '0'; + cb1_ip_reg <= '0'; + + ca2_ip_reg <= '0'; + cb2_ip_reg <= '0'; + + r_ira <= x"00"; + r_irb <= x"00"; + + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- we have a fast clock, so we can have input registers + ca1_ip_reg <= I_CA1; + cb1_ip_reg <= cb1_in_mux; + + ca2_ip_reg <= I_CA2; + cb2_ip_reg <= I_CB2; + + if (r_acr(0) = '0') then + r_ira <= I_PA; + else -- enable latching + if ca1_int then + r_ira <= I_PA; + end if; + end if; + + if (r_acr(1) = '0') then + r_irb <= I_PB; + else -- enable latching + if cb1_int then + r_irb <= I_PB; + end if; + end if; + end if; + end if; + end process; + + + p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) + begin + -- data direction reg (ddr) 0 = input, 1 = output + O_PA <= r_ora; + O_PA_OE_L <= not r_ddra; + + if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well + O_PB_OE_L(7) <= '0'; -- an output if under t1 control + else + O_PB_OE_L(7) <= not (r_ddrb(7)); + end if; + + O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); + O_PB(7 downto 0) <= r_orb(7 downto 0); + + end process; + -- + -- Timer 1 + -- + p_timer1_done : process + variable done : boolean; + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + done := (t1c = x"0000"); + t1c_done <= done and (phase = "11"); + if (phase = "11") then + t1_reload_counter <= done and (r_acr(6) = '1'); + end if; + if t1_load_counter then -- done reset on load! + t1c_done <= false; + end if; + end if; + end process; + + p_timer1 : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + if t1_load_counter or (t1_reload_counter and phase = "11") then + t1c( 7 downto 0) <= r_t1l_l; + t1c(15 downto 8) <= r_t1l_h; + elsif (phase="11") then + t1c <= std_logic_vector(unsigned(t1c) - 1); + end if; + + if t1_load_counter or t1_reload_counter then + t1c_active <= true; + elsif t1c_done then + t1c_active <= false; + end if; + + t1_toggle <= '0'; + if t1c_active and t1c_done then + t1_toggle <= '1'; + t1_irq <= '1'; + elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then + t1_irq <= '0'; + end if; + if t1_load_counter then -- irq reset on load! + t1_irq <= '0'; + end if; + end if; + end process; + -- + -- Timer2 + -- + p_timer2_pb6_input : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + if (phase = "01") then -- leading edge p2_h + t2_pb6 <= I_PB(6); + t2_pb6_t1 <= t2_pb6; + end if; + end if; + end process; + + p_timer2_done : process + variable done : boolean; + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + done := (t2c = x"0000"); + t2c_done <= done and (phase = "11"); + if (phase = "11") then + t2_reload_counter <= done; + end if; + if t2_load_counter then -- done reset on load! + t2c_done <= false; + end if; + end if; + end process; + + p_timer2 : process + variable ena : boolean; + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + if (r_acr(5) = '0') then + ena := true; + else + ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge + end if; + + if t2_load_counter or (t2_reload_counter and phase = "11") then + -- not sure if t2c_reload should be here. Does timer2 just continue to + -- count down, or is it reloaded ? Reloaded makes more sense if using + -- it to generate a clock for the shift register. + t2c( 7 downto 0) <= r_t2l_l; + t2c(15 downto 8) <= r_t2l_h; + else + if (phase="11") and ena then -- or count mode + t2c <= std_logic_vector(unsigned(t2c) - 1); + end if; + end if; + + t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); + + if t2_load_counter then + t2c_active <= true; + elsif t2c_done then + t2c_active <= false; + end if; + + if t2c_active and t2c_done then + t2_irq <= '1'; + elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then + t2_irq <= '0'; + end if; + if t2_load_counter then -- irq reset on load! + t2_irq <= '0'; + end if; + end if; + end process; + -- + -- Shift Register + -- + p_sr : process(RESET_L, CLK) + variable dir_out : std_logic; + variable ena : std_logic; + variable cb1_op : std_logic; + variable cb1_ip : std_logic; + variable use_t2 : std_logic; + variable free_run : std_logic; + variable sr_count_ena : boolean; + begin + if (RESET_L = '0') then + r_sr <= x"00"; + sr_drive_cb2 <= '0'; + sr_cb1_oe_l <= '1'; + sr_cb1_out <= '0'; + sr_strobe <= '1'; + sr_cnt <= "0000"; + sr_irq <= '0'; + sr_out <= '1'; + sr_off_delay <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- decode mode + dir_out := r_acr(4); -- output on cb2 + cb1_op := '0'; + cb1_ip := '0'; + use_t2 := '0'; + free_run := '0'; + + -- DMB: SR still runs even in disabled mode (on rising edge of CB1). + -- It just doesn't generate any interrupts. + -- Ref BBC micro advanced user guide p409 + + case r_acr(4 downto 2) is + -- DMB: in disabled mode, configure cb1 as an input + when "000" => ena := '0'; cb1_ip := '1'; + when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; + when "010" => ena := '1'; cb1_op := '1'; + when "011" => ena := '1'; cb1_ip := '1'; + when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; + when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; + when "110" => ena := '1'; --free_run := '1'; -- hack + when "111" => ena := '1'; cb1_ip := '1'; + when others => null; + end case; + + -- clock select + -- DMB: in disabled mode, strobe from cb1 + if (cb1_ip = '1') then + sr_strobe <= I_CB1; + else + if (sr_cnt(3) = '0') and (free_run = '0') then + sr_strobe <= '1'; + else + if ((use_t2 = '1') and t2_sr_ena) or + ((use_t2 = '0') and (phase = "00")) then + sr_strobe <= not sr_strobe; + end if; + end if; + end if; + + -- latch on rising edge, shift on falling edge + if sr_write_ena then + r_sr <= load_data; + + else + -- DMB: allow shifting in all modes + if (dir_out = '0') then + -- input + if (sr_cnt(3) = '1') or (cb1_ip = '1') then + if sr_strobe_rising then + r_sr(0) <= I_CB2; + elsif sr_strobe_falling then + r_sr(7 downto 1) <= r_sr(6 downto 0); + end if; + end if; + sr_out <= '1'; + else + -- output + if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then + if sr_strobe_falling then + r_sr(7 downto 1) <= r_sr(6 downto 0); + r_sr(0) <= r_sr(7); + sr_out <= r_sr(7); + end if; + else + sr_out <= '1'; + end if; + end if; + end if; + + sr_count_ena := sr_strobe_rising; + + -- DMB: reseting sr_count when not enabled cause the sr to + -- start running immediately it was enabled, which is incorrect + -- and broke the latest SmartSPI ROM on the BBC Micro + if ena = '1' and (sr_write_ena or sr_read_ena) then + -- some documentation says sr bit in IFR must be set as well ? + sr_cnt <= "1000"; + elsif sr_count_ena and (sr_cnt(3) = '1') then + sr_cnt <= std_logic_vector(unsigned(sr_cnt) + 1); + end if; + + if (phase = "00") then + sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out + end if; + + if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then + sr_irq <= '1'; + elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then + sr_irq <= '0'; + end if; + + -- assign ops + sr_drive_cb2 <= dir_out; + sr_cb1_oe_l <= not cb1_op; + sr_cb1_out <= sr_strobe; + end if; + end if; + end process; + + p_sr_strobe_rise_fall : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + sr_strobe_t1 <= sr_strobe; + sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); + sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); + end if; + end process; + -- + -- Interrupts + -- + p_ier : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + r_ier <= "0000000"; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + if ier_write_ena then + if (load_data(7) = '1') then + -- set + r_ier <= r_ier or load_data(6 downto 0); + else + -- clear + r_ier <= r_ier and not load_data(6 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, + cb1_irq, cb2_irq) + begin + r_ifr(7) <= final_irq; + r_ifr(6) <= t1_irq; + r_ifr(5) <= t2_irq; + r_ifr(4) <= cb1_irq; + r_ifr(3) <= cb2_irq; + r_ifr(2) <= sr_irq; + r_ifr(1) <= ca1_irq; + r_ifr(0) <= ca2_irq; + + O_IRQ_L <= not final_irq; + end process; + + p_irq : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + final_irq <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then + final_irq <= '0'; -- no interrupts + else + final_irq <= '1'; + end if; + end if; + end if; + end process; + + p_clear_irq : process(ifr_write_ena, load_data) + begin + clear_irq <= x"00"; + if ifr_write_ena then + clear_irq <= load_data; + end if; + end process; + + end architecture RTL; \ No newline at end of file diff --git a/Commodore - 64_Mist/rtl/mist_io.v b/Commodore - 64_Mist/rtl/mist_io.v new file mode 100644 index 00000000..107c0f69 --- /dev/null +++ b/Commodore - 64_Mist/rtl/mist_io.v @@ -0,0 +1,521 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + input ioctl_force_erase, + output reg ioctl_download = 0, // signal indicating an active download + output reg ioctl_erasing = 0, // signal indicating an active erase + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr = 0, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +reg [24:0] erase_mask; +wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask; + +always@(posedge clk_sys) begin + reg rclkD, rclkD2; + reg old_force = 0; + reg [6:0] erase_clk_div; + reg [24:0] end_addr; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wr <= 0; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wr <= 1; + end + + if(ioctl_download) begin + old_force <= 0; + ioctl_erasing <= 0; + end else begin + + old_force <= ioctl_force_erase; + if(ioctl_force_erase & ~old_force) begin + ioctl_addr <= 'h1FFFF; + erase_mask <= 'h1FFFF; + end_addr <= 'h10002; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if(ioctl_erasing) begin + erase_clk_div <= erase_clk_div + 1'd1; + if(!erase_clk_div) begin + if(next_erase == end_addr) ioctl_erasing <= 0; + else begin + ioctl_addr <= next_erase; + ioctl_dout <= 0; + ioctl_wr <= 1; + end + end + end + end +end + +endmodule \ No newline at end of file diff --git a/Commodore - 64_Mist/rtl/osd.v b/Commodore - 64_Mist/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Commodore - 64_Mist/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Commodore - 64_Mist/rtl/pll.vhd b/Commodore - 64_Mist/rtl/pll.vhd new file mode 100644 index 00000000..1e72638b --- /dev/null +++ b/Commodore - 64_Mist/rtl/pll.vhd @@ -0,0 +1,421 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 64, + clk0_phase_shift => "0", + clk1_divide_by => 27, + clk1_duty_cycle => 50, + clk1_multiply_by => 64, + clk1_phase_shift => "-2604", + clk2_divide_by => 27, + clk2_duty_cycle => 50, + clk2_multiply_by => 32, + clk2_phase_shift => "0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NO_COMPENSATION", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "ON", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "64.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "64.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "32.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "26.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "48" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "64.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "64.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "32.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "64" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "64" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2604" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "32" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Commodore - 64_Mist/rtl/rom_C1541.vhd b/Commodore - 64_Mist/rtl/rom_C1541.vhd new file mode 100644 index 00000000..f25b3691 --- /dev/null +++ b/Commodore - 64_Mist/rtl/rom_C1541.vhd @@ -0,0 +1,198 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: rom_C1541.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY rom_C1541 IS + PORT + ( + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + wren : IN STD_LOGIC := '0'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END rom_C1541; + + +ARCHITECTURE SYN OF rom_c1541 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + init_file => "roms/std_C1541.mif", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 16384, + numwords_b => 16384, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 14, + widthad_b => 14, + width_a => 8, + width_b => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => wraddress, + clock0 => clock, + data_a => data, + wren_a => wren, + address_b => rdaddress, + q_b => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/std_C1541.mif" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/std_C1541.mif" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0 +-- Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C1541.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C1541.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C1541.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C1541.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C1541_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - 64_Mist/rtl/rom_C64.vhd b/Commodore - 64_Mist/rtl/rom_C64.vhd new file mode 100644 index 00000000..e422e4a6 --- /dev/null +++ b/Commodore - 64_Mist/rtl/rom_C64.vhd @@ -0,0 +1,198 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: rom_C64.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY rom_C64 IS + PORT + ( + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + wren : IN STD_LOGIC := '0'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END rom_C64; + + +ARCHITECTURE SYN OF rom_c64 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + init_file => "roms/std_C64.mif", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 16384, + numwords_b => 16384, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 14, + widthad_b => 14, + width_a => 8, + width_b => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => wraddress, + clock0 => clock, + data_a => data, + wren_a => wren, + address_b => rdaddress, + q_b => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "std_C64.mif" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "std_C64.mif" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0 +-- Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C64.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C64.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C64.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C64.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_C64_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - 64_Mist/rtl/rom_GS64.vhd b/Commodore - 64_Mist/rtl/rom_GS64.vhd new file mode 100644 index 00000000..0afeb249 --- /dev/null +++ b/Commodore - 64_Mist/rtl/rom_GS64.vhd @@ -0,0 +1,198 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: rom_GS64.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY rom_GS64 IS + PORT + ( + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + wraddress : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + wren : IN STD_LOGIC := '0'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END rom_GS64; + + +ARCHITECTURE SYN OF rom_GS64 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_b => "NONE", + address_reg_b => "CLOCK0", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + init_file => "roms/std_C64GS.mif", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 16384, + numwords_b => 16384, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_mixed_ports => "DONT_CARE", + widthad_a => 14, + widthad_b => 14, + width_a => 8, + width_b => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => wraddress, + clock0 => clock, + data_a => data, + wren_a => wren, + address_b => rdaddress, + q_b => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "std_GS64.mif" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "std_C64.mif" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]" +-- Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0 +-- Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_GS64.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_GS64.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_GS64.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_GS64.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_GS64_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - 64_Mist/rtl/rom_c64_chargen.vhd b/Commodore - 64_Mist/rtl/rom_c64_chargen.vhd new file mode 100644 index 00000000..d4784e0a --- /dev/null +++ b/Commodore - 64_Mist/rtl/rom_c64_chargen.vhd @@ -0,0 +1,283 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +entity rom_c64_chargen is + port ( + clk: in std_logic; + addr: in unsigned(11 downto 0); + do: out unsigned(7 downto 0) + ); +end entity; + +architecture rtl of rom_c64_chargen is + type romDef is array(0 to 4095) of unsigned(7 downto 0); + constant romData: romDef := ( + X"3C", X"66", X"6E", X"6E", X"60", X"62", X"3C", X"00", X"18", X"3C", X"66", X"7E", X"66", X"66", X"66", X"00", + X"7C", X"66", X"66", X"7C", X"66", X"66", X"7C", X"00", X"3C", X"66", X"60", X"60", X"60", X"66", X"3C", X"00", + X"78", X"6C", X"66", X"66", X"66", X"6C", X"78", X"00", X"7E", X"60", X"60", X"78", X"60", X"60", X"7E", X"00", + X"7E", X"60", X"60", X"78", X"60", X"60", X"60", X"00", X"3C", X"66", X"60", X"6E", X"66", X"66", X"3C", X"00", + X"66", X"66", X"66", X"7E", X"66", X"66", X"66", X"00", X"3C", X"18", X"18", X"18", X"18", X"18", X"3C", X"00", + X"1E", X"0C", X"0C", X"0C", X"0C", X"6C", X"38", X"00", X"66", X"6C", X"78", X"70", X"78", X"6C", X"66", X"00", + X"60", X"60", X"60", X"60", X"60", X"60", X"7E", X"00", X"63", X"77", X"7F", X"6B", X"63", X"63", X"63", X"00", + X"66", X"76", X"7E", X"7E", X"6E", X"66", X"66", X"00", X"3C", X"66", X"66", X"66", X"66", X"66", X"3C", X"00", + X"7C", X"66", X"66", X"7C", X"60", X"60", X"60", X"00", X"3C", X"66", X"66", X"66", X"66", X"3C", X"0E", X"00", + X"7C", X"66", X"66", X"7C", X"78", X"6C", X"66", X"00", X"3C", X"66", X"60", X"3C", X"06", X"66", X"3C", X"00", + X"7E", X"18", X"18", X"18", X"18", X"18", X"18", X"00", X"66", X"66", X"66", X"66", X"66", X"66", X"3C", X"00", + X"66", X"66", X"66", X"66", X"66", X"3C", X"18", X"00", X"63", X"63", X"63", X"6B", X"7F", X"77", X"63", X"00", + X"66", X"66", X"3C", X"18", X"3C", X"66", X"66", X"00", X"66", X"66", X"66", X"3C", X"18", X"18", X"18", X"00", + X"7E", X"06", X"0C", X"18", X"30", X"60", X"7E", X"00", X"3C", X"30", X"30", X"30", X"30", X"30", X"3C", X"00", + X"0C", X"12", X"30", X"7C", X"30", X"62", X"FC", X"00", X"3C", X"0C", X"0C", X"0C", X"0C", X"0C", X"3C", X"00", + X"00", X"18", X"3C", X"7E", X"18", X"18", X"18", X"18", X"00", X"10", X"30", X"7F", X"7F", X"30", X"10", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"18", X"18", X"18", X"18", X"00", X"00", X"18", X"00", + X"66", X"66", X"66", X"00", X"00", X"00", X"00", X"00", X"66", X"66", X"FF", X"66", X"FF", X"66", X"66", X"00", + X"18", X"3E", X"60", X"3C", X"06", X"7C", X"18", X"00", X"62", X"66", X"0C", X"18", X"30", X"66", X"46", X"00", + X"3C", X"66", X"3C", X"38", X"67", X"66", X"3F", X"00", X"06", X"0C", X"18", X"00", X"00", X"00", X"00", X"00", + X"0C", X"18", X"30", X"30", X"30", X"18", X"0C", X"00", X"30", X"18", X"0C", X"0C", X"0C", X"18", X"30", X"00", + X"00", X"66", X"3C", X"FF", X"3C", X"66", X"00", X"00", X"00", X"18", X"18", X"7E", X"18", X"18", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"18", X"18", X"30", X"00", X"00", X"00", X"7E", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"18", X"18", X"00", X"00", X"03", X"06", X"0C", X"18", X"30", X"60", X"00", + X"3C", X"66", X"6E", X"76", X"66", X"66", X"3C", X"00", X"18", X"18", X"38", X"18", X"18", X"18", X"7E", X"00", + X"3C", X"66", X"06", X"0C", X"30", X"60", X"7E", X"00", X"3C", X"66", X"06", X"1C", X"06", X"66", X"3C", X"00", + X"06", X"0E", X"1E", X"66", X"7F", X"06", X"06", X"00", X"7E", X"60", X"7C", X"06", X"06", X"66", X"3C", X"00", + X"3C", X"66", X"60", X"7C", X"66", X"66", X"3C", X"00", X"7E", X"66", X"0C", X"18", X"18", X"18", X"18", X"00", + X"3C", X"66", X"66", X"3C", X"66", X"66", X"3C", X"00", X"3C", X"66", X"66", X"3E", X"06", X"66", X"3C", X"00", + X"00", X"00", X"18", X"00", X"00", X"18", X"00", X"00", X"00", X"00", X"18", X"00", X"00", X"18", X"18", X"30", + X"0E", X"18", X"30", X"60", X"30", X"18", X"0E", X"00", X"00", X"00", X"7E", X"00", X"7E", X"00", X"00", X"00", + X"70", X"18", X"0C", X"06", X"0C", X"18", X"70", X"00", X"3C", X"66", X"06", X"0C", X"18", X"00", X"18", X"00", + X"00", X"00", X"00", X"FF", X"FF", X"00", X"00", X"00", X"08", X"1C", X"3E", X"7F", X"7F", X"1C", X"3E", X"00", + X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"00", X"00", X"00", X"FF", X"FF", X"00", X"00", X"00", + X"00", X"00", X"FF", X"FF", X"00", X"00", X"00", X"00", X"00", X"FF", X"FF", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"FF", X"FF", X"00", X"00", X"30", X"30", X"30", X"30", X"30", X"30", X"30", X"30", + X"0C", X"0C", X"0C", X"0C", X"0C", X"0C", X"0C", X"0C", X"00", X"00", X"00", X"E0", X"F0", X"38", X"18", X"18", + X"18", X"18", X"1C", X"0F", X"07", X"00", X"00", X"00", X"18", X"18", X"38", X"F0", X"E0", X"00", X"00", X"00", + X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", X"FF", X"FF", X"C0", X"E0", X"70", X"38", X"1C", X"0E", X"07", X"03", + X"03", X"07", X"0E", X"1C", X"38", X"70", X"E0", X"C0", X"FF", X"FF", X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", + X"FF", X"FF", X"03", X"03", X"03", X"03", X"03", X"03", X"00", X"3C", X"7E", X"7E", X"7E", X"7E", X"3C", X"00", + X"00", X"00", X"00", X"00", X"00", X"FF", X"FF", X"00", X"36", X"7F", X"7F", X"7F", X"3E", X"1C", X"08", X"00", + X"60", X"60", X"60", X"60", X"60", X"60", X"60", X"60", X"00", X"00", X"00", X"07", X"0F", X"1C", X"18", X"18", + X"C3", X"E7", X"7E", X"3C", X"3C", X"7E", X"E7", X"C3", X"00", X"3C", X"7E", X"66", X"66", X"7E", X"3C", X"00", + X"18", X"18", X"66", X"66", X"18", X"18", X"3C", X"00", X"06", X"06", X"06", X"06", X"06", X"06", X"06", X"06", + X"08", X"1C", X"3E", X"7F", X"3E", X"1C", X"08", X"00", X"18", X"18", X"18", X"FF", X"FF", X"18", X"18", X"18", + X"C0", X"C0", X"30", X"30", X"C0", X"C0", X"30", X"30", X"18", X"18", X"18", X"18", X"18", X"18", X"18", X"18", + X"00", X"00", X"03", X"3E", X"76", X"36", X"36", X"00", X"FF", X"7F", X"3F", X"1F", X"0F", X"07", X"03", X"01", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"F0", X"F0", X"F0", X"F0", X"F0", X"F0", X"F0", X"F0", + X"00", X"00", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"FF", X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", + X"CC", X"CC", X"33", X"33", X"CC", X"CC", X"33", X"33", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"03", + X"00", X"00", X"00", X"00", X"CC", X"CC", X"33", X"33", X"FF", X"FE", X"FC", X"F8", X"F0", X"E0", X"C0", X"80", + X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"18", X"18", X"18", X"1F", X"1F", X"18", X"18", X"18", + X"00", X"00", X"00", X"00", X"0F", X"0F", X"0F", X"0F", X"18", X"18", X"18", X"1F", X"1F", X"00", X"00", X"00", + X"00", X"00", X"00", X"F8", X"F8", X"18", X"18", X"18", X"00", X"00", X"00", X"00", X"00", X"00", X"FF", X"FF", + X"00", X"00", X"00", X"1F", X"1F", X"18", X"18", X"18", X"18", X"18", X"18", X"FF", X"FF", X"00", X"00", X"00", + X"00", X"00", X"00", X"FF", X"FF", X"18", X"18", X"18", X"18", X"18", X"18", X"F8", X"F8", X"18", X"18", X"18", + X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", X"C0", X"E0", X"E0", X"E0", X"E0", X"E0", X"E0", X"E0", X"E0", + X"07", X"07", X"07", X"07", X"07", X"07", X"07", X"07", X"FF", X"FF", X"00", X"00", X"00", X"00", X"00", X"00", + X"FF", X"FF", X"FF", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"FF", X"FF", X"FF", + X"03", X"03", X"03", X"03", X"03", X"03", X"FF", X"FF", X"00", X"00", X"00", X"00", X"F0", X"F0", X"F0", X"F0", + X"0F", X"0F", X"0F", X"0F", X"00", X"00", X"00", X"00", X"18", X"18", X"18", X"F8", X"F8", X"00", X"00", X"00", + X"F0", X"F0", X"F0", X"F0", X"00", X"00", X"00", X"00", X"F0", X"F0", X"F0", X"F0", X"0F", X"0F", X"0F", X"0F", + X"C3", X"99", X"91", X"91", X"9F", X"99", X"C3", X"FF", X"E7", X"C3", X"99", X"81", X"99", X"99", X"99", X"FF", + X"83", X"99", X"99", X"83", X"99", X"99", X"83", X"FF", X"C3", X"99", X"9F", X"9F", X"9F", X"99", X"C3", X"FF", + X"87", X"93", X"99", X"99", X"99", X"93", X"87", X"FF", X"81", X"9F", X"9F", X"87", X"9F", X"9F", X"81", X"FF", + X"81", X"9F", X"9F", X"87", X"9F", X"9F", X"9F", X"FF", X"C3", X"99", X"9F", X"91", X"99", X"99", X"C3", X"FF", + X"99", X"99", X"99", X"81", X"99", X"99", X"99", X"FF", X"C3", X"E7", X"E7", X"E7", X"E7", X"E7", X"C3", X"FF", + X"E1", X"F3", X"F3", X"F3", X"F3", X"93", X"C7", X"FF", X"99", X"93", X"87", X"8F", X"87", X"93", X"99", X"FF", + X"9F", X"9F", X"9F", X"9F", X"9F", X"9F", X"81", X"FF", X"9C", X"88", X"80", X"94", X"9C", X"9C", X"9C", X"FF", + X"99", X"89", X"81", X"81", X"91", X"99", X"99", X"FF", X"C3", X"99", X"99", X"99", X"99", X"99", X"C3", X"FF", + X"83", X"99", X"99", X"83", X"9F", X"9F", X"9F", X"FF", X"C3", X"99", X"99", X"99", X"99", X"C3", X"F1", X"FF", + X"83", X"99", X"99", X"83", X"87", X"93", X"99", X"FF", X"C3", X"99", X"9F", X"C3", X"F9", X"99", X"C3", X"FF", + X"81", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"FF", X"99", X"99", X"99", X"99", X"99", X"99", X"C3", X"FF", + X"99", X"99", X"99", X"99", X"99", X"C3", X"E7", X"FF", X"9C", X"9C", X"9C", X"94", X"80", X"88", X"9C", X"FF", + X"99", X"99", X"C3", X"E7", X"C3", X"99", X"99", X"FF", X"99", X"99", X"99", X"C3", X"E7", X"E7", X"E7", X"FF", + X"81", X"F9", X"F3", X"E7", X"CF", X"9F", X"81", X"FF", X"C3", X"CF", X"CF", X"CF", X"CF", X"CF", X"C3", X"FF", + X"F3", X"ED", X"CF", X"83", X"CF", X"9D", X"03", X"FF", X"C3", X"F3", X"F3", X"F3", X"F3", X"F3", X"C3", X"FF", + X"FF", X"E7", X"C3", X"81", X"E7", X"E7", X"E7", X"E7", X"FF", X"EF", X"CF", X"80", X"80", X"CF", X"EF", X"FF", + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"E7", X"E7", X"FF", X"FF", X"E7", X"FF", + X"99", X"99", X"99", X"FF", X"FF", X"FF", X"FF", X"FF", X"99", X"99", X"00", X"99", X"00", X"99", X"99", X"FF", + X"E7", X"C1", X"9F", X"C3", X"F9", X"83", X"E7", X"FF", X"9D", X"99", X"F3", X"E7", X"CF", X"99", X"B9", X"FF", + X"C3", X"99", X"C3", X"C7", X"98", X"99", X"C0", X"FF", X"F9", X"F3", X"E7", X"FF", X"FF", X"FF", X"FF", X"FF", + X"F3", X"E7", X"CF", X"CF", X"CF", X"E7", X"F3", X"FF", X"CF", X"E7", X"F3", X"F3", X"F3", X"E7", X"CF", X"FF", + X"FF", X"99", X"C3", X"00", X"C3", X"99", X"FF", X"FF", X"FF", X"E7", X"E7", X"81", X"E7", X"E7", X"FF", X"FF", + X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"CF", X"FF", X"FF", X"FF", X"81", X"FF", X"FF", X"FF", X"FF", + X"FF", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"FF", X"FF", X"FC", X"F9", X"F3", X"E7", X"CF", X"9F", X"FF", + X"C3", X"99", X"91", X"89", X"99", X"99", X"C3", X"FF", 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X"CF", X"9F", X"81", X"FF", X"E7", X"E7", X"E7", X"00", X"00", X"E7", X"E7", X"E7", + X"3F", X"3F", X"CF", X"CF", X"3F", X"3F", X"CF", X"CF", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", + X"CC", X"CC", X"33", X"33", X"CC", X"CC", X"33", X"33", X"CC", X"66", X"33", X"99", X"CC", X"66", X"33", X"99", + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"0F", X"0F", X"0F", X"0F", X"0F", X"0F", X"0F", X"0F", + X"FF", X"FF", X"FF", X"FF", X"00", X"00", X"00", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"00", X"3F", X"3F", X"3F", X"3F", X"3F", X"3F", X"3F", X"3F", + X"33", X"33", X"CC", X"CC", X"33", X"33", X"CC", X"CC", X"FC", X"FC", X"FC", X"FC", X"FC", X"FC", X"FC", X"FC", + X"FF", X"FF", X"FF", X"FF", X"33", X"33", X"CC", X"CC", X"33", X"66", X"CC", X"99", X"33", X"66", X"CC", X"99", + X"FC", X"FC", X"FC", X"FC", X"FC", X"FC", X"FC", X"FC", X"E7", X"E7", X"E7", X"E0", X"E0", X"E7", X"E7", X"E7", + X"FF", X"FF", X"FF", X"FF", X"F0", X"F0", X"F0", X"F0", X"E7", X"E7", X"E7", X"E0", X"E0", X"FF", X"FF", X"FF", + X"FF", X"FF", X"FF", X"07", X"07", X"E7", X"E7", X"E7", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"00", X"00", + X"FF", X"FF", X"FF", X"E0", X"E0", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"00", X"00", X"FF", X"FF", X"FF", + X"FF", X"FF", X"FF", X"00", X"00", X"E7", X"E7", X"E7", X"E7", X"E7", X"E7", X"07", X"07", X"E7", X"E7", X"E7", + X"3F", X"3F", X"3F", X"3F", X"3F", X"3F", X"3F", X"3F", X"1F", X"1F", X"1F", X"1F", X"1F", X"1F", X"1F", X"1F", + X"F8", X"F8", X"F8", X"F8", X"F8", X"F8", X"F8", X"F8", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", + X"00", X"00", X"00", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"00", X"00", X"00", + X"FE", X"FC", X"F9", X"93", X"87", X"8F", X"9F", X"FF", X"FF", X"FF", X"FF", X"FF", X"0F", X"0F", X"0F", X"0F", + X"F0", X"F0", X"F0", X"F0", X"FF", X"FF", X"FF", X"FF", X"E7", X"E7", X"E7", X"07", X"07", X"FF", X"FF", X"FF", + X"0F", X"0F", X"0F", X"0F", X"FF", X"FF", X"FF", X"FF", X"0F", X"0F", X"0F", X"0F", X"F0", X"F0", X"F0", X"F0" + ); + +begin + + process(clk) + begin + if rising_edge(clk) then + do <= romData(to_integer(addr(11 downto 0))) after 2 ns; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/Commodore - 64_Mist/rtl/roms/std_C1541.mif b/Commodore - 64_Mist/rtl/roms/std_C1541.mif new file mode 100644 index 00000000..d0d3cf05 --- /dev/null +++ b/Commodore - 64_Mist/rtl/roms/std_C1541.mif @@ -0,0 +1,15762 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=16384; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0000 : 97; + [0001..00FF] : AA; + 0100 : 78; + 0101 : A9; + 0102 : F7; + 0103 : 2D; + 0104 : 00; + 0105 : 1C; + 0106 : 48; + 0107 : A5; + 0108 : 7F; + 0109 : F0; + 010A : 05; + 010B : 68; + 010C : 09; + 010D : 00; + 010E : D0; + 010F : 03; + 0110 : 68; + 0111 : 09; + 0112 : 08; + 0113 : 8D; + 0114 : 00; + 0115 : 1C; + 0116 : 58; + 0117 : 60; + 0118 : 78; + 0119 : A9; + 011A : 08; + 011B : 0D; + 011C : 00; + 011D : 1C; + 011E : 8D; + 011F : 00; + 0120 : 1C; + 0121 : 58; + 0122 : 60; + 0123 : A9; + 0124 : 00; + 0125 : 8D; + 0126 : 6C; + 0127 : 02; + 0128 : 8D; + 0129 : 6D; + 012A : 02; + 012B : 60; + 012C : 78; + 012D : 8A; + 012E : 48; + 012F : A9; + 0130 : 50; + 0131 : 8D; + 0132 : 6C; + 0133 : 02; + 0134 : A2; + 0135 : 00; + 0136 : BD; + 0137 : CA; + 0138 : FE; + 0139 : 8D; + 013A : 6D; + 013B : 02; + 013C : 0D; + 013D : 00; + 013E : 1C; + 013F : 8D; + 0140 : 00; + 0141 : 1C; + 0142 : 68; + 0143 : AA; + 0144 : 58; + 0145 : 60; + 0146 : A9; + 0147 : 00; + 0148 : 8D; + 0149 : F9; + 014A : 02; + 014B : AD; + 014C : 8E; + 014D : 02; + 014E : 85; + 014F : 7F; + 0150 : 20; + 0151 : BC; + 0152 : E6; + 0153 : A5; + 0154 : 84; + 0155 : 10; + 0156 : 09; + 0157 : 29; + 0158 : 0F; + 0159 : C9; + 015A : 0F; + 015B : F0; + 015C : 03; + 015D : 4C; + 015E : B4; + 015F : D7; + 0160 : 20; + 0161 : B3; + 0162 : C2; + 0163 : B1; + 0164 : A3; + 0165 : 8D; + 0166 : 75; + 0167 : 02; + 0168 : A2; + 0169 : 0B; + 016A : BD; + 016B : 89; + 016C : FE; + 016D : CD; + 016E : 75; + 016F : 02; + 0170 : F0; + 0171 : 08; + 0172 : CA; + 0173 : 10; + 0174 : F5; + 0175 : A9; + 0176 : 31; + 0177 : 4C; + 0178 : C8; + 0179 : C1; + 017A : 8E; + 017B : 2A; + 017C : 02; + 017D : E0; + 017E : 09; + 017F : 90; + 0180 : 03; + 0181 : 20; + 0182 : EE; + 0183 : C1; + 0184 : AE; + 0185 : 2A; + 0186 : 02; + 0187 : BD; + 0188 : 95; + 0189 : FE; + 018A : 85; + 018B : 6F; + 018C : BD; + 018D : A1; + 018E : FE; + 018F : 85; + 0190 : 70; + 0191 : 6C; + 0192 : 6F; + 0193 : 00; + 0194 : A9; + 0195 : 00; + 0196 : 8D; + 0197 : F9; + 0198 : 02; + 0199 : AD; + 019A : 6C; + 019B : 02; + 019C : D0; + 019D : 2A; + 019E : A0; + 019F : 00; + 01A0 : 98; + 01A1 : 84; + 01A2 : 80; + 01A3 : 84; + 01A4 : 81; + 01A5 : 84; + 01A6 : A3; + 01A7 : 20; + 01A8 : C7; + 01A9 : E6; + 01AA : 20; + 01AB : 23; + 01AC : C1; + 01AD : A5; + 01AE : 7F; + 01AF : 8D; + 01B0 : 8E; + 01B1 : 02; + 01B2 : AA; + 01B3 : A9; + 01B4 : 00; + 01B5 : 95; + 01B6 : FF; + 01B7 : 20; + 01B8 : BD; + 01B9 : C1; + 01BA : 4C; + 01BB : DA; + 01BC : D4; + 01BD : A0; + 01BE : 28; + 01BF : A9; + 01C0 : 00; + 01C1 : 99; + 01C2 : 00; + 01C3 : 02; + 01C4 : 88; + 01C5 : 10; + 01C6 : FA; + 01C7 : 60; + 01C8 : A0; + 01C9 : 00; + 01CA : 84; + 01CB : 80; + 01CC : 84; + 01CD : 81; + 01CE : 4C; + 01CF : 45; + 01D0 : E6; + 01D1 : A2; + 01D2 : 00; + 01D3 : 8E; + 01D4 : 7A; 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+ 3EAD : 51; + 3EAE : DD; + 3EAF : 1C; + 3EB0 : 9E; + 3EB1 : 1C; + 3EB2 : 52; + 3EB3 : 57; + 3EB4 : 41; + 3EB5 : 4D; + 3EB6 : 44; + 3EB7 : 53; + 3EB8 : 50; + 3EB9 : 55; + 3EBA : 4C; + 3EBB : 44; + 3EBC : 53; + 3EBD : 50; + 3EBE : 55; + 3EBF : 52; + [3EC0..3EC1] : 45; + 3EC2 : 52; + 3EC3 : 53; + 3EC4 : 45; + 3EC5 : 4C; + 3EC6 : 51; + 3EC7 : 47; + 3EC8 : 52; + 3EC9 : 4C; + 3ECA : 08; + [3ECB..3ECC] : 00; + 3ECD : 3F; + 3ECE : 7F; + 3ECF : BF; + 3ED0 : FF; + 3ED1 : 11; + 3ED2 : 12; + 3ED3 : 13; + 3ED4 : 15; + 3ED5 : 41; + 3ED6 : 04; + 3ED7 : 24; + 3ED8 : 1F; + 3ED9 : 19; + 3EDA : 12; + 3EDB : 01; + [3EDC..3EDD] : FF; + 3EDE : 01; + 3EDF : 00; + 3EE0 : 03; + 3EE1 : 04; + 3EE2 : 05; + 3EE3 : 06; + [3EE4..3EE5] : 07; + 3EE6 : EC; + 3EE7 : 6C; + 3EE8 : 65; + 3EE9 : 00; + 3EEA : 8D; + 3EEB : 00; + 3EEC : 1C; + 3EED : 8D; + 3EEE : 02; + 3EEF : 1C; + 3EF0 : 4C; + 3EF1 : 7D; + 3EF2 : EA; + 3EF3 : 8A; + 3EF4 : A2; + 3EF5 : 05; + 3EF6 : CA; + 3EF7 : D0; + 3EF8 : FD; + 3EF9 : AA; + 3EFA : 60; + 3EFB : 20; + 3EFC : AE; + 3EFD : E9; + 3EFE : 4C; + 3EFF : 9C; + 3F00 : E9; + 3F01 : AD; + [3F02..3F03] : 02; + 3F04 : C9; + 3F05 : 2D; + 3F06 : F0; + 3F07 : 05; + 3F08 : 38; + 3F09 : E9; + 3F0A : 2B; + 3F0B : D0; + 3F0C : DA; + 3F0D : 85; + 3F0E : 23; + 3F0F : 60; + 3F10 : 8E; + 3F11 : 03; + 3F12 : 18; + 3F13 : A9; + 3F14 : 02; + 3F15 : 8D; + 3F16 : 00; + 3F17 : 18; + 3F18 : A9; + 3F19 : 1A; + 3F1A : 8D; + 3F1B : 02; + 3F1C : 18; + 3F1D : 4C; + 3F1E : A7; + 3F1F : EA; + 3F20 : AD; + 3F21 : 00; + 3F22 : 18; + 3F23 : 29; + 3F24 : 01; + 3F25 : D0; + 3F26 : F9; + 3F27 : A9; + 3F28 : 01; + 3F29 : 8D; + 3F2A : 05; + 3F2B : 18; + 3F2C : 4C; + 3F2D : DF; + 3F2E : E9; + 3F2F : A9; + 3F30 : FF; + 3F31 : 85; + 3F32 : 51; + 3F33 : 4C; + 3F34 : C6; + 3F35 : C8; + [3F36..3FE5] : AA; + 3FE6 : C6; + 3FE7 : C8; + 3FE8 : 8F; + 3FE9 : F9; + 3FEA : 5F; + 3FEB : CD; + 3FEC : 97; + 3FED : CD; + 3FEE : 00; + 3FEF : 05; + 3FF0 : 03; + 3FF1 : 05; + 3FF2 : 06; + 3FF3 : 05; + 3FF4 : 09; + 3FF5 : 05; + 3FF6 : 0C; + 3FF7 : 05; + 3FF8 : 0F; + 3FF9 : 05; + 3FFA : 01; + 3FFB : FF; + 3FFC : A0; + 3FFD : EA; + 3FFE : 67; + 3FFF : FE; +END; diff --git a/Commodore - 64_Mist/rtl/roms/std_C64.mif b/Commodore - 64_Mist/rtl/roms/std_C64.mif new file mode 100644 index 00000000..9ab99201 --- /dev/null +++ b/Commodore - 64_Mist/rtl/roms/std_C64.mif @@ -0,0 +1,16169 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=16384; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0000 : 94; + 0001 : E3; + 0002 : 7B; + 0003 : E3; + 0004 : 43; + 0005 : 42; + 0006 : 4D; + 0007 : 42; + 0008 : 41; + 0009 : 53; + 000A : 49; + 000B : 43; + 000C : 30; + 000D : A8; + 000E : 41; + 000F : A7; + 0010 : 1D; + 0011 : AD; + 0012 : F7; + 0013 : A8; + 0014 : A4; + 0015 : AB; + 0016 : BE; + 0017 : AB; + 0018 : 80; + 0019 : B0; + 001A : 05; + 001B : AC; + 001C : A4; + 001D : A9; + 001E : 9F; + 001F : A8; + 0020 : 70; + 0021 : A8; + 0022 : 27; + 0023 : A9; + 0024 : 1C; + 0025 : A8; + 0026 : 82; + 0027 : A8; + 0028 : D1; + 0029 : A8; + 002A : 3A; + 002B : A9; + 002C : 2E; + 002D : A8; + 002E : 4A; + 002F : A9; + 0030 : 2C; + 0031 : B8; + 0032 : 67; + 0033 : E1; + 0034 : 55; + 0035 : E1; + 0036 : 64; + 0037 : E1; + 0038 : B2; + 0039 : B3; + 003A : 23; + 003B : B8; + 003C : 7F; + 003D : AA; + 003E : 9F; + 003F : AA; + 0040 : 56; + 0041 : A8; + 0042 : 9B; + 0043 : A6; + 0044 : 5D; + 0045 : A6; + 0046 : 85; + 0047 : AA; + 0048 : 29; + 0049 : E1; + 004A : BD; + 004B : E1; + 004C : C6; + 004D : E1; + 004E : 7A; + 004F : AB; + 0050 : 41; + 0051 : A6; + 0052 : 39; + 0053 : BC; + 0054 : CC; + 0055 : BC; + 0056 : 58; + 0057 : BC; + 0058 : 10; + 0059 : 03; + 005A : 7D; + 005B : B3; + 005C : 9E; + 005D : B3; + 005E : 71; + 005F : BF; + 0060 : 97; + 0061 : E0; + 0062 : EA; + 0063 : B9; + 0064 : ED; + 0065 : BF; + 0066 : 64; + 0067 : E2; + 0068 : 6B; + 0069 : E2; + 006A : B4; + 006B : E2; + 006C : 0E; + 006D : E3; + 006E : 0D; + 006F : B8; + 0070 : 7C; + 0071 : B7; + 0072 : 65; + 0073 : B4; + 0074 : AD; + 0075 : B7; + 0076 : 8B; + 0077 : B7; + 0078 : EC; + 0079 : B6; + 007A : 00; + 007B : B7; + 007C : 2C; + 007D : B7; + 007E : 37; + 007F : B7; + 0080 : 79; + 0081 : 69; + 0082 : B8; + 0083 : 79; + 0084 : 52; + 0085 : B8; + 0086 : 7B; + 0087 : 2A; + 0088 : BA; + 0089 : 7B; + 008A : 11; + 008B : BB; + 008C : 7F; + 008D : 7A; + 008E : BF; + 008F : 50; + 0090 : E8; + 0091 : AF; + 0092 : 46; + 0093 : E5; + 0094 : AF; + 0095 : 7D; + 0096 : B3; + 0097 : BF; + 0098 : 5A; + 0099 : D3; + 009A : AE; + 009B : 64; + 009C : 15; + 009D : B0; + 009E : 45; + 009F : 4E; + 00A0 : C4; + 00A1 : 46; + 00A2 : 4F; + 00A3 : D2; + 00A4 : 4E; + 00A5 : 45; + 00A6 : 58; + 00A7 : D4; + 00A8 : 44; + 00A9 : 41; + 00AA : 54; + 00AB : C1; + 00AC : 49; + 00AD : 4E; + 00AE : 50; + 00AF : 55; + 00B0 : 54; + 00B1 : A3; + 00B2 : 49; + 00B3 : 4E; + 00B4 : 50; + 00B5 : 55; + 00B6 : D4; + 00B7 : 44; + 00B8 : 49; + 00B9 : CD; + 00BA : 52; + 00BB : 45; + 00BC : 41; + 00BD : C4; + 00BE : 4C; + 00BF : 45; + 00C0 : D4; + 00C1 : 47; + 00C2 : 4F; + 00C3 : 54; + 00C4 : CF; + 00C5 : 52; + 00C6 : 55; + 00C7 : CE; + 00C8 : 49; + 00C9 : C6; + 00CA : 52; + 00CB : 45; + 00CC : 53; + 00CD : 54; + 00CE : 4F; + 00CF : 52; + 00D0 : C5; + 00D1 : 47; + 00D2 : 4F; + 00D3 : 53; + 00D4 : 55; + 00D5 : C2; + 00D6 : 52; + 00D7 : 45; + 00D8 : 54; + 00D9 : 55; + 00DA : 52; + 00DB : CE; + 00DC : 52; + 00DD : 45; + 00DE : CD; + 00DF : 53; + 00E0 : 54; + 00E1 : 4F; + 00E2 : D0; + 00E3 : 4F; + 00E4 : CE; + 00E5 : 57; + 00E6 : 41; + 00E7 : 49; + 00E8 : D4; + 00E9 : 4C; + 00EA : 4F; + 00EB : 41; + 00EC : C4; + 00ED : 53; + 00EE : 41; + 00EF : 56; + 00F0 : C5; + 00F1 : 56; + 00F2 : 45; + 00F3 : 52; + 00F4 : 49; + 00F5 : 46; + 00F6 : D9; + 00F7 : 44; + 00F8 : 45; + 00F9 : C6; + 00FA : 50; + 00FB : 4F; + 00FC : 4B; + 00FD : C5; + 00FE : 50; + 00FF : 52; + 0100 : 49; + 0101 : 4E; + 0102 : 54; + 0103 : A3; + 0104 : 50; + 0105 : 52; + 0106 : 49; + 0107 : 4E; + 0108 : D4; + 0109 : 43; + 010A : 4F; + 010B : 4E; + 010C : D4; + 010D : 4C; + 010E : 49; + 010F : 53; + 0110 : D4; + 0111 : 43; + 0112 : 4C; + 0113 : D2; + 0114 : 43; + 0115 : 4D; + 0116 : C4; + 0117 : 53; + 0118 : 59; + 0119 : D3; + 011A : 4F; + 011B : 50; + 011C : 45; + 011D : CE; + 011E : 43; + 011F : 4C; + 0120 : 4F; + 0121 : 53; + 0122 : C5; + 0123 : 47; + 0124 : 45; + 0125 : D4; + 0126 : 4E; + 0127 : 45; + 0128 : D7; + 0129 : 54; + 012A : 41; + 012B : 42; + 012C : A8; + 012D : 54; + 012E : CF; + 012F : 46; + 0130 : CE; + 0131 : 53; + 0132 : 50; + 0133 : 43; + 0134 : A8; + 0135 : 54; + 0136 : 48; + 0137 : 45; + 0138 : CE; + 0139 : 4E; + 013A : 4F; + 013B : D4; + 013C : 53; + 013D : 54; + 013E : 45; + 013F : D0; + 0140 : AB; + 0141 : AD; + 0142 : AA; + 0143 : AF; + 0144 : DE; + 0145 : 41; + 0146 : 4E; + 0147 : C4; + 0148 : 4F; + 0149 : D2; + 014A : BE; + 014B : BD; + 014C : BC; + 014D : 53; + 014E : 47; + 014F : CE; + 0150 : 49; + 0151 : 4E; + 0152 : D4; + 0153 : 41; + 0154 : 42; + 0155 : D3; + 0156 : 55; + 0157 : 53; + 0158 : D2; + 0159 : 46; + 015A : 52; + 015B : C5; + 015C : 50; + 015D : 4F; + 015E : D3; + 015F : 53; + 0160 : 51; + 0161 : D2; + 0162 : 52; + 0163 : 4E; + 0164 : C4; + 0165 : 4C; + 0166 : 4F; + 0167 : C7; + 0168 : 45; + 0169 : 58; + 016A : D0; + 016B : 43; + 016C : 4F; + 016D : D3; + 016E : 53; + 016F : 49; + 0170 : CE; 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+ 01BF : 50; + 01C0 : 45; + 01C1 : CE; + 01C2 : 46; + 01C3 : 49; + 01C4 : 4C; + 01C5 : 45; + 01C6 : 20; + 01C7 : 4E; + 01C8 : 4F; + 01C9 : 54; + 01CA : 20; + 01CB : 46; + 01CC : 4F; + 01CD : 55; + 01CE : 4E; + 01CF : C4; + 01D0 : 44; + 01D1 : 45; + 01D2 : 56; + 01D3 : 49; + 01D4 : 43; + 01D5 : 45; + 01D6 : 20; + 01D7 : 4E; + 01D8 : 4F; + 01D9 : 54; + 01DA : 20; + 01DB : 50; + 01DC : 52; + 01DD : 45; + 01DE : 53; + 01DF : 45; + 01E0 : 4E; + 01E1 : D4; + 01E2 : 4E; + 01E3 : 4F; + 01E4 : 54; + 01E5 : 20; + 01E6 : 49; + 01E7 : 4E; + 01E8 : 50; + 01E9 : 55; + 01EA : 54; + 01EB : 20; + 01EC : 46; + 01ED : 49; + 01EE : 4C; + 01EF : C5; + 01F0 : 4E; + 01F1 : 4F; + 01F2 : 54; + 01F3 : 20; + 01F4 : 4F; + 01F5 : 55; + 01F6 : 54; + 01F7 : 50; + 01F8 : 55; + 01F9 : 54; + 01FA : 20; + 01FB : 46; + 01FC : 49; + 01FD : 4C; + 01FE : C5; + 01FF : 4D; + 0200 : 49; + [0201..0202] : 53; + 0203 : 49; + 0204 : 4E; + 0205 : 47; + 0206 : 20; + 0207 : 46; + 0208 : 49; + 0209 : 4C; + 020A : 45; + 020B : 20; + 020C : 4E; + 020D : 41; + 020E : 4D; + 020F : C5; + 0210 : 49; + [0211..0212] : 4C; + 0213 : 45; + 0214 : 47; + 0215 : 41; + 0216 : 4C; + 0217 : 20; + 0218 : 44; + 0219 : 45; + 021A : 56; + 021B : 49; + 021C : 43; + 021D : 45; + 021E : 20; + 021F : 4E; + 0220 : 55; + 0221 : 4D; + 0222 : 42; + 0223 : 45; + 0224 : D2; + 0225 : 4E; + 0226 : 45; + 0227 : 58; + 0228 : 54; + 0229 : 20; + 022A : 57; + 022B : 49; + 022C : 54; + 022D : 48; + 022E : 4F; + 022F : 55; + 0230 : 54; + 0231 : 20; + 0232 : 46; + 0233 : 4F; + 0234 : D2; + 0235 : 53; + 0236 : 59; + 0237 : 4E; + 0238 : 54; + 0239 : 41; + 023A : D8; + 023B : 52; + 023C : 45; + 023D : 54; + 023E : 55; + 023F : 52; + 0240 : 4E; + 0241 : 20; + 0242 : 57; + 0243 : 49; + 0244 : 54; + 0245 : 48; + 0246 : 4F; + 0247 : 55; + 0248 : 54; + 0249 : 20; + 024A : 47; + 024B : 4F; + 024C : 53; + 024D : 55; + 024E : C2; + 024F : 4F; + 0250 : 55; + 0251 : 54; + 0252 : 20; + 0253 : 4F; + 0254 : 46; + 0255 : 20; + 0256 : 44; + 0257 : 41; + 0258 : 54; + 0259 : C1; + 025A : 49; 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+ 3F49 : 8A; + 3F4A : 48; + 3F4B : 98; + 3F4C : 48; + 3F4D : BA; + 3F4E : BD; + 3F4F : 04; + 3F50 : 01; + 3F51 : 29; + 3F52 : 10; + 3F53 : F0; + 3F54 : 03; + 3F55 : 6C; + 3F56 : 16; + 3F57 : 03; + 3F58 : 6C; + 3F59 : 14; + 3F5A : 03; + 3F5B : 20; + 3F5C : 18; + 3F5D : E5; + 3F5E : AD; + 3F5F : 12; + [3F60..3F61] : D0; + 3F62 : FB; + 3F63 : AD; + 3F64 : 19; + 3F65 : D0; + 3F66 : 29; + 3F67 : 01; + 3F68 : 8D; + 3F69 : A6; + 3F6A : 02; + 3F6B : 4C; + 3F6C : DD; + 3F6D : FD; + 3F6E : A9; + 3F6F : 81; + 3F70 : 8D; + 3F71 : 0D; + 3F72 : DC; + 3F73 : AD; + 3F74 : 0E; + 3F75 : DC; + 3F76 : 29; + 3F77 : 80; + 3F78 : 09; + 3F79 : 11; + 3F7A : 8D; + 3F7B : 0E; + 3F7C : DC; + 3F7D : 4C; + 3F7E : 8E; + 3F7F : EE; + 3F80 : 03; + 3F81 : 4C; + 3F82 : 5B; + 3F83 : FF; + 3F84 : 4C; + 3F85 : A3; + 3F86 : FD; + 3F87 : 4C; + 3F88 : 50; + 3F89 : FD; + 3F8A : 4C; + 3F8B : 15; + 3F8C : FD; + 3F8D : 4C; + 3F8E : 1A; + 3F8F : FD; + 3F90 : 4C; + 3F91 : 18; + 3F92 : FE; + 3F93 : 4C; + 3F94 : B9; + 3F95 : ED; + 3F96 : 4C; + 3F97 : C7; + 3F98 : ED; + 3F99 : 4C; + 3F9A : 25; + 3F9B : FE; + 3F9C : 4C; + 3F9D : 34; + 3F9E : FE; + 3F9F : 4C; + 3FA0 : 87; + 3FA1 : EA; + 3FA2 : 4C; + 3FA3 : 21; + 3FA4 : FE; + 3FA5 : 4C; + 3FA6 : 13; + 3FA7 : EE; + 3FA8 : 4C; + 3FA9 : DD; + 3FAA : ED; + 3FAB : 4C; + 3FAC : EF; + 3FAD : ED; + 3FAE : 4C; + 3FAF : FE; + 3FB0 : ED; + 3FB1 : 4C; + 3FB2 : 0C; + 3FB3 : ED; + 3FB4 : 4C; + 3FB5 : 09; + 3FB6 : ED; + 3FB7 : 4C; + 3FB8 : 07; + 3FB9 : FE; + 3FBA : 4C; + 3FBB : 00; + 3FBC : FE; + 3FBD : 4C; + 3FBE : F9; + 3FBF : FD; + 3FC0 : 6C; + 3FC1 : 1A; + 3FC2 : 03; + 3FC3 : 6C; + 3FC4 : 1C; + 3FC5 : 03; + 3FC6 : 6C; + 3FC7 : 1E; + 3FC8 : 03; + 3FC9 : 6C; + 3FCA : 20; + 3FCB : 03; + 3FCC : 6C; + 3FCD : 22; + 3FCE : 03; + 3FCF : 6C; + 3FD0 : 24; + 3FD1 : 03; + 3FD2 : 6C; + 3FD3 : 26; + 3FD4 : 03; + 3FD5 : 4C; + 3FD6 : 9E; + 3FD7 : F4; + 3FD8 : 4C; + 3FD9 : DD; + 3FDA : F5; + 3FDB : 4C; + 3FDC : E4; + 3FDD : F6; + 3FDE : 4C; + 3FDF : DD; + 3FE0 : F6; + 3FE1 : 6C; + 3FE2 : 28; + 3FE3 : 03; + 3FE4 : 6C; + 3FE5 : 2A; + 3FE6 : 03; + 3FE7 : 6C; + 3FE8 : 2C; + 3FE9 : 03; + 3FEA : 4C; + 3FEB : 9B; + 3FEC : F6; + 3FED : 4C; + 3FEE : 05; + 3FEF : E5; + 3FF0 : 4C; + 3FF1 : 0A; + 3FF2 : E5; + 3FF3 : 4C; + 3FF4 : 00; + 3FF5 : E5; + [3FF6..3FF7] : 52; + 3FF8 : 42; + 3FF9 : 59; + 3FFA : 43; + 3FFB : FE; + 3FFC : E2; + 3FFD : FC; + 3FFE : 48; + 3FFF : FF; +END; diff --git a/Commodore - 64_Mist/rtl/roms/std_C64GS.mif b/Commodore - 64_Mist/rtl/roms/std_C64GS.mif new file mode 100644 index 00000000..5bffbfe2 --- /dev/null +++ b/Commodore - 64_Mist/rtl/roms/std_C64GS.mif @@ -0,0 +1,15800 @@ +-- Copyright (C) 2017 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel MegaCore Function License Agreement, or other +-- applicable license agreement, including, without limitation, +-- that your use is for the sole purpose of programming logic +-- devices manufactured by Intel and sold by Intel or its +-- authorized distributors. Please refer to the applicable +-- agreement for further details. + +-- Quartus Prime generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=16384; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0000 : 94; + 0001 : E3; + 0002 : 7B; + 0003 : E3; + 0004 : 43; + 0005 : 42; + 0006 : 4D; + 0007 : 42; + 0008 : 41; + 0009 : 53; + 000A : 49; + 000B : 43; + 000C : 30; + 000D : A8; + 000E : 41; + 000F : A7; + 0010 : 1D; + 0011 : AD; + 0012 : F7; + 0013 : A8; + 0014 : A4; + 0015 : AB; + 0016 : BE; + 0017 : AB; + 0018 : 80; + 0019 : B0; + 001A : 05; + 001B : AC; + 001C : A4; + 001D : A9; + 001E : 9F; + 001F : A8; + 0020 : 70; + 0021 : A8; + 0022 : 27; + 0023 : A9; + 0024 : 1C; + 0025 : A8; + 0026 : 82; + 0027 : A8; + 0028 : D1; + 0029 : A8; + 002A : 3A; + 002B : A9; + 002C : 2E; + 002D : A8; + 002E : 4A; + 002F : A9; + 0030 : 2C; + 0031 : B8; + 0032 : 67; + 0033 : E1; + 0034 : 55; + 0035 : E1; + 0036 : 64; + 0037 : E1; + 0038 : B2; + 0039 : B3; + 003A : 23; + 003B : B8; + 003C : 7F; + 003D : AA; + 003E : 9F; + 003F : AA; + 0040 : 56; + 0041 : A8; + 0042 : 9B; + 0043 : A6; + 0044 : 5D; + 0045 : A6; + 0046 : 85; + 0047 : AA; + 0048 : 29; + 0049 : E1; + 004A : BD; + 004B : E1; + 004C : C6; + 004D : E1; + 004E : 7A; + 004F : AB; + 0050 : 41; + 0051 : A6; + 0052 : 39; + 0053 : BC; + 0054 : CC; + 0055 : BC; + 0056 : 58; + 0057 : BC; + 0058 : 10; + 0059 : 03; + 005A : 7D; + 005B : B3; + 005C : 9E; + 005D : B3; + 005E : 71; + 005F : BF; + 0060 : 97; + 0061 : E0; + 0062 : EA; + 0063 : B9; + 0064 : ED; + 0065 : BF; + 0066 : 64; + 0067 : E2; + 0068 : 6B; + 0069 : E2; + 006A : B4; + 006B : E2; + 006C : 0E; + 006D : E3; + 006E : 0D; + 006F : B8; + 0070 : 7C; + 0071 : B7; + 0072 : 65; + 0073 : B4; + 0074 : AD; + 0075 : B7; + 0076 : 8B; + 0077 : B7; + 0078 : EC; + 0079 : B6; + 007A : 00; + 007B : B7; + 007C : 2C; + 007D : B7; + 007E : 37; + 007F : B7; + 0080 : 79; + 0081 : 69; + 0082 : B8; + 0083 : 79; + 0084 : 52; + 0085 : B8; + 0086 : 7B; + 0087 : 2A; + 0088 : BA; + 0089 : 7B; + 008A : 11; + 008B : BB; + 008C : 7F; + 008D : 7A; + 008E : BF; + 008F : 50; + 0090 : E8; + 0091 : AF; + 0092 : 46; + 0093 : E5; + 0094 : AF; + 0095 : 7D; + 0096 : B3; + 0097 : BF; + 0098 : 5A; + 0099 : D3; + 009A : AE; + 009B : 64; + 009C : 15; + 009D : B0; + 009E : 45; + 009F : 4E; + 00A0 : C4; + 00A1 : 46; + 00A2 : 4F; + 00A3 : D2; + 00A4 : 4E; + 00A5 : 45; + 00A6 : 58; + 00A7 : D4; + 00A8 : 44; + 00A9 : 41; + 00AA : 54; + 00AB : C1; + 00AC : 49; + 00AD : 4E; + 00AE : 50; + 00AF : 55; + 00B0 : 54; + 00B1 : A3; + 00B2 : 49; + 00B3 : 4E; + 00B4 : 50; + 00B5 : 55; + 00B6 : D4; + 00B7 : 44; + 00B8 : 49; + 00B9 : CD; + 00BA : 52; + 00BB : 45; + 00BC : 41; + 00BD : C4; + 00BE : 4C; + 00BF : 45; + 00C0 : D4; + 00C1 : 47; + 00C2 : 4F; + 00C3 : 54; + 00C4 : CF; + 00C5 : 52; + 00C6 : 55; + 00C7 : CE; + 00C8 : 49; + 00C9 : C6; + 00CA : 52; + 00CB : 45; + 00CC : 53; + 00CD : 54; + 00CE : 4F; + 00CF : 52; + 00D0 : C5; + 00D1 : 47; + 00D2 : 4F; + 00D3 : 53; + 00D4 : 55; + 00D5 : C2; + 00D6 : 52; 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+ [3FF6..3FF7] : 52; + 3FF8 : 42; + 3FF9 : 59; + 3FFA : 43; + 3FFB : FE; + 3FFC : E2; + 3FFD : FC; + 3FFE : 48; + 3FFF : FF; +END; diff --git a/Commodore - 64_Mist/rtl/scandoubler.v b/Commodore - 64_Mist/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Commodore - 64_Mist/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Commodore - 64_Mist/rtl/sd_card.sv b/Commodore - 64_Mist/rtl/sd_card.sv new file mode 100644 index 00000000..41eafaba --- /dev/null +++ b/Commodore - 64_Mist/rtl/sd_card.sv @@ -0,0 +1,142 @@ +// +// sd_card.v +// +// Copyright (c) 2016 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the Lesser GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// +///////////////////////////////////////////////////////////////////////// + +module sd_card +( + input clk, + input reset, + + output [31:0] sd_lba, + output reg sd_rd, + output reg sd_wr, + input sd_ack, + input sd_ack_conf, + output sd_conf, + output sd_sdhc, + + input [8:0] sd_buff_addr, + input [7:0] sd_buff_dout, + output [7:0] sd_buff_din, + input sd_buff_wr, + + input save_track, + input change, + input [5:0] track, + input [4:0] sector, + input [7:0] buff_addr, + output [7:0] buff_dout, + input [7:0] buff_din, + input buff_we, + output reg busy +); + +assign sd_lba = lba; +assign sd_conf = 0; +assign sd_sdhc = 1; + +trkbuf buffer +( + .clock(~clk), + + .address_a(sd_buff_base + base_fix + sd_buff_addr), + .data_a(sd_buff_dout), + .wren_a(sd_ack & sd_buff_wr), + .q_a(sd_buff_din), + + .address_b({sector, buff_addr}), + .data_b(buff_din), + .wren_b(buff_we), + .q_b(buff_dout) +); + +wire [9:0] start_sectors[41] = + '{ 0, 0, 21, 42, 63, 84,105,126,147,168,189,210,231,252,273,294,315,336,357,376,395, + 414,433,452,471,490,508,526,544,562,580,598,615,632,649,666,683,700,717,734,751}; + +reg [31:0] lba; +reg [12:0] base_fix; +reg [12:0] sd_buff_base; + +always @(posedge clk) begin + reg [5:0] ack; + reg [5:0] cur_track = 0; + reg old_change, ready = 0; + reg saving = 0; + + old_change <= change; + if(~old_change & change) ready <= 1; + + ack <= {ack[4:0], sd_ack}; + if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0; + + if(reset) begin + cur_track <= 'b111111; + busy <= 0; + sd_rd <= 0; + sd_wr <= 0; + saving<= 0; + end + + else + if(busy) begin + if(ack[5:4] == 2'b10) begin + if(sd_buff_base < 'h1800) begin + sd_buff_base <= sd_buff_base + 13'd512; + lba <= lba + 1'd1; + if(saving) sd_wr <= 1; + else sd_rd <= 1; + end + else + if(saving && (cur_track != track)) begin + saving <= 0; + cur_track <= track; + sd_buff_base <= 0; + base_fix <= start_sectors[track][0] ? 13'h1F00 : 13'h0000; + lba <= start_sectors[track][9:1]; + sd_rd <= 1; + end else begin + busy <= 0; + end + end + end + else + if(ready) begin + if(save_track && cur_track != 'b111111) begin + saving <= 1; + sd_buff_base <= 0; + lba <= start_sectors[cur_track][9:1]; + sd_wr <= 1; + busy <= 1; + end + else + if((cur_track != track) || (old_change && ~change)) begin + saving <= 0; + cur_track <= track; + sd_buff_base <= 0; + base_fix <= start_sectors[track][0] ? 13'h1F00 : 13'h0000; + lba <= start_sectors[track][9:1]; + sd_rd <= 1; + busy <= 1; + end + end +end + +endmodule diff --git a/Commodore - 64_Mist/rtl/sdram.v b/Commodore - 64_Mist/rtl/sdram.v new file mode 100644 index 00000000..f8497d55 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sdram.v @@ -0,0 +1,147 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2013 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + output [12:0] sd_addr, // 13 bit multiplexed address bus + output [1:0] sd_ba, // two banks + output sd_cs, // a single chip select + output sd_we, // write enable + output sd_ras, // row address select + output sd_cas, // columns address select + + // cpu/chipset interface + input init, // init signal after FPGA config to initialize RAM + input clk, // sdram is accessed at up to 128MHz + +// input [15:0] addr, // 25 bit byte address + input [24:0] addr, // 25 bit byte address + input refresh, // refresh cycle + input ce, // cpu/chipset access + input we // cpu/chipset requests write +); + +// no burst configured +localparam RASCAS_DELAY = 3'd2; // tRCD>=20ns -> 2 cycles@64MHz +localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +localparam STATE_IDLE = 3'd0; // first state in cycle +localparam STATE_CMD_START = 3'd1; // state in which a new command can be started +localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued +localparam STATE_LAST = 3'd7; // last state in cycle + +reg [2:0] q /* synthesis noprune */; +reg last_ce, last_refresh; +always @(posedge clk) begin + last_ce <= ce; + last_refresh <= refresh; + + // start a new cycle in rising edge of ce or refresh + if((ce && !last_ce) || (refresh && !last_refresh)) + q <= 3'd1; + + if(q != 0) + q <= q + 3'd1; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 clkref cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +always @(posedge clk) begin + if(init) reset <= 5'h1f; + else if((q == STATE_LAST) && (reset != 0)) + reset <= reset - 5'd1; +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram + +// drive control signals according to current command +assign sd_cs = sd_cmd[3]; +assign sd_ras = sd_cmd[2]; +assign sd_cas = sd_cmd[1]; +assign sd_we = sd_cmd[0]; + +// assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ; +// assign dout = sd_data[7:0]; + +always @(posedge clk) begin + sd_cmd <= CMD_INHIBIT; + + if(reset != 0) begin + if(q == STATE_IDLE) begin + if(reset == 13) sd_cmd <= CMD_PRECHARGE; + if(reset == 2) sd_cmd <= CMD_LOAD_MODE; + end + end else begin + if(q == STATE_IDLE) begin + if(ce && !last_ce) sd_cmd <= CMD_ACTIVE; + if(refresh && !last_refresh) sd_cmd <= CMD_AUTO_REFRESH; + end else if((q == STATE_CMD_CONT)&&(!refresh)) begin + if(we) sd_cmd <= CMD_WRITE; + else if(ce) sd_cmd <= CMD_READ; + end + end +end + +wire [12:0] reset_addr = (reset == 13)?13'b0010000000000:MODE; + +wire [12:0] run_addr = +// (q == STATE_CMD_START)?{ 5'b00000, addr[15:8]}:{ 5'b00100, addr[7:0]}; +//(q == STATE_CMD_START)?addr[21:9]:{ 4'b0010, addr[8:0]}; //possibly try this LCA 6mar17 + (q == STATE_CMD_START)?addr[20:8]:{ 4'b0010, addr[23], addr[7:0]}; + +assign sd_addr = (reset != 0)?reset_addr:run_addr; + +//assign sd_ba = 2'b00; +assign sd_ba = addr[22:21]; + +endmodule diff --git a/Commodore - 64_Mist/rtl/sid/Q_table.vhd b/Commodore - 64_Mist/rtl/sid/Q_table.vhd new file mode 100644 index 00000000..61dfd33b --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/Q_table.vhd @@ -0,0 +1,45 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Q_table is +port ( + Q_reg : in unsigned(3 downto 0); + filter_q : out signed(17 downto 0) ); +end Q_table; + +architecture Gideon of Q_table is + + type t_18_bit_array is array(natural range <>) of signed(17 downto 0); + function create_factors(max_Q: real) return t_18_bit_array is + constant critical : real := 0.70710678; -- no resonance at 0.5*sqrt(2) + variable q_step : real; + variable q : real; + variable scaled : real; + variable ret : t_18_bit_array(0 to 15); + begin + q_step := (max_Q - critical) / 15.0; -- linear + for i in 0 to 15 loop + q := critical + (real(i) * q_step); + scaled := 65536.0 / q; + ret(i) := to_signed(integer(scaled), 18); + end loop; + return ret; + end function; + + constant c_table : t_18_bit_array(0 to 15) := create_factors(1.8); +begin + filter_q <= c_table(to_integer(Q_reg)); +end Gideon; diff --git a/Commodore - 64_Mist/rtl/sid/adsr_multi.vhd b/Commodore - 64_Mist/rtl/sid/adsr_multi.vhd new file mode 100644 index 00000000..0387df45 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/adsr_multi.vhd @@ -0,0 +1,220 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.sid_debug_pkg.all; + +-- LUT: 195, FF:68 + +entity adsr_multi is +generic ( + g_num_voices : integer := 8 ); +port ( + clock : in std_logic; + reset : in std_logic; + + voice_i : in unsigned(3 downto 0); + enable_i : in std_logic; + voice_o : out unsigned(3 downto 0); + enable_o : out std_logic; + + gate : in std_logic; + attack : in std_logic_vector(3 downto 0); + decay : in std_logic_vector(3 downto 0); + sustain : in std_logic_vector(3 downto 0); + release : in std_logic_vector(3 downto 0); + + env_state: out std_logic_vector(1 downto 0); -- for testing only + env_out : out unsigned(7 downto 0) ); + +end adsr_multi; + +-- 158 1 62 .. FF +-- 45 2 35 .. 61 +-- 26 4 1C .. 34 +-- 13 8 0D .. 1B +-- 6 16 07 .. 0C +-- 7 30 00 .. 06 + +architecture gideon of adsr_multi is + + type presc_array_t is array(natural range <>) of unsigned(15 downto 0); + constant prescalers : presc_array_t(0 to 15) := ( + X"0008", X"001F", X"003E", X"005E", + X"0094", X"00DB", X"010A", X"0138", + X"0187", X"03D0", X"07A1", X"0C35", + X"0F42", X"2DC7", X"4C4B", X"7A12" ); + + + signal enveloppe : unsigned(7 downto 0) := (others => '0'); + signal state : unsigned(1 downto 0) := (others => '0'); + + constant st_release : unsigned(1 downto 0) := "00"; + constant st_attack : unsigned(1 downto 0) := "01"; + constant st_decay : unsigned(1 downto 0) := "11"; + + type state_array_t is array(natural range <>) of unsigned(29 downto 0); + signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0')); +begin + env_out <= enveloppe; + env_state <= std_logic_vector(state); + + -- FF-5E 01 + -- 5D-37 02 + -- 36-1B 04 + -- 1A-0F 08 + -- 0E-07 10 + -- 06-01 1E + process(clock) + function logarithmic(lev: unsigned(7 downto 0)) return unsigned is + variable res : unsigned(4 downto 0); + begin + if lev = X"00" then + res := "00000"; -- prescaler off + elsif lev < X"07" then + res := "11101"; -- 1E-1 + elsif lev < X"0F" then + res := "01111"; -- 10-1 + elsif lev < X"1B" then + res := "00111"; -- 08-1 + elsif lev < X"37" then + res := "00011"; -- 04-1 + elsif lev < X"5E" then + res := "00001"; -- 02-1 + else + res := "00000"; -- 01-1 + end if; + return res; + end function logarithmic; + + variable presc_select : integer range 0 to 15; + variable cur_state : unsigned(1 downto 0); + variable cur_env : unsigned(7 downto 0); + variable cur_pre15 : unsigned(14 downto 0); + variable cur_pre5 : unsigned(4 downto 0); + variable next_state : unsigned(1 downto 0); + variable next_env : unsigned(7 downto 0); + variable next_pre15 : unsigned(14 downto 0); + variable next_pre5 : unsigned(4 downto 0); + variable presc_val : unsigned(14 downto 0); + variable log_div : unsigned(4 downto 0); + variable do_count_15 : std_logic; + variable do_count_5 : std_logic; + begin + if rising_edge(clock) then + cur_state := state_array(0)(1 downto 0); + cur_env := state_array(0)(9 downto 2); + cur_pre15 := state_array(0)(24 downto 10); + cur_pre5 := state_array(0)(29 downto 25); + + voice_o <= voice_i; + enable_o <= enable_i; + + next_state := cur_state; + next_env := cur_env; + next_pre15 := cur_pre15; + next_pre5 := cur_pre5; + + + -- PRESCALER LOGIC, output: do_count -- + -- 15 bit prescaler select -- + case cur_state is + when st_attack => + presc_select := to_integer(unsigned(attack)); + when st_decay => + presc_select := to_integer(unsigned(decay)); + when others => -- includes release and idle + presc_select := to_integer(unsigned(release)); + end case; + presc_val := prescalers(presc_select)(14 downto 0); + + -- 15 bit prescaler counter -- + do_count_15 := '0'; + if cur_pre15 = presc_val then + next_pre15 := (others => '0'); + do_count_15 := '1'; + else + next_pre15 := cur_pre15 + 1; + end if; + + -- 5 bit prescaler -- + log_div := logarithmic(cur_env); + do_count_5 := '0'; + if do_count_15='1' then + if (cur_state = st_attack) or cur_pre5 = log_div then + next_pre5 := "00000"; + do_count_5 := '1'; + else + next_pre5 := cur_pre5 + 1; + end if; + end if; + -- END PRESCALER LOGIC -- + + case cur_state is + + when st_attack => + if gate = '0' then + next_state := st_release; + elsif cur_env = X"FF" then + next_state := st_decay; + end if; + + if do_count_15='1' then + next_env := cur_env + 1; +-- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!! +-- next_state := st_decay; +-- end if; + end if; + + when st_decay => + if gate = '0' then + next_state := st_release; + end if; + + if do_count_15='1' and do_count_5='1' and + std_logic_vector(cur_env) /= (sustain & sustain) and + cur_env /= X"00" then + next_env := cur_env - 1; + end if; + + when st_release => + if gate = '1' then + next_state := st_attack; + end if; + + if do_count_15='1' and do_count_5='1' and + cur_env /= X"00" then + next_env := cur_env - 1; + end if; + + when others => + next_state := st_release; + + end case; + + if enable_i='1' then + state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1); + state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state; + enveloppe <= next_env; + state <= next_state; + end if; + + if reset='1' then + state <= "00"; + enveloppe <= (others => '0'); + enable_o <= '0'; + end if; + end if; + end process; +end gideon; diff --git a/Commodore - 64_Mist/rtl/sid/mult_acc.vhd b/Commodore - 64_Mist/rtl/sid/mult_acc.vhd new file mode 100644 index 00000000..fbabfd0a --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/mult_acc.vhd @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.my_math_pkg.all; + +entity mult_acc is +port ( + clock : in std_logic; + reset : in std_logic; + + voice_i : in unsigned(3 downto 0); + enable_i : in std_logic; + voice3_off_l : in std_logic; + voice3_off_r : in std_logic; + + filter_en : in std_logic := '0'; + + enveloppe : in unsigned(7 downto 0); + waveform : in unsigned(11 downto 0); + + -- + osc3 : out std_logic_vector(7 downto 0); + env3 : out std_logic_vector(7 downto 0); + + -- + valid_out : out std_logic; + + direct_out_L : out signed(17 downto 0); + direct_out_R : out signed(17 downto 0); + + filter_out_L : out signed(17 downto 0); + filter_out_R : out signed(17 downto 0) ); +end mult_acc; + +-- architecture unsigned_wave of mult_acc is +-- signal filter_m : std_logic; +-- signal voice_m : unsigned(3 downto 0); +-- signal mult_m : unsigned(19 downto 0); +-- signal accu_f : unsigned(17 downto 0); +-- signal accu_u : unsigned(17 downto 0); +-- signal enable_d : std_logic; +-- signal direct_i : unsigned(17 downto 0); +-- signal filter_i : unsigned(17 downto 0); +-- begin +-- process(clock) +-- variable mult_ext : unsigned(21 downto 0); +-- variable mult_trunc : unsigned(21 downto 4); +-- begin +-- if rising_edge(clock) then +-- -- latch outputs +-- if reset='1' then +-- osc3 <= (others => '0'); +-- env3 <= (others => '0'); +-- elsif voice_i = X"2" then +-- osc3 <= std_logic_vector(waveform(11 downto 4)); +-- env3 <= std_logic_vector(enveloppe); +-- end if; +-- +-- mult_ext := extend(mult_m, mult_ext'length); +-- mult_trunc := mult_ext(mult_trunc'range); +-- filter_m <= filter_en; +-- voice_m <= voice_i; +-- mult_m <= enveloppe * waveform; +-- valid_out <= '0'; +-- enable_d <= enable_i; +-- +-- if enable_d='1' then +-- if voice_m = 0 then +-- valid_out <= '1'; +-- direct_i <= accu_u; +-- filter_i <= accu_f; +-- if filter_m='1' then +-- accu_f <= mult_trunc; +-- accu_u <= (others => '0'); +-- else +-- accu_f <= (others => '0'); +-- accu_u <= mult_trunc; +-- end if; +-- else +-- valid_out <= '0'; +-- if filter_m='1' then +-- accu_f <= sum_limit(accu_f, mult_trunc); +-- else +-- if (voice_m /= 2) or (voice3_off = '0') then +-- accu_u <= sum_limit(accu_u, mult_trunc); +-- end if; +-- end if; +-- end if; +-- end if; +-- +-- if reset = '1' then +-- valid_out <= '0'; +-- accu_u <= (others => '0'); +-- accu_f <= (others => '0'); +-- direct_i <= (others => '0'); +-- filter_i <= (others => '0'); +-- end if; +-- end if; +-- end process; +-- +-- direct_out <= '0' & signed(direct_i(17 downto 1)); +-- filter_out <= '0' & signed(filter_i(17 downto 1)); +-- end unsigned_wave; +-- + +architecture signed_wave of mult_acc is + signal filter_m : std_logic; + signal voice_m : unsigned(3 downto 0); + signal mult_m : signed(20 downto 0); + signal accu_fl : signed(17 downto 0); + signal accu_fr : signed(17 downto 0); + signal accu_ul : signed(17 downto 0); + signal accu_ur : signed(17 downto 0); + signal enable_d : std_logic; +begin + process(clock) + variable mult_ext : signed(21 downto 0); + variable mult_trunc : signed(21 downto 4); + variable env_signed : signed(8 downto 0); + variable wave_signed: signed(11 downto 0); + begin + if rising_edge(clock) then + -- latch outputs + if reset='1' then + osc3 <= (others => '0'); + env3 <= (others => '0'); + elsif voice_i = X"2" then + osc3 <= std_logic_vector(waveform(11 downto 4)); + env3 <= std_logic_vector(enveloppe); + end if; + + env_signed := '0' & signed(enveloppe); + wave_signed := not waveform(11) & signed(waveform(10 downto 0)); + + mult_ext := extend(mult_m, mult_ext'length); + mult_trunc := mult_ext(mult_trunc'range); + filter_m <= filter_en; + voice_m <= voice_i; + mult_m <= env_signed * wave_signed; + valid_out <= '0'; + enable_d <= enable_i; + if enable_d='1' then + if voice_m = 0 then + valid_out <= '1'; + direct_out_l <= accu_ul; + direct_out_r <= accu_ur; + filter_out_l <= accu_fl; + filter_out_r <= accu_fr; + accu_fr <= (others => '0'); + accu_ur <= (others => '0'); + if filter_m='1' then + accu_fl <= mult_trunc; + accu_ul <= (others => '0'); + else + accu_fl <= (others => '0'); + accu_ul <= mult_trunc; + end if; + elsif voice_m(3)='0' then + valid_out <= '0'; + if filter_m='1' then + accu_fl <= sum_limit(accu_fl, mult_trunc); + else + if (voice_m /= 2) or (voice3_off_l = '0') then + accu_ul <= sum_limit(accu_ul, mult_trunc); + end if; + end if; + else -- upper 8 voices go to right + valid_out <= '0'; + if filter_m='1' then + accu_fr <= sum_limit(accu_fr, mult_trunc); + else + if (voice_m /= 10) or (voice3_off_r = '0') then + accu_ur <= sum_limit(accu_ur, mult_trunc); + end if; + end if; + end if; + + end if; + + if reset = '1' then + valid_out <= '0'; + accu_ul <= (others => '0'); + accu_fl <= (others => '0'); + accu_ur <= (others => '0'); + accu_fr <= (others => '0'); + direct_out_l <= (others => '0'); + direct_out_r <= (others => '0'); + filter_out_l <= (others => '0'); + filter_out_r <= (others => '0'); + end if; + end if; + end process; + + +end signed_wave; diff --git a/Commodore - 64_Mist/rtl/sid/my_math_pkg.vhd b/Commodore - 64_Mist/rtl/sid/my_math_pkg.vhd new file mode 100644 index 00000000..40f77fdf --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/my_math_pkg.vhd @@ -0,0 +1,120 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package my_math_pkg is + + function sum_limit(i1, i2 : signed) return signed; + function sub_limit(i1, i2 : signed) return signed; + function sum_limit(i1, i2 : unsigned) return unsigned; + function extend(x : signed; len : natural) return signed; + function extend(x : unsigned; len : natural) return unsigned; + function left_align(x : signed; len : natural) return signed; + function left_scale(x : signed; sh : natural) return signed; + +-- function shift_right(x : signed; positions: natural) return signed; +end; + +package body my_math_pkg is + + function sum_limit(i1, i2 : signed) return signed is + variable o : signed(i1'range); + begin + assert i1'length = i2'length + report "i1 and i2 should have the same length!" + severity failure; + o := i1 + i2; + if (i1(i1'left) = i2(i2'left)) and (o(o'left) /= i1(i1'left)) then + if i1(i1'left)='1' then + o := to_signed(-(2**(o'length-1)), o'length); + else + o := to_signed(2**(o'length-1) - 1, o'length); + end if; + end if; + return o; + end function; + + function sub_limit(i1, i2 : signed) return signed is + variable o : signed(i1'range); + begin + assert i1'length = i2'length + report "i1 and i2 should have the same length!" + severity failure; + o := i1 - i2; + if (i1(i1'left) /= i2(i2'left)) and (o(o'left) /= i1(i1'left)) then + if i1(i1'left)='1' then + o := to_signed(-(2**(o'length-1)), o'length); + else + o := to_signed(2**(o'length-1) - 1, o'length); + end if; + end if; + return o; + end function; + + function sum_limit(i1, i2 : unsigned) return unsigned is + variable o : unsigned(i1'length downto 0); + begin + o := ('0' & i1) + i2; + if o(o'left)='1' then + o := (others => '1'); + end if; + return o(i1'length-1 downto 0); + end function; + + function extend(x : signed; len : natural) return signed is + variable ret : signed(len-1 downto 0); + alias a : signed(x'length-1 downto 0) is x; + begin + ret := (others => x(x'left)); + ret(a'range) := a; + return ret; + end function extend; + + function extend(x : unsigned; len : natural) return unsigned is + variable ret : unsigned(len-1 downto 0); + alias a : unsigned(x'length-1 downto 0) is x; + begin + ret := (others => '0'); + ret(a'range) := a; + return ret; + end function extend; + + function left_align(x : signed; len : natural) return signed is + variable ret : signed(len-1 downto 0); + begin + ret := (others => '0'); + ret(len-1 downto len-x'length) := x; + return ret; + end function left_align; + + function left_scale(x : signed; sh : natural) return signed is + alias a : signed(x'length-1 downto 0) is x; + variable ret : signed(x'length-(1+sh) downto 0); + variable top : signed(sh downto 0); + begin + if sh=0 then + return x; + end if; + + top := a(a'high downto a'high-sh); + if (top = -1) or (top = 0) then -- can shift without getting punished! + ret := a(ret'range); + elsif a(a'high)='1' then -- negative and can't shift, so max neg: + ret := (others => '0'); + ret(ret'high) := '1'; + else -- positive and can't shift, so max pos + ret := (others => '1'); + ret(ret'high) := '0'; + end if; + return ret; + end function left_scale; + +-- function shift_right(x : signed; positions: natural) return signed is +-- alias a : signed(x'length-1 downto 0) is x; +-- variable ret : signed(x'length-1 downto 0); +-- begin +-- ret := (others => x(x'left)); +-- ret(a'left-positions downto 0) := a(a'left downto positions); +-- return ret; +-- end function shift_right; +end; diff --git a/Commodore - 64_Mist/rtl/sid/oscillator.vhd b/Commodore - 64_Mist/rtl/sid/oscillator.vhd new file mode 100644 index 00000000..543cfdcd --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/oscillator.vhd @@ -0,0 +1,92 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity oscillator is +generic ( + g_num_voices : integer := 8); +port ( + clock : in std_logic; + reset : in std_logic; + + enable_i : in std_logic; + voice_i : in unsigned(3 downto 0); + freq : in unsigned(15 downto 0); + test : in std_logic := '0'; + sync : in std_logic := '0'; + + voice_o : out unsigned(3 downto 0); + enable_o : out std_logic; + test_o : out std_logic; + osc_val : out unsigned(23 downto 0); + carry_20 : out std_logic; + msb_other: out std_logic ); + +end oscillator; + + +architecture Gideon of oscillator is + type accu_array_t is array (natural range <>) of unsigned(23 downto 0); + signal accu_reg : accu_array_t(0 to g_num_voices-1) := (others => (others => '0')); + + type int4_array is array (natural range <>) of integer range 0 to 15; + + constant voice_linkage : int4_array(0 to 15) := ( 2, 0, 1, 7, 3, 4, 5, 6, + 10, 8, 9, 15, 11, 12, 13, 14 ); + + signal ring_index : integer range 0 to 15; + signal sync_index : integer range 0 to 15; + signal msb_register : std_logic_vector(0 to 15) := (others => '0'); + signal car_register : std_logic_vector(0 to 15) := (others => '0'); + signal do_sync : std_logic; +begin + sync_index <= voice_linkage(to_integer(voice_i)); + do_sync <= sync and car_register(sync_index); + ring_index <= voice_linkage(to_integer(voice_i)); + + process(clock) + variable cur_accu : unsigned(23 downto 0); + variable new_accu : unsigned(24 downto 0); + variable cur_20 : std_logic; + begin + if rising_edge(clock) then + cur_accu := accu_reg(0); + cur_20 := cur_accu(20); + + if reset='1' or test='1' or do_sync='1' then + new_accu := (others => '0'); + else + new_accu := ('0' & cur_accu) + freq; + end if; + + osc_val <= new_accu(23 downto 0); +-- carry <= new_accu(24); + carry_20 <= new_accu(20) xor cur_20; + msb_other <= msb_register(ring_index); + voice_o <= voice_i; + enable_o <= enable_i; + test_o <= test; + + if enable_i='1' then + accu_reg(0 to g_num_voices-2) <= accu_reg(1 to g_num_voices-1); + accu_reg(g_num_voices-1) <= new_accu(23 downto 0); + + car_register(to_integer(voice_i)) <= new_accu(24); + msb_register(to_integer(voice_i)) <= cur_accu(23); + end if; + end if; + end process; + +end Gideon; diff --git a/Commodore - 64_Mist/rtl/sid/sid_ctrl.vhd b/Commodore - 64_Mist/rtl/sid/sid_ctrl.vhd new file mode 100644 index 00000000..5b2bb3c8 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/sid_ctrl.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sid_ctrl is +generic ( + g_num_voices : natural := 8 ); +port ( + clock : in std_logic; + reset : in std_logic; + + start_iter : in std_logic; + + voice_osc : out unsigned(3 downto 0); + enable_osc : out std_logic ); + +end sid_ctrl; + +architecture gideon of sid_ctrl is + + signal voice_cnt : unsigned(3 downto 0); + signal enable : std_logic; + +begin + process(clock) + begin + if rising_edge(clock) then + if reset='1' then + voice_cnt <= X"0"; + enable <= '0'; + elsif start_iter='1' then + voice_cnt <= X"0"; + enable <= '1'; + elsif voice_cnt = g_num_voices-1 then + voice_cnt <= X"0"; + enable <= '0'; + elsif enable='1' then + voice_cnt <= voice_cnt + 1; + enable <= '1'; + end if; + end if; + end process; + + voice_osc <= voice_cnt; + enable_osc <= enable; +end gideon; diff --git a/Commodore - 64_Mist/rtl/sid/sid_debug_pkg.vhd b/Commodore - 64_Mist/rtl/sid/sid_debug_pkg.vhd new file mode 100644 index 00000000..13452751 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/sid_debug_pkg.vhd @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package sid_debug_pkg is + + type t_voice_debug is record + state : unsigned(1 downto 0); + enveloppe : unsigned(7 downto 0); + pre15 : unsigned(14 downto 0); + pre5 : unsigned(4 downto 0); + presc : unsigned(14 downto 0); + gate : std_logic; + attack : std_logic_vector(3 downto 0); + decay : std_logic_vector(3 downto 0); + sustain : std_logic_vector(3 downto 0); + release : std_logic_vector(3 downto 0); + end record; + + type t_voice_debug_array is array(natural range <>) of t_voice_debug; + +end; diff --git a/Commodore - 64_Mist/rtl/sid/sid_filter.vhd b/Commodore - 64_Mist/rtl/sid/sid_filter.vhd new file mode 100644 index 00000000..cfadd865 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/sid_filter.vhd @@ -0,0 +1,309 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.my_math_pkg.all; + +entity sid_filter is +generic ( + g_divider : natural := 221 ); +port ( + clock : in std_logic; + reset : in std_logic; + enable : in std_logic; + + filt_co : in unsigned(10 downto 0); + filt_res : in unsigned(3 downto 0); + + valid_in : in std_logic := '0'; + error_out : out std_logic; + input : in signed(17 downto 0); + high_pass : out signed(17 downto 0); + band_pass : out signed(17 downto 0); + low_pass : out signed(17 downto 0); + + valid_out : out std_logic ); +end sid_filter; + +architecture dsvf of sid_filter is + signal filter_q : signed(17 downto 0); + signal filter_f : signed(17 downto 0); + signal input_sc : signed(17 downto 0); + signal filt_ram : std_logic_vector(15 downto 0); + signal xa : signed(17 downto 0); + signal xb : signed(17 downto 0); + signal sum_b : signed(17 downto 0); + signal sub_a : signed(17 downto 0); + signal sub_b : signed(17 downto 0); + signal x_reg : signed(17 downto 0) := (others => '0'); + signal bp_reg : signed(17 downto 0); + signal hp_reg : signed(17 downto 0); + signal lp_reg : signed(17 downto 0); + signal temp_reg : signed(17 downto 0); + signal error : std_logic := '0'; + signal divider : integer range 0 to g_divider-1; + + signal instruction : std_logic_vector(7 downto 0); + type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0); + constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20"); + + type t_word_array is array(1023 downto 0) of signed(15 downto 0); + constant coef : t_word_array := + ( + X"fff6", X"ffe5", X"ffd4", X"ffc3", X"ffb2", X"ffa0", X"ff8f", X"ff7e", + X"ff6d", X"ff5c", X"ff4a", X"ff39", X"ff28", X"ff17", X"ff06", X"fef4", + X"fee3", X"fed2", X"fec1", X"feb0", X"fe9e", X"fe8d", X"fe7c", X"fe6b", + X"fe5a", X"fe48", X"fe37", X"fe26", X"fe15", X"fe04", X"fdf2", X"fde1", + X"fdd0", X"fdbf", X"fdae", X"fd9c", X"fd8b", X"fd7a", X"fd69", X"fd58", + X"fd46", X"fd35", X"fd24", X"fd13", X"fd02", X"fcf0", X"fcdf", X"fcce", + X"fcbd", X"fcac", X"fc9a", X"fc89", X"fc78", X"fc67", X"fc56", X"fc44", + X"fc33", X"fc22", X"fc11", X"fc00", X"fbee", X"fbdd", X"fbcc", X"fbbb", + X"fb99", X"fb76", X"fb54", X"fb32", X"fb10", X"faee", X"facc", X"faaa", + X"fa88", X"fa65", X"fa43", X"fa21", X"f9ff", X"f9dd", X"f9bb", X"f999", + X"f976", X"f954", X"f932", X"f910", X"f8ee", X"f8cc", X"f8aa", X"f888", + X"f865", X"f843", X"f821", X"f7ff", X"f7dd", X"f7bb", X"f799", X"f776", + X"f754", X"f732", X"f710", X"f6ee", X"f6cc", X"f6aa", X"f688", X"f665", + X"f643", X"f621", X"f5ff", X"f5dd", X"f5bb", X"f599", X"f576", X"f554", + X"f532", X"f510", X"f4ee", X"f4cc", X"f4aa", X"f488", X"f465", X"f443", + X"f421", X"f3ff", X"f3dd", X"f3bb", X"f399", X"f376", X"f354", X"f332", + X"f2f4", X"f2b5", X"f276", X"f238", X"f1f9", X"f1bb", X"f17c", X"f13e", + X"f0ff", X"f0c0", X"f082", X"f043", X"f005", X"efc6", X"ef88", X"ef49", + X"ef0a", X"eecc", X"ee8d", X"ee4f", X"ee10", X"edd2", X"ed93", X"ed54", + X"ed16", X"ecd7", X"ec99", X"ec5a", X"ec1b", X"ebdd", X"eb9e", X"eb60", + X"eb21", X"eae3", X"eaa4", X"ea65", X"ea27", X"e9e8", X"e9aa", X"e96b", + X"e92d", X"e8ee", X"e8af", X"e871", X"e832", X"e7f4", X"e7b5", X"e777", + X"e738", X"e6f9", X"e6bb", X"e67c", X"e63e", X"e5ff", X"e5c0", X"e582", + X"e543", X"e505", X"e4c6", X"e488", X"e449", X"e40a", X"e3cc", X"e38d", + X"e338", X"e2e3", X"e28d", X"e238", X"e1e3", X"e18d", X"e138", X"e0e3", + X"e08d", X"e038", X"dfe3", X"df8d", X"df38", X"dee3", X"de8d", X"de38", + X"dde3", X"dd8d", X"dd38", X"dce3", X"dc8d", X"dc38", X"dbe3", X"db8d", + X"db38", X"dae3", X"da8d", X"da38", X"d9e3", X"d98d", X"d938", X"d8e3", + X"d88d", X"d838", X"d7e3", X"d78d", X"d738", X"d6e3", X"d68d", X"d638", + X"d5e3", X"d58d", X"d538", X"d4e3", X"d48d", X"d438", X"d3e3", X"d38d", + X"d338", X"d2e3", X"d28d", X"d238", X"d1e3", X"d18d", X"d138", X"d0e3", + X"d08d", X"d038", X"cfe3", X"cf8d", X"cf38", X"cee3", X"ce8d", X"ce38", + X"cdaa", X"cd1c", X"cc8d", X"cbff", X"cb71", X"cae3", X"ca54", X"c9c6", + X"c938", X"c8aa", X"c81c", X"c78d", X"c6ff", X"c671", X"c5e3", X"c554", + X"c4c6", X"c438", X"c3aa", X"c31c", X"c28d", X"c1ff", X"c171", X"c0e3", + X"c054", X"bfc6", X"bf38", X"beaa", X"be1c", X"bd8d", X"bcff", X"bc71", + X"bbe3", X"bb54", X"bac6", X"ba38", X"b9aa", X"b91c", X"b88d", X"b7ff", + X"b771", X"b6e3", X"b654", X"b5c6", X"b538", X"b4aa", X"b41c", X"b38d", + X"b2ff", X"b271", X"b1e3", X"b154", X"b0c6", X"b038", X"afaa", X"af1c", + X"ae8d", X"adff", X"ad71", X"ace3", X"ac54", X"abc6", X"ab38", X"aaaa", + X"aa1c", X"a98d", X"a8ff", X"a871", X"a7e3", X"a755", X"a6c6", X"a638", + X"a5aa", X"a51c", X"a48d", X"a3ff", X"a371", X"a2e3", X"a255", X"a1c6", + X"a138", X"a0aa", X"a01c", X"9f8d", X"9eff", X"9e71", X"9de3", X"9d55", + X"9cc6", X"9c38", X"9baa", X"9b1c", X"9a8d", X"99ff", X"9971", X"98e3", + X"9855", X"97c6", X"9738", X"96aa", X"961c", X"958d", X"94ff", X"9471", + X"93e3", X"9355", X"92c6", X"9238", X"91aa", X"911c", X"908d", X"8fff", + X"8f71", X"8ee3", X"8e55", X"8dc6", X"8d38", X"8caa", X"8c1c", X"8b8d", + X"8aff", X"8a71", X"89e3", X"8955", X"88c6", X"8838", X"87aa", X"871c", + X"8699", X"8616", X"8593", X"8510", X"848d", X"840b", X"8388", X"8305", + X"8282", X"81ff", X"817c", X"80fa", X"8077", X"7ff4", X"7f71", X"7eee", + X"7e6b", X"7de8", X"7d66", X"7ce3", X"7c60", X"7bdd", X"7b5a", X"7ad7", + X"7a55", X"79d2", X"794f", X"78cc", X"7849", X"77c6", X"7744", X"76c1", + X"763e", X"75bb", X"7538", X"74b5", X"7432", X"73b0", X"732d", X"72aa", + X"7227", X"71a4", X"7121", X"709f", X"701c", X"6f99", X"6f16", X"6e93", + X"6e10", X"6d8e", X"6d0b", X"6c88", X"6c05", X"6b82", X"6aff", X"6a7c", + X"69fa", X"6977", X"68f4", X"6871", X"67ee", X"676b", X"66e9", X"6666", + X"65dd", X"6555", X"64cc", X"6444", X"63bb", X"6333", X"62aa", X"6221", + X"6199", X"6110", X"6088", X"5fff", X"5f77", X"5eee", X"5e66", X"5ddd", + X"5d55", X"5ccc", X"5c44", X"5bbb", X"5b33", X"5aaa", X"5a21", X"5999", + X"5910", X"5888", X"57ff", X"5777", X"56ee", X"5666", X"55dd", X"5555", + X"54b5", X"5416", X"5377", X"52d8", X"5238", X"5199", X"50fa", X"505a", + X"4fbb", X"4f1c", X"4e7d", X"4ddd", X"4d3e", X"4c9f", X"4bff", X"4b60", + X"4ac8", X"4a31", X"4999", X"4901", X"486a", X"47d2", X"473a", X"46a2", + X"460b", X"4573", X"44db", X"4444", X"438e", X"42d8", X"4222", X"416b", + X"54b9", X"5381", X"5248", X"5110", X"4fff", X"4eee", X"4ddd", X"4ccc", + X"4c16", X"4b60", X"4aaa", X"49f4", X"493e", X"4888", X"47d2", X"471c", + X"467d", X"45dd", X"453e", X"449f", X"43ff", X"4360", X"42c1", X"4222", + X"4182", X"40e3", X"4044", X"3fa4", X"3f05", X"3e66", X"3dc6", X"3d27", + X"3caa", X"3c2d", X"3bb0", X"3b33", X"3ab5", X"3a38", X"39bb", X"393e", + X"38c1", X"3844", X"37c7", X"3749", X"36cc", X"364f", X"35d2", X"3555", + X"34d8", X"345a", X"33dd", X"3360", X"32e3", X"3266", X"31e9", X"316b", + X"30ee", X"3071", X"2ff4", X"2f77", X"2efa", X"2e7d", X"2dff", X"2d82", + X"2d1c", X"2cb5", X"2c4f", X"2be9", X"2b82", X"2b1c", X"2ab5", X"2a4f", + X"29e9", X"2982", X"291c", X"28b5", X"284f", X"27e9", X"2782", X"271c", + X"26b5", X"264f", X"25e9", X"2582", X"251c", X"24b5", X"244f", X"23e9", + X"2382", X"231c", X"22b5", X"224f", X"21e9", X"2182", X"211c", X"20b5", + X"2066", X"2016", X"1fc7", X"1f77", X"1f27", X"1ed8", X"1e88", X"1e38", + X"1de9", X"1d99", X"1d49", X"1cfa", X"1caa", X"1c5a", X"1c0b", X"1bbb", + X"1b6c", X"1b1c", X"1acc", X"1a7d", X"1a2d", X"19dd", X"198e", X"193e", + X"18ee", X"189f", X"184f", X"17ff", X"17b0", X"1760", X"1711", X"16c1", + X"1692", X"1664", X"1635", X"1606", X"15d8", X"15a9", X"157a", X"154c", + X"151d", X"14ee", X"14c0", X"1491", X"1462", X"1434", X"1405", X"13d7", + X"13a8", X"1379", X"134b", X"131c", X"12ed", X"12bf", X"1290", X"1261", + X"1233", X"1204", X"11d5", X"11a7", X"1178", X"1149", X"111b", X"10ec", + X"10bd", X"108f", X"1060", X"1032", X"1003", X"0fd4", X"0fa6", X"0f77", + X"0f48", X"0f1a", X"0eeb", X"0ebc", X"0e8e", X"0e5f", X"0e30", X"0e02", + X"0dd3", X"0da4", X"0d76", X"0d47", X"0d19", X"0cea", X"0cbb", X"0c8d", + X"0c5e", X"0c2f", X"0c01", X"0bd2", X"0ba3", X"0b75", X"0b46", X"0b17", + X"0b03", X"0aee", X"0ada", X"0ac5", X"0ab1", X"0a9c", X"0a88", X"0a74", + X"0a5f", X"0a4b", X"0a36", X"0a22", X"0a0d", X"09f9", X"09e4", X"09d0", + X"09bb", X"09a7", X"0992", X"097e", X"0969", X"0955", X"0940", X"092c", + X"0917", X"0903", X"08ee", X"08da", X"08c5", X"08b1", X"089c", X"0888", + X"0874", X"085f", X"084b", X"0836", X"0822", X"080d", X"07f9", X"07e4", + X"07d0", X"07bb", X"07a7", X"0792", X"077e", X"0769", X"0755", X"0740", + X"072c", X"0717", X"0703", X"06ee", X"06da", X"06c5", X"06b1", X"069d", + X"0688", X"0674", X"065f", X"064b", X"0636", X"0622", X"060d", X"05f9", + X"05f2", X"05eb", X"05e4", X"05dd", X"05d7", X"05d0", X"05c9", X"05c2", + X"05bb", X"05b4", X"05ae", X"05a7", X"05a0", X"0599", X"0592", X"058b", + X"0585", X"057e", X"0577", X"0570", X"0569", X"0562", X"055c", X"0555", + X"054e", X"0547", X"0540", X"053a", X"0533", X"052c", X"0525", X"051e", + X"0517", X"0511", X"050a", X"0503", X"04fc", X"04f5", X"04ee", X"04e8", + X"04e1", X"04da", X"04d3", X"04cc", X"04c5", X"04bf", X"04b8", X"04b1", + X"04aa", X"04a3", X"049d", X"0496", X"048f", X"0488", X"0481", X"047a", + X"0474", X"046d", X"0466", X"045f", X"0458", X"0451", X"044b", X"0444", + X"0441", X"043e", X"043b", X"0438", X"0436", X"0433", X"0430", X"042d", + X"042a", X"0427", X"0424", X"0422", X"041f", X"041c", X"0419", X"0416", + X"0413", X"0411", X"040e", X"040b", X"0408", X"0405", X"0402", X"03ff", + X"03fd", X"03fa", X"03f7", X"03f4", X"03f1", X"03ee", X"03ec", X"03e9", + X"03e6", X"03e3", X"03e0", X"03dd", X"03db", X"03d8", X"03d5", X"03d2", + X"03cf", X"03cc", X"03c9", X"03c7", X"03c4", X"03c1", X"03be", X"03bb", + X"03b8", X"03b6", X"03b3", X"03b0", X"03ad", X"03aa", X"03a7", X"03a4", + X"03a2", X"039f", X"039c", X"0399", X"0396", X"0393", X"0391", X"038e", + X"038d", X"038b", X"038a", X"0389", X"0388", X"0387", X"0386", X"0385", + X"0383", X"0382", X"0381", X"0380", X"037f", X"037e", X"037d", X"037c", + X"037a", X"0379", X"0378", X"0377", X"0376", X"0375", X"0374", X"0372", + X"0371", X"0370", X"036f", X"036e", X"036d", X"036c", X"036a", X"0369", + X"0368", X"0367", X"0366", X"0365", X"0364", X"0362", X"0361", X"0360", + X"035f", X"035e", X"035d", X"035c", X"035b", X"0359", X"0358", X"0357", + X"0356", X"0355", X"0354", X"0353", X"0351", X"0350", X"034f", X"034e", + X"034d", X"034c", X"034b", X"0349", X"0348", X"0347", X"0346", X"0345", + X"0344", X"0344", X"0343", X"0343", X"0342", X"0341", X"0341", X"0340", + X"0340", X"033f", X"033f", X"033e", X"033e", X"033d", X"033c", X"033c", + X"033b", X"033b", X"033a", X"033a", X"0339", X"0338", X"0338", X"0337", + X"0337", X"0336", X"0336", X"0335", X"0334", X"0334", X"0333", X"0333", + X"0332", X"0332", X"0331", X"0330", X"0330", X"032f", X"032f", X"032e", + X"032e", X"032d", X"032c", X"032c", X"032b", X"032b", X"032a", X"032a", + X"0329", X"0328", X"0328", X"0327", X"0327", X"0326", X"0326", X"0325", + X"0324", X"0324", X"0323", X"0323", X"0322", X"0322", X"0321", X"0320" + ); + + alias xa_select : std_logic is instruction(0); + alias xb_select : std_logic is instruction(1); + alias sub_a_sel : std_logic is instruction(2); + alias sub_b_sel : std_logic is instruction(3); + alias sum_to_lp : std_logic is instruction(4); + alias sum_to_bp : std_logic is instruction(5); + alias sub_to_hp : std_logic is instruction(6); + alias mult_enable : std_logic is instruction(7); + +begin + -- Derive the actual 'f' and 'q' parameters + i_q_table: entity work.Q_table + port map ( + Q_reg => filt_res, + filter_q => filter_q ); -- 2.16 format + + process(clock) + begin + if rising_edge(clock) then + if(enable = '1') then + filter_f <= "00" & coef(to_integer(filt_co(10 downto 1))); + else + filter_f <= "001111111111111111"; + end if; + end if; + end process; + + --input_sc <= input; + input_sc <= shift_right(input, 1); + + -- operations to execute the filter: + -- bp_f = f * bp_reg + -- q_contrib = q * bp_reg + -- lp = bp_f + lp_reg + -- temp = input - lp + -- hp = temp - q_contrib + -- hp_f = f * hp + -- bp = hp_f + bp_reg + -- bp_reg = bp + -- lp_reg = lp + + -- x_reg = f * bp_reg -- 10000000 -- 80 + -- lp_reg = x_reg + lp_reg -- 00010010 -- 12 + -- q_contrib = q * bp_reg -- 10000001 -- 81 + -- temp = input - lp -- 00000000 -- 00 (can be merged with previous!) + -- hp_reg = temp - q_contrib -- 01001100 -- 4C + -- x_reg = f * hp_reg -- 10000010 -- 82 + -- bp_reg = x_reg + bp_reg -- 00100000 -- 20 + + + -- now perform the arithmetic + xa <= filter_f when xa_select='0' else filter_q; + xb <= bp_reg when xb_select='0' else hp_reg; + sum_b <= bp_reg when xb_select='0' else lp_reg; + sub_a <= input_sc when sub_a_sel='0' else temp_reg; + sub_b <= lp_reg when sub_b_sel='0' else x_reg; + + process(clock) + variable x_result : signed(35 downto 0); + variable sum_result : signed(17 downto 0); + variable sub_result : signed(17 downto 0); + begin + if rising_edge(clock) then + x_result := xa * xb; + if mult_enable='1' then + x_reg <= x_result(33 downto 16); + if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then + error <= not error; + end if; + end if; + + sum_result := sum_limit(x_reg, sum_b); + temp_reg <= sum_result; + if sum_to_lp='1' then + lp_reg <= sum_result; + end if; + if sum_to_bp='1' then + bp_reg <= sum_result; + end if; + + sub_result := sub_limit(sub_a, sub_b); + temp_reg <= sub_result; + if sub_to_hp='1' then + hp_reg <= sub_result; + end if; + + -- control part + instruction <= (others => '0'); + if reset='1' then + hp_reg <= (others => '0'); + lp_reg <= (others => '0'); + bp_reg <= (others => '0'); + divider <= 0; + elsif divider = g_divider-1 then + divider <= 0; + else + divider <= divider + 1; + if divider < c_program'length then + instruction <= c_program(divider); + end if; + end if; + if divider = c_program'length then + valid_out <= '1'; + else + valid_out <= '0'; + end if; + end if; + end process; + + high_pass <= hp_reg; + band_pass <= bp_reg; + low_pass <= lp_reg; + error_out <= error; +end dsvf; diff --git a/Commodore - 64_Mist/rtl/sid/sid_mixer.vhd b/Commodore - 64_Mist/rtl/sid/sid_mixer.vhd new file mode 100644 index 00000000..0b6c090f --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/sid_mixer.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.my_math_pkg.all; + +entity sid_mixer is +port ( + clock : in std_logic; + reset : in std_logic; + + valid_in : in std_logic := '0'; + + direct_out : in signed(17 downto 0); + high_pass : in signed(17 downto 0); + band_pass : in signed(17 downto 0); + low_pass : in signed(17 downto 0); + + filter_hp : in std_logic; + filter_bp : in std_logic; + filter_lp : in std_logic; + + volume : in unsigned(3 downto 0); + + mixed_out : out signed(17 downto 0); + valid_out : out std_logic ); +end sid_mixer; + +architecture arith of sid_mixer is + signal mix_i : signed(17 downto 0); + signal mix_uns : unsigned(16 downto 0); + signal vol_uns : unsigned(16 downto 0); + signal vol_s : signed(16 downto 0); + signal state : integer range 0 to 7; + signal p_mul : unsigned(33 downto 0); + signal p_mul_s : signed(34 downto 0); + + type t_volume_lut is array(natural range <>) of unsigned(15 downto 0); + constant c_volume_lut : t_volume_lut(0 to 15) := ( + X"0000", X"0EEF", X"1DDE", X"2CCD", X"3BBC", X"4AAA", X"5999", X"6888", + X"7777", X"8666", X"9555", X"A444", X"B333", X"C221", X"D110", X"DFFF" ); + + +begin + process(clock) + variable mix_total : signed(17 downto 0); + begin + if rising_edge(clock) then + valid_out <= '0'; + + state <= state + 1; + case state is + when 0 => + if valid_in = '1' then + mix_i <= sum_limit(direct_out, to_signed(16384, 18)); + else + state <= 0; + end if; + + when 1 => + if filter_hp='1' then + mix_i <= sum_limit(mix_i, high_pass); + end if; + + when 2 => + if filter_bp='1' then + mix_i <= sum_limit(mix_i, band_pass); + end if; + + when 3 => + if filter_lp='1' then + mix_i <= sum_limit(mix_i, low_pass); + end if; + + when 4 => +-- p_mul <= mix_uns * vol_uns; + p_mul_s <= mix_i * vol_s; + valid_out <= '1'; + state <= 0; + + when others => + state <= 0; + + end case; + +-- mix_total := not(p_mul(32)) & signed(p_mul(31 downto 15)); +-- mixed_out <= mix_total; -- + to_signed(16384, 18); + mixed_out <= p_mul_s(33 downto 16); + + if reset='1' then + mix_i <= (others => '0'); + state <= 0; + end if; + end if; + end process; + +-- vol_uns <= "0" & volume & volume & volume & volume; +-- vol_uns <= '0' & c_volume_lut(to_integer(volume)); +-- mix_uns <= not mix_i(17) & unsigned(mix_i(16 downto 1)); + + vol_s <= '0' & signed(c_volume_lut(to_integer(volume))); +end arith; diff --git a/Commodore - 64_Mist/rtl/sid/sid_regs.vhd b/Commodore - 64_Mist/rtl/sid/sid_regs.vhd new file mode 100644 index 00000000..8586f25e --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/sid_regs.vhd @@ -0,0 +1,242 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sid_regs is +port ( + clock : in std_logic; + reset : in std_logic; + + addr : in unsigned(7 downto 0); + wren : in std_logic; + wdata : in std_logic_vector(7 downto 0); + rdata : out std_logic_vector(7 downto 0); + potx : in std_logic; + poty : in std_logic;--- + comb_wave_l : in std_logic; + comb_wave_r : in std_logic; +--- + voice_osc : in unsigned(3 downto 0); + voice_wave : in unsigned(3 downto 0); + voice_adsr : in unsigned(3 downto 0); + voice_mul : in unsigned(3 downto 0); + + -- Oscillator parameters + freq : out unsigned(15 downto 0); + test : out std_logic; + sync : out std_logic; + + -- Wave map parameters + comb_mode : out std_logic; + ring_mod : out std_logic; + wave_sel : out std_logic_vector(3 downto 0); + sq_width : out unsigned(11 downto 0); + + -- ADSR parameters + gate : out std_logic; + attack : out std_logic_vector(3 downto 0); + decay : out std_logic_vector(3 downto 0); + sustain : out std_logic_vector(3 downto 0); + release : out std_logic_vector(3 downto 0); + + -- mixer 1 parameters + filter_en : out std_logic; + + -- globals + volume_l : out unsigned(3 downto 0) := (others => '0'); + filter_co_l : out unsigned(10 downto 0) := (others => '0'); + filter_res_l : out unsigned(3 downto 0) := (others => '0'); + filter_ex_l : out std_logic := '0'; + filter_hp_l : out std_logic := '0'; + filter_bp_l : out std_logic := '0'; + filter_lp_l : out std_logic := '0'; + voice3_off_l : out std_logic := '0'; + + volume_r : out unsigned(3 downto 0) := (others => '0'); + filter_co_r : out unsigned(10 downto 0) := (others => '0'); + filter_res_r : out unsigned(3 downto 0) := (others => '0'); + filter_ex_r : out std_logic := '0'; + filter_hp_r : out std_logic := '0'; + filter_bp_r : out std_logic := '0'; + filter_lp_r : out std_logic := '0'; + voice3_off_r : out std_logic := '0'; + + -- readback + osc3 : in std_logic_vector(7 downto 0); + env3 : in std_logic_vector(7 downto 0) ); + + attribute ramstyle : string; + +end sid_regs; + +architecture gideon of sid_regs is + attribute ramstyle of gideon : architecture is "logic"; + + type byte_array_t is array(natural range <>) of std_logic_vector(7 downto 0); + type nibble_array_t is array(natural range <>) of std_logic_vector(3 downto 0); + signal freq_lo : byte_array_t(0 to 15) := (others => (others => '0')); + signal freq_hi : byte_array_t(0 to 15) := (others => (others => '0')); + signal phase_lo : byte_array_t(0 to 15) := (others => (others => '0')); + signal phase_hi : nibble_array_t(0 to 15):= (others => (others => '0')); + signal control : byte_array_t(0 to 15) := (others => (others => '0')); + signal att_dec : byte_array_t(0 to 15) := (others => (others => '0')); + signal sust_rel : byte_array_t(0 to 15) := (others => (others => '0')); + signal do_write : std_logic; + signal wdata_d : std_logic_vector(7 downto 0); + signal filt_en_i: std_logic_vector(15 downto 0) := (others => '0'); + + constant address_remap : byte_array_t(0 to 255) := ( + X"00", X"01", X"02", X"03", X"04", X"05", X"06", -- 00 Voice 1 + X"10", X"11", X"12", X"13", X"14", X"15", X"16", -- 07 Voice 2 + X"20", X"21", X"22", X"23", X"24", X"25", X"26", -- 0E Voice 3 + + X"08", X"09", X"0A", X"0B", -- 15 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 19 + + X"30", X"31", X"32", X"33", X"34", X"35", X"36", -- 20 Voice 4 + X"40", X"41", X"42", X"43", X"44", X"45", X"46", -- 27 Voice 5 + X"50", X"51", X"52", X"53", X"54", X"55", X"56", -- 2E Voice 6 + X"60", X"61", X"62", X"63", X"64", X"65", X"66", -- 35 Voice 7 + X"70", X"71", X"72", X"73", X"74", X"75", X"76", -- 3C Voice 8 + X"0C", X"0D", X"0E", -- 43 + + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 46 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 4D + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 54 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 5B + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 62 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 69 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 70 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 77 + X"FF", X"FF", -- 7E + + X"80", X"81", X"82", X"83", X"84", X"85", X"86", -- 80 Voice 9 + X"90", X"91", X"92", X"93", X"94", X"95", X"96", -- 87 Voice 10 + X"A0", X"A1", X"A2", X"A3", X"A4", X"A5", X"A6", -- 8E Voice 11 + + X"88", X"89", X"8A", X"8B", -- 95 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 99 + + X"B0", X"B1", X"B2", X"B3", X"B4", X"B5", X"B6", -- A0 Voice 12 + X"C0", X"C1", X"C2", X"C3", X"C4", X"C5", X"C6", -- A7 Voice 13 + X"D0", X"D1", X"D2", X"D3", X"D4", X"D5", X"D6", -- AE Voice 14 + X"E0", X"E1", X"E2", X"E3", X"E4", X"E5", X"E6", -- B5 Voice 15 + X"F0", X"F1", X"F2", X"F3", X"F4", X"F5", X"F6", -- BC Voice 16 + X"8C", X"8D", X"8E", -- C3 + + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C6 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- CD + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D4 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- DB + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E2 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E9 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0 + X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F7 + X"FF", X"FF" ); -- FE + + signal address : unsigned(7 downto 0); +begin + process(clock) + begin + if rising_edge(clock) then + address <= unsigned(address_remap(to_integer(addr))); + do_write <= wren; + wdata_d <= wdata; + + if do_write='0' and wren='1' then + if address(3)='0' then -- Voice register + case address(2 downto 0) is + when "000" => freq_lo(to_integer(address(7 downto 4))) <= wdata_d; + when "001" => freq_hi(to_integer(address(7 downto 4))) <= wdata_d; + when "010" => phase_lo(to_integer(address(7 downto 4))) <= wdata_d; + when "011" => phase_hi(to_integer(address(7 downto 4))) <= wdata_d(3 downto 0); + when "100" => control(to_integer(address(7 downto 4))) <= wdata_d; + when "101" => att_dec(to_integer(address(7 downto 4))) <= wdata_d; + when "110" => sust_rel(to_integer(address(7 downto 4))) <= wdata_d; + when others => null; + end case; + elsif address(7)='0' then -- Global register for left + case address(2 downto 0) is + when "000" => filter_co_l(2 downto 0) <= unsigned(wdata_d(2 downto 0)); + when "001" => filter_co_l(10 downto 3) <= unsigned(wdata_d); + when "010" => filter_res_l <= unsigned(wdata_d(7 downto 4)); + filter_ex_l <= wdata_d(3); + filt_en_i(2 downto 0) <= wdata_d(2 downto 0); + when "011" => voice3_off_l <= wdata_d(7); + filter_hp_l <= wdata_d(6); + filter_bp_l <= wdata_d(5); + filter_lp_l <= wdata_d(4); + volume_l <= unsigned(wdata_d(3 downto 0)); + when "100" => filt_en_i(7 downto 0) <= wdata_d; + when others => null; + end case; + else -- Global register for right + case address(2 downto 0) is + when "000" => filter_co_r(2 downto 0) <= unsigned(wdata_d(2 downto 0)); + when "001" => filter_co_r(10 downto 3) <= unsigned(wdata_d); + when "010" => filter_res_r <= unsigned(wdata_d(7 downto 4)); + filter_ex_r <= wdata_d(3); + filt_en_i(10 downto 8) <= wdata_d(2 downto 0); + when "011" => voice3_off_r <= wdata_d(7); + filter_hp_r <= wdata_d(6); + filter_bp_r <= wdata_d(5); + filter_lp_r <= wdata_d(4); + volume_r <= unsigned(wdata_d(3 downto 0)); + when "100" => filt_en_i(15 downto 8) <= wdata_d; + when others => null; + end case; + end if; + end if; + + -- Readback (unmapped address) + case addr is + when "00011001" => rdata <= potx & potx & potx & potx & potx & potx & potx & potx; + when "00011010" => rdata <= poty & poty & poty & poty & poty & poty & poty & poty; + when "00011011" => rdata <= osc3; + when "00011100" => rdata <= env3; + when others => rdata <= (others => '0'); + end case; + + if reset='1' then + filt_en_i <= (others => '0'); + voice3_off_l <= '0'; + voice3_off_r <= '0'; + volume_l <= X"0"; + volume_r <= X"0"; + end if; + end if; + end process; + + freq <= unsigned(freq_hi(to_integer(voice_osc))) & unsigned(freq_lo(to_integer(voice_osc))); + test <= control(to_integer(voice_osc))(3); + sync <= control(to_integer(voice_osc))(1); + + -- Wave map parameters + ring_mod <= control(to_integer(voice_wave))(2); + wave_sel <= control(to_integer(voice_wave))(7 downto 4); + sq_width <= unsigned(phase_hi(to_integer(voice_wave))) & unsigned(phase_lo(to_integer(voice_wave))); + comb_mode <= (voice_wave(3) and comb_wave_r) or (not voice_wave(3) and comb_wave_l); + + -- ADSR parameters + gate <= control(to_integer(voice_adsr))(0); + attack <= att_dec(to_integer(voice_adsr))(7 downto 4); + decay <= att_dec(to_integer(voice_adsr))(3 downto 0); + sustain <= sust_rel(to_integer(voice_adsr))(7 downto 4); + release <= sust_rel(to_integer(voice_adsr))(3 downto 0); + + -- Mixer 1 parameters + filter_en <= filt_en_i(to_integer(voice_mul)); + +end gideon; diff --git a/Commodore - 64_Mist/rtl/sid/sid_top.vhd b/Commodore - 64_Mist/rtl/sid/sid_top.vhd new file mode 100644 index 00000000..374d3ce9 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/sid_top.vhd @@ -0,0 +1,409 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity sid_top is +generic ( + g_filter_div : natural := 141; --for 32 MHz (221; -- for 50 MHz) + g_num_voices : natural := 3 ); +port ( + clock : in std_logic; + reset : in std_logic; + + addr : in unsigned(7 downto 0); + wren : in std_logic; + wdata : in std_logic_vector(7 downto 0); + rdata : out std_logic_vector(7 downto 0); + potx : in std_logic; + poty : in std_logic; + + comb_wave_l : in std_logic := '0'; + comb_wave_r : in std_logic := '0'; + + start_iter : in std_logic; + sample_left : out signed(17 downto 0); + sample_right : out signed(17 downto 0); + + extfilter_en : in std_logic +); +end sid_top; + + +architecture structural of sid_top is + + -- Voice index in pipe + signal voice_osc : unsigned(3 downto 0); + signal voice_wave : unsigned(3 downto 0); + signal voice_mul : unsigned(3 downto 0); + signal enable_osc : std_logic; + signal enable_wave : std_logic; + signal enable_mul : std_logic; + + -- Oscillator parameters + signal freq : unsigned(15 downto 0); + signal test : std_logic; + signal sync : std_logic; + + -- Wave map parameters + signal msb_other : std_logic; + signal comb_mode : std_logic; + signal ring_mod : std_logic; + signal wave_sel : std_logic_vector(3 downto 0); + signal sq_width : unsigned(11 downto 0); + + -- ADSR parameters + signal gate : std_logic; + signal attack : std_logic_vector(3 downto 0); + signal decay : std_logic_vector(3 downto 0); + signal sustain : std_logic_vector(3 downto 0); + signal release : std_logic_vector(3 downto 0); + + -- Filter enable + signal filter_en : std_logic; + + -- globals + signal volume_l : unsigned(3 downto 0); + signal filter_co_l : unsigned(10 downto 0); + signal filter_res_l : unsigned(3 downto 0); + signal filter_hp_l : std_logic; + signal filter_bp_l : std_logic; + signal filter_lp_l : std_logic; + signal voice3_off_l : std_logic; + + signal volume_r : unsigned(3 downto 0); + signal filter_co_r : unsigned(10 downto 0); + signal filter_res_r : unsigned(3 downto 0); + signal filter_hp_r : std_logic; + signal filter_bp_r : std_logic; + signal filter_lp_r : std_logic; + signal voice3_off_r : std_logic; + + -- readback + signal osc3 : std_logic_vector(7 downto 0); + signal env3 : std_logic_vector(7 downto 0); + + -- intermediate flags and signals + signal test_wave : std_logic; + signal osc_val : unsigned(23 downto 0); + signal carry_20 : std_logic; + signal enveloppe : unsigned(7 downto 0); + signal waveform : unsigned(11 downto 0); + + signal valid_sum : std_logic; + signal valid_filt : std_logic; + signal valid_mix : std_logic; + + signal filter_out_l: signed(17 downto 0) := (others => '0'); + signal direct_out_l: signed(17 downto 0) := (others => '0'); + signal high_pass_l : signed(17 downto 0) := (others => '0'); + signal band_pass_l : signed(17 downto 0) := (others => '0'); + signal low_pass_l : signed(17 downto 0) := (others => '0'); + signal mixed_out_l : signed(17 downto 0) := (others => '0'); + + signal filter_out_r: signed(17 downto 0) := (others => '0'); + signal direct_out_r: signed(17 downto 0) := (others => '0'); + signal high_pass_r : signed(17 downto 0) := (others => '0'); + signal band_pass_r : signed(17 downto 0) := (others => '0'); + signal low_pass_r : signed(17 downto 0) := (others => '0'); + signal mixed_out_r : signed(17 downto 0) := (others => '0'); +begin + + i_regs: entity work.sid_regs + port map + ( + clock => clock, + reset => reset, + + addr => addr, + wren => wren, + wdata => wdata, + rdata => rdata, + potx => potx, + poty => poty, + + comb_wave_l => comb_wave_l, + comb_wave_r => comb_wave_r, + + voice_osc => voice_osc, + voice_wave => voice_wave, + voice_adsr => voice_wave, + voice_mul => voice_mul, + + -- Oscillator parameters + freq => freq, + test => test, + sync => sync, + + -- Wave map parameters + comb_mode => comb_mode, + ring_mod => ring_mod, + wave_sel => wave_sel, + sq_width => sq_width, + + -- ADSR parameters + gate => gate, + attack => attack, + decay => decay, + sustain => sustain, + release => release, + + -- mixer parameters + filter_en => filter_en, + + -- globals + volume_l => volume_l, + filter_co_l => filter_co_l, + filter_res_l=> filter_res_l, + filter_ex_l => open, + filter_hp_l => filter_hp_l, + filter_bp_l => filter_bp_l, + filter_lp_l => filter_lp_l, + voice3_off_l=> voice3_off_l, + + volume_r => volume_r, + filter_co_r => filter_co_r, + filter_res_r=> filter_res_r, + filter_ex_r => open, + filter_hp_r => filter_hp_r, + filter_bp_r => filter_bp_r, + filter_lp_r => filter_lp_r, + voice3_off_r=> voice3_off_r, + + -- readback + osc3 => osc3, + env3 => env3 + ); + + i_ctrl: entity work.sid_ctrl + generic map + ( + g_num_voices => g_num_voices + ) + port map + ( + clock => clock, + reset => reset, + start_iter => start_iter, + voice_osc => voice_osc, + enable_osc => enable_osc + ); + + + osc: entity work.oscillator + generic map + ( + g_num_voices + ) + port map + ( + clock => clock, + reset => reset, + + voice_i => voice_osc, + voice_o => voice_wave, + + enable_i => enable_osc, + enable_o => enable_wave, + + freq => freq, + test => test, + sync => sync, + + osc_val => osc_val, + test_o => test_wave, + carry_20 => carry_20, + msb_other => msb_other + ); + + wmap: entity work.wave_map + generic map + ( + g_num_voices => g_num_voices, + g_sample_bits => 12 + ) + port map + ( + clock => clock, + reset => reset, + test => test_wave, + + osc_val => osc_val, + carry_20 => carry_20, + msb_other => msb_other, + + voice_i => voice_wave, + enable_i => enable_wave, + comb_mode => comb_mode, + wave_sel => wave_sel, + ring_mod => ring_mod, + sq_width => sq_width, + + voice_o => voice_mul, + enable_o => enable_mul, + wave_out => waveform + ); + + adsr: entity work.adsr_multi + generic map + ( + g_num_voices => g_num_voices + ) + port map + ( + clock => clock, + reset => reset, + + voice_i => voice_wave, + enable_i => enable_wave, + voice_o => open, + enable_o => open, + + gate => gate, + attack => attack, + decay => decay, + sustain => sustain, + release => release, + + env_state=> open, -- for testing only + env_out => enveloppe + ); + + sum: entity work.mult_acc(signed_wave) + port map + ( + clock => clock, + reset => reset, + + voice_i => voice_mul, + enable_i => enable_mul, + voice3_off_l=> voice3_off_l, + voice3_off_r=> voice3_off_r, + + enveloppe => enveloppe, + waveform => waveform, + filter_en => filter_en, + + osc3 => osc3, + env3 => env3, + + valid_out => valid_sum, + filter_out_L => filter_out_L, + filter_out_R => filter_out_R, + direct_out_L => direct_out_L, + direct_out_R => direct_out_R + ); + + i_filt_left: entity work.sid_filter + generic map + ( + g_divider => g_filter_div + ) + port map + ( + clock => clock, + reset => reset, + enable => extfilter_en, + + filt_co => filter_co_l, + filt_res => filter_res_l, + + valid_in => valid_sum, + + input => filter_out_L, + high_pass => high_pass_L, + band_pass => band_pass_L, + low_pass => low_pass_L, + + error_out => open, + valid_out => valid_filt + ); + + mix: entity work.sid_mixer + port map + ( + clock => clock, + reset => reset, + + valid_in => valid_filt, + + direct_out => direct_out_L, + high_pass => high_pass_L, + band_pass => band_pass_L, + low_pass => low_pass_L, + + filter_hp => filter_hp_l, + filter_bp => filter_bp_l, + filter_lp => filter_lp_l, + + volume => volume_l, + + mixed_out => mixed_out_L, + valid_out => open + ); + + i_filt_right: entity work.sid_filter + generic map + ( + g_divider => g_filter_div + ) + port map + ( + clock => clock, + reset => reset, + enable => extfilter_en, + + filt_co => filter_co_r, + filt_res => filter_res_r, + + valid_in => valid_sum, + + input => filter_out_R, + high_pass => high_pass_R, + band_pass => band_pass_R, + low_pass => low_pass_R, + + error_out => open, + valid_out => open + ); + + mix_right: entity work.sid_mixer + port map + ( + clock => clock, + reset => reset, + + valid_in => valid_filt, + + direct_out => direct_out_R, + high_pass => high_pass_R, + band_pass => band_pass_R, + low_pass => low_pass_R, + + filter_hp => filter_hp_r, + filter_bp => filter_bp_r, + filter_lp => filter_lp_r, + + volume => volume_r, + + mixed_out => mixed_out_R, + valid_out => open + ); + + sample_left <= mixed_out_L; + sample_right <= mixed_out_R; + +end structural; diff --git a/Commodore - 64_Mist/rtl/sid/wave_map.vhd b/Commodore - 64_Mist/rtl/sid/wave_map.vhd new file mode 100644 index 00000000..47e79854 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sid/wave_map.vhd @@ -0,0 +1,178 @@ +------------------------------------------------------------------------------- +-- +-- (C) COPYRIGHT 2010 Gideon's Logic Architectures' +-- +------------------------------------------------------------------------------- +-- +-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) +-- +-- Note that this file is copyrighted, and is not supposed to be used in other +-- projects without written permission from the author. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity wave_map is +generic ( + g_num_voices : integer := 8; -- 8 or 16, clock should then be 8 or 16 MHz, too! + g_sample_bits : integer := 8 ); +port ( + clock : in std_logic; + reset : in std_logic; + + osc_val : in unsigned(23 downto 0); + carry_20 : in std_logic; + + msb_other: in std_logic := '0'; + ring_mod : in std_logic := '0'; + test : in std_logic := '0'; + + voice_i : in unsigned(3 downto 0); + comb_mode: in std_logic; + enable_i : in std_logic; + wave_sel : in std_logic_vector(3 downto 0); + sq_width : in unsigned(11 downto 0); + + voice_o : out unsigned(3 downto 0); + enable_o : out std_logic; + wave_out : out unsigned(g_sample_bits-1 downto 0) ); + +end wave_map; + + +architecture Gideon of wave_map is + type noise_array_t is array (natural range <>) of unsigned(22 downto 0); + signal noise_reg : noise_array_t(0 to g_num_voices-1) := (others => (0 => '1', others => '0')); + type voice_array_t is array (natural range <>) of unsigned(g_sample_bits-1 downto 0); + signal voice_reg : voice_array_t(0 to g_num_voices-1) := (others => (others => '0')); + + type t_byte_array is array(natural range <>) of unsigned(7 downto 0); + constant c_wave_TP : t_byte_array(0 to 255) := ( + 16#FF# => X"FF", 16#F7# => X"F7", 16#EF# => X"EF", 16#E7# => X"E0", + 16#FE# => X"FE", 16#F6# => X"F0", 16#EE# => X"E0", 16#E6# => X"00", + 16#FD# => X"FD", 16#F5# => X"FD", 16#ED# => X"E0", 16#E5# => X"00", + 16#FC# => X"F8", 16#F4# => X"80", 16#EC# => X"00", 16#E4# => X"00", + 16#FB# => X"FB", 16#F3# => X"F0", 16#EB# => X"E0", 16#E3# => X"00", + 16#FA# => X"F8", 16#F2# => X"08", 16#EA# => X"00", 16#E2# => X"00", + 16#F9# => X"F0", 16#F1# => X"00", 16#E9# => X"00", 16#E1# => X"00", + 16#F8# => X"80", 16#F0# => X"00", 16#E8# => X"00", 16#E0# => X"00", + + 16#DF# => X"DF", 16#DE# => X"D0", 16#DD# => X"C0", 16#DB# => X"C0", + 16#D7# => X"C0", 16#CF# => X"C0", 16#BF# => X"BF", 16#BE# => X"B0", + 16#BD# => X"A0", 16#B9# => X"80", 16#B7# => X"80", 16#AF# => X"80", + + 16#7F# => X"7F", 16#7E# => X"70", 16#7D# => X"70", 16#7B# => X"60", + 16#77# => X"40", others => X"00" ); + + constant c_wave_TS : t_byte_array(0 to 255) := ( + 16#7F# => X"1E", 16#FE# => X"18", 16#FF# => X"3E", others => X"00" ); + +begin + process(clock) + variable noise_tmp : unsigned(22 downto 0); + variable voice_tmp : unsigned(g_sample_bits-1 downto 0); + variable triangle : unsigned(g_sample_bits-1 downto 0); + variable square : unsigned(g_sample_bits-1 downto 0); + variable sawtooth : unsigned(g_sample_bits-1 downto 0); + variable out_tmp : unsigned(g_sample_bits-1 downto 0); + variable new_bit : std_logic; + begin + if rising_edge(clock) then + -- take top of list + voice_tmp := voice_reg(0); + noise_tmp := noise_reg(0); + + if reset='1' or test='1' then + noise_tmp := (others => '1'); -- seed not equal to zero + elsif carry_20='1' then + new_bit := noise_tmp(22) xor noise_tmp(21) xor noise_tmp(20) xor noise_tmp(15); + noise_tmp := noise_tmp(21 downto 0) & new_bit; + end if; + + if osc_val(23)='1' then + triangle := not osc_val(22 downto 23-g_sample_bits); + else + triangle := osc_val(22 downto 23-g_sample_bits); + end if; + if ring_mod='1' and msb_other='0' then + triangle := not triangle; + end if; + + sawtooth := osc_val(23 downto 24-g_sample_bits); + if osc_val(23 downto 12) < sq_width then + square := (others => '0'); + else + square := (others => '1'); + end if; + + out_tmp := (others => '0'); + case wave_sel is + when X"0" => + out_tmp := voice_tmp; + when X"1" => + out_tmp := triangle; + when X"2" => + out_tmp := sawtooth; + when X"3" => + if comb_mode='0' then + out_tmp(g_sample_bits-1 downto g_sample_bits-8) := + c_wave_TS(to_integer(osc_val(23 downto 23-g_sample_bits))); + else -- 8580 + out_tmp := triangle and sawtooth; + end if; + when X"4" => + out_tmp := square; + when X"5" => -- combined triangle and square + if comb_mode='0' then + if square(0)='1' then + out_tmp(g_sample_bits-1 downto g_sample_bits-8) := + c_wave_TP(to_integer(triangle(g_sample_bits-1 downto g_sample_bits-8))); + end if; + else -- 8580 + out_tmp := triangle and square; + end if; + when X"6" => -- combined saw and pulse + if comb_mode='1' then + out_tmp := sawtooth and square; + end if; + + when X"7" => -- combined triangle, saw and pulse + if comb_mode='1' then + out_tmp := triangle and sawtooth and square; + end if; + + when X"8" => + out_tmp(g_sample_bits-1) := noise_tmp(22); -- unsure.. 21? + out_tmp(g_sample_bits-2) := noise_tmp(20); + out_tmp(g_sample_bits-3) := noise_tmp(16); + out_tmp(g_sample_bits-4) := noise_tmp(13); + out_tmp(g_sample_bits-5) := noise_tmp(11); + out_tmp(g_sample_bits-6) := noise_tmp(7); + out_tmp(g_sample_bits-7) := noise_tmp(4); + out_tmp(g_sample_bits-8) := noise_tmp(2); + +-- when X"9"|X"A"|X"B"|X"C"|X"D"|X"E"|X"F" => +-- out_tmp := noise_tmp(20 downto 21-g_sample_bits); +-- noise_tmp := (others => '0'); + when others => + null; + end case; + + if enable_i='1' then + noise_reg(g_num_voices-1) <= noise_tmp; + noise_reg(0 to g_num_voices-2) <= noise_reg(1 to g_num_voices-1); + voice_reg(g_num_voices-1) <= out_tmp; + voice_reg(0 to g_num_voices-2) <= voice_reg(1 to g_num_voices-1); + end if; + + --out_tmp(out_tmp'high) := not out_tmp(out_tmp'high); + wave_out <= unsigned(out_tmp); + + voice_o <= voice_i; + enable_o <= enable_i; + end if; + end process; + +end Gideon; diff --git a/Commodore - 64_Mist/rtl/sigma_delta_dac.v b/Commodore - 64_Mist/rtl/sigma_delta_dac.v new file mode 100644 index 00000000..d692f3a0 --- /dev/null +++ b/Commodore - 64_Mist/rtl/sigma_delta_dac.v @@ -0,0 +1,29 @@ + +module sigma_delta_dac #(parameter MSBI=14, parameter INV=1'b1) +( + output reg DACout = INV, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= INV; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= SigmaLatch[MSBI+2] ^ INV; + end +end + +endmodule diff --git a/Commodore - 64_Mist/rtl/trkbuf.v b/Commodore - 64_Mist/rtl/trkbuf.v new file mode 100644 index 00000000..b91fea12 --- /dev/null +++ b/Commodore - 64_Mist/rtl/trkbuf.v @@ -0,0 +1,242 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: trkbuf.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module trkbuf ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [12:0] address_a; + input [12:0] address_b; + input clock; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .clock0 (clock), + .wren_a (wren_a), + .address_b (address_b), + .data_b (data_b), + .wren_b (wren_b), + .address_a (address_a), + .data_a (data_a), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.numwords_b = 8192, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 13, + altsyncram_component.widthad_b = 13, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL "address_a[12..0]" +// Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL "address_b[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0 +// Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL trkbuf.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL trkbuf.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL trkbuf.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL trkbuf.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL trkbuf_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL trkbuf_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - 64_Mist/rtl/unused/Header_buffer.sv b/Commodore - 64_Mist/rtl/unused/Header_buffer.sv new file mode 100644 index 00000000..2058965a --- /dev/null +++ b/Commodore - 64_Mist/rtl/unused/Header_buffer.sv @@ -0,0 +1,20 @@ +// 64 byte buffer for loading files +// used to interrogate file type +// L.C.Ashmore 17 +// +// + + +module header_buffer +( +inout reg [7:0] header_buff [0:63] +); + +integer i; + +initial begin + for (i = 0; i < 64; i = i +1) + header_buff [i] = 0; + end +endmodule + \ No newline at end of file diff --git a/Commodore - 64_Mist/rtl/unused/block_transfer.v b/Commodore - 64_Mist/rtl/unused/block_transfer.v new file mode 100644 index 00000000..5db33b45 --- /dev/null +++ b/Commodore - 64_Mist/rtl/unused/block_transfer.v @@ -0,0 +1,46 @@ +// memory block transfer routine +// L.C.Ashmore feb17 +// +// PRG T64 CRT TAP files load to intermediate buffer 0x200000 (2m) +// +// this routine reads 1st 16bytes to determine file type then either: +// 1, if CRT or TAP move to 0x100000 (1m) and sets cartridge or tap attached flags +// 2, if PRG or T64 moves directly into c64 memory map (injection) +// T64 format pain in the arse so only basic function !! + +module block_transfer +( +input clk32, +input [31:0] addr_total_size, +input sdram_we, +input sdram_data_out, +output cart_attached, +output reg [24:0] sdram_read_addr, +output reg [24:0] sdram_write_addr, +inout reg [7:0] sdram_data +); + +localparam buffer_address2m = 'h200000; +localparam buffer_address1m = 'h100000; + +reg [24:0] block_addr; +//reg [24:0] sdram_read_addr; +//reg [24:0] sdram_write_addr; +//reg [7:0] sdram_data; +reg transfer_active; +reg read_flag; + +always @(negedge clk32) + begin + if (sdram_we == 1 && transfer_active && !read_flag) //sdram in read cycle - not yet read + begin + sdram_read_addr <= block_addr + buffer_address2m; + sdram_data <= sdram_data_out; + read_flag = 1; + end + if (sdram_we == 0 && read_flag) + begin + sdram_write_addr <= block_addr +buffer_address1m; + end + end +endmodule diff --git a/Commodore - 64_Mist/rtl/video_mixer.sv b/Commodore - 64_Mist/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Commodore - 64_Mist/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Commodore - 64_Mist/rtl/video_vicII_656x_a.vhd b/Commodore - 64_Mist/rtl/video_vicII_656x_a.vhd new file mode 100644 index 00000000..ab15e7cb --- /dev/null +++ b/Commodore - 64_Mist/rtl/video_vicII_656x_a.vhd @@ -0,0 +1,1447 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- VIC-II - Video Interface Chip no 2 +-- +-- ----------------------------------------------------------------------- +-- Dar 08/03/2014 : shift hsync to sprite #3 +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +architecture rtl of video_vicii_656x is + type vicCycles is ( + cycleRefresh1, cycleRefresh2, cycleRefresh3, cycleRefresh4, cycleRefresh5, + cycleIdle1, + cycleChar, + cycleCalcSprites, cycleSpriteBa1, cycleSpriteBa2, cycleSpriteBa3, + cycleSpriteA, cycleSpriteB + ); + subtype ColorDef is unsigned(3 downto 0); + type MFlags is array(0 to 7) of boolean; + type MXdef is array(0 to 7) of unsigned(8 downto 0); + type MYdef is array(0 to 7) of unsigned(7 downto 0); + type MCntDef is array(0 to 7) of unsigned(5 downto 0); + type MPixelsDef is array(0 to 7) of unsigned(23 downto 0); + type MCurrentPixelDef is array(0 to 7) of unsigned(1 downto 0); + type charStoreDef is array(38 downto 0) of unsigned(11 downto 0); + type spriteColorsDef is array(7 downto 0) of unsigned(3 downto 0); + type pixelColorStoreDef is array(7 downto 0) of unsigned(3 downto 0); + +-- State machine + signal lastLineFlag : boolean; -- True for on last line of the frame. + signal beyondFrameFlag : boolean; -- Y>frame lines + signal vicCycle : vicCycles := cycleRefresh1; + signal sprite : unsigned(2 downto 0) := "000"; + signal shiftChars : boolean; + signal idle: std_logic := '1'; + signal rasterIrqDone : std_logic; -- Only one interrupt each rasterLine + signal rasterEnable: std_logic; + +-- BA signal + signal badLine : boolean; -- true if we have a badline condition + signal baLoc : std_logic; + signal baCnt : unsigned(2 downto 0); + + signal baChars : std_logic; + signal baSprite04 : std_logic; + signal baSprite15 : std_logic; + signal baSprite26 : std_logic; + signal baSprite37 : std_logic; + +-- Memory refresh cycles + signal refreshCounter : unsigned(7 downto 0); + +-- User registers + signal MX : MXdef; -- Sprite X + signal MY : MYdef; -- Sprite Y + signal ME : unsigned(7 downto 0); -- Sprite enable + signal MXE : unsigned(7 downto 0); -- Sprite X expansion + signal MYE : unsigned(7 downto 0); -- Sprite Y expansion + signal MPRIO : unsigned(7 downto 0); -- Sprite priority + signal MC : unsigned(7 downto 0); -- sprite multi color + + -- !!! Krestage 3 hacks + signal MCDelay : unsigned(7 downto 0); -- sprite multi color + + -- mode + signal BMM: std_logic; -- Bitmap mode + signal ECM: std_logic; -- Extended color mode + signal MCM: std_logic; -- Multi color mode + signal DEN: std_logic; -- DMA enable + signal RSEL: std_logic; -- Visible rows selection (24/25) + signal CSEL: std_logic; -- Visible columns selection (38/40) + + signal RES: std_logic; + + signal VM: unsigned(13 downto 10); + signal CB: unsigned(13 downto 11); + + signal EC : ColorDef; -- border color + signal B0C : ColorDef; -- background color 0 + signal B1C : ColorDef; -- background color 1 + signal B2C : ColorDef; -- background color 2 + signal B3C : ColorDef; -- background color 3 + signal MM0 : ColorDef; -- sprite multicolor 0 + signal MM1 : ColorDef; -- sprite multicolor 1 + signal spriteColors: spriteColorsDef; + +-- borders and blanking + signal LRBorder: std_logic; + signal TBBorder: std_logic; + signal hBlack: std_logic; + signal vBlanking : std_logic; + signal hBlanking : std_logic; + signal xscroll: unsigned(2 downto 0); + signal yscroll: unsigned(2 downto 0); + signal rasterCmp : unsigned(8 downto 0); + +-- Address generator + signal vicAddrReg : unsigned(13 downto 0); + signal vicAddrLoc : unsigned(13 downto 0); + +-- Address counters + signal ColCounter: unsigned(9 downto 0) := (others => '0'); + signal ColRestart: unsigned(9 downto 0) := (others => '0'); + signal RowCounter: unsigned(2 downto 0) := (others => '0'); + +-- IRQ Registers + signal IRST: std_logic := '0'; + signal ERST: std_logic := '0'; + signal IMBC: std_logic := '0'; + signal EMBC: std_logic := '0'; + signal IMMC: std_logic := '0'; + signal EMMC: std_logic := '0'; + signal ILP: std_logic := '0'; + signal ELP: std_logic := '0'; + signal IRQ: std_logic; + +-- Collision detection registers + signal M2M: unsigned(7 downto 0); -- Sprite to sprite collision + signal M2D: unsigned(7 downto 0); -- Sprite to character collision + signal M2Mhit : std_logic; + signal M2Dhit : std_logic; + +-- Raster counters + signal rasterX : unsigned(9 downto 0) := (others => '0'); + signal rasterY : unsigned(8 downto 0) := (others => '0'); + +-- Light pen + signal lightPenHit: std_logic; + signal lpX : unsigned(7 downto 0); + signal lpY : unsigned(7 downto 0); + +-- IRQ Resets + signal resetLightPenIrq: std_logic; + signal resetIMMC : std_logic; + signal resetIMBC : std_logic; + signal resetRasterIrq : std_logic; + +-- Character generation + signal charStore: charStoreDef; + signal nextChar : unsigned(11 downto 0); + -- Char/Pixels just coming from memory + signal readChar : unsigned(11 downto 0); + signal readPixels : unsigned(7 downto 0); + -- Char/Pixels pair waiting to be shifted + signal waitingChar : unsigned(11 downto 0); + signal waitingPixels : unsigned(7 downto 0); + -- Stores colorinfo and the Pixels that are currently in shift register + signal shiftingChar : unsigned(11 downto 0); + signal shiftingPixels : unsigned(7 downto 0); + signal shifting_ff : std_logic; -- Multicolor shift-regiter status bit. + +-- Sprite work registers + signal MPtr : unsigned(7 downto 0); -- sprite base pointer + signal MPixels : MPixelsDef; -- Sprite 24 bit shift register + signal MActive : MFlags; -- Sprite is active (derived from MCnt) + signal MCnt : MCntDef; + signal MXE_ff : unsigned(7 downto 0); -- Sprite X expansion flipflop + signal MYE_ff : unsigned(7 downto 0); -- Sprite Y expansion flipflop + signal MC_ff : unsigned(7 downto 0); -- controls sprite shift-register in multicolor + signal MShift : MFlags; -- Sprite is shifting + signal MCurrentPixel : MCurrentPixelDef; + +-- Current colors and pixels + signal pixelColor: ColorDef; + signal pixelBgFlag: std_logic; -- For collision detection + signal pixelDelay: pixelColorStoreDef; + +-- Read/Write lines + signal myWr : std_logic; + signal myRd : std_logic; + +begin +-- ----------------------------------------------------------------------- +-- Ouput signals +-- ----------------------------------------------------------------------- + ba <= baLoc; + vicAddr <= vicAddrReg when registeredAddress else vicAddrLoc; + hSync <= hBlanking; + vSync <= vBlanking; + irq_n <= not IRQ; + +-- ----------------------------------------------------------------------- +-- chip-select signals +-- ----------------------------------------------------------------------- + myWr <= cs and we; + myRd <= cs and rd; + +-- ----------------------------------------------------------------------- +-- debug signals +-- ----------------------------------------------------------------------- + debugX <= rasterX; + debugY <= rasterY; + +-- ----------------------------------------------------------------------- +-- Badline condition +-- ----------------------------------------------------------------------- + process(rasterY, yscroll, rasterEnable) + begin + badLine <= false; + if (rasterY(2 downto 0) = yscroll) + and (rasterEnable = '1') then + badLine <= true; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- BA=low counter +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if baLoc = '0' then + if phi = '0' + and enaData = '1' + and baCnt(2) = '0' then + baCnt <= baCnt + 1; + end if; + else + baCnt <= (others => '0'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Calculate lastLineFlag +-- ----------------------------------------------------------------------- + process(clk) + variable rasterLines : integer range 0 to 312; + begin + if rising_edge(clk) then + lastLineFlag <= false; + + rasterLines := 311; -- PAL + if mode6567old = '1' then + rasterLines := 261; -- NTSC (R7 and earlier have 262 lines) + end if; + if mode6567R8 = '1' then + rasterLines := 262; -- NTSC (R8 and newer have 263 lines) + end if; + if rasterY = rasterLines then + lastLineFlag <= true; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- State machine +-- ----------------------------------------------------------------------- +vicStateMachine: process(clk) + begin + if rising_edge(clk) then + if enaData = '1' + and baSync = '0' then + if phi = '0' then + case vicCycle is + when cycleRefresh1 => + vicCycle <= cycleRefresh2; + if ((mode6567old or mode6567R8) = '1') then + vicCycle <= cycleIdle1; + end if; + when cycleIdle1 => vicCycle <= cycleRefresh2; + when cycleRefresh2 => vicCycle <= cycleRefresh3; + when cycleRefresh3 => vicCycle <= cycleRefresh4; + when cycleRefresh4 => vicCycle <= cycleRefresh5; -- X=0..7 on this cycle + when cycleRefresh5 => vicCycle <= cycleChar; + when cycleChar => + if ((mode6569 = '1') and rasterX(9 downto 3) = "0100111") -- PAL + or ((mode6567old = '1') and rasterX(9 downto 3) = "0100111") -- Old NTSC + or ((mode6567R8 = '1') and rasterX(9 downto 3) = "0101000") -- New NTSC + or ((mode6572 = '1') and rasterX(9 downto 3) = "0101000") then -- PAL-N + vicCycle <= cycleCalcSprites; + end if; + when cycleCalcSprites => vicCycle <= cycleSpriteBa1; + when cycleSpriteBa1 => vicCycle <= cycleSpriteBa2; + when cycleSpriteBa2 => vicCycle <= cycleSpriteBa3; + when others => + null; + end case; + else + case vicCycle is + when cycleSpriteBa3 => vicCycle <= cycleSpriteA; + when cycleSpriteA => + vicCycle <= cycleSpriteB; + when cycleSpriteB => + vicCycle <= cycleSpriteA; + if sprite = 7 then + vicCycle <= cycleRefresh1; + end if; + when others => + null; + end case; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Iterate through all sprites. +-- Only used when state-machine above is in any sprite cycles. +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '1' + and enaData = '1' + and vicCycle = cycleSpriteB + and baSync = '0' then + sprite <= sprite + 1; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Address generator +-- ----------------------------------------------------------------------- + process(phi, vicCycle, sprite, shiftChars, idle, + VM, CB, ECM, BMM, nextChar, colCounter, rowCounter, MPtr, MCnt) + begin + -- + -- Default case ($3FFF fetches) + vicAddrLoc <= (others => '1'); + if (idle = '0') + and shiftChars then + if BMM = '1' then + vicAddrLoc <= CB(13) & colCounter & rowCounter; + else + vicAddrLoc <= CB & nextChar(7 downto 0) & rowCounter; + end if; + end if; + if ECM = '1' then + vicAddrLoc(10 downto 9) <= "00"; + end if; + + case vicCycle is + when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => + if emulateRefresh then + vicAddrLoc <= "111111" & refreshCounter; + else + vicAddrLoc <= (others => '-'); + end if; + when cycleSpriteBa1 | cycleSpriteBa2 | cycleSpriteBa3 => + vicAddrLoc <= (others => '1'); + when cycleSpriteA => + vicAddrLoc <= VM & "1111111" & sprite; + if phi = '1' then + vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + end if; + when cycleSpriteB => + vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + when others => + if phi = '1' then + vicAddrLoc <= VM & colCounter; + end if; + end case; + end process; + + -- Registered address + process(clk) + begin + if rising_edge(clk) then + vicAddrReg <= vicAddrLoc; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Character storage +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if enaData = '1' + and shiftChars + and phi = '1' then + if badLine then + nextChar(7 downto 0) <= di; + nextChar(11 downto 8) <= diColor; + else + nextChar <= charStore(38); + end if; + charStore <= charStore(37 downto 0) & nextChar; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite base pointer (MPtr) +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' + and enaData = '1' + and vicCycle = cycleSpriteA then + MPtr <= (others => '1'); + if MActive(to_integer(sprite)) then + MPtr <= di; + end if; + + -- If refresh counter is not emulated we don't care about + -- MPtr having the correct value in idle state. + if not emulateRefresh then + MPtr <= di; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Refresh counter +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + vicRefresh <= '0'; + case vicCycle is + when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => + vicRefresh <= '1'; + if phi = '0' + and enaData = '1' + and baSync = '0' then + refreshCounter <= refreshCounter - 1; + end if; + when others => + null; + end case; + if lastLineFlag then + refreshCounter <= (others => '1'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Generate Raster Enable +-- ----------------------------------------------------------------------- + process(clk) + begin + -- Enable screen and character display. + -- This is only possible in line 48 on the VIC-II. + -- On other lines any DEN changes are ignored. + if rising_edge(clk) then + if (rasterY = 48) and (DEN = '1') then + rasterEnable <= '1'; + end if; + if (rasterY = 248) then + rasterEnable <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- BA generator (Text/Bitmap) +-- ----------------------------------------------------------------------- +-- +-- For Text/Bitmap BA goes low 3 cycles before real access. So BA starts +-- going low during refresh2 state. See diagram below for timing: +-- +-- X 0 0 0 0 0 +-- 0 0 0 0 1 +-- 0 4 8 C 0 +-- +-- phi ___ ___ ___ ___ ___ ___ ___ ___... +-- ___ ___ ___ ___ ___ ___ ___ ... +-- +-- | | | | | | |... +-- rfr2 rfr3 rfr4 rfr5 char1 char2 char3 +-- +-- BA _______ +-- \\\_______________________________________ +-- | 1 | 2 | 3 | +-- +-- BACnt 000 001 | 010 | 011 | 100 100 100 ... +-- +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' then + baChars <= '1'; + case vicCycle is + when cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => + if badLine then + baChars <= '0'; + end if; + when others => + if rasterX(9 downto 3) < "0101000" + and badLine then + baChars <= '0'; + end if; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- BA generator (Sprites) +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' then + if sprite = 1 then + baSprite04 <= '1'; + end if; + if sprite = 2 then + baSprite15 <= '1'; + end if; + if sprite = 3 then + baSprite26 <= '1'; + end if; + if sprite = 4 then + baSprite37 <= '1'; + end if; + if sprite = 5 then + baSprite04 <= '1'; + end if; + if sprite = 6 then + baSprite15 <= '1'; + end if; + if sprite = 7 then + baSprite26 <= '1'; + end if; + if vicCycle = cycleRefresh1 then + baSprite37 <= '1'; + end if; + + if MActive(0) and (vicCycle = cycleCalcSprites) then + baSprite04 <= '0'; + end if; + if MActive(1) and (vicCycle = cycleSpriteBa2) then + baSprite15 <= '0'; + end if; + if MActive(2) and (vicCycle = cycleSpriteB) and (sprite = 0) then + baSprite26 <= '0'; + end if; + if MActive(3) and (vicCycle = cycleSpriteB) and (sprite = 1) then + baSprite37 <= '0'; + end if; + if MActive(4) and (vicCycle = cycleSpriteB) and (sprite = 2) then + baSprite04 <= '0'; + end if; + if MActive(5) and (vicCycle = cycleSpriteB) and (sprite = 3) then + baSprite15 <= '0'; + end if; + if MActive(6) and (vicCycle = cycleSpriteB) and (sprite = 4) then + baSprite26 <= '0'; + end if; + if MActive(7) and (vicCycle = cycleSpriteB) and (sprite = 5) then + baSprite37 <= '0'; + end if; + end if; + end if; + end process; + baLoc <= baChars and baSprite04 and baSprite15 and baSprite26 and baSprite37; + +-- ----------------------------------------------------------------------- +-- Address valid? +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + addrValid <= '0'; + if phi = '0' + or baCnt(2) = '1' then + addrValid <= '1'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Generate ShiftChars flag +-- ----------------------------------------------------------------------- + process(rasterX) + begin + shiftChars <= false; + if rasterX(9 downto 3) > "0000000" + and rasterX(9 downto 3) < "0101001" then + shiftChars <= true; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- RowCounter and ColCounter +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' + and enaData = '1' + and baSync = '0' then + if shiftChars + and idle = '0' then + colCounter <= colCounter + 1; + end if; + case vicCycle is + when cycleRefresh4 => + colCounter <= colRestart; + if badline then + rowCounter <= (others => '0'); + end if; + when cycleSpriteA => + if sprite = "000" then + if rowCounter = 7 then + colRestart <= colCounter; + idle <= '1'; + else + rowCounter <= rowCounter + 1; + end if; + if badline then + rowCounter <= rowCounter + 1; + end if; + end if; + when others => + null; + end case; + if lastLineFlag then + -- Reset column counter outside visible range. + colRestart <= (others => '0'); + end if; + + -- Set display mode (leave idle-mode) as soon as + -- there is a badline condition. + if badline then + idle <= '0'; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- X/Y Raster counter +-- ----------------------------------------------------------------------- +rasterCounters: process(clk) + begin + if rising_edge(clk) then + if enaPixel = '1' then + rasterX(2 downto 0) <= rasterX(2 downto 0) + 1; + end if; + if phi = '0' + and enaData = '1' + and baSync = '0' then + rasterX(9 downto 3) <= rasterX(9 downto 3) + 1; + rasterX(2 downto 0) <= (others => '0'); + if vicCycle = cycleRefresh4 then + rasterX <= (others => '0'); + end if; + end if; + if phi = '1' + and enaData = '1' + and baSync = '0' then + beyondFrameFlag <= false; + if (vicCycle = cycleSpriteB) + and (sprite = 2) then + rasterY <= rasterY + 1; + beyondFrameFlag <= lastLineFlag; + end if; + if beyondFrameFlag then + rasterY <= (others => '0'); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Raster IRQ +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '1' + and enaData = '1' + and baSync = '0' + and (vicCycle = cycleSpriteB) + and (sprite = 2) then + rasterIrqDone <= '0'; + end if; + if resetRasterIrq = '1' then + IRST <= '0'; + end if; + if (rasterIrqDone = '0') + and (rasterY = rasterCmp) then + rasterIrqDone <= '1'; + IRST <= '1'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Light pen +-- ----------------------------------------------------------------------- +-- On a negative edge on the LP input, the current position of the raster beam +-- is latched in the registers LPX ($d013) and LPY ($d014). LPX contains the +-- upper 8 bits (of 9) of the X position and LPY the lower 8 bits (likewise of +-- 9) of the Y position. So the horizontal resolution of the light pen is +-- limited to 2 pixels. + +-- Only one negative edge on LP is recognized per frame. If multiple edges +-- occur on LP, all following ones are ignored. The trigger is not released +-- until the next vertical blanking interval. +-- ----------------------------------------------------------------------- +lightPen: process(clk) + begin + if rising_edge(clk) then + if emulateLightpen then + if resetLightPenIrq = '1' then + -- Reset light pen interrupt + ILP <= '0'; + end if; + if lastLineFlag then + -- Reset lightpen state at beginning of frame + lightPenHit <= '0'; + elsif (lightPenHit = '0') and (lp_n = '0') then + -- One hit/frame + lightPenHit <= '1'; + -- Toggle Interrupt + ILP <= '1'; + -- Store position of beam + lpx <= rasterX(8 downto 1); + lpy <= rasterY(7 downto 0); + end if; + else + ILP <= '0'; + lpx <= (others => '1'); + lpy <= (others => '1'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- VSync +-- ----------------------------------------------------------------------- +doVBlanking: process(clk, mode6569, mode6567old, mode6567R8) + variable rasterBlank : integer range 0 to 300; + begin + rasterBlank := 300; + if (mode6567old or mode6567R8) = '1' then + rasterBlank := 12; + end if; + if rising_edge(clk) then + vBlanking <= '0'; + if rasterY = rasterBlank then + vBlanking <= '1'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- HSync +-- ----------------------------------------------------------------------- +doHBlanking: process(clk) + begin + if rising_edge(clk) then + if sprite = 3 then + hBlack <= '1'; + end if; + if vicCycle = cycleRefresh1 then + hBlack <= '0'; + end if; + if sprite = 3 then -- dar 5 then + hBlanking <= '1'; + else + hBlanking <= '0'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Borders +-- ----------------------------------------------------------------------- +calcBorders: process(clk) + variable newTBBorder: std_logic; + begin + if rising_edge(clk) then + if enaPixel = '1' then + -- + -- Calc top/bottom border + newTBBorder := TBBorder; +-- if (rasterY = 55) and (RSEL = '0') and (rasterEnable = '1') then + if (rasterY = 55) and (rasterEnable = '1') then + newTBBorder := '0'; + end if; + if (rasterY = 51) and (RSEL = '1') and (rasterEnable = '1') then + newTBBorder := '0'; + end if; + if (rasterY = 247) and (RSEL = '0') then + newTBBorder := '1'; + end if; + if (rasterY = 251) and (RSEL = '1') then + newTBBorder := '1'; + end if; + + -- + -- Calc left/right border + if (rasterX = (31+1)) and (CSEL = '0') then + LRBorder <= newTBBorder; + TBBorder <= newTBBorder; + end if; + if (rasterX = (24+1)) and (CSEL = '1') then + LRBorder <= newTBBorder; + TBBorder <= newTBBorder; + end if; + if (rasterX = (335+1)) and (CSEL = '0') then + LRBorder <= '1'; + end if; + if (rasterX = (344+1)) and (CSEL = '1') then + LRBorder <= '1'; + end if; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Pixel generator for Text/Bitmap screen +-- ----------------------------------------------------------------------- +calcBitmap: process(clk) + variable multiColor : std_logic; + begin + if rising_edge(clk) then + if enaPixel = '1' then + -- + -- Toggle flipflop for multicolor 2-bits shift. + shifting_ff <= not shifting_ff; + + -- + -- Multicolor mode is active with MCM, but for character + -- mode it depends on bit3 of color ram too. + multiColor := MCM and (BMM or ECM or shiftingChar(11)); + + -- + -- Reload shift register when xscroll=rasterX + -- otherwise shift pixels + if xscroll = rasterX(2 downto 0) then + shifting_ff <= '0'; + shiftingChar <= waitingChar; + shiftingPixels <= waitingPixels; + elsif multiColor = '0' then + shiftingPixels <= shiftingPixels(6 downto 0) & '0'; + elsif shifting_ff = '1' then + shiftingPixels <= shiftingPixels(5 downto 0) & "00"; + end if; + + -- + -- Calculate if pixel is in foreground or background + pixelBgFlag <= shiftingPixels(7); + + -- + -- Calculate color of next pixel + pixelColor <= B0C; + if (BMM = '0') and (ECM='0') then + if (multiColor = '0') then + -- normal character mode + if shiftingPixels(7) = '1' then + pixelColor <= shiftingChar(11 downto 8); + end if; + else + -- multi-color character mode + case shiftingPixels(7 downto 6) is + when "01" => pixelColor <= B1C; + when "10" => pixelColor <= B2C; + when "11" => pixelColor <= '0' & shiftingChar(10 downto 8); + when others => null; + end case; + end if; + elsif (MCM = '0') and (BMM = '0') and (ECM='1') then + -- extended-color character mode + -- multiple background colors but only 64 characters + if shiftingPixels(7) = '1' then + pixelColor <= shiftingChar(11 downto 8); + else + case shiftingChar(7 downto 6) is + when "01" => pixelColor <= B1C; + when "10" => pixelColor <= B2C; + when "11" => pixelColor <= B3C; + when others => null; + end case; + end if; + elsif emulateGraphics and (MCM = '0') and (BMM = '1') and (ECM='0') then + -- highres bitmap mode + if shiftingPixels(7) = '1' then + pixelColor <= shiftingChar(7 downto 4); + else + pixelColor <= shiftingChar(3 downto 0); + end if; + elsif emulateGraphics and (MCM = '1') and (BMM = '1') and (ECM='0') then + -- Multi-color bitmap mode + case shiftingPixels(7 downto 6) is + when "01" => pixelColor <= shiftingChar(7 downto 4); + when "10" => pixelColor <= shiftingChar(3 downto 0); + when "11" => pixelColor <= shiftingChar(11 downto 8); + when others => null; + end case; + else + -- illegal display mode, the output is black + pixelColor <= "0000"; + end if; + end if; + + -- + -- Store fetched pixels, until current pixels are displayed + -- and shift-register is empty. + if enaData = '1' + and phi = '0' then + readPixels <= (others => '0'); + if shiftChars then + readPixels <= di; + readChar <= (others => '0'); + if idle = '0' then + readChar <= nextChar; + end if; + end if; + -- Store the characters until shiftregister is empty + waitingPixels <= readPixels; + waitingChar <= readChar; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Which sprites are active? +-- ----------------------------------------------------------------------- + process(MCnt) + begin + for i in 0 to 7 loop + MActive(i) <= false; + if MCnt(i) /= 63 then + MActive(i) <= true; + end if; + end loop; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite byte counter +-- Y expansion flipflop +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' + and enaData = '1' then + case vicCycle is + when cycleRefresh5 => + for i in 0 to 7 loop + MYE_ff(i) <= not MYE_ff(i); + if MActive(i) then + if MYE_ff(i) = MYE(i) then + MCnt(i) <= MCnt(i) + 1; + else + MCnt(i) <= MCnt(i) - 2; + end if; + end if; + end loop; + when others => + null; + end case; + end if; + for i in 0 to 7 loop + if MYE(i) = '0' + or not MActive(i) then + MYE_ff(i) <= '0'; + end if; + end loop; + + -- + -- On cycleCalcSprite check for each inactive sprite if + -- there is a Y match. Reset MCnt if this is so. + -- + -- The RasterX counter is used here to multiplex the compare logic. + -- This saves a few logic cells in the FPGA. + if vicCycle = cycleCalcSprites then + if (not MActive(to_integer(RasterX(2 downto 0)))) + and (ME(to_integer(RasterX(2 downto 0))) = '1') + and (rasterY(7 downto 0) = MY(to_integer(RasterX(2 downto 0)))) then + MCnt(to_integer(RasterX(2 downto 0))) <= (others => '0'); + end if; + end if; + -- + -- Original non-multiplexed version +-- if vicCycle = cycleCalcSprites then +-- for i in 0 to 7 loop +-- if (not MActive(i)) +-- and (ME(i) = '1') +-- and (rasterY(7 downto 0) = MY(i)) then +-- MCnt(i) <= (others => '0'); +-- end if; +-- end loop; +-- end if; + + -- + -- Increment MCnt after fetching data. + if enaData = '1' then + if (vicCycle = cycleSpriteA and phi = '1') + or (vicCycle = cycleSpriteB and phi = '0') then + if MActive(to_integer(sprite)) then + MCnt(to_integer(sprite)) <= MCnt(to_integer(sprite)) + 1; + end if; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite pixel Shift register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if enaPixel = '1' then + -- Enable sprites on the correct X position + for i in 0 to 7 loop + if rasterX = MX(i) then + MShift(i) <= true; + end if; + end loop; + + -- Shift one pixel of the sprite from the shift register. + for i in 0 to 7 loop + if MShift(i) then + MXE_ff(i) <= (not MXE_ff(i)) and MXE(i); + if MXE_ff(i) = '0' then + MC_ff(i) <= (not MC_ff(i)) and MC(i); + if MC_ff(i) = '0' then + MCurrentPixel(i) <= MPixels(i)(23 downto 22); + end if; + MPixels(i) <= MPixels(i)(22 downto 0) & '0'; + end if; + else + MXE_ff(i) <= '0'; + MC_ff(i) <= '0'; + MCurrentPixel(i) <= "00"; + end if; + end loop; + end if; + + -- + -- Fill Sprite shift-register with new data. + if enaData = '1' then + if phi = '0' + and vicCycle = cycleSpriteA then + MShift(to_integer(sprite)) <= false; + end if; + + if Mactive(to_integer(sprite)) then + if phi = '0' then + case vicCycle is + when cycleSpriteB => + MPixels(to_integer(sprite)) <= MPixels(to_integer(sprite))(15 downto 0) & di; + when others => null; + end case; + else + case vicCycle is + when cycleSpriteA | cycleSpriteB => + MPixels(to_integer(sprite)) <= MPixels(to_integer(sprite))(15 downto 0) & di; + when others => null; + end case; + end if; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Video output +-- ----------------------------------------------------------------------- + process(clk) + variable myColor: unsigned(3 downto 0); + variable muxSprite : unsigned(2 downto 0); + variable muxColor : unsigned(1 downto 0); + -- 00 = pixels + -- 01 = MM0 + -- 10 = Sprite + -- 11 = MM1 + begin + if rising_edge(clk) then + muxColor := "00"; + muxSprite := (others => '-'); + for i in 7 downto 0 loop + if (MPRIO(i) = '0') or (pixelBgFlag = '0') then + if MC(i) = '1' then + if MCurrentPixel(i) /= "00" then + muxColor := MCurrentPixel(i); + muxSprite := to_unsigned(i, 3); + end if; + elsif MCurrentPixel(i)(1) = '1' then + muxColor := "10"; + muxSprite := to_unsigned(i, 3); + end if; + end if; + end loop; + + myColor := pixelColor; + case muxColor is + when "01" => myColor := MM0; + when "10" => myColor := spriteColors(to_integer(muxSprite)); + when "11" => myColor := MM1; + when others => + null; + end case; + + +-- myColor := pixelColor; +-- for i in 7 downto 0 loop +-- if (MPRIO(i) = '0') or (pixelBgFlag = '0') then +-- if MC(i) = '1' then +-- case MCurrentPixel(i) is +-- when "01" => myColor := MM0; +-- when "10" => myColor := spriteColors(i); +-- when "11" => myColor := MM1; +-- when others => null; +-- end case; +-- elsif MCurrentPixel(i)(1) = '1' then +-- myColor := spriteColors(i); +-- end if; +-- end if; +-- end loop; + + if enaPixel = '1' then + colorIndex <= myColor; + +-- Krestage 3 debugging routine +-- if (cs = '1' and aRegisters = "011100") then +-- colorIndex <= "1111"; +-- end if; + if (LRBorder = '1') or (TBBorder = '1') then + colorIndex <= EC; + end if; + if (hBlack = '1') then + colorIndex <= (others => '0'); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite to sprite collision +-- ----------------------------------------------------------------------- +spriteSpriteCollision: process(clk) + variable collision : unsigned(7 downto 0); + begin + if rising_edge(clk) then + if resetIMMC = '1' then + IMMC <= '0'; + end if; + + if (myRd = '1') + and (aRegisters = "011110") then + M2M <= (others => '0'); + M2Mhit <= '0'; + end if; + + for i in 0 to 7 loop + collision(i) := MCurrentPixel(i)(1); + end loop; + if (collision /= "00000000") + and (collision /= "00000001") + and (collision /= "00000010") + and (collision /= "00000100") + and (collision /= "00001000") + and (collision /= "00010000") + and (collision /= "00100000") + and (collision /= "01000000") + and (collision /= "10000000") + and (TBBorder = '0') then + M2M <= M2M or collision; + + -- Give collision interrupt but only once until clear of register + if M2Mhit = '0' then + IMMC <= '1'; + M2Mhit <= '1'; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite to background collision +-- ----------------------------------------------------------------------- +spriteBackgroundCollision: process(clk) + begin + if rising_edge(clk) then + if resetIMBC = '1' then + IMBC <= '0'; + end if; + + if (myRd = '1') + and (aRegisters = "011111") then + M2D <= (others => '0'); + M2Dhit <= '0'; + end if; + + for i in 0 to 7 loop + if MCurrentPixel(i)(1) = '1' + and pixelBgFlag = '1' + and (TBBorder = '0') then + M2D(i) <= '1'; + + -- Give collision interrupt but only once until clear of register + if M2Dhit = '0' then + IMBC <= '1'; + M2Dhit <= '1'; + end if; + end if; + end loop; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Generate IRQ signal +-- ----------------------------------------------------------------------- + IRQ <= (ILP and ELP) or (IMMC and EMMC) or (IMBC and EMBC) or (IRST and ERST); + +-- ----------------------------------------------------------------------- +-- Krestage 3 hack +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '1' + and enaData = '1' then + MC <= MCDelay; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Write registers +-- ----------------------------------------------------------------------- +writeRegisters: process(clk) + begin + if rising_edge(clk) then + resetLightPenIrq <= '0'; + resetIMMC <= '0'; + resetIMBC <= '0'; + resetRasterIrq <= '0'; + + -- + -- write to registers + if(reset = '1') then + MX(0) <= (others => '0'); + MX(1) <= (others => '0'); + MX(2) <= (others => '0'); + MX(3) <= (others => '0'); + MX(4) <= (others => '0'); + MX(5) <= (others => '0'); + MX(6) <= (others => '0'); + MX(7) <= (others => '0'); + rasterCmp <= (others => '0'); + ECM <= '0'; + BMM <= '0'; + DEN <= '0'; + RSEL <= '0'; + yscroll <= (others => '0'); + ME <= (others => '0'); + RES <= '0'; + MCM <= '0'; + CSEL <= '0'; + xscroll <= (others => '0'); + MYE <= (others => '0'); + VM <= (others => '0'); + CB <= (others => '0'); + resetLightPenIrq <= '0'; + resetIMMC <= '0'; + resetIMBC <= '0'; + resetRasterIrq <= '0'; + ELP <= '0'; + EMMC <= '0'; + EMBC <= '0'; + ERST <= '0'; + MPRIO <= (others => '0'); + MCDelay <= (others => '0'); + MXE <= (others => '0'); + EC <= (others => '0'); + B0C <= (others => '0'); + B1C <= (others => '0'); + B2C <=(others => '0'); + B3C <= (others => '0'); + MM0 <= (others => '0'); + MM1 <= (others => '0'); + spriteColors(0) <= (others => '0'); + spriteColors(1) <= (others => '0'); + spriteColors(2) <= (others => '0'); + spriteColors(3) <= (others => '0'); + spriteColors(4) <= (others => '0'); + spriteColors(5) <= (others => '0'); + spriteColors(6) <= (others => '0'); + spriteColors(7) <= (others => '0'); + + elsif (myWr = '1') then + case aRegisters is + when "000000" => MX(0)(7 downto 0) <= diRegisters; + when "000001" => MY(0) <= diRegisters; + when "000010" => MX(1)(7 downto 0) <= diRegisters; + when "000011" => MY(1) <= diRegisters; + when "000100" => MX(2)(7 downto 0) <= diRegisters; + when "000101" => MY(2) <= diRegisters; + when "000110" => MX(3)(7 downto 0) <= diRegisters; + when "000111" => MY(3) <= diRegisters; + when "001000" => MX(4)(7 downto 0) <= diRegisters; + when "001001" => MY(4) <= diRegisters; + when "001010" => MX(5)(7 downto 0) <= diRegisters; + when "001011" => MY(5) <= diRegisters; + when "001100" => MX(6)(7 downto 0) <= diRegisters; + when "001101" => MY(6) <= diRegisters; + when "001110" => MX(7)(7 downto 0) <= diRegisters; + when "001111" => MY(7) <= diRegisters; + when "010000" => + MX(0)(8) <= diRegisters(0); + MX(1)(8) <= diRegisters(1); + MX(2)(8) <= diRegisters(2); + MX(3)(8) <= diRegisters(3); + MX(4)(8) <= diRegisters(4); + MX(5)(8) <= diRegisters(5); + MX(6)(8) <= diRegisters(6); + MX(7)(8) <= diRegisters(7); + when "010001" => + rasterCmp(8) <= diRegisters(7); + ECM <= diRegisters(6); + BMM <= diRegisters(5); + DEN <= diRegisters(4); + RSEL <= diRegisters(3); + yscroll <= diRegisters(2 downto 0); + when "010010" => + rasterCmp(7 downto 0) <= diRegisters; + when "010101" => + ME <= diRegisters; + when "010110" => + RES <= diRegisters(5); + MCM <= diRegisters(4); + CSEL <= diRegisters(3); + xscroll <= diRegisters(2 downto 0); + + when "010111" => MYE <= diRegisters; + when "011000" => + VM <= diRegisters(7 downto 4); + CB <= diRegisters(3 downto 1); + when "011001" => + resetLightPenIrq <= diRegisters(3); + resetIMMC <= diRegisters(2); + resetIMBC <= diRegisters(1); + resetRasterIrq <= diRegisters(0); + when "011010" => + ELP <= diRegisters(3); + EMMC <= diRegisters(2); + EMBC <= diRegisters(1); + ERST <= diRegisters(0); + when "011011" => MPRIO <= diRegisters; + when "011100" => + -- MC <= diRegisters; + MCDelay <= diRegisters; -- !!! Krestage 3 hack + when "011101" => MXE <= diRegisters; + when "100000" => EC <= diRegisters(3 downto 0); + when "100001" => B0C <= diRegisters(3 downto 0); + when "100010" => B1C <= diRegisters(3 downto 0); + when "100011" => B2C <= diRegisters(3 downto 0); + when "100100" => B3C <= diRegisters(3 downto 0); + when "100101" => MM0 <= diRegisters(3 downto 0); + when "100110" => MM1 <= diRegisters(3 downto 0); + when "100111" => spriteColors(0) <= diRegisters(3 downto 0); + when "101000" => spriteColors(1) <= diRegisters(3 downto 0); + when "101001" => spriteColors(2) <= diRegisters(3 downto 0); + when "101010" => spriteColors(3) <= diRegisters(3 downto 0); + when "101011" => spriteColors(4) <= diRegisters(3 downto 0); + when "101100" => spriteColors(5) <= diRegisters(3 downto 0); + when "101101" => spriteColors(6) <= diRegisters(3 downto 0); + when "101110" => spriteColors(7) <= diRegisters(3 downto 0); + when others => null; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Read registers +-- ----------------------------------------------------------------------- +readRegisters: process(clk) + begin + if rising_edge(clk) then + case aRegisters is + when "000000" => do <= MX(0)(7 downto 0); + when "000001" => do <= MY(0); + when "000010" => do <= MX(1)(7 downto 0); + when "000011" => do <= MY(1); + when "000100" => do <= MX(2)(7 downto 0); + when "000101" => do <= MY(2); + when "000110" => do <= MX(3)(7 downto 0); + when "000111" => do <= MY(3); + when "001000" => do <= MX(4)(7 downto 0); + when "001001" => do <= MY(4); + when "001010" => do <= MX(5)(7 downto 0); + when "001011" => do <= MY(5); + when "001100" => do <= MX(6)(7 downto 0); + when "001101" => do <= MY(6); + when "001110" => do <= MX(7)(7 downto 0); + when "001111" => do <= MY(7); + when "010000" => + do <= MX(7)(8) & MX(6)(8) & MX(5)(8) & MX(4)(8) + & MX(3)(8) & MX(2)(8) & MX(1)(8) & MX(0)(8); + when "010001" => do <= rasterY(8) & ECM & BMM & DEN & RSEL & yscroll; + when "010010" => do <= rasterY(7 downto 0); + when "010011" => do <= lpX; + when "010100" => do <= lpY; + when "010101" => do <= ME; + when "010110" => do <= "11" & RES & MCM & CSEL & xscroll; + when "010111" => do <= MYE; + when "011000" => do <= VM & CB & '1'; + when "011001" => do <= IRQ & "111" & ILP & IMMC & IMBC & IRST; + when "011010" => do <= "1111" & ELP & EMMC & EMBC & ERST; + when "011011" => do <= MPRIO; + when "011100" => do <= MC; + when "011101" => do <= MXE; + when "011110" => do <= M2M; + when "011111" => do <= M2D; + when "100000" => do <= "1111" & EC; + when "100001" => do <= "1111" & B0C; + when "100010" => do <= "1111" & B1C; + when "100011" => do <= "1111" & B2C; + when "100100" => do <= "1111" & B3C; + when "100101" => do <= "1111" & MM0; + when "100110" => do <= "1111" & MM1; + when "100111" => do <= "1111" & spriteColors(0); + when "101000" => do <= "1111" & spriteColors(1); + when "101001" => do <= "1111" & spriteColors(2); + when "101010" => do <= "1111" & spriteColors(3); + when "101011" => do <= "1111" & spriteColors(4); + when "101100" => do <= "1111" & spriteColors(5); + when "101101" => do <= "1111" & spriteColors(6); + when "101110" => do <= "1111" & spriteColors(7); + when others => do <= (others => '1'); + end case; + end if; + end process; +end architecture; diff --git a/Commodore - 64_Mist/rtl/video_vicII_656x_e.vhd b/Commodore - 64_Mist/rtl/video_vicII_656x_e.vhd new file mode 100644 index 00000000..86eedc63 --- /dev/null +++ b/Commodore - 64_Mist/rtl/video_vicII_656x_e.vhd @@ -0,0 +1,73 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- VIC-II - Video Interface Chip no 2 +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity video_vicii_656x is + generic ( + registeredAddress : boolean; + emulateRefresh : boolean := false; + emulateLightpen : boolean := false; + emulateGraphics : boolean := true + ); + port ( + clk: in std_logic; + -- phi = 0 is VIC cycle + -- phi = 1 is CPU cycle (only used by VIC when BA is low) + phi : in std_logic; + enaData : in std_logic; + enaPixel : in std_logic; + + baSync : in std_logic; + ba: out std_logic; + + mode6569 : in std_logic; -- PAL 63 cycles and 312 lines + mode6567old : in std_logic; -- old NTSC 64 cycles and 262 line + mode6567R8 : in std_logic; -- new NTSC 65 cycles and 263 line + mode6572 : in std_logic; -- PAL-N 65 cycles and 312 lines + + reset : in std_logic; + cs : in std_logic; + we : in std_logic; + rd : in std_logic; + lp_n : in std_logic; + + aRegisters: in unsigned(5 downto 0); + diRegisters: in unsigned(7 downto 0); + + di: in unsigned(7 downto 0); + diColor: in unsigned(3 downto 0); + do: out unsigned(7 downto 0); + + vicAddr: out unsigned(13 downto 0); + irq_n: out std_logic; + + -- Video output + hSync : out std_logic; + vSync : out std_logic; + colorIndex : out unsigned(3 downto 0); + + -- Debug outputs + debugX : out unsigned(9 downto 0); + debugY : out unsigned(8 downto 0); + vicRefresh : out std_logic; + addrValid : out std_logic + ); +end entity; + diff --git a/Commodore - Pet2001_MiST/Pet2001.qpf b/Commodore - Pet2001_MiST/Pet2001.qpf new file mode 100644 index 00000000..bf0dbc76 --- /dev/null +++ b/Commodore - Pet2001_MiST/Pet2001.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 10:56:12 January 03, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "10:56:12 January 03, 2017" + +# Revisions + +PROJECT_REVISION = "Pet2001" diff --git a/Commodore - Pet2001_MiST/Pet2001.qsf b/Commodore - Pet2001_MiST/Pet2001.qsf new file mode 100644 index 00000000..a99b9bc2 --- /dev/null +++ b/Commodore - Pet2001_MiST/Pet2001.qsf @@ -0,0 +1,329 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 08:30:59 December 07, 2015 +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Pet2001 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON + +# Fitter Assignments +# ================== +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------ +# start ENTITY(pet2001_mist) + +# Pin & Location Assignments +# ========================== +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] + +# Fitter Assignments +# ================== +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 + +# end ENTITY(pet2001_mist) +# ---------------------- +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/via6522.v +set_global_assignment -name VERILOG_FILE rtl/tape.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sram.sv +set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VERILOG_FILE rtl/pia6520.v +set_global_assignment -name VERILOG_FILE rtl/pet2001vram.v +set_global_assignment -name VERILOG_FILE rtl/pet2001video.v +set_global_assignment -name VERILOG_FILE rtl/pet2001rom.v +set_global_assignment -name VERILOG_FILE rtl/pet2001ram.v +set_global_assignment -name VERILOG_FILE rtl/pet2001io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/pet2001hw.sv +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/cpu65xx_fast.vhd +set_global_assignment -name VHDL_FILE rtl/cpu65xx_e.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pet2001.sv +set_global_assignment -name CDF_FILE output_files/Chain1.cdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Commodore - Pet2001_MiST/Pet2001.sdc b/Commodore - Pet2001_MiST/Pet2001.sdc new file mode 100644 index 00000000..3eba3b05 --- /dev/null +++ b/Commodore - Pet2001_MiST/Pet2001.sdc @@ -0,0 +1,33 @@ +#************************************************************ +# THIS IS A WIZARD-GENERATED FILE. +# +# Version 13.1.4 Build 182 03/12/2014 SJ Full Version +# +#************************************************************ + +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +# Clock constraints + +create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}] +create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty diff --git a/Commodore - Pet2001_MiST/clean.bat b/Commodore - Pet2001_MiST/clean.bat new file mode 100644 index 00000000..83fb0c47 --- /dev/null +++ b/Commodore - Pet2001_MiST/clean.bat @@ -0,0 +1,15 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +del *.ddb +pause diff --git a/Commodore - Pet2001_MiST/release/Pet2001.rbf b/Commodore - Pet2001_MiST/release/Pet2001.rbf new file mode 100644 index 00000000..5a5844d3 Binary files /dev/null and b/Commodore - Pet2001_MiST/release/Pet2001.rbf differ diff --git a/Commodore - Pet2001_MiST/rtl/Pet2001.sv b/Commodore - Pet2001_MiST/rtl/Pet2001.sv new file mode 100644 index 00000000..92912118 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/Pet2001.sv @@ -0,0 +1,301 @@ +`timescale 1ns / 1ps +//Pet2001 Mist Toplevel 2017 Gehstock + +module Pet2001 +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + + +////////////////////////////////////////////////////////////////////// +// MiST I/O // +////////////////////////////////////////////////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +`include "rtl\build_id.v" + +localparam CONF_STR = +{ + "PET2001;TAPPRG;", + "O78,TAP mode,Fast,Normal,Normal+Sound;", + "O9A,CPU Speed,Normal,x2,x4,x8;", + "O2,Screen Color,White,Green;", + "O3,Diag,Off,On(needs Reset);", + "O56,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T7,Reset;", + "V,v0.61.",`BUILD_DATE + +}; + +wire ioctl_download; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .ps2_caps_led (shift_lock ), + .status (status ), + .ioctl_download (ioctl_download ), + .ioctl_index (ioctl_index ), + .ioctl_wr (ioctl_wr ), + .ioctl_addr (ioctl_addr ), + .ioctl_dout (ioctl_dout ) +); + + +////////////////////////////////////////////////////////////////////// +// Global Clock and System Reset. // +////////////////////////////////////////////////////////////////////// + +wire clk, sdram_clk; +wire locked; + +pll pll +( + .inclk0(CLOCK_27), + .c0(sdram_clk), //112Mhz + .c1(SDRAM_CLK), //112Mhz + .c2(clk), //56MHz + .locked(locked) +); + +reg reset = 1; +wire RESET = status[0] | buttons[1] | status[7]; +always @(posedge clk) begin + integer initRESET = 20000000; + reg [3:0] reset_cnt; + + if ((!RESET && reset_cnt==4'd14) && !initRESET) + reset <= 0; + else begin + if(initRESET) initRESET <= initRESET - 1; + reset <= 1; + reset_cnt <= reset_cnt+4'd1; + end +end + + +//////////////////////////////////////////////////////////////////// +// Clocks +//////////////////////////////////////////////////////////////////// + +reg ce_7mp; +reg ce_7mn; +reg ce_1m; +wire [6:0] cpu_rates[4] = '{55, 27, 13, 6}; + +always @(negedge clk) begin + reg [4:0] div = 0; + reg [6:0] cpu_div = 0; + reg [6:0] cpu_rate = 55; + + div <= div + 1'd1; + ce_7mp <= !div[2] & !div[1:0]; + ce_7mn <= div[2] & !div[1:0]; + + cpu_div <= cpu_div + 1'd1; + if(cpu_div == cpu_rate) begin + cpu_div <= 0; + cpu_rate <= (tape_active && !status[8:7]) ? 7'd2 : cpu_rates[status[10:9]]; + end + ce_1m <= ~(tape_active & ~ram_ready) && !cpu_div; +end + + +/////////////////////////////////////////////////// +// RAM +/////////////////////////////////////////////////// + +wire ram_ready; + +sram ram +( + .*, + .clk(sdram_clk), + .init(~locked), + .dout(tape_data), + .din (ioctl_dout), + .addr(ioctl_download ? ioctl_addr : tape_addr), + .wtbt(0), + .we( ioctl_download && ioctl_wr && (ioctl_index == 1)), + .rd(!ioctl_download && tape_rd), + .ready(ram_ready) +); + + +/////////////////////////////////////////////////// +// CPU +/////////////////////////////////////////////////// + +wire [15:0] addr; +wire [7:0] cpu_data_out; +wire [7:0] cpu_data_in; + +wire we; +wire irq; + +cpu6502 cpu +( + .clk(clk), + .ce(ce_1m), + .reset(reset), + .nmi(0), + .irq(irq), + .din(cpu_data_in), + .dout(cpu_data_out), + .addr(addr), + .we(we) +); + + +/////////////////////////////////////////////////// +// Commodore Pet hardware +/////////////////////////////////////////////////// + +wire pix; +wire HSync, VSync; +wire audioDat; + +pet2001hw hw +( + .*, + .data_out(cpu_data_in), + .data_in(cpu_data_out), + + .cass_motor_n(), + .cass_write(tape_write), + .audio(audioDat), + .cass_sense_n(0), + .cass_read(tape_audio), + .diag_l(!status[3]), + + .dma_addr(dma_off[13:0]+ioctl_addr[13:0]-2'd2), + .dma_din(ioctl_dout), + .dma_dout(), + .dma_we(ioctl_wr && ioctl_download && (ioctl_index == 8'h41) && (ioctl_addr>1)), + + .clk_speed(0), + .clk_stop(0) +); + +reg [15:0] dma_off; +always @(posedge clk) begin + if(ioctl_wr && ioctl_download && (ioctl_index == 8'h41)) begin + if(ioctl_addr == 0) dma_off[7:0] <= ioctl_dout; + if(ioctl_addr == 1) dma_off[15:8] <= ioctl_dout; + end +end + + +//////////////////////////////////////////////////////////////////// +// Video // +//////////////////////////////////////////////////////////////////// + +wire [2:0] G = {3{pix}}; +wire [2:0] R = status[2] ? 3'd0 : G; +wire [2:0] B = R; + +video_mixer #(.LINE_LENGTH(448), .HALF_DEPTH(1)) video_mixer +( + .*, + .clk_sys(clk), + .ce_pix(ce_7mp), + .ce_pix_actual(ce_7mp), + + .scanlines(scandoubler_disable ? 2'b00 : {status[6:5] == 3, status[6:5] == 2}), + .hq2x(status[6:5]==1), + + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + + +//////////////////////////////////////////////////////////////////// +// Audio // +//////////////////////////////////////////////////////////////////// + +assign AUDIO_R = AUDIO_L; +sigma_delta_dac #(.MSBI(1)) dac +( + .CLK(clk), + .RESET(reset), + .DACin({audioDat ^ tape_write, tape_audio & tape_active & (status[8:7] == 2)}), + .DACout(AUDIO_L) +); + +assign LED = ~(tape_led | ioctl_download); + +wire tape_audio; +wire tape_rd; +wire [24:0] tape_addr; +wire [7:0] tape_data; +wire tape_pause = 0; +wire tape_active; +wire tape_write; + +tape tape(.*, .ioctl_download(ioctl_download && (ioctl_index==1))); + +reg [18:0] act_cnt; +wire tape_led = act_cnt[18] ? act_cnt[17:10] <= act_cnt[7:0] : act_cnt[17:10] > act_cnt[7:0]; +always @(posedge clk) if((|status[8:7] ? ce_1m : ce_7mp) && (tape_active || act_cnt[18] || act_cnt[17:0])) act_cnt <= act_cnt + 1'd1; + + +////////////////////////////////////////////////////////////////////// +// PS/2 to PET keyboard interface +////////////////////////////////////////////////////////////////////// +wire [7:0] keyin; +wire [3:0] keyrow; +wire shift_lock; + +keyboard keyboard(.*, .Fn(), .mod()); + +endmodule // pet2001 + diff --git a/Commodore - Pet2001_MiST/rtl/build_id.tcl b/Commodore - Pet2001_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Commodore - Pet2001_MiST/rtl/build_id.v b/Commodore - Pet2001_MiST/rtl/build_id.v new file mode 100644 index 00000000..c05d8a9d --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171120" +`define BUILD_TIME "173612" diff --git a/Commodore - Pet2001_MiST/rtl/cpu65xx_e.vhd b/Commodore - Pet2001_MiST/rtl/cpu65xx_e.vhd new file mode 100644 index 00000000..72e4b6cd --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/cpu65xx_e.vhd @@ -0,0 +1,87 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Interface to 6502/6510 core +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cpu65xx is + generic ( + pipelineOpcode : boolean; + pipelineAluMux : boolean; + pipelineAluOut : boolean + ); + port ( + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + nmi_n : in std_logic; + irq_n : in std_logic; + so_n : in std_logic := '1'; + + di : in unsigned(7 downto 0); + do : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic; + + debugOpcode : out unsigned(7 downto 0); + debugPc : out unsigned(15 downto 0); + debugA : out unsigned(7 downto 0); + debugX : out unsigned(7 downto 0); + debugY : out unsigned(7 downto 0); + debugS : out unsigned(7 downto 0) + ); +end cpu65xx; + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +entity cpu6502 is + port( + clk : in std_logic; + ce : in std_logic; + reset : in std_logic; + nmi : in std_logic; + irq : in std_logic; + din : in unsigned(7 downto 0); + dout : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic + ); +end cpu6502; + +architecture cpu6502 of cpu6502 is +begin + cpuInstance: entity work.cpu65xx(fast) + generic map ( + pipelineOpcode => false, + pipelineAluMux => false, + pipelineAluOut => false + ) + port map ( + clk => clk, + enable=> ce, + reset => reset, + nmi_n => not nmi, + irq_n => not irq, + di => din, + do => dout, + addr => addr, + we => we + ); +end architecture; diff --git a/Commodore - Pet2001_MiST/rtl/cpu65xx_fast.vhd b/Commodore - Pet2001_MiST/rtl/cpu65xx_fast.vhd new file mode 100644 index 00000000..a387b37d --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/cpu65xx_fast.vhd @@ -0,0 +1,1565 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Table driven, cycle exact 6502/6510 core +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +-- Store Zp (3) => fetch, cycle2, cycleEnd +-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd +-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2 +-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd +-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd +-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd +-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd +-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump +-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump +-- Jmp abs (-) => fetch, cycle2, .., cycleJump +-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump +-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4 +-- ----------------------------------------------------------------------- + +architecture fast of cpu65xx is +-- Statemachine + type cpuCycles is ( + opcodeFetch, -- New opcode is read and registers updated + cycle2, + cycle3, + cyclePreIndirect, + cycleIndirect, + cycleBranchTaken, + cycleBranchPage, + cyclePreRead, -- Cycle before read while doing zeropage indexed addressing. + cycleRead, -- Read cycle + cycleRead2, -- Second read cycle after page-boundary crossing. + cycleRmw, -- Calculate ALU output for read-modify-write instr. + cyclePreWrite, -- Cycle before write when doing indexed addressing. + cycleWrite, -- Write cycle for zeropage or absolute addressing. + cycleStack1, + cycleStack2, + cycleStack3, + cycleStack4, + cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr. + cycleEnd + ); + signal theCpuCycle : cpuCycles; + signal nextCpuCycle : cpuCycles; + signal updateRegisters : boolean; + signal processIrq : std_logic; + signal nmiReg: std_logic; + signal nmiEdge: std_logic; + signal irqReg : std_logic; -- Delay IRQ input with one clock cycle. + signal soReg : std_logic; -- SO pin edge detection + +-- Opcode decoding + constant opcUpdateA : integer := 0; + constant opcUpdateX : integer := 1; + constant opcUpdateY : integer := 2; + constant opcUpdateS : integer := 3; + constant opcUpdateN : integer := 4; + constant opcUpdateV : integer := 5; + constant opcUpdateD : integer := 6; + constant opcUpdateI : integer := 7; + constant opcUpdateZ : integer := 8; + constant opcUpdateC : integer := 9; + + constant opcSecondByte : integer := 10; + constant opcAbsolute : integer := 11; + constant opcZeroPage : integer := 12; + constant opcIndirect : integer := 13; + constant opcStackAddr : integer := 14; -- Push/Pop address + constant opcStackData : integer := 15; -- Push/Pop status/data + constant opcJump : integer := 16; + constant opcBranch : integer := 17; + constant indexX : integer := 18; + constant indexY : integer := 19; + constant opcStackUp : integer := 20; + constant opcWrite : integer := 21; + constant opcRmw : integer := 22; + constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS) + constant opcRti : integer := 24; + constant opcIRQ : integer := 25; + + constant opcInA : integer := 26; + constant opcInE : integer := 27; + constant opcInX : integer := 28; + constant opcInY : integer := 29; + constant opcInS : integer := 30; + constant opcInT : integer := 31; + constant opcInH : integer := 32; + constant opcInClear : integer := 33; + constant aluMode1From : integer := 34; + -- + constant aluMode1To : integer := 37; + constant aluMode2From : integer := 38; + -- + constant aluMode2To : integer := 40; + -- + constant opcInCmp : integer := 41; + constant opcInCpx : integer := 42; + constant opcInCpy : integer := 43; + + + subtype addrDef is unsigned(0 to 15); + -- + -- is Interrupt -----------------+ + -- instruction is RTI ----------------+| + -- PC++ on last cycle (RTS) ---------------+|| + -- RMW --------------+||| + -- Write -------------+|||| + -- Pop/Stack up -------------+||||| + -- Branch ---------+ |||||| + -- Jump ----------+| |||||| + -- Push or Pop data -------+|| |||||| + -- Push or Pop addr ------+||| |||||| + -- Indirect -----+|||| |||||| + -- ZeroPage ----+||||| |||||| + -- Absolute ---+|||||| |||||| + -- PC++ on cycle2 --+||||||| |||||| + -- |AZI||JBXY|WM||| + constant immediate : addrDef := "1000000000000000"; + constant implied : addrDef := "0000000000000000"; + -- Zero page + constant readZp : addrDef := "1010000000000000"; + constant writeZp : addrDef := "1010000000010000"; + constant rmwZp : addrDef := "1010000000001000"; + -- Zero page indexed + constant readZpX : addrDef := "1010000010000000"; + constant writeZpX : addrDef := "1010000010010000"; + constant rmwZpX : addrDef := "1010000010001000"; + constant readZpY : addrDef := "1010000001000000"; + constant writeZpY : addrDef := "1010000001010000"; + constant rmwZpY : addrDef := "1010000001001000"; + -- Zero page indirect + constant readIndX : addrDef := "1001000010000000"; + constant writeIndX : addrDef := "1001000010010000"; + constant rmwIndX : addrDef := "1001000010001000"; + constant readIndY : addrDef := "1001000001000000"; + constant writeIndY : addrDef := "1001000001010000"; + constant rmwIndY : addrDef := "1001000001001000"; + -- |AZI||JBXY|WM|| + -- Absolute + constant readAbs : addrDef := "1100000000000000"; + constant writeAbs : addrDef := "1100000000010000"; + constant rmwAbs : addrDef := "1100000000001000"; + constant readAbsX : addrDef := "1100000010000000"; + constant writeAbsX : addrDef := "1100000010010000"; + constant rmwAbsX : addrDef := "1100000010001000"; + constant readAbsY : addrDef := "1100000001000000"; + constant writeAbsY : addrDef := "1100000001010000"; + constant rmwAbsY : addrDef := "1100000001001000"; + -- PHA PHP + constant push : addrDef := "0000010000000000"; + -- PLA PLP + constant pop : addrDef := "0000010000100000"; + -- Jumps + constant jsr : addrDef := "1000101000000000"; + constant jumpAbs : addrDef := "1000001000000000"; + constant jumpInd : addrDef := "1100001000000000"; + constant relative : addrDef := "1000000100000000"; + -- Specials + constant rts : addrDef := "0000101000100100"; + constant rti : addrDef := "0000111000100010"; + constant brk : addrDef := "1000111000000001"; +-- constant : unsigned(0 to 0) := "0"; + constant xxxxxxxx : addrDef := "----------0---00"; + + -- A = accu + -- E = Accu | 0xEE (for ANE, LXA) + -- X = index X + -- Y = index Y + -- S = Stack pointer + -- H = indexH + -- + -- AEXYSTHc + constant aluInA : unsigned(0 to 7) := "10000000"; + constant aluInE : unsigned(0 to 7) := "01000000"; + constant aluInEXT : unsigned(0 to 7) := "01100100"; + constant aluInET : unsigned(0 to 7) := "01000100"; + constant aluInX : unsigned(0 to 7) := "00100000"; + constant aluInXH : unsigned(0 to 7) := "00100010"; + constant aluInY : unsigned(0 to 7) := "00010000"; + constant aluInYH : unsigned(0 to 7) := "00010010"; + constant aluInS : unsigned(0 to 7) := "00001000"; + constant aluInT : unsigned(0 to 7) := "00000100"; + constant aluInAX : unsigned(0 to 7) := "10100000"; + constant aluInAXH : unsigned(0 to 7) := "10100010"; + constant aluInAT : unsigned(0 to 7) := "10000100"; + constant aluInXT : unsigned(0 to 7) := "00100100"; + constant aluInST : unsigned(0 to 7) := "00001100"; + constant aluInSet : unsigned(0 to 7) := "00000000"; + constant aluInClr : unsigned(0 to 7) := "00000001"; + constant aluInXXX : unsigned(0 to 7) := "--------"; + + -- Most of the aluModes are just like the opcodes. + -- aluModeInp -> input is output. calculate N and Z + -- aluModeCmp -> Compare for CMP, CPX, CPY + -- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV + -- aluModeInc -> for INC but also INX, INY + -- aluModeDec -> for DEC but also DEX, DEY + + subtype aluMode1 is unsigned(0 to 3); + subtype aluMode2 is unsigned(0 to 2); + subtype aluMode is unsigned(0 to 9); + + -- Logic/Shift ALU + constant aluModeInp : aluMode1 := "0000"; + constant aluModeP : aluMode1 := "0001"; + constant aluModeInc : aluMode1 := "0010"; + constant aluModeDec : aluMode1 := "0011"; + constant aluModeFlg : aluMode1 := "0100"; + constant aluModeBit : aluMode1 := "0101"; + -- 0110 + -- 0111 + constant aluModeLsr : aluMode1 := "1000"; + constant aluModeRor : aluMode1 := "1001"; + constant aluModeAsl : aluMode1 := "1010"; + constant aluModeRol : aluMode1 := "1011"; + -- 1100 + -- 1101 + -- 1110 + constant aluModeAnc : aluMode1 := "1111"; + + -- Arithmetic ALU + constant aluModePss : aluMode2 := "000"; + constant aluModeCmp : aluMode2 := "001"; + constant aluModeAdc : aluMode2 := "010"; + constant aluModeSbc : aluMode2 := "011"; + constant aluModeAnd : aluMode2 := "100"; + constant aluModeOra : aluMode2 := "101"; + constant aluModeEor : aluMode2 := "110"; + constant aluModeArr : aluMode2 := "111"; + + + constant aluInp : aluMode := aluModeInp & aluModePss & "---"; + constant aluP : aluMode := aluModeP & aluModePss & "---"; + constant aluInc : aluMode := aluModeInc & aluModePss & "---"; + constant aluDec : aluMode := aluModeDec & aluModePss & "---"; + constant aluFlg : aluMode := aluModeFlg & aluModePss & "---"; + constant aluBit : aluMode := aluModeBit & aluModeAnd & "---"; + constant aluRor : aluMode := aluModeRor & aluModePss & "---"; + constant aluLsr : aluMode := aluModeLsr & aluModePss & "---"; + constant aluRol : aluMode := aluModeRol & aluModePss & "---"; + constant aluAsl : aluMode := aluModeAsl & aluModePss & "---"; + + constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100"; + constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010"; + constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001"; + constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---"; + constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---"; + constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---"; + constant aluOra : aluMode := aluModeInp & aluModeOra & "---"; + constant aluEor : aluMode := aluModeInp & aluModeEor & "---"; + + constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---"; + constant aluSre : aluMode := aluModeLsr & aluModeEor & "---"; + constant aluRra : aluMode := aluModeRor & aluModeAdc & "---"; + constant aluRla : aluMode := aluModeRol & aluModeAnd & "---"; + constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100"; + constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---"; + constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---"; + constant aluArr : aluMode := aluModeRor & aluModeArr & "---"; + constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110"; + + constant aluXXX : aluMode := (others => '-'); + + + -- Stack operations. Push/Pop/None + constant stackInc : unsigned(0 to 0) := "0"; + constant stackDec : unsigned(0 to 0) := "1"; + constant stackXXX : unsigned(0 to 0) := "-"; + + subtype decodedBitsDef is unsigned(0 to 43); + type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef; + constant opcodeInfoTable : opcodeInfoTableDef := ( + -- +------- Update register A + -- |+------ Update register X + -- ||+----- Update register Y + -- |||+---- Update register S + -- |||| +-- Update Flags + -- |||| | + -- |||| _|__ + -- |||| / \ + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK + "1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp + "1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp + "0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp + "1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp + "0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP + "1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm + "1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm + "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs + "1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs + "0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs + "1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL + "1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x + "0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x + "0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC + "1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR + "1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x) + "0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp + "1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp + "0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp + "1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp + "0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP + "1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm + "1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm + "0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs + "1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs + "0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs + "1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI + "1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x + "0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC + "1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI + "1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp + "1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp + "0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp + "1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp + "0000" & "000000" & push & aluInA & aluInp, -- 48 PHA + "1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm + "1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu + "1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm + "0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs + "1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs + "0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs + "1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC + "1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x + "0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x + "0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI + "1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS + "1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM *** + "1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp + "1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp + "0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp + "1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp + "1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA + "1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm + "1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu + "1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm + "0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect + "1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs + "0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs + "1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS + "1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x + "1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x + "0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI + "1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm + "0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm + "0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x) + "0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp + "0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp + "0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp + "0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp + "0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm + "1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA + "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm + "0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs + "0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs + "0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs + "0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC + "0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM *** + "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y + "0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x + "0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x + "0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y + "0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y + "1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA + "0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y + "0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS + "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y + "0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x + "0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x + "0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y + "0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm + "1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x) + "0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm + "1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x) + "0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp + "1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp + "0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp + "1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp + "0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY + "1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm + "0100" & "100010" & implied & aluInA & aluInp, -- AA TAX + "1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm + "0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs + "1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs + "0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs + "1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS + "1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM *** + "1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y + "0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x + "1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x + "0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y + "1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y + "0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV + "1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y + "0100" & "100010" & implied & aluInS & aluInp, -- BA TSX + "1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y + "0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x + "1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x + "0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y + "1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm + "0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm + "0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp + "0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp + "0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp + "0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp + "0010" & "100010" & implied & aluInY & aluInc, -- C8 INY + "0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm + "0100" & "100010" & implied & aluInX & aluDec, -- CA DEX + "0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm + "0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs + "0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs + "0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs + "0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE + "0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM *** + "0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x + "0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x + "0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x + "0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD + "0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied + "0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x + "0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm + "1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm + "1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp + "1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp + "0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp + "1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp + "0100" & "100010" & implied & aluInX & aluInc, -- E8 INX + "1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm + "0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP + "1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc) + "0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs + "1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs + "0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs + "1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ + "1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x + "0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x + "1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x + "0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED + "1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x + ); + signal opcInfo : decodedBitsDef; + signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded) + signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined + signal theOpcode : unsigned(7 downto 0); + signal nextOpcode : unsigned(7 downto 0); + +-- Program counter + signal PC : unsigned(15 downto 0); -- Program counter + +-- Address generation + type nextAddrDef is ( + nextAddrHold, + nextAddrIncr, + nextAddrIncrL, -- Increment low bits only (zeropage accesses) + nextAddrIncrH, -- Increment high bits only (page-boundary) + nextAddrDecrH, -- Decrement high bits (branch backwards) + nextAddrPc, + nextAddrIrq, + nextAddrReset, + nextAddrAbs, + nextAddrAbsIndexed, + nextAddrZeroPage, + nextAddrZPIndexed, + nextAddrStack, + nextAddrRelative + ); + signal nextAddr : nextAddrDef; + signal myAddr : unsigned(15 downto 0); + signal myAddrIncr : unsigned(15 downto 0); + signal myAddrIncrH : unsigned(7 downto 0); + signal myAddrDecrH : unsigned(7 downto 0); + signal theWe : std_logic; + + signal irqActive : std_logic; + +-- Output register + signal doReg : unsigned(7 downto 0); + +-- Buffer register + signal T : unsigned(7 downto 0); + +-- General registers + signal A: unsigned(7 downto 0); -- Accumulator + signal X: unsigned(7 downto 0); -- Index X + signal Y: unsigned(7 downto 0); -- Index Y + signal S: unsigned(7 downto 0); -- stack pointer + +-- Status register + signal C: std_logic; -- Carry + signal Z: std_logic; -- Zero flag + signal I: std_logic; -- Interrupt flag + signal D: std_logic; -- Decimal mode + signal V: std_logic; -- Overflow + signal N: std_logic; -- Negative + +-- ALU + -- ALU input + signal aluInput : unsigned(7 downto 0); + signal aluCmpInput : unsigned(7 downto 0); + -- ALU output + signal aluRegisterOut : unsigned(7 downto 0); + signal aluRmwOut : unsigned(7 downto 0); + signal aluC : std_logic; + signal aluZ : std_logic; + signal aluV : std_logic; + signal aluN : std_logic; + -- Pipeline registers + signal aluInputReg : unsigned(7 downto 0); + signal aluCmpInputReg : unsigned(7 downto 0); + signal aluRmwReg : unsigned(7 downto 0); + signal aluNineReg : unsigned(7 downto 0); + signal aluCReg : std_logic; + signal aluZReg : std_logic; + signal aluVReg : std_logic; + signal aluNReg : std_logic; + +-- Indexing + signal indexOut : unsigned(8 downto 0); + +begin +processAluInput: process(clk, opcInfo, A, X, Y, T, S) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInA) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInE) = '1' then + temp := temp and (A or X"EE"); + end if; + if opcInfo(opcInX) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInY) = '1' then + temp := temp and Y; + end if; + if opcInfo(opcInS) = '1' then + temp := temp and S; + end if; + if opcInfo(opcInT) = '1' then + temp := temp and T; + end if; + if opcInfo(opcInClear) = '1' then + temp := (others => '0'); + end if; + if rising_edge(clk) then + aluInputReg <= temp; + end if; + + aluInput <= temp; + if pipelineAluMux then + aluInput <= aluInputReg; + end if; + end process; + +processCmpInput: process(clk, opcInfo, A, X, Y) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInCmp) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInCpx) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInCpy) = '1' then + temp := temp and Y; + end if; + if rising_edge(clk) then + aluCmpInputReg <= temp; + end if; + + aluCmpInput <= temp; + if pipelineAluMux then + aluCmpInput <= aluCmpInputReg; + end if; + end process; + + -- ALU consists of two parts + -- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL + -- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA + -- Some instructions are both RMW and accumulator so for most + -- instructions the rmw results are routed through accu alu too. +processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C) + variable lowBits: unsigned(5 downto 0); + variable nineBits: unsigned(8 downto 0); + variable rmwBits: unsigned(8 downto 0); + + variable varC : std_logic; + variable varZ : std_logic; + variable varV : std_logic; + variable varN : std_logic; + begin + lowBits := (others => '-'); + nineBits := (others => '-'); + rmwBits := (others => '-'); + varV := aluInput(6); -- Default for BIT / PLP / RTI + + -- Shift unit + case opcInfo(aluMode1From to aluMode1To) is + when aluModeInp => + rmwBits := C & aluInput; + when aluModeP => + rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C; + when aluModeInc => + rmwBits := C & (aluInput + 1); + when aluModeDec => + rmwBits := C & (aluInput - 1); + when aluModeAsl => + rmwBits := aluInput & "0"; + when aluModeFlg => + rmwBits := aluInput(0) & aluInput; + when aluModeLsr => + rmwBits := aluInput(0) & "0" & aluInput(7 downto 1); + when aluModeRol => + rmwBits := aluInput & C; + when aluModeRoR => + rmwBits := aluInput(0) & C & aluInput(7 downto 1); + when aluModeAnc => + rmwBits := (aluInput(7) and A(7)) & aluInput; + when others => + rmwBits := C & aluInput; + end case; + + -- ALU + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1"); + ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8)); + when aluModeSbc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1"); + ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8)); + when aluModeCmp => + ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001"; + when aluModeAnd => + ninebits := rmwBits(8) & (A and rmwBits(7 downto 0)); + when aluModeEor => + ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0)); + when aluModeOra => + ninebits := rmwBits(8) & (A or rmwBits(7 downto 0)); + when others => + ninebits := rmwBits; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varZ := rmwBits(1); + elsif ninebits(7 downto 0) = X"00" then + varZ := '1'; + else + varZ := '0'; + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode low bits correction, is done after setting Z flag. + if D = '1' then + if lowBits(5 downto 1) > 9 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + if lowBits(5) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) + 1; + end if; + end if; + end if; + when others => + null; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) + or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varN := rmwBits(7); + else + varN := nineBits(7); + end if; + varC := ninebits(8); + if opcInfo(aluMode2From to aluMode2To) = aluModeArr then + varC := aluInput(7); + varV := aluInput(7) xor aluInput(6); + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode high bits correction, is done after setting Z and N flags + varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7)); + if D = '1' then + if ninebits(8 downto 4) > 9 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + end if; + end if; + when aluModeSbc => + varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7)); + if D = '1' then + -- Check for borrow (lower 4 bits) + if lowBits(5) = '0' then + ninebits(3 downto 0) := ninebits(3 downto 0) - 6; + end if; + -- Check for borrow (upper 4 bits) + if ninebits(8) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) - 6; + end if; + end if; + when aluModeArr => + if D = '1' then + if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + end if; + if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + else + varC := '0'; + end if; + end if; + when others => + null; + end case; + + if rising_edge(clk) then + aluRmwReg <= rmwBits(7 downto 0); + aluNineReg <= ninebits(7 downto 0); + aluCReg <= varC; + aluZReg <= varZ; + aluVReg <= varV; + aluNReg <= varN; + end if; + + aluRmwOut <= rmwBits(7 downto 0); + aluRegisterOut <= ninebits(7 downto 0); + aluC <= varC; + aluZ <= varZ; + aluV <= varV; + aluN <= varN; + if pipelineAluOut then + aluRmwOut <= aluRmwReg; + aluRegisterOut <= aluNineReg; + aluC <= aluCReg; + aluZ <= aluZReg; + aluV <= aluVReg; + aluN <= aluNReg; + end if; + end process; + +calcInterrupt: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = cycleStack4 + or reset = '1' then + nmiReg <= '1'; + end if; + + if nextCpuCycle /= cycleBranchTaken + and nextCpuCycle /= opcodeFetch then + irqReg <= irq_n; + nmiEdge <= nmi_n; + if (nmiEdge = '1') and (nmi_n = '0') then + nmiReg <= '0'; + end if; + end if; + -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ. + -- Presumably this is done in the real 6502/6510 to prevent a double IRQ. + processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ)); + end if; + end if; + end process; + +calcNextOpcode: process(clk, di, reset, processIrq) + variable myNextOpcode : unsigned(7 downto 0); + begin + -- Next opcode is read from input unless a reset or IRQ is pending. + myNextOpcode := di; + if reset = '1' then + myNextOpcode := X"4C"; + elsif processIrq = '1' then + myNextOpcode := X"00"; + end if; + + nextOpcode <= myNextOpcode; + end process; + + nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode)); + process(clk) + begin + if rising_edge(clk) then + nextOpcInfoReg <= nextOpcInfo; + end if; + end process; + + -- Read bits and flags from opcodeInfoTable and store in opcInfo. + -- This info is used to control the execution of the opcode. +calcOpcInfo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if (reset = '1') or (theCpuCycle = opcodeFetch) then + opcInfo <= nextOpcInfo; + if pipelineOpcode then + opcInfo <= nextOpcInfoReg; + end if; + end if; + end if; + end if; + end process; + +calcTheOpcode: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = opcodeFetch then + irqActive <= '0'; + if processIrq = '1' then + irqActive <= '1'; + end if; + -- Fetch opcode + theOpcode <= nextOpcode; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- State machine +-- ----------------------------------------------------------------------- + process(enable, theCpuCycle, opcInfo) + begin + updateRegisters <= false; + if enable = '1' then + if opcInfo(opcRti) = '1' then + if theCpuCycle = cycleRead then + updateRegisters <= true; + end if; + elsif theCpuCycle = opcodeFetch then + updateRegisters <= true; + end if; + end if; + end process; + + debugOpcode <= theOpcode; + process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theCpuCycle <= nextCpuCycle; + end if; + if reset = '1' then + theCpuCycle <= cycle2; + end if; + end if; + end process; + + -- Determine the next cpu cycle. After the last cycle we always + -- go to opcodeFetch to get the next opcode. +calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z) + begin + nextCpuCycle <= opcodeFetch; + + case theCpuCycle is + when opcodeFetch => + nextCpuCycle <= cycle2; + when cycle2 => + if opcInfo(opcBranch) = '1' then + if (N = theOpcode(5) and theOpcode(7 downto 6) = "00") + or (V = theOpcode(5) and theOpcode(7 downto 6) = "01") + or (C = theOpcode(5) and theOpcode(7 downto 6) = "10") + or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then + -- Branch condition is true + nextCpuCycle <= cycleBranchTaken; + end if; + elsif (opcInfo(opcStackUp) = '1') then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackAddr) = '1' + and opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleStack2; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleWrite; + elsif opcInfo(opcAbsolute) = '1' then + nextCpuCycle <= cycle3; + elsif opcInfo(opcIndirect) = '1' then + if opcInfo(indexX) = '1' then + nextCpuCycle <= cyclePreIndirect; + else + nextCpuCycle <= cycleIndirect; + end if; + elsif opcInfo(opcZeroPage) = '1' then + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + else + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreRead; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + elsif opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycle3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + end if; + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + if opcInfo(opcWrite) = '1' then + nextCpuCycle <= cycleWrite; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + when cyclePreIndirect => + nextCpuCycle <= cycleIndirect; + when cycleIndirect => + nextCpuCycle <= cycle3; + when cycleBranchTaken => + if indexOut(8) /= T(7) then + -- Page boundary crossing during branch. + nextCpuCycle <= cycleBranchPage; + end if; + when cyclePreRead => + if opcInfo(opcZeroPage) = '1' then + nextCpuCycle <= cycleRead2; + end if; + when cycleRead => + if opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + elsif indexOut(8) = '1' then + -- Page boundary crossing while indexed addressing. + nextCpuCycle <= cycleRead2; + elsif opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + if opcInfo(indexX) = '1' + or opcInfo(indexY) = '1' then + -- 6510 needs extra cycle for indexed addressing + -- combined with RMW indexing + nextCpuCycle <= cycleRead2; + end if; + end if; + when cycleRead2 => + if opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + end if; + when cycleRmw => + nextCpuCycle <= cycleWrite; + when cyclePreWrite => + nextCpuCycle <= cycleWrite; + when cycleStack1 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack2; + end if; + when cycleStack2 => + nextCpuCycle <= cycleStack3; + if opcInfo(opcRti) = '1' then + nextCpuCycle <= cycleRead; + end if; + if opcInfo(opcStackData) = '0' + and opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycleStack3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackData) = '0' + or opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack4; + end if; + when cycleStack4 => + nextCpuCycle <= cycleRead; + when cycleJump => + if opcInfo(opcIncrAfter) = '1' then + -- Insert extra cycle + nextCpuCycle <= cycleEnd; + end if; + when others => + null; + end case; + end process; + +-- ----------------------------------------------------------------------- +-- T register +-- ----------------------------------------------------------------------- +calcT: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when cycle2 => + T <= di; + when cycleStack1 | cycleStack2 => + if opcInfo(opcStackUp) = '1' then + -- Read from stack + T <= di; + end if; + when cycleIndirect | cycleRead | cycleRead2 => + T <= di; + when others => + null; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- A register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateA) = '1' then + A <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- X register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateX) = '1' then + X <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Y register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateY) = '1' then + Y <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- C flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateC) = '1' then + C <= aluC; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Z flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateZ) = '1' then + Z <= aluZ; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- I flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateI) = '1' then + I <= aluInput(2); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- D flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateD) = '1' then + D <= aluInput(3); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- V flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateV) = '1' then + V <= aluV; + end if; + end if; + if enable = '1' then + if soReg = '1' and so_n = '0' then + V <= '1'; + end if; + soReg <= so_n; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- N flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateN) = '1' then + N <= aluN; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Stack pointer +-- ----------------------------------------------------------------------- + process(clk) + variable sIncDec : unsigned(7 downto 0); + variable updateFlag : boolean; + begin + if rising_edge(clk) then + + if opcInfo(opcStackUp) = '1' then + sIncDec := S + 1; + else + sIncDec := S - 1; + end if; + + if enable = '1' then + updateFlag := false; + case nextCpuCycle is + when cycleStack1 => + if (opcInfo(opcStackUp) = '1') + or (opcInfo(opcStackData) = '1') then + updateFlag := true; + end if; + when cycleStack2 => + updateFlag := true; + when cycleStack3 => + updateFlag := true; + when cycleStack4 => + updateFlag := true; + when cycleRead => + if opcInfo(opcRti) = '1' then + updateFlag := true; + end if; + when cycleWrite => + if opcInfo(opcStackData) = '1' then + updateFlag := true; + end if; + when others => + null; + end case; + if updateFlag then + S <= sIncDec; + end if; + end if; + if updateRegisters then + if opcInfo(opcUpdateS) = '1' then + S <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Data out +-- ----------------------------------------------------------------------- +--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T) +calcDo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + doReg <= aluRmwOut; + if opcInfo(opcInH) = '1' then + -- For illegal opcodes SHA, SHX, SHY, SHS + doReg <= aluRmwOut and myAddrIncrH; + end if; + + case nextCpuCycle is + when cycleStack2 => + if opcInfo(opcIRQ) = '1' + and irqActive = '0' then + doReg <= myAddrIncr(15 downto 8); + else + doReg <= PC(15 downto 8); + end if; + when cycleStack3 => + doReg <= PC(7 downto 0); + when cycleRmw => +-- do <= T; -- Read-modify-write write old value first. + doReg <= di; -- Read-modify-write write old value first. + when others => null; + end case; + end if; + end if; + end process; + do <= doReg; + + + +-- ----------------------------------------------------------------------- +-- Write enable +-- ----------------------------------------------------------------------- +calcWe: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theWe <= '0'; + case nextCpuCycle is + when cycleStack1 => + if opcInfo(opcStackUp) = '0' + and ((opcInfo(opcStackAddr) = '0') + or (opcInfo(opcStackData) = '1')) then + theWe <= '1'; + end if; + when cycleStack2 | cycleStack3 | cycleStack4 => + if opcInfo(opcStackUp) = '0' then + theWe <= '1'; + end if; + when cycleRmw => + theWe <= '1'; + when cycleWrite => + theWe <= '1'; + when others => + null; + end case; + end if; + end if; + end process; + we <= theWe; + +-- ----------------------------------------------------------------------- +-- Program counter +-- ----------------------------------------------------------------------- +calcPC: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when opcodeFetch => + PC <= myAddr; + when cycle2 => + if irqActive = '0' then + if opcInfo(opcSecondByte) = '1' then + PC <= myAddrIncr; + else + PC <= myAddr; + end if; + end if; + when cycle3 => + if opcInfo(opcAbsolute) = '1' then + PC <= myAddrIncr; + end if; + when others => + null; + end case; + end if; + end if; + end process; + debugPc <= PC; + +-- ----------------------------------------------------------------------- +-- Address generation +-- ----------------------------------------------------------------------- +calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset) + begin + nextAddr <= nextAddrIncr; + case theCpuCycle is + when cycle2 => + if opcInfo(opcStackAddr) = '1' + or opcInfo(opcStackData) = '1' then + nextAddr <= nextAddrStack; + elsif opcInfo(opcAbsolute) = '1' then + nextAddr <= nextAddrIncr; + elsif opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcIndirect) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcSecondByte) = '1' then + nextAddr <= nextAddrIncr; + else + nextAddr <= nextAddrHold; + end if; + when cycle3 => + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + nextAddr <= nextAddrAbs; + else + nextAddr <= nextAddrAbsIndexed; + end if; + when cyclePreIndirect => + nextAddr <= nextAddrZPIndexed; + when cycleIndirect => + nextAddr <= nextAddrIncrL; + when cycleBranchTaken => + nextAddr <= nextAddrRelative; + when cycleBranchPage => + if T(7) = '0' then + nextAddr <= nextAddrIncrH; + else + nextAddr <= nextAddrDecrH; + end if; + when cyclePreRead => + nextAddr <= nextAddrZPIndexed; + when cycleRead => + nextAddr <= nextAddrPc; + if opcInfo(opcJump) = '1' then + -- Emulate 6510 bug, jmp(xxFF) fetches from same page. + -- Replace with nextAddrIncr if emulating 65C02 or later cpu. + nextAddr <= nextAddrIncrL; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + elsif opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRead2 => + nextAddr <= nextAddrPc; + if opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRmw => + nextAddr <= nextAddrHold; + when cyclePreWrite => + nextAddr <= nextAddrHold; + if opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZPIndexed; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + end if; + when cycleWrite => + nextAddr <= nextAddrPc; + when cycleStack1 => + nextAddr <= nextAddrStack; + when cycleStack2 => + nextAddr <= nextAddrStack; + when cycleStack3 => + nextAddr <= nextAddrStack; + if opcInfo(opcStackData) = '0' then + nextAddr <= nextAddrPc; + end if; + when cycleStack4 => + nextAddr <= nextAddrIrq; + when cycleJump => + nextAddr <= nextAddrAbs; + when others => + null; + end case; + if reset = '1' then + nextAddr <= nextAddrReset; + end if; + end process; + +indexAlu: process(opcInfo, myAddr, T, X, Y) + begin + if opcInfo(indexX) = '1' then + indexOut <= (B"0" & T) + (B"0" & X); + elsif opcInfo(indexY) = '1' then + indexOut <= (B"0" & T) + (B"0" & Y); + elsif opcInfo(opcBranch) = '1' then + indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0)); + else + indexOut <= B"0" & T; + end if; + end process; + +calcAddr: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case nextAddr is + when nextAddrIncr => myAddr <= myAddrIncr; + when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0); + when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH; + when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH; + when nextAddrPc => myAddr <= PC; + when nextAddrIrq => + myAddr <= X"FFFE"; + if nmiReg = '0' then + myAddr <= X"FFFA"; + end if; + when nextAddrReset => myAddr <= X"FFFC"; + when nextAddrAbs => myAddr <= di & T; + when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0); + when nextAddrZeroPage => myAddr <= "00000000" & di; + when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0); + when nextAddrStack => myAddr <= "00000001" & S; + when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0); + when others => null; + end case; + end if; + end if; + end process; + + myAddrIncr <= myAddr + 1; + myAddrIncrH <= myAddr(15 downto 8) + 1; + myAddrDecrH <= myAddr(15 downto 8) - 1; + + addr <= myAddr; + + debugA <= A; + debugX <= X; + debugY <= Y; + debugS <= S; + +end architecture; + + diff --git a/Commodore - Pet2001_MiST/rtl/hq2x.sv b/Commodore - Pet2001_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Commodore - Pet2001_MiST/rtl/keyboard.sv b/Commodore - Pet2001_MiST/rtl/keyboard.sv new file mode 100644 index 00000000..dbb26c24 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/keyboard.sv @@ -0,0 +1,286 @@ + +module keyboard +( + input reset, + input clk, + + input ps2_kbd_clk, + input ps2_kbd_data, + + input [3:0] keyrow, + output [7:0] keyin, + output reg shift_lock, + + output reg [11:1] Fn = 0, + output reg [2:0] mod = 0 +); + +reg [3:0] prev_clk = 0; +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg [7:0] keys[10]; +reg release_btn = 0; +reg [7:0] code; + +assign keyin = keys[keyrow]; + +reg input_strobe = 0; +wire shift = mod[0]; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + keys[0] <= 8'hFF; + keys[1] <= 8'hFF; + keys[2] <= 8'hFF; + keys[3] <= 8'hFF; + keys[4] <= 8'hFF; + keys[5] <= 8'hFF; + keys[6] <= 8'hFF; + keys[7] <= 8'hFF; + keys[8] <= 8'hFF; + keys[9] <= 8'hFF; + shift_lock <= 0; + end + + if(input_strobe) begin + case(code) + 8'h59: mod[0]<= ~release_btn; // right shift + 8'h12: mod[0]<= ~release_btn; // Left shift + 8'h11: mod[1]<= ~release_btn; // alt + 8'h14: mod[2]<= ~release_btn; // ctrl + 8'h05: Fn[1] <= ~release_btn; // F1 + 8'h06: Fn[2] <= ~release_btn; // F2 + 8'h04: Fn[3] <= ~release_btn; // F3 + 8'h0C: Fn[4] <= ~release_btn; // F4 + 8'h03: Fn[5] <= ~release_btn; // F5 + 8'h0B: Fn[6] <= ~release_btn; // F6 + 8'h83: Fn[7] <= ~release_btn; // F7 + 8'h0A: Fn[8] <= ~release_btn; // F8 + 8'h01: Fn[9] <= ~release_btn; // F9 + 8'h09: Fn[10]<= ~release_btn; // F10 + 8'h78: Fn[11]<= ~release_btn; // F11 + endcase + + case(code) + 'h76: begin + keys[9][4] <= release_btn; // ESC -> STOP + if(~release_btn) keys[8][5] <= 1; + else keys[8][5] <= ~shift_lock; + end + 'h05: begin + keys[9][4] <= release_btn; // F1 -> RUN + if(~release_btn) keys[8][5] <= 0; + else keys[8][5] <= ~shift_lock; + end + 'h06: begin + keys[0][6] <= release_btn; // F2 -> CLR + if(~release_btn) keys[8][5] <= 0; + else keys[8][5] <= ~shift_lock; + end + 'h71: begin + keys[1][7] <= release_btn; // DEL + if(~release_btn) keys[8][5] <= 1; + else keys[8][5] <= ~shift_lock; + end + 'h70: begin + keys[1][7] <= release_btn; // INSERT + if(~release_btn) keys[8][5] <= 0; + else keys[8][5] <= ~shift_lock; + end + 'h6C: begin + keys[0][6] <= release_btn; // HOME + if(~release_btn) keys[8][5] <= 1; + else keys[8][5] <= ~shift_lock; + end + 'h72: begin + keys[1][6] <= release_btn; // DOWN + if(~release_btn) keys[8][5] <= 1; + else keys[8][5] <= ~shift_lock; + end + 'h75: begin + keys[1][6] <= release_btn; // UP + if(~release_btn) keys[8][5] <= 0; + else keys[8][5] <= ~shift_lock; + end + 'h74: begin + keys[0][7] <= release_btn; // RIGHT + if(~release_btn) keys[8][5] <= 1; + else keys[8][5] <= ~shift_lock; + end + 'h6B: begin + keys[0][7] <= release_btn; // LEFT + if(~release_btn) keys[8][5] <= 0; + else keys[8][5] <= ~shift_lock; + end + + 'h58: begin + keys[8][5] <= release_btn ^ shift_lock; // CAPS -> R SHIFT + if(~release_btn) shift_lock <= ~shift_lock; + end + + 'h11: keys[8][5] <= release_btn ^ shift_lock; // ALT -> R SHIFT + 'h14: keys[8][0] <= release_btn; // CTRL -> L SHIFT + 'h1F: keys[9][0] <= release_btn; // L GUI -> REV ON/OFF + 'h5A: keys[6][5] <= release_btn; // RETURN + 'h66: keys[1][7] <= release_btn; // BKSP -> DEL + + 'h1C: keys[4][0] <= release_btn; // a + 'h32: keys[6][2] <= release_btn; // b + 'h21: keys[6][1] <= release_btn; // c + 'h23: keys[4][1] <= release_btn; // d + 'h24: keys[2][1] <= release_btn; // e + 'h2B: keys[5][1] <= release_btn; // f + 'h34: keys[4][2] <= release_btn; // g + 'h33: keys[5][2] <= release_btn; // h + 'h43: keys[3][3] <= release_btn; // i + 'h3B: keys[4][3] <= release_btn; // j + 'h42: keys[5][3] <= release_btn; // k + 'h4B: keys[4][4] <= release_btn; // l + 'h3A: keys[6][3] <= release_btn; // m + 'h31: keys[7][2] <= release_btn; // n + 'h44: keys[2][4] <= release_btn; // o + 'h4D: keys[3][4] <= release_btn; // p + 'h15: keys[2][0] <= release_btn; // q + 'h2D: keys[3][1] <= release_btn; // r + 'h1B: keys[5][0] <= release_btn; // s + 'h2C: keys[2][2] <= release_btn; // t + 'h3C: keys[2][3] <= release_btn; // u + 'h2A: keys[7][1] <= release_btn; // v + 'h1D: keys[3][0] <= release_btn; // w + 'h22: keys[7][0] <= release_btn; // x + 'h35: keys[3][2] <= release_btn; // y + 'h1A: keys[6][0] <= release_btn; // z + + 'h54: keys[9][1] <= release_btn; // [ + 'h5B: keys[8][2] <= release_btn; // ] + 'h5D: keys[1][3] <= release_btn; // \ + 'h29: keys[9][2] <= release_btn; // SPACE + + 'h16: begin + keys[6][6] <= release_btn | shift; // 1 + keys[0][0] <= release_btn | ~shift; // ! + end + + 'h1E: begin + keys[7][6] <= release_btn | shift; // 2 + keys[8][1] <= release_btn | ~shift; // @ + end + + 'h26: begin + keys[6][7] <= release_btn | shift; // 3 + keys[0][1] <= release_btn | ~shift; // # + end + + 'h25: begin + keys[4][6] <= release_btn | shift; // 4 + keys[1][1] <= release_btn | ~shift; // $ + end + + 'h2E: begin + keys[5][6] <= release_btn | shift; // 5 + keys[0][2] <= release_btn | ~shift; // % + end + + 'h36: begin + keys[4][7] <= release_btn | shift; // 6 + keys[2][5] <= release_btn | ~shift; // ^ + end + + 'h3D: begin + keys[2][6] <= release_btn | shift; // 7 + keys[0][3] <= release_btn | ~shift; // & + end + + 'h3E: begin + keys[3][6] <= release_btn | shift; // 8 + keys[5][7] <= release_btn | ~shift; // * + end + + 'h46: begin + keys[2][7] <= release_btn | shift; // 9 + keys[0][4] <= release_btn | ~shift; // ( + end + + 'h45: begin + keys[8][6] <= release_btn | shift; // 0 + keys[1][4] <= release_btn | ~shift; // ) + end + + 'h41: begin + keys[7][3] <= release_btn | shift; // , + keys[9][3] <= release_btn | ~shift; // < + end + + 'h49: begin + keys[9][6] <= release_btn | shift; // . + keys[8][4] <= release_btn | ~shift; // > + end + + 'h4A: begin + keys[3][7] <= release_btn | shift; // / + keys[7][4] <= release_btn | ~shift; // ? + end + + 'h4C: begin + keys[6][4] <= release_btn | shift; // ; + keys[5][4] <= release_btn | ~shift; // : + end + + 'h4E: begin + keys[8][7] <= release_btn | shift; // - + keys[0][5] <= release_btn | ~shift; // _ + end + + 'h52: begin + keys[1][2] <= release_btn | shift; // ' + keys[1][0] <= release_btn | ~shift; // " + end + + 'h55: begin + keys[9][7] <= release_btn | shift; // = + keys[7][7] <= release_btn | ~shift; // + + end + + default:; + endcase + end +end + +always @(posedge clk) begin + reg old_reset = 0; + reg action = 0; + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/mist_io.v b/Commodore - Pet2001_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/osd.v b/Commodore - Pet2001_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/pet2001hw.sv b/Commodore - Pet2001_MiST/rtl/pet2001hw.sv new file mode 100644 index 00000000..3098936b --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pet2001hw.sv @@ -0,0 +1,186 @@ +`timescale 1ns / 1ps +/////////////////////////////////////////////////////////////////////////////// +// +// Engineer: Thomas Skibo +// +// Create Date: Sep 23, 2011 +// +// Module Name: pet2001hw +// +// Description: Encapsulate all Pet hardware except cpu. +// +////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2011, Thomas Skibo. All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * The names of contributors may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL Thomas Skibo OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +// SUCH DAMAGE. +// +////////////////////////////////////////////////////////////////////////////// + +module pet2001hw +( + input [15:0] addr, // CPU Interface + input [7:0] data_in, + output reg [7:0] data_out, + input we, + output irq, + + output pix, + output HSync, + output VSync, + + output [3:0] keyrow, // Keyboard + input [7:0] keyin, + + output cass_motor_n, // Cassette + output cass_write, + input cass_sense_n, + input cass_read, + output audio, // CB2 audio + + input [13:0] dma_addr, + input [7:0] dma_din, + output [7:0] dma_dout, + input dma_we, + + input clk_speed, + input clk_stop, + input diag_l, + input clk, + input ce_7mp, + input ce_7mn, + input ce_1m, + input reset +); + +///////////////////////////////////////////////////////////// +// Pet ROMS incuding character ROM. Character data is read +// out second port. This brings total ROM to 16K which is +// easy to arrange. +///////////////////////////////////////////////////////////// +wire [7:0] rom_data; + +wire [10:0] charaddr; +wire [7:0] chardata; + +pet2001rom rom +( + .q_a(rom_data), + .q_b(chardata), + .address_a(addr[13:0]), + .address_b({3'b101,charaddr}), + .clock(clk) +); + + +////////////////////////////////////////////////////////////// +// Pet RAM and video RAM. Video RAM is dual ported. +////////////////////////////////////////////////////////////// +wire [7:0] ram_data; +wire [7:0] vram_data; +wire [7:0] video_data; +wire [10:0] video_addr; + +wire ram_we = we && (addr[15:14] == 2'b00); +wire vram_we = we && (addr[15:11] == 5'b1000_0); + +pet2001ram ram +( + .clock(clk), + + .q_a(ram_data), + .data_a(data_in), + .address_a(addr[13:0]), + .wren_a(ram_we), + + .q_b(dma_dout), + .data_b(dma_din), + .address_b(dma_addr), + .wren_b(dma_we) +); + +pet2001vram vidram +( + .clock(clk), + + .address_a(addr[10:0]), + .data_a(data_in), + .wren_a(vram_we), + .q_a(vram_data), + + .address_b(video_addr), + .data_b(0), + .wren_b(0), + .q_b(video_data) +); + +////////////////////////////////////// +// Video hardware. +////////////////////////////////////// +wire video_on; // signal indicating VGA is scanning visible + // rows. Used to generate tick interrupts. +wire video_blank; // blank screen during scrolling +wire video_gfx; // display graphic characters vs. lower-case + +pet2001video vid(.*); + +//////////////////////////////////////////////////////// +// I/O hardware +//////////////////////////////////////////////////////// +wire [7:0] io_read_data; +wire io_we = we && (addr[15:11] == 5'b1110_1); + +pet2001io io +( + .*, + .ce(ce_1m), + .data_out(io_read_data), + .data_in(data_in), + .addr(addr[10:0]), + .we(io_we), + .video_sync(video_on) +); + +///////////////////////////////////// +// Read data mux (to CPU) +///////////////////////////////////// +always @(*) +casex(addr[15:11]) + 5'b1111_x: // F000-FFFF + data_out = rom_data; + 5'b1110_1: // E800-EFFF + data_out = io_read_data; + 5'b1110_0: // E000-E7FF + data_out = rom_data; + 5'b110x_x: // C000-DFFF + data_out = rom_data; + 5'b1000_0: // 8000-87FF + data_out = vram_data; + 5'b00xx_x: // 0000-3FFF + data_out = ram_data; + default: + data_out = 8'h55; +endcase + +endmodule // pet2001hw diff --git a/Commodore - Pet2001_MiST/rtl/pet2001io.v b/Commodore - Pet2001_MiST/rtl/pet2001io.v new file mode 100644 index 00000000..59fd8ae6 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pet2001io.v @@ -0,0 +1,208 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////// +// +// Engineer: Thomas Skibo +// +// Create Date: Sep 24, 2011 +// +// Module Name: pet2001io +// +// Description: +// I/O devices for Pet emulator. Includes two PIAs and a VIA and a +// module that converts a PS2 keyboard into a PET keyboard. +// +// I/O is mapped into region 0xE800-0xEFFF. +// +// 0xE810-0xE813 PIA1 +// 0xE820-0xE823 PIA2 +// 0xE840-0xE84F VIA +// +///////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2011, Thomas Skibo. All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * The names of contributors may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL Thomas Skibo OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +// SUCH DAMAGE. +// +////////////////////////////////////////////////////////////////////////////// + +module pet2001io +( + output reg [7:0] data_out, // CPU interface + input [7:0] data_in, + input [10:0] addr, + input we, + + output irq, + + output [3:0] keyrow, // Keyboard + input [7:0] keyin, + + output video_blank, // Video controls + output video_gfx, + input video_sync, + + output cass_motor_n, // Cassette #1 interface + output cass_write, + input cass_sense_n, + input cass_read, + output audio, // CB2 audio + + input diag_l, // diag jumper input + + input ce, + input clk, + input reset +); + +//delay ce for io for stability. +reg strobe_io; +always @(negedge clk) strobe_io <= ce; + +/////////////////////////// 6520 PIA1 //////////////////////////////////// +// +wire pia1_strobe = strobe_io && (addr[10:2] == 9'b000_0001_00); +wire [7:0] pia1_data_out; +wire pia1_irq; +wire [7:0] pia1_porta_out; +wire [7:0] pia1_porta_in = {diag_l, 2'b00, cass_sense_n, 4'b0000}; +wire pia1_ca1_in = !cass_read; +wire pia1_ca2_out; + +pia6520 pia1 +( + .data_out(pia1_data_out), + .data_in(data_in), + .addr(addr[1:0]), + .strobe(pia1_strobe), + .we(we), + + .irq(pia1_irq), + .porta_out(pia1_porta_out), + .porta_in(pia1_porta_in), + .portb_out(), + .portb_in(keyin), + + .ca1_in(pia1_ca1_in), + .ca2_out(pia1_ca2_out), + .ca2_in(1'b0), + + .cb1_in(video_sync), + .cb2_out(cass_motor_n), + .cb2_in(1'b0), + + .clk(clk), + .reset(reset) +); + +assign video_blank = !pia1_ca2_out; +assign keyrow = pia1_porta_out[3:0]; + + +////////////////////////// 6520 PIA2 //////////////////////////////////// +// (does nothing for now) +wire pia2_strobe = strobe_io && (addr[10:2] == 9'b000_0010_00); +wire [7:0] pia2_data_out; +wire pia2_irq; + +pia6520 pia2 +( + .data_out(pia2_data_out), + .data_in(data_in), + .addr(addr[1:0]), + .strobe(pia2_strobe), + .we(we), + + .irq(pia2_irq), + .porta_out(), + .porta_in(8'h00), + .portb_out(), + .portb_in(8'h00), + + .ca1_in(1'b0), + .ca2_out(), + .ca2_in(1'b0), + + .cb1_in(1'b0), + .cb2_out(), + .cb2_in(1'b0), + + .clk(clk), + .reset(reset) +); + + +/////////////////////////// 6522 VIA //////////////////////////////////// +// +wire via_strobe = strobe_io && (addr[10:4] == 7'b000_0100); +wire [7:0] via_data_out; +wire via_irq; +wire [7:0] via_portb_out; +wire [7:0] via_portb_in = {2'b00, video_sync, 5'b0_0000}; + +via6522 via +( + .data_out(via_data_out), + .data_in(data_in), + .addr(addr[3:0]), + .strobe(via_strobe), + .we(we), + + .irq(via_irq), + .porta_out(), + .porta_in(8'h00), + .portb_out(via_portb_out), + .portb_in(via_portb_in), + + .ca1_in(1'b0), + .ca2_out(video_gfx), + .ca2_in(1'b0), + + .cb1_out(), + .cb1_in(1'b0), + .cb2_out(audio), + .cb2_in(1'b0), + + .ce(ce), + + .clk(clk), + .reset(reset) +); + +assign cass_write = via_portb_out[3]; + + +/////////////// Read data mux ///////////////////////// +// register I/O stuff, therefore RDY must be delayed a cycle! +// +always @(posedge clk) +casex (addr[10:2]) + 9'b000_0001_00: data_out <= pia1_data_out; + 9'b000_0010_00: data_out <= pia2_data_out; + 9'b000_0100_xx: data_out <= via_data_out; + default: data_out <= 8'hXX; +endcase + +assign irq = pia1_irq || pia2_irq || via_irq; + +endmodule // pet2001io diff --git a/Commodore - Pet2001_MiST/rtl/pet2001ram.v b/Commodore - Pet2001_MiST/rtl/pet2001ram.v new file mode 100644 index 00000000..1eeed5c0 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pet2001ram.v @@ -0,0 +1,242 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pet2001ram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pet2001ram ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [13:0] address_a; + input [13:0] address_b; + input clock; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .clock0 (clock), + .wren_a (wren_a), + .address_b (address_b), + .data_b (data_b), + .wren_b (wren_b), + .address_a (address_a), + .data_a (data_a), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 16384, + altsyncram_component.numwords_b = 16384, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 14, + altsyncram_component.widthad_b = 14, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001ram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001ram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001ram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001ram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001ram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001ram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - Pet2001_MiST/rtl/pet2001rom.v b/Commodore - Pet2001_MiST/rtl/pet2001rom.v new file mode 100644 index 00000000..0d4d90ea --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pet2001rom.v @@ -0,0 +1,228 @@ +// megafunction wizard: %ROM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pet2001rom.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pet2001rom ( + address_a, + address_b, + clock, + q_a, + q_b); + + input [13:0] address_a; + input [13:0] address_b; + input clock; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire sub_wire2 = 1'h0; + wire [7:0] sub_wire3 = 8'h0; + wire [7:0] q_b = sub_wire0[7:0]; + wire [7:0] q_a = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .clock0 (clock), + .wren_a (sub_wire2), + .address_b (address_b), + .data_b (sub_wire3), + .wren_b (sub_wire2), + .address_a (address_a), + .data_a (sub_wire3), + .q_b (sub_wire0), + .q_a (sub_wire1) + // synopsys translate_off + , + .aclr0 (), + .aclr1 (), + .addressstall_a (), + .addressstall_b (), + .byteena_a (), + .byteena_b (), + .clock1 (), + .clocken0 (), + .clocken1 (), + .clocken2 (), + .clocken3 (), + .eccstatus (), + .rden_a (), + .rden_b () + // synopsys translate_on + ); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.init_file = "./roms/Pet2001_RomType2.mif", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 16384, + altsyncram_component.numwords_b = 16384, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.widthad_a = 14, + altsyncram_component.widthad_b = 14, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./roms/Pet2001_RomType2.mif" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INIT_FILE STRING "./roms/Pet2001_RomType2.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 GND 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 GND 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001rom.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001rom.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001rom.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001rom.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001rom_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001rom_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - Pet2001_MiST/rtl/pet2001video.v b/Commodore - Pet2001_MiST/rtl/pet2001video.v new file mode 100644 index 00000000..cfe0af32 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pet2001video.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps + +module pet2001video +( + output pix, + output reg HSync, + output reg VSync, + + output [10:0] video_addr, // Video RAM intf + input [7:0] video_data, + + output [10:0] charaddr, // char rom intf + input [7:0] chardata, + output video_on, // control sigs + input video_blank, + input video_gfx, + input clk, + input ce_7mp, + input ce_7mn +); + +assign video_on = (vc < 200); +assign video_addr = {vc[8:3], 5'b00000}+{vc[8:3], 3'b000}+hc[8:3]; +assign charaddr = {video_gfx, video_data[6:0], vc[2:0]}; + +reg [8:0] hc; +reg [8:0] vc; + +always @(posedge clk) begin + if(ce_7mp) begin + hc <= hc + 1'd1; + if(hc == 447) begin + hc <=0; + vc <= vc + 1'd1; + if(vc == 261) vc <= 0; + end + end + + if(ce_7mn) begin + if(hc == 358) HSync <= 1; + if(hc == 391) HSync <= 0; + if(vc == 225) VSync <= 1; + if(vc == 234) VSync <= 0; + end +end + +reg [7:0] vdata; +reg inv; +assign pix = (vdata[7] ^ inv) & ~video_blank; + +always @(posedge clk) begin + if(ce_7mn) begin + if(!hc[2:0]) {inv, vdata} <= ((hc<320) && (vc<200)) ? {video_data[7], chardata} : 9'd0; + else vdata <= {vdata[6:0], 1'b0}; + end +end + + +endmodule // pet2001video + diff --git a/Commodore - Pet2001_MiST/rtl/pet2001vram.v b/Commodore - Pet2001_MiST/rtl/pet2001vram.v new file mode 100644 index 00000000..02c78a2b --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pet2001vram.v @@ -0,0 +1,242 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pet2001vram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pet2001vram ( + address_a, + address_b, + clock, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [10:0] address_a; + input [10:0] address_b; + input clock; + input [7:0] data_a; + input [7:0] data_b; + input wren_a; + input wren_b; + output [7:0] q_a; + output [7:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] sub_wire1; + wire [7:0] q_a = sub_wire0[7:0]; + wire [7:0] q_b = sub_wire1[7:0]; + + altsyncram altsyncram_component ( + .clock0 (clock), + .wren_a (wren_a), + .address_b (address_b), + .data_b (data_b), + .wren_b (wren_b), + .address_a (address_a), + .data_a (data_a), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK0", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2048, + altsyncram_component.numwords_b = 2048, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 11, + altsyncram_component.widthad_b = 11, + altsyncram_component.width_a = 8, + altsyncram_component.width_b = 8, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "0" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" +// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]" +// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" +// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]" +// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]" +// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0 +// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001vram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001vram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001vram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001vram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001vram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pet2001vram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore - Pet2001_MiST/rtl/pia6520.v b/Commodore - Pet2001_MiST/rtl/pia6520.v new file mode 100644 index 00000000..ae4770e6 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pia6520.v @@ -0,0 +1,230 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////// +// +// Engineer: Thomas Skibo +// +// Create Date: Sep 24, 2011 +// +// Module Name: pia6520 +// +// Description: +// +// A simple implementation of the 6520 Peripheral Interface Adapter (PIA). +// Tri-state lines aren't used. Instead, All PIA I/O signals have +// seperate "in" and "out" signals. Wire or ignore appropriately. +// +///////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2011, Thomas Skibo. All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * The names of contributors may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL Thomas Skibo OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +// SUCH DAMAGE. +// +////////////////////////////////////////////////////////////////////////////// + +module pia6520 +( + output reg [7:0] data_out, // cpu interface + input [7:0] data_in, + input [1:0] addr, + input strobe, + input we, + + output irq, + + output reg [7:0] porta_out, + input [7:0] porta_in, + output reg [7:0] portb_out, + input [7:0] portb_in, + + input ca1_in, + output reg ca2_out, + input ca2_in, + input cb1_in, + output reg cb2_out, + input cb2_in, + + input clk, + input reset +); + +reg [7:0] ddra; +reg [5:0] cra; +reg irqa1; +reg irqa2; + +reg [7:0] ddrb; +reg [5:0] crb; +reg irqb1; +reg irqb2; + +// Register address offsets +parameter [1:0] + ADDR_PORTA = 2'b00, + ADDR_CRA = 2'b01, + ADDR_PORTB = 2'b10, + ADDR_CRB = 2'b11; + +wire wr_strobe = strobe && we; +wire rd_strobe = strobe && !we; +wire porta_rd_strobe = rd_strobe && addr == ADDR_PORTA; +wire portb_rd_strobe = rd_strobe && addr == ADDR_PORTB; +wire portb_wr_strobe = wr_strobe && addr == ADDR_PORTB; + +// Implement CRA[5:0] +always @(posedge clk) begin + if (reset) cra <= 6'b00_0000; + else if (wr_strobe && addr == ADDR_CRA) cra <= data_in[5:0]; +end + +// Implement CRB[5:0] +always @(posedge clk) begin + if (reset) crb <= 6'b00_0000; + else if (wr_strobe && addr == ADDR_CRB) crb <= data_in[5:0]; +end + +// Implement PORTA (out) +always @(posedge clk) begin + if (reset) porta_out <= 8'h00; + else if (wr_strobe && addr == ADDR_PORTA && cra[2]) porta_out <= data_in; +end + +// Implement DDRA +always @(posedge clk) begin + if (reset) ddra <= 8'h00; + else if (wr_strobe && addr == ADDR_PORTA && !cra[2]) ddra <= data_in; +end + +// Implement PORTB (out) +always @(posedge clk) begin + if (reset) portb_out <= 8'h00; + else if (wr_strobe && addr == ADDR_PORTB && crb[2]) portb_out <= data_in; +end + +// Implement DDRB +always @(posedge clk) begin + if (reset) ddrb <= 8'h00; + else if (wr_strobe && addr == ADDR_PORTB && !crb[2]) ddrb <= data_in; +end + +//////////////////////////////////////////////////////// +// IRQA logic + +// register ca1_in and ca2_in to detect transitions. +reg ca1_in_1; +reg ca2_in_1; +always @(posedge clk) begin + ca1_in_1 <= ca1_in; + ca2_in_1 <= ca2_in; +end + +// detect "active" transitions +wire ca1_act_trans = ((ca1_in && !ca1_in_1 && cra[1]) || (!ca1_in && ca1_in_1 && !cra[1])); +wire ca2_act_trans = ((ca2_in && !ca2_in_1 && cra[4]) || (!ca2_in && ca2_in_1 && !cra[4])); + +// IRQA1 +always @(posedge clk) begin + if (reset || (porta_rd_strobe && !ca1_act_trans)) irqa1 <= 1'b0; + else if (ca1_act_trans) irqa1 <= 1'b1; +end + +// IRQA2 +always @(posedge clk) begin + if (reset || (porta_rd_strobe && !ca2_act_trans)) irqa2 <= 1'b0; + else if (ca2_act_trans && !cra[5]) irqa2 <= 1'b1; +end + + +//////////////////////////////////////////////////////// +// IRQB logic + +// register cb1_in and cb2_in to detect transitions. +reg cb1_in_1; +reg cb2_in_1; +always @(posedge clk) begin + cb1_in_1 <= cb1_in; + cb2_in_1 <= cb2_in; +end + +// detect "active" transitions +wire cb1_act_trans = ((cb1_in && !cb1_in_1 && crb[1]) || (!cb1_in && cb1_in_1 && !crb[1])); +wire cb2_act_trans = ((cb2_in && !cb2_in_1 && crb[4]) || (!cb2_in && cb2_in_1 && !crb[4])); + +// IRQB1 +always @(posedge clk) begin + if (reset || (portb_rd_strobe && !cb1_act_trans)) irqb1 <= 1'b0; + else if (cb1_act_trans) irqb1 <= 1'b1; +end + +// IRQB2 +always @(posedge clk) begin + if (reset || (portb_rd_strobe && !cb2_act_trans)) irqb2 <= 1'b0; + else if (cb2_act_trans && !crb[5]) irqb2 <= 1'b1; +end + + +// IRQ and enable logic. +assign irq = (irqa1 && cra[0]) || (irqa2 && cra[3]) || + (irqb1 && crb[0]) || (irqb2 && crb[3]); + +/////////////////////////////////////////////////// +// CA2 and CB2 output modes +always @(posedge clk) begin + case (cra[5:3]) + 3'b100: ca2_out <= irqa1; + 3'b101: ca2_out <= !ca1_act_trans; + 3'b111: ca2_out <= 1'b1; + default: ca2_out <= 1'b0; + endcase +end + +reg cb2_out_r; +always @(posedge clk) begin + if (reset || (portb_wr_strobe && !cb1_act_trans)) cb2_out_r <= 1'b0; + else if (cb1_act_trans) cb2_out_r <= 1'b1; +end + +always @(posedge clk) begin + case (crb[5:3]) + 3'b100: cb2_out <= cb2_out_r; + 3'b101: cb2_out <= !portb_wr_strobe; + 3'b111: cb2_out <= 1'b1; + default: cb2_out <= 1'b0; + endcase +end + +/////////////////////////////////////////////////// +// Read data mux +wire [7:0] porta = (porta_out & ddra) | (porta_in & ~ddra); +wire [7:0] portb = (portb_out & ddrb) | (portb_in & ~ddrb); + +always @(*) begin + case (addr) + ADDR_PORTA: data_out = cra[2] ? porta : ddra; + ADDR_CRA: data_out = { irqa1, irqa2, cra }; + ADDR_PORTB: data_out = crb[2] ? portb : ddrb; + ADDR_CRB: data_out = { irqb1, irqb2, crb }; + endcase +end + +endmodule // pia6520 diff --git a/Commodore - Pet2001_MiST/rtl/pll.v b/Commodore - Pet2001_MiST/rtl/pll.v new file mode 100644 index 00000000..18c60289 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/pll.v @@ -0,0 +1,363 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + c2, + locked); + + input inclk0; + output c0; + output c1; + output c2; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 112, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 27, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 112, + altpll_component.clk1_phase_shift = "-1488", + altpll_component.clk2_divide_by = 27, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 56, + altpll_component.clk2_phase_shift = "0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NO_COMPENSATION", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "ON", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "112.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "112.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "56.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "112.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "112.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "56.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "112" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1488" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "56" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Commodore - Pet2001_MiST/rtl/roms/Pet2001_RomType1.mif b/Commodore - Pet2001_MiST/rtl/roms/Pet2001_RomType1.mif new file mode 100644 index 00000000..180c40e4 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/roms/Pet2001_RomType1.mif @@ -0,0 +1,15354 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=16384; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0000 : 1D; + 0001 : C7; + 0002 : 48; + 0003 : C6; + 0004 : 35; + 0005 : CC; + 0006 : EF; + 0007 : C7; + 0008 : C5; + 0009 : CA; + 000A : DF; + 000B : CA; + 000C : 70; + 000D : CF; + 000E : 23; + 000F : CB; + 0010 : 9C; + 0011 : C8; + 0012 : 9C; + 0013 : C7; + 0014 : 74; + 0015 : C7; + 0016 : 1F; + 0017 : C8; + 0018 : 0C; + 0019 : C7; + 001A : 7F; + 001B : C7; + 001C : C9; + 001D : C7; + 001E : 32; + 001F : C8; + 0020 : 1B; + 0021 : C7; + 0022 : 42; + 0023 : C8; + 0024 : 01; + 0025 : D7; + 0026 : D4; + 0027 : FF; + 0028 : D7; + 0029 : FF; + 002A : DA; + 002B : FF; + 002C : 94; + 002D : D2; + 002E : F8; + 002F : D6; + 0030 : 7E; + 0031 : C9; + 0032 : 9E; + 0033 : C9; + 0034 : 44; + 0035 : C7; + 0036 : A7; + 0037 : C5; + 0038 : 6F; + 0039 : C7; + 003A : 84; + 003B : C9; + 003C : DD; + 003D : FF; + 003E : BF; + 003F : FF; + 0040 : C2; + 0041 : FF; + 0042 : 9E; + 0043 : CA; + 0044 : 50; + 0045 : C5; + 0046 : 0B; + 0047 : DB; + 0048 : 9E; + 0049 : DB; + 004A : 2A; + 004B : DB; + [004C..004D] : 00; + 004E : 64; + 004F : D2; + 0050 : 85; + 0051 : D2; + 0052 : 24; + 0053 : DE; + 0054 : 45; + 0055 : DF; + 0056 : BF; + 0057 : D8; + 0058 : A0; + 0059 : DE; + 005A : 9E; + 005B : DF; + 005C : A5; + 005D : DF; + 005E : EE; + 005F : DF; + 0060 : 48; + 0061 : E0; + 0062 : E6; + 0063 : D6; + 0064 : 54; + 0065 : D6; + 0066 : 49; + 0067 : D3; + 0068 : 85; + 0069 : D6; + 006A : 63; + 006B : D6; + 006C : C4; + 006D : D5; + 006E : D8; + 006F : D5; + 0070 : 04; + 0071 : D6; + 0072 : 0F; + 0073 : D6; + 0074 : 79; + 0075 : 3E; + 0076 : D7; + 0077 : 79; + 0078 : 27; + 0079 : D7; + 007A : 7B; + 007B : FF; + 007C : D8; + 007D : 7B; + 007E : E3; + 007F : D9; + 0080 : 7F; + 0081 : 2D; + 0082 : DE; + 0083 : 50; + 0084 : D8; + 0085 : CE; + 0086 : 46; + 0087 : D5; + 0088 : CE; + 0089 : 7D; + 008A : 66; + 008B : DE; + 008C : 5A; + 008D : E7; + 008E : CD; + 008F : 64; + 0090 : 05; + 0091 : CF; + 0092 : 45; + 0093 : 4E; + 0094 : C4; + 0095 : 46; + 0096 : 4F; + 0097 : D2; + 0098 : 4E; + 0099 : 45; + 009A : 58; + 009B : D4; + 009C : 44; + 009D : 41; + 009E : 54; + 009F : C1; + 00A0 : 49; + 00A1 : 4E; + 00A2 : 50; + 00A3 : 55; + 00A4 : 54; + 00A5 : A3; + 00A6 : 49; + 00A7 : 4E; + 00A8 : 50; + 00A9 : 55; + 00AA : D4; + 00AB : 44; + 00AC : 49; + 00AD : CD; + 00AE : 52; + 00AF : 45; + 00B0 : 41; + 00B1 : C4; + 00B2 : 4C; + 00B3 : 45; + 00B4 : D4; + 00B5 : 47; + 00B6 : 4F; + 00B7 : 54; + 00B8 : CF; + 00B9 : 52; + 00BA : 55; + 00BB : CE; + 00BC : 49; + 00BD : C6; + 00BE : 52; + 00BF : 45; + 00C0 : 53; + 00C1 : 54; + 00C2 : 4F; + 00C3 : 52; + 00C4 : C5; + 00C5 : 47; + 00C6 : 4F; + 00C7 : 53; + 00C8 : 55; + 00C9 : C2; + 00CA : 52; + 00CB : 45; + 00CC : 54; + 00CD : 55; + 00CE : 52; + 00CF : CE; + 00D0 : 52; + 00D1 : 45; + 00D2 : CD; + 00D3 : 53; + 00D4 : 54; + 00D5 : 4F; + 00D6 : D0; + 00D7 : 4F; + 00D8 : CE; + 00D9 : 57; + 00DA : 41; + 00DB : 49; + 00DC : D4; + 00DD : 4C; + 00DE : 4F; + 00DF : 41; + 00E0 : C4; + 00E1 : 53; + 00E2 : 41; + 00E3 : 56; + 00E4 : C5; + 00E5 : 56; + 00E6 : 45; + 00E7 : 52; + 00E8 : 49; + 00E9 : 46; + 00EA : D9; + 00EB : 44; + 00EC : 45; + 00ED : C6; + 00EE : 50; + 00EF : 4F; + 00F0 : 4B; + 00F1 : C5; + 00F2 : 50; + 00F3 : 52; + 00F4 : 49; + 00F5 : 4E; + 00F6 : 54; + 00F7 : A3; + 00F8 : 50; + 00F9 : 52; + 00FA : 49; + 00FB : 4E; + 00FC : D4; + 00FD : 43; + 00FE : 4F; + 00FF : 4E; + 0100 : D4; + 0101 : 4C; + 0102 : 49; + 0103 : 53; + 0104 : D4; + 0105 : 43; + 0106 : 4C; + 0107 : D2; + 0108 : 43; + 0109 : 4D; + 010A : C4; + 010B : 53; + 010C : 59; + 010D : D3; + 010E : 4F; + 010F : 50; + 0110 : 45; + 0111 : CE; + 0112 : 43; + 0113 : 4C; + 0114 : 4F; + 0115 : 53; + 0116 : C5; + 0117 : 47; + 0118 : 45; + 0119 : D4; + 011A : 4E; + 011B : 45; + 011C : D7; + 011D : 54; + 011E : 41; + 011F : 42; + 0120 : A8; + 0121 : 54; + 0122 : CF; + 0123 : 46; + 0124 : CE; + 0125 : 53; + 0126 : 50; + 0127 : 43; + 0128 : A8; + 0129 : 54; + 012A : 48; + 012B : 45; + 012C : CE; + 012D : 4E; + 012E : 4F; + 012F : D4; + 0130 : 53; + 0131 : 54; + 0132 : 45; + 0133 : D0; + 0134 : AB; + 0135 : AD; + 0136 : AA; + 0137 : AF; + 0138 : DE; + 0139 : 41; + 013A : 4E; + 013B : C4; + 013C : 4F; + 013D : D2; + 013E : BE; + 013F : BD; + 0140 : BC; + 0141 : 53; + 0142 : 47; + 0143 : CE; + 0144 : 49; + 0145 : 4E; + 0146 : D4; + 0147 : 41; + 0148 : 42; + 0149 : D3; + 014A : 55; + 014B : 53; + 014C : D2; + 014D : 46; + 014E : 52; + 014F : C5; + 0150 : 50; + 0151 : 4F; + 0152 : D3; + 0153 : 53; + 0154 : 51; + 0155 : D2; + 0156 : 52; + 0157 : 4E; + 0158 : C4; + 0159 : 4C; + 015A : 4F; + 015B : C7; + 015C : 45; + 015D : 58; + 015E : D0; + 015F : 43; + 0160 : 4F; + 0161 : D3; + 0162 : 53; + 0163 : 49; + 0164 : CE; + 0165 : 54; + 0166 : 41; + 0167 : CE; + 0168 : 41; + 0169 : 54; + 016A : CE; + 016B : 50; + [016C..016D] : 45; + 016E : CB; + 016F : 4C; + 0170 : 45; + 0171 : CE; + 0172 : 53; + 0173 : 54; + 0174 : 52; + 0175 : A4; + 0176 : 56; + 0177 : 41; + 0178 : CC; + 0179 : 41; + 017A : 53; + 017B : C3; + 017C : 43; + 017D : 48; + 017E : 52; + 017F : A4; + 0180 : 4C; + 0181 : 45; + 0182 : 46; + 0183 : 54; + 0184 : A4; + 0185 : 52; + 0186 : 49; + 0187 : 47; + 0188 : 48; + 0189 : 54; + 018A : A4; + 018B : 4D; + 018C : 49; + 018D : 44; + 018E : A4; + 018F : 00; + 0190 : 4E; + 0191 : 45; + 0192 : 58; + 0193 : 54; + 0194 : 20; + 0195 : 57; + 0196 : 49; + 0197 : 54; + 0198 : 48; + 0199 : 4F; + 019A : 55; + 019B : 54; + 019C : 20; + 019D : 46; + 019E : 4F; + 019F : D2; + 01A0 : 53; + 01A1 : 59; + 01A2 : 4E; + 01A3 : 54; + 01A4 : 41; + 01A5 : D8; + 01A6 : 52; + 01A7 : 45; + 01A8 : 54; + 01A9 : 55; + 01AA : 52; + 01AB : 4E; + 01AC : 20; + 01AD : 57; + 01AE : 49; + 01AF : 54; + 01B0 : 48; + 01B1 : 4F; + 01B2 : 55; + 01B3 : 54; + 01B4 : 20; + 01B5 : 47; + 01B6 : 4F; + 01B7 : 53; + 01B8 : 55; + 01B9 : C2; + 01BA : 4F; + 01BB : 55; + 01BC : 54; + 01BD : 20; + 01BE : 4F; + 01BF : 46; + 01C0 : 20; + 01C1 : 44; + 01C2 : 41; + 01C3 : 54; + 01C4 : C1; + 01C5 : 49; + [01C6..01C7] : 4C; + 01C8 : 45; + 01C9 : 47; + 01CA : 41; + 01CB : 4C; + 01CC : 20; + 01CD : 51; + 01CE : 55; + 01CF : 41; + 01D0 : 4E; + 01D1 : 54; + 01D2 : 49; + 01D3 : 54; + 01D4 : D9; + [01D5..01D9] : 00; + 01DA : 4F; + 01DB : 56; + 01DC : 45; + 01DD : 52; + 01DE : 46; + 01DF : 4C; + 01E0 : 4F; + 01E1 : D7; + 01E2 : 4F; + 01E3 : 55; + 01E4 : 54; + 01E5 : 20; + 01E6 : 4F; + 01E7 : 46; + 01E8 : 20; + 01E9 : 4D; + 01EA : 45; + 01EB : 4D; + 01EC : 4F; + 01ED : 52; + 01EE : D9; + 01EF : 55; + 01F0 : 4E; + 01F1 : 44; + 01F2 : 45; + 01F3 : 46; + 01F4 : 27; + 01F5 : 44; + 01F6 : 20; + 01F7 : 53; + 01F8 : 54; + 01F9 : 41; + 01FA : 54; + 01FB : 45; + 01FC : 4D; + 01FD : 45; + 01FE : 4E; + 01FF : D4; + 0200 : 42; + 0201 : 41; + 0202 : 44; + 0203 : 20; + 0204 : 53; + 0205 : 55; + 0206 : 42; + 0207 : 53; + 0208 : 43; + 0209 : 52; + 020A : 49; + 020B : 50; + 020C : D4; + 020D : 52; + 020E : 45; + 020F : 44; + 0210 : 49; + 0211 : 4D; + 0212 : 27; + 0213 : 44; + 0214 : 20; + 0215 : 41; + [0216..0217] : 52; + 0218 : 41; + 0219 : D9; + 021A : 44; + 021B : 49; + 021C : 56; + 021D : 49; + 021E : 53; + 021F : 49; + 0220 : 4F; + 0221 : 4E; + 0222 : 20; + 0223 : 42; + 0224 : 59; + 0225 : 20; + 0226 : 5A; + 0227 : 45; + 0228 : 52; + 0229 : CF; + 022A : 49; + [022B..022C] : 4C; + 022D : 45; + 022E : 47; + 022F : 41; + 0230 : 4C; + 0231 : 20; + 0232 : 44; + 0233 : 49; + 0234 : 52; + 0235 : 45; + 0236 : 43; + 0237 : D4; + 0238 : 54; + 0239 : 59; + 023A : 50; + 023B : 45; + 023C : 20; + 023D : 4D; + 023E : 49; + 023F : 53; + 0240 : 4D; + 0241 : 41; + 0242 : 54; + 0243 : 43; + 0244 : C8; + 0245 : 53; + 0246 : 54; + 0247 : 52; + 0248 : 49; + 0249 : 4E; + 024A : 47; + 024B : 20; + 024C : 54; + [024D..024E] : 4F; + 024F : 20; + 0250 : 4C; + 0251 : 4F; + 0252 : 4E; + 0253 : C7; + 0254 : 42; + 0255 : 41; + 0256 : 44; + 0257 : 20; + 0258 : 44; + 0259 : 41; + 025A : 54; + 025B : C1; + 025C : 46; + 025D : 4F; + 025E : 52; + 025F : 4D; + 0260 : 55; + 0261 : 4C; + 0262 : 41; + 0263 : 20; + 0264 : 54; + [0265..0266] : 4F; + 0267 : 20; + 0268 : 43; + 0269 : 4F; + 026A : 4D; + 026B : 50; + 026C : 4C; + 026D : 45; + 026E : D8; + 026F : 43; + 0270 : 41; + 0271 : 4E; + 0272 : 27; + 0273 : 54; + 0274 : 20; + 0275 : 43; + 0276 : 4F; + 0277 : 4E; + 0278 : 54; + 0279 : 49; + 027A : 4E; + 027B : 55; + 027C : C5; + 027D : 55; + 027E : 4E; + 027F : 44; + 0280 : 45; + 0281 : 46; + 0282 : 27; + 0283 : 44; + 0284 : 20; + 0285 : 46; + 0286 : 55; + 0287 : 4E; + 0288 : 43; + 0289 : 54; + 028A : 49; + 028B : 4F; + 028C : CE; + 028D : 20; + 028E : 45; + [028F..0290] : 52; + 0291 : 4F; + 0292 : 52; + 0293 : 00; + 0294 : 20; + 0295 : 49; + 0296 : 4E; + 0297 : 20; + 0298 : 00; + 0299 : 0D; + 029A : 0A; + 029B : 52; + 029C : 45; + 029D : 41; + 029E : 44; + 029F : 59; + 02A0 : 2E; + 02A1 : 0D; + 02A2 : 0A; + 02A3 : 00; + 02A4 : 0D; + 02A5 : 0A; + 02A6 : 42; + 02A7 : 52; + 02A8 : 45; + 02A9 : 41; + 02AA : 4B; + 02AB : 00; + 02AC : BA; + [02AD..02B0] : E8; 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+ 3E6E : 8E; + 3E6F : 40; + 3E70 : E8; + 3E71 : EE; + 3E72 : 11; + 3E73 : E8; + 3E74 : 2C; + 3E75 : 10; + 3E76 : E8; + 3E77 : 58; + 3E78 : 0E; + 3E79 : 40; + 3E7A : E8; + 3E7B : 4E; + 3E7C : 40; + 3E7D : E8; + 3E7E : D0; + 3E7F : FE; + 3E80 : CE; + 3E81 : 11; + 3E82 : E8; + 3E83 : 10; + 3E84 : FE; + 3E85 : 2C; + 3E86 : 10; + 3E87 : E8; + 3E88 : A2; + 3E89 : 06; + 3E8A : 20; + 3E8B : 1B; + 3E8C : FD; + 3E8D : 2C; + 3E8E : 40; + 3E8F : E8; + 3E90 : A9; + 3E91 : 90; + 3E92 : 8D; + 3E93 : 4E; + 3E94 : E8; + 3E95 : 58; + 3E96 : 0E; + 3E97 : 40; + 3E98 : E8; + 3E99 : 4E; + 3E9A : 40; + 3E9B : E8; + 3E9C : D0; + 3E9D : FE; + 3E9E : 2C; + 3E9F : 4D; + 3EA0 : E8; + 3EA1 : 10; + 3EA2 : FE; + 3EA3 : A9; + 3EA4 : 7F; + 3EA5 : 8D; + 3EA6 : 4E; + 3EA7 : E8; + 3EA8 : 2C; + 3EA9 : 40; + 3EAA : E8; + 3EAB : 4C; + 3EAC : C3; + 3EAD : FE; + 3EAE : 2C; + 3EAF : 41; + 3EB0 : E8; + 3EB1 : 70; + 3EB2 : FB; + 3EB3 : 2C; + 3EB4 : 4F; + 3EB5 : E8; + 3EB6 : 50; + 3EB7 : FB; + 3EB8 : 2C; + 3EB9 : 4F; + 3EBA : E8; + 3EBB : 70; + 3EBC : FB; + 3EBD : AD; + 3EBE : 4D; + 3EBF : E8; + 3EC0 : 29; + 3EC1 : 02; + 3EC2 : 60; + 3EC3 : A2; + 3EC4 : 0A; + 3EC5 : 2C; + 3EC6 : 41; + 3EC7 : E8; + 3EC8 : 10; + 3EC9 : FB; + 3ECA : 2C; + 3ECB : 41; + 3ECC : E8; + 3ECD : 30; + 3ECE : FB; + 3ECF : CA; + 3ED0 : D0; + 3ED1 : FD; + 3ED2 : 2C; + 3ED3 : 41; + 3ED4 : E8; + 3ED5 : 30; + 3ED6 : 02; + 3ED7 : 10; + 3ED8 : FE; + 3ED9 : EE; + [3EDA..3EDB] : FF; + 3EDC : 2C; + 3EDD : 41; + 3EDE : E8; + 3EDF : 30; + 3EE0 : FE; + 3EE1 : 2C; + 3EE2 : 41; + 3EE3 : E8; + 3EE4 : 50; + 3EE5 : FB; + 3EE6 : 2C; + 3EE7 : 41; + 3EE8 : E8; + 3EE9 : 70; + 3EEA : FB; + 3EEB : 2C; + 3EEC : 41; + 3EED : E8; + 3EEE : 50; + 3EEF : FB; + 3EF0 : 2C; + 3EF1 : 41; + 3EF2 : E8; + 3EF3 : 70; + 3EF4 : FB; + 3EF5 : 20; + 3EF6 : F0; + 3EF7 : E1; + 3EF8 : 20; + 3EF9 : AE; + 3EFA : FE; + 3EFB : D0; + 3EFC : FE; + 3EFD : A0; + 3EFE : 00; + 3EFF : A9; + 3F00 : A0; + 3F01 : 91; + 3F02 : E0; + 3F03 : 20; + 3F04 : AE; + 3F05 : FE; + 3F06 : F0; + 3F07 : FE; + 3F08 : A9; + 3F09 : 20; + 3F0A : 91; + 3F0B : E0; + 3F0C : 20; + 3F0D : AE; + 3F0E : FE; + 3F0F : D0; + 3F10 : FE; + 3F11 : C0; + 3F12 : E7; + 3F13 : D0; + 3F14 : 06; + 3F15 : A9; + 3F16 : 83; + 3F17 : C5; + 3F18 : E1; + 3F19 : F0; + 3F1A : 09; + 3F1B : C8; + 3F1C : D0; + 3F1D : E1; + 3F1E : E6; + 3F1F : E1; + 3F20 : D0; + 3F21 : DD; + 3F22 : F0; + 3F23 : FE; + 3F24 : 98; + 3F25 : 91; + 3F26 : E0; + 3F27 : 88; + 3F28 : C0; + 3F29 : FF; + 3F2A : D0; + 3F2B : F8; + 3F2C : C6; + 3F2D : E1; + 3F2E : A9; + 3F2F : 7F; + 3F30 : C5; + 3F31 : E1; + 3F32 : D0; + 3F33 : F0; + 3F34 : A9; + 3F35 : 34; + 3F36 : 8D; + 3F37 : 11; + 3F38 : E8; + 3F39 : 20; + 3F3A : AE; + 3F3B : FE; + 3F3C : D0; + 3F3D : FE; + 3F3E : A9; + 3F3F : 3C; + 3F40 : 8D; + 3F41 : 11; + 3F42 : E8; + 3F43 : A6; + 3F44 : 00; + 3F45 : 8E; + 3F46 : 22; + 3F47 : E8; + 3F48 : EC; + 3F49 : 20; + 3F4A : E8; + 3F4B : D0; + 3F4C : FE; + 3F4D : E8; + 3F4E : D0; + 3F4F : F5; + 3F50 : 2C; + 3F51 : 20; + 3F52 : E8; + 3F53 : A9; + 3F54 : FB; + 3F55 : 8D; + 3F56 : 40; + 3F57 : E8; + 3F58 : 2C; + 3F59 : 21; + 3F5A : E8; + 3F5B : 10; + 3F5C : FE; + 3F5D : 2C; + 3F5E : 40; + 3F5F : E8; + 3F60 : 50; + 3F61 : FE; + 3F62 : 4A; + 3F63 : 8D; + 3F64 : 40; + 3F65 : E8; + 3F66 : 2C; + 3F67 : 40; + 3F68 : E8; + 3F69 : 70; + 3F6A : FE; + 3F6B : 10; + 3F6C : FE; + 3F6D : A9; + 3F6E : 34; + 3F6F : 8D; + 3F70 : 23; + 3F71 : E8; + 3F72 : AD; + 3F73 : 40; + 3F74 : E8; + 3F75 : 30; + 3F76 : FE; + 3F77 : 4A; + 3F78 : 90; + 3F79 : FE; + 3F7A : A9; + 3F7B : 34; + 3F7C : 8D; + 3F7D : 21; + 3F7E : E8; + 3F7F : 4E; + 3F80 : 40; + 3F81 : E8; + 3F82 : B0; + 3F83 : FE; + 3F84 : A9; + 3F85 : 02; + 3F86 : 8D; + 3F87 : 43; + 3F88 : E8; + 3F89 : 8D; + 3F8A : 41; + 3F8B : E8; + 3F8C : 2C; + 3F8D : 10; + 3F8E : E8; + 3F8F : 50; + 3F90 : FE; + 3F91 : 8E; + 3F92 : 41; + 3F93 : E8; + 3F94 : 2C; + 3F95 : 10; + 3F96 : E8; + 3F97 : 50; + 3F98 : 05; + [3F99..3F9A] : EA; + 3F9B : 4C; + 3F9C : 9B; + 3F9D : FF; + 3F9E : 8E; + 3F9F : 11; + 3FA0 : E8; + 3FA1 : A0; + 3FA2 : 0F; + 3FA3 : 8C; + 3FA4 : 10; + 3FA5 : E8; + 3FA6 : 0A; + 3FA7 : 8D; + 3FA8 : 11; + 3FA9 : E8; + 3FAA : 49; + 3FAB : FF; + 3FAC : 8D; + 3FAD : 10; + 3FAE : E8; + 3FAF : 4C; + 3FB0 : AF; + 3FB1 : FF; + 3FB2 : 61; + [3FB3..3FBF] : 00; + 3FC0 : 4C; + 3FC1 : 2A; + 3FC2 : F5; + 3FC3 : 4C; + 3FC4 : C8; + 3FC5 : F2; + 3FC6 : 4C; + 3FC7 : 8B; + 3FC8 : F7; + 3FC9 : 4C; + 3FCA : DC; + 3FCB : F7; + 3FCC : 4C; + 3FCD : 7D; + 3FCE : F2; + 3FCF : 4C; + 3FD0 : DF; + 3FD1 : F1; + 3FD2 : 4C; + 3FD3 : 30; + 3FD4 : F2; + 3FD5 : 4C; + 3FD6 : 46; + 3FD7 : F3; + 3FD8 : 4C; + 3FD9 : 9E; + 3FDA : F6; + 3FDB : 4C; + 3FDC : BB; + 3FDD : F4; + 3FDE : 4C; + 3FDF : 95; + 3FE0 : F6; + 3FE1 : 4C; + 3FE2 : 39; + 3FE3 : F3; + 3FE4 : 4C; + 3FE5 : CC; + 3FE6 : F1; + 3FE7 : 4C; + 3FE8 : A4; + 3FE9 : F2; + 3FEA : 4C; + 3FEB : 36; + 3FEC : F7; + 3FED : A9; + 3FEE : 3C; + 3FEF : 8D; + 3FF0 : 13; + 3FF1 : E8; + 3FF2 : AD; + 3FF3 : 40; + 3FF4 : E8; + 3FF5 : 09; + 3FF6 : 10; + 3FF7 : 8D; + 3FF8 : 40; + 3FF9 : E8; + 3FFA : 60; + 3FFB : CA; + 3FFC : 38; + 3FFD : FD; + 3FFE : 6B; + 3FFF : E6; +END; diff --git a/Commodore - Pet2001_MiST/rtl/roms/Pet2001_RomType2.mif b/Commodore - Pet2001_MiST/rtl/roms/Pet2001_RomType2.mif new file mode 100644 index 00000000..72f6ec61 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/roms/Pet2001_RomType2.mif @@ -0,0 +1,15344 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=16384; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 0000 : 40; + 0001 : C7; + 0002 : 57; + 0003 : C6; + 0004 : 1F; + 0005 : CC; + 0006 : FF; + 0007 : C7; + 0008 : A6; + 0009 : CA; + 000A : C0; + 000B : CA; + 000C : 62; + 000D : CF; + 000E : 06; + 000F : CB; + 0010 : AC; + 0011 : C8; + 0012 : AC; + 0013 : C7; + 0014 : 84; + 0015 : C7; + 0016 : 2F; + 0017 : C8; + 0018 : 2F; + 0019 : C7; + 001A : 8F; + 001B : C7; + 001C : D9; + 001D : C7; + 001E : 42; + 001F : C8; + 0020 : 3E; + 0021 : C7; + 0022 : 52; + 0023 : C8; + 0024 : 0F; + 0025 : D7; + 0026 : D4; + 0027 : FF; + 0028 : D7; + 0029 : FF; + 002A : DA; + 002B : FF; + 002C : 8C; + 002D : D2; + 002E : 06; + 002F : D7; + 0030 : 8A; + 0031 : C9; + 0032 : AA; + 0033 : C9; + 0034 : 6A; + 0035 : C7; + 0036 : B4; + 0037 : C5; + 0038 : 76; + 0039 : C5; + 003A : 90; + 003B : C9; + 003C : DD; + 003D : FF; + 003E : BF; + 003F : FF; + 0040 : C2; + 0041 : FF; + 0042 : 7C; + 0043 : CA; + 0044 : 5A; + 0045 : C5; + 0046 : 45; + 0047 : DB; + 0048 : D8; + 0049 : DB; + 004A : 64; + 004B : DB; + [004C..004D] : 00; + 004E : 59; + 004F : D2; + 0050 : 7A; + 0051 : D2; + 0052 : 5E; + 0053 : DE; + 0054 : 7F; + 0055 : DF; + 0056 : F6; + 0057 : D8; + 0058 : DA; + 0059 : DE; + 005A : D8; + [005B..005D] : DF; + 005E : 28; + 005F : E0; + 0060 : 8C; + 0061 : E0; + 0062 : E8; + 0063 : D6; + 0064 : 56; + 0065 : D6; + 0066 : 3F; + 0067 : D3; + 0068 : 87; + 0069 : D6; + 006A : 65; + 006B : D6; + 006C : C6; + 006D : D5; + 006E : DA; + 006F : D5; + 0070 : 06; + 0071 : D6; + 0072 : 11; + 0073 : D6; + 0074 : 79; + 0075 : 75; + 0076 : D7; + 0077 : 79; + 0078 : 35; + 0079 : D7; + 007A : 7B; + 007B : 36; + 007C : D9; + 007D : 7B; + 007E : 1D; + 007F : DA; + 0080 : 7F; + 0081 : 67; + 0082 : DE; + 0083 : 50; + 0084 : CA; + 0085 : CE; + 0086 : 46; + 0087 : C7; + 0088 : CE; + 0089 : 7D; + 008A : A0; + 008B : DE; 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+ 2C42 : 5C; + 2C43 : 62; + [2C44..2C46] : 42; + 2C47 : 00; + 2C48 : 08; + 2C49 : 00; + 2C4A : 18; + [2C4B..2C4D] : 08; + 2C4E : 1C; + 2C4F : 00; + 2C50 : 04; + 2C51 : 00; + 2C52 : 0C; + [2C53..2C55] : 04; + 2C56 : 44; + 2C57 : 38; + [2C58..2C59] : 40; + 2C5A : 44; + 2C5B : 48; + 2C5C : 50; + 2C5D : 68; + 2C5E : 44; + 2C5F : 00; + 2C60 : 18; + [2C61..2C65] : 08; + 2C66 : 1C; + [2C67..2C69] : 00; + 2C6A : 76; + [2C6B..2C6E] : 49; + [2C6F..2C71] : 00; + 2C72 : 5C; + 2C73 : 62; + [2C74..2C76] : 42; + [2C77..2C79] : 00; + 2C7A : 3C; + [2C7B..2C7D] : 42; + 2C7E : 3C; + [2C7F..2C81] : 00; + 2C82 : 5C; + [2C83..2C84] : 62; + 2C85 : 5C; + [2C86..2C87] : 40; + [2C88..2C89] : 00; + 2C8A : 3A; + [2C8B..2C8C] : 46; + 2C8D : 3A; + [2C8E..2C8F] : 02; + [2C90..2C91] : 00; + 2C92 : 5C; + 2C93 : 62; + [2C94..2C96] : 40; + [2C97..2C99] : 00; + 2C9A : 3E; + 2C9B : 40; + 2C9C : 3C; + 2C9D : 02; + 2C9E : 7C; + 2C9F : 00; + [2CA0..2CA1] : 10; + 2CA2 : 7C; + [2CA3..2CA4] : 10; + 2CA5 : 12; + 2CA6 : 0C; + [2CA7..2CA9] : 00; + [2CAA..2CAC] : 42; + 2CAD : 46; + 2CAE : 3A; + [2CAF..2CB1] : 00; + [2CB2..2CB4] : 42; + 2CB5 : 24; + 2CB6 : 18; + [2CB7..2CB9] : 00; + 2CBA : 41; + [2CBB..2CBD] : 49; + 2CBE : 36; + [2CBF..2CC1] : 00; + 2CC2 : 42; + 2CC3 : 24; + 2CC4 : 18; + 2CC5 : 24; + 2CC6 : 42; + [2CC7..2CC9] : 00; + [2CCA..2CCB] : 42; + 2CCC : 46; + 2CCD : 3A; + 2CCE : 02; + 2CCF : 3C; + [2CD0..2CD1] : 00; + 2CD2 : 7E; + 2CD3 : 04; + 2CD4 : 18; + 2CD5 : 20; + 2CD6 : 7E; + 2CD7 : 00; + 2CD8 : 3C; + [2CD9..2CDD] : 20; + 2CDE : 3C; + [2CDF..2CE0] : 00; + 2CE1 : 40; + 2CE2 : 20; + 2CE3 : 10; + 2CE4 : 08; + 2CE5 : 04; + 2CE6 : 02; + 2CE7 : 00; + 2CE8 : 3C; + [2CE9..2CED] : 04; + 2CEE : 3C; + [2CEF..2CF0] : 00; + 2CF1 : 08; + 2CF2 : 1C; + 2CF3 : 2A; + [2CF4..2CF7] : 08; + [2CF8..2CF9] : 00; + 2CFA : 10; + 2CFB : 20; + 2CFC : 7F; + 2CFD : 20; + 2CFE : 10; + [2CFF..2D07] : 00; + [2D08..2D0B] : 08; + [2D0C..2D0D] : 00; + 2D0E : 08; + 2D0F : 00; + [2D10..2D12] : 24; + [2D13..2D17] : 00; + [2D18..2D19] : 24; + 2D1A : 7E; + 2D1B : 24; + 2D1C : 7E; + [2D1D..2D1E] : 24; + 2D1F : 00; + 2D20 : 08; + 2D21 : 1E; + 2D22 : 28; + 2D23 : 1C; + 2D24 : 0A; + 2D25 : 3C; + 2D26 : 08; + [2D27..2D28] : 00; + 2D29 : 62; + 2D2A : 64; + 2D2B : 08; + 2D2C : 10; + 2D2D : 26; + 2D2E : 46; + 2D2F : 00; + 2D30 : 30; + [2D31..2D32] : 48; + 2D33 : 30; + 2D34 : 4A; + 2D35 : 44; + 2D36 : 3A; + 2D37 : 00; + 2D38 : 04; + 2D39 : 08; + 2D3A : 10; + [2D3B..2D3F] : 00; + 2D40 : 04; + 2D41 : 08; + [2D42..2D44] : 10; + 2D45 : 08; + 2D46 : 04; + 2D47 : 00; + 2D48 : 20; + 2D49 : 10; + [2D4A..2D4C] : 08; + 2D4D : 10; + 2D4E : 20; + 2D4F : 00; + 2D50 : 08; + 2D51 : 2A; + 2D52 : 1C; + 2D53 : 3E; + 2D54 : 1C; + 2D55 : 2A; + 2D56 : 08; + [2D57..2D58] : 00; + [2D59..2D5A] : 08; + 2D5B : 3E; + [2D5C..2D5D] : 08; + [2D5E..2D64] : 00; + [2D65..2D66] : 08; + 2D67 : 10; + [2D68..2D6A] : 00; + 2D6B : 7E; + [2D6C..2D74] : 00; + [2D75..2D76] : 18; + [2D77..2D78] : 00; + 2D79 : 02; + 2D7A : 04; + 2D7B : 08; + 2D7C : 10; + 2D7D : 20; + 2D7E : 40; + 2D7F : 00; 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+ [2DD3..2DD4] : 00; + 2DD5 : 08; + [2DD6..2DD9] : 00; + 2DDA : 08; + [2DDB..2DDC] : 00; + [2DDD..2DDE] : 08; + 2DDF : 10; + 2DE0 : 0E; + 2DE1 : 18; + 2DE2 : 30; + 2DE3 : 60; + 2DE4 : 30; + 2DE5 : 18; + 2DE6 : 0E; + [2DE7..2DE9] : 00; + 2DEA : 7E; + 2DEB : 00; + 2DEC : 7E; + [2DED..2DEF] : 00; + 2DF0 : 70; + 2DF1 : 18; + 2DF2 : 0C; + 2DF3 : 06; + 2DF4 : 0C; + 2DF5 : 18; + 2DF6 : 70; + 2DF7 : 00; + 2DF8 : 3C; + 2DF9 : 42; + 2DFA : 02; + 2DFB : 0C; + 2DFC : 10; + 2DFD : 00; + 2DFE : 10; + [2DFF..2E03] : 00; + 2E04 : FF; + [2E05..2E07] : 00; + 2E08 : 18; + 2E09 : 24; + 2E0A : 42; + 2E0B : 7E; + [2E0C..2E0E] : 42; + 2E0F : 00; + 2E10 : 7C; + [2E11..2E12] : 22; + 2E13 : 3C; + [2E14..2E15] : 22; + 2E16 : 7C; + 2E17 : 00; + 2E18 : 1C; + 2E19 : 22; + [2E1A..2E1C] : 40; + 2E1D : 22; + 2E1E : 1C; + 2E1F : 00; + 2E20 : 78; + 2E21 : 24; + [2E22..2E24] : 22; + 2E25 : 24; + 2E26 : 78; + 2E27 : 00; + 2E28 : 7E; + [2E29..2E2A] : 40; + 2E2B : 78; + [2E2C..2E2D] : 40; + 2E2E : 7E; + 2E2F : 00; + 2E30 : 7E; + [2E31..2E32] : 40; + 2E33 : 78; + [2E34..2E36] : 40; + 2E37 : 00; + 2E38 : 1C; + 2E39 : 22; + 2E3A : 40; + 2E3B : 4E; + 2E3C : 42; + 2E3D : 22; + 2E3E : 1C; + 2E3F : 00; + [2E40..2E42] : 42; + 2E43 : 7E; + [2E44..2E46] : 42; + 2E47 : 00; + 2E48 : 1C; + [2E49..2E4D] : 08; + 2E4E : 1C; + 2E4F : 00; + 2E50 : 0E; + [2E51..2E54] : 04; + 2E55 : 44; + 2E56 : 38; + 2E57 : 00; + 2E58 : 42; + 2E59 : 44; + 2E5A : 48; + 2E5B : 70; + 2E5C : 48; + 2E5D : 44; + 2E5E : 42; + 2E5F : 00; + [2E60..2E65] : 40; + 2E66 : 7E; + 2E67 : 00; + 2E68 : 42; + 2E69 : 66; + [2E6A..2E6B] : 5A; + [2E6C..2E6E] : 42; + 2E6F : 00; + 2E70 : 42; + 2E71 : 62; + 2E72 : 52; + 2E73 : 4A; + 2E74 : 46; + [2E75..2E76] : 42; + 2E77 : 00; + 2E78 : 18; + 2E79 : 24; + [2E7A..2E7C] : 42; + 2E7D : 24; + 2E7E : 18; + 2E7F : 00; + 2E80 : 7C; + [2E81..2E82] : 42; + 2E83 : 7C; + [2E84..2E86] : 40; + 2E87 : 00; + 2E88 : 18; + 2E89 : 24; + [2E8A..2E8B] : 42; + 2E8C : 4A; + 2E8D : 24; + 2E8E : 1A; + 2E8F : 00; + 2E90 : 7C; + [2E91..2E92] : 42; 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+ [2FC0..2FC2] : FF; + [2FC3..2FCC] : 00; + [2FCD..2FCF] : FF; + 2FD0 : 01; + 2FD1 : 02; + 2FD2 : 44; + 2FD3 : 48; + 2FD4 : 50; + 2FD5 : 60; + 2FD6 : 40; + [2FD7..2FDB] : 00; + [2FDC..2FDF] : F0; + [2FE0..2FE3] : 0F; + [2FE4..2FE7] : 00; + [2FE8..2FEB] : 08; + 2FEC : F8; + [2FED..2FEF] : 00; + [2FF0..2FF3] : F0; + [2FF4..2FF7] : 00; + [2FF8..2FFB] : F0; + [2FFC..2FFF] : 0F; + 3000 : 54; + [3001..3002] : 4F; + 3003 : 20; + 3004 : 4D; + 3005 : 41; + 3006 : 4E; + 3007 : 59; + 3008 : 20; + 3009 : 46; + 300A : 49; + 300B : 4C; + 300C : 45; + 300D : D3; + 300E : 46; + 300F : 49; + 3010 : 4C; + 3011 : 45; + 3012 : 20; + 3013 : 4F; + 3014 : 50; + 3015 : 45; + 3016 : CE; + 3017 : 46; + 3018 : 49; + 3019 : 4C; + 301A : 45; + 301B : 20; + 301C : 4E; + 301D : 4F; + 301E : 54; + 301F : 20; + 3020 : 4F; + 3021 : 50; + 3022 : 45; + 3023 : CE; + 3024 : 46; + 3025 : 49; + 3026 : 4C; + 3027 : 45; + 3028 : 20; + 3029 : 4E; + 302A : 4F; + 302B : 54; + 302C : 20; + 302D : 46; + 302E : 4F; + 302F : 55; + 3030 : 4E; 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+ 3FAA : F8; + 3FAB : 20; + 3FAC : A4; + 3FAD : F6; + 3FAE : 4C; + 3FAF : 56; + 3FB0 : FD; + 3FB1 : 43; + 3FB2 : 2E; + 3FB3 : 20; + 3FB4 : 30; + 3FB5 : 39; + 3FB6 : 37; + 3FB7 : 38; + 3FB8 : 20; + 3FB9 : 43; + 3FBA : 42; + 3FBB : 4D; + 3FBC : 20; + [3FBD..3FBF] : AA; + 3FC0 : 4C; + 3FC1 : 21; + 3FC2 : F5; + 3FC3 : 4C; + 3FC4 : A9; + 3FC5 : F2; + 3FC6 : 4C; + 3FC7 : 70; + 3FC8 : F7; + 3FC9 : 4C; + 3FCA : BC; + 3FCB : F7; + 3FCC : 4C; + 3FCD : 72; + 3FCE : F2; + 3FCF : 4C; + 3FD0 : E1; + 3FD1 : F1; + 3FD2 : 4C; + 3FD3 : 32; + 3FD4 : F2; + 3FD5 : 4C; + 3FD6 : C2; + 3FD7 : F3; + 3FD8 : 4C; + 3FD9 : 9E; + 3FDA : F6; + 3FDB : 4C; + 3FDC : B7; + 3FDD : F4; + 3FDE : 4C; + 3FDF : 84; + 3FE0 : F6; + 3FE1 : 4C; + 3FE2 : 0F; + 3FE3 : F3; + 3FE4 : 4C; + 3FE5 : D1; + 3FE6 : F1; + 3FE7 : 4C; + 3FE8 : 6E; + 3FE9 : F2; + 3FEA : 4C; + 3FEB : 29; + 3FEC : F7; + [3FED..3FF9] : AA; + 3FFA : FE; + 3FFB : FC; + 3FFC : D1; + 3FFD : FC; + 3FFE : 1B; + 3FFF : E6; +END; diff --git a/Commodore - Pet2001_MiST/rtl/scandoubler.v b/Commodore - Pet2001_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/sigma_delta_dac.v b/Commodore - Pet2001_MiST/rtl/sigma_delta_dac.v new file mode 100644 index 00000000..bba2c552 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=7) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= 1; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= ~SigmaLatch[MSBI+2]; + end +end + +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/sram.sv b/Commodore - Pet2001_MiST/rtl/sram.sv new file mode 100644 index 00000000..2e099419 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/sram.sv @@ -0,0 +1,262 @@ +// +// sram.v +// +// Static RAM controller implementation using SDRAM MT48LC16M16A2 +// +// Copyright (c) 2015,2016 Sorgelig +// +// Some parts of SDRAM code used from project: +// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// +// v2.1 - Add universal 8/16 bit mode. +// + +module sram +( + input init, // reset to initialize RAM + input clk, // clock ~100MHz + // + // SDRAM_* - signals to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + output SDRAM_CKE, // clock enable + // + input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte, + // 8bit mode: 2'b00 - use addr[0] to decide which byte to write + // Ignored while reading. + // + input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations. + output [15:0] dout, // data output to cpu + input [15:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output reg ready // dout is valid. Ready to accept new read/write. +); + +assign SDRAM_nCS = command[3]; +assign SDRAM_nRAS = command[2]; +assign SDRAM_nCAS = command[1]; +assign SDRAM_nWE = command[0]; +assign SDRAM_CKE = cke; +assign dout = latched ? data_l : data_d; + +// no burst configured +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write +localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz +localparam cycles_per_refresh = 14'd780; // (64000*100)/8192-1 Calc'd as (64ms @ 100MHz)/8192 rose +localparam startup_refresh_max = 14'b11111111111111; + +// SDRAM commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles; +reg [3:0] command = CMD_INHIBIT; +reg cke = 0; +reg [24:0] save_addr; + +reg latched; +reg [15:0] data; +wire[15:0] data_l = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]}; +wire[15:0] data_d = save_addr[0] ? {SDRAM_DQ[7:0], SDRAM_DQ[15:8]} : {SDRAM_DQ[15:8], SDRAM_DQ[7:0]}; + +typedef enum +{ + STATE_STARTUP, + STATE_OPEN_1, STATE_OPEN_2, + STATE_WRITE, + STATE_READ, + STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3, + STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7 +} state_t; + +always @(posedge clk) begin + reg old_we, old_rd; + reg [CAS_LATENCY:0] data_ready_delay; + + reg [15:0] new_data; + reg [1:0] new_wtbt; + reg new_we; + reg new_rd; + reg save_we = 1; + + state_t state = STATE_STARTUP; + + command <= CMD_NOP; + refresh_count <= refresh_count+1'b1; + + data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]}; + + // make it ready 1T in advance + if(data_ready_delay[1]) {latched, ready} <= {1'b0, 1'b1}; + if(data_ready_delay[0]) {latched, data} <= {1'b1, SDRAM_DQ}; + + case(state) + STATE_STARTUP: begin + //------------------------------------------------------------------------ + //-- This is the initial startup state, where we wait for at least 100us + //-- before starting the start sequence + //-- + //-- The initialisation is sequence is + //-- * de-assert SDRAM_CKE + //-- * 100us wait, + //-- * assert SDRAM_CKE + //-- * wait at least one cycle, + //-- * PRECHARGE + //-- * wait 2 cycles + //-- * REFRESH, + //-- * tREF wait + //-- * REFRESH, + //-- * tREF wait + //-- * LOAD_MODE_REG + //-- * 2 cycles wait + //------------------------------------------------------------------------ + cke <= 1; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + SDRAM_DQML <= 1; + SDRAM_DQMH <= 1; + SDRAM_A <= 0; + SDRAM_BA <= 0; + + // All the commands during the startup are NOPS, except these + if(refresh_count == startup_refresh_max-31) begin + // ensure all rows are closed + command <= CMD_PRECHARGE; + SDRAM_A[10] <= 1; // all banks + SDRAM_BA <= 2'b00; + end else if (refresh_count == startup_refresh_max-23) begin + // these refreshes need to be at least tREF (66ns) apart + command <= CMD_AUTO_REFRESH; + end else if (refresh_count == startup_refresh_max-15) + command <= CMD_AUTO_REFRESH; + else if (refresh_count == startup_refresh_max-7) begin + // Now load the mode register + command <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + end + + //------------------------------------------------------ + //-- if startup is complete then go into idle mode, + //-- get prepared to accept a new command, and schedule + //-- the first refresh cycle + //------------------------------------------------------ + if(!refresh_count) begin + state <= STATE_IDLE; + ready <= 1; + refresh_count <= 0; + end + end + + STATE_IDLE_7: state <= STATE_IDLE_6; + STATE_IDLE_6: state <= STATE_IDLE_5; + STATE_IDLE_5: state <= STATE_IDLE_4; + STATE_IDLE_4: state <= STATE_IDLE_3; + STATE_IDLE_3: state <= STATE_IDLE_2; + STATE_IDLE_2: state <= STATE_IDLE_1; + STATE_IDLE_1: begin + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + state <= STATE_IDLE; + // mask possible refresh to reduce colliding. + if(refresh_count > cycles_per_refresh) begin + //------------------------------------------------------------------------ + //-- Start the refresh cycle. + //-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz + //------------------------------------------------------------------------ + state <= STATE_IDLE_7; + command <= CMD_AUTO_REFRESH; + refresh_count <= refresh_count - cycles_per_refresh + 1'd1; + end + end + + STATE_IDLE: begin + // Priority is to issue a refresh if one is outstanding + if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1; + else if(new_rd | new_we) begin + new_we <= 0; + new_rd <= 0; + save_addr<= addr; + save_we <= new_we; + state <= STATE_OPEN_1; + command <= CMD_ACTIVE; + SDRAM_A <= addr[13:1]; + SDRAM_BA <= addr[24:23]; + end + end + + // ACTIVE-to-READ or WRITE delay >20ns (-75) + STATE_OPEN_1: state <= STATE_OPEN_2; + STATE_OPEN_2: begin + SDRAM_A <= {4'b0010, save_addr[22:14]}; + SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]); + SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]); + state <= save_we ? STATE_WRITE : STATE_READ; + end + + STATE_READ: begin + state <= STATE_IDLE_5; + command <= CMD_READ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + + // Schedule reading the data values off the bus + data_ready_delay[CAS_LATENCY] <= 1; + end + + STATE_WRITE: begin + state <= STATE_IDLE_5; + command <= CMD_WRITE; + SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]}; + ready <= 1; + end + endcase + + if(init) begin + state <= STATE_STARTUP; + refresh_count <= startup_refresh_max - sdram_startup_cycles; + end + + old_we <= we; + if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt}; + + old_rd <= rd; + if(rd & ~old_rd) begin + if(ready & ~save_we & (save_addr[24:1] == addr[24:1])) save_addr <= addr; + else {ready, new_rd} <= {1'b0, 1'b1}; + end +end + +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/tape.v b/Commodore - Pet2001_MiST/rtl/tape.v new file mode 100644 index 00000000..54c055d7 --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/tape.v @@ -0,0 +1,131 @@ +// +// tape.v +// +// tape implementation for the PET2001 core for the MiST board +// +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module tape +( + input reset, + input clk, + input ce_1m, + + input ioctl_download, + input tape_pause, + output reg tape_audio, + output tape_active, + + output reg tape_rd, + output reg [24:0] tape_addr, + input [7:0] tape_data +); + +reg [23:0] cnt; + +assign tape_active = (cnt>0); + +always @(posedge clk) begin + reg [23:0] size; + //reg [7:0] version; + reg [23:0] tmp; + reg [26:0] bit_cnt, bit_half; + reg ioctl_downloadD; + reg [2:0] reload32; + reg byte_ready; + reg [7:0] din; + reg play_pause; + reg pauseD; + + pauseD <= tape_pause; + if(tape_pause && ~pauseD) play_pause <= !play_pause; + + if(reset || ioctl_download) begin + cnt <= 0; + reload32 <= 0; + byte_ready <= 0; + play_pause <= 0; + tape_rd <= 0; + size <= 0; + bit_cnt <= 0; + ioctl_downloadD <= ioctl_download; + + end else if(ce_1m) begin + + ioctl_downloadD <= ioctl_download; + tape_rd <= 0; + + if(tape_rd) begin + byte_ready <= 1; + din <= tape_data; + end + + // download complete, start parsing + if(!ioctl_download && ioctl_downloadD) begin + cnt <= 8; + tape_rd <= 1; + tape_addr <= 12; + end + + if(cnt != 0) begin + if(byte_ready) begin + if(tape_addr<20) begin + cnt <= cnt - 1'd1; + tape_addr <= tape_addr + 1'd1; + byte_ready <= 0; + tape_rd <= 1; + case(tape_addr) + //12: version <= din; + 16: size[7:0] <= din; + 17: size[15:8] <= din; + 18: size[23:16] <= din; + 19: cnt <= size ? size : 24'd0; + default:; + endcase + end else begin + if(bit_cnt <= 1) begin + cnt <= cnt - 1'd1; + tape_addr <= tape_addr + 1'd1; + byte_ready <= 0; + tape_rd <= 1; + if(reload32 != 0) begin + tmp <= {din, tmp[23:8]}; + reload32 <= reload32 - 1'd1; + if(reload32 == 1) begin + bit_cnt <= {din, tmp[23:8], 3'd0}; + bit_half <= {din, tmp[23:8], 2'd0}; + tape_audio <= 1; + end + end else if(din == 0) begin + reload32 <= 3; + end else begin + bit_cnt <= {din, 3'd0}; + bit_half <= {din, 2'd0}; + tape_audio <= 1; + end + end + end + end + if(!play_pause && (bit_cnt>1)) begin + bit_cnt <= bit_cnt - 1'd1; + if(bit_cnt < bit_half) tape_audio <= 0; + end + end + end +end + +endmodule diff --git a/Commodore - Pet2001_MiST/rtl/via6522.v b/Commodore - Pet2001_MiST/rtl/via6522.v new file mode 100644 index 00000000..b4c9ecaf --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/via6522.v @@ -0,0 +1,483 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////// +// +// Engineer: Thomas Skibo +// +// Create Date: Sep 24, 2011 +// +// Module Name: via6522 +// +// Description: +// +// A simple implementation of the 6522 Versatile Interface Adapter (VIA). +// Tri-state lines aren't used. Instead, All PIA I/O signals have +// seperate "in" and "out" signals. Wire or ignore appropriately. +// +// A seperate "slow clock" (a synchronous pulse) runs the timers. +// Typically, it's 1Mhz. +// +///////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (C) 2011, Thomas Skibo. All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * The names of contributors may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL Thomas Skibo OR CONTRIBUTORS BE LIABLE FOR +// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +// SUCH DAMAGE. +// +////////////////////////////////////////////////////////////////////////////// + +module via6522 +( + output reg [7:0] data_out, // cpu interface + input [7:0] data_in, + input [3:0] addr, + input strobe, + input we, + + output reg irq, + + output reg [7:0] porta_out, + input [7:0] porta_in, + output reg [7:0] portb_out, + input [7:0] portb_in, + + input ca1_in, + output reg ca2_out, + input ca2_in, + output reg cb1_out, + input cb1_in, + output reg cb2_out, + input cb2_in, + + input ce, + input clk, + input reset +); + +// Register address offsets +parameter [3:0] + ADDR_PORTB = 4'h0, + ADDR_PORTA = 4'h1, + ADDR_DDRB = 4'h2, + ADDR_DDRA = 4'h3, + ADDR_TIMER1_LO = 4'h4, + ADDR_TIMER1_HI = 4'h5, + ADDR_TIMER1_LATCH_LO = 4'h6, + ADDR_TIMER1_LATCH_HI = 4'h7, + ADDR_TIMER2_LO = 4'h8, + ADDR_TIMER2_HI = 4'h9, + ADDR_SR = 4'ha, + ADDR_ACR = 4'hb, + ADDR_PCR = 4'hc, + ADDR_IFR = 4'hd, + ADDR_IER = 4'he, + ADDR_PORTA_NH = 4'hf; + +wire wr_strobe = strobe && we; +wire rd_strobe = strobe && !we; + +/////////////////////////////////////////////////// +// IER - Interrupt Enable Register +reg [6:0] ier; + +always @(posedge clk) begin + if (reset) ier <= 7'd0; + else if (wr_strobe && addr == ADDR_IER) ier <= data_in[7] ? (ier | data_in[6:0]) : (ier & ~data_in[6:0]); +end + +//////////////////////////////////////////////////// +// PCR - Peripheral Control Register +reg [7:0] pcr; + +always @(posedge clk) begin + if (reset) pcr <= 8'h00; + else if (wr_strobe && addr == ADDR_PCR) pcr <= data_in; +end + +////////////////////////////////////////////////////// +// ACR - Auxiliary Control Register +reg [7:0] acr; + +always @(posedge clk) begin + if (reset) acr <= 8'h00; + else if (wr_strobe && addr == ADDR_ACR) acr <= data_in; +end + +///////////////////////////////////////////////////// +// PORTs and DDRs +reg [7:0] ddra; +reg [7:0] ddrb; +reg pb7_nxt; // generated by timer1 logic, used when acr7 is set + +// Implement PORTA (out) +always @(posedge clk) begin + if (reset) porta_out <= 8'h00; + else if (wr_strobe && (addr == ADDR_PORTA || addr == ADDR_PORTA_NH)) porta_out <= data_in; +end + +// Implement DDRA +always @(posedge clk) begin + if (reset) ddra <= 8'h00; + else if (wr_strobe && addr == ADDR_DDRA) ddra <= data_in; +end + +// Implement PORTB (out). +always @(posedge clk) begin + if (reset) portb_out[6:0] <= 7'h00; + else if (wr_strobe && addr == ADDR_PORTB) portb_out[6:0] <= data_in[6:0]; +end + +always @(posedge clk) begin + if (reset) portb_out[7] <= 1'b0; + else if (acr[7]) portb_out[7] <= pb7_nxt; + else if (wr_strobe && addr == ADDR_PORTB) portb_out[7] <= data_in[7]; +end + +// Implement DDRB +always @(posedge clk) begin + if (reset) ddrb <= 8'h00; + else if (wr_strobe && addr == ADDR_DDRB) ddrb <= data_in; +end + +//////////////////////////////////////////////////////// +// CA interrupt logic +reg irq_ca1; +reg irq_ca2; + +// CA1 and CA2 transition logic. +reg ca1_in_1; +reg ca2_in_1; +always @(posedge clk) begin + ca1_in_1 <= ca1_in; + ca2_in_1 <= ca2_in; +end + +// detect "active" transitions. +wire ca1_act_trans = ((ca1_in && !ca1_in_1 && pcr[0]) || + (!ca1_in && ca1_in_1 && !pcr[0])); +wire ca2_act_trans = ((ca2_in && !ca2_in_1 && pcr[2]) || + (!ca2_in && ca2_in_1 && !pcr[2])); + + // logic for clearing CA1 and CA2 interrupt bits. +wire irq_ca1_clr = ((strobe && addr == ADDR_PORTA) || + (wr_strobe && addr == ADDR_IFR && data_in[1])); +wire irq_ca2_clr = ((strobe && addr == ADDR_PORTA) || + (wr_strobe && addr == ADDR_IFR && data_in[0])); + +always @(posedge clk) begin + if (reset || (irq_ca1_clr && !ca1_act_trans)) irq_ca1 <= 1'b0; + else if (ca1_act_trans) irq_ca1 <= 1'b1; +end + +always @(posedge clk) begin + if (reset || (irq_ca2_clr && !ca2_act_trans)) irq_ca2 <= 1'b0; + else if (ca2_act_trans) irq_ca2 <= 1'b1; +end + + +//////////////////////////////////////////////////////// +// CB logic +reg irq_cb1; +reg irq_cb2; + +// transition logic +reg cb1_in_1; +reg cb2_in_1; +always @(posedge clk) begin + cb1_in_1 <= cb1_in; + cb2_in_1 <= cb2_in; +end + +// detect "active" transitions. +wire cb1_act_trans = ((cb1_in && !cb1_in_1 && pcr[4]) || + (!cb1_in && cb1_in_1 && !pcr[4])); +wire cb2_act_trans = ((cb2_in && !cb2_in_1 && pcr[6]) || + (!cb2_in && cb2_in_1 && !pcr[6])); + +// logic for clearing CB1 and CB2 interrupt bits. +wire irq_cb1_clr = ((strobe && addr == ADDR_PORTB) || + (wr_strobe && addr == ADDR_IFR && data_in[4])); +wire irq_cb2_clr = ((strobe && addr == ADDR_PORTB) || + (wr_strobe && addr == ADDR_IFR && data_in[3])); + +always @(posedge clk) begin + if (reset || (irq_cb1_clr && !cb1_act_trans)) irq_cb1 <= 1'b0; + else if (cb1_act_trans) irq_cb1 <= 1'b1; +end + +always @(posedge clk) begin + if (reset || (irq_cb2_clr && !cb2_act_trans)) irq_cb2 <= 1'b0; + else if (cb2_act_trans) irq_cb2 <= 1'b1; +end + +/////////////////////////////////////////////////// +// CA2/CB2 output modes +always @(posedge clk) begin + case (pcr[3:1]) + 3'b100: ca2_out <= irq_ca1; + 3'b101: ca2_out <= !ca1_act_trans; + 3'b111: ca2_out <= 1'b1; + default: ca2_out <= 1'b0; + endcase +end + +reg cb2_out_r; +wire portb_wr_strobe = wr_strobe && addr == ADDR_PORTB; +wire cb2_sr_out; + +always @(posedge clk) begin + if (reset || (portb_wr_strobe && !cb1_act_trans)) cb2_out_r <= 1'b0; + else if (cb1_act_trans) cb2_out_r <= 1'b1; +end + +always @(posedge clk) begin + if (acr[4]) cb2_out <= cb2_sr_out; + else begin + case (pcr[7:5]) + 3'b100: cb2_out <= cb2_out_r; + 3'b101: cb2_out <= !portb_wr_strobe; + 3'b111: cb2_out <= 1'b1; + default: cb2_out <= 1'b0; + endcase + end +end + +////////////////////////////////////////////////////////// +// Implement PORTA (in) latch +reg [7:0] porta_in_r; +always @(posedge clk) begin + if (!acr[0] || !irq_ca1) porta_in_r <= porta_in; +end + +// Implement PORTB (in) latch +reg [7:0] portb_in_r; +always @(posedge clk) begin + if (!acr[1] || !irq_cb1) portb_in_r <= portb_in; +end + +/////////////////////////////////////////////////// +// Timers +reg [15:0] timer1; +reg [7:0] timer1_latch_lo; +reg [7:0] timer1_latch_hi; + +reg [15:0] timer2; +reg [7:0] timer2_latch_lo; + +reg irq_t1_one_shot; +reg irq_t1; +reg irq_t2_one_shot; +reg irq_t2; + +// TIMER1 +always @(posedge clk) begin + if (reset) timer1 <= 16'hffff; + else if (wr_strobe && addr == ADDR_TIMER1_HI) timer1 <= {data_in, timer1_latch_lo}; + else if (timer1 == 16'h0000 && ce && acr[6]) timer1 <= {timer1_latch_hi, timer1_latch_lo}; + else if (ce) timer1 <= timer1 - 1'b1; +end + +// T1 latch lo +always @(posedge clk) begin + if (reset) timer1_latch_lo <= 8'hff; + else if (wr_strobe && (addr == ADDR_TIMER1_LO || addr == ADDR_TIMER1_LATCH_LO)) timer1_latch_lo <= data_in; +end + +// T1 latch hi +always @(posedge clk) begin + if (reset) timer1_latch_hi <= 8'hff; + else if (wr_strobe && (addr == ADDR_TIMER1_HI || addr == ADDR_TIMER1_LATCH_HI)) timer1_latch_hi <= data_in; +end + +// "one-shot" logic so we only get an interrupt on first counter roll-over +always @(posedge clk) begin + if (reset) irq_t1_one_shot <= 1'b0; + else if (wr_strobe && addr == ADDR_TIMER1_HI) irq_t1_one_shot <= 1'b1; + else if (timer1 == 16'h0000 && ce) irq_t1_one_shot <= 1'b0; +end + +// T1 interrupt set and clear logic +wire irq_t1_set = (timer1 == 16'h0000 && ce && (irq_t1_one_shot || acr[6])); +wire irq_t1_clr = ((wr_strobe && addr == ADDR_TIMER1_HI) || + (wr_strobe && addr == ADDR_TIMER1_LATCH_HI) || + (rd_strobe && addr == ADDR_TIMER1_LO) || + (wr_strobe && addr == ADDR_IFR && data_in[6])); + +// T1 IRQ +always @(posedge clk) begin + if (reset || irq_t1_clr) irq_t1 <= 1'b0; + else if (irq_t1_set) irq_t1 <= 1'b1; +end + +// I forget what this is for +always @(posedge clk) begin + if (reset) pb7_nxt <= 1'b1; + else if (wr_strobe && addr == ADDR_TIMER1_HI) pb7_nxt <= 1'b0; + else if (timer1 == 16'h0001 && ce) pb7_nxt <= !pb7_nxt; +end + +// TIMER2 +always @(posedge clk) begin + if (reset) timer2 <= 16'hffff; + else if (wr_strobe && addr == ADDR_TIMER2_HI) timer2 <= {data_in, timer2_latch_lo}; + else if ((!acr[5] || !portb_in[6]) && ce) timer2 <= timer2 - 1'b1; +end + +// T2 latch lo (i.e. writes to T2L) +always @(posedge clk) begin + if (reset) timer2_latch_lo <= 8'hff; + else if (wr_strobe && addr == ADDR_TIMER2_LO) timer2_latch_lo <= data_in; +end + +// T2 IRQ "one-shot" logic +always @(posedge clk) begin + if (reset) irq_t2_one_shot <= 1'b0; + else if (wr_strobe && addr == ADDR_TIMER2_HI) irq_t2_one_shot <= 1'b1; + else if (timer2 == 16'h0000 && ce) irq_t2_one_shot <= 1'b0; +end + +// T2 IRQ set and clear logic +wire irq_t2_set = (timer2 == 16'h0000 && ce && irq_t2_one_shot); +wire irq_t2_clr = ((wr_strobe && addr == ADDR_TIMER2_HI) || + (rd_strobe && addr == ADDR_TIMER2_LO) || + (wr_strobe && addr == ADDR_IFR && data_in[5])); + +// T2 IRQ +always @(posedge clk) begin + if (reset || irq_t2_clr) irq_t2 <= 1'b0; + else if (irq_t2_set) irq_t2 <= 1'b1; +end + + +//////////////////////////////////////////////////////// +// SR - shift register +reg [7:0] sr; +reg [2:0] sr_cntr; +reg [7:0] sr_clk_div_ctr; +reg sr_clk_div; +reg irq_sr; +reg sr_go; +reg do_shift; + +always @(posedge clk) begin + if (reset) sr <= 8'h00; + else if (wr_strobe && addr == ADDR_SR) sr <= data_in; + else if (do_shift) sr <= { sr[6:0], (acr[4] ? sr[7] : cb2_in) }; +end + +assign cb2_sr_out = sr[7]; + +always @(posedge clk) begin + if (reset) sr_clk_div_ctr <= 8'd0; + else if (ce && sr_clk_div_ctr == 8'd0) sr_clk_div_ctr <= timer2_latch_lo; + else if (ce) sr_clk_div_ctr <= sr_clk_div_ctr - 1'b1; +end + +always @(posedge clk) begin + if (reset) sr_clk_div <= 1'b0; + else sr_clk_div <= (ce && sr_clk_div_ctr == 8'd0); +end + +always @(posedge clk) begin + if (reset || (strobe && addr == ADDR_SR)) sr_cntr <= 3'd7; + else if (do_shift) sr_cntr <= sr_cntr - 1'b1; +end + +// SR IRQ set and clr logic +wire irq_sr_set = do_shift && sr_cntr == 3'b000; +wire irq_sr_clr = ((strobe && addr == ADDR_SR) || (wr_strobe && addr == ADDR_IFR && data_in[2])); + +// SR IRQ +always @(posedge clk) begin + if (reset || (irq_sr_clr && !irq_sr_set)) irq_sr <= 1'b0; + else if (irq_sr_set) irq_sr <= 1'b1; +end + +always @(posedge clk) begin + if (reset) sr_go <= 1'b0; + else if (strobe && addr == ADDR_SR) sr_go <= 1'b1; + else if (irq_sr_set) sr_go <= 1'b0; +end + +// cominatorial logic for do_shift signal. +always @(sr_clk_div or ce or cb1_act_trans or sr_go or acr) begin + case (acr[4:2]) + 3'b000: do_shift = 1'b0; + 3'b100: do_shift = sr_clk_div; + 3'b001, + 3'b101: do_shift = (sr_go && sr_clk_div); + 3'b010, + 3'b110: do_shift = (sr_go && ce); + 3'b011, + 3'b111: do_shift = cb1_act_trans; + endcase +end + +always @(posedge clk) begin + if (reset) cb1_out <= 1'b1; + else if (do_shift) cb1_out <= !cb1_out; +end + +//////////////////////////////////////////////////////// +// IRQ and enable logic. +// + +// IFR register (not including bit 7) +wire [6:0] ifr = { irq_t1, irq_t2, irq_cb1, irq_cb2, irq_sr, irq_ca1, irq_ca2 }; + +// IRQ combinatorial logic +wire irq_p = |{ (ifr & ier) }; + +// IRQ output +always @(posedge clk) begin + if (reset) irq <= 1'b0; + else irq <= irq_p; +end + +/////////////////////////////////////////////////// +// Read data mux +wire [7:0] porta = (porta_out & ddra) | (porta_in_r & ~ddra); +wire [7:0] portb = (portb_out & ddrb) | (portb_in_r & ~ddrb); + +always @(*) begin + case (addr) + ADDR_PORTB: data_out = portb; + ADDR_PORTA: data_out = porta; + ADDR_DDRB: data_out = ddrb; + ADDR_DDRA: data_out = ddra; + ADDR_TIMER1_LO: data_out = timer1[7:0]; + ADDR_TIMER1_HI: data_out = timer1[15:8]; + ADDR_TIMER1_LATCH_LO: data_out = timer1_latch_lo; + ADDR_TIMER1_LATCH_HI: data_out = timer1_latch_hi; + ADDR_TIMER2_LO: data_out = timer2[7:0]; + ADDR_TIMER2_HI: data_out = timer2[15:8]; + ADDR_IER: data_out = {1'b1, ier}; + ADDR_PCR: data_out = pcr; + ADDR_ACR: data_out = acr; + ADDR_IFR: data_out = {irq_p, ifr}; + ADDR_SR: data_out = sr; + ADDR_PORTA_NH: data_out = porta; + default: data_out = 8'hXX; + endcase +end + +endmodule // via6522 diff --git a/Commodore - Pet2001_MiST/rtl/video_mixer.sv b/Commodore - Pet2001_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Commodore - Pet2001_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Commodore MAX/MAX.qpf b/Commodore MAX/MAX.qpf new file mode 100644 index 00000000..dc3a3a2c --- /dev/null +++ b/Commodore MAX/MAX.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 16:51:32 December 14, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "16:51:32 December 14, 2017" + +# Revisions + +PROJECT_REVISION = "MAX" diff --git a/Commodore MAX/MAX.qsf b/Commodore MAX/MAX.qsf new file mode 100644 index 00000000..828985b1 --- /dev/null +++ b/Commodore MAX/MAX.qsf @@ -0,0 +1,172 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 16:51:32 December 14, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# MAX_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_46 -to UART_TX + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY MAX +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:51:32 DECEMBER 14, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VHDL_FILE rtl/sid_voice.vhd +set_global_assignment -name VHDL_FILE rtl/sid_components.vhd +set_global_assignment -name VHDL_FILE rtl/sid_6581.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/MAX.sv +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name QIP_FILE rtl/COLRAM.qip +set_global_assignment -name QIP_FILE rtl/MAINRAM.qip +set_global_assignment -name VHDL_FILE rtl/cpu_6510.vhd +set_global_assignment -name VHDL_FILE rtl/cpu65xx_e.vhd +set_global_assignment -name VHDL_FILE rtl/cpu65xx_fast.vhd +set_global_assignment -name VHDL_FILE rtl/fpga64_rgbcolor.vhd +set_global_assignment -name VERILOG_FILE rtl/user_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/data_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VHDL_FILE rtl/cia_6526.vhd +set_global_assignment -name VERILOG_FILE rtl/pla_6703.v +set_global_assignment -name VHDL_FILE rtl/vic_656x_a.vhd +set_global_assignment -name VHDL_FILE rtl/vic_656x_e.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Commodore MAX/Schematic/326100.bmp b/Commodore MAX/Schematic/326100.bmp new file mode 100644 index 00000000..816401da Binary files /dev/null and b/Commodore MAX/Schematic/326100.bmp differ diff --git a/Commodore MAX/Schematic/326100.png b/Commodore MAX/Schematic/326100.png new file mode 100644 index 00000000..8987c18b Binary files /dev/null and b/Commodore MAX/Schematic/326100.png differ diff --git a/Commodore MAX/Schematic/Max_schematic.jpg b/Commodore MAX/Schematic/Max_schematic.jpg new file mode 100644 index 00000000..b23f2e97 Binary files /dev/null and b/Commodore MAX/Schematic/Max_schematic.jpg differ diff --git a/Commodore MAX/Schematic/scematic.pdf b/Commodore MAX/Schematic/scematic.pdf new file mode 100644 index 00000000..15505744 Binary files /dev/null and b/Commodore MAX/Schematic/scematic.pdf differ diff --git a/Commodore MAX/Schematic/ultimaxSchematic.gif b/Commodore MAX/Schematic/ultimaxSchematic.gif new file mode 100644 index 00000000..119f1498 Binary files /dev/null and b/Commodore MAX/Schematic/ultimaxSchematic.gif differ diff --git a/Commodore MAX/clean.bat b/Commodore MAX/clean.bat new file mode 100644 index 00000000..d76d65c1 --- /dev/null +++ b/Commodore MAX/clean.bat @@ -0,0 +1,13 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +del PLLJ_PLLSPE_INFO.txt +del *.qws +del *.ppf +del *.qip +pause diff --git a/Commodore MAX/rtl/COLRAM.qip b/Commodore MAX/rtl/COLRAM.qip new file mode 100644 index 00000000..25074317 --- /dev/null +++ b/Commodore MAX/rtl/COLRAM.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "COLRAM.v"] diff --git a/Commodore MAX/rtl/COLRAM.v b/Commodore MAX/rtl/COLRAM.v new file mode 100644 index 00000000..989754a8 --- /dev/null +++ b/Commodore MAX/rtl/COLRAM.v @@ -0,0 +1,177 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: COLRAM.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module COLRAM ( + address, + clock, + data, + rden, + wren, + q); + + input [9:0] address; + input clock; + input [3:0] data; + input rden; + input wren; + output [3:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [3:0] sub_wire0; + wire [3:0] q = sub_wire0[3:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .rden_a (rden), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 4, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "4" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]" +// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0 +// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore MAX/rtl/MAINRAM.qip b/Commodore MAX/rtl/MAINRAM.qip new file mode 100644 index 00000000..91977785 --- /dev/null +++ b/Commodore MAX/rtl/MAINRAM.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "MAINRAM.v"] diff --git a/Commodore MAX/rtl/MAINRAM.v b/Commodore MAX/rtl/MAINRAM.v new file mode 100644 index 00000000..878b2d98 --- /dev/null +++ b/Commodore MAX/rtl/MAINRAM.v @@ -0,0 +1,177 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: MAINRAM.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module MAINRAM ( + address, + clock, + data, + rden, + wren, + q); + + input [10:0] address; + input clock; + input [7:0] data; + input rden; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .rden_a (rden), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2048, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 11, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Commodore MAX/rtl/MAX.sv b/Commodore MAX/rtl/MAX.sv new file mode 100644 index 00000000..6ea7fd5f --- /dev/null +++ b/Commodore MAX/rtl/MAX.sv @@ -0,0 +1,354 @@ +module MAX( + input CLOCK_27, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output LED, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0 + + ); + +`include "build_id.sv" + +localparam CONF_STR = { + "Commodore MAX;e0;", + "O2,SID Filter,On,Off;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T5,Reset;", + "V,v0.0.",`BUILD_DATE + }; + +wire clk_cpu, clk_sid, clk_ce, phi0_cpu; +wire locked; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; + + +reg [7:0] reset_cnt; +always @(posedge clk_cpu) begin + if(!locked || buttons[1] || status[0] || status[5])// | dio_download) + reset_cnt <= 8'h0; + else if(reset_cnt != 8'd255) + reset_cnt <= reset_cnt + 8'd1; +end + +wire reset = (reset_cnt != 8'd255); + +wire [15:0]ADDR_BUS; +wire [15:0]VIC_ADDR_BUS; +tri [7:0]DATA_BUS; +wire BA; +wire RW; +wire nRW_PLA; +wire nRAM; +wire nEXTRAM; +wire nVIC; +wire nSID; +wire nCIA_PLA; +wire nCIA; +wire nROML; +wire nROMH; +wire nCOLRAM; +wire nIRQ; +wire nNMI; +wire BUF; +wire AEC; + +// Video +wire hs, vs; +wire [5:0]r, g, b; +wire [17:0]audio; +//EXPANSIONS PORT +wire SP; +wire CNT; +//Joystick +wire [7:0]JoyA,JoyB; + + +wire [7:0]CPU_DI; +wire [7:0]CPU_DO; +wire [7:0]cpuIO; +//CIA +wire [7:0]CIA_DO; +//VIC +wire [7:0]VIC_DO; +wire [3:0]VIC_ColIndex; +//Main RAM +wire [7:0]RAM_DO; +//Color RAM +wire [3:0]COL_DI; +wire [3:0]COL_DO; +wire [3:0]COL_rDO; +//SID +wire [7:0]SID_DO; +//CARD +wire [7:0]CARD_DO; +wire [7:0]cia_pai; +wire [7:0]cia_pao; +wire [7:0]cia_pbi; +wire [7:0]cia_pbo; + +wire enableCPU, enableCIA, enableVIC = 1; +wire enablePixel; +wire pulseRd; + +pll pll( + .inclk0(CLOCK_27), + .areset(0), + .c0(clk_cpu),//32 + .c1(clk_sid),//1 + .c2(clk_ce),//8 + .c3(phi0_cpu),//todo + .locked(locked) + ); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .conf_str(CONF_STR), + .clk_sys(clk_cpu), + .SPI_SCK(SPI_SCK), + .CONF_DATA0(CONF_DATA0), + .SPI_SS2(SPI_SS2), + .SPI_DO(SPI_DO), + .SPI_DI(SPI_DI), + .buttons(buttons), + .switches(switches), + .scandoubler_disable(scandoubler_disable), + .ypbpr(ypbpr), + .status(status), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick_0(JoyA), + .joystick_1(JoyB) +); + +video_mixer #(.LINE_LENGTH(600), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_cpu), + .ce_pix(clk_ce), + .ce_pix_actual(clk_ce), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .scandoubler_disable(1),//scandoubler_disable), + .hq2x(status[4:3]==1), + .ypbpr(ypbpr), + .ypbpr_full(1), + .R(r), + .G(g), + .B(b), + .mono(0), + .HSync(hs), + .VSync(vs), + .line_start(0), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS) +); + +sigma_delta_dac sigma_delta_dac +( + .DACout(AUDIO_L), + .DACin(audio), + .CLK(clk_cpu), + .RESET(0) +); + +assign AUDIO_R = AUDIO_L; + +//CPU MOS6510 +cpu_6510 U5 ( + .clk(clk_cpu), + .reset(reset), + .enable(enableCPU), + .nmi_n(nNMI), + .nmi_ack(), + .irq_n(nIRQ), + .CPUdi(CPU_DI), + .CPUdo(CPU_DO), + .addr(ADDR_BUS), + .we(RW), + .doIO(cpuIO), + .diIO("00010111") + ); + +//PLA MOS6703 +pla_6703 pla_6703 ( + .A(ADDR_BUS[15:10]), + .CLK(clk_cpu), + .BA(BA), + .RW_IN(~RW), + .RAM(nRAM), //invert + .EXRAM(nEXTRAM), //invert + .VIC(nVIC), //invert + .SID(nSID), //invert + .CIA(nCIA_PLA), //invert + .COLRAM(nCOLRAM), //invert + .ROML(nROML), //invert + .ROMH(nROMH), //invert + .BUF(BUF), //not invert + .RW_OUT(nRW_PLA) //invert + ); + + +always@(posedge clk_cpu) begin + if (~nRW_PLA) begin + if (~nRAM) begin + RAM_DO =CPU_DI; + if (~nVIC) begin + VIC_DO =CPU_DI; + end + end + end + if (~RW) begin + if (~nSID) begin + SID_DO =CPU_DI; + end + // if (~nCARD) begin +// CARD_DO =CPU_DI; +// end + if (~nCIA_PLA) begin + CIA_DO =CPU_DI; + end + end + COL_DO = COL_rDO ? (BUF & ~nCOLRAM) : 4'b0; +end + + + +//COLRAM 1024x4 +COLRAM U11 ( + .address(ADDR_BUS[9:0]), + .clock(clk_cpu), + .data(CPU_DO), + .rden(~nCOLRAM), + .wren(~nRW_PLA), + .q(COL_rDO) + ); + +//MAINRAM 2048x8 +MAINRAM U6 ( + .address(ADDR_BUS[10:0]), + .clock(clk_cpu), + .data(CPU_DO), + .rden(~nRAM), + .wren(~nRW_PLA), + .q(CPU_DI) + ); + + +//VIC MOS6566 +vic_656x vic_656x ( + .clk(clk_cpu), + .phi(phi0_cpu),// phi = 0 is VIC cycle-- phi = 1 is CPU cycle (only used by VIC when BA is low) + .enaData(enablePixel), + .enaPixel(enableVIC), + .baSync(0), + .ba(BA), + .mode6569(0),// PAL 63 cycles and 312 lines + .mode6567old(1),// old NTSC 64 cycles and 262 line + .mode6567R8(0),// new NTSC 65 cycles and 263 line + .mode6572(0),// PAL-N 65 cycles and 312 lines + .reset(reset), + .cs(~nVIC), + .we(~nRW_PLA), + .rd(pulseRd), + .lp_n(), + .aRegisters(DATA_BUS[5:0]), + .diRegisters(CPU_DO), + .datai(CPU_DO), + .diColor(COL_DO), + .datao(VIC_DO), + .vicAddr(VIC_ADDR_BUS[13:0]), + .irq_n(nIRQ), + .hSync(hs), + .vSync(vs), + .colorIndex(VIC_ColIndex), + .debugX(), + .debugY(), + .vicRefresh(), + .addrValid() + ); + +fpga64_rgbcolor fpga64_rgbcolor ( + .index(VIC_ColIndex), + .r(r), + .g(g), + .b(b) + ); + +//CIA MOS6526 +cia_6526 cia_6526 ( + .clk(clk_cpu), + .todClk(vs), + .reset(reset), + .enable(enableCIA), + .cs(~nCIA), + .we(~RW), + .rd(pulseRd), + .addr(ADDR_BUS[3:0]), + .CIAdi(CPU_DO), + .CIAdo(CIA_DO), + .ppai(cia_pai),//Keyboard + .ppao(cia_pao),//Keyboard + .ppbi(cia_pbi),//Keyboard + .ppbo(cia_pbo),//Keyboard + .flag_n(1), + .sp(SP), + .cnt(CNT), + .irq_n(~nIRQ) + ); + +//SID MOS6581 +sid_6581 sid_6581 ( + .clk32(clk_cpu), + .clk_1MHz(clk_sid), + .reset(reset), + .cs(~nSID), + .we(~RW), + .addr({4'b0,ADDR_BUS[3:0]}), + .data_i(CPU_DO), + .data_o(SID_DO), + .poti_x(~(cia_pao[7] & JoyA[5]) | (cia_pao[6] & JoyB[5])),//todo + .poti_y(~(cia_pao[7] & JoyA[6]) | (cia_pao[6] & JoyB[6])),//todo + .audio_data(audio) + ); + +cart cart( + .clk0(clk_cpu), + .addr(ADDR_BUS), + .data_i(CPU_DO), + .data_o(CART_DO), + .nmi(nNMI), + .reset(reset), + .romL(nROML), + .romH(nROMH), + .rw_pla_n(nRW_PLA), + .ba(BA), + .cia_pla_n(nCIA_PLA), + .cia_n(nCIA), + .cnt(CNT), + .exram_n(nEXTRAM), + .sp(SP), + .rw_n(RW), + .irq_n(nIRQ) + ); + +endmodule \ No newline at end of file diff --git a/Commodore MAX/rtl/build_id.sv b/Commodore MAX/rtl/build_id.sv new file mode 100644 index 00000000..7d0ba7de --- /dev/null +++ b/Commodore MAX/rtl/build_id.sv @@ -0,0 +1,2 @@ +`define BUILD_DATE "180103" +`define BUILD_TIME "021747" diff --git a/Commodore MAX/rtl/build_id.tcl b/Commodore MAX/rtl/build_id.tcl new file mode 100644 index 00000000..be673dac --- /dev/null +++ b/Commodore MAX/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.sv" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Commodore MAX/rtl/cart.sv b/Commodore MAX/rtl/cart.sv new file mode 100644 index 00000000..83235c84 --- /dev/null +++ b/Commodore MAX/rtl/cart.sv @@ -0,0 +1,21 @@ +module cart( + input clk0, + input [15:0] addr, + input [7:0] data_i, + output [7:0] data_o, + output reg nmi, + input reset, + input romL, // romL signal in + input romH, + input rw_pla_n, + input ba, + input cia_pla_n, + input cia_n, + input cnt, + input exram_n, + input sp, + input rw_n, + input irq_n +); + +endmodule \ No newline at end of file diff --git a/Commodore MAX/rtl/cia_6526.vhd b/Commodore MAX/rtl/cia_6526.vhd new file mode 100644 index 00000000..a9766508 --- /dev/null +++ b/Commodore MAX/rtl/cia_6526.vhd @@ -0,0 +1,783 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- 6526 Complex Interface Adapter +-- +-- rev 1 - june17 / TOD alarms +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cia_6526 is + generic ( + todEnabled : std_logic := '0' + ); + port ( + clk: in std_logic; + todClk: in std_logic; + reset: in std_logic; + enable: in std_logic; + cs: in std_logic; + we: in std_logic; -- Write strobe + rd: in std_logic; -- Read strobe + + addr: in unsigned(3 downto 0); + CIAdi: in unsigned(7 downto 0); + CIAdo: out unsigned(7 downto 0); + + ppai: in unsigned(7 downto 0); + ppao: out unsigned(7 downto 0); + ppad: out unsigned(7 downto 0); + + ppbi: in unsigned(7 downto 0); + ppbo: out unsigned(7 downto 0); + ppbd: out unsigned(7 downto 0); + + flag_n: in std_logic; + sp: out std_logic; + cnt: out std_logic; + irq_n: out std_logic + ); +end cia_6526; + +-- ----------------------------------------------------------------------- + +architecture Behavioral of cia_6526 is + -- IO ports + signal pra: unsigned(7 downto 0); + signal prb: unsigned(7 downto 0); + signal ddra: unsigned(7 downto 0); + signal ddrb: unsigned(7 downto 0); + + -- Timer to IO ports + signal timerAPulse : std_logic; + signal timerAToggle : std_logic; + signal timerBPulse : std_logic; + signal timerBToggle : std_logic; + + -- Timer A reload registers + signal talo: unsigned(7 downto 0) := (others => '1'); + signal tahi: unsigned(7 downto 0) := (others => '1'); + + -- Timer B reload registers + signal tblo: unsigned(7 downto 0) := (others => '1'); + signal tbhi: unsigned(7 downto 0) := (others => '1'); + + -- Timer A and B internal registers + signal timerA : unsigned(15 downto 0); + signal forceTimerA : std_logic; + signal loadTimerA : std_logic; + signal clkTimerA : std_logic; -- internal timer clock + + signal timerB: unsigned(15 downto 0); + signal forceTimerB : std_logic; + signal loadTimerB : std_logic; + signal clkTimerB : std_logic; -- internal timer clock + + signal WR_Delay_offset : std_logic; -- adjustable WR signal delay - LCA jun17 + + -- Config register A + signal cra_start : std_logic; + signal cra_pbon : std_logic; + signal cra_outmode : std_logic; + signal cra_runmode : std_logic; + signal cra_runmode_reg : std_logic; + signal cra_inmode : std_logic; + signal cra_spmode : std_logic; + signal cra_todin : std_logic; + + -- Config register B + signal crb_start : std_logic; + signal crb_pbon : std_logic; + signal crb_outmode : std_logic; + signal crb_runmode : std_logic; + signal crb_runmode_reg : std_logic; + signal crb_inmode5 : std_logic; + signal crb_inmode6 : std_logic; + signal crb_alarm : std_logic; + + -- TOD 50/60 hz clock + signal todTick : std_logic; + signal oldTodClk : std_logic; + signal tod_clkcnt: unsigned(2 downto 0); + + -- TOD counters + signal tod_running: std_logic; + signal tod_10ths: unsigned(3 downto 0); + signal tod_secs: unsigned(6 downto 0); + signal tod_mins: unsigned(6 downto 0); + signal tod_hrs: unsigned(7 downto 0); + signal tod_pm: std_logic; + + -- TOD latches + signal tod_latched: std_logic; + signal tod_latch_10ths: unsigned(3 downto 0); + signal tod_latch_secs: unsigned(6 downto 0); + signal tod_latch_mins: unsigned(6 downto 0); + signal tod_latch_hrs: unsigned(7 downto 0); + constant tod_latch_pm: std_logic := '0'; + + -- TOD alarms - LCA + signal tod_10ths_alarm: unsigned(3 downto 0); + signal tod_secs_alarm: unsigned(6 downto 0); + signal tod_mins_alarm: unsigned(6 downto 0); + signal tod_hrs_alarm: unsigned(7 downto 0); + signal tod_pm_alarm: std_logic; + + -- Interrupt processing + signal resetIrq : boolean; + signal intr_flagn : std_logic; + signal intr_serial : std_logic; + signal intr_alarm : std_logic; -- LCA + signal intr_timerA : std_logic; + signal intr_timerB : std_logic; + signal mask_timerA : std_logic; + signal mask_timerB : std_logic; + signal mask_alarm : std_logic; -- LCA + signal mask_serial : std_logic; + signal mask_flagn : std_logic; + signal ir: std_logic; + + signal prevFlag_n: std_logic; + + signal myWr : std_logic; + signal myRd : std_logic; +begin +-- ----------------------------------------------------------------------- +-- chip-select signals +-- ----------------------------------------------------------------------- + myWr <= cs and we; + myRd <= cs and rd; + +-- ----------------------------------------------------------------------- +-- I/O ports +-- ----------------------------------------------------------------------- + -- Port A + process(pra, ddra) + begin + ppad <= ddra; + ppao <= pra or (not ddra); + end process; + + -- Port B + process(prb, ddrb, cra_pbon, cra_outmode, crb_pbon, crb_outmode, timerAPulse, timerAToggle, timerBPulse, timerBToggle) + begin + ppbd <= ddrb; + ppbo <= prb or (not ddrb); + if cra_pbon = '1' then + ppbo(6) <= timerAPulse or (not ddrb(6)); + if cra_outmode = '1' then + ppbo(6) <= timerAToggle or (not ddrb(6)); + end if; + end if; + if crb_pbon = '1' then + ppbo(7) <= timerBPulse or (not ddrb(7)); + if crb_outmode = '1' then + ppbo(7) <= timerBToggle or (not ddrb(7)); + end if; + end if; + end process; + + -- I/O port registers + process(clk) + begin + if rising_edge(clk) then + if myWr = '1' then + case addr is + when X"0" => pra <= CIAdi; + when X"1" => prb <= CIAdi; + when X"2" => ddra <= CIAdi; + when X"3" => ddrb <= CIAdi; + when others => null; + end case; + end if; + if reset = '1' then + pra <= (others => '0'); + prb <= (others => '0'); + ddra <= (others => '0'); + ddrb <= (others => '0'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- TOD - time of day +-- ----------------------------------------------------------------------- + process(clk) + begin + -- Process rising edge on the todClk. + -- There is a prescaler of 5 or 6 to get 10ths of seconds from + -- 50 Hz or 60 Hz line frequency. + -- + -- Output is a 'todTick' signal synchronished with enable signal (@ 1Mhz). + if rising_edge(clk) then + if todEnabled = '1' then + if enable = '1' then + todTick <= '0'; + end if; + + if todClk = '1' and oldTodClk = '0' then + -- Divide by 5 or 6 dependng on 50/60 Hz flag. + if tod_clkcnt /= "000" then + tod_clkcnt <= tod_clkcnt - 1; + else + todTick <= tod_running; + tod_clkcnt <= "101"; -- 60 Hz + if cra_todin = '1' then + tod_clkcnt <= "100"; -- 50 Hz + end if; + end if; + end if; + oldTodClk <= todClk; + else + todTick <= '0'; + end if; + end if; + end process; + + process(clk) + variable new_10ths : unsigned(3 downto 0); + variable new_secsL : unsigned(3 downto 0); + variable new_secsH : unsigned(2 downto 0); + variable new_minsL : unsigned(3 downto 0); + variable new_minsH : unsigned(2 downto 0); + variable new_hrsL : unsigned(3 downto 0); + variable new_hrsH : std_logic; + variable new_hrs_byte : unsigned(7 downto 0); -- LCA am/pm and hours + begin + if rising_edge(clk) then + new_10ths := tod_10ths; + new_secsL := tod_secs(3 downto 0); + new_secsH := tod_secs(6 downto 4); + new_minsL := tod_mins(3 downto 0); + new_minsH := tod_mins(6 downto 4); +-- new_hrsL := tod_hrs(3 downto 0); +-- new_hrsH := tod_hrs(4); + new_hrs_byte := tod_hrs (7 downto 0); -- LCA am/pm and hours +-- new_hrs_byte := new_hrsH & new_hrsL; + + if enable = '1' + and todTick = '1' then + if new_10ths /= "1001" then + new_10ths := new_10ths + 1; + else + new_10ths := "0000"; + if new_secsL /= "1001" then + new_secsL := new_secsL + 1; + else + new_secsL := "0000"; + if new_secsH /= "101" then + new_secsH := new_secsH + 1; + else + new_secsH := "000"; + if new_minsL /= "1001" then + new_minsL := new_minsL + 1; + else + new_minsL := "0000"; + if new_minsH /= "101" then + new_minsH := new_minsH + 1; + else + new_minsH := "000"; + -- hrs were missing jun17 LCA + -- I mean completely absent from code :) !!!!!! + -- case to lookup then handles oddities in others + -- retarded am/pm flag flip madness handled at register load below (REG B) + + case tod_hrs is -- case state to set hours and am/pm + when "00010010" => + new_hrs_byte := "00000001"; -- 1 am set + when "00000001" => + new_hrs_byte := "00000010"; + when "00000010" => + new_hrs_byte := "00000011"; + when "00000011" => + new_hrs_byte := "00000100"; + when "00000100" => + new_hrs_byte := "00000101"; + when "00000101" => + new_hrs_byte := "00000110"; + when "00000110" => + new_hrs_byte := "00000111"; + when "00000111" => + new_hrs_byte := "00001000"; + when "00001000" => + new_hrs_byte := "00001001"; + when "00001001" => + new_hrs_byte := "00010000"; + when "00010000" => + new_hrs_byte := "00010001"; -- 11am set + when "00010001" => + new_hrs_byte := "10010010"; -- 12pm set + when "10010010" => + new_hrs_byte := "10000001"; -- 1 pm set + + when "10000001" => + new_hrs_byte := "10000010"; + when "10000010" => + new_hrs_byte := "10000011"; + when "10000011" => + new_hrs_byte := "10000100"; + when "10000100" => + new_hrs_byte := "10000101"; + when "10000101" => + new_hrs_byte := "10000110"; + when "10000110" => + new_hrs_byte := "10000111"; + when "10000111" => + new_hrs_byte := "10001000"; + when "10001000" => + new_hrs_byte := "10001001"; + when "10001001" => + new_hrs_byte := "10010000"; -- 10pm set + when "10010000" => + new_hrs_byte := "10010001"; -- 11pm set + when "10010001" => + new_hrs_byte := "00010010"; -- 12am set (midnight) + when others => + new_hrs_byte (3 downto 0) := new_hrs_byte (3 downto 0) + 1; + --null; + end case; + + end if; + end if; + end if; + end if; + end if; + end if; + + if myWr = '1' then + if crb_alarm = '0' then + case addr is + when X"8" => + new_10ths := CIAdi(3 downto 0); + tod_running <= '1'; + when X"9" => + new_secsL := CIAdi(3 downto 0); + new_secsH := CIAdi(6 downto 4); + when X"A" => + new_minsL := CIAdi(3 downto 0); + new_minsH := CIAdi(6 downto 4); + when X"B" => + new_hrs_byte := CIAdi(7) & "00" & CIAdi(4 downto 0); -- LCA + tod_running <= '0'; + if CIAdi(7 downto 0) = "10010010" or CIAdi(7 downto 0) = "00010010" then -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!) + new_hrs_byte(7) := not new_hrs_byte(7); -- This P.O.S. now mimics real commodore 64 !!!!! LCA + end if; + when others => + null; + end case; + else -- TOD ALARM UPDATE + case addr is + when X"8" => + tod_10ths_alarm <= CIAdi(3 downto 0); + when X"9" => + tod_secs_alarm <= CIAdi(6 downto 0); + when X"A" => + tod_mins_alarm <= CIAdi(6 downto 0); + when X"B" => +-- tod_hrs_alarm <= CIAdi(4 downto 0); +-- tod_pm_alarm <= CIAdi(7); + tod_hrs_alarm <= CIAdi(7) & "00" & CIAdi(4 downto 0); -- LCA + if CIAdi(7 downto 0) = "10010010" or CIAdi(7 downto 0) = "00010010" then -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!) + tod_hrs_alarm(7) <= not tod_hrs_alarm(7); -- This P.O.S. now mimics real commodore 64 !!!!! LCA + end if; + when others => + null; + end case; + end if; + end if; + + -- Update state + tod_10ths <= new_10ths; + tod_secs <= new_secsH & new_secsL; + tod_mins <= new_minsH & new_minsL; + tod_hrs <= new_hrs_byte; -- LCA + + if tod_latched = '0' then + tod_latch_10ths <= new_10ths; + tod_latch_secs <= new_secsH & new_secsL; + tod_latch_mins <= new_minsH & new_minsL; + tod_latch_hrs <= new_hrs_byte; -- LCA + end if; + + -- TOD ALARM test for match - LCA + if (tod_10ths = tod_10ths_alarm) and + (tod_secs = tod_secs_alarm) and + (tod_mins = tod_mins_alarm) and + (tod_hrs = tod_hrs_alarm) and + (crb_alarm = '1') then + intr_alarm <= '1' ; + end if; + + if reset = '1' then + tod_running <= '0'; + tod_10ths_alarm <= "0000" ; + tod_secs_alarm <= "0000000" ; + tod_mins_alarm <= "0000000" ; + tod_hrs_alarm <= "00000000" ; + tod_pm_alarm <= '0' ; + end if; + + if resetIrq then + intr_alarm <= '0' ; + end if; + end if; + end process; + + -- Control TOD output latch + -- Reading the hours latches the output until + -- the 10ths of seconds are read. While latched the + -- clock continues to run in the bankground. + process(clk) + begin + if rising_edge(clk) then + if myRd = '1' then + case addr is + when X"8" => tod_latched <= '0'; + when X"B" => tod_latched <= '1'; + when others => null; + end case; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Timer A and B +-- ----------------------------------------------------------------------- + + +-- adjustable time delay jun17 - LCA + +-- ----------------------------------------------------------------------- +-- ----------------------------------------------------------------------- + + process(clk) + variable WR_delay : unsigned(15 downto 0); + begin + if rising_edge(clk) then + if (myWr = '0' or reset = '1') then + WR_delay := "0000000000000000"; + WR_Delay_offset <= '0'; +-- end if; + elsif (myWr = '1' and (WR_delay < 31)) then + WR_delay := WR_delay + 1; +-- end if; + elsif (WR_delay > 8) then -- adds a (1/32mhz * value) qualifier to WR signal in timers - LCA jun17 + WR_Delay_offset <= '1'; + else + WR_Delay_offset <= '0'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- + + process(clk) + variable newTimerA : unsigned(15 downto 0); + variable nextClkTimerA : std_logic; + variable timerBInput : std_logic; + variable newTimerB : unsigned(15 downto 0); + variable nextClkTimerB : std_logic; + variable new_cra_runmode : std_logic; + variable new_crb_runmode : std_logic; + begin + if rising_edge(clk) then + loadTimerA <= '0'; + loadTimerB <= '0'; + new_cra_runmode := cra_runmode; + new_crb_runmode := crb_runmode; + + if resetIrq then + intr_timerA <= '0'; + intr_timerB <= '0'; + end if; + + if myWr = '1' then +-- if (myWr = '1' and WR_Delay_offset = '1') then -- x/32mhz offset to qualify WR signal LCA jun17 + case addr is + when X"4" => + talo <= CIAdi; + when X"5" => + tahi <= CIAdi; + if cra_start = '0' then + loadTimerA <= '1'; + end if; + when X"6" => + tblo <= CIAdi; + when X"7" => + tbhi <= CIAdi; + if crb_start = '0' then + loadTimerB <= '1'; + end if; + when X"E" => + if cra_start = '0' then + -- Only set on rising edge + timerAToggle <= timerAToggle or CIAdi(0); + end if; + cra_start <= CIAdi(0); + new_cra_runmode := CIAdi(3); + when X"F" => + if crb_start = '0' then + -- Only set on rising edge + timerBToggle <= timerBToggle or CIAdi(0); + end if; + crb_start <= CIAdi(0); + new_crb_runmode := CIAdi(3); + when others => null; + end case; + end if; + + if reset = '1' then + new_cra_runmode := '0'; + new_crb_runmode := '0'; + end if; + + cra_runmode <= new_cra_runmode; + crb_runmode <= new_crb_runmode; + + if enable = '1' then + -- + -- process timer A + -- + timerAPulse <= '0'; + newTimerA := timerA; + + -- CNT is not emulated so don't count when inmode = 1 + nextClkTimerA := cra_start and (not cra_inmode); + if clkTimerA = '1' then + newTimerA := newTimerA - 1; + end if; + if nextClkTimerA = '1' + and newTimerA = 0 then + intr_timerA <= '1'; + loadTimerA <= '1'; + timerAPulse <= '1'; + timerAToggle <= not timerAToggle; + if (new_cra_runmode or cra_runmode) = '1' then + cra_start <= '0'; + end if; + end if; + if forceTimerA = '1' then + loadTimerA <= '1'; + end if; + clkTimerA <= nextClkTimerA; + timerA <= newTimerA; + + -- + -- process timer B + -- + timerBPulse <= '0'; + newTimerB := timerB; + + if crb_inmode6 = '1' then + -- count timerA underflows + timerBInput := timerAPulse; + elsif crb_inmode5 = '0' then + -- count clock pulses + timerBInput := '1'; + else + -- CNT is not emulated so don't count + timerBInput := '0'; + end if; + nextClkTimerB := timerBInput and crb_start; + if clkTimerB = '1' then + newTimerB := newTimerB - 1; + end if; + if nextClkTimerB = '1' + and newTimerB = 0 then + intr_timerB <= '1'; + loadTimerB <= '1'; + timerBPulse <= '1'; + timerBToggle <= not timerBToggle; + if (new_crb_runmode or crb_runmode) = '1' then + crb_start <= '0'; + end if; + end if; + if forceTimerB = '1' then + loadTimerB <= '1'; + end if; + clkTimerB <= nextClkTimerB; + timerB <= newTimerB; + end if; + + if loadTimerA = '1' then + timerA <= tahi & talo; + clkTimerA <= '0'; + end if; + + if loadTimerB = '1' then + timerB <= tbhi & tblo; + clkTimerB <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Interrupts +-- ----------------------------------------------------------------------- + resetIrq <= ((myRd = '1') and (addr = X"D")) or (reset = '1'); + irq_n <= not(ir); + intr_serial <= '0'; + + process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + ir <= ir + or (intr_timerA and mask_timerA) + or (intr_timerB and mask_timerB) + or (intr_alarm and mask_alarm) + or (intr_serial and mask_serial) + or (intr_flagn and mask_flagn); + end if; + + if myWr = '1' then + case addr is + when X"D" => + if CIAdi(7) ='0' then + mask_timerA <= mask_timerA and (not CIAdi(0)); + mask_timerB <= mask_timerB and (not CIAdi(1)); + mask_alarm <= mask_alarm and (not CIAdi(2)); -- LCA + mask_serial <= mask_serial and (not CIAdi(3)); + mask_flagn <= mask_flagn and (not CIAdi(4)); + else + mask_timerA <= mask_timerA or CIAdi(0); + mask_timerB <= mask_timerB or CIAdi(1); + mask_alarm <= mask_alarm or CIAdi(2); -- LCA + mask_serial <= mask_serial or CIAdi(3); + mask_flagn <= mask_flagn or CIAdi(4); + end if; + when others => + null; + end case; + end if; + + if resetIrq then + ir <= '0'; + end if; + + if reset = '1' then + mask_timerA <= '0'; + mask_timerB <= '0'; + mask_alarm <= '0' ; + mask_serial <= '0'; + mask_flagn <= '0'; + end if; + end if; + end process; + + + + +-- ----------------------------------------------------------------------- +-- FLAG_N input +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + prevFlag_n <= flag_n; + if (flag_n = '0') and (prevFlag_n = '1') then + intr_flagn <= '1'; + end if; + if resetIrq then + intr_flagn <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Write registers +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then +-- resetIrq <= '0'; + if enable = '1' then + forceTimerA <= '0'; + forceTimerB <= '0'; +-- cra_runmode_reg <= cra_runmode; +-- crb_runmode_reg <= crb_runmode; + end if; + if myWr = '1' then + case addr is + when X"E" => + cra_pbon <= CIAdi(1); + cra_outmode <= CIAdi(2); +-- cra_runmode <= CIAdi(3); + forceTimerA <= CIAdi(4); + cra_inmode <= CIAdi(5); + cra_spmode <= CIAdi(6); + cra_todin <= CIAdi(7); + when X"F" => + crb_pbon <= CIAdi(1); + crb_outmode <= CIAdi(2); +-- crb_runmode <= CIAdi(3); + forceTimerB <= CIAdi(4); + crb_inmode5 <= CIAdi(5); + crb_inmode6 <= CIAdi(6); + crb_alarm <= CIAdi(7); + when others => null; + end case; + end if; + if reset = '1' then + cra_pbon <= '0'; + cra_outmode <= '0'; +-- cra_runmode <= '0'; + cra_inmode <= '0'; + cra_spmode <= '0'; + cra_todin <= '0'; + crb_pbon <= '0'; + crb_outmode <= '0'; +-- crb_runmode <= '0'; + crb_inmode5 <= '0'; + crb_inmode6 <= '0'; + crb_alarm <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Read registers +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + case addr is + when X"0" => CIAdo <= ppai; + when X"1" => CIAdo <= ppbi; + when X"2" => CIAdo <= DDRA; + when X"3" => CIAdo <= DDRB; + when X"4" => CIAdo <= timera(7 downto 0); + when X"5" => CIAdo <= timera(15 downto 8); + when X"6" => CIAdo <= timerb(7 downto 0); + when X"7" => CIAdo <= timerb(15 downto 8); + when X"8" => CIAdo <= "0000" & tod_latch_10ths; + when X"9" => CIAdo <= "0" & tod_latch_secs; + when X"A" => CIAdo <= "0" & tod_latch_mins; +-- when X"B" => CIAdo <= tod_latch_pm & "00" & tod_latch_hrs; + when X"B" => CIAdo <= tod_latch_hrs; -- LCA + when X"C" => CIAdo <= (others => '0'); + when X"D" => CIAdo <= ir & "00" & intr_flagn & intr_serial & intr_alarm & intr_timerB & intr_timerA; + when X"E" => CIAdo <= cra_todin & cra_spmode & cra_inmode & '0' & cra_runmode & cra_outmode & cra_pbon & cra_start; + when X"F" => CIAdo <= crb_alarm & crb_inmode6 & crb_inmode5 & '0' & crb_runmode & crb_outmode & crb_pbon & crb_start; + when others => CIAdo <= (others => '-'); + end case; + end if; + end process; +end Behavioral; diff --git a/Commodore MAX/rtl/cpu65xx_e.vhd b/Commodore MAX/rtl/cpu65xx_e.vhd new file mode 100644 index 00000000..27166e7a --- /dev/null +++ b/Commodore MAX/rtl/cpu65xx_e.vhd @@ -0,0 +1,49 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Interface to 6502/6510 core +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cpu65xx is + generic ( + pipelineOpcode : boolean; + pipelineAluMux : boolean; + pipelineAluOut : boolean + ); + port ( + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + nmi_n : in std_logic; + nmi_ack : out std_logic; + irq_n : in std_logic; + so_n : in std_logic := '1'; + + di : in unsigned(7 downto 0); + do : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic; + + debugOpcode : out unsigned(7 downto 0); + debugPc : out unsigned(15 downto 0); + debugA : out unsigned(7 downto 0); + debugX : out unsigned(7 downto 0); + debugY : out unsigned(7 downto 0); + debugS : out unsigned(7 downto 0) + ); +end cpu65xx; \ No newline at end of file diff --git a/Commodore MAX/rtl/cpu65xx_fast.vhd b/Commodore MAX/rtl/cpu65xx_fast.vhd new file mode 100644 index 00000000..a387b37d --- /dev/null +++ b/Commodore MAX/rtl/cpu65xx_fast.vhd @@ -0,0 +1,1565 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- Table driven, cycle exact 6502/6510 core +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +-- Store Zp (3) => fetch, cycle2, cycleEnd +-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd +-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2 +-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd +-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd +-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd +-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd +-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump +-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump +-- Jmp abs (-) => fetch, cycle2, .., cycleJump +-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump +-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4 +-- ----------------------------------------------------------------------- + +architecture fast of cpu65xx is +-- Statemachine + type cpuCycles is ( + opcodeFetch, -- New opcode is read and registers updated + cycle2, + cycle3, + cyclePreIndirect, + cycleIndirect, + cycleBranchTaken, + cycleBranchPage, + cyclePreRead, -- Cycle before read while doing zeropage indexed addressing. + cycleRead, -- Read cycle + cycleRead2, -- Second read cycle after page-boundary crossing. + cycleRmw, -- Calculate ALU output for read-modify-write instr. + cyclePreWrite, -- Cycle before write when doing indexed addressing. + cycleWrite, -- Write cycle for zeropage or absolute addressing. + cycleStack1, + cycleStack2, + cycleStack3, + cycleStack4, + cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr. + cycleEnd + ); + signal theCpuCycle : cpuCycles; + signal nextCpuCycle : cpuCycles; + signal updateRegisters : boolean; + signal processIrq : std_logic; + signal nmiReg: std_logic; + signal nmiEdge: std_logic; + signal irqReg : std_logic; -- Delay IRQ input with one clock cycle. + signal soReg : std_logic; -- SO pin edge detection + +-- Opcode decoding + constant opcUpdateA : integer := 0; + constant opcUpdateX : integer := 1; + constant opcUpdateY : integer := 2; + constant opcUpdateS : integer := 3; + constant opcUpdateN : integer := 4; + constant opcUpdateV : integer := 5; + constant opcUpdateD : integer := 6; + constant opcUpdateI : integer := 7; + constant opcUpdateZ : integer := 8; + constant opcUpdateC : integer := 9; + + constant opcSecondByte : integer := 10; + constant opcAbsolute : integer := 11; + constant opcZeroPage : integer := 12; + constant opcIndirect : integer := 13; + constant opcStackAddr : integer := 14; -- Push/Pop address + constant opcStackData : integer := 15; -- Push/Pop status/data + constant opcJump : integer := 16; + constant opcBranch : integer := 17; + constant indexX : integer := 18; + constant indexY : integer := 19; + constant opcStackUp : integer := 20; + constant opcWrite : integer := 21; + constant opcRmw : integer := 22; + constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS) + constant opcRti : integer := 24; + constant opcIRQ : integer := 25; + + constant opcInA : integer := 26; + constant opcInE : integer := 27; + constant opcInX : integer := 28; + constant opcInY : integer := 29; + constant opcInS : integer := 30; + constant opcInT : integer := 31; + constant opcInH : integer := 32; + constant opcInClear : integer := 33; + constant aluMode1From : integer := 34; + -- + constant aluMode1To : integer := 37; + constant aluMode2From : integer := 38; + -- + constant aluMode2To : integer := 40; + -- + constant opcInCmp : integer := 41; + constant opcInCpx : integer := 42; + constant opcInCpy : integer := 43; + + + subtype addrDef is unsigned(0 to 15); + -- + -- is Interrupt -----------------+ + -- instruction is RTI ----------------+| + -- PC++ on last cycle (RTS) ---------------+|| + -- RMW --------------+||| + -- Write -------------+|||| + -- Pop/Stack up -------------+||||| + -- Branch ---------+ |||||| + -- Jump ----------+| |||||| + -- Push or Pop data -------+|| |||||| + -- Push or Pop addr ------+||| |||||| + -- Indirect -----+|||| |||||| + -- ZeroPage ----+||||| |||||| + -- Absolute ---+|||||| |||||| + -- PC++ on cycle2 --+||||||| |||||| + -- |AZI||JBXY|WM||| + constant immediate : addrDef := "1000000000000000"; + constant implied : addrDef := "0000000000000000"; + -- Zero page + constant readZp : addrDef := "1010000000000000"; + constant writeZp : addrDef := "1010000000010000"; + constant rmwZp : addrDef := "1010000000001000"; + -- Zero page indexed + constant readZpX : addrDef := "1010000010000000"; + constant writeZpX : addrDef := "1010000010010000"; + constant rmwZpX : addrDef := "1010000010001000"; + constant readZpY : addrDef := "1010000001000000"; + constant writeZpY : addrDef := "1010000001010000"; + constant rmwZpY : addrDef := "1010000001001000"; + -- Zero page indirect + constant readIndX : addrDef := "1001000010000000"; + constant writeIndX : addrDef := "1001000010010000"; + constant rmwIndX : addrDef := "1001000010001000"; + constant readIndY : addrDef := "1001000001000000"; + constant writeIndY : addrDef := "1001000001010000"; + constant rmwIndY : addrDef := "1001000001001000"; + -- |AZI||JBXY|WM|| + -- Absolute + constant readAbs : addrDef := "1100000000000000"; + constant writeAbs : addrDef := "1100000000010000"; + constant rmwAbs : addrDef := "1100000000001000"; + constant readAbsX : addrDef := "1100000010000000"; + constant writeAbsX : addrDef := "1100000010010000"; + constant rmwAbsX : addrDef := "1100000010001000"; + constant readAbsY : addrDef := "1100000001000000"; + constant writeAbsY : addrDef := "1100000001010000"; + constant rmwAbsY : addrDef := "1100000001001000"; + -- PHA PHP + constant push : addrDef := "0000010000000000"; + -- PLA PLP + constant pop : addrDef := "0000010000100000"; + -- Jumps + constant jsr : addrDef := "1000101000000000"; + constant jumpAbs : addrDef := "1000001000000000"; + constant jumpInd : addrDef := "1100001000000000"; + constant relative : addrDef := "1000000100000000"; + -- Specials + constant rts : addrDef := "0000101000100100"; + constant rti : addrDef := "0000111000100010"; + constant brk : addrDef := "1000111000000001"; +-- constant : unsigned(0 to 0) := "0"; + constant xxxxxxxx : addrDef := "----------0---00"; + + -- A = accu + -- E = Accu | 0xEE (for ANE, LXA) + -- X = index X + -- Y = index Y + -- S = Stack pointer + -- H = indexH + -- + -- AEXYSTHc + constant aluInA : unsigned(0 to 7) := "10000000"; + constant aluInE : unsigned(0 to 7) := "01000000"; + constant aluInEXT : unsigned(0 to 7) := "01100100"; + constant aluInET : unsigned(0 to 7) := "01000100"; + constant aluInX : unsigned(0 to 7) := "00100000"; + constant aluInXH : unsigned(0 to 7) := "00100010"; + constant aluInY : unsigned(0 to 7) := "00010000"; + constant aluInYH : unsigned(0 to 7) := "00010010"; + constant aluInS : unsigned(0 to 7) := "00001000"; + constant aluInT : unsigned(0 to 7) := "00000100"; + constant aluInAX : unsigned(0 to 7) := "10100000"; + constant aluInAXH : unsigned(0 to 7) := "10100010"; + constant aluInAT : unsigned(0 to 7) := "10000100"; + constant aluInXT : unsigned(0 to 7) := "00100100"; + constant aluInST : unsigned(0 to 7) := "00001100"; + constant aluInSet : unsigned(0 to 7) := "00000000"; + constant aluInClr : unsigned(0 to 7) := "00000001"; + constant aluInXXX : unsigned(0 to 7) := "--------"; + + -- Most of the aluModes are just like the opcodes. + -- aluModeInp -> input is output. calculate N and Z + -- aluModeCmp -> Compare for CMP, CPX, CPY + -- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV + -- aluModeInc -> for INC but also INX, INY + -- aluModeDec -> for DEC but also DEX, DEY + + subtype aluMode1 is unsigned(0 to 3); + subtype aluMode2 is unsigned(0 to 2); + subtype aluMode is unsigned(0 to 9); + + -- Logic/Shift ALU + constant aluModeInp : aluMode1 := "0000"; + constant aluModeP : aluMode1 := "0001"; + constant aluModeInc : aluMode1 := "0010"; + constant aluModeDec : aluMode1 := "0011"; + constant aluModeFlg : aluMode1 := "0100"; + constant aluModeBit : aluMode1 := "0101"; + -- 0110 + -- 0111 + constant aluModeLsr : aluMode1 := "1000"; + constant aluModeRor : aluMode1 := "1001"; + constant aluModeAsl : aluMode1 := "1010"; + constant aluModeRol : aluMode1 := "1011"; + -- 1100 + -- 1101 + -- 1110 + constant aluModeAnc : aluMode1 := "1111"; + + -- Arithmetic ALU + constant aluModePss : aluMode2 := "000"; + constant aluModeCmp : aluMode2 := "001"; + constant aluModeAdc : aluMode2 := "010"; + constant aluModeSbc : aluMode2 := "011"; + constant aluModeAnd : aluMode2 := "100"; + constant aluModeOra : aluMode2 := "101"; + constant aluModeEor : aluMode2 := "110"; + constant aluModeArr : aluMode2 := "111"; + + + constant aluInp : aluMode := aluModeInp & aluModePss & "---"; + constant aluP : aluMode := aluModeP & aluModePss & "---"; + constant aluInc : aluMode := aluModeInc & aluModePss & "---"; + constant aluDec : aluMode := aluModeDec & aluModePss & "---"; + constant aluFlg : aluMode := aluModeFlg & aluModePss & "---"; + constant aluBit : aluMode := aluModeBit & aluModeAnd & "---"; + constant aluRor : aluMode := aluModeRor & aluModePss & "---"; + constant aluLsr : aluMode := aluModeLsr & aluModePss & "---"; + constant aluRol : aluMode := aluModeRol & aluModePss & "---"; + constant aluAsl : aluMode := aluModeAsl & aluModePss & "---"; + + constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100"; + constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010"; + constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001"; + constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---"; + constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---"; + constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---"; + constant aluOra : aluMode := aluModeInp & aluModeOra & "---"; + constant aluEor : aluMode := aluModeInp & aluModeEor & "---"; + + constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---"; + constant aluSre : aluMode := aluModeLsr & aluModeEor & "---"; + constant aluRra : aluMode := aluModeRor & aluModeAdc & "---"; + constant aluRla : aluMode := aluModeRol & aluModeAnd & "---"; + constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100"; + constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---"; + constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---"; + constant aluArr : aluMode := aluModeRor & aluModeArr & "---"; + constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110"; + + constant aluXXX : aluMode := (others => '-'); + + + -- Stack operations. Push/Pop/None + constant stackInc : unsigned(0 to 0) := "0"; + constant stackDec : unsigned(0 to 0) := "1"; + constant stackXXX : unsigned(0 to 0) := "-"; + + subtype decodedBitsDef is unsigned(0 to 43); + type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef; + constant opcodeInfoTable : opcodeInfoTableDef := ( + -- +------- Update register A + -- |+------ Update register X + -- ||+----- Update register Y + -- |||+---- Update register S + -- |||| +-- Update Flags + -- |||| | + -- |||| _|__ + -- |||| / \ + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK + "1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp + "1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp + "0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp + "1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp + "0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP + "1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm + "1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm + "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs + "1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs + "0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs + "1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL + "1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x + "0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x + "0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC + "1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR + "1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x) + "0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp + "1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp + "0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp + "1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp + "0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP + "1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm + "1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm + "0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs + "1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs + "0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs + "1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI + "1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x + "0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC + "1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI + "1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp + "1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp + "0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp + "1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp + "0000" & "000000" & push & aluInA & aluInp, -- 48 PHA + "1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm + "1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu + "1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm + "0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs + "1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs + "0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs + "1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC + "1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x + "0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x + "0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI + "1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS + "1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM *** + "1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp + "1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp + "0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp + "1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp + "1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA + "1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm + "1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu + "1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm + "0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect + "1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs + "0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs + "1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS + "1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x + "1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x + "0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI + "1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm + "0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm + "0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x) + "0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp + "0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp + "0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp + "0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp + "0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm + "1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA + "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm + "0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs + "0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs + "0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs + "0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC + "0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM *** + "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y + "0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x + "0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x + "0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y + "0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y + "1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA + "0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y + "0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS + "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y + "0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x + "0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x + "0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y + "0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm + "1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x) + "0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm + "1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x) + "0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp + "1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp + "0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp + "1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp + "0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY + "1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm + "0100" & "100010" & implied & aluInA & aluInp, -- AA TAX + "1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm + "0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs + "1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs + "0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs + "1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS + "1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM *** + "1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y + "0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x + "1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x + "0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y + "1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y + "0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV + "1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y + "0100" & "100010" & implied & aluInS & aluInp, -- BA TSX + "1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y + "0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x + "1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x + "0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y + "1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm + "0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm + "0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp + "0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp + "0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp + "0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp + "0010" & "100010" & implied & aluInY & aluInc, -- C8 INY + "0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm + "0100" & "100010" & implied & aluInX & aluDec, -- CA DEX + "0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm + "0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs + "0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs + "0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs + "0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE + "0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM *** + "0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x + "0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x + "0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x + "0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD + "0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied + "0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x + "0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm + "1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm + "1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp + "1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp + "0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp + "1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp + "0100" & "100010" & implied & aluInX & aluInc, -- E8 INX + "1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm + "0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP + "1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc) + "0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs + "1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs + "0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs + "1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ + "1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x + "0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x + "1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x + "0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED + "1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x + ); + signal opcInfo : decodedBitsDef; + signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded) + signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined + signal theOpcode : unsigned(7 downto 0); + signal nextOpcode : unsigned(7 downto 0); + +-- Program counter + signal PC : unsigned(15 downto 0); -- Program counter + +-- Address generation + type nextAddrDef is ( + nextAddrHold, + nextAddrIncr, + nextAddrIncrL, -- Increment low bits only (zeropage accesses) + nextAddrIncrH, -- Increment high bits only (page-boundary) + nextAddrDecrH, -- Decrement high bits (branch backwards) + nextAddrPc, + nextAddrIrq, + nextAddrReset, + nextAddrAbs, + nextAddrAbsIndexed, + nextAddrZeroPage, + nextAddrZPIndexed, + nextAddrStack, + nextAddrRelative + ); + signal nextAddr : nextAddrDef; + signal myAddr : unsigned(15 downto 0); + signal myAddrIncr : unsigned(15 downto 0); + signal myAddrIncrH : unsigned(7 downto 0); + signal myAddrDecrH : unsigned(7 downto 0); + signal theWe : std_logic; + + signal irqActive : std_logic; + +-- Output register + signal doReg : unsigned(7 downto 0); + +-- Buffer register + signal T : unsigned(7 downto 0); + +-- General registers + signal A: unsigned(7 downto 0); -- Accumulator + signal X: unsigned(7 downto 0); -- Index X + signal Y: unsigned(7 downto 0); -- Index Y + signal S: unsigned(7 downto 0); -- stack pointer + +-- Status register + signal C: std_logic; -- Carry + signal Z: std_logic; -- Zero flag + signal I: std_logic; -- Interrupt flag + signal D: std_logic; -- Decimal mode + signal V: std_logic; -- Overflow + signal N: std_logic; -- Negative + +-- ALU + -- ALU input + signal aluInput : unsigned(7 downto 0); + signal aluCmpInput : unsigned(7 downto 0); + -- ALU output + signal aluRegisterOut : unsigned(7 downto 0); + signal aluRmwOut : unsigned(7 downto 0); + signal aluC : std_logic; + signal aluZ : std_logic; + signal aluV : std_logic; + signal aluN : std_logic; + -- Pipeline registers + signal aluInputReg : unsigned(7 downto 0); + signal aluCmpInputReg : unsigned(7 downto 0); + signal aluRmwReg : unsigned(7 downto 0); + signal aluNineReg : unsigned(7 downto 0); + signal aluCReg : std_logic; + signal aluZReg : std_logic; + signal aluVReg : std_logic; + signal aluNReg : std_logic; + +-- Indexing + signal indexOut : unsigned(8 downto 0); + +begin +processAluInput: process(clk, opcInfo, A, X, Y, T, S) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInA) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInE) = '1' then + temp := temp and (A or X"EE"); + end if; + if opcInfo(opcInX) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInY) = '1' then + temp := temp and Y; + end if; + if opcInfo(opcInS) = '1' then + temp := temp and S; + end if; + if opcInfo(opcInT) = '1' then + temp := temp and T; + end if; + if opcInfo(opcInClear) = '1' then + temp := (others => '0'); + end if; + if rising_edge(clk) then + aluInputReg <= temp; + end if; + + aluInput <= temp; + if pipelineAluMux then + aluInput <= aluInputReg; + end if; + end process; + +processCmpInput: process(clk, opcInfo, A, X, Y) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInCmp) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInCpx) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInCpy) = '1' then + temp := temp and Y; + end if; + if rising_edge(clk) then + aluCmpInputReg <= temp; + end if; + + aluCmpInput <= temp; + if pipelineAluMux then + aluCmpInput <= aluCmpInputReg; + end if; + end process; + + -- ALU consists of two parts + -- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL + -- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA + -- Some instructions are both RMW and accumulator so for most + -- instructions the rmw results are routed through accu alu too. +processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C) + variable lowBits: unsigned(5 downto 0); + variable nineBits: unsigned(8 downto 0); + variable rmwBits: unsigned(8 downto 0); + + variable varC : std_logic; + variable varZ : std_logic; + variable varV : std_logic; + variable varN : std_logic; + begin + lowBits := (others => '-'); + nineBits := (others => '-'); + rmwBits := (others => '-'); + varV := aluInput(6); -- Default for BIT / PLP / RTI + + -- Shift unit + case opcInfo(aluMode1From to aluMode1To) is + when aluModeInp => + rmwBits := C & aluInput; + when aluModeP => + rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C; + when aluModeInc => + rmwBits := C & (aluInput + 1); + when aluModeDec => + rmwBits := C & (aluInput - 1); + when aluModeAsl => + rmwBits := aluInput & "0"; + when aluModeFlg => + rmwBits := aluInput(0) & aluInput; + when aluModeLsr => + rmwBits := aluInput(0) & "0" & aluInput(7 downto 1); + when aluModeRol => + rmwBits := aluInput & C; + when aluModeRoR => + rmwBits := aluInput(0) & C & aluInput(7 downto 1); + when aluModeAnc => + rmwBits := (aluInput(7) and A(7)) & aluInput; + when others => + rmwBits := C & aluInput; + end case; + + -- ALU + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1"); + ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8)); + when aluModeSbc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1"); + ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8)); + when aluModeCmp => + ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001"; + when aluModeAnd => + ninebits := rmwBits(8) & (A and rmwBits(7 downto 0)); + when aluModeEor => + ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0)); + when aluModeOra => + ninebits := rmwBits(8) & (A or rmwBits(7 downto 0)); + when others => + ninebits := rmwBits; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varZ := rmwBits(1); + elsif ninebits(7 downto 0) = X"00" then + varZ := '1'; + else + varZ := '0'; + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode low bits correction, is done after setting Z flag. + if D = '1' then + if lowBits(5 downto 1) > 9 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + if lowBits(5) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) + 1; + end if; + end if; + end if; + when others => + null; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) + or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varN := rmwBits(7); + else + varN := nineBits(7); + end if; + varC := ninebits(8); + if opcInfo(aluMode2From to aluMode2To) = aluModeArr then + varC := aluInput(7); + varV := aluInput(7) xor aluInput(6); + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode high bits correction, is done after setting Z and N flags + varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7)); + if D = '1' then + if ninebits(8 downto 4) > 9 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + end if; + end if; + when aluModeSbc => + varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7)); + if D = '1' then + -- Check for borrow (lower 4 bits) + if lowBits(5) = '0' then + ninebits(3 downto 0) := ninebits(3 downto 0) - 6; + end if; + -- Check for borrow (upper 4 bits) + if ninebits(8) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) - 6; + end if; + end if; + when aluModeArr => + if D = '1' then + if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + end if; + if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + else + varC := '0'; + end if; + end if; + when others => + null; + end case; + + if rising_edge(clk) then + aluRmwReg <= rmwBits(7 downto 0); + aluNineReg <= ninebits(7 downto 0); + aluCReg <= varC; + aluZReg <= varZ; + aluVReg <= varV; + aluNReg <= varN; + end if; + + aluRmwOut <= rmwBits(7 downto 0); + aluRegisterOut <= ninebits(7 downto 0); + aluC <= varC; + aluZ <= varZ; + aluV <= varV; + aluN <= varN; + if pipelineAluOut then + aluRmwOut <= aluRmwReg; + aluRegisterOut <= aluNineReg; + aluC <= aluCReg; + aluZ <= aluZReg; + aluV <= aluVReg; + aluN <= aluNReg; + end if; + end process; + +calcInterrupt: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = cycleStack4 + or reset = '1' then + nmiReg <= '1'; + end if; + + if nextCpuCycle /= cycleBranchTaken + and nextCpuCycle /= opcodeFetch then + irqReg <= irq_n; + nmiEdge <= nmi_n; + if (nmiEdge = '1') and (nmi_n = '0') then + nmiReg <= '0'; + end if; + end if; + -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ. + -- Presumably this is done in the real 6502/6510 to prevent a double IRQ. + processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ)); + end if; + end if; + end process; + +calcNextOpcode: process(clk, di, reset, processIrq) + variable myNextOpcode : unsigned(7 downto 0); + begin + -- Next opcode is read from input unless a reset or IRQ is pending. + myNextOpcode := di; + if reset = '1' then + myNextOpcode := X"4C"; + elsif processIrq = '1' then + myNextOpcode := X"00"; + end if; + + nextOpcode <= myNextOpcode; + end process; + + nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode)); + process(clk) + begin + if rising_edge(clk) then + nextOpcInfoReg <= nextOpcInfo; + end if; + end process; + + -- Read bits and flags from opcodeInfoTable and store in opcInfo. + -- This info is used to control the execution of the opcode. +calcOpcInfo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if (reset = '1') or (theCpuCycle = opcodeFetch) then + opcInfo <= nextOpcInfo; + if pipelineOpcode then + opcInfo <= nextOpcInfoReg; + end if; + end if; + end if; + end if; + end process; + +calcTheOpcode: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = opcodeFetch then + irqActive <= '0'; + if processIrq = '1' then + irqActive <= '1'; + end if; + -- Fetch opcode + theOpcode <= nextOpcode; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- State machine +-- ----------------------------------------------------------------------- + process(enable, theCpuCycle, opcInfo) + begin + updateRegisters <= false; + if enable = '1' then + if opcInfo(opcRti) = '1' then + if theCpuCycle = cycleRead then + updateRegisters <= true; + end if; + elsif theCpuCycle = opcodeFetch then + updateRegisters <= true; + end if; + end if; + end process; + + debugOpcode <= theOpcode; + process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theCpuCycle <= nextCpuCycle; + end if; + if reset = '1' then + theCpuCycle <= cycle2; + end if; + end if; + end process; + + -- Determine the next cpu cycle. After the last cycle we always + -- go to opcodeFetch to get the next opcode. +calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z) + begin + nextCpuCycle <= opcodeFetch; + + case theCpuCycle is + when opcodeFetch => + nextCpuCycle <= cycle2; + when cycle2 => + if opcInfo(opcBranch) = '1' then + if (N = theOpcode(5) and theOpcode(7 downto 6) = "00") + or (V = theOpcode(5) and theOpcode(7 downto 6) = "01") + or (C = theOpcode(5) and theOpcode(7 downto 6) = "10") + or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then + -- Branch condition is true + nextCpuCycle <= cycleBranchTaken; + end if; + elsif (opcInfo(opcStackUp) = '1') then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackAddr) = '1' + and opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleStack2; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleWrite; + elsif opcInfo(opcAbsolute) = '1' then + nextCpuCycle <= cycle3; + elsif opcInfo(opcIndirect) = '1' then + if opcInfo(indexX) = '1' then + nextCpuCycle <= cyclePreIndirect; + else + nextCpuCycle <= cycleIndirect; + end if; + elsif opcInfo(opcZeroPage) = '1' then + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + else + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreRead; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + elsif opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycle3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + end if; + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + if opcInfo(opcWrite) = '1' then + nextCpuCycle <= cycleWrite; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + when cyclePreIndirect => + nextCpuCycle <= cycleIndirect; + when cycleIndirect => + nextCpuCycle <= cycle3; + when cycleBranchTaken => + if indexOut(8) /= T(7) then + -- Page boundary crossing during branch. + nextCpuCycle <= cycleBranchPage; + end if; + when cyclePreRead => + if opcInfo(opcZeroPage) = '1' then + nextCpuCycle <= cycleRead2; + end if; + when cycleRead => + if opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + elsif indexOut(8) = '1' then + -- Page boundary crossing while indexed addressing. + nextCpuCycle <= cycleRead2; + elsif opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + if opcInfo(indexX) = '1' + or opcInfo(indexY) = '1' then + -- 6510 needs extra cycle for indexed addressing + -- combined with RMW indexing + nextCpuCycle <= cycleRead2; + end if; + end if; + when cycleRead2 => + if opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + end if; + when cycleRmw => + nextCpuCycle <= cycleWrite; + when cyclePreWrite => + nextCpuCycle <= cycleWrite; + when cycleStack1 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack2; + end if; + when cycleStack2 => + nextCpuCycle <= cycleStack3; + if opcInfo(opcRti) = '1' then + nextCpuCycle <= cycleRead; + end if; + if opcInfo(opcStackData) = '0' + and opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycleStack3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackData) = '0' + or opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack4; + end if; + when cycleStack4 => + nextCpuCycle <= cycleRead; + when cycleJump => + if opcInfo(opcIncrAfter) = '1' then + -- Insert extra cycle + nextCpuCycle <= cycleEnd; + end if; + when others => + null; + end case; + end process; + +-- ----------------------------------------------------------------------- +-- T register +-- ----------------------------------------------------------------------- +calcT: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when cycle2 => + T <= di; + when cycleStack1 | cycleStack2 => + if opcInfo(opcStackUp) = '1' then + -- Read from stack + T <= di; + end if; + when cycleIndirect | cycleRead | cycleRead2 => + T <= di; + when others => + null; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- A register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateA) = '1' then + A <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- X register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateX) = '1' then + X <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Y register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateY) = '1' then + Y <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- C flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateC) = '1' then + C <= aluC; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Z flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateZ) = '1' then + Z <= aluZ; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- I flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateI) = '1' then + I <= aluInput(2); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- D flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateD) = '1' then + D <= aluInput(3); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- V flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateV) = '1' then + V <= aluV; + end if; + end if; + if enable = '1' then + if soReg = '1' and so_n = '0' then + V <= '1'; + end if; + soReg <= so_n; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- N flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateN) = '1' then + N <= aluN; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Stack pointer +-- ----------------------------------------------------------------------- + process(clk) + variable sIncDec : unsigned(7 downto 0); + variable updateFlag : boolean; + begin + if rising_edge(clk) then + + if opcInfo(opcStackUp) = '1' then + sIncDec := S + 1; + else + sIncDec := S - 1; + end if; + + if enable = '1' then + updateFlag := false; + case nextCpuCycle is + when cycleStack1 => + if (opcInfo(opcStackUp) = '1') + or (opcInfo(opcStackData) = '1') then + updateFlag := true; + end if; + when cycleStack2 => + updateFlag := true; + when cycleStack3 => + updateFlag := true; + when cycleStack4 => + updateFlag := true; + when cycleRead => + if opcInfo(opcRti) = '1' then + updateFlag := true; + end if; + when cycleWrite => + if opcInfo(opcStackData) = '1' then + updateFlag := true; + end if; + when others => + null; + end case; + if updateFlag then + S <= sIncDec; + end if; + end if; + if updateRegisters then + if opcInfo(opcUpdateS) = '1' then + S <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Data out +-- ----------------------------------------------------------------------- +--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T) +calcDo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + doReg <= aluRmwOut; + if opcInfo(opcInH) = '1' then + -- For illegal opcodes SHA, SHX, SHY, SHS + doReg <= aluRmwOut and myAddrIncrH; + end if; + + case nextCpuCycle is + when cycleStack2 => + if opcInfo(opcIRQ) = '1' + and irqActive = '0' then + doReg <= myAddrIncr(15 downto 8); + else + doReg <= PC(15 downto 8); + end if; + when cycleStack3 => + doReg <= PC(7 downto 0); + when cycleRmw => +-- do <= T; -- Read-modify-write write old value first. + doReg <= di; -- Read-modify-write write old value first. + when others => null; + end case; + end if; + end if; + end process; + do <= doReg; + + + +-- ----------------------------------------------------------------------- +-- Write enable +-- ----------------------------------------------------------------------- +calcWe: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theWe <= '0'; + case nextCpuCycle is + when cycleStack1 => + if opcInfo(opcStackUp) = '0' + and ((opcInfo(opcStackAddr) = '0') + or (opcInfo(opcStackData) = '1')) then + theWe <= '1'; + end if; + when cycleStack2 | cycleStack3 | cycleStack4 => + if opcInfo(opcStackUp) = '0' then + theWe <= '1'; + end if; + when cycleRmw => + theWe <= '1'; + when cycleWrite => + theWe <= '1'; + when others => + null; + end case; + end if; + end if; + end process; + we <= theWe; + +-- ----------------------------------------------------------------------- +-- Program counter +-- ----------------------------------------------------------------------- +calcPC: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when opcodeFetch => + PC <= myAddr; + when cycle2 => + if irqActive = '0' then + if opcInfo(opcSecondByte) = '1' then + PC <= myAddrIncr; + else + PC <= myAddr; + end if; + end if; + when cycle3 => + if opcInfo(opcAbsolute) = '1' then + PC <= myAddrIncr; + end if; + when others => + null; + end case; + end if; + end if; + end process; + debugPc <= PC; + +-- ----------------------------------------------------------------------- +-- Address generation +-- ----------------------------------------------------------------------- +calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset) + begin + nextAddr <= nextAddrIncr; + case theCpuCycle is + when cycle2 => + if opcInfo(opcStackAddr) = '1' + or opcInfo(opcStackData) = '1' then + nextAddr <= nextAddrStack; + elsif opcInfo(opcAbsolute) = '1' then + nextAddr <= nextAddrIncr; + elsif opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcIndirect) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcSecondByte) = '1' then + nextAddr <= nextAddrIncr; + else + nextAddr <= nextAddrHold; + end if; + when cycle3 => + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + nextAddr <= nextAddrAbs; + else + nextAddr <= nextAddrAbsIndexed; + end if; + when cyclePreIndirect => + nextAddr <= nextAddrZPIndexed; + when cycleIndirect => + nextAddr <= nextAddrIncrL; + when cycleBranchTaken => + nextAddr <= nextAddrRelative; + when cycleBranchPage => + if T(7) = '0' then + nextAddr <= nextAddrIncrH; + else + nextAddr <= nextAddrDecrH; + end if; + when cyclePreRead => + nextAddr <= nextAddrZPIndexed; + when cycleRead => + nextAddr <= nextAddrPc; + if opcInfo(opcJump) = '1' then + -- Emulate 6510 bug, jmp(xxFF) fetches from same page. + -- Replace with nextAddrIncr if emulating 65C02 or later cpu. + nextAddr <= nextAddrIncrL; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + elsif opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRead2 => + nextAddr <= nextAddrPc; + if opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRmw => + nextAddr <= nextAddrHold; + when cyclePreWrite => + nextAddr <= nextAddrHold; + if opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZPIndexed; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + end if; + when cycleWrite => + nextAddr <= nextAddrPc; + when cycleStack1 => + nextAddr <= nextAddrStack; + when cycleStack2 => + nextAddr <= nextAddrStack; + when cycleStack3 => + nextAddr <= nextAddrStack; + if opcInfo(opcStackData) = '0' then + nextAddr <= nextAddrPc; + end if; + when cycleStack4 => + nextAddr <= nextAddrIrq; + when cycleJump => + nextAddr <= nextAddrAbs; + when others => + null; + end case; + if reset = '1' then + nextAddr <= nextAddrReset; + end if; + end process; + +indexAlu: process(opcInfo, myAddr, T, X, Y) + begin + if opcInfo(indexX) = '1' then + indexOut <= (B"0" & T) + (B"0" & X); + elsif opcInfo(indexY) = '1' then + indexOut <= (B"0" & T) + (B"0" & Y); + elsif opcInfo(opcBranch) = '1' then + indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0)); + else + indexOut <= B"0" & T; + end if; + end process; + +calcAddr: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case nextAddr is + when nextAddrIncr => myAddr <= myAddrIncr; + when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0); + when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH; + when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH; + when nextAddrPc => myAddr <= PC; + when nextAddrIrq => + myAddr <= X"FFFE"; + if nmiReg = '0' then + myAddr <= X"FFFA"; + end if; + when nextAddrReset => myAddr <= X"FFFC"; + when nextAddrAbs => myAddr <= di & T; + when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0); + when nextAddrZeroPage => myAddr <= "00000000" & di; + when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0); + when nextAddrStack => myAddr <= "00000001" & S; + when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0); + when others => null; + end case; + end if; + end if; + end process; + + myAddrIncr <= myAddr + 1; + myAddrIncrH <= myAddr(15 downto 8) + 1; + myAddrDecrH <= myAddr(15 downto 8) - 1; + + addr <= myAddr; + + debugA <= A; + debugX <= X; + debugY <= Y; + debugS <= S; + +end architecture; + + diff --git a/Commodore MAX/rtl/cpu_6510.vhd b/Commodore MAX/rtl/cpu_6510.vhd new file mode 100644 index 00000000..8ae35705 --- /dev/null +++ b/Commodore MAX/rtl/cpu_6510.vhd @@ -0,0 +1,150 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- 6510 wrapper for 65xx core +-- Adds 8 bit I/O port mapped at addresses $0000 to $0001 +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity cpu_6510 is + generic ( + pipelineOpcode : boolean:= false; + pipelineAluMux : boolean:= false; + pipelineAluOut : boolean:= false + ); + port ( + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + nmi_n : in std_logic; + nmi_ack : out std_logic; + irq_n : in std_logic; + + CPUdi : in unsigned(7 downto 0); + CPUdo : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic; + + diIO : in unsigned(7 downto 0); + doIO : out unsigned(7 downto 0); + + debugOpcode : out unsigned(7 downto 0); + debugPc : out unsigned(15 downto 0); + debugA : out unsigned(7 downto 0); + debugX : out unsigned(7 downto 0); + debugY : out unsigned(7 downto 0); + debugS : out unsigned(7 downto 0) + ); +end cpu_6510; + +-- ----------------------------------------------------------------------- + +architecture rtl of cpu_6510 is + signal localA : unsigned(15 downto 0); + signal localDi : unsigned(7 downto 0); + signal localDo : unsigned(7 downto 0); + signal localWe : std_logic; + + signal currentIO : unsigned(7 downto 0); + signal ioDir : unsigned(7 downto 0); + signal ioData : unsigned(7 downto 0); + + signal accessIO : std_logic; +begin + cpuInstance: entity work.cpu65xx(fast) + generic map ( + pipelineOpcode => pipelineOpcode, + pipelineAluMux => pipelineAluMux, + pipelineAluOut => pipelineAluOut + ) + port map ( + clk => clk, + enable => enable, + reset => reset, + nmi_n => nmi_n, + nmi_ack => nmi_ack, + irq_n => irq_n, + + di => localDi, + do => localDo, + addr => localA, + we => localWe, + + debugOpcode => debugOpcode, + debugPc => debugPc, + debugA => debugA, + debugX => debugX, + debugY => debugY, + debugS => debugS + ); + + process(localA) + begin + accessIO <= '0'; + if localA(15 downto 1) = 0 then + accessIO <= '1'; + end if; + end process; + + process(CPUdi, localA, ioDir, currentIO, accessIO) + begin + localDi <= CPUdi; + if accessIO = '1' then + if localA(0) = '0' then + localDi <= ioDir; + else + localDi <= currentIO; + end if; + end if; + end process; + + process(clk) + begin + if rising_edge(clk) then + if accessIO = '1' then + if localWe = '1' + and enable = '1' then + if localA(0) = '0' then + ioDir <= localDo; + else + ioData <= localDo; + end if; + end if; + end if; + if reset = '1' then + ioDir <= (others => '0'); + end if; + end if; + end process; + + process(ioDir, ioData, diIO) + begin + for i in 0 to 7 loop + if ioDir(i) = '0' then + currentIO(i) <= diIO(i); + else + currentIO(i) <= ioData(i); + end if; + end loop; + end process; + + -- Cunnect zee wires + addr <= localA; + CPUdo <= localDo; + we <= localWe; + doIO <= currentIO; +end architecture; diff --git a/Commodore MAX/rtl/data_io.v b/Commodore MAX/rtl/data_io.v new file mode 100644 index 00000000..4629033b --- /dev/null +++ b/Commodore MAX/rtl/data_io.v @@ -0,0 +1,126 @@ +// +// data_io.v +// +// io controller writable ram for the MiST board +// http://code.google.com/p/mist-board/ +// +// ZX Spectrum adapted version +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module data_io ( + // io controller spi interface + input sck, + input ss, + input sdi, + + output downloading, // signal indicating an active download + output reg [4:0] index, // menu index used to upload the file + + // external ram interface + input clk, + output reg wr, + output reg [24:0] addr, + output reg [7:0] data +); + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// filter spi clock. the 8 bit gate delay is ~2.5ns in total +wire [7:0] spi_sck_D = { spi_sck_D[6:0], sck } /* synthesis keep */; +wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff); + +// this core supports only the display related OSD commands +// of the minimig +reg [6:0] sbuf; +reg [7:0] cmd; +reg [4:0] cnt; +reg rclk; + +reg [24:0] laddr; +reg [7:0] ldata; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +assign downloading = downloading_reg; +reg downloading_reg = 1'b0; + +// data_io has its own SPI interface to the io controller +always@(posedge spi_sck, posedge ss) begin + if(ss == 1'b1) + cnt <= 5'd0; + else begin + rclk <= 1'b0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) + sbuf <= { sbuf[5:0], sdi}; + + // increase target address after write + if(rclk) + laddr <= laddr + 1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 4'd1; + else cnt <= 4'd8; + + // finished command byte + if(cnt == 7) + cmd <= {sbuf, sdi}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(sdi) begin + laddr <= 25'd0; + downloading_reg <= 1'b1; + end else + downloading_reg <= 1'b0; + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + ldata <= {sbuf, sdi}; + rclk <= 1'b1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) + index <= {sbuf[3:0], sdi}; + end +end + +reg rclkD, rclkD2; +always@(posedge clk) begin + // bring all signals from spi clock domain into local clock domain + rclkD <= rclk; + rclkD2 <= rclkD; + wr <= 1'b0; + + if(rclkD && !rclkD2) begin + addr <= laddr; + data <= ldata; + wr <= 1'b1; + end +end + +endmodule diff --git a/Commodore MAX/rtl/fpga64_rgbcolor.vhd b/Commodore MAX/rtl/fpga64_rgbcolor.vhd new file mode 100644 index 00000000..1fc4eb9a --- /dev/null +++ b/Commodore MAX/rtl/fpga64_rgbcolor.vhd @@ -0,0 +1,56 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- C64 palette index to 24 bit RGB color +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +-- ----------------------------------------------------------------------- + +entity fpga64_rgbcolor is + port ( + index: in unsigned(3 downto 0); + r: out unsigned(7 downto 0); + g: out unsigned(7 downto 0); + b: out unsigned(7 downto 0) + ); +end fpga64_rgbcolor; + +-- ----------------------------------------------------------------------- + +architecture Behavioral of fpga64_rgbcolor is +begin + process(index) + begin + case index is + when X"0" => r <= X"00"; g <= X"00"; b <= X"00"; + when X"1" => r <= X"FF"; g <= X"FF"; b <= X"FF"; + when X"2" => r <= X"68"; g <= X"37"; b <= X"2B"; + when X"3" => r <= X"70"; g <= X"A4"; b <= X"B2"; + when X"4" => r <= X"6F"; g <= X"3D"; b <= X"86"; + when X"5" => r <= X"58"; g <= X"8D"; b <= X"43"; + when X"6" => r <= X"35"; g <= X"28"; b <= X"79"; + when X"7" => r <= X"B8"; g <= X"C7"; b <= X"6F"; + when X"8" => r <= X"6F"; g <= X"4F"; b <= X"25"; + when X"9" => r <= X"43"; g <= X"39"; b <= X"00"; + when X"A" => r <= X"9A"; g <= X"67"; b <= X"59"; + when X"B" => r <= X"44"; g <= X"44"; b <= X"44"; + when X"C" => r <= X"6C"; g <= X"6C"; b <= X"6C"; + when X"D" => r <= X"9A"; g <= X"D2"; b <= X"84"; + when X"E" => r <= X"6C"; g <= X"5E"; b <= X"B5"; + when X"F" => r <= X"95"; g <= X"95"; b <= X"95"; + end case; + end process; +end Behavioral; diff --git a/Commodore MAX/rtl/hq2x.sv b/Commodore MAX/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Commodore MAX/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Commodore MAX/rtl/mist_io.v b/Commodore MAX/rtl/mist_io.v new file mode 100644 index 00000000..ab9ef8ad --- /dev/null +++ b/Commodore MAX/rtl/mist_io.v @@ -0,0 +1,532 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // ARM -> FPGA download + input ioctl_force_erase, + output reg ioctl_download = 0, // signal indicating an active download + output reg ioctl_erasing = 0, // signal indicating an active erase + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr = 0, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + case(ioctl_index) + 0: addr <= 'h080000; // BOOT ROM + 'h01: addr <= 'h000100; // ROM file + 'h41: addr <= 'h000100; // COM file + 'h81: addr <= 'h000000; // C00 file + 'hC1: addr <= 'h010000; // EDD file + default: addr <= 'h100000; // FDD file + endcase + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +reg [24:0] erase_mask; +wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask; + +always@(posedge clk_sys) begin + reg rclkD, rclkD2; + reg old_force = 0; + reg [5:0] erase_clk_div; + reg [24:0] end_addr; + reg erase_trigger = 0; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wr <= 0; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wr <= 1; + end + + if(ioctl_download) begin + old_force <= 0; + ioctl_erasing <= 0; + erase_trigger <= (ioctl_index == 1); + end else begin + + old_force <= ioctl_force_erase; + + // start erasing + if(erase_trigger) begin + erase_trigger <= 0; + erase_mask <= 'hFFFF; + end_addr <= 'h0100; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if((ioctl_force_erase & ~old_force)) begin + erase_trigger <= 0; + ioctl_addr <= 'h1FFFFFF; + erase_mask <= 'h1FFFFFF; + end_addr <= 'h0050000; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if(ioctl_erasing) begin + erase_clk_div <= erase_clk_div + 1'd1; + if(!erase_clk_div) begin + if(next_erase == end_addr) ioctl_erasing <= 0; + else begin + ioctl_addr <= next_erase; + ioctl_dout <= 0; + ioctl_wr <= 1; + end + end + end + end +end + +endmodule \ No newline at end of file diff --git a/Commodore MAX/rtl/osd.v b/Commodore MAX/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Commodore MAX/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Commodore MAX/rtl/pla_6703.v b/Commodore MAX/rtl/pla_6703.v new file mode 100644 index 00000000..42c6bba3 --- /dev/null +++ b/Commodore MAX/rtl/pla_6703.v @@ -0,0 +1,57 @@ +module pla_6703( + +input [15:10]A, +input CLK,//CLK +input BA,//BA +input RW_IN,// RW + +output reg RAM,//RAM invert +output reg EXRAM,//EXRAM invert +output reg VIC,//VIC invert +output reg SID,//SID invert +output reg CIA,//CIA_PLA invert +output reg COLRAM,//COLRAM invert +output reg ROML,//ROML invert +output reg ROMH,//ROMH invert +output reg BUF,//to the 4066 COLOR Ram DATA +output reg RW_OUT//RW_PLA invert + +); + + + +always @ (posedge CLK) +begin +RAM = ~(~A[11] & ~A[12] & ~A[13] & ~A[14] & ~A[15] & CLK & BA); +EXRAM = ~(A[11] & ~A[12] & ~A[13] & ~A[14] & ~A[15] & CLK & BA); +ROML = ~(~A[13] & ~A[14] & A[15] & CLK & BA); +ROMH = ~(A[13] & A[14] & A[15] & CLK & BA); +SID = ~(A[10] & ~A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA); +VIC = ~(~A[10] & ~A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA); +COLRAM = ~(~A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA); +BUF = (~A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA); +CIA = ~(A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA); +RW_OUT = ~(CLK & ~RW_IN); +end + + + +//GAL Code +/*!RAM = !A11 & !A12 & !A13 & !A14 & !A15 & CLK & BA +!EXRAM = A11 & !A12 & !A13 & !A14 & !A15 & CLK & BA +# A11 & !A12 & !A13 & !CLK +# A11 & !A12 & !A13 & !BA; +!ROML = !A13 & !A14 & A15 & CLK & BA; +!ROMH = A13 & A14 & A15 & CLK & BA +# A12 & A13 & !CLK +# A12 & A13 & !BA; +!SID = A10 & !A11 & A12 & !A13 & A14 & A15 & CLK & BA; +!VIC = !A10 & !A11 & A12 & !A13 & A14 & A15 & CLK & BA; +!COLRAM = !A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA +# !CLK +# !BA; +BUF = !A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA; +!CIA = A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA; +!RW_OUT = CLK & !RW_IN;*/ + +endmodule \ No newline at end of file diff --git a/Commodore MAX/rtl/pll.qip b/Commodore MAX/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Commodore MAX/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Commodore MAX/rtl/pll.v b/Commodore MAX/rtl/pll.v new file mode 100644 index 00000000..0adb538f --- /dev/null +++ b/Commodore MAX/rtl/pll.v @@ -0,0 +1,404 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + c2, + c3, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output c3; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire3; + wire [0:0] sub_wire8 = 1'h0; + wire [2:2] sub_wire5 = sub_wire0[2:2]; + wire [0:0] sub_wire4 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire c3 = sub_wire2; + wire locked = sub_wire3; + wire c0 = sub_wire4; + wire c2 = sub_wire5; + wire sub_wire6 = inclk0; + wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire7), + .clk (sub_wire0), + .locked (sub_wire3), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 32, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 27, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 1, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 27, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 8, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 2240, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 83, + altpll_component.clk3_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "2240" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "1.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "8.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "1.000446" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "32" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "83" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "1.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "8.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "1.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2240" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "83" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Commodore MAX/rtl/scandoubler.v b/Commodore MAX/rtl/scandoubler.v new file mode 100644 index 00000000..5a3ccd17 --- /dev/null +++ b/Commodore MAX/rtl/scandoubler.v @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Commodore MAX/rtl/sid_6581.vhd b/Commodore MAX/rtl/sid_6581.vhd new file mode 100644 index 00000000..920c6f1b --- /dev/null +++ b/Commodore MAX/rtl/sid_6581.vhd @@ -0,0 +1,348 @@ +------------------------------------------------------------------------------- +-- +-- SID 6581 +-- +-- A fully functional SID chip implementation in VHDL +-- +------------------------------------------------------------------------------- +-- to do: - filter +-- - smaller implementation, use multiplexed channels +-- +-- +-- "The Filter was a classic multi-mode (state variable) VCF design. There was +-- no way to create a variable transconductance amplifier in our NMOS process, +-- so I simply used FETs as voltage-controlled resistors to control the cutoff +-- frequency. An 11-bit D/A converter generates the control voltage for the +-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I +-- disconnected it!)." +-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each +-- bit would turn on one of the weighted resistors and allow a portion of the +-- output to feed back to the input. The state-variable design provided +-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches +-- selected which combination of outputs were sent to the final amplifier (a +-- notch filter was created by enabling both the high and low-pass outputs +-- simultaneously)." +-- "The filter is the worst part of SID because I could not create high-gain +-- op-amps in NMOS, which were essential to a resonant filter. In addition, +-- the resistance of the FETs varied considerably with processing, so different +-- lots of SID chips had different cutoff frequency characteristics. I knew it +-- wouldn't work very well, but it was better than nothing and I didn't have +-- time to make it better." +-- +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +------------------------------------------------------------------------------- + +entity sid_6581 is + port ( + clk_1MHz : in std_logic; -- main SID clock signal + clk32 : in std_logic; -- main clock signal + reset : in std_logic; -- high active signal (reset when reset = '1') + cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed + we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read + + addr : in std_logic_vector(4 downto 0); -- address lines + data_i : in std_logic_vector(7 downto 0); -- data in (to chip) + data_o : out std_logic_vector(7 downto 0); -- data out (from chip) + + poti_x : in std_logic; -- paddle input-X + poti_y : in std_logic; -- paddle input-Y + audio_data : out std_logic_vector(17 downto 0) + ); +end sid_6581; + +architecture Behavioral of sid_6581 is + + component pwm_sdadc is + port ( + clk : in std_logic; -- main clock signal (actually the higher the better) + reset : in std_logic; -- + ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted + ADC_in : in std_logic -- "analog" paddle input pin + ); + end component; + + -- Implementation of the SID voices (sound channels) + component sid_voice is + port ( + clk_1MHz : in std_logic; -- this line drives the oscilator + reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1) + Freq_lo : in std_logic_vector(7 downto 0); -- + Freq_hi : in std_logic_vector(7 downto 0); -- + Pw_lo : in std_logic_vector(7 downto 0); -- + Pw_hi : in std_logic_vector(3 downto 0); -- + Control : in std_logic_vector(7 downto 0); -- + Att_dec : in std_logic_vector(7 downto 0); -- + Sus_Rel : in std_logic_vector(7 downto 0); -- + PA_MSB_in : in std_logic; -- + PA_MSB_out : out std_logic; -- + Osc : out std_logic_vector(7 downto 0); -- + Env : out std_logic_vector(7 downto 0); -- + voice : out std_logic_vector(11 downto 0) -- + ); + end component; + +------------------------------------------------------------------------------- +--constant : := ; +-- DC offset required to play samples, this is actually a bug of the real 6581, +-- that was converted into an advantage to play samples +constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111"; +------------------------------------------------------------------------------- + +signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0'); +signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0'); + +signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0'); +signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0'); + +signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0'); +signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0'); +signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0'); + +signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0'); +signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0'); +signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0'); +signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0'); + +signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0'); +signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0'); +signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0'); +signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0'); + +signal do_buf : std_logic_vector(7 downto 0) := (others => '0'); + +signal voice_1 : std_logic_vector(11 downto 0) := (others => '0'); +signal voice_2 : std_logic_vector(11 downto 0) := (others => '0'); +signal voice_3 : std_logic_vector(11 downto 0) := (others => '0'); +signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0'); + +signal divide_0 : std_logic_vector(31 downto 0) := (others => '0'); +signal voice_1_PA_MSB : std_logic := '0'; +signal voice_2_PA_MSB : std_logic := '0'; +signal voice_3_PA_MSB : std_logic := '0'; + +------------------------------------------------------------------------------- + +begin + + paddle_x: pwm_sdadc + port map ( + clk => clk_1MHz, + reset => reset, + ADC_out => Misc_PotX, + ADC_in => poti_x + ); + + paddle_y: pwm_sdadc + port map ( + clk => clk_1MHz, + reset => reset, + ADC_out => Misc_PotY, + ADC_in => poti_y + ); + + sid_voice_1: sid_voice + port map( + clk_1MHz => clk_1MHz, + reset => reset, + Freq_lo => Voice_1_Freq_lo, + Freq_hi => Voice_1_Freq_hi, + Pw_lo => Voice_1_Pw_lo, + Pw_hi => Voice_1_Pw_hi, + Control => Voice_1_Control, + Att_dec => Voice_1_Att_dec, + Sus_Rel => Voice_1_Sus_Rel, + PA_MSB_in => voice_3_PA_MSB, + PA_MSB_out => voice_1_PA_MSB, + Osc => Voice_1_Osc, + Env => Voice_1_Env, + voice => voice_1 + ); + + sid_voice_2: sid_voice + port map( + clk_1MHz => clk_1MHz, + reset => reset, + Freq_lo => Voice_2_Freq_lo, + Freq_hi => Voice_2_Freq_hi, + Pw_lo => Voice_2_Pw_lo, + Pw_hi => Voice_2_Pw_hi, + Control => Voice_2_Control, + Att_dec => Voice_2_Att_dec, + Sus_Rel => Voice_2_Sus_Rel, + PA_MSB_in => voice_1_PA_MSB, + PA_MSB_out => voice_2_PA_MSB, + Osc => Voice_2_Osc, + Env => Voice_2_Env, + voice => voice_2 + ); + + sid_voice_3: sid_voice + port map( + clk_1MHz => clk_1MHz, + reset => reset, + Freq_lo => Voice_3_Freq_lo, + Freq_hi => Voice_3_Freq_hi, + Pw_lo => Voice_3_Pw_lo, + Pw_hi => Voice_3_Pw_hi, + Control => Voice_3_Control, + Att_dec => Voice_3_Att_dec, + Sus_Rel => Voice_3_Sus_Rel, + PA_MSB_in => voice_2_PA_MSB, + PA_MSB_out => voice_3_PA_MSB, + Osc => Misc_Osc3_Random, + Env => Misc_Env3, + voice => voice_3 + ); + +------------------------------------------------------------------------------------- +data_o <= do_buf; + +-- add voice 1+2 and 3, we must do this in this way to create the shortest +-- timing path (keep in mind that a basic adder can only add two variables) +voice_mixed <= (("00" & voice_1) + ("00" & voice_2)) + (voice_3 + DC_offset); +-- multiply the volume register with the voices +audio_data <= (voice_mixed * Filter_Mode_Vol(3 downto 0)); + +-- Register decoding +register_decoder:process(clk32) +begin + if rising_edge(clk32) then + if (reset = '1') then + --------------------------------------- Voice-1 + Voice_1_Freq_lo <= (others => '0'); + Voice_1_Freq_hi <= (others => '0'); + Voice_1_Pw_lo <= (others => '0'); + Voice_1_Pw_hi <= (others => '0'); + Voice_1_Control <= (others => '0'); + Voice_1_Att_dec <= (others => '0'); + Voice_1_Sus_Rel <= (others => '0'); + --------------------------------------- Voice-2 + Voice_2_Freq_lo <= (others => '0'); + Voice_2_Freq_hi <= (others => '0'); + Voice_2_Pw_lo <= (others => '0'); + Voice_2_Pw_hi <= (others => '0'); + Voice_2_Control <= (others => '0'); + Voice_2_Att_dec <= (others => '0'); + Voice_2_Sus_Rel <= (others => '0'); + --------------------------------------- Voice-3 + Voice_3_Freq_lo <= (others => '0'); + Voice_3_Freq_hi <= (others => '0'); + Voice_3_Pw_lo <= (others => '0'); + Voice_3_Pw_hi <= (others => '0'); + Voice_3_Control <= (others => '0'); + Voice_3_Att_dec <= (others => '0'); + Voice_3_Sus_Rel <= (others => '0'); + --------------------------------------- Filter & volume + Filter_Fc_lo <= (others => '0'); + Filter_Fc_hi <= (others => '0'); + Filter_Res_Filt <= (others => '0'); + Filter_Mode_Vol <= (others => '0'); + else + Voice_1_Freq_lo <= Voice_1_Freq_lo; + Voice_1_Freq_hi <= Voice_1_Freq_hi; + Voice_1_Pw_lo <= Voice_1_Pw_lo; + Voice_1_Pw_hi <= Voice_1_Pw_hi; + Voice_1_Control <= Voice_1_Control; + Voice_1_Att_dec <= Voice_1_Att_dec; + Voice_1_Sus_Rel <= Voice_1_Sus_Rel; + Voice_2_Freq_lo <= Voice_2_Freq_lo; + Voice_2_Freq_hi <= Voice_2_Freq_hi; + Voice_2_Pw_lo <= Voice_2_Pw_lo; + Voice_2_Pw_hi <= Voice_2_Pw_hi; + Voice_2_Control <= Voice_2_Control; + Voice_2_Att_dec <= Voice_2_Att_dec; + Voice_2_Sus_Rel <= Voice_2_Sus_Rel; + Voice_3_Freq_lo <= Voice_3_Freq_lo; + Voice_3_Freq_hi <= Voice_3_Freq_hi; + Voice_3_Pw_lo <= Voice_3_Pw_lo; + Voice_3_Pw_hi <= Voice_3_Pw_hi; + Voice_3_Control <= Voice_3_Control; + Voice_3_Att_dec <= Voice_3_Att_dec; + Voice_3_Sus_Rel <= Voice_3_Sus_Rel; + Filter_Fc_lo <= Filter_Fc_lo; + Filter_Fc_hi <= Filter_Fc_hi; + Filter_Res_Filt <= Filter_Res_Filt; + Filter_Mode_Vol <= Filter_Mode_Vol; + do_buf <= (others => '0'); + + if (cs='1') then + if (we='1') then -- Write to SID-register + ------------------------ + case addr is + -------------------------------------- Voice-1 + when "00000" => Voice_1_Freq_lo <= data_i; + when "00001" => Voice_1_Freq_hi <= data_i; + when "00010" => Voice_1_Pw_lo <= data_i; + when "00011" => Voice_1_Pw_hi <= data_i(3 downto 0); + when "00100" => Voice_1_Control <= data_i; + when "00101" => Voice_1_Att_dec <= data_i; + when "00110" => Voice_1_Sus_Rel <= data_i; + --------------------------------------- Voice-2 + when "00111" => Voice_2_Freq_lo <= data_i; + when "01000" => Voice_2_Freq_hi <= data_i; + when "01001" => Voice_2_Pw_lo <= data_i; + when "01010" => Voice_2_Pw_hi <= data_i(3 downto 0); + when "01011" => Voice_2_Control <= data_i; + when "01100" => Voice_2_Att_dec <= data_i; + when "01101" => Voice_2_Sus_Rel <= data_i; + --------------------------------------- Voice-3 + when "01110" => Voice_3_Freq_lo <= data_i; + when "01111" => Voice_3_Freq_hi <= data_i; + when "10000" => Voice_3_Pw_lo <= data_i; + when "10001" => Voice_3_Pw_hi <= data_i(3 downto 0); + when "10010" => Voice_3_Control <= data_i; + when "10011" => Voice_3_Att_dec <= data_i; + when "10100" => Voice_3_Sus_Rel <= data_i; + --------------------------------------- Filter & volume + when "10101" => Filter_Fc_lo <= data_i; + when "10110" => Filter_Fc_hi <= data_i; + when "10111" => Filter_Res_Filt <= data_i; + when "11000" => Filter_Mode_Vol <= data_i; + -------------------------------------- + when others => null; + end case; + + else -- Read from SID-register + ------------------------- + --case CONV_INTEGER(addr) is + case addr is + -------------------------------------- Misc + when "11001" => do_buf <= Misc_PotX; + when "11010" => do_buf <= Misc_PotY; + when "11011" => do_buf <= Misc_Osc3_Random; + when "11100" => do_buf <= Misc_Env3; + -------------------------------------- +-- when others => null; + when others => do_buf <= (others => '0'); + end case; + end if; + end if; + end if; + end if; +end process; + +end Behavioral; diff --git a/Commodore MAX/rtl/sid_components.vhd b/Commodore MAX/rtl/sid_components.vhd new file mode 100644 index 00000000..6f2e1ed7 --- /dev/null +++ b/Commodore MAX/rtl/sid_components.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------- +-- +-- SID 6581 (voice) +-- +-- This piece of VHDL code describes a single SID voice (sound channel) +-- +------------------------------------------------------------------------------- +-- to do: - better resolution of result signal voice, this is now only 12bits, +-- but it could be 20 !! Problem, it does not fit the PWM-dac +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- +--Implementation Digital to Analog converter +entity pwm_sddac is + generic ( + msbi_g : integer := 9 + ); + port ( + clk_i : in std_logic; + reset : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); +end pwm_sddac; + +architecture rtl of pwm_sddac is + signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0'); + +begin + seq: process (clk_i, reset) + begin + if reset = '1' then + sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i); + dac_o <= sig_in(msbi_g+2); + end if; + end process seq; +end rtl; + +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity pwm_sdadc is + port ( + clk : in std_logic; -- main clock signal (the higher the better) + reset : in std_logic; -- + ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted + ADC_in : in std_logic -- "analog" paddle input pin + ); +end pwm_sdadc; + +-- Dummy implementation (no real A/D conversion performed) +architecture rtl of pwm_sdadc is +begin + process (clk, ADC_in) + begin + if ADC_in = '1' then + ADC_out <= (others => '1'); + else + ADC_out <= (others => '0'); + end if; + end process; +end rtl; diff --git a/Commodore MAX/rtl/sid_voice.vhd b/Commodore MAX/rtl/sid_voice.vhd new file mode 100644 index 00000000..69fa50f1 --- /dev/null +++ b/Commodore MAX/rtl/sid_voice.vhd @@ -0,0 +1,656 @@ +------------------------------------------------------------------------------- +-- +-- SID 6581 (voice) +-- +-- This piece of VHDL code describes a single SID voice (sound channel) +-- +------------------------------------------------------------------------------- +-- to do: - better resolution of result signal voice, this is now only 12bits +-- but it could be 20 !! Problem, it does not fit the PWM-dac +------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +------------------------------------------------------------------------------- + +entity sid_voice is + port ( + clk_1MHz : in std_logic; -- this line drives the oscilator + reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1) + Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register + Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register + Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register + Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register + Control : in std_logic_vector(7 downto 0); -- control register + Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register + Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register + PA_MSB_in : in std_logic; -- Phase Accumulator MSB input + PA_MSB_out : out std_logic; -- Phase Accumulator MSB output + Osc : out std_logic_vector(7 downto 0); -- Voice waveform register + Env : out std_logic_vector(7 downto 0); -- Voice envelope register + voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal + ); +end sid_voice; + +architecture Behavioral of sid_voice is + +------------------------------------------------------------------------------- +-- Altera multiplier +-- COMPONENT lpm_mult +-- GENERIC +-- ( +-- lpm_hint : STRING; +-- lpm_representation : STRING; +-- lpm_type : STRING; +-- lpm_widtha : NATURAL; +-- lpm_widthb : NATURAL; +-- lpm_widthp : NATURAL; +-- lpm_widths : NATURAL +-- ); +-- PORT +-- ( +-- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0); +-- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0); +-- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0) +-- ); +-- END COMPONENT; + +------------------------------------------------------------------------------- + +signal accumulator : std_logic_vector(23 downto 0) := (others => '0'); +signal accu_bit_prev : std_logic := '0'; +signal PA_MSB_in_prev : std_logic := '0'; + +-- this type of signal has only two states 0 or 1 (so no more bits are required) +signal pulse : std_logic := '0'; +signal sawtooth : std_logic_vector(11 downto 0) := (others => '0'); +signal triangle : std_logic_vector(11 downto 0) := (others => '0'); +signal noise : std_logic_vector(11 downto 0) := (others => '0'); +signal LFSR : std_logic_vector(22 downto 0) := (others => '0'); + +signal frequency : std_logic_vector(15 downto 0) := (others => '0'); +signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0'); + +-- Envelope Generator +type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, releases, release_lp); +signal cur_state, next_state : envelope_state_types; +signal divider_value : integer range 0 to 2**15 - 1 :=0; +signal divider_attack : integer range 0 to 2**15 - 1 :=0; +signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0; +signal divider_counter : integer range 0 to 2**18 - 1 :=0; +signal exp_table_value : integer range 0 to 2**18 - 1 :=0; +signal exp_table_active : std_logic := '0'; +signal divider_rst : std_logic := '0'; +signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0'); +signal Dec_rel_sel : std_logic := '0'; + +signal env_counter : std_logic_vector(17 downto 0) := (others => '0'); +signal env_count_hold_A : std_logic := '0'; +signal env_count_hold_B : std_logic := '0'; +signal env_cnt_up : std_logic := '0'; +signal env_cnt_clear : std_logic := '0'; + +signal signal_mux : std_logic_vector(17 downto 0) := (others => '0'); +signal signal_vol : std_logic_vector(35 downto 0) := (others => '0'); + +------------------------------------------------------------------------------------- + +-- stop the oscillator when test = '1' +alias test : std_logic is Control(3); +-- Ring Modulation was accomplished by substituting the accumulator MSB of an +-- oscillator in the EXOR function of the triangle waveform generator with the +-- accumulator MSB of the previous oscillator. That is why the triangle waveform +-- must be selected to use Ring Modulation. +alias ringmod : std_logic is Control(2); +-- Hard Sync was accomplished by clearing the accumulator of an Oscillator +-- based on the accumulator MSB of the previous oscillator. +alias sync : std_logic is Control(1); +-- +alias gate : std_logic is Control(0); + +------------------------------------------------------------------------------------- + +begin + +-- output the Phase accumulator's MSB for sync and ringmod purposes +PA_MSB_out <= accumulator(23); +-- output the upper 8-bits of the waveform. +-- Useful for random numbers (noise must be selected) +Osc <= signal_mux(11 downto 4); +-- output the envelope register, for special sound effects when connecting this +-- signal to the input of other channels/voices +Env <= env_counter(7 downto 0); +-- use the register value to fill the variable +frequency(15 downto 8) <= Freq_hi(7 downto 0); +-- +frequency(7 downto 0) <= Freq_lo(7 downto 0); +-- use the register value to fill the variable +pulsewidth(11 downto 8) <= Pw_hi(3 downto 0); +-- +pulsewidth(7 downto 0) <= Pw_lo(7 downto 0); +-- +voice <= signal_vol(19 downto 8); + +-- Phase accumulator : +-- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which +-- the lower 16-bits are programmable for pitch control. The output of the +-- accumulator goes directly to a D/A converter through a waveform selector. +-- Normally, the output of a phase-accumulating oscillator would be used as an +-- address into memory which contained a wavetable, but SID had to be entirely +-- self-contained and there was no room at all for a wavetable on the chip." +-- "Hard Sync was accomplished by clearing the accumulator of an Oscillator +-- based on the accumulator MSB of the previous oscillator." +PhaseAcc:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + PA_MSB_in_prev <= PA_MSB_in; + -- the reset and test signal can stop the oscillator, + -- stopping the oscillator is very useful when you want to play "samples" + if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then + accumulator <= (others => '0'); + else + -- accumulate the new phase (i.o.w. increment env_counter with the freq. value) + accumulator <= accumulator + ("0" & frequency(15 downto 0)); + end if; + end if; +end process; + +-- Sawtooth waveform : +-- "The Sawtooth waveform was created by sending the upper 12-bits of the +-- accumulator to the 12-bit Waveform D/A." +Snd_Sawtooth:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + sawtooth <= accumulator(23 downto 12); + end if; +end process; + +--Pulse waveform : +-- "The Pulse waveform was created by sending the upper 12-bits of the +-- accumulator to a 12-bit digital comparator. The output of the comparator was +-- either a one or a zero. This single output was then sent to all 12 bits of +-- the Waveform D/A. " +Snd_pulse:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then + pulse <= '1'; + else + pulse <= '0'; + end if; + end if; +end process; + +--Triangle waveform : +-- "The Triangle waveform was created by using the MSB of the accumulator to +-- invert the remaining upper 11 accumulator bits using EXOR gates. These 11 +-- bits were then left-shifted (throwing away the MSB) and sent to the Waveform +-- D/A (so the resolution of the triangle waveform was half that of the sawtooth, +-- but the amplitude and frequency were the same). " +-- "Ring Modulation was accomplished by substituting the accumulator MSB of an +-- oscillator in the EXOR function of the triangle waveform generator with the +-- accumulator MSB of the previous oscillator. That is why the triangle waveform +-- must be selected to use Ring Modulation." +Snd_triangle:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + if ringmod = '0' then + -- no ringmodulation + triangle(11)<= accumulator(23) xor accumulator(22); + triangle(10)<= accumulator(23) xor accumulator(21); + triangle(9) <= accumulator(23) xor accumulator(20); + triangle(8) <= accumulator(23) xor accumulator(19); + triangle(7) <= accumulator(23) xor accumulator(18); + triangle(6) <= accumulator(23) xor accumulator(17); + triangle(5) <= accumulator(23) xor accumulator(16); + triangle(4) <= accumulator(23) xor accumulator(15); + triangle(3) <= accumulator(23) xor accumulator(14); + triangle(2) <= accumulator(23) xor accumulator(13); + triangle(1) <= accumulator(23) xor accumulator(12); + triangle(0) <= accumulator(23) xor accumulator(11); + else + -- ringmodulation by the other voice (previous voice) + triangle(11)<= PA_MSB_in xor accumulator(22); + triangle(10)<= PA_MSB_in xor accumulator(21); + triangle(9) <= PA_MSB_in xor accumulator(20); + triangle(8) <= PA_MSB_in xor accumulator(19); + triangle(7) <= PA_MSB_in xor accumulator(18); + triangle(6) <= PA_MSB_in xor accumulator(17); + triangle(5) <= PA_MSB_in xor accumulator(16); + triangle(4) <= PA_MSB_in xor accumulator(15); + triangle(3) <= PA_MSB_in xor accumulator(14); + triangle(2) <= PA_MSB_in xor accumulator(13); + triangle(1) <= PA_MSB_in xor accumulator(12); + triangle(0) <= PA_MSB_in xor accumulator(11); + end if; + end if; +end process; + +--Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) : +-- "The Noise waveform was created using a 23-bit pseudo-random sequence +-- generator (i.e., a shift register with specific outputs fed back to the input +-- through combinatorial logic). The shift register was clocked by one of the +-- intermediate bits of the accumulator to keep the frequency content of the +-- noise waveform relatively the same as the pitched waveforms. +-- The upper 12-bits of the shift register were sent to the Waveform D/A." +noise <= LFSR(22 downto 11); + +Snd_noise:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + -- the test signal can stop the oscillator, + -- stopping the oscillator is very useful when you want to play "samples" + if ((reset = '1') or (test = '1')) then + accu_bit_prev <= '0'; + -- the "seed" value (the value that eventually determines the output + -- pattern) may never be '0' otherwise the generator "locks up" + LFSR <= "00000000000000000000001"; + else + accu_bit_prev <= accumulator(22); + -- when not equal to ... + if (accu_bit_prev /= accumulator(22)) then + LFSR(22 downto 1) <= LFSR(21 downto 0); + LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps + else + LFSR <= LFSR; + end if; + end if; + end if; +end process; + +-- Waveform Output selector (MUX): +-- "Since all of the waveforms were just digital bits, the Waveform Selector +-- consisted of multiplexers that selected which waveform bits would be sent +-- to the Waveform D/A. The multiplexers were single transistors and did not +-- provide a "lock-out", allowing combinations of the waveforms to be selected. +-- The combination was actually a logical ANDing of the bits of each waveform, +-- which produced unpredictable results, so I didn't encourage this, especially +-- since it could lock up the pseudo-random sequence generator by filling it +-- with zeroes." +Snd_select:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7)); + signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7)); + signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7)); + signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7)); + signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7)); + signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7)); + signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7)); + signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7)); + signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7)); + signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7)); + signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7)); + signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7)); + end if; +end process; + +-- Waveform envelope (volume) control : +-- "The output of the Waveform D/A (which was an analog voltage at this point) +-- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA +-- (digitally-controlled-amplifier). The digital control word which modulated +-- the amplitude of the waveform came from the Envelope Generator." +-- "The 8-bit output of the Envelope Generator was then sent to the Multiplying +-- D/A converter to modulate the amplitude of the selected Oscillator Waveform +-- (to be technically accurate, actually the waveform was modulating the output +-- of the Envelope Generator, but the result is the same)." + Envelope_multiplier:process(clk_1MHz) + begin + if (rising_edge(clk_1MHz)) then + --calculate the resulting volume (due to the envelope generator) of the + --voice, signal_mux(12bit) * env_counter(8bit), so the result will + --require 20 bits !! + signal_vol <= signal_mux * env_counter; + end if; +end process; + +-- Altera multiplier +-- lpm_mult_component : lpm_mult +-- GENERIC MAP +-- ( +-- lpm_hint => "MAXIMIZE_SPEED=5", +-- lpm_representation => "UNSIGNED", +-- lpm_type => "LPM_MULT", +-- lpm_widtha => 12, +-- lpm_widthb => 8, +-- lpm_widthp => 20, +-- lpm_widths => 1 +-- ) +-- PORT MAP +-- ( +-- dataa(11 downto 0) => signal_mux, +-- datab(7 downto 0) => env_counter, +-- result => signal_vol +-- ); + +-- Envelope generator : +-- "The Envelope Generator was simply an 8-bit up/down counter which, when +-- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from +-- 255 down to the programmed Sustain value at the Decay rate, remained at the +-- Sustain value until the Gate bit was cleared then counted down from the +-- Sustain value to 0 at the Release rate." +-- +-- /\ +-- / \ +-- / | \________ +-- / | | \ +-- / | | |\ +-- / | | | \ +-- attack|dec|sustain|rel + +-- this process controls the state machine "current-state"-value +Envelope_SM_advance: process (reset, clk_1MHz) +begin + if (reset = '1') then + cur_state <= idle; + else + if (rising_edge(clk_1MHz)) then + cur_state <= next_state; + end if; + end if; +end process; + + +-- this process controls the envelope (in other words, the volume control) +Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter) +begin + if (reset = '1') then + next_state <= idle; + env_cnt_clear <='1'; + env_cnt_up <='1'; + env_count_hold_B <='1'; + divider_rst <='1'; + divider_value <= 0; + exp_table_active <='0'; + Dec_rel_sel <='0'; -- select decay as input for decay/release table + else + env_cnt_clear <='0'; -- use this statement unless stated otherwise + env_cnt_up <='1'; -- use this statement unless stated otherwise + env_count_hold_B <='1'; -- use this statement unless stated otherwise + divider_rst <='0'; -- use this statement unless stated otherwise + divider_value <= 0; -- use this statement unless stated otherwise + exp_table_active <='0'; -- use this statement unless stated otherwise + case cur_state is + + -- IDLE + when idle => + env_cnt_clear <= '1'; -- clear envelope env_counter + divider_rst <= '1'; + Dec_rel_sel <= '0'; -- select decay as input for decay/release table + if gate = '1' then + next_state <= attack; + else + next_state <= idle; + end if; + + when attack => + env_cnt_clear <= '1'; -- clear envelope env_counter + divider_rst <= '1'; + divider_value <= divider_attack; + next_state <= attack_lp; + Dec_rel_sel <= '0'; -- select decay as input for decay/release table + + when attack_lp => + env_count_hold_B <= '0'; -- enable envelope env_counter + env_cnt_up <= '1'; -- envelope env_counter must count up (increment) + divider_value <= divider_attack; + Dec_rel_sel <= '0'; -- select decay as input for decay/release table + if env_counter = "11111111" then + next_state <= decay; + else + if gate = '0' then + next_state <= releases; + else + next_state <= attack_lp; + end if; + end if; + + when decay => + divider_rst <= '1'; + exp_table_active <= '1'; -- activate exponential look-up table + env_cnt_up <= '0'; -- envelope env_counter must count down (decrement) + divider_value <= divider_dec_rel; + next_state <= decay_lp; + Dec_rel_sel <= '0'; -- select decay as input for decay/release table + + when decay_lp => + exp_table_active <= '1'; -- activate exponential look-up table + env_count_hold_B <= '0'; -- enable envelope env_counter + env_cnt_up <= '0'; -- envelope env_counter must count down (decrement) + divider_value <= divider_dec_rel; + Dec_rel_sel <= '0'; -- select decay as input for decay/release table + if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then + next_state <= sustain; + else + if gate = '0' then + next_state <= releases; + else + next_state <= decay_lp; + end if; + end if; + + -- "A digital comparator was used for the Sustain function. The upper + -- four bits of the Up/Down counter were compared to the programmed + -- Sustain value and would stop the clock to the Envelope Generator when + -- the counter counted down to the Sustain value. This created 16 linearly + -- spaced sustain levels without havingto go through a look-up table + -- translation between the 4-bit register value and the 8-bit Envelope + -- Generator output. It also meant that sustain levels were adjustable + -- in steps of 16. Again, more register bits would have provided higher + -- resolution." + -- "When the Gate bit was cleared, the clock would again be enabled, + -- allowing the counter to count down to zero. Like an analog envelope + -- generator, the SID Envelope Generator would track the Sustain level + -- if it was changed to a lower value during the Sustain portion of the + -- envelope, however, it would not count UP if the Sustain level were set + -- higher." Instead it would count down to '0'. + when sustain => + divider_value <= 0; + Dec_rel_sel <='1'; -- select release as input for decay/release table + if gate = '0' then + next_state <= releases; + else + if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then + next_state <= sustain; + else + next_state <= decay; + end if; + end if; + + when releases => + divider_rst <= '1'; + exp_table_active <= '1'; -- activate exponential look-up table + env_cnt_up <= '0'; -- envelope env_counter must count down (decrement) + divider_value <= divider_dec_rel; + Dec_rel_sel <= '1'; -- select release as input for decay/release table + next_state <= release_lp; + + when release_lp => + exp_table_active <= '1'; -- activate exponential look-up table + env_count_hold_B <= '0'; -- enable envelope env_counter + env_cnt_up <= '0'; -- envelope env_counter must count down (decrement) + divider_value <= divider_dec_rel; + Dec_rel_sel <= '1'; -- select release as input for decay/release table + if env_counter = "00000000" then + next_state <= idle; + else + if gate = '1' then + next_state <= idle; + else + next_state <= release_lp; + end if; + end if; + + when others => + divider_value <= 0; + Dec_rel_sel <= '0'; -- select decay as input for decay/release table + next_state <= idle; + end case; + end if; +end process; + +-- 8 bit up/down env_counter +Envelope_counter:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + if ((reset = '1') or (env_cnt_clear = '1')) then + env_counter <= (others => '0'); + else + if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then + env_counter <= env_counter; + else + if (env_cnt_up = '1') then + env_counter <= env_counter + 1; + else + env_counter <= env_counter - 1; + end if; + end if; + end if; + end if; +end process; + +-- Divider : +-- "A programmable frequency divider was used to set the various rates +-- (unfortunately I don't remember how many bits the divider was, either 12 +-- or 16 bits). A small look-up table translated the 16 register-programmable +-- values to the appropriate number to load into the frequency divider. +-- Depending on what state the Envelope Generator was in (i.e. ADS or R), the +-- appropriate register would be selected and that number would be translated +-- and loaded into the divider. Obviously it would have been better to have +-- individual bit control of the divider which would have provided great +-- resolution for each rate, however I did not have enough silicon area for a +-- lot of register bits. Using this approach, I was able to cram a wide range +-- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead +-- of eight. The actual numbers in the look-up table were arrived at +-- subjectively by setting up typical patches on a Sequential Circuits Pro-1 +-- and measuring the envelope times by ear (which is why the available rates +-- seem strange)!" +prog_freq_div:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + if ((reset = '1') or (divider_rst = '1')) then + env_count_hold_A <= '1'; + divider_counter <= 0; + else + if (divider_counter = 0) then + env_count_hold_A <= '0'; + if (exp_table_active = '1') then + divider_counter <= exp_table_value; + else + divider_counter <= divider_value; + end if; + else + env_count_hold_A <= '1'; + divider_counter <= divider_counter - 1; + end if; + end if; + end if; +end process; + +-- Piese-wise linear approximation of an exponential : +-- "In order to more closely model the exponential decay of sounds, another +-- look-up table on the output of the Envelope Generator would sequentially +-- divide the clock to the Envelope Generator by two at specific counts in the +-- Decay and Release cycles. This created a piece-wise linear approximation of +-- an exponential. I was particularly happy how well this worked considering +-- the simplicity of the circuitry. The Attack, however, was linear, but this +-- sounded fine." +-- The clock is divided by two at specifiek values of the envelope generator to +-- create an exponential. +Exponential_table:process(clk_1MHz) +BEGIN + if (rising_edge(clk_1MHz)) then + if (reset = '1') then + exp_table_value <= 0; + else + case CONV_INTEGER(env_counter) is + when 0 to 51 => exp_table_value <= divider_value * 16; + when 52 to 101 => exp_table_value <= divider_value * 8; + when 102 to 152 => exp_table_value <= divider_value * 4; + when 153 to 203 => exp_table_value <= divider_value * 2; + when 204 to 255 => exp_table_value <= divider_value; + when others => exp_table_value <= divider_value; + end case; + end if; + end if; +end process; + +-- Attack Lookup table : +-- It takes 255 clock cycles from zero to peak value. Therefore the divider +-- equals (attack rate / clockcycletime of 1MHz clock) / 254; +Attack_table:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + if (reset = '1') then + divider_attack <= 0; + else + case Att_dec(7 downto 4) is + when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps + when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps + when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps + when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps + when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps + when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps + when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps + when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps + when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps + when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps + when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps + when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps + when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps + when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps + when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps + when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps + when others => divider_attack <= 0; -- + end case; + end if; + end if; +end process; + +Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel) +begin + if (Dec_rel_sel = '0') then + Dec_rel(3 downto 0) <= Att_dec(3 downto 0); + else + Dec_rel(3 downto 0) <= Sus_rel(3 downto 0); + end if; +end process; + +-- Decay Lookup table : +-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero. +-- Release Lookup table : +-- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero. +Decay_Release_table:process(clk_1MHz) +begin + if (rising_edge(clk_1MHz)) then + if reset = '1' then + divider_dec_rel <= 0; + else + case Dec_rel(3 downto 0) is + when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632 + when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632 + when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632 + when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632 + when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632 + when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632 + when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632 + when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632 + when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632 + when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632 + when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632 + when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632 + when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632 + when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632 + when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632 + when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632 + when others => divider_dec_rel <= 0; -- + end case; + end if; + end if; +end process; + +end Behavioral; diff --git a/Commodore MAX/rtl/sigma_delta_dac.v b/Commodore MAX/rtl/sigma_delta_dac.v new file mode 100644 index 00000000..34cfd312 --- /dev/null +++ b/Commodore MAX/rtl/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=18) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= 1; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= ~SigmaLatch[MSBI+2]; + end +end + +endmodule diff --git a/Commodore MAX/rtl/user_io.v b/Commodore MAX/rtl/user_io.v new file mode 100644 index 00000000..c66c515f --- /dev/null +++ b/Commodore MAX/rtl/user_io.v @@ -0,0 +1,411 @@ +// +// user_io.v +// +// user_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +// parameter STRLEN and the actual length of conf_str have to match + +module user_io #(parameter STRLEN=0) ( + input [(8*STRLEN)-1:0] conf_str, + + input SPI_CLK, + input SPI_SS_IO, + output reg SPI_MISO, + input SPI_MOSI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + + output reg [7:0] status, + + // connection to sd card emulation + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + input sd_conf, + input sd_sdhc, + output reg [7:0] sd_dout, + output reg sd_dout_strobe, + input [7:0] sd_din, + output reg sd_din_strobe, + + + // ps2 keyboard emulation + input ps2_clk, // 12-16khz provided by core + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // serial com port + input [7:0] serial_data, + input serial_strobe +); + +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [7:0] joystick0; +reg [7:0] joystick1; +reg [4:0] but_sw; +reg [2:0] stick_idx; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +// filter spi clock. the 8 bit gate delay is ~2.5ns in total +wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */; +wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff); + +// drive MISO only when transmitting core id +always@(negedge spi_sck or posedge SPI_SS_IO) begin + if(SPI_SS_IO == 1) begin + SPI_MISO <= 1'bZ; + end else begin + + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + SPI_MISO <= core_type[~bit_cnt]; + + end else begin + // reading serial fifo + if(cmd == 8'h1b) begin + // send alternating flag byte and data + if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt]; + else SPI_MISO <= serial_out_byte[~bit_cnt]; + end + + // reading config string + else if(cmd == 8'h14) begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) + SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else + SPI_MISO <= 1'b0; + end + + // reading sd card status + else if(cmd == 8'h16) begin + if(byte_cnt == 1) + SPI_MISO <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) + SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else + SPI_MISO <= 1'b0; + end + + // reading sd card write data + else if(cmd == 8'h18) + SPI_MISO <= sd_din[~bit_cnt]; + + else + SPI_MISO <= 1'b0; + end + end +end + +// ---------------- PS2 --------------------- + +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +// keyboard +reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_kbd_tx_state; +reg [7:0] ps2_kbd_tx_byte; +reg ps2_kbd_parity; + +assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_kbd_r_inc; +always@(posedge ps2_clk) begin + ps2_kbd_r_inc <= 1'b0; + + if(ps2_kbd_r_inc) + ps2_kbd_rptr <= ps2_kbd_rptr + 1; + + // transmitter is idle? + if(ps2_kbd_tx_state == 0) begin + // data in fifo present? + if(ps2_kbd_wptr != ps2_kbd_rptr) begin + // load tx register from fifo + ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; + ps2_kbd_r_inc <= 1'b1; + + // reset parity + ps2_kbd_parity <= 1'b1; + + // start transmitter + ps2_kbd_tx_state <= 4'd1; + + // put start bit on data line + ps2_kbd_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) + ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) + ps2_kbd_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) + ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; + else + ps2_kbd_tx_state <= 4'd0; + + end +end + +// mouse +reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_mouse_tx_state; +reg [7:0] ps2_mouse_tx_byte; +reg ps2_mouse_parity; + +assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_mouse_r_inc; +always@(posedge ps2_clk) begin + ps2_mouse_r_inc <= 1'b0; + + if(ps2_mouse_r_inc) + ps2_mouse_rptr <= ps2_mouse_rptr + 1; + + // transmitter is idle? + if(ps2_mouse_tx_state == 0) begin + // data in fifo present? + if(ps2_mouse_wptr != ps2_mouse_rptr) begin + // load tx register from fifo + ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; + ps2_mouse_r_inc <= 1'b1; + + // reset parity + ps2_mouse_parity <= 1'b1; + + // start transmitter + ps2_mouse_tx_state <= 4'd1; + + // put start bit on data line + ps2_mouse_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) + ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) + ps2_mouse_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) + ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; + else + ps2_mouse_tx_state <= 4'd0; + + end +end + +// fifo to receive serial data from core to be forwarded to io controller + +// 16 byte fifo to store serial bytes +localparam SERIAL_OUT_FIFO_BITS = 6; +reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0]; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr; + +wire serial_out_data_available = serial_out_wptr != serial_out_rptr; +wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */; +wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available}; + +// status[0] is reset signal from io controller and is thus used to flush +// the fifo +always @(posedge serial_strobe or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_wptr <= 0; + end else begin + serial_out_fifo[serial_out_wptr] <= serial_data; + serial_out_wptr <= serial_out_wptr + 1; + end +end + +always@(negedge spi_sck or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_rptr <= 0; + end else begin + if((byte_cnt != 0) && (cmd == 8'h1b)) begin + // read last bit -> advance read pointer + if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) + serial_out_rptr <= serial_out_rptr + 1; + end + end +end + +// SPI receiver +always@(posedge spi_sck or posedge SPI_SS_IO) begin + + if(SPI_SS_IO == 1) begin + bit_cnt <= 3'd0; + byte_cnt <= 8'd0; + sd_ack <= 1'b0; + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + end else begin + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + + sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; + bit_cnt <= bit_cnt + 3'd1; + if((bit_cnt == 7)&&(byte_cnt != 8'd255)) + byte_cnt <= byte_cnt + 8'd1; + + // finished reading command byte + if(bit_cnt == 7) begin + if(byte_cnt == 0) begin + cmd <= { sbuf, SPI_MOSI}; + + // fetch first byte when sectore FPGA->IO command has been seen + if({ sbuf, SPI_MOSI} == 8'h18) + sd_din_strobe <= 1'b1; + + if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18)) + sd_ack <= 1'b1; + + end else begin + + // buttons and switches + if(cmd == 8'h01) + but_sw <= { sbuf[3:0], SPI_MOSI }; + + if(cmd == 8'h02) + joystick_0 <= { sbuf, SPI_MOSI }; + + if(cmd == 8'h03) + joystick_1 <= { sbuf, SPI_MOSI }; + + if(cmd == 8'h04) begin + // store incoming ps2 mouse bytes + ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; + ps2_mouse_wptr <= ps2_mouse_wptr + 1; + end + + if(cmd == 8'h05) begin + // store incoming ps2 keyboard bytes + ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; + ps2_kbd_wptr <= ps2_kbd_wptr + 1; + end + + if(cmd == 8'h15) + status <= { sbuf[6:0], SPI_MOSI }; + + // send sector IO -> FPGA + if(cmd == 8'h17) begin + // flag that download begins + sd_dout <= { sbuf, SPI_MOSI}; + sd_dout_strobe <= 1'b1; + end + + // send sector FPGA -> IO + if(cmd == 8'h18) + sd_din_strobe <= 1'b1; + + // send SD config IO -> FPGA + if(cmd == 8'h19) begin + // flag that download begins + sd_dout <= { sbuf, SPI_MOSI}; + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + sd_dout_strobe <= 1'b1; + end + + // joystick analog + if(cmd == 8'h1a) begin + // first byte is joystick indes + if(byte_cnt == 1) + stick_idx <= { sbuf[1:0], SPI_MOSI }; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) + joystick_analog_0[15:8] <= { sbuf, SPI_MOSI }; + else if(stick_idx == 1) + joystick_analog_1[15:8] <= { sbuf, SPI_MOSI }; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) + joystick_analog_0[7:0] <= { sbuf, SPI_MOSI }; + else if(stick_idx == 1) + joystick_analog_1[7:0] <= { sbuf, SPI_MOSI }; + end + end + + end + end + end +end + +endmodule diff --git a/Commodore MAX/rtl/vic_656x_a.vhd b/Commodore MAX/rtl/vic_656x_a.vhd new file mode 100644 index 00000000..7333518f --- /dev/null +++ b/Commodore MAX/rtl/vic_656x_a.vhd @@ -0,0 +1,1447 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- VIC-II - Video Interface Chip no 2 +-- +-- ----------------------------------------------------------------------- +-- Dar 08/03/2014 : shift hsync to sprite #3 +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +architecture rtl of vic_656x is + type vicCycles is ( + cycleRefresh1, cycleRefresh2, cycleRefresh3, cycleRefresh4, cycleRefresh5, + cycleIdle1, + cycleChar, + cycleCalcSprites, cycleSpriteBa1, cycleSpriteBa2, cycleSpriteBa3, + cycleSpriteA, cycleSpriteB + ); + subtype ColorDef is unsigned(3 downto 0); + type MFlags is array(0 to 7) of boolean; + type MXdef is array(0 to 7) of unsigned(8 downto 0); + type MYdef is array(0 to 7) of unsigned(7 downto 0); + type MCntDef is array(0 to 7) of unsigned(5 downto 0); + type MPixelsDef is array(0 to 7) of unsigned(23 downto 0); + type MCurrentPixelDef is array(0 to 7) of unsigned(1 downto 0); + type charStoreDef is array(38 downto 0) of unsigned(11 downto 0); + type spriteColorsDef is array(7 downto 0) of unsigned(3 downto 0); + type pixelColorStoreDef is array(7 downto 0) of unsigned(3 downto 0); + +-- State machine + signal lastLineFlag : boolean; -- True for on last line of the frame. + signal beyondFrameFlag : boolean; -- Y>frame lines + signal vicCycle : vicCycles := cycleRefresh1; + signal sprite : unsigned(2 downto 0) := "000"; + signal shiftChars : boolean; + signal idle: std_logic := '1'; + signal rasterIrqDone : std_logic; -- Only one interrupt each rasterLine + signal rasterEnable: std_logic; + +-- BA signal + signal badLine : boolean; -- true if we have a badline condition + signal baLoc : std_logic; + signal baCnt : unsigned(2 downto 0); + + signal baChars : std_logic; + signal baSprite04 : std_logic; + signal baSprite15 : std_logic; + signal baSprite26 : std_logic; + signal baSprite37 : std_logic; + +-- Memory refresh cycles + signal refreshCounter : unsigned(7 downto 0); + +-- User registers + signal MX : MXdef; -- Sprite X + signal MY : MYdef; -- Sprite Y + signal ME : unsigned(7 downto 0); -- Sprite enable + signal MXE : unsigned(7 downto 0); -- Sprite X expansion + signal MYE : unsigned(7 downto 0); -- Sprite Y expansion + signal MPRIO : unsigned(7 downto 0); -- Sprite priority + signal MC : unsigned(7 downto 0); -- sprite multi color + + -- !!! Krestage 3 hacks + signal MCDelay : unsigned(7 downto 0); -- sprite multi color + + -- mode + signal BMM: std_logic; -- Bitmap mode + signal ECM: std_logic; -- Extended color mode + signal MCM: std_logic; -- Multi color mode + signal DEN: std_logic; -- DMA enable + signal RSEL: std_logic; -- Visible rows selection (24/25) + signal CSEL: std_logic; -- Visible columns selection (38/40) + + signal RES: std_logic; + + signal VM: unsigned(13 downto 10); + signal CB: unsigned(13 downto 11); + + signal EC : ColorDef; -- border color + signal B0C : ColorDef; -- background color 0 + signal B1C : ColorDef; -- background color 1 + signal B2C : ColorDef; -- background color 2 + signal B3C : ColorDef; -- background color 3 + signal MM0 : ColorDef; -- sprite multicolor 0 + signal MM1 : ColorDef; -- sprite multicolor 1 + signal spriteColors: spriteColorsDef; + +-- borders and blanking + signal LRBorder: std_logic; + signal TBBorder: std_logic; + signal hBlack: std_logic; + signal vBlanking : std_logic; + signal hBlanking : std_logic; + signal xscroll: unsigned(2 downto 0); + signal yscroll: unsigned(2 downto 0); + signal rasterCmp : unsigned(8 downto 0); + +-- Address generator + signal vicAddrReg : unsigned(13 downto 0); + signal vicAddrLoc : unsigned(13 downto 0); + +-- Address counters + signal ColCounter: unsigned(9 downto 0) := (others => '0'); + signal ColRestart: unsigned(9 downto 0) := (others => '0'); + signal RowCounter: unsigned(2 downto 0) := (others => '0'); + +-- IRQ Registers + signal IRST: std_logic := '0'; + signal ERST: std_logic := '0'; + signal IMBC: std_logic := '0'; + signal EMBC: std_logic := '0'; + signal IMMC: std_logic := '0'; + signal EMMC: std_logic := '0'; + signal ILP: std_logic := '0'; + signal ELP: std_logic := '0'; + signal IRQ: std_logic; + +-- Collision detection registers + signal M2M: unsigned(7 downto 0); -- Sprite to sprite collision + signal M2D: unsigned(7 downto 0); -- Sprite to character collision + signal M2Mhit : std_logic; + signal M2Dhit : std_logic; + +-- Raster counters + signal rasterX : unsigned(9 downto 0) := (others => '0'); + signal rasterY : unsigned(8 downto 0) := (others => '0'); + +-- Light pen + signal lightPenHit: std_logic; + signal lpX : unsigned(7 downto 0); + signal lpY : unsigned(7 downto 0); + +-- IRQ Resets + signal resetLightPenIrq: std_logic; + signal resetIMMC : std_logic; + signal resetIMBC : std_logic; + signal resetRasterIrq : std_logic; + +-- Character generation + signal charStore: charStoreDef; + signal nextChar : unsigned(11 downto 0); + -- Char/Pixels just coming from memory + signal readChar : unsigned(11 downto 0); + signal readPixels : unsigned(7 downto 0); + -- Char/Pixels pair waiting to be shifted + signal waitingChar : unsigned(11 downto 0); + signal waitingPixels : unsigned(7 downto 0); + -- Stores colorinfo and the Pixels that are currently in shift register + signal shiftingChar : unsigned(11 downto 0); + signal shiftingPixels : unsigned(7 downto 0); + signal shifting_ff : std_logic; -- Multicolor shift-regiter status bit. + +-- Sprite work registers + signal MPtr : unsigned(7 downto 0); -- sprite base pointer + signal MPixels : MPixelsDef; -- Sprite 24 bit shift register + signal MActive : MFlags; -- Sprite is active (derived from MCnt) + signal MCnt : MCntDef; + signal MXE_ff : unsigned(7 downto 0); -- Sprite X expansion flipflop + signal MYE_ff : unsigned(7 downto 0); -- Sprite Y expansion flipflop + signal MC_ff : unsigned(7 downto 0); -- controls sprite shift-register in multicolor + signal MShift : MFlags; -- Sprite is shifting + signal MCurrentPixel : MCurrentPixelDef; + +-- Current colors and pixels + signal pixelColor: ColorDef; + signal pixelBgFlag: std_logic; -- For collision detection + signal pixelDelay: pixelColorStoreDef; + +-- Read/Write lines + signal myWr : std_logic; + signal myRd : std_logic; + +begin +-- ----------------------------------------------------------------------- +-- Ouput signals +-- ----------------------------------------------------------------------- + ba <= baLoc; + vicAddr <= vicAddrReg when registeredAddress else vicAddrLoc; + hSync <= hBlanking; + vSync <= vBlanking; + irq_n <= not IRQ; + +-- ----------------------------------------------------------------------- +-- chip-select signals +-- ----------------------------------------------------------------------- + myWr <= cs and we; + myRd <= cs and rd; + +-- ----------------------------------------------------------------------- +-- debug signals +-- ----------------------------------------------------------------------- + debugX <= rasterX; + debugY <= rasterY; + +-- ----------------------------------------------------------------------- +-- Badline condition +-- ----------------------------------------------------------------------- + process(rasterY, yscroll, rasterEnable) + begin + badLine <= false; + if (rasterY(2 downto 0) = yscroll) + and (rasterEnable = '1') then + badLine <= true; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- BA=low counter +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if baLoc = '0' then + if phi = '0' + and enaData = '1' + and baCnt(2) = '0' then + baCnt <= baCnt + 1; + end if; + else + baCnt <= (others => '0'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Calculate lastLineFlag +-- ----------------------------------------------------------------------- + process(clk) + variable rasterLines : integer range 0 to 312; + begin + if rising_edge(clk) then + lastLineFlag <= false; + + rasterLines := 311; -- PAL + if mode6567old = '1' then + rasterLines := 261; -- NTSC (R7 and earlier have 262 lines) + end if; + if mode6567R8 = '1' then + rasterLines := 262; -- NTSC (R8 and newer have 263 lines) + end if; + if rasterY = rasterLines then + lastLineFlag <= true; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- State machine +-- ----------------------------------------------------------------------- +vicStateMachine: process(clk) + begin + if rising_edge(clk) then + if enaData = '1' + and baSync = '0' then + if phi = '0' then + case vicCycle is + when cycleRefresh1 => + vicCycle <= cycleRefresh2; + if ((mode6567old or mode6567R8) = '1') then + vicCycle <= cycleIdle1; + end if; + when cycleIdle1 => vicCycle <= cycleRefresh2; + when cycleRefresh2 => vicCycle <= cycleRefresh3; + when cycleRefresh3 => vicCycle <= cycleRefresh4; + when cycleRefresh4 => vicCycle <= cycleRefresh5; -- X=0..7 on this cycle + when cycleRefresh5 => vicCycle <= cycleChar; + when cycleChar => + if ((mode6569 = '1') and rasterX(9 downto 3) = "0100111") -- PAL + or ((mode6567old = '1') and rasterX(9 downto 3) = "0100111") -- Old NTSC + or ((mode6567R8 = '1') and rasterX(9 downto 3) = "0101000") -- New NTSC + or ((mode6572 = '1') and rasterX(9 downto 3) = "0101000") then -- PAL-N + vicCycle <= cycleCalcSprites; + end if; + when cycleCalcSprites => vicCycle <= cycleSpriteBa1; + when cycleSpriteBa1 => vicCycle <= cycleSpriteBa2; + when cycleSpriteBa2 => vicCycle <= cycleSpriteBa3; + when others => + null; + end case; + else + case vicCycle is + when cycleSpriteBa3 => vicCycle <= cycleSpriteA; + when cycleSpriteA => + vicCycle <= cycleSpriteB; + when cycleSpriteB => + vicCycle <= cycleSpriteA; + if sprite = 7 then + vicCycle <= cycleRefresh1; + end if; + when others => + null; + end case; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Iterate through all sprites. +-- Only used when state-machine above is in any sprite cycles. +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '1' + and enaData = '1' + and vicCycle = cycleSpriteB + and baSync = '0' then + sprite <= sprite + 1; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Address generator +-- ----------------------------------------------------------------------- + process(phi, vicCycle, sprite, shiftChars, idle, + VM, CB, ECM, BMM, nextChar, colCounter, rowCounter, MPtr, MCnt) + begin + -- + -- Default case ($3FFF fetches) + vicAddrLoc <= (others => '1'); + if (idle = '0') + and shiftChars then + if BMM = '1' then + vicAddrLoc <= CB(13) & colCounter & rowCounter; + else + vicAddrLoc <= CB & nextChar(7 downto 0) & rowCounter; + end if; + end if; + if ECM = '1' then + vicAddrLoc(10 downto 9) <= "00"; + end if; + + case vicCycle is + when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => + if emulateRefresh then + vicAddrLoc <= "111111" & refreshCounter; + else + vicAddrLoc <= (others => '-'); + end if; + when cycleSpriteBa1 | cycleSpriteBa2 | cycleSpriteBa3 => + vicAddrLoc <= (others => '1'); + when cycleSpriteA => + vicAddrLoc <= VM & "1111111" & sprite; + if phi = '1' then + vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + end if; + when cycleSpriteB => + vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + when others => + if phi = '1' then + vicAddrLoc <= VM & colCounter; + end if; + end case; + end process; + + -- Registered address + process(clk) + begin + if rising_edge(clk) then + vicAddrReg <= vicAddrLoc; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Character storage +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if enaData = '1' + and shiftChars + and phi = '1' then + if badLine then + nextChar(7 downto 0) <= datai; + nextChar(11 downto 8) <= diColor; + else + nextChar <= charStore(38); + end if; + charStore <= charStore(37 downto 0) & nextChar; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite base pointer (MPtr) +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' + and enaData = '1' + and vicCycle = cycleSpriteA then + MPtr <= (others => '1'); + if MActive(to_integer(sprite)) then + MPtr <= datai; + end if; + + -- If refresh counter is not emulated we don't care about + -- MPtr having the correct value in idle state. + if not emulateRefresh then + MPtr <= datai; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Refresh counter +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + vicRefresh <= '0'; + case vicCycle is + when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => + vicRefresh <= '1'; + if phi = '0' + and enaData = '1' + and baSync = '0' then + refreshCounter <= refreshCounter - 1; + end if; + when others => + null; + end case; + if lastLineFlag then + refreshCounter <= (others => '1'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Generate Raster Enable +-- ----------------------------------------------------------------------- + process(clk) + begin + -- Enable screen and character display. + -- This is only possible in line 48 on the VIC-II. + -- On other lines any DEN changes are ignored. + if rising_edge(clk) then + if (rasterY = 48) and (DEN = '1') then + rasterEnable <= '1'; + end if; + if (rasterY = 248) then + rasterEnable <= '0'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- BA generator (Text/Bitmap) +-- ----------------------------------------------------------------------- +-- +-- For Text/Bitmap BA goes low 3 cycles before real access. So BA starts +-- going low during refresh2 state. See diagram below for timing: +-- +-- X 0 0 0 0 0 +-- 0 0 0 0 1 +-- 0 4 8 C 0 +-- +-- phi ___ ___ ___ ___ ___ ___ ___ ___... +-- ___ ___ ___ ___ ___ ___ ___ ... +-- +-- | | | | | | |... +-- rfr2 rfr3 rfr4 rfr5 char1 char2 char3 +-- +-- BA _______ +-- \\\_______________________________________ +-- | 1 | 2 | 3 | +-- +-- BACnt 000 001 | 010 | 011 | 100 100 100 ... +-- +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' then + baChars <= '1'; + case vicCycle is + when cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => + if badLine then + baChars <= '0'; + end if; + when others => + if rasterX(9 downto 3) < "0101000" + and badLine then + baChars <= '0'; + end if; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- BA generator (Sprites) +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' then + if sprite = 1 then + baSprite04 <= '1'; + end if; + if sprite = 2 then + baSprite15 <= '1'; + end if; + if sprite = 3 then + baSprite26 <= '1'; + end if; + if sprite = 4 then + baSprite37 <= '1'; + end if; + if sprite = 5 then + baSprite04 <= '1'; + end if; + if sprite = 6 then + baSprite15 <= '1'; + end if; + if sprite = 7 then + baSprite26 <= '1'; + end if; + if vicCycle = cycleRefresh1 then + baSprite37 <= '1'; + end if; + + if MActive(0) and (vicCycle = cycleCalcSprites) then + baSprite04 <= '0'; + end if; + if MActive(1) and (vicCycle = cycleSpriteBa2) then + baSprite15 <= '0'; + end if; + if MActive(2) and (vicCycle = cycleSpriteB) and (sprite = 0) then + baSprite26 <= '0'; + end if; + if MActive(3) and (vicCycle = cycleSpriteB) and (sprite = 1) then + baSprite37 <= '0'; + end if; + if MActive(4) and (vicCycle = cycleSpriteB) and (sprite = 2) then + baSprite04 <= '0'; + end if; + if MActive(5) and (vicCycle = cycleSpriteB) and (sprite = 3) then + baSprite15 <= '0'; + end if; + if MActive(6) and (vicCycle = cycleSpriteB) and (sprite = 4) then + baSprite26 <= '0'; + end if; + if MActive(7) and (vicCycle = cycleSpriteB) and (sprite = 5) then + baSprite37 <= '0'; + end if; + end if; + end if; + end process; + baLoc <= baChars and baSprite04 and baSprite15 and baSprite26 and baSprite37; + +-- ----------------------------------------------------------------------- +-- Address valid? +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + addrValid <= '0'; + if phi = '0' + or baCnt(2) = '1' then + addrValid <= '1'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Generate ShiftChars flag +-- ----------------------------------------------------------------------- + process(rasterX) + begin + shiftChars <= false; + if rasterX(9 downto 3) > "0000000" + and rasterX(9 downto 3) < "0101001" then + shiftChars <= true; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- RowCounter and ColCounter +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' + and enaData = '1' + and baSync = '0' then + if shiftChars + and idle = '0' then + colCounter <= colCounter + 1; + end if; + case vicCycle is + when cycleRefresh4 => + colCounter <= colRestart; + if badline then + rowCounter <= (others => '0'); + end if; + when cycleSpriteA => + if sprite = "000" then + if rowCounter = 7 then + colRestart <= colCounter; + idle <= '1'; + else + rowCounter <= rowCounter + 1; + end if; + if badline then + rowCounter <= rowCounter + 1; + end if; + end if; + when others => + null; + end case; + if lastLineFlag then + -- Reset column counter outside visible range. + colRestart <= (others => '0'); + end if; + + -- Set display mode (leave idle-mode) as soon as + -- there is a badline condition. + if badline then + idle <= '0'; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- X/Y Raster counter +-- ----------------------------------------------------------------------- +rasterCounters: process(clk) + begin + if rising_edge(clk) then + if enaPixel = '1' then + rasterX(2 downto 0) <= rasterX(2 downto 0) + 1; + end if; + if phi = '0' + and enaData = '1' + and baSync = '0' then + rasterX(9 downto 3) <= rasterX(9 downto 3) + 1; + rasterX(2 downto 0) <= (others => '0'); + if vicCycle = cycleRefresh4 then + rasterX <= (others => '0'); + end if; + end if; + if phi = '1' + and enaData = '1' + and baSync = '0' then + beyondFrameFlag <= false; + if (vicCycle = cycleSpriteB) + and (sprite = 2) then + rasterY <= rasterY + 1; + beyondFrameFlag <= lastLineFlag; + end if; + if beyondFrameFlag then + rasterY <= (others => '0'); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Raster IRQ +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '1' + and enaData = '1' + and baSync = '0' + and (vicCycle = cycleSpriteB) + and (sprite = 2) then + rasterIrqDone <= '0'; + end if; + if resetRasterIrq = '1' then + IRST <= '0'; + end if; + if (rasterIrqDone = '0') + and (rasterY = rasterCmp) then + rasterIrqDone <= '1'; + IRST <= '1'; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Light pen +-- ----------------------------------------------------------------------- +-- On a negative edge on the LP input, the current position of the raster beam +-- is latched in the registers LPX ($d013) and LPY ($d014). LPX contains the +-- upper 8 bits (of 9) of the X position and LPY the lower 8 bits (likewise of +-- 9) of the Y position. So the horizontal resolution of the light pen is +-- limited to 2 pixels. + +-- Only one negative edge on LP is recognized per frame. If multiple edges +-- occur on LP, all following ones are ignored. The trigger is not released +-- until the next vertical blanking interval. +-- ----------------------------------------------------------------------- +lightPen: process(clk) + begin + if rising_edge(clk) then + if emulateLightpen then + if resetLightPenIrq = '1' then + -- Reset light pen interrupt + ILP <= '0'; + end if; + if lastLineFlag then + -- Reset lightpen state at beginning of frame + lightPenHit <= '0'; + elsif (lightPenHit = '0') and (lp_n = '0') then + -- One hit/frame + lightPenHit <= '1'; + -- Toggle Interrupt + ILP <= '1'; + -- Store position of beam + lpx <= rasterX(8 downto 1); + lpy <= rasterY(7 downto 0); + end if; + else + ILP <= '0'; + lpx <= (others => '1'); + lpy <= (others => '1'); + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- VSync +-- ----------------------------------------------------------------------- +doVBlanking: process(clk, mode6569, mode6567old, mode6567R8) + variable rasterBlank : integer range 0 to 300; + begin + rasterBlank := 300; + if (mode6567old or mode6567R8) = '1' then + rasterBlank := 12; + end if; + if rising_edge(clk) then + vBlanking <= '0'; + if rasterY = rasterBlank then + vBlanking <= '1'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- HSync +-- ----------------------------------------------------------------------- +doHBlanking: process(clk) + begin + if rising_edge(clk) then + if sprite = 3 then + hBlack <= '1'; + end if; + if vicCycle = cycleRefresh1 then + hBlack <= '0'; + end if; + if sprite = 3 then -- dar 5 then + hBlanking <= '1'; + else + hBlanking <= '0'; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Borders +-- ----------------------------------------------------------------------- +calcBorders: process(clk) + variable newTBBorder: std_logic; + begin + if rising_edge(clk) then + if enaPixel = '1' then + -- + -- Calc top/bottom border + newTBBorder := TBBorder; +-- if (rasterY = 55) and (RSEL = '0') and (rasterEnable = '1') then + if (rasterY = 55) and (rasterEnable = '1') then + newTBBorder := '0'; + end if; + if (rasterY = 51) and (RSEL = '1') and (rasterEnable = '1') then + newTBBorder := '0'; + end if; + if (rasterY = 247) and (RSEL = '0') then + newTBBorder := '1'; + end if; + if (rasterY = 251) and (RSEL = '1') then + newTBBorder := '1'; + end if; + + -- + -- Calc left/right border + if (rasterX = (31+1)) and (CSEL = '0') then + LRBorder <= newTBBorder; + TBBorder <= newTBBorder; + end if; + if (rasterX = (24+1)) and (CSEL = '1') then + LRBorder <= newTBBorder; + TBBorder <= newTBBorder; + end if; + if (rasterX = (335+1)) and (CSEL = '0') then + LRBorder <= '1'; + end if; + if (rasterX = (344+1)) and (CSEL = '1') then + LRBorder <= '1'; + end if; + end if; + end if; + end process; + + +-- ----------------------------------------------------------------------- +-- Pixel generator for Text/Bitmap screen +-- ----------------------------------------------------------------------- +calcBitmap: process(clk) + variable multiColor : std_logic; + begin + if rising_edge(clk) then + if enaPixel = '1' then + -- + -- Toggle flipflop for multicolor 2-bits shift. + shifting_ff <= not shifting_ff; + + -- + -- Multicolor mode is active with MCM, but for character + -- mode it depends on bit3 of color ram too. + multiColor := MCM and (BMM or ECM or shiftingChar(11)); + + -- + -- Reload shift register when xscroll=rasterX + -- otherwise shift pixels + if xscroll = rasterX(2 downto 0) then + shifting_ff <= '0'; + shiftingChar <= waitingChar; + shiftingPixels <= waitingPixels; + elsif multiColor = '0' then + shiftingPixels <= shiftingPixels(6 downto 0) & '0'; + elsif shifting_ff = '1' then + shiftingPixels <= shiftingPixels(5 downto 0) & "00"; + end if; + + -- + -- Calculate if pixel is in foreground or background + pixelBgFlag <= shiftingPixels(7); + + -- + -- Calculate color of next pixel + pixelColor <= B0C; + if (BMM = '0') and (ECM='0') then + if (multiColor = '0') then + -- normal character mode + if shiftingPixels(7) = '1' then + pixelColor <= shiftingChar(11 downto 8); + end if; + else + -- multi-color character mode + case shiftingPixels(7 downto 6) is + when "01" => pixelColor <= B1C; + when "10" => pixelColor <= B2C; + when "11" => pixelColor <= '0' & shiftingChar(10 downto 8); + when others => null; + end case; + end if; + elsif (MCM = '0') and (BMM = '0') and (ECM='1') then + -- extended-color character mode + -- multiple background colors but only 64 characters + if shiftingPixels(7) = '1' then + pixelColor <= shiftingChar(11 downto 8); + else + case shiftingChar(7 downto 6) is + when "01" => pixelColor <= B1C; + when "10" => pixelColor <= B2C; + when "11" => pixelColor <= B3C; + when others => null; + end case; + end if; + elsif emulateGraphics and (MCM = '0') and (BMM = '1') and (ECM='0') then + -- highres bitmap mode + if shiftingPixels(7) = '1' then + pixelColor <= shiftingChar(7 downto 4); + else + pixelColor <= shiftingChar(3 downto 0); + end if; + elsif emulateGraphics and (MCM = '1') and (BMM = '1') and (ECM='0') then + -- Multi-color bitmap mode + case shiftingPixels(7 downto 6) is + when "01" => pixelColor <= shiftingChar(7 downto 4); + when "10" => pixelColor <= shiftingChar(3 downto 0); + when "11" => pixelColor <= shiftingChar(11 downto 8); + when others => null; + end case; + else + -- illegal display mode, the output is black + pixelColor <= "0000"; + end if; + end if; + + -- + -- Store fetched pixels, until current pixels are displayed + -- and shift-register is empty. + if enaData = '1' + and phi = '0' then + readPixels <= (others => '0'); + if shiftChars then + readPixels <= datai; + readChar <= (others => '0'); + if idle = '0' then + readChar <= nextChar; + end if; + end if; + -- Store the characters until shiftregister is empty + waitingPixels <= readPixels; + waitingChar <= readChar; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Which sprites are active? +-- ----------------------------------------------------------------------- + process(MCnt) + begin + for i in 0 to 7 loop + MActive(i) <= false; + if MCnt(i) /= 63 then + MActive(i) <= true; + end if; + end loop; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite byte counter +-- Y expansion flipflop +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '0' + and enaData = '1' then + case vicCycle is + when cycleRefresh5 => + for i in 0 to 7 loop + MYE_ff(i) <= not MYE_ff(i); + if MActive(i) then + if MYE_ff(i) = MYE(i) then + MCnt(i) <= MCnt(i) + 1; + else + MCnt(i) <= MCnt(i) - 2; + end if; + end if; + end loop; + when others => + null; + end case; + end if; + for i in 0 to 7 loop + if MYE(i) = '0' + or not MActive(i) then + MYE_ff(i) <= '0'; + end if; + end loop; + + -- + -- On cycleCalcSprite check for each inactive sprite if + -- there is a Y match. Reset MCnt if this is so. + -- + -- The RasterX counter is used here to multiplex the compare logic. + -- This saves a few logic cells in the FPGA. + if vicCycle = cycleCalcSprites then + if (not MActive(to_integer(RasterX(2 downto 0)))) + and (ME(to_integer(RasterX(2 downto 0))) = '1') + and (rasterY(7 downto 0) = MY(to_integer(RasterX(2 downto 0)))) then + MCnt(to_integer(RasterX(2 downto 0))) <= (others => '0'); + end if; + end if; + -- + -- Original non-multiplexed version +-- if vicCycle = cycleCalcSprites then +-- for i in 0 to 7 loop +-- if (not MActive(i)) +-- and (ME(i) = '1') +-- and (rasterY(7 downto 0) = MY(i)) then +-- MCnt(i) <= (others => '0'); +-- end if; +-- end loop; +-- end if; + + -- + -- Increment MCnt after fetching data. + if enaData = '1' then + if (vicCycle = cycleSpriteA and phi = '1') + or (vicCycle = cycleSpriteB and phi = '0') then + if MActive(to_integer(sprite)) then + MCnt(to_integer(sprite)) <= MCnt(to_integer(sprite)) + 1; + end if; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite pixel Shift register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if enaPixel = '1' then + -- Enable sprites on the correct X position + for i in 0 to 7 loop + if rasterX = MX(i) then + MShift(i) <= true; + end if; + end loop; + + -- Shift one pixel of the sprite from the shift register. + for i in 0 to 7 loop + if MShift(i) then + MXE_ff(i) <= (not MXE_ff(i)) and MXE(i); + if MXE_ff(i) = '0' then + MC_ff(i) <= (not MC_ff(i)) and MC(i); + if MC_ff(i) = '0' then + MCurrentPixel(i) <= MPixels(i)(23 downto 22); + end if; + MPixels(i) <= MPixels(i)(22 downto 0) & '0'; + end if; + else + MXE_ff(i) <= '0'; + MC_ff(i) <= '0'; + MCurrentPixel(i) <= "00"; + end if; + end loop; + end if; + + -- + -- Fill Sprite shift-register with new data. + if enaData = '1' then + if phi = '0' + and vicCycle = cycleSpriteA then + MShift(to_integer(sprite)) <= false; + end if; + + if Mactive(to_integer(sprite)) then + if phi = '0' then + case vicCycle is + when cycleSpriteB => + MPixels(to_integer(sprite)) <= MPixels(to_integer(sprite))(15 downto 0) & datai; + when others => null; + end case; + else + case vicCycle is + when cycleSpriteA | cycleSpriteB => + MPixels(to_integer(sprite)) <= MPixels(to_integer(sprite))(15 downto 0) & datai; + when others => null; + end case; + end if; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Video output +-- ----------------------------------------------------------------------- + process(clk) + variable myColor: unsigned(3 downto 0); + variable muxSprite : unsigned(2 downto 0); + variable muxColor : unsigned(1 downto 0); + -- 00 = pixels + -- 01 = MM0 + -- 10 = Sprite + -- 11 = MM1 + begin + if rising_edge(clk) then + muxColor := "00"; + muxSprite := (others => '-'); + for i in 7 downto 0 loop + if (MPRIO(i) = '0') or (pixelBgFlag = '0') then + if MC(i) = '1' then + if MCurrentPixel(i) /= "00" then + muxColor := MCurrentPixel(i); + muxSprite := to_unsigned(i, 3); + end if; + elsif MCurrentPixel(i)(1) = '1' then + muxColor := "10"; + muxSprite := to_unsigned(i, 3); + end if; + end if; + end loop; + + myColor := pixelColor; + case muxColor is + when "01" => myColor := MM0; + when "10" => myColor := spriteColors(to_integer(muxSprite)); + when "11" => myColor := MM1; + when others => + null; + end case; + + +-- myColor := pixelColor; +-- for i in 7 downto 0 loop +-- if (MPRIO(i) = '0') or (pixelBgFlag = '0') then +-- if MC(i) = '1' then +-- case MCurrentPixel(i) is +-- when "01" => myColor := MM0; +-- when "10" => myColor := spriteColors(i); +-- when "11" => myColor := MM1; +-- when others => null; +-- end case; +-- elsif MCurrentPixel(i)(1) = '1' then +-- myColor := spriteColors(i); +-- end if; +-- end if; +-- end loop; + + if enaPixel = '1' then + colorIndex <= myColor; + +-- Krestage 3 debugging routine +-- if (cs = '1' and aRegisters = "011100") then +-- colorIndex <= "1111"; +-- end if; + if (LRBorder = '1') or (TBBorder = '1') then + colorIndex <= EC; + end if; + if (hBlack = '1') then + colorIndex <= (others => '0'); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite to sprite collision +-- ----------------------------------------------------------------------- +spriteSpriteCollision: process(clk) + variable collision : unsigned(7 downto 0); + begin + if rising_edge(clk) then + if resetIMMC = '1' then + IMMC <= '0'; + end if; + + if (myRd = '1') + and (aRegisters = "011110") then + M2M <= (others => '0'); + M2Mhit <= '0'; + end if; + + for i in 0 to 7 loop + collision(i) := MCurrentPixel(i)(1); + end loop; + if (collision /= "00000000") + and (collision /= "00000001") + and (collision /= "00000010") + and (collision /= "00000100") + and (collision /= "00001000") + and (collision /= "00010000") + and (collision /= "00100000") + and (collision /= "01000000") + and (collision /= "10000000") + and (TBBorder = '0') then + M2M <= M2M or collision; + + -- Give collision interrupt but only once until clear of register + if M2Mhit = '0' then + IMMC <= '1'; + M2Mhit <= '1'; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Sprite to background collision +-- ----------------------------------------------------------------------- +spriteBackgroundCollision: process(clk) + begin + if rising_edge(clk) then + if resetIMBC = '1' then + IMBC <= '0'; + end if; + + if (myRd = '1') + and (aRegisters = "011111") then + M2D <= (others => '0'); + M2Dhit <= '0'; + end if; + + for i in 0 to 7 loop + if MCurrentPixel(i)(1) = '1' + and pixelBgFlag = '1' + and (TBBorder = '0') then + M2D(i) <= '1'; + + -- Give collision interrupt but only once until clear of register + if M2Dhit = '0' then + IMBC <= '1'; + M2Dhit <= '1'; + end if; + end if; + end loop; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Generate IRQ signal +-- ----------------------------------------------------------------------- + IRQ <= (ILP and ELP) or (IMMC and EMMC) or (IMBC and EMBC) or (IRST and ERST); + +-- ----------------------------------------------------------------------- +-- Krestage 3 hack +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if phi = '1' + and enaData = '1' then + MC <= MCDelay; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Write registers +-- ----------------------------------------------------------------------- +writeRegisters: process(clk) + begin + if rising_edge(clk) then + resetLightPenIrq <= '0'; + resetIMMC <= '0'; + resetIMBC <= '0'; + resetRasterIrq <= '0'; + + -- + -- write to registers + if(reset = '1') then + MX(0) <= (others => '0'); + MX(1) <= (others => '0'); + MX(2) <= (others => '0'); + MX(3) <= (others => '0'); + MX(4) <= (others => '0'); + MX(5) <= (others => '0'); + MX(6) <= (others => '0'); + MX(7) <= (others => '0'); + rasterCmp <= (others => '0'); + ECM <= '0'; + BMM <= '0'; + DEN <= '0'; + RSEL <= '0'; + yscroll <= (others => '0'); + ME <= (others => '0'); + RES <= '0'; + MCM <= '0'; + CSEL <= '0'; + xscroll <= (others => '0'); + MYE <= (others => '0'); + VM <= (others => '0'); + CB <= (others => '0'); + resetLightPenIrq <= '0'; + resetIMMC <= '0'; + resetIMBC <= '0'; + resetRasterIrq <= '0'; + ELP <= '0'; + EMMC <= '0'; + EMBC <= '0'; + ERST <= '0'; + MPRIO <= (others => '0'); + MCDelay <= (others => '0'); + MXE <= (others => '0'); + EC <= (others => '0'); + B0C <= (others => '0'); + B1C <= (others => '0'); + B2C <=(others => '0'); + B3C <= (others => '0'); + MM0 <= (others => '0'); + MM1 <= (others => '0'); + spriteColors(0) <= (others => '0'); + spriteColors(1) <= (others => '0'); + spriteColors(2) <= (others => '0'); + spriteColors(3) <= (others => '0'); + spriteColors(4) <= (others => '0'); + spriteColors(5) <= (others => '0'); + spriteColors(6) <= (others => '0'); + spriteColors(7) <= (others => '0'); + + elsif (myWr = '1') then + case aRegisters is + when "000000" => MX(0)(7 downto 0) <= diRegisters; + when "000001" => MY(0) <= diRegisters; + when "000010" => MX(1)(7 downto 0) <= diRegisters; + when "000011" => MY(1) <= diRegisters; + when "000100" => MX(2)(7 downto 0) <= diRegisters; + when "000101" => MY(2) <= diRegisters; + when "000110" => MX(3)(7 downto 0) <= diRegisters; + when "000111" => MY(3) <= diRegisters; + when "001000" => MX(4)(7 downto 0) <= diRegisters; + when "001001" => MY(4) <= diRegisters; + when "001010" => MX(5)(7 downto 0) <= diRegisters; + when "001011" => MY(5) <= diRegisters; + when "001100" => MX(6)(7 downto 0) <= diRegisters; + when "001101" => MY(6) <= diRegisters; + when "001110" => MX(7)(7 downto 0) <= diRegisters; + when "001111" => MY(7) <= diRegisters; + when "010000" => + MX(0)(8) <= diRegisters(0); + MX(1)(8) <= diRegisters(1); + MX(2)(8) <= diRegisters(2); + MX(3)(8) <= diRegisters(3); + MX(4)(8) <= diRegisters(4); + MX(5)(8) <= diRegisters(5); + MX(6)(8) <= diRegisters(6); + MX(7)(8) <= diRegisters(7); + when "010001" => + rasterCmp(8) <= diRegisters(7); + ECM <= diRegisters(6); + BMM <= diRegisters(5); + DEN <= diRegisters(4); + RSEL <= diRegisters(3); + yscroll <= diRegisters(2 downto 0); + when "010010" => + rasterCmp(7 downto 0) <= diRegisters; + when "010101" => + ME <= diRegisters; + when "010110" => + RES <= diRegisters(5); + MCM <= diRegisters(4); + CSEL <= diRegisters(3); + xscroll <= diRegisters(2 downto 0); + + when "010111" => MYE <= diRegisters; + when "011000" => + VM <= diRegisters(7 downto 4); + CB <= diRegisters(3 downto 1); + when "011001" => + resetLightPenIrq <= diRegisters(3); + resetIMMC <= diRegisters(2); + resetIMBC <= diRegisters(1); + resetRasterIrq <= diRegisters(0); + when "011010" => + ELP <= diRegisters(3); + EMMC <= diRegisters(2); + EMBC <= diRegisters(1); + ERST <= diRegisters(0); + when "011011" => MPRIO <= diRegisters; + when "011100" => + -- MC <= diRegisters; + MCDelay <= diRegisters; -- !!! Krestage 3 hack + when "011101" => MXE <= diRegisters; + when "100000" => EC <= diRegisters(3 downto 0); + when "100001" => B0C <= diRegisters(3 downto 0); + when "100010" => B1C <= diRegisters(3 downto 0); + when "100011" => B2C <= diRegisters(3 downto 0); + when "100100" => B3C <= diRegisters(3 downto 0); + when "100101" => MM0 <= diRegisters(3 downto 0); + when "100110" => MM1 <= diRegisters(3 downto 0); + when "100111" => spriteColors(0) <= diRegisters(3 downto 0); + when "101000" => spriteColors(1) <= diRegisters(3 downto 0); + when "101001" => spriteColors(2) <= diRegisters(3 downto 0); + when "101010" => spriteColors(3) <= diRegisters(3 downto 0); + when "101011" => spriteColors(4) <= diRegisters(3 downto 0); + when "101100" => spriteColors(5) <= diRegisters(3 downto 0); + when "101101" => spriteColors(6) <= diRegisters(3 downto 0); + when "101110" => spriteColors(7) <= diRegisters(3 downto 0); + when others => null; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Read registers +-- ----------------------------------------------------------------------- +readRegisters: process(clk) + begin + if rising_edge(clk) then + case aRegisters is + when "000000" => datao <= MX(0)(7 downto 0); + when "000001" => datao <= MY(0); + when "000010" => datao <= MX(1)(7 downto 0); + when "000011" => datao <= MY(1); + when "000100" => datao <= MX(2)(7 downto 0); + when "000101" => datao <= MY(2); + when "000110" => datao <= MX(3)(7 downto 0); + when "000111" => datao <= MY(3); + when "001000" => datao <= MX(4)(7 downto 0); + when "001001" => datao <= MY(4); + when "001010" => datao <= MX(5)(7 downto 0); + when "001011" => datao <= MY(5); + when "001100" => datao <= MX(6)(7 downto 0); + when "001101" => datao <= MY(6); + when "001110" => datao <= MX(7)(7 downto 0); + when "001111" => datao <= MY(7); + when "010000" => + datao <= MX(7)(8) & MX(6)(8) & MX(5)(8) & MX(4)(8) + & MX(3)(8) & MX(2)(8) & MX(1)(8) & MX(0)(8); + when "010001" => datao <= rasterY(8) & ECM & BMM & DEN & RSEL & yscroll; + when "010010" => datao <= rasterY(7 downto 0); + when "010011" => datao <= lpX; + when "010100" => datao <= lpY; + when "010101" => datao <= ME; + when "010110" => datao <= "11" & RES & MCM & CSEL & xscroll; + when "010111" => datao <= MYE; + when "011000" => datao <= VM & CB & '1'; + when "011001" => datao <= IRQ & "111" & ILP & IMMC & IMBC & IRST; + when "011010" => datao <= "1111" & ELP & EMMC & EMBC & ERST; + when "011011" => datao <= MPRIO; + when "011100" => datao <= MC; + when "011101" => datao <= MXE; + when "011110" => datao <= M2M; + when "011111" => datao <= M2D; + when "100000" => datao <= "1111" & EC; + when "100001" => datao <= "1111" & B0C; + when "100010" => datao <= "1111" & B1C; + when "100011" => datao <= "1111" & B2C; + when "100100" => datao <= "1111" & B3C; + when "100101" => datao <= "1111" & MM0; + when "100110" => datao <= "1111" & MM1; + when "100111" => datao <= "1111" & spriteColors(0); + when "101000" => datao <= "1111" & spriteColors(1); + when "101001" => datao <= "1111" & spriteColors(2); + when "101010" => datao <= "1111" & spriteColors(3); + when "101011" => datao <= "1111" & spriteColors(4); + when "101100" => datao <= "1111" & spriteColors(5); + when "101101" => datao <= "1111" & spriteColors(6); + when "101110" => datao <= "1111" & spriteColors(7); + when others => datao <= (others => '1'); + end case; + end if; + end process; +end architecture; diff --git a/Commodore MAX/rtl/vic_656x_e.vhd b/Commodore MAX/rtl/vic_656x_e.vhd new file mode 100644 index 00000000..7e42eacc --- /dev/null +++ b/Commodore MAX/rtl/vic_656x_e.vhd @@ -0,0 +1,73 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- ----------------------------------------------------------------------- +-- +-- VIC-II - Video Interface Chip no 2 +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity vic_656x is + generic ( + registeredAddress : boolean := false; + emulateRefresh : boolean := false; + emulateLightpen : boolean := false; + emulateGraphics : boolean := true + ); + port ( + clk: in std_logic; + -- phi = 0 is VIC cycle + -- phi = 1 is CPU cycle (only used by VIC when BA is low) + phi : in std_logic; + enaData : in std_logic; + enaPixel : in std_logic; + + baSync : in std_logic; + ba: out std_logic; + + mode6569 : in std_logic; -- PAL 63 cycles and 312 lines + mode6567old : in std_logic; -- old NTSC 64 cycles and 262 line + mode6567R8 : in std_logic; -- new NTSC 65 cycles and 263 line + mode6572 : in std_logic; -- PAL-N 65 cycles and 312 lines + + reset : in std_logic; + cs : in std_logic; + we : in std_logic; + rd : in std_logic; + lp_n : in std_logic; + + aRegisters: in unsigned(5 downto 0); + diRegisters: in unsigned(7 downto 0); + + datai: in unsigned(7 downto 0); + diColor: in unsigned(3 downto 0); + datao: out unsigned(7 downto 0); + + vicAddr: out unsigned(13 downto 0); + irq_n: out std_logic; + + -- Video output + hSync : out std_logic; + vSync : out std_logic; + colorIndex : out unsigned(3 downto 0); + + -- Debug outputs + debugX : out unsigned(9 downto 0); + debugY : out unsigned(8 downto 0); + vicRefresh : out std_logic; + addrValid : out std_logic + ); +end entity; + diff --git a/Commodore MAX/rtl/video_mixer.sv b/Commodore MAX/rtl/video_mixer.sv new file mode 100644 index 00000000..ec953e53 --- /dev/null +++ b/Commodore MAX/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd7, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/ace.qpf b/Jupiter Cantab - JupiterACE_MiST/ace.qpf new file mode 100644 index 00000000..1fa2938b --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/ace.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 23:59:05 March 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "23:59:05 March 16, 2017" + +# Revisions + +PROJECT_REVISION = "ace" diff --git a/Jupiter Cantab - JupiterACE_MiST/ace.qsf b/Jupiter Cantab - JupiterACE_MiST/ace.qsf new file mode 100644 index 00000000..05b2ee6b --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/ace.qsf @@ -0,0 +1,218 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 18:40:37 November 24, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ace_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/glue.v +set_global_assignment -name VERILOG_FILE rtl/T80/tv80n.v +set_global_assignment -name VERILOG_FILE rtl/T80/tv80_reg.v +set_global_assignment -name VERILOG_FILE rtl/T80/tv80_mcode.v +set_global_assignment -name VERILOG_FILE rtl/T80/tv80_core.v +set_global_assignment -name VERILOG_FILE rtl/T80/tv80_alu.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/ace_mist.sv +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v +set_global_assignment -name VERILOG_FILE rtl/jupiter_ace.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name VERILOG_FILE rtl/rom_ram.v +set_global_assignment -name VERILOG_FILE rtl/ps2_port.v +set_global_assignment -name VERILOG_FILE rtl/io_write_to_rom.v + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_46 -to UART_TX + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY ace_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# EDA Netlist Writer Assignments +# ============================== +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# start EDA_TOOL_SETTINGS(eda_simulation) +# --------------------------------------- + + # EDA Netlist Writer Assignments + # ============================== +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +# end EDA_TOOL_SETTINGS(eda_simulation) +# ------------------------------------- + +# ---------------------- +# start ENTITY(ace_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(ace_mist) +# -------------------- +set_global_assignment -name VERILOG_FILE rtl/sram.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Jupiter Cantab - JupiterACE_MiST/clean.bat b/Jupiter Cantab - JupiterACE_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v new file mode 100644 index 00000000..2f015e21 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v @@ -0,0 +1,442 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_alu (/*AUTOARG*/ + // Outputs + Q, F_Out, + // Inputs + Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input Arith16; + input Z16; + input [3:0] ALU_Op ; + input [5:0] IR; + input [1:0] ISet; + input [7:0] BusA; + input [7:0] BusB; + input [7:0] F_In; + output [7:0] Q; + output [7:0] F_Out; + reg [7:0] Q; + reg [7:0] F_Out; + + function [4:0] AddSub4; + input [3:0] A; + input [3:0] B; + input Sub; + input Carry_In; + begin + AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + function [3:0] AddSub3; + input [2:0] A; + input [2:0] B; + input Sub; + input Carry_In; + begin + AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + function [1:0] AddSub1; + input A; + input B; + input Sub; + input Carry_In; + begin + AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In; + end + endfunction // AddSub4 + + // AddSub variables (temporary signals) + reg UseCarry; + reg Carry7_v; + reg OverFlow_v; + reg HalfCarry_v; + reg Carry_v; + reg [7:0] Q_v; + + reg [7:0] BitMask; + + + always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) + begin + case (IR[5:3]) + 3'b000 : BitMask = 8'b00000001; + 3'b001 : BitMask = 8'b00000010; + 3'b010 : BitMask = 8'b00000100; + 3'b011 : BitMask = 8'b00001000; + 3'b100 : BitMask = 8'b00010000; + 3'b101 : BitMask = 8'b00100000; + 3'b110 : BitMask = 8'b01000000; + default: BitMask = 8'b10000000; + endcase // case(IR[5:3]) + + UseCarry = ~ ALU_Op[2] && ALU_Op[0]; + { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); + { Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); + { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); + OverFlow_v = Carry_v ^ Carry7_v; + end // always @ * + + reg [7:0] Q_t; + reg [8:0] DAA_Q; + + always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB + or Carry_v or F_In or HalfCarry_v or IR or ISet + or OverFlow_v or Q_v or Z16) + begin + Q_t = 8'hxx; + DAA_Q = {9{1'bx}}; + + F_Out = F_In; + case (ALU_Op) + 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : + begin + F_Out[Flag_N] = 1'b0; + F_Out[Flag_C] = 1'b0; + + case (ALU_Op[2:0]) + + 3'b000, 3'b001 : // ADD, ADC + begin + Q_t = Q_v; + F_Out[Flag_C] = Carry_v; + F_Out[Flag_H] = HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b010, 3'b011, 3'b111 : // SUB, SBC, CP + begin + Q_t = Q_v; + F_Out[Flag_N] = 1'b1; + F_Out[Flag_C] = ~ Carry_v; + F_Out[Flag_H] = ~ HalfCarry_v; + F_Out[Flag_P] = OverFlow_v; + end + + 3'b100 : // AND + begin + Q_t[7:0] = BusA & BusB; + F_Out[Flag_H] = 1'b1; + end + + 3'b101 : // XOR + begin + Q_t[7:0] = BusA ^ BusB; + F_Out[Flag_H] = 1'b0; + end + + default : // OR 3'b110 + begin + Q_t[7:0] = BusA | BusB; + F_Out[Flag_H] = 1'b0; + end + + endcase // case(ALU_OP[2:0]) + + if (ALU_Op[2:0] == 3'b111 ) + begin // CP + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + else + begin + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + end + + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + if (Z16 == 1'b1 ) + begin + F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC + end + end + else + begin + F_Out[Flag_Z] = 1'b0; + end // else: !if(Q_t[7:0] == 8'b00000000 ) + + F_Out[Flag_S] = Q_t[7]; + case (ALU_Op[2:0]) + 3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP + ; + + default : + F_Out[Flag_P] = ~(^Q_t); + endcase // case(ALU_Op[2:0]) + + if (Arith16 == 1'b1 ) + begin + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + F_Out[Flag_P] = F_In[Flag_P]; + end + end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 + + 4'b1100 : + begin + // DAA + F_Out[Flag_H] = F_In[Flag_H]; + F_Out[Flag_C] = F_In[Flag_C]; + DAA_Q[7:0] = BusA; + DAA_Q[8] = 1'b0; + if (F_In[Flag_N] == 1'b0 ) + begin + // After addition + // Alow > 9 || H == 1 + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if ((DAA_Q[3:0] > 9) ) + begin + F_Out[Flag_H] = 1'b1; + end + else + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q = DAA_Q + 6; + end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + + // new Ahigh > 9 || C == 1 + if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q + 96; // 0x60 + end + end + else + begin + // After subtraction + if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) + begin + if (DAA_Q[3:0] > 5 ) + begin + F_Out[Flag_H] = 1'b0; + end + DAA_Q[7:0] = DAA_Q[7:0] - 6; + end + if (BusA > 153 || F_In[Flag_C] == 1'b1 ) + begin + DAA_Q = DAA_Q - 352; // 0x160 + end + end // else: !if(F_In[Flag_N] == 1'b0 ) + + F_Out[Flag_X] = DAA_Q[3]; + F_Out[Flag_Y] = DAA_Q[5]; + F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; + Q_t = DAA_Q[7:0]; + + if (DAA_Q[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + + F_Out[Flag_S] = DAA_Q[7]; + F_Out[Flag_P] = ~ (^DAA_Q); + end // case: 4'b1100 + + 4'b1101, 4'b1110 : + begin + // RLD, RRD + Q_t[7:4] = BusA[7:4]; + if (ALU_Op[0] == 1'b1 ) + begin + Q_t[3:0] = BusB[7:4]; + end + else + begin + Q_t[3:0] = BusB[3:0]; + end + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_S] = Q_t[7]; + F_Out[Flag_P] = ~(^Q_t); + end // case: when 4'b1101, 4'b1110 + + 4'b1001 : + begin + // BIT + Q_t[7:0] = BusB & BitMask; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + F_Out[Flag_P] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + F_Out[Flag_P] = 1'b0; + end + F_Out[Flag_H] = 1'b1; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = 1'b0; + F_Out[Flag_Y] = 1'b0; + if (IR[2:0] != 3'b110 ) + begin + F_Out[Flag_X] = BusB[3]; + F_Out[Flag_Y] = BusB[5]; + end + end // case: when 4'b1001 + + 4'b1010 : + // SET + Q_t[7:0] = BusB | BitMask; + + 4'b1011 : + // RES + Q_t[7:0] = BusB & ~ BitMask; + + 4'b1000 : + begin + // ROT + case (IR[5:3]) + 3'b000 : // RLC + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = BusA[7]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b010 : // RL + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[7]; + end + + 3'b001 : // RRC + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[0]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b011 : // RR + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = F_In[Flag_C]; + F_Out[Flag_C] = BusA[0]; + end + + 3'b100 : // SLA + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b0; + F_Out[Flag_C] = BusA[7]; + end + + 3'b110 : // SLL (Undocumented) / SWAP + begin + if (Mode == 3 ) + begin + Q_t[7:4] = BusA[3:0]; + Q_t[3:0] = BusA[7:4]; + F_Out[Flag_C] = 1'b0; + end + else + begin + Q_t[7:1] = BusA[6:0]; + Q_t[0] = 1'b1; + F_Out[Flag_C] = BusA[7]; + end // else: !if(Mode == 3 ) + end // case: 3'b110 + + 3'b101 : // SRA + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = BusA[7]; + F_Out[Flag_C] = BusA[0]; + end + + default : // SRL + begin + Q_t[6:0] = BusA[7:1]; + Q_t[7] = 1'b0; + F_Out[Flag_C] = BusA[0]; + end + endcase // case(IR[5:3]) + + F_Out[Flag_H] = 1'b0; + F_Out[Flag_N] = 1'b0; + F_Out[Flag_X] = Q_t[3]; + F_Out[Flag_Y] = Q_t[5]; + F_Out[Flag_S] = Q_t[7]; + if (Q_t[7:0] == 8'b00000000 ) + begin + F_Out[Flag_Z] = 1'b1; + end + else + begin + F_Out[Flag_Z] = 1'b0; + end + F_Out[Flag_P] = ~(^Q_t); + + if (ISet == 2'b00 ) + begin + F_Out[Flag_P] = F_In[Flag_P]; + F_Out[Flag_S] = F_In[Flag_S]; + F_Out[Flag_Z] = F_In[Flag_Z]; + end + end // case: 4'b1000 + + + default : + ; + + endcase // case(ALU_Op) + + Q = Q_t; + end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + +endmodule // T80_ALU diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v new file mode 100644 index 00000000..af1483a1 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v @@ -0,0 +1,1351 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_core (/*AUTOARG*/ + // Outputs + m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc, ts, + intcycle_n, IntE, stop, + // Inputs + reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di + ); + // Beginning of automatic inputs (from unused autoinst inputs) + // End of automatics + + parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input reset_n; + input clk; + input cen; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output iorq; + output no_read; + output write; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] dinst; + input [7:0] di; + output [7:0] dout; + output [6:0] mc; + output [6:0] ts; + output intcycle_n; + output IntE; + output stop; + + reg m1_n; + reg iorq; + reg rfsh_n; + reg halt_n; + reg busak_n; + reg [15:0] A; + reg [7:0] dout; + reg [6:0] mc; + reg [6:0] ts; + reg intcycle_n; + reg IntE; + reg stop; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + + // Registers + reg [7:0] ACC, F; + reg [7:0] Ap, Fp; + reg [7:0] I; + reg [7:0] R; + reg [15:0] SP, PC; + reg [7:0] RegDIH; + reg [7:0] RegDIL; + wire [15:0] RegBusA; + wire [15:0] RegBusB; + wire [15:0] RegBusC; + reg [2:0] RegAddrA_r; + reg [2:0] RegAddrA; + reg [2:0] RegAddrB_r; + reg [2:0] RegAddrB; + reg [2:0] RegAddrC; + reg RegWEH; + reg RegWEL; + reg Alternate; + + // Help Registers + reg [15:0] TmpAddr; // Temporary address register + reg [7:0] IR; // Instruction register + reg [1:0] ISet; // Instruction set selector + reg [15:0] RegBusA_r; + + reg [15:0] ID16; + reg [7:0] Save_Mux; + + reg [6:0] tstate; + reg [6:0] mcycle; + reg last_mcycle, last_tstate; + reg IntE_FF1; + reg IntE_FF2; + reg Halt_FF; + reg BusReq_s; + reg BusAck; + reg ClkEn; + reg NMI_s; + reg INT_s; + reg [1:0] IStatus; + + reg [7:0] DI_Reg; + reg T_Res; + reg [1:0] XY_State; + reg [2:0] Pre_XY_F_M; + reg NextIs_XY_Fetch; + reg XY_Ind; + reg No_BTR; + reg BTR_r; + reg Auto_Wait; + reg Auto_Wait_t1; + reg Auto_Wait_t2; + reg IncDecZ; + + // ALU signals + reg [7:0] BusB; + reg [7:0] BusA; + wire [7:0] ALU_Q; + wire [7:0] F_Out; + + // Registered micro code outputs + reg [4:0] Read_To_Reg_r; + reg Arith16_r; + reg Z16_r; + reg [3:0] ALU_Op_r; + reg Save_ALU_r; + reg PreserveC_r; + reg [2:0] mcycles; + + // Micro code outputs + wire [2:0] mcycles_d; + wire [2:0] tstates; + reg IntCycle; + reg NMICycle; + wire Inc_PC; + wire Inc_WZ; + wire [3:0] IncDec_16; + wire [1:0] Prefix; + wire Read_To_Acc; + wire Read_To_Reg; + wire [3:0] Set_BusB_To; + wire [3:0] Set_BusA_To; + wire [3:0] ALU_Op; + wire Save_ALU; + wire PreserveC; + wire Arith16; + wire [2:0] Set_Addr_To; + wire Jump; + wire JumpE; + wire JumpXY; + wire Call; + wire RstP; + wire LDZ; + wire LDW; + wire LDSPHL; + wire iorq_i; + wire [2:0] Special_LD; + wire ExchangeDH; + wire ExchangeRp; + wire ExchangeAF; + wire ExchangeRS; + wire I_DJNZ; + wire I_CPL; + wire I_CCF; + wire I_SCF; + wire I_RETN; + wire I_BT; + wire I_BC; + wire I_BTR; + wire I_RLD; + wire I_RRD; + wire I_INRC; + wire SetDI; + wire SetEI; + wire [1:0] IMode; + wire Halt; + + reg [15:0] PC16; + reg [15:0] PC16_B; + reg [15:0] SP16, SP16_A, SP16_B; + reg [15:0] ID16_B; + reg Oldnmi_n; + + tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode + ( + .IR (IR), + .ISet (ISet), + .MCycle (mcycle), + .F (F), + .NMICycle (NMICycle), + .IntCycle (IntCycle), + .MCycles (mcycles_d), + .TStates (tstates), + .Prefix (Prefix), + .Inc_PC (Inc_PC), + .Inc_WZ (Inc_WZ), + .IncDec_16 (IncDec_16), + .Read_To_Acc (Read_To_Acc), + .Read_To_Reg (Read_To_Reg), + .Set_BusB_To (Set_BusB_To), + .Set_BusA_To (Set_BusA_To), + .ALU_Op (ALU_Op), + .Save_ALU (Save_ALU), + .PreserveC (PreserveC), + .Arith16 (Arith16), + .Set_Addr_To (Set_Addr_To), + .IORQ (iorq_i), + .Jump (Jump), + .JumpE (JumpE), + .JumpXY (JumpXY), + .Call (Call), + .RstP (RstP), + .LDZ (LDZ), + .LDW (LDW), + .LDSPHL (LDSPHL), + .Special_LD (Special_LD), + .ExchangeDH (ExchangeDH), + .ExchangeRp (ExchangeRp), + .ExchangeAF (ExchangeAF), + .ExchangeRS (ExchangeRS), + .I_DJNZ (I_DJNZ), + .I_CPL (I_CPL), + .I_CCF (I_CCF), + .I_SCF (I_SCF), + .I_RETN (I_RETN), + .I_BT (I_BT), + .I_BC (I_BC), + .I_BTR (I_BTR), + .I_RLD (I_RLD), + .I_RRD (I_RRD), + .I_INRC (I_INRC), + .SetDI (SetDI), + .SetEI (SetEI), + .IMode (IMode), + .Halt (Halt), + .NoRead (no_read), + .Write (write) + ); + + tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu + ( + .Arith16 (Arith16_r), + .Z16 (Z16_r), + .ALU_Op (ALU_Op_r), + .IR (IR[5:0]), + .ISet (ISet), + .BusA (BusA), + .BusB (BusB), + .F_In (F), + .Q (ALU_Q), + .F_Out (F_Out) + ); + + function [6:0] number_to_bitvec; + input [2:0] num; + begin + case (num) + 1 : number_to_bitvec = 7'b0000001; + 2 : number_to_bitvec = 7'b0000010; + 3 : number_to_bitvec = 7'b0000100; + 4 : number_to_bitvec = 7'b0001000; + 5 : number_to_bitvec = 7'b0010000; + 6 : number_to_bitvec = 7'b0100000; + 7 : number_to_bitvec = 7'b1000000; + default : number_to_bitvec = 7'bx; + endcase // case(num) + end + endfunction // number_to_bitvec + + always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates) + begin + case (mcycles) + 1 : last_mcycle = mcycle[0]; + 2 : last_mcycle = mcycle[1]; + 3 : last_mcycle = mcycle[2]; + 4 : last_mcycle = mcycle[3]; + 5 : last_mcycle = mcycle[4]; + 6 : last_mcycle = mcycle[5]; + 7 : last_mcycle = mcycle[6]; + default : last_mcycle = 1'bx; + endcase // case(mcycles) + + case (tstates) + 0 : last_tstate = tstate[0]; + 1 : last_tstate = tstate[1]; + 2 : last_tstate = tstate[2]; + 3 : last_tstate = tstate[3]; + 4 : last_tstate = tstate[4]; + 5 : last_tstate = tstate[5]; + 6 : last_tstate = tstate[6]; + default : last_tstate = 1'bx; + endcase + end // always @ (... + + + always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg + or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind + or XY_State or cen or last_tstate or mcycle) + begin + ClkEn = cen && ~ BusAck; + + if (last_tstate) + T_Res = 1'b1; + else T_Res = 1'b0; + + if (XY_State != 2'b00 && XY_Ind == 1'b0 && + ((Set_Addr_To == aXY) || + (mcycle[0] && IR == 8'b11001011) || + (mcycle[0] && IR == 8'b00110110))) + NextIs_XY_Fetch = 1'b1; + else + NextIs_XY_Fetch = 1'b0; + + if (ExchangeRp) + Save_Mux = BusB; + else if (!Save_ALU_r) + Save_Mux = DI_Reg; + else + Save_Mux = ALU_Q; + end // always @ * + + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + PC <= #1 0; // Program Counter + A <= #1 0; + TmpAddr <= #1 0; + IR <= #1 8'b00000000; + ISet <= #1 2'b00; + XY_State <= #1 2'b00; + IStatus <= #1 2'b00; + mcycles <= #1 3'b000; + dout <= #1 8'b00000000; + + ACC <= #1 8'hFF; + F <= #1 8'hFF; + Ap <= #1 8'hFF; + Fp <= #1 8'hFF; + I <= #1 0; + `ifdef TV80_REFRESH + R <= #1 0; + `endif + SP <= #1 16'hFFFF; + Alternate <= #1 1'b0; + + Read_To_Reg_r <= #1 5'b00000; + Arith16_r <= #1 1'b0; + BTR_r <= #1 1'b0; + Z16_r <= #1 1'b0; + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + PreserveC_r <= #1 1'b0; + XY_Ind <= #1 1'b0; + end + else + begin + + if (ClkEn == 1'b1 ) + begin + + ALU_Op_r <= #1 4'b0000; + Save_ALU_r <= #1 1'b0; + Read_To_Reg_r <= #1 5'b00000; + + mcycles <= #1 mcycles_d; + + if (IMode != 2'b11 ) + begin + IStatus <= #1 IMode; + end + + Arith16_r <= #1 Arith16; + PreserveC_r <= #1 PreserveC; + if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) + begin + Z16_r <= #1 1'b1; + end + else + begin + Z16_r <= #1 1'b0; + end + + if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) + begin + // mcycle == 1 && tstate == 1, 2, || 3 + if (tstate[2] && wait_n == 1'b1 ) + begin + `ifdef TV80_REFRESH + if (Mode < 2 ) + begin + A[7:0] <= #1 R; + A[15:8] <= #1 I; + R[6:0] <= #1 R[6:0] + 1; + end + `endif + if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) + begin + PC <= #1 PC16; + end + + if (IntCycle == 1'b1 && IStatus == 2'b01 ) + begin + IR <= #1 8'b11111111; + end + else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) + begin + IR <= #1 8'b00000000; + end + else + begin + IR <= #1 dinst; + end + + ISet <= #1 2'b00; + if (Prefix != 2'b00 ) + begin + if (Prefix == 2'b11 ) + begin + if (IR[5] == 1'b1 ) + begin + XY_State <= #1 2'b10; + end + else + begin + XY_State <= #1 2'b01; + end + end + else + begin + if (Prefix == 2'b10 ) + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + ISet <= #1 Prefix; + end + end + else + begin + XY_State <= #1 2'b00; + XY_Ind <= #1 1'b0; + end + end // if (tstate == 2 && wait_n == 1'b1 ) + + + end + else + begin + // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3) + + if (mcycle[5] ) + begin + XY_Ind <= #1 1'b1; + if (Prefix == 2'b01 ) + begin + ISet <= #1 2'b01; + end + end + + if (T_Res == 1'b1 ) + begin + BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR; + if (Jump == 1'b1 ) + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 DI_Reg; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else if (JumpXY == 1'b1 ) + begin + A <= #1 RegBusC; + PC <= #1 RegBusC; + end else if (Call == 1'b1 || RstP == 1'b1 ) + begin + A <= #1 TmpAddr; + PC <= #1 TmpAddr; + end + else if (last_mcycle && NMICycle == 1'b1 ) + begin + A <= #1 16'b0000000001100110; + PC <= #1 16'b0000000001100110; + end + else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) + begin + A[15:8] <= #1 I; + A[7:0] <= #1 TmpAddr[7:0]; + PC[15:8] <= #1 I; + PC[7:0] <= #1 TmpAddr[7:0]; + end + else + begin + case (Set_Addr_To) + aXY : + begin + if (XY_State == 2'b00 ) + begin + A <= #1 RegBusC; + end + else + begin + if (NextIs_XY_Fetch == 1'b1 ) + begin + A <= #1 PC; + end + else + begin + A <= #1 TmpAddr; + end + end // else: !if(XY_State == 2'b00 ) + end // case: aXY + + aIOA : + begin + if (Mode == 3 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + end + else if (Mode == 2 ) + begin + // Duplicate I/O address on 8080 + A[15:8] <= #1 DI_Reg; + end + else + begin + A[15:8] <= #1 ACC; + end + A[7:0] <= #1 DI_Reg; + end // case: aIOA + + + aSP : + begin + A <= #1 SP; + end + + aBC : + begin + if (Mode == 3 && iorq_i == 1'b1 ) + begin + // Memory map I/O on GBZ80 + A[15:8] <= #1 8'hFF; + A[7:0] <= #1 RegBusC[7:0]; + end + else + begin + A <= #1 RegBusC; + end + end // case: aBC + + aDE : + begin + A <= #1 RegBusC; + end + + aZI : + begin + if (Inc_WZ == 1'b1 ) + begin + A <= #1 TmpAddr + 1; + end + else + begin + A[15:8] <= #1 DI_Reg; + A[7:0] <= #1 TmpAddr[7:0]; + end + end // case: aZI + + default : + begin + A <= #1 PC; + end + endcase // case(Set_Addr_To) + + end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) + + + Save_ALU_r <= #1 Save_ALU; + ALU_Op_r <= #1 ALU_Op; + + if (I_CPL == 1'b1 ) + begin + // CPL + ACC <= #1 ~ ACC; + F[Flag_Y] <= #1 ~ ACC[5]; + F[Flag_H] <= #1 1'b1; + F[Flag_X] <= #1 ~ ACC[3]; + F[Flag_N] <= #1 1'b1; + end + if (I_CCF == 1'b1 ) + begin + // CCF + F[Flag_C] <= #1 ~ F[Flag_C]; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 F[Flag_C]; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + if (I_SCF == 1'b1 ) + begin + // SCF + F[Flag_C] <= #1 1'b1; + F[Flag_Y] <= #1 ACC[5]; + F[Flag_H] <= #1 1'b0; + F[Flag_X] <= #1 ACC[3]; + F[Flag_N] <= #1 1'b0; + end + end // if (T_Res == 1'b1 ) + + + if (tstate[2] && wait_n == 1'b1 ) + begin + if (ISet == 2'b01 && mcycle[6] ) + begin + IR <= #1 dinst; + end + if (JumpE == 1'b1 ) + begin + PC <= #1 PC16; + end + else if (Inc_PC == 1'b1 ) + begin + //PC <= #1 PC + 1; + PC <= #1 PC16; + end + if (BTR_r == 1'b1 ) + begin + //PC <= #1 PC - 2; + PC <= #1 PC16; + end + if (RstP == 1'b1 ) + begin + TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 }; + //TmpAddr <= #1 (others =>1'b0); + //TmpAddr[5:3] <= #1 IR[5:3]; + end + end + if (tstate[3] && mcycle[5] ) + begin + TmpAddr <= #1 SP16; + end + + if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) + begin + if (IncDec_16[2:0] == 3'b111 ) + begin + SP <= #1 SP16; + end + end + + if (LDSPHL == 1'b1 ) + begin + SP <= #1 RegBusC; + end + if (ExchangeAF == 1'b1 ) + begin + Ap <= #1 ACC; + ACC <= #1 Ap; + Fp <= #1 F; + F <= #1 Fp; + end + if (ExchangeRS == 1'b1 ) + begin + Alternate <= #1 ~ Alternate; + end + end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 ) + + + if (tstate[3] ) + begin + if (LDZ == 1'b1 ) + begin + TmpAddr[7:0] <= #1 DI_Reg; + end + if (LDW == 1'b1 ) + begin + TmpAddr[15:8] <= #1 DI_Reg; + end + + if (Special_LD[2] == 1'b1 ) + begin + case (Special_LD[1:0]) + 2'b00 : + begin + ACC <= #1 I; + F[Flag_P] <= #1 IntE_FF2; + end + + 2'b01 : + begin + ACC <= #1 R; + F[Flag_P] <= #1 IntE_FF2; + end + + 2'b10 : + I <= #1 ACC; + + `ifdef TV80_REFRESH + default : + R <= #1 ACC; + `else + default : ; + `endif + endcase + end + end // if (tstate == 3 ) + + + if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + begin + if (Mode == 3 ) + begin + F[6] <= #1 F_Out[6]; + F[5] <= #1 F_Out[5]; + F[7] <= #1 F_Out[7]; + if (PreserveC_r == 1'b0 ) + begin + F[4] <= #1 F_Out[4]; + end + end + else + begin + F[7:1] <= #1 F_Out[7:1]; + if (PreserveC_r == 1'b0 ) + begin + F[Flag_C] <= #1 F_Out[0]; + end + end + end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) + + if (T_Res == 1'b1 && I_INRC == 1'b1 ) + begin + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + if (DI_Reg[7:0] == 8'b00000000 ) + begin + F[Flag_Z] <= #1 1'b1; + end + else + begin + F[Flag_Z] <= #1 1'b0; + end + F[Flag_S] <= #1 DI_Reg[7]; + F[Flag_P] <= #1 ~ (^DI_Reg[7:0]); + end // if (T_Res == 1'b1 && I_INRC == 1'b1 ) + + + if (tstate[1] && Auto_Wait_t1 == 1'b0 ) + begin + dout <= #1 BusB; + if (I_RLD == 1'b1 ) + begin + dout[3:0] <= #1 BusA[3:0]; + dout[7:4] <= #1 BusB[3:0]; + end + if (I_RRD == 1'b1 ) + begin + dout[3:0] <= #1 BusB[7:4]; + dout[7:4] <= #1 BusA[3:0]; + end + end + + if (T_Res == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 Set_BusA_To; + Read_To_Reg_r[4] <= #1 Read_To_Reg; + if (Read_To_Acc == 1'b1 ) + begin + Read_To_Reg_r[3:0] <= #1 4'b0111; + Read_To_Reg_r[4] <= #1 1'b1; + end + end + + if (tstate[1] && I_BT == 1'b1 ) + begin + F[Flag_X] <= #1 ALU_Q[3]; + F[Flag_Y] <= #1 ALU_Q[1]; + F[Flag_H] <= #1 1'b0; + F[Flag_N] <= #1 1'b0; + end + if (I_BC == 1'b1 || I_BT == 1'b1 ) + begin + F[Flag_P] <= #1 IncDecZ; + end + + if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10111 : + ACC <= #1 Save_Mux; + 5'b10110 : + dout <= #1 Save_Mux; + 5'b11000 : + SP[7:0] <= #1 Save_Mux; + 5'b11001 : + SP[15:8] <= #1 Save_Mux; + 5'b11011 : + F <= #1 Save_Mux; + endcase + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + end // if (ClkEn == 1'b1 ) + end // else: !if(reset_n == 1'b0 ) + end + + + //------------------------------------------------------------------------- + // + // BC('), DE('), HL('), IX && IY + // + //------------------------------------------------------------------------- + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + // Bus A / Write + RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) + begin + RegAddrA_r <= #1 { XY_State[1], 2'b11 }; + end + + // Bus B + RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] }; + if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) + begin + RegAddrB_r <= #1 { XY_State[1], 2'b11 }; + end + + // Address from register + RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] }; + // Jump (HL), LD SP,HL + if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) + begin + RegAddrC <= #1 { Alternate, 2'b10 }; + end + if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) + begin + RegAddrC <= #1 { XY_State[1], 2'b11 }; + end + + if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) + begin + IncDecZ <= #1 F_Out[Flag_Z]; + end + if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) + begin + if (ID16 == 0 ) + begin + IncDecZ <= #1 1'b0; + end + else + begin + IncDecZ <= #1 1'b1; + end + end + + RegBusA_r <= #1 RegBusA; + end + + end // always @ (posedge clk) + + + always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16 + or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate) + begin + if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00) + RegAddrA = { Alternate, IncDec_16[1:0] }; + else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10) + RegAddrA = { XY_State[1], 2'b11 }; + else if (ExchangeDH == 1'b1 && tstate[3]) + RegAddrA = { Alternate, 2'b10 }; + else if (ExchangeDH == 1'b1 && tstate[4]) + RegAddrA = { Alternate, 2'b01 }; + else + RegAddrA = RegAddrA_r; + + if (ExchangeDH == 1'b1 && tstate[3]) + RegAddrB = { Alternate, 2'b01 }; + else + RegAddrB = RegAddrB_r; + end // always @ * + + + always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH + or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle + or tstate or wait_n) + begin + RegWEH = 1'b0; + RegWEL = 1'b0; + if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) || + (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) + begin + case (Read_To_Reg_r) + 5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 : + begin + RegWEH = ~ Read_To_Reg_r[0]; + RegWEL = Read_To_Reg_r[0]; + end + endcase // case(Read_To_Reg_r) + + end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||... + + + if (ExchangeDH == 1'b1 && (tstate[3] || tstate[4]) ) + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + + if (IncDec_16[2] == 1'b1 && ((tstate[2] && wait_n == 1'b1 && mcycle != 3'b001) || (tstate[3] && mcycle[0])) ) + begin + case (IncDec_16[1:0]) + 2'b00 , 2'b01 , 2'b10 : + begin + RegWEH = 1'b1; + RegWEL = 1'b1; + end + endcase + end + end // always @ * + + + always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r + or RegBusB or Save_Mux or mcycle or tstate) + begin + RegDIH = Save_Mux; + RegDIL = Save_Mux; + + if (ExchangeDH == 1'b1 && tstate[3] ) + begin + RegDIH = RegBusB[15:8]; + RegDIL = RegBusB[7:0]; + end + else if (ExchangeDH == 1'b1 && tstate[4] ) + begin + RegDIH = RegBusA_r[15:8]; + RegDIL = RegBusA_r[7:0]; + end + else if (IncDec_16[2] == 1'b1 && ((tstate[2] && mcycle != 3'b001) || (tstate[3] && mcycle[0])) ) + begin + RegDIH = ID16[15:8]; + RegDIL = ID16[7:0]; + end + end + + tv80_reg i_reg + ( + .clk (clk), + .CEN (ClkEn), + .WEH (RegWEH), + .WEL (RegWEL), + .AddrA (RegAddrA), + .AddrB (RegAddrB), + .AddrC (RegAddrC), + .DIH (RegDIH), + .DIL (RegDIL), + .DOAH (RegBusA[15:8]), + .DOAL (RegBusA[7:0]), + .DOBH (RegBusB[15:8]), + .DOBL (RegBusB[7:0]), + .DOCH (RegBusC[15:8]), + .DOCL (RegBusC[7:0]) + ); + + //------------------------------------------------------------------------- + // + // Buses + // + //------------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (ClkEn == 1'b1 ) + begin + case (Set_BusB_To) + 4'b0111 : + BusB <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusB_To[0] == 1'b1 ) + begin + BusB <= #1 RegBusB[7:0]; + end + else + begin + BusB <= #1 RegBusB[15:8]; + end + end + 4'b0110 : + BusB <= #1 DI_Reg; + 4'b1000 : + BusB <= #1 SP[7:0]; + 4'b1001 : + BusB <= #1 SP[15:8]; + 4'b1010 : + BusB <= #1 8'b00000001; + 4'b1011 : + BusB <= #1 F; + 4'b1100 : + BusB <= #1 PC[7:0]; + 4'b1101 : + BusB <= #1 PC[15:8]; + 4'b1110 : + BusB <= #1 8'b00000000; + default : + BusB <= #1 8'hxx; + endcase + + case (Set_BusA_To) + 4'b0111 : + BusA <= #1 ACC; + 4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 : + begin + if (Set_BusA_To[0] == 1'b1 ) + begin + BusA <= #1 RegBusA[7:0]; + end + else + begin + BusA <= #1 RegBusA[15:8]; + end + end + 4'b0110 : + BusA <= #1 DI_Reg; + 4'b1000 : + BusA <= #1 SP[7:0]; + 4'b1001 : + BusA <= #1 SP[15:8]; + 4'b1010 : + BusA <= #1 8'b00000000; + default : + BusB <= #1 8'hxx; + endcase + end + end + + //------------------------------------------------------------------------- + // + // Generate external control signals + // + //------------------------------------------------------------------------- +`ifdef TV80_REFRESH + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + rfsh_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) || tstate[3]) ) + begin + rfsh_n <= #1 1'b0; + end + else + begin + rfsh_n <= #1 1'b1; + end + end + end + end +`endif + + always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle + or IntE_FF1 or di or iorq_i or mcycle or tstate) + begin + mc = mcycle; + ts = tstate; + DI_Reg = di; + halt_n = ~ Halt_FF; + busak_n = ~ BusAck; + intcycle_n = ~ IntCycle; + IntE = IntE_FF1; + iorq = iorq_i; + stop = I_DJNZ; + end + + //----------------------------------------------------------------------- + // + // Syncronise inputs + // + //----------------------------------------------------------------------- + + always @ (posedge clk) + begin : sync_inputs + + if (reset_n == 1'b0 ) + begin + BusReq_s <= #1 1'b0; + INT_s <= #1 1'b0; + NMI_s <= #1 1'b0; + Oldnmi_n <= #1 1'b0; + end + else + begin + if (cen == 1'b1 ) + begin + BusReq_s <= #1 ~ busrq_n; + INT_s <= #1 ~ int_n; + if (NMICycle == 1'b1 ) + begin + NMI_s <= #1 1'b0; + end + else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) + begin + NMI_s <= #1 1'b1; + end + Oldnmi_n <= #1 nmi_n; + end + end + end + + //----------------------------------------------------------------------- + // + // Main state machine + // + //----------------------------------------------------------------------- + + always @ (posedge clk) + begin + if (reset_n == 1'b0 ) + begin + mcycle <= #1 7'b0000001; + tstate <= #1 7'b0000001; + Pre_XY_F_M <= #1 3'b000; + Halt_FF <= #1 1'b0; + BusAck <= #1 1'b0; + NMICycle <= #1 1'b0; + IntCycle <= #1 1'b0; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + No_BTR <= #1 1'b0; + Auto_Wait_t1 <= #1 1'b0; + Auto_Wait_t2 <= #1 1'b0; + m1_n <= #1 1'b1; + end + else + begin + if (cen == 1'b1 ) + begin + if (T_Res == 1'b1 ) + begin + Auto_Wait_t1 <= #1 1'b0; + end + else + begin + Auto_Wait_t1 <= #1 Auto_Wait || iorq_i; + end + Auto_Wait_t2 <= #1 Auto_Wait_t1; + No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) || + (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) || + (I_BTR && (~ IR[4] || F[Flag_Z])); + if (tstate[2] ) + begin + if (SetEI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b1; + IntE_FF2 <= #1 1'b1; + end + if (I_RETN == 1'b1 ) + begin + IntE_FF1 <= #1 IntE_FF2; + end + end + if (tstate[3] ) + begin + if (SetDI == 1'b1 ) + begin + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + Halt_FF <= #1 1'b0; + end + if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) + begin + m1_n <= #1 1'b1; + end + if (BusReq_s == 1'b1 && BusAck == 1'b1 ) + begin + end + else + begin + BusAck <= #1 1'b0; + if (tstate[2] && wait_n == 1'b0 ) + begin + end + else if (T_Res == 1'b1 ) + begin + if (Halt == 1'b1 ) + begin + Halt_FF <= #1 1'b1; + end + if (BusReq_s == 1'b1 ) + begin + BusAck <= #1 1'b1; + end + else + begin + tstate <= #1 7'b0000010; + if (NextIs_XY_Fetch == 1'b1 ) + begin + mcycle <= #1 7'b0100000; + Pre_XY_F_M <= #1 mcycle; + if (IR == 8'b00110110 && Mode == 0 ) + begin + Pre_XY_F_M <= #1 3'b010; + end + end + else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) + begin + mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1); + end + else if ((last_mcycle) || + No_BTR == 1'b1 || + (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) + begin + m1_n <= #1 1'b0; + mcycle <= #1 7'b0000001; + IntCycle <= #1 1'b0; + NMICycle <= #1 1'b0; + if (NMI_s == 1'b1 && Prefix == 2'b00 ) + begin + NMICycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + end + else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) + begin + IntCycle <= #1 1'b1; + IntE_FF1 <= #1 1'b0; + IntE_FF2 <= #1 1'b0; + end + end + else + begin + mcycle <= #1 { mcycle[5:0], mcycle[6] }; + end + end + end + else + begin // verilog has no "nor" operator + if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) && + ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) + begin + tstate <= #1 { tstate[5:0], tstate[6] }; + end + end + end + if (tstate[0]) + begin + m1_n <= #1 1'b0; + end + end + end + end + + always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC + or RegBusA or RegBusC or SP or tstate) + begin + if (JumpE == 1'b1 ) + begin + PC16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else if (BTR_r == 1'b1 ) + begin + PC16_B = -2; + end + else + begin + PC16_B = 1; + end + + if (tstate[3]) + begin + SP16_A = RegBusC; + SP16_B = { {8{DI_Reg[7]}}, DI_Reg }; + end + else + begin + // suspect that ID16 and SP16 could be shared + SP16_A = SP; + + if (IncDec_16[3] == 1'b1) + SP16_B = -1; + else + SP16_B = 1; + end + + if (IncDec_16[3]) + ID16_B = -1; + else + ID16_B = 1; + + ID16 = RegBusA + ID16_B; + PC16 = PC + PC16_B; + SP16 = SP16_A + SP16_B; + end // always @ * + + + always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle) + begin + Auto_Wait = 1'b0; + if (IntCycle == 1'b1 || NMICycle == 1'b1 ) + begin + if (mcycle[0] ) + begin + Auto_Wait = 1'b1; + end + end + end // always @ * + +endmodule // T80 + diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v new file mode 100644 index 00000000..7d49cb51 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v @@ -0,0 +1,2724 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_mcode + (/*AUTOARG*/ + // Outputs + MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, + Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, + Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, + LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, + ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, + I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, + // Inputs + IR, ISet, MCycle, F, NMICycle, IntCycle + ); + + parameter Mode = 0; + parameter Flag_C = 0; + parameter Flag_N = 1; + parameter Flag_P = 2; + parameter Flag_X = 3; + parameter Flag_H = 4; + parameter Flag_Y = 5; + parameter Flag_Z = 6; + parameter Flag_S = 7; + + input [7:0] IR; + input [1:0] ISet ; + input [6:0] MCycle ; + input [7:0] F ; + input NMICycle ; + input IntCycle ; + output [2:0] MCycles ; + output [2:0] TStates ; + output [1:0] Prefix ; // None,BC,ED,DD/FD + output Inc_PC ; + output Inc_WZ ; + output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + output Read_To_Reg ; + output Read_To_Acc ; + output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + output [3:0] ALU_Op ; + output Save_ALU ; + output PreserveC ; + output Arith16 ; + output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + output IORQ ; + output Jump ; + output JumpE ; + output JumpXY ; + output Call ; + output RstP ; + output LDZ ; + output LDW ; + output LDSPHL ; + output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + output ExchangeDH ; + output ExchangeRp ; + output ExchangeAF ; + output ExchangeRS ; + output I_DJNZ ; + output I_CPL ; + output I_CCF ; + output I_SCF ; + output I_RETN ; + output I_BT ; + output I_BC ; + output I_BTR ; + output I_RLD ; + output I_RRD ; + output I_INRC ; + output SetDI ; + output SetEI ; + output [1:0] IMode ; + output Halt ; + output NoRead ; + output Write ; + + // regs + reg [2:0] MCycles ; + reg [2:0] TStates ; + reg [1:0] Prefix ; // None,BC,ED,DD/FD + reg Inc_PC ; + reg Inc_WZ ; + reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc + reg Read_To_Reg ; + reg Read_To_Acc ; + reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + reg [3:0] ALU_Op ; + reg Save_ALU ; + reg PreserveC ; + reg Arith16 ; + reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI + reg IORQ ; + reg Jump ; + reg JumpE ; + reg JumpXY ; + reg Call ; + reg RstP ; + reg LDZ ; + reg LDW ; + reg LDSPHL ; + reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None + reg ExchangeDH ; + reg ExchangeRp ; + reg ExchangeAF ; + reg ExchangeRS ; + reg I_DJNZ ; + reg I_CPL ; + reg I_CCF ; + reg I_SCF ; + reg I_RETN ; + reg I_BT ; + reg I_BC ; + reg I_BTR ; + reg I_RLD ; + reg I_RRD ; + reg I_INRC ; + reg SetDI ; + reg SetEI ; + reg [1:0] IMode ; + reg Halt ; + reg NoRead ; + reg Write ; + + parameter aNone = 3'b111; + parameter aBC = 3'b000; + parameter aDE = 3'b001; + parameter aXY = 3'b010; + parameter aIOA = 3'b100; + parameter aSP = 3'b101; + parameter aZI = 3'b110; + // constant aNone : std_logic_vector[2:0] = 3'b000; + // constant aXY : std_logic_vector[2:0] = 3'b001; + // constant aIOA : std_logic_vector[2:0] = 3'b010; + // constant aSP : std_logic_vector[2:0] = 3'b011; + // constant aBC : std_logic_vector[2:0] = 3'b100; + // constant aDE : std_logic_vector[2:0] = 3'b101; + // constant aZI : std_logic_vector[2:0] = 3'b110; + + function is_cc_true; + input [7:0] F; + input [2:0] cc; + begin + if (Mode == 3 ) + begin + case (cc) + 3'b000 : is_cc_true = F[7] == 1'b0; // NZ + 3'b001 : is_cc_true = F[7] == 1'b1; // Z + 3'b010 : is_cc_true = F[4] == 1'b0; // NC + 3'b011 : is_cc_true = F[4] == 1'b1; // C + 3'b100 : is_cc_true = 0; + 3'b101 : is_cc_true = 0; + 3'b110 : is_cc_true = 0; + 3'b111 : is_cc_true = 0; + endcase + end + else + begin + case (cc) + 3'b000 : is_cc_true = F[6] == 1'b0; // NZ + 3'b001 : is_cc_true = F[6] == 1'b1; // Z + 3'b010 : is_cc_true = F[0] == 1'b0; // NC + 3'b011 : is_cc_true = F[0] == 1'b1; // C + 3'b100 : is_cc_true = F[2] == 1'b0; // PO + 3'b101 : is_cc_true = F[2] == 1'b1; // PE + 3'b110 : is_cc_true = F[7] == 1'b0; // P + 3'b111 : is_cc_true = F[7] == 1'b1; // M + endcase + end + end + endfunction // is_cc_true + + + reg [2:0] DDD; + reg [2:0] SSS; + reg [1:0] DPAIR; + reg [7:0] IRB; + + always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle + or NMICycle) + begin + DDD = IR[5:3]; + SSS = IR[2:0]; + DPAIR = IR[5:4]; + IRB = IR; + + MCycles = 3'b001; + if (MCycle[0] ) + begin + TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + Prefix = 2'b00; + Inc_PC = 1'b0; + Inc_WZ = 1'b0; + IncDec_16 = 4'b0000; + Read_To_Acc = 1'b0; + Read_To_Reg = 1'b0; + Set_BusB_To = 4'b0000; + Set_BusA_To = 4'b0000; + ALU_Op = { 1'b0, IR[5:3] }; + Save_ALU = 1'b0; + PreserveC = 1'b0; + Arith16 = 1'b0; + IORQ = 1'b0; + Set_Addr_To = aNone; + Jump = 1'b0; + JumpE = 1'b0; + JumpXY = 1'b0; + Call = 1'b0; + RstP = 1'b0; + LDZ = 1'b0; + LDW = 1'b0; + LDSPHL = 1'b0; + Special_LD = 3'b000; + ExchangeDH = 1'b0; + ExchangeRp = 1'b0; + ExchangeAF = 1'b0; + ExchangeRS = 1'b0; + I_DJNZ = 1'b0; + I_CPL = 1'b0; + I_CCF = 1'b0; + I_SCF = 1'b0; + I_RETN = 1'b0; + I_BT = 1'b0; + I_BC = 1'b0; + I_BTR = 1'b0; + I_RLD = 1'b0; + I_RRD = 1'b0; + I_INRC = 1'b0; + SetDI = 1'b0; + SetEI = 1'b0; + IMode = 2'b11; + Halt = 1'b0; + NoRead = 1'b0; + Write = 1'b0; + + case (ISet) + 2'b00 : + begin + + //---------------------------------------------------------------------------- + // + // Unprefixed instructions + // + //---------------------------------------------------------------------------- + + casex (IRB) + // 8 BIT LOAD GROUP + 8'b01xxxxxx : + begin + if (IRB[5:0] == 6'b110110) + Halt = 1'b1; + else if (IRB[2:0] == 3'b110) + begin + // LD r,(HL) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aXY; + if (MCycle[1]) + begin + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + end // if (IRB[2:0] == 3'b110) + else if (IRB[5:3] == 3'b110) + begin + // LD (HL),r + MCycles = 3'b010; + if (MCycle[0]) + begin + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (MCycle[1]) + Write = 1'b1; + end // if (IRB[5:3] == 3'b110) + else + begin + Set_BusB_To[2:0] = SSS; + ExchangeRp = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end // else: !if(IRB[5:3] == 3'b110) + end // case: 8'b01xxxxxx + + 8'b00xxx110 : + begin + if (IRB[5:3] == 3'b110) + begin + // LD (HL),n + MCycles = 3'b011; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + Set_Addr_To = aXY; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (MCycle[2]) + Write = 1'b1; + end // if (IRB[5:3] == 3'b110) + else + begin + // LD r,n + MCycles = 3'b010; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + end + end + end + + 8'b00001010 : + begin + // LD A,(BC) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aBC; + if (MCycle[1]) + Read_To_Acc = 1'b1; + end // case: 8'b00001010 + + 8'b00011010 : + begin + // LD A,(DE) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aDE; + if (MCycle[1]) + Read_To_Acc = 1'b1; + end // case: 8'b00011010 + + 8'b00111010 : + begin + if (Mode == 3 ) + begin + // LDD A,(HL) + MCycles = 3'b010; + if (MCycle[0]) + Set_Addr_To = aXY; + if (MCycle[1]) + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b1110; + end + end + else + begin + // LD A,(nn) + MCycles = 3'b100; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + if (MCycle[2]) + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + if (MCycle[3]) + begin + Read_To_Acc = 1'b1; + end + end // else: !if(Mode == 3 ) + end // case: 8'b00111010 + + 8'b00000010 : + begin + // LD (BC),A + MCycles = 3'b010; + if (MCycle[0]) + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + if (MCycle[1]) + begin + Write = 1'b1; + end + end // case: 8'b00000010 + + 8'b00010010 : + begin + // LD (DE),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aDE; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00010010 + + 8'b00110010 : + begin + if (Mode == 3 ) + begin + // LDD (HL),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b1110; + end + default :; + endcase // case(MCycle) + + end + else + begin + // LD (nn),A + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + MCycle[3] : + begin + Write = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00110010 + + + // 16 BIT LOAD GROUP + 8'b00000001,8'b00010001,8'b00100001,8'b00110001 : + begin + // LD dd,nn + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + MCycle[2] : + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 + + 8'b00101010 : + begin + if (Mode == 3 ) + begin + // LDI A,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + Read_To_Acc = 1'b1; + IncDec_16 = 4'b0110; + end + + default :; + endcase + end + else + begin + // LD HL,(nn) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + MCycle[3] : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + MCycle[4] : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00101010 + + 8'b00100010 : + begin + if (Mode == 3 ) + begin + // LDI (HL),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b0110; + end + default :; + endcase + end + else + begin + // LD (nn),HL + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b0101; // L + end + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b0100; // H + end + MCycle[4] : + Write = 1'b1; + default :; + endcase + end // else: !if(Mode == 3 ) + end // case: 8'b00100010 + + 8'b11111001 : + begin + // LD SP,HL + TStates = 3'b110; + LDSPHL = 1'b1; + end + + 8'b11xx0101 : + begin + // PUSH qq + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b0111; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 1 + + MCycle[1] : + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + if (DPAIR == 2'b11 ) + begin + Set_BusB_To = 4'b1011; + end + else + begin + Set_BusB_To[2:1] = DPAIR; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + Write = 1'b1; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 + + 8'b11xx0001 : + begin + // POP qq + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b1011; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b1; + end + end // case: 2 + + MCycle[2] : + begin + IncDec_16 = 4'b0111; + Read_To_Reg = 1'b1; + if (DPAIR == 2'b11 ) + begin + Set_BusA_To[3:0] = 4'b0111; + end + else + begin + Set_BusA_To[2:1] = DPAIR; + Set_BusA_To[0] = 1'b0; + end + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 + + + // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + 8'b11101011 : + begin + if (Mode != 3 ) + begin + // EX DE,HL + ExchangeDH = 1'b1; + end + end + + 8'b00001000 : + begin + if (Mode == 3 ) + begin + // LD (nn),SP + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + Set_BusB_To = 4'b1000; + end + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + Set_BusB_To = 4'b1001; + end + + MCycle[4] : + Write = 1'b1; + default :; + endcase + end + else if (Mode < 2 ) + begin + // EX AF,AF' + ExchangeAF = 1'b1; + end + end // case: 8'b00001000 + + 8'b11011001 : + begin + if (Mode == 3 ) + begin + // RETI + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + SetEI = 1'b1; + end + default :; + endcase + end + else if (Mode < 2 ) + begin + // EXX + ExchangeRS = 1'b1; + end + end // case: 8'b11011001 + + 8'b11100011 : + begin + if (Mode != 3 ) + begin + // EX (SP),HL + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + MCycle[1] : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0101; + Set_BusB_To = 4'b0101; + Set_Addr_To = aSP; + end + MCycle[2] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + TStates = 3'b100; + Write = 1'b1; + end + MCycle[3] : + begin + Read_To_Reg = 1'b1; + Set_BusA_To = 4'b0100; + Set_BusB_To = 4'b0100; + Set_Addr_To = aSP; + end + MCycle[4] : + begin + IncDec_16 = 4'b1111; + TStates = 3'b101; + Write = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11100011 + + + // 8 BIT ARITHMETIC AND LOGICAL GROUP + 8'b10xxxxxx : + begin + if (IR[2:0] == 3'b110) + begin + // ADD A,(HL) + // ADC A,(HL) + // SUB A,(HL) + // SBC A,(HL) + // AND A,(HL) + // OR A,(HL) + // XOR A,(HL) + // CP A,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + + default :; + endcase // case(MCycle) + end // if (IR[2:0] == 3'b110) + else + begin + // ADD A,r + // ADC A,r + // SUB A,r + // SBC A,r + // AND A,r + // OR A,r + // XOR A,r + // CP A,r + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // else: !if(IR[2:0] == 3'b110) + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b11xxx110 : + begin + // ADD A,n + // ADC A,n + // SUB A,n + // SBC A,n + // AND A,n + // OR A,n + // XOR A,n + // CP A,n + MCycles = 3'b010; + if (MCycle[1] ) + begin + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusB_To[2:0] = SSS; + Set_BusA_To[2:0] = 3'b111; + end + end + + 8'b00xxx100 : + begin + if (IRB[5:3] == 3'b110) + begin + // INC (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00110100 + else + begin + // INC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0000; + end + end + + 8'b00xxx101 : + begin + if (IRB[5:3] == 3'b110) + begin + // DEC (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aXY; + MCycle[1] : + begin + TStates = 3'b100; + Set_Addr_To = aXY; + ALU_Op = 4'b0010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + end // case: 2 + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end + else + begin + // DEC r + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = DDD; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + PreserveC = 1'b1; + ALU_Op = 4'b0010; + end + end + + // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + 8'b00100111 : + begin + // DAA + Set_BusA_To[2:0] = 3'b111; + Read_To_Reg = 1'b1; + ALU_Op = 4'b1100; + Save_ALU = 1'b1; + end + + 8'b00101111 : + // CPL + I_CPL = 1'b1; + + 8'b00111111 : + // CCF + I_CCF = 1'b1; + + 8'b00110111 : + // SCF + I_SCF = 1'b1; + + 8'b00000000 : + begin + if (NMICycle == 1'b1 ) + begin + // NMI + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + TStates = 3'b100; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + + end + else if (IntCycle == 1'b1 ) + begin + // INT (IM 2) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[0] : + begin + LDZ = 1'b1; + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + TStates = 3'b100; + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + TStates = 3'b100; + Write = 1'b1; + end + + MCycle[3] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[4] : + Jump = 1'b1; + default :; + endcase + end + end // case: 8'b00000000 + + 8'b11110011 : + // DI + SetDI = 1'b1; + + 8'b11111011 : + // EI + SetEI = 1'b1; + + // 16 BIT ARITHMETIC GROUP + 8'b00001001,8'b00011001,8'b00101001,8'b00111001 : + begin + // ADD HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + + default : + Set_BusB_To = 4'b1000; + endcase // case(IR[5:4]) + + TStates = 3'b100; + Arith16 = 1'b1; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + Arith16 = 1'b1; + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 + + 8'b00000011,8'b00010011,8'b00100011,8'b00110011 : + begin + // INC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b01; + IncDec_16[1:0] = DPAIR; + end + + 8'b00001011,8'b00011011,8'b00101011,8'b00111011 : + begin + // DEC ss + TStates = 3'b110; + IncDec_16[3:2] = 2'b11; + IncDec_16[1:0] = DPAIR; + end + + // ROTATE AND SHIFT GROUP + 8'b00000111, + // RLCA + 8'b00010111, + // RLA + 8'b00001111, + // RRCA + 8'b00011111 : + // RRA + begin + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end // case: 8'b00000111,... + + + // JUMP GROUP + 8'b11000011 : + begin + // JP nn + MCycles = 3'b011; + if (MCycle[1]) + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + if (MCycle[2]) + begin + Inc_PC = 1'b1; + Jump = 1'b1; + end + + end // case: 8'b11000011 + + 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IRB[4:3]) + 2'b00 : + begin + // LD ($FF00+C),A + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b0111; + end + MCycle[1] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // LD (nn),A + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + Set_BusB_To = 4'b0111; + end + + MCycle[3] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: default :... + + 2'b10 : + begin + // LD A,($FF00+C) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aBC; + MCycle[1] : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD A,(nn) + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + end + MCycle[3] : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end + endcase + end + else + begin + // JP cc,nn + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Inc_PC = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + Jump = 1'b1; + end + end + + default :; + endcase + end // else: !if(DPAIR == 2'b11 ) + end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 + + 8'b00011000 : + begin + if (Mode != 2 ) + begin + // JR e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + Inc_PC = 1'b1; + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00011000 + + 8'b00111000 : + begin + if (Mode != 2 ) + begin + // JR C,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + if (F[Flag_C] == 1'b0 ) + begin + MCycles = 3'b010; + end + end + + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00111000 + + 8'b00110000 : + begin + if (Mode != 2 ) + begin + // JR NC,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + if (F[Flag_C] == 1'b1 ) + begin + MCycles = 3'b010; + end + end + + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00110000 + + 8'b00101000 : + begin + if (Mode != 2 ) + begin + // JR Z,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + if (F[Flag_Z] == 1'b0 ) + begin + MCycles = 3'b010; + end + end + + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00101000 + + 8'b00100000 : + begin + if (Mode != 2 ) + begin + // JR NZ,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + if (F[Flag_Z] == 1'b1 ) + begin + MCycles = 3'b010; + end + end + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode != 2 ) + end // case: 8'b00100000 + + 8'b11101001 : + // JP (HL) + JumpXY = 1'b1; + + 8'b00010000 : + begin + if (Mode == 3 ) + begin + I_DJNZ = 1'b1; + end + else if (Mode < 2 ) + begin + // DJNZ,e + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + I_DJNZ = 1'b1; + Set_BusB_To = 4'b1010; + Set_BusA_To[2:0] = 3'b000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + MCycle[1] : + begin + I_DJNZ = 1'b1; + Inc_PC = 1'b1; + end + MCycle[2] : + begin + NoRead = 1'b1; + JumpE = 1'b1; + TStates = 3'b101; + end + default :; + endcase + end // if (Mode < 2 ) + end // case: 8'b00010000 + + + // CALL AND RETURN GROUP + 8'b11001101 : + begin + // CALL nn + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + IncDec_16 = 4'b1111; + Inc_PC = 1'b1; + TStates = 3'b100; + Set_Addr_To = aSP; + LDW = 1'b1; + Set_BusB_To = 4'b1101; + end + MCycle[3] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + MCycle[4] : + begin + Write = 1'b1; + Call = 1'b1; + end + default :; + endcase // case(MCycle) + end // case: 8'b11001101 + + 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 : + begin + if (IR[5] == 1'b0 || Mode != 3 ) + begin + // CALL cc,nn + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + MCycle[2] : + begin + Inc_PC = 1'b1; + LDW = 1'b1; + if (is_cc_true(F, IR[5:3]) ) + begin + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + TStates = 3'b100; + Set_BusB_To = 4'b1101; + end + else + begin + MCycles = 3'b011; + end // else: !if(is_cc_true(F, IR[5:3]) ) + end // case: 3 + + MCycle[3] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[4] : + begin + Write = 1'b1; + Call = 1'b1; + end + + default :; + endcase + end // if (IR[5] == 1'b0 || Mode != 3 ) + end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 + + 8'b11001001 : + begin + // RET + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + Set_Addr_To = aSP; + end + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11001001 + + 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : + begin + if (IR[5] == 1'b1 && Mode == 3 ) + begin + case (IRB[4:3]) + 2'b00 : + begin + // LD ($FF00+nn),A + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b00 + + 2'b01 : + begin + // ADD SP,n + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + ALU_Op = 4'b0000; + Inc_PC = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To = 4'b1000; + Set_BusB_To = 4'b0110; + end + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To = 4'b1001; + Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + end + + default :; + endcase // case(MCycle) + end // case: 2'b01 + + 2'b10 : + begin + // LD A,($FF00+nn) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + MCycle[2] : + Read_To_Acc = 1'b1; + default :; + endcase // case(MCycle) + end // case: 2'b10 + + 2'b11 : + begin + // LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + MCycle[3] : + begin + Set_BusA_To[2:0] = 3'b101; // L + Read_To_Reg = 1'b1; + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end + + MCycle[4] : + begin + Set_BusA_To[2:0] = 3'b100; // H + Read_To_Reg = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 2'b11 + + endcase // case(IRB[4:3]) + + end + else + begin + // RET cc + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + if (is_cc_true(F, IR[5:3]) ) + begin + Set_Addr_To = aSP; + end + else + begin + MCycles = 3'b001; + end + TStates = 3'b101; + end // case: 1 + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + end + default :; + endcase + end // else: !if(IR[5] == 1'b1 && Mode == 3 ) + end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 + + 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : + begin + // RST p + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1101; + end + + MCycle[1] : + begin + Write = 1'b1; + IncDec_16 = 4'b1111; + Set_Addr_To = aSP; + Set_BusB_To = 4'b1100; + end + + MCycle[2] : + begin + Write = 1'b1; + RstP = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 + + // INPUT AND OUTPUT GROUP + 8'b11011011 : + begin + if (Mode != 3 ) + begin + // IN A,(n) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + end + + MCycle[2] : + begin + Read_To_Acc = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11011011 + + 8'b11010011 : + begin + if (Mode != 3 ) + begin + // OUT (n),A + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + Set_Addr_To = aIOA; + Set_BusB_To = 4'b0111; + end + + MCycle[2] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase + end // if (Mode != 3 ) + end // case: 8'b11010011 + + + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + // MULTIBYTE INSTRUCTIONS + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + + 8'b11001011 : + begin + if (Mode != 2 ) + begin + Prefix = 2'b01; + end + end + + 8'b11101101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b10; + end + end + + 8'b11011101,8'b11111101 : + begin + if (Mode < 2 ) + begin + Prefix = 2'b11; + end + end + + endcase // case(IRB) + end // case: 2'b00 + + + 2'b01 : + begin + + + //---------------------------------------------------------------------------- + // + // CB prefixed instructions + // + //---------------------------------------------------------------------------- + + Set_BusA_To[2:0] = IR[2:0]; + Set_BusB_To[2:0] = IR[2:0]; + + case (IRB) + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, + 8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, + 8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, + 8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, + 8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, + 8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, + 8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, + 8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : + begin + // RLC r + // RL r + // RRC r + // RR r + // SLA r + // SRA r + // SRL r + // SLL r (Undocumented) / SWAP r + if (MCycle[0] ) begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... + + 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 : + begin + // RLC (HL) + // RL (HL) + // RRC (HL) + // RR (HL) + // SRA (HL) + // SRL (HL) + // SLA (HL) + // SLL (HL) (Undocumented) / SWAP (HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 + + 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, + 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, + 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, + 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, + 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, + 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, + 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, + 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : + begin + // BIT b,r + if (MCycle[0] ) + begin + Set_BusB_To[2:0] = IR[2:0]; + ALU_Op = 4'b1001; + end + end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... + + 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : + begin + // BIT b,(HL) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1001; + TStates = 3'b100; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 + + 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, + 8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, + 8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, + 8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, + 8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, + 8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, + 8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, + 8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : + begin + // SET b,r + if (MCycle[0] ) + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... + + 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : + begin + // SET b,(HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1010; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 + + 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, + 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, + 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, + 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, + 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, + 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, + 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, + 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : + begin + // RES b,r + if (MCycle[0] ) + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + end + end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... + + 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : + begin + // RES b,(HL) + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0], MCycle[6] : + Set_Addr_To = aXY; + MCycle[1] : + begin + ALU_Op = 4'b1011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_Addr_To = aXY; + TStates = 3'b100; + end + + MCycle[2] : + Write = 1'b1; + default :; + endcase // case(MCycle) + end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 + + endcase // case(IRB) + end // case: 2'b01 + + + default : + begin : default_ed_block + + //---------------------------------------------------------------------------- + // + // ED prefixed instructions + // + //---------------------------------------------------------------------------- + + case (IRB) + 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 + ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 + ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 + ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 + ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 + ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 + ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 + ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 + + + ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 + ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 + ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 + ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 + , 8'b10100100,8'b10100101,8'b10100110,8'b10100111 + , 8'b10101100,8'b10101101,8'b10101110,8'b10101111 + , 8'b10110100,8'b10110101,8'b10110110,8'b10110111 + , 8'b10111100,8'b10111101,8'b10111110,8'b10111111 + ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 + ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 + ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 + ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 + ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 + ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 + ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 + ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : + ; // NOP, undocumented + + 8'b01111110,8'b01111111 : + // NOP, undocumented + ; + // 8 BIT LOAD GROUP + 8'b01010111 : + begin + // LD A,I + Special_LD = 3'b100; + TStates = 3'b101; + end + + 8'b01011111 : + begin + // LD A,R + Special_LD = 3'b101; + TStates = 3'b101; + end + + 8'b01000111 : + begin + // LD I,A + Special_LD = 3'b110; + TStates = 3'b101; + end + + 8'b01001111 : + begin + // LD R,A + Special_LD = 3'b111; + TStates = 3'b101; + end + + // 16 BIT LOAD GROUP + 8'b01001011,8'b01011011,8'b01101011,8'b01111011 : + begin + // LD dd,(nn) + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + end + + MCycle[3] : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1000; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b1; + end + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + end // case: 4 + + MCycle[4] : + begin + Read_To_Reg = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusA_To = 4'b1001; + end + else + begin + Set_BusA_To[2:1] = IR[5:4]; + Set_BusA_To[0] = 1'b0; + end + end // case: 5 + + default :; + endcase // case(MCycle) + end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 + + + 8'b01000011,8'b01010011,8'b01100011,8'b01110011 : + begin + // LD (nn),dd + MCycles = 3'b101; + case (1'b1) // MCycle + MCycle[1] : + begin + Inc_PC = 1'b1; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Set_Addr_To = aZI; + Inc_PC = 1'b1; + LDW = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1000; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + Set_BusB_To[3] = 1'b0; + end + end // case: 3 + + MCycle[3] : + begin + Inc_WZ = 1'b1; + Set_Addr_To = aZI; + Write = 1'b1; + if (IR[5:4] == 2'b11 ) + begin + Set_BusB_To = 4'b1001; + end + else + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + Set_BusB_To[3] = 1'b0; + end + end // case: 4 + + MCycle[4] : + begin + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 + + 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : + begin + // LDI, LDD, LDIR, LDDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0000; + Set_Addr_To = aDE; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; // IX + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + MCycle[2] : + begin + I_BT = 1'b1; + TStates = 3'b101; + Write = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0101; // DE + end + else + begin + IncDec_16 = 4'b1101; + end + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 + + 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : + begin + // CPI, CPD, CPIR, CPDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aXY; + IncDec_16 = 4'b1100; // BC + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b0111; + Save_ALU = 1'b1; + PreserveC = 1'b1; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + I_BC = 1'b1; + TStates = 3'b101; + end + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 + + 8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : + begin + // NEG + ALU_Op = 4'b0010; + Set_BusB_To = 4'b0111; + Set_BusA_To = 4'b1010; + Read_To_Acc = 1'b1; + Save_ALU = 1'b1; + end + + 8'b01000110,8'b01001110,8'b01100110,8'b01101110 : + begin + // IM 0 + IMode = 2'b00; + end + + 8'b01010110,8'b01110110 : + // IM 1 + IMode = 2'b01; + + 8'b01011110,8'b01110111 : + // IM 2 + IMode = 2'b10; + + // 16 bit arithmetic + 8'b01001010,8'b01011010,8'b01101010,8'b01111010 : + begin + // ADC HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0001; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0001; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b0; + end + default : + Set_BusB_To = 4'b1001; + endcase // case(IR[5:4]) + end // case: 3 + + default :; + endcase // case(MCycle) + end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 + + 8'b01000010,8'b01010010,8'b01100010,8'b01110010 : + begin + // SBC HL,ss + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b101; + case (IR[5:4]) + 0,1,2 : + begin + Set_BusB_To[2:1] = IR[5:4]; + Set_BusB_To[0] = 1'b1; + end + default : + Set_BusB_To = 4'b1000; + endcase + TStates = 3'b100; + end // case: 2 + + MCycle[2] : + begin + NoRead = 1'b1; + ALU_Op = 4'b0011; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + Set_BusA_To[2:0] = 3'b100; + case (IR[5:4]) + 0,1,2 : + Set_BusB_To[2:1] = IR[5:4]; + default : + Set_BusB_To = 4'b1001; + endcase + end // case: 3 + + default :; + + endcase // case(MCycle) + end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 + + 8'b01101111 : + begin + // RLD + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + begin + NoRead = 1'b1; + Set_Addr_To = aXY; + end + + MCycle[2] : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1101; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + MCycle[3] : + begin + I_RLD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01101111 + + 8'b01100111 : + begin + // RRD + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[1] : + Set_Addr_To = aXY; + MCycle[2] : + begin + Read_To_Reg = 1'b1; + Set_BusB_To[2:0] = 3'b110; + Set_BusA_To[2:0] = 3'b111; + ALU_Op = 4'b1110; + TStates = 3'b100; + Set_Addr_To = aXY; + Save_ALU = 1'b1; + end + + MCycle[3] : + begin + I_RRD = 1'b1; + Write = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01100111 + + 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : + begin + // RETI, RETN + MCycles = 3'b011; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aSP; + + MCycle[1] : + begin + IncDec_16 = 4'b0111; + Set_Addr_To = aSP; + LDZ = 1'b1; + end + + MCycle[2] : + begin + Jump = 1'b1; + IncDec_16 = 4'b0111; + I_RETN = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 + + 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : + begin + // IN r,(C) + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + Set_Addr_To = aBC; + + MCycle[1] : + begin + IORQ = 1'b1; + if (IR[5:3] != 3'b110 ) + begin + Read_To_Reg = 1'b1; + Set_BusA_To[2:0] = IR[5:3]; + end + I_INRC = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 + + 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : + begin + // OUT (C),r + // OUT (C),0 + MCycles = 3'b010; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To[2:0] = IR[5:3]; + if (IR[5:3] == 3'b110 ) + begin + Set_BusB_To[3] = 1'b1; + end + end + + MCycle[1] : + begin + Write = 1'b1; + IORQ = 1'b1; + end + + default :; + endcase // case(MCycle) + end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 + + 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : + begin + // INI, IND, INIR, INDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + Set_Addr_To = aBC; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + MCycle[1] : + begin + IORQ = 1'b1; + Set_BusB_To = 4'b0110; + Set_Addr_To = aXY; + end + + MCycle[2] : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + TStates = 3'b100; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 + + 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : + begin + // OUTI, OUTD, OTIR, OTDR + MCycles = 3'b100; + case (1'b1) // MCycle + MCycle[0] : + begin + TStates = 3'b101; + Set_Addr_To = aXY; + Set_BusB_To = 4'b1010; + Set_BusA_To = 4'b0000; + Read_To_Reg = 1'b1; + Save_ALU = 1'b1; + ALU_Op = 4'b0010; + end + + MCycle[1] : + begin + Set_BusB_To = 4'b0110; + Set_Addr_To = aBC; + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0110; + end + else + begin + IncDec_16 = 4'b1110; + end + end + + MCycle[2] : + begin + if (IR[3] == 1'b0 ) + begin + IncDec_16 = 4'b0010; + end + else + begin + IncDec_16 = 4'b1010; + end + IORQ = 1'b1; + Write = 1'b1; + I_BTR = 1'b1; + end // case: 3 + + MCycle[3] : + begin + NoRead = 1'b1; + TStates = 3'b101; + end + + default :; + endcase // case(MCycle) + end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 + + endcase // case(IRB) + end // block: default_ed_block + endcase // case(ISet) + + if (Mode == 1 ) + begin + if (MCycle[0] ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b011; + end + end + + if (Mode == 3 ) + begin + if (MCycle[0] ) + begin + //TStates = 3'b100; + end + else + begin + TStates = 3'b100; + end + end + + if (Mode < 2 ) + begin + if (MCycle[5] ) + begin + Inc_PC = 1'b1; + if (Mode == 1 ) + begin + Set_Addr_To = aXY; + TStates = 3'b100; + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + end + if (IRB == 8'b00110110 || IRB == 8'b11001011 ) + begin + Set_Addr_To = aNone; + end + end + if (MCycle[6] ) + begin + if (Mode == 0 ) + begin + TStates = 3'b101; + end + if (ISet != 2'b01 ) + begin + Set_Addr_To = aXY; + end + Set_BusB_To[2:0] = SSS; + Set_BusB_To[3] = 1'b0; + if (IRB == 8'b00110110 || ISet == 2'b01 ) + begin + // LD (HL),n + Inc_PC = 1'b1; + end + else + begin + NoRead = 1'b1; + end + end + end // if (Mode < 2 ) + + end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) + +endmodule // T80_MCode diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v new file mode 100644 index 00000000..9d378330 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v @@ -0,0 +1,68 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +module tv80_reg (/*AUTOARG*/ + // Outputs + DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, + // Inputs + AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL + ); + input [2:0] AddrC; + output [7:0] DOBH; + input [2:0] AddrA; + input [2:0] AddrB; + input [7:0] DIH; + output [7:0] DOAL; + output [7:0] DOCL; + input [7:0] DIL; + output [7:0] DOBL; + output [7:0] DOCH; + output [7:0] DOAH; + input clk, CEN, WEH, WEL; + + reg [7:0] RegsH [0:7]; + reg [7:0] RegsL [0:7]; + + always @(posedge clk) + begin + if (CEN) + begin + if (WEH) RegsH[AddrA] <= DIH; + if (WEL) RegsL[AddrA] <= DIL; + end + end + + assign DOAH = RegsH[AddrA]; + assign DOAL = RegsL[AddrA]; + assign DOBH = RegsH[AddrB]; + assign DOBL = RegsL[AddrB]; + assign DOCH = RegsH[AddrC]; + assign DOCL = RegsL[AddrC]; + + // break out ram bits for waveform debug + wire [7:0] H = RegsH[2]; + wire [7:0] L = RegsL[2]; + +endmodule + diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v new file mode 100644 index 00000000..b7802e33 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v @@ -0,0 +1,182 @@ +// +// TV80 8-Bit Microprocessor Core +// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) +// +// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// Negative-edge based wrapper allows memory wait_n signal to work +// correctly without resorting to asynchronous logic. + +module tv80n (/*AUTOARG*/ + // Outputs + m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, + // Inputs + reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di + ); + + parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2 + parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle + + + input reset_n; + input clk; + input wait_n; + input int_n; + input nmi_n; + input busrq_n; + output m1_n; + output mreq_n; + output iorq_n; + output rd_n; + output wr_n; + output rfsh_n; + output halt_n; + output busak_n; + output [15:0] A; + input [7:0] di; + output [7:0] dout; + + reg mreq_n; + reg iorq_n; + reg rd_n; + reg wr_n; + reg nxt_mreq_n; + reg nxt_iorq_n; + reg nxt_rd_n; + reg nxt_wr_n; + + wire cen; + wire intcycle_n; + wire no_read; + wire write; + wire iorq; + reg [7:0] di_reg; + wire [6:0] mcycle; + wire [6:0] tstate; + + assign cen = 1; + + tv80_core #(Mode, IOWait) i_tv80_core + ( + .cen (cen), + .m1_n (m1_n), + .iorq (iorq), + .no_read (no_read), + .write (write), + .rfsh_n (rfsh_n), + .halt_n (halt_n), + .wait_n (wait_n), + .int_n (int_n), + .nmi_n (nmi_n), + .reset_n (reset_n), + .busrq_n (busrq_n), + .busak_n (busak_n), + .clk (clk), + .IntE (), + .stop (), + .A (A), + .dinst (di), + .di (di_reg), + .dout (dout), + .mc (mcycle), + .ts (tstate), + .intcycle_n (intcycle_n) + ); + + always @* + begin + nxt_mreq_n = 1; + nxt_rd_n = 1; + nxt_iorq_n = 1; + nxt_wr_n = 1; + + if (mcycle[0]) + begin + if (tstate[1] || tstate[2]) + begin + nxt_rd_n = ~ intcycle_n; + nxt_mreq_n = ~ intcycle_n; + nxt_iorq_n = intcycle_n; + end + end // if (mcycle[0]) + else + begin + if ((tstate[1] || tstate[2]) && !no_read && !write) + begin + nxt_rd_n = 1'b0; + nxt_iorq_n = ~ iorq; + nxt_mreq_n = iorq; + end + if (T2Write == 0) + begin + if (tstate[2] && write) + begin + nxt_wr_n = 1'b0; + nxt_iorq_n = ~ iorq; + nxt_mreq_n = iorq; + end + end + else + begin + if ((tstate[1] || (tstate[2] && !wait_n)) && write) + begin + nxt_wr_n = 1'b0; + nxt_iorq_n = ~ iorq; + nxt_mreq_n = iorq; + end + end // else: !if(T2write == 0) + end // else: !if(mcycle[0]) + end // always @ * + + always @(negedge clk) + begin + if (!reset_n) + begin + rd_n <= #1 1'b1; + wr_n <= #1 1'b1; + iorq_n <= #1 1'b1; + mreq_n <= #1 1'b1; + end + else + begin + rd_n <= #1 nxt_rd_n; + wr_n <= #1 nxt_wr_n; + iorq_n <= #1 nxt_iorq_n; + mreq_n <= #1 nxt_mreq_n; + end // else: !if(!reset_n) + end // always @ (posedge clk or negedge reset_n) + + always @(posedge clk) + begin + if (!reset_n) + begin + di_reg <= #1 0; + end + else + begin + if (tstate[2] && wait_n == 1'b1) + di_reg <= #1 di; + end // else: !if(!reset_n) + end // always @ (posedge clk) + +endmodule // t80n + diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/ace.hex b/Jupiter Cantab - JupiterACE_MiST/rtl/ace.hex new file mode 100644 index 00000000..fcc8b102 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/ace.hex @@ -0,0 +1,8192 @@ +F3 +21 +00 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a/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv b/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv new file mode 100644 index 00000000..553ebed4 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv @@ -0,0 +1,205 @@ +`timescale 1ns / 1ps +`default_nettype none + +module ace_mist( + input CLOCK_27, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output LED, + output AUDIO_L, + output AUDIO_R, + output UART_TX,//uses for Tape Record + input UART_RX,//uses for Tape Play + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0, + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE + ); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "Jupiter ACE;;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T5,Reset;", + "V,v0.2.",`BUILD_DATE + }; + +wire clk_sys; +wire clk_65; +wire clk_cpu; +wire clk_sdram; +wire locked; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire audio; +wire TapeIn; +wire TapeOut; +wire HSync, VSync; +wire video; +wire [7:0] kbd_rows; +wire [4:0] kbd_columns; + +pll pll( + .areset(), + .inclk0(CLOCK_27), + .c0(clk_sys),//26.0Mhz + .c1(clk_65),//6.5Mhz + .c2(clk_cpu),//3.25Mhz + .c3(clk_sdram),//100Mhz + .locked(locked) + ); + +reg [7:0] reset_cnt; +always @(posedge clk_sys) begin + if(!locked || buttons[1] || status[0] || status[5]) + reset_cnt <= 8'h0; + else if(reset_cnt != 8'd255) + reset_cnt <= reset_cnt + 8'd1; +end + +wire reset = (reset_cnt != 8'd255); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .conf_str(CONF_STR), + .clk_sys(clk_sys), + .SPI_SCK(SPI_SCK), + .CONF_DATA0(CONF_DATA0), + .SPI_SS2(SPI_SS2), + .SPI_DO(SPI_DO), + .SPI_DI(SPI_DI), + .buttons(buttons), + .switches(switches), + .scandoubler_disable(scandoubler_disable), + .ypbpr(ypbpr), + .status(status), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data) +); + +video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(clk_65), + .ce_pix_actual(clk_65), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .scandoubler_disable(scandoubler_disable), + .hq2x(status[4:3]==1), + .ypbpr(ypbpr), + .ypbpr_full(1), + .R({video,video,1'b0}), + .G({video,video,1'b0}), + .B({video,video,1'b0}), + .mono(1), + .HSync(HSync), + .VSync(VSync), + .line_start(0), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS) +); + +wire [24:0]sd_addr; +wire [7:0]sd_dout; +wire [7:0]sd_din; +wire sd_we; +wire sd_rd; +wire sd_ready; + +sram sram( + .SDRAM_DQ(SDRAM_DQ), + .SDRAM_A(SDRAM_A), + .SDRAM_DQML(SDRAM_DQML), + .SDRAM_DQMH(SDRAM_DQMH), + .SDRAM_BA(SDRAM_BA), + .SDRAM_nCS(SDRAM_nCS), + .SDRAM_nWE(SDRAM_nWE), + .SDRAM_nRAS(SDRAM_nRAS), + .SDRAM_nCAS(SDRAM_nCAS), + .SDRAM_CKE(SDRAM_CKE), + .init(~reset), + .clk_sdram(clk_sdram), + .addr(sd_addr), // 25 bit address + .dout(sd_dout), // data output to cpu + .din(sd_din), // data input from cpu + .we(sd_we), // cpu requests write + .rd(sd_rd), // cpu requests read + .ready(sd_ready) +); + + +jupiter_ace jupiter_ace +( + .clk_65(clk_65), + .clk_cpu(clk_cpu), + .reset(~reset), + .filas(kbd_rows), + .columnas(kbd_columns), + .video(video), + .hsync(HSync), + .vsync(VSync), + .ear(UART_RX),//Play + .mic(UART_TX),//Record + .spk(audio), + .sd_addr(sd_addr), + .sd_dout(sd_dout), + .sd_din(sd_din), + .sd_we(sd_we), + .sd_rd(sd_rd), + .sd_ready(sd_ready) +); + +sigma_delta_dac sigma_delta_dac +( + .DACout(AUDIO_L), + .DACin({audio}), + .CLK(clk_65), + .RESET(0) +); + +assign AUDIO_R = AUDIO_L; + +keyboard keyboard +( + .clk(clk_65), + .clkps2(ps2_kbd_clk), + .dataps2(ps2_kbd_data), + .rows(kbd_rows), + .columns(kbd_columns), + .kbd_reset(), + .kbd_nmi(), + .kbd_mreset() +); + + + + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.tcl b/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v b/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v new file mode 100644 index 00000000..ef44ea45 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171124" +`define BUILD_TIME "193745" diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/glue.v b/Jupiter Cantab - JupiterACE_MiST/rtl/glue.v new file mode 100644 index 00000000..f1d66bb9 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/glue.v @@ -0,0 +1,197 @@ +`timescale 1ns / 1ps +`default_nettype none +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 00:32:05 11/08/2015 +// Design Name: +// Module Name: glue +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module glue ( + input wire clk, + // CPU interface + input wire [15:0] cpu_addr, + input wire mreq_n, + input wire iorq_n, + input wire rd_n, + input wire wr_n, + input wire [7:0] data_from_cpu, + output reg [7:0] data_to_cpu, + output reg data_to_cpu_oe, + output reg wait_n, + output wire int_n, + // CPU-RAM interface + output reg rom_enable, + output reg sram_enable, + output reg cram_enable, + output reg uram_enable, + output reg xram_enable, + output reg eram_enable, + // Screen RAM and Char RAM interface + output wire [9:0] screen_addr, + input wire [7:0] screen_data, + output wire [9:0] char_addr, + input wire [7:0] char_data, + // Devices + input wire [4:0] kbdcols, + input wire ear, + output reg spk, + output reg mic, + output wire video, + output wire hsync_pal, + output wire vsync_pal + ); + + initial begin + wait_n = 1'b1; + spk = 1'b0; + mic = 1'b0; + end + + reg [8:0] cntpix = 9'd0; + reg [8:0] cntscn = 9'd0; + wire [17:0] cnt = {cntscn, cntpix}; + + always @(posedge clk) begin + if (cntpix != 9'd415) + cntpix <= cntpix + 9'd1; + else begin + cntpix <= 9'd0; + if (cntscn != 9'd311) + cntscn <= cntscn + 9'd1; + else + cntscn <= 9'd0; + end + end + + reg vsync; // FIELD signal in schematic + always @* begin + if (cntscn >= 9'd248 && cntscn <= 9'd255) + vsync = 1'b0; + else + vsync = 1'b1; + end + assign int_n = vsync; + + reg hsync; // LINE signal in schematic + always @* begin + if (cntpix >= 9'd320 && cntpix <= 9'd351) + hsync = 1'b0; + else + hsync = 1'b1; + end + + //assign csync = hsync & vsync; + assign hsync_pal = hsync; + assign vsync_pal = vsync; + + reg viden; // VIDEN signal in schematic + always @* begin + if (cntpix >= 9'd0 && cntpix <= 9'd255 && + cntscn >= 9'd0 && cntscn <= 9'd191) + viden = 1'b1; + else + viden = 1'b0; + end + + // SHIFT/LOAD signal to 74LS166 + reg shiftload; + always @* begin + if (cnt[2:0] == 3'b000 && viden == 1'b1) + shiftload = 1'b1; + else + shiftload = 1'b0; + end + + assign screen_addr = {cnt[16:12], cnt[7:3]}; + assign char_addr = {screen_data[6:0], cnt[11:9]}; + + // 74LS166 + reg [7:0] shiftreg = 8'h00; + always @(posedge clk) begin + if (shiftload == 1'b1) + shiftreg <= char_data; + else + shiftreg <= {shiftreg[6:0], 1'b0}; + end + + // Pixel inverter reg and video output stage + reg pixinverter = 1'b0; + always @(posedge clk) begin + if (cnt[2:0] == 3'b000) + pixinverter <= viden & screen_data[7]; + end + + assign video = shiftreg[7] ^ pixinverter; + + // Address decoder + reg fast_access; + always @* begin + rom_enable = 1'b0; + sram_enable = 1'b0; + cram_enable = 1'b0; + uram_enable = 1'b0; + xram_enable = 1'b0; + eram_enable = 1'b0; + fast_access = 1'b1; + if (mreq_n == 1'b0) begin + if (cpu_addr >= 16'h0000 && cpu_addr <= 16'h1FFF) + rom_enable = 1'b1; + else if (cpu_addr >= 16'h2000 && cpu_addr <= 16'h27FF) begin + sram_enable = 1'b1; + if (cpu_addr >= 16'h2400 && cpu_addr <= 16'h27FF) + fast_access = 1'b0; + end + else if (cpu_addr >= 16'h2800 && cpu_addr <= 16'h2FFF) begin + cram_enable = 1'b1; + if (cpu_addr >= 16'h2C00 && cpu_addr <= 16'h2FFF) + fast_access = 1'b0; + end + else if (cpu_addr >= 16'h3000 && cpu_addr <= 16'h3FFF) + uram_enable = 1'b1; + else if (cpu_addr >= 16'h4000 && cpu_addr <= 16'h7FFF) + xram_enable = 1'b1; + else + eram_enable = 1'b1; + end + end + + // CPU arbitration to share memory with video generator + always @(posedge clk) begin + if ((sram_enable == 1'b1 || cram_enable == 1'b1) && viden == 1'b1 && fast_access == 1'b0) + wait_n <= 1'b0; + else if (viden == 1'b0) + wait_n <= 1'b1; + end + + // IO devices + always @* begin + data_to_cpu_oe = 1'b0; + data_to_cpu = {2'b11, ear, kbdcols}; + if (iorq_n == 1'b0 && cpu_addr[0] == 1'b0 && rd_n == 1'b0) begin + data_to_cpu_oe = 1'b1; + end + end + always @(posedge clk) begin + if (iorq_n == 1'b0 && cpu_addr[0] == 1'b0) begin + if (rd_n == 1'b0 && wr_n == 1'b1) + spk <= 1'b0; + else if (rd_n == 1'b1 && wr_n == 1'b0) + spk <= 1'b1; + if (wr_n == 1'b0) + mic <= data_from_cpu[3]; + end + end +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/hq2x.sv b/Jupiter Cantab - JupiterACE_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/io_write_to_rom.v b/Jupiter Cantab - JupiterACE_MiST/rtl/io_write_to_rom.v new file mode 100644 index 00000000..3a21c492 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/io_write_to_rom.v @@ -0,0 +1,81 @@ +`timescale 1ns / 1ps +`default_nettype none + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:45:40 11/08/2015 +// Design Name: +// Module Name: io_write_to_rom +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module io_write_to_rom ( + input wire clk, + input wire [15:0] a, + input wire iorq_n, + input wire rd_n, + input wire wr_n, + input wire [7:0] din, + output reg [7:0] dout, + output reg dout_oe, + output reg enable_write_to_rom + ); + + parameter IOADDR = 127; // Puerto 127 para esta historia + reg [7:0] magicsequence[0:7]; + initial begin + enable_write_to_rom = 1'b0; + magicsequence[0] = "E"; + magicsequence[1] = "N"; + magicsequence[2] = "A"; + magicsequence[3] = "B"; + magicsequence[4] = "L"; + magicsequence[5] = "E"; + magicsequence[6] = "W"; + magicsequence[7] = "R"; + end + + reg [2:0] indexseq = 3'd0; + reg in_io_write = 1'b0; + reg [7:0] data_from_cpu; + + always @(posedge clk) begin + if (in_io_write == 1'b0 && iorq_n == 1'b0 && wr_n == 1'b0 && a[7:0] == IOADDR) begin + data_from_cpu <= din; + in_io_write <= 1'b1; + end + else if (in_io_write == 1'b1 && (iorq_n == 1'b1 || wr_n == 1'b1 || a[7:0] != IOADDR)) begin + in_io_write <= 1'b0; + if (data_from_cpu == magicsequence[indexseq]) begin + if (indexseq == 3'd7) + enable_write_to_rom <= 1'b1; + else begin + enable_write_to_rom <= 1'b0; + indexseq <= indexseq + 3'd1; + end + end + else begin + enable_write_to_rom <= 1'b0; + indexseq <= 3'd0; + end + end + end + + always @* begin + dout_oe = 1'b0; + dout = {7'b0000000,enable_write_to_rom}; + if (iorq_n == 1'b0 && rd_n == 1'b0 && a[7:0] == IOADDR) + dout_oe = 1'b1; + end +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v b/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v new file mode 100644 index 00000000..ae0fb3c8 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v @@ -0,0 +1,217 @@ +`timescale 1ns / 1ps +`default_nettype none + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:06:40 03/19/2011 +// Design Name: +// Module Name: jace_on_fpga +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module jupiter_ace ( + input wire clk_65, + input wire clk_cpu, + input wire reset, + input wire ear, + output wire [7:0] filas, + input wire [4:0] columnas, + output wire video, + output wire hsync, + output wire vsync, + output wire mic, + output wire spk, + output wire sd_addr, + input wire sd_dout, + output wire sd_din, + output wire sd_we, + output wire sd_rd, + input wire sd_ready + ); + + wire [7:0] DinZ80; + wire [7:0] DoutZ80; + wire [15:0] AZ80; + + + wire iorq_n, mreq_n, rd_n, wr_n, wait_n, int_n; + wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe; + wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace; + wire [7:0] sram_data, cram_data; + wire [9:0] sram_addr, cram_addr; + + + wire enable_write_to_rom; + wire [7:0] dout_modulo_enable_write; + wire modulo_enable_write_oe; + + + assign filas = AZ80[15:8]; + + // Multiplexer + assign DinZ80 = (rom_enable == 1'b1)? dout_rom : + (sram_enable == 1'b1)? dout_sram : + (cram_enable == 1'b1)? dout_cram : + (uram_enable == 1'b1)? dout_uram : + (xram_enable == 1'b1)? dout_xram : + (eram_enable == 1'b1)? dout_eram : + (modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write : + (data_from_jace_oe == 1'b1)? data_from_jace : + sram_data | cram_data; // By default, this is what the data bus sees + + ram1k_dualport sram ( + .clk(clk_65), + .ce(sram_enable), + .a1(AZ80[9:0]), + .a2(sram_addr), + .din(DoutZ80), + .dout1(dout_sram), + .dout2(sram_data), + .we(~wr_n) + ); + + ram1k_dualport cram ( + .clk(clk_65), + .ce(cram_enable), + .a1(AZ80[9:0]), + .a2(cram_addr), + .din(DoutZ80), + .dout1(dout_cram), + .dout2(cram_data), + .we(~wr_n) + ); + + ram1k uram( + .clk(clk_65), + .ce(uram_enable), + .a(AZ80[9:0]), + .din(DoutZ80), + .dout(dout_uram), + .we(~wr_n) + ); + + ram16k xram( + .clk(clk_65), + .ce(xram_enable), + .a(AZ80[13:0]), + .din(DoutZ80), + .dout(dout_xram), + .we(~wr_n) + ); + +assign sd_addr = AZ80[13:0]; +//assign sd_dout = dout_eram; +assign sd_din = DoutZ80; +assign sd_we = ~wr_n; +assign sd_rd = eram_enable; + + +// ram32k eram(//16k for now//todo 32k +// .clk(clk_65), +// .ce(eram_enable), +// .a(AZ80[13:0]),//14 +// .din(DoutZ80), +// .dout(dout_eram), +// .we(~wr_n) +// ); + +// rom the_rom( +// .clk(clk_65), +// .a(AZ80[12:0]), +// .dout(dout_rom) +// ); + + rom2 the_rom( + .clk(clk_65), + .ce(rom_enable), + .a(AZ80[12:0]), + .din(DoutZ80), + .dout(dout_rom), + .we(~wr_n & enable_write_to_rom) + ); + + io_write_to_rom modulo_habilitador_escrituras ( + .clk(clk_65), + .a(AZ80), + .iorq_n(iorq_n), + .rd_n(rd_n), + .wr_n(wr_n), + .din(DoutZ80), + .dout(dout_modulo_enable_write), + .dout_oe(modulo_enable_write_oe), + .enable_write_to_rom(enable_write_to_rom) + ); + + + tv80n cpu( + // Outputs + .m1_n(), + .mreq_n(mreq_n), + .iorq_n(iorq_n), + .rd_n(rd_n), + .wr_n(wr_n), + .rfsh_n(), + .halt_n(), + .busak_n(), + .A(AZ80), + .dout(DoutZ80), + // Inputs + .di(DinZ80), + .reset_n(reset), + .clk(clk_cpu), + .wait_n(wait_n), + .int_n(int_n), + .nmi_n(1'b1), + .busrq_n(1'b1) + ); + + glue glogic ( + .clk(clk_65), + // CPU interface + .cpu_addr(AZ80), + .mreq_n(mreq_n), + .iorq_n(iorq_n), + .rd_n(rd_n), + .wr_n(wr_n), + .data_from_cpu(DoutZ80), + .data_to_cpu(data_from_jace), + .data_to_cpu_oe(data_from_jace_oe), + .wait_n(wait_n), + .int_n(int_n), + // CPU-RAM interface + .rom_enable(rom_enable), + .sram_enable(sram_enable), + .cram_enable(cram_enable), + .uram_enable(uram_enable), + .xram_enable(xram_enable), + .eram_enable(eram_enable), + // Screen RAM and Char RAM interface + .screen_addr(sram_addr), + .screen_data(sram_data), + .char_addr(cram_addr), + .char_data(cram_data), + // Devices + .kbdcols(columnas), + .ear(ear), + .spk(spk), + .mic(mic), + .video(video), + .hsync_pal(hsync), + .vsync_pal(vsync) + ); + + +endmodule + diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v b/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v new file mode 100644 index 00000000..e4f69fa6 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v @@ -0,0 +1,632 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:36:45 11/07/2015 +// Design Name: +// Module Name: keyboard +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module keyboard( + input wire clk, + input wire clkps2, + input wire dataps2, + input wire [7:0] rows, + output wire [4:0] columns, + output reg kbd_reset, + output reg kbd_nmi, + output reg kbd_mreset + ); + + initial begin + kbd_reset = 1'b1; + kbd_nmi = 1'b1; + kbd_mreset = 1'b1; + end + + // Teclas no extendidas +`define KEY_RELEASED 8'hf0 +`define KEY_EXTENDED 8'he0 +`define KEY_ESC 8'h76 +`define KEY_F1 8'h05 +`define KEY_F2 8'h06 +`define KEY_F3 8'h04 +`define KEY_F4 8'h0C +`define KEY_F5 8'h03 +`define KEY_F6 8'h0B +`define KEY_F7 8'h83 +`define KEY_F8 8'h0A +`define KEY_F9 8'h01 +`define KEY_F10 8'h09 +`define KEY_F11 8'h78 +`define KEY_F12 8'h07 + +`define KEY_BL 8'h0E +`define KEY_1 8'h16 +`define KEY_2 8'h1E +`define KEY_3 8'h26 +`define KEY_4 8'h25 +`define KEY_5 8'h2E +`define KEY_6 8'h36 +`define KEY_7 8'h3D +`define KEY_8 8'h3E +`define KEY_9 8'h46 +`define KEY_0 8'h45 +`define KEY_APOS 8'h4E +`define KEY_AEXC 8'h55 +`define KEY_BKSP 8'h66 + +`define KEY_TAB 8'h0D +`define KEY_Q 8'h15 +`define KEY_W 8'h1D +`define KEY_E 8'h24 +`define KEY_R 8'h2D +`define KEY_T 8'h2C +`define KEY_Y 8'h35 +`define KEY_U 8'h3C +`define KEY_I 8'h43 +`define KEY_O 8'h44 +`define KEY_P 8'h4D +`define KEY_CORCHA 8'h54 +`define KEY_CORCHC 8'h5B +`define KEY_ENTER 8'h5A + +`define KEY_CPSLK 8'h58 +`define KEY_A 8'h1C +`define KEY_S 8'h1B +`define KEY_D 8'h23 +`define KEY_F 8'h2B +`define KEY_G 8'h34 +`define KEY_H 8'h33 +`define KEY_J 8'h3B +`define KEY_K 8'h42 +`define KEY_L 8'h4B +`define KEY_NT 8'h4C +`define KEY_LLAVA 8'h52 +`define KEY_LLAVC 8'h5D + +`define KEY_LSHIFT 8'h12 +`define KEY_LT 8'h61 +`define KEY_Z 8'h1A +`define KEY_X 8'h22 +`define KEY_C 8'h21 +`define KEY_V 8'h2A +`define KEY_B 8'h32 +`define KEY_N 8'h31 +`define KEY_M 8'h3A +`define KEY_COMA 8'h41 +`define KEY_PUNTO 8'h49 +`define KEY_MENOS 8'h4A +`define KEY_RSHIFT 8'h59 + +`define KEY_LCTRL 8'h14 +`define KEY_LALT 8'h11 +`define KEY_SPACE 8'h29 + +`define KEY_KP0 8'h70 +`define KEY_KP1 8'h69 +`define KEY_KP2 8'h72 +`define KEY_KP3 8'h7A +`define KEY_KP4 8'h6B +`define KEY_KP5 8'h73 +`define KEY_KP6 8'h74 +`define KEY_KP7 8'h6C +`define KEY_KP8 8'h75 +`define KEY_KP9 8'h7D +`define KEY_KPPUNTO 8'h71 +`define KEY_KPMAS 8'h79 +`define KEY_KPMENOS 8'h7B +`define KEY_KPASTER 8'h7C + +`define KEY_BLKNUM 8'h77 +`define KEY_BLKSCR 8'h7E + +// Teclas extendidas (E0 + scancode) +`define KEY_WAKEUP 8'h5E +`define KEY_SLEEP 8'h3F +`define KEY_POWER 8'h37 +`define KEY_INS 8'h70 +`define KEY_SUP 8'h71 +`define KEY_HOME 8'h6C +`define KEY_END 8'h69 +`define KEY_PGU 8'h7D +`define KEY_PGD 8'h7A +`define KEY_UP 8'h75 +`define KEY_DOWN 8'h72 +`define KEY_LEFT 8'h6B +`define KEY_RIGHT 8'h74 +`define KEY_RCTRL 8'h14 +`define KEY_ALTGR 8'h11 +`define KEY_KPENTER 8'h5A +`define KEY_KPSLASH 8'h4A +`define KEY_PRTSCR 8'h7C + + + wire new_key_aval; + wire [7:0] scancode; + wire is_released; + wire is_extended; + + reg shift_pressed = 1'b0; + reg ctrl_pressed = 1'b0; + reg alt_pressed = 1'b0; + + ps2_port ps2_kbd ( + .clk(clk), // se recomienda 1 MHz <= clk <= 600 MHz + .enable_rcv(1'b1), // habilitar la maquina de estados de recepcion + .ps2clk_ext(clkps2), + .ps2data_ext(dataps2), + .kb_interrupt(new_key_aval), // a 1 durante 1 clk para indicar nueva tecla recibida + .scancode(scancode), // make o breakcode de la tecla + .released(is_released), // soltada=1, pulsada=0 + .extended(is_extended) // extendida=1, no extendida=0 + ); + + reg [4:0] matrix[0:7]; // 40-key matrix keyboard + initial begin + matrix[0] = 5'b11111; // C X Z SS CS + matrix[1] = 5'b11111; // G F D S A + matrix[2] = 5'b11111; // T R E W Q + matrix[3] = 5'b11111; // 5 4 3 2 1 + matrix[4] = 5'b11111; // 6 7 8 9 0 + matrix[5] = 5'b11111; // Y U I O P + matrix[6] = 5'b11111; // H J K L ENT + matrix[7] = 5'b11111; // V B N M SP + end + + assign columns = (matrix[0] | { {8{rows[0]}} }) & + (matrix[1] | { {8{rows[1]}} }) & + (matrix[2] | { {8{rows[2]}} }) & + (matrix[3] | { {8{rows[3]}} }) & + (matrix[4] | { {8{rows[4]}} }) & + (matrix[5] | { {8{rows[5]}} }) & + (matrix[6] | { {8{rows[6]}} }) & + (matrix[7] | { {8{rows[7]}} }); + + always @(posedge clk) begin + if (new_key_aval == 1'b1) begin + case (scancode) + // Special and control keys + `KEY_LSHIFT, + `KEY_RSHIFT: + shift_pressed <= ~is_released; + `KEY_LCTRL, + `KEY_RCTRL: + begin + ctrl_pressed <= ~is_released; + if (is_extended) + matrix[0][1] <= is_released; // Right control = Symbol shift + else + matrix[0][0] <= is_released; // Left control = Caps shift + end + `KEY_LALT: + alt_pressed <= ~is_released; + `KEY_KPPUNTO: + if (ctrl_pressed && alt_pressed) begin + kbd_reset <= is_released; + if (is_released == 1'b0) begin + matrix[0] <= 5'b11111; // C X Z SS CS + matrix[1] <= 5'b11111; // G F D S A + matrix[2] <= 5'b11111; // T R E W Q + matrix[3] <= 5'b11111; // 5 4 3 2 1 + matrix[4] <= 5'b11111; // 6 7 8 9 0 + matrix[5] <= 5'b11111; // Y U I O P + matrix[6] <= 5'b11111; // H J K L ENT + matrix[7] <= 5'b11111; // V B N M SP + end + end + `KEY_F5: + if (ctrl_pressed && alt_pressed) + kbd_nmi <= is_released; + `KEY_ENTER: + matrix[6][0] <= is_released; + `KEY_ESC: + begin + matrix[0][0] <= is_released; + matrix[7][0] <= is_released; + end + `KEY_BKSP: + if (ctrl_pressed && alt_pressed) begin + kbd_mreset <= is_released; + end + else begin + matrix[0][0] <= is_released; + matrix[4][0] <= is_released; + end + `KEY_CPSLK: + begin + matrix[0][0] <= is_released; + matrix[3][1] <= is_released; // CAPS LOCK + end + `KEY_F2: + begin + matrix[0][0] <= is_released; + matrix[3][0] <= is_released; // EDIT + end + + // Digits and puntuaction marks inside digits + `KEY_1: + begin + if (alt_pressed) begin + matrix[0][1] <= is_released; + matrix[1][1] <= is_released; // | + end + else if (shift_pressed) begin + matrix[0][1] <= is_released; + matrix[3][0] <= is_released; // ! + end + else + matrix[3][0] <= is_released; + + end + `KEY_2: + begin + if (alt_pressed) begin + matrix[0][1] <= is_released; + matrix[3][1] <= is_released; // @ + end + else if (shift_pressed) begin + matrix[0][1] <= is_released; + matrix[5][0] <= is_released; // " + end + else + matrix[3][1] <= is_released; + end + `KEY_3: + begin + if (!shift_pressed) + matrix[3][2] <= is_released; + else begin + matrix[0][1] <= is_released; + matrix[3][2] <= is_released; // # + end + end + `KEY_4: + begin + if (shift_pressed) begin + matrix[0][1] <= is_released; + matrix[3][3] <= is_released; // $ + end + else if (ctrl_pressed) begin + matrix[0][0] <= is_released; + matrix[3][3] <= is_released; // INV VIDEO + end + else + matrix[3][3] <= is_released; + end + `KEY_5: + begin + if (!shift_pressed) + matrix[3][4] <= is_released; + else begin + matrix[0][1] <= is_released; + matrix[3][4] <= is_released; // % + end + end + `KEY_6: + begin + if (!shift_pressed) + matrix[4][4] <= is_released; + else begin + matrix[0][1] <= is_released; + matrix[4][4] <= is_released; // & + end + end + `KEY_7: + begin + if (!shift_pressed) + matrix[4][3] <= is_released; + else begin + matrix[0][1] <= is_released; + matrix[7][4] <= is_released; // / + end + end + `KEY_8: + begin + if (!shift_pressed) + matrix[4][2] <= is_released; + else begin + matrix[0][1] <= is_released; + matrix[4][2] <= is_released; // ( + end + end + `KEY_9: + begin + if (shift_pressed) begin + matrix[0][1] <= is_released; + matrix[4][1] <= is_released; // ) + end + else if (ctrl_pressed) begin + matrix[0][0] <= is_released; + matrix[4][1] <= is_released; + end + else + matrix[4][1] <= is_released; + end + `KEY_0: + begin + if (!shift_pressed) + matrix[4][0] <= is_released; + else begin + matrix[0][1] <= is_released; + matrix[6][1] <= is_released; // = + end + end + + // Alphabetic characters + `KEY_Z: + begin + matrix[0][2] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_X: + begin + matrix[0][3] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_C: + begin + matrix[0][4] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_A: + begin + matrix[1][0] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_S: + begin + matrix[1][1] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_D: + begin + matrix[1][2] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_F: + begin + matrix[1][3] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_G: + begin + matrix[1][4] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_Q: + begin + matrix[2][0] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_W: + begin + matrix[2][1] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_E: + begin + matrix[2][2] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_R: + begin + matrix[2][3] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_T: + begin + matrix[2][4] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_P: + begin + matrix[5][0] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_O: + begin + matrix[5][1] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_I: + begin + matrix[5][2] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_U: + begin + matrix[5][3] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_Y: + begin + matrix[5][4] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_L: + begin + matrix[6][1] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_K: + begin + matrix[6][2] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_J: + begin + matrix[6][3] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_H: + begin + matrix[6][4] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_M: + begin + matrix[7][1] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_N: + begin + matrix[7][2] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_B: + begin + matrix[7][3] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + `KEY_V: + begin + matrix[7][4] <= is_released; + if (shift_pressed) + matrix[0][0] <= is_released; + end + + // Symbols + `KEY_APOS: + begin + matrix[0][1] <= is_released; + if (!shift_pressed) + matrix[4][3] <= is_released; + else + matrix[0][4] <= is_released; // ? + end + `KEY_CORCHA: + begin + matrix[0][1] <= is_released; + if (alt_pressed || shift_pressed) + matrix[5][4] <= is_released; // [ + else + matrix[6][4] <= is_released; // ^ + end + `KEY_CORCHC: + begin + matrix[0][1] <= is_released; + if (shift_pressed) + matrix[7][3] <= is_released; // * + else if (alt_pressed) + matrix[5][3] <= is_released; // ] + else + matrix[6][2] <= is_released; // + + end + `KEY_LLAVA: + begin + matrix[0][1] <= is_released; + if (alt_pressed || shift_pressed) + matrix[1][3] <= is_released; // { + else + matrix[0][3] <= is_released; // pound + end + `KEY_LLAVC: + begin + matrix[0][1] <= is_released; + if (alt_pressed || shift_pressed) + matrix[1][4] <= is_released; // } + else + matrix[5][2] <= is_released; // copyright + end + `KEY_COMA: + begin + matrix[0][1] <= is_released; + if (!shift_pressed) + matrix[7][2] <= is_released; + else + matrix[5][1] <= is_released; // ; + end + `KEY_PUNTO: + begin + matrix[0][1] <= is_released; + if (!shift_pressed) + matrix[7][1] <= is_released; + else + matrix[0][2] <= is_released; // : + end + `KEY_MENOS: + begin + matrix[0][1] <= is_released; + if (!shift_pressed) + matrix[6][3] <= is_released; // + else + matrix[4][0] <= is_released; // _ + end + `KEY_LT: + begin + matrix[0][1] <= is_released; + if (!shift_pressed) + matrix[2][3] <= is_released; // < + else + matrix[2][4] <= is_released; // > + end + `KEY_BL: + begin + matrix[0][1] <= is_released; + matrix[1][2] <= is_released; // \ + end + `KEY_SPACE: + matrix[7][0] <= is_released; + + // Cursor keys + `KEY_UP: + begin + matrix[0][0] <= is_released; + matrix[4][4] <= is_released; + end + `KEY_DOWN: + begin + matrix[0][0] <= is_released; + matrix[4][3] <= is_released; + end + `KEY_LEFT: + begin + matrix[0][0] <= is_released; + matrix[3][4] <= is_released; + end + `KEY_RIGHT: + begin + matrix[0][0] <= is_released; + matrix[4][2] <= is_released; + end + endcase + end + end +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v b/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ab9ef8ad --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v @@ -0,0 +1,532 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // ARM -> FPGA download + input ioctl_force_erase, + output reg ioctl_download = 0, // signal indicating an active download + output reg ioctl_erasing = 0, // signal indicating an active erase + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr = 0, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + case(ioctl_index) + 0: addr <= 'h080000; // BOOT ROM + 'h01: addr <= 'h000100; // ROM file + 'h41: addr <= 'h000100; // COM file + 'h81: addr <= 'h000000; // C00 file + 'hC1: addr <= 'h010000; // EDD file + default: addr <= 'h100000; // FDD file + endcase + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +reg [24:0] erase_mask; +wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask; + +always@(posedge clk_sys) begin + reg rclkD, rclkD2; + reg old_force = 0; + reg [5:0] erase_clk_div; + reg [24:0] end_addr; + reg erase_trigger = 0; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wr <= 0; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wr <= 1; + end + + if(ioctl_download) begin + old_force <= 0; + ioctl_erasing <= 0; + erase_trigger <= (ioctl_index == 1); + end else begin + + old_force <= ioctl_force_erase; + + // start erasing + if(erase_trigger) begin + erase_trigger <= 0; + erase_mask <= 'hFFFF; + end_addr <= 'h0100; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if((ioctl_force_erase & ~old_force)) begin + erase_trigger <= 0; + ioctl_addr <= 'h1FFFFFF; + erase_mask <= 'h1FFFFFF; + end_addr <= 'h0050000; + erase_clk_div <= 1; + ioctl_erasing <= 1; + end else if(ioctl_erasing) begin + erase_clk_div <= erase_clk_div + 1'd1; + if(!erase_clk_div) begin + if(next_erase == end_addr) ioctl_erasing <= 0; + else begin + ioctl_addr <= next_erase; + ioctl_dout <= 0; + ioctl_wr <= 1; + end + end + end + end +end + +endmodule \ No newline at end of file diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v b/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip b/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v b/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v new file mode 100644 index 00000000..47bde791 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v @@ -0,0 +1,404 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + areset, + inclk0, + c0, + c1, + c2, + c3, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output c3; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire3; + wire [0:0] sub_wire8 = 1'h0; + wire [2:2] sub_wire5 = sub_wire0[2:2]; + wire [0:0] sub_wire4 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire c3 = sub_wire2; + wire locked = sub_wire3; + wire c0 = sub_wire4; + wire c2 = sub_wire5; + wire sub_wire6 = inclk0; + wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire7), + .clk (sub_wire0), + .locked (sub_wire3), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 26, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 54, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 13, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 108, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 13, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 27, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 104, + altpll_component.clk3_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "54" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "26.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.500000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "3.250000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "104.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "26" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "13" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "13" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "104" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "26.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.50000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "3.25000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "104.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "26" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "13" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "104" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/ps2_port.v b/Jupiter Cantab - JupiterACE_MiST/rtl/ps2_port.v new file mode 100644 index 00000000..b4064f61 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/ps2_port.v @@ -0,0 +1,124 @@ +`timescale 1ns / 1ps +`default_nettype none + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:16:31 12/26/2014 +// Design Name: +// Module Name: ps2_port +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ps2_port ( + input wire clk, // se recomienda 1 MHz <= clk <= 600 MHz + input wire enable_rcv, // habilitar la maquina de estados de recepcion + input wire ps2clk_ext, + input wire ps2data_ext, + output wire kb_interrupt, // a 1 durante 1 clk para indicar nueva tecla recibida + output reg [7:0] scancode, // make o breakcode de la tecla + output wire released, // soltada=1, pulsada=0 + output wire extended // extendida=1, no extendida=0 + ); + + `define RCVSTART 2'b00 + `define RCVDATA 2'b01 + `define RCVPARITY 2'b10 + `define RCVSTOP 2'b11 + + reg [7:0] key = 8'h00; + + // Fase de sincronizacion de señales externas con el reloj del sistema + reg [1:0] ps2clk_synchr; + reg [1:0] ps2dat_synchr; + wire ps2clk = ps2clk_synchr[1]; + wire ps2data = ps2dat_synchr[1]; + always @(posedge clk) begin + ps2clk_synchr[0] <= ps2clk_ext; + ps2clk_synchr[1] <= ps2clk_synchr[0]; + ps2dat_synchr[0] <= ps2data_ext; + ps2dat_synchr[1] <= ps2dat_synchr[0]; + end + + // De-glitcher. Sólo detecto flanco de bajada + reg [15:0] negedgedetect = 16'h0000; + always @(posedge clk) begin + negedgedetect <= {negedgedetect[14:0], ps2clk}; + end + wire ps2clkedge = (negedgedetect == 16'hF000)? 1'b1 : 1'b0; + + // Paridad instantánea de los bits recibidos + wire paritycalculated = ^key; + + // Contador de time-out. Al llegar a 65536 ciclos sin que ocurra + // un flanco de bajada en PS2CLK, volvemos al estado inicial + reg [15:0] timeoutcnt = 16'h0000; + + reg [1:0] state = `RCVSTART; + reg [1:0] regextended = 2'b00; + reg [1:0] regreleased = 2'b00; + reg rkb_interrupt = 1'b0; + assign released = regreleased[1]; + assign extended = regextended[1]; + assign kb_interrupt = rkb_interrupt; + + always @(posedge clk) begin + if (rkb_interrupt == 1'b1) begin + rkb_interrupt <= 1'b0; + end + if (ps2clkedge && enable_rcv) begin + timeoutcnt <= 16'h0000; + if (state == `RCVSTART && ps2data == 1'b0) begin + state <= `RCVDATA; + key <= 8'h80; + end + else if (state == `RCVDATA) begin + key <= {ps2data, key[7:1]}; + if (key[0] == 1'b1) begin + state <= `RCVPARITY; + end + end + else if (state == `RCVPARITY) begin + if (ps2data^paritycalculated == 1'b1) begin + state <= `RCVSTOP; + end + else begin + state <= `RCVSTART; + end + end + else if (state == `RCVSTOP) begin + state <= `RCVSTART; + if (ps2data == 1'b1) begin + scancode <= key; + if (key == 8'hE0) begin + regextended <= 2'b01; + end + else if (key == 8'hF0) begin + regreleased <= 2'b01; + end + else begin + regextended <= {regextended[0], 1'b0}; + regreleased <= {regreleased[0], 1'b0}; + rkb_interrupt <= 1'b1; + end + end + end + end + else begin + timeoutcnt <= timeoutcnt + 1; + if (timeoutcnt == 16'hFFFF) begin + state <= `RCVSTART; + end + end + end +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/rom_ram.v b/Jupiter Cantab - JupiterACE_MiST/rtl/rom_ram.v new file mode 100644 index 00000000..8483e4ee --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/rom_ram.v @@ -0,0 +1,131 @@ +`timescale 1ns / 1ps +`default_nettype none +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04:47:33 03/21/2011 +// Design Name: +// Module Name: memorias +// Project Name: +// Target Device_ns: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module rom ( + input wire clk, + input wire [12:0] a, + output reg [7:0] dout + ); + + reg [7:0] mem[0:8191]; + integer i; + initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM + $readmemh ("ace.hex", mem, 0); + end + + always @(posedge clk) begin + dout <= mem[a[12:0]]; + end +endmodule + + +module rom2 ( + input wire clk, + input wire ce, + input wire [12:0] a, + input wire we, + input wire [7:0] din, + output reg [7:0] dout + ); + + reg [7:0] mem[0:8191]; + integer i; + initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM + $readmemh ("ace.hex", mem, 0); + end + + always @(posedge clk) begin + dout <= mem[a]; + if (we == 1'b1 && ce == 1'b1) + mem[a] <= din; + end +endmodule + +module ram1k ( + input wire clk, + input wire ce, + input wire [9:0] a, + input wire [7:0] din, + output reg [7:0] dout, + input wire we + ); + + reg [7:0] mem[0:1023]; + always @(posedge clk) begin + dout <= mem[a]; + if (we == 1'b1 && ce == 1'b1) + mem[a] <= din; + end +endmodule + +module ram1k_dualport( + input wire clk, + input wire ce, + input wire [9:0] a1, + input wire [9:0] a2, + input wire [7:0] din, + output reg [7:0] dout1, + output reg [7:0] dout2, + input wire we + ); + + reg [7:0] mem[0:1023]; + always @(posedge clk) begin + dout2 <= mem[a2]; + dout1 <= mem[a1]; + if (we == 1'b1 && ce == 1'b1) + mem[a1] <= din; + end +endmodule + +module ram16k ( + input wire clk, + input wire ce, + input wire [13:0] a, + input wire [7:0] din, + output reg [7:0] dout, + input wire we + ); + + reg [7:0] mem[0:16383]; + always @(posedge clk) begin + dout <= mem[a]; + if (we == 1'b1 && ce == 1'b1) + mem[a] <= din; + end +endmodule + +module ram32k ( + input wire clk, + input wire ce, + input wire [14:0] a, + input wire [7:0] din, + output reg [7:0] dout, + input wire we + ); + + reg [7:0] mem[0:32767]; + always @(posedge clk) begin + dout <= mem[a]; + if (we == 1'b1 && ce == 1'b1) + mem[a] <= din; + end +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/scandoubler.v b/Jupiter Cantab - JupiterACE_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..5a3ccd17 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/scandoubler.v @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/sigma_delta_dac.v b/Jupiter Cantab - JupiterACE_MiST/rtl/sigma_delta_dac.v new file mode 100644 index 00000000..29daea6e --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=0) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= 1; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= ~SigmaLatch[MSBI+2]; + end +end + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/sram.v b/Jupiter Cantab - JupiterACE_MiST/rtl/sram.v new file mode 100644 index 00000000..f428097a --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/sram.v @@ -0,0 +1,286 @@ +// +// sram.v +// +// Static RAM controller implementation using SDRAM MT48LC16M16A2 +// +// Copyright (c) 2015 Sorgelig +// +// Some parts of SDRAM code used from project: +// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + output SDRAM_CKE, // clock enable + + // cpu/chipset interface + input init, // reset to initialize RAM + input clk_sdram, + + input [24:0] addr, // 25 bit address + + output reg [7:0] dout, // data output to cpu + input [7:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output reg ready +); + +assign SDRAM_nCS = command[3]; +assign SDRAM_nRAS = command[2]; +assign SDRAM_nCAS = command[1]; +assign SDRAM_nWE = command[0]; +assign SDRAM_CKE = cke; + + +// no burst configured +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd3; // 2 for < 100MHz, 3 for >100MHz +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +parameter sdram_startup_cycles = 14'd10100; // -- 100us, plus a little more, @ 100MHz +parameter cycles_per_refresh = 14'd1524; // (64000*100)/4196-1 Calc'd as (64ms @ 100MHz)/ 4196 rose +parameter startup_refresh_max = 14'b11111111111111; + +reg [13:0] startup_refresh_count = startup_refresh_max-sdram_startup_cycles; +wire pending_refresh = |startup_refresh_count[13:11]; +wire forcing_refresh = |startup_refresh_count[13:12]; + +localparam STATE_STARTUP = 0; +localparam STATE_OPEN_1 = 1; +localparam STATE_OPEN_2 = 2; +localparam STATE_WRITE = 3; +localparam STATE_READ = 4; +localparam STATE_IDLE = 5; +localparam STATE_IDLE_1 = 6; +localparam STATE_IDLE_2 = 7; +localparam STATE_IDLE_3 = 8; +localparam STATE_IDLE_4 = 9; +localparam STATE_IDLE_5 = 10; +localparam STATE_IDLE_6 = 11; +localparam STATE_IDLE_7 = 12; +localparam STATE_IDLE_8 = 13; + +// SDRAM commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [4:0] state = STATE_STARTUP; +reg [3:0] command = CMD_INHIBIT; +reg cke = 0; + +parameter data_ready_delay_high = CAS_LATENCY+1; +reg [data_ready_delay_high:0] data_ready_delay; + +always @(posedge clk_sdram) begin + reg old_we, old_rd, new_we, new_rd; + + reg [7:0] new_data; + reg [24:0] save_addr; + reg save_we; + reg save_addr0; + reg avail; + + command <= CMD_NOP; + + startup_refresh_count <= startup_refresh_count+1'b1; + + if(data_ready_delay[0]) begin + dout <= save_addr0 ? SDRAM_DQ[15:8] : SDRAM_DQ[7:0]; + avail <= 1; + ready <= 1; + end + + data_ready_delay <= {1'b0, data_ready_delay[data_ready_delay_high:1]}; + + case(state) + STATE_STARTUP: begin + //------------------------------------------------------------------------ + //-- This is the initial startup state, where we wait for at least 100us + //-- before starting the start sequence + //-- + //-- The initialisation is sequence is + //-- * de-assert SDRAM_CKE + //-- * 100us wait, + //-- * assert SDRAM_CKE + //-- * wait at least one cycle, + //-- * PRECHARGE + //-- * wait 2 cycles + //-- * REFRESH, + //-- * tREF wait + //-- * REFRESH, + //-- * tREF wait + //-- * LOAD_MODE_REG + //-- * 2 cycles wait + //------------------------------------------------------------------------ + cke <= 1; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + SDRAM_DQML <= 1; + SDRAM_DQMH <= 1; + SDRAM_A <= 0; + SDRAM_BA <= 0; + + // All the commands during the startup are NOPS, except these + if(startup_refresh_count == startup_refresh_max-31) begin + // ensure all rows are closed + command <= CMD_PRECHARGE; + SDRAM_A[10] <= 1; // all banks + SDRAM_BA <= 2'b00; + end else if (startup_refresh_count == startup_refresh_max-23) begin + // these refreshes need to be at least tREF (66ns) apart + command <= CMD_AUTO_REFRESH; + end else if (startup_refresh_count == startup_refresh_max-15) + command <= CMD_AUTO_REFRESH; + else if (startup_refresh_count == startup_refresh_max-7) begin + // Now load the mode register + command <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + end + + //------------------------------------------------------ + //-- if startup is complete then go into idle mode, + //-- get prepared to accept a new command, and schedule + //-- the first refresh cycle + //------------------------------------------------------ + if(!startup_refresh_count) begin + state <= STATE_IDLE; + avail <= 1; + ready <= 1; + startup_refresh_count <= 14'd2048 - cycles_per_refresh + 1'd1; + end + end + + STATE_IDLE_8: state <= STATE_IDLE_7; + STATE_IDLE_7: state <= STATE_IDLE_6; + STATE_IDLE_6: state <= STATE_IDLE_5; + STATE_IDLE_5: state <= STATE_IDLE_4; + STATE_IDLE_4: state <= STATE_IDLE_3; + STATE_IDLE_3: state <= STATE_IDLE_2; + STATE_IDLE_2: state <= STATE_IDLE_1; + STATE_IDLE_1: begin + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + state <= STATE_IDLE; + if(pending_refresh) begin + //------------------------------------------------------------------------ + //-- Start the refresh cycle. + //-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz + //------------------------------------------------------------------------ + state <= STATE_IDLE_8; + command <= CMD_AUTO_REFRESH; + startup_refresh_count <= startup_refresh_count - cycles_per_refresh + 1'd1; + end + end + + STATE_IDLE: begin + // Priority is to issue a refresh if one is outstanding + if(forcing_refresh) state <= STATE_IDLE_1; + else if(avail & (new_rd | new_we)) begin + save_addr<= addr; + save_we <= new_we; + avail <= 0; + new_we <= 0; + new_rd <= 0; + state <= STATE_OPEN_1; + command <= CMD_ACTIVE; + SDRAM_A <= addr[22:10]; + SDRAM_BA <= addr[24:23]; + end + + SDRAM_DQML <= 1; + SDRAM_DQMH <= 1; + end + + //-------------------------------------------- + //-- Opening the row ready for reads or writes + //-------------------------------------------- + // ACTIVE-to-READ or WRITE delay >20ns (-75) + STATE_OPEN_1: state <= STATE_OPEN_2; + STATE_OPEN_2: begin + SDRAM_A <= {4'b0010, save_addr[9:1]}; + SDRAM_DQML <= save_addr[0]; + SDRAM_DQMH <= ~save_addr[0]; + state <= (save_we) ? STATE_WRITE : STATE_READ; + end + + //---------------------------------- + //-- Processing the read transaction + //---------------------------------- + STATE_READ: begin + state <= STATE_IDLE_5; + command <= CMD_READ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + + // Schedule reading the data values off the bus + data_ready_delay[data_ready_delay_high] <= 1; + save_addr0 <= save_addr[0]; + end + + //------------------------------------------------------------------ + // -- Processing the write transaction + //------------------------------------------------------------------- + STATE_WRITE: begin + state <= STATE_IDLE_5; + command <= CMD_WRITE; + SDRAM_DQ <= {new_data, new_data}; + avail <= 1; + ready <= 1; + end + + //------------------------------------------------------------------- + //-- We should never get here, but if we do then reset the memory + //------------------------------------------------------------------- + default: begin + state <= STATE_STARTUP; + avail <= 0; + startup_refresh_count <= startup_refresh_max-sdram_startup_cycles; + end + endcase + + if(init) begin // Sync reset + state <= STATE_STARTUP; + avail <= 0; + startup_refresh_count <= startup_refresh_max-sdram_startup_cycles; + end + + old_we <= we; + if(we & ~old_we) {ready, new_we, new_data} <= {1'b0, 1'b1, din}; + + old_rd <= rd; + if(rd & ~old_rd) {ready, new_rd} <= {1'b0, 1'b1}; +end + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv b/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..ec953e53 --- /dev/null +++ b/Jupiter Cantab - JupiterACE_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd7, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Jupiter Cantab - JupiterACE_MiST/snapshot/ace.rbf b/Jupiter Cantab - JupiterACE_MiST/snapshot/ace.rbf new file mode 100644 index 00000000..5a2c2c34 Binary files /dev/null and b/Jupiter Cantab - JupiterACE_MiST/snapshot/ace.rbf differ diff --git a/Nintendo - Gameboy_Mist/Release/gb.rbf b/Nintendo - Gameboy_Mist/Release/gb.rbf new file mode 100644 index 00000000..ae8fab57 Binary files /dev/null and b/Nintendo - Gameboy_Mist/Release/gb.rbf differ diff --git a/Nintendo - Gameboy_Mist/clean.bat b/Nintendo - Gameboy_Mist/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Nintendo - Gameboy_Mist/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Nintendo - Gameboy_Mist/gb.qpf b/Nintendo - Gameboy_Mist/gb.qpf new file mode 100644 index 00000000..ed107778 --- /dev/null +++ b/Nintendo - Gameboy_Mist/gb.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 10.1 Build 153 11/29/2010 SJ Full Version +# Date created = 11:11:11 June 13, 2011 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "10.1" +DATE = "11:11:11 June 13, 2011" + +# Revisions + +PROJECT_REVISION = "gb" diff --git a/Nintendo - Gameboy_Mist/gb.qsf b/Nintendo - Gameboy_Mist/gb.qsf new file mode 100644 index 00000000..5c3cfa1d --- /dev/null +++ b/Nintendo - Gameboy_Mist/gb.qsf @@ -0,0 +1,191 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2011 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 11.0 Build 157 04/27/2011 SJ Full Version +# Date created = 17:14:01 April 10, 2012 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# led_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY gb_mist +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:14:01 APRIL 10, 2012" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_22 -to CLOCK_50[0] +set_location_assignment PIN_23 -to CLOCK_50[1] +set_location_assignment PIN_128 -to CLOCK_32[0] +set_location_assignment PIN_129 -to CLOCK_32[1] +set_location_assignment PIN_54 -to CLOCK_27[0] +set_location_assignment PIN_55 -to CLOCK_27[1] +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_46 -to UART_TX +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 + +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + + +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "FAST FIT" +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name SYSTEMVERILOG_FILE rtl/gb_mist.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/gb.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/lcd.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprites.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprite_sort.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprite.sv +set_global_assignment -name VHDL_FILE rtl/gbc_snd.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/timer.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/zpram.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/vram.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/iram.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/data_io.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv +set_global_assignment -name VHDL_FILE rtl/BROM.vhd +set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd +set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd +set_global_assignment -name VHDL_FILE rtl/t80/GBse.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Nintendo - Gameboy_Mist/readme.txt b/Nintendo - Gameboy_Mist/readme.txt new file mode 100644 index 00000000..f8c9535e --- /dev/null +++ b/Nintendo - Gameboy_Mist/readme.txt @@ -0,0 +1,43 @@ +--------------------------------------------------------------------------------- +-- +-- Gameboy Core for MiST by Till Harbaum +-- Changed by Gehstock +-- 19 December 2017 +-- +--------------------------------------------------------------------------------- + +-- This is source code of a gameboy implementation for the MIST. + + + +-- It's based on the [t80](http://opencores.com/project,t80) CPU core. + +-- A minor +fix was needed for the "LD ($FF00+C)" instruction. + + + +-- The audio implementation has been taken from the PACE framework. + +-- The +original file is available in the [pacedev svn] +-- (https://svn.pacedev.net/repos/pace/sw/src/component/sound/gb/gbc_snd.vhd). + + +--------------------------------------------------------------------------------- +-- +-- +-- Keyboard inputs : +-- +-- ESC: : Start +-- TAB: : Select +-- SPACE : Button A +-- LALT : Button B +-- ARROW KEYS : Movements +-- +-- Joystick support. +-- +--------------------------------------------------------------------------------- + +ToDo: Mappers + diff --git a/Nintendo - Gameboy_Mist/rtl/BROM.vhd b/Nintendo - Gameboy_Mist/rtl/BROM.vhd new file mode 100644 index 00000000..ae9ac80b --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/BROM.vhd @@ -0,0 +1,56 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity BROM is +port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of BROM is + type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); + signal ROM : ROM_ARRAY := ( + x"31",x"FE",x"FF",x"AF",x"21",x"FF",x"9F",x"32", -- 0x0000 + x"CB",x"7C",x"20",x"FB",x"21",x"26",x"FF",x"0E", -- 0x0008 + x"11",x"3E",x"80",x"32",x"E2",x"0C",x"3E",x"F3", -- 0x0010 + x"E2",x"32",x"3E",x"77",x"77",x"3E",x"FC",x"E0", -- 0x0018 + x"47",x"F0",x"50",x"FE",x"42",x"28",x"75",x"11", -- 0x0020 + x"04",x"01",x"21",x"10",x"80",x"1A",x"4F",x"CD", -- 0x0028 + x"A0",x"00",x"CD",x"A0",x"00",x"13",x"7B",x"FE", -- 0x0030 + x"34",x"20",x"F2",x"11",x"B2",x"00",x"06",x"08", -- 0x0038 + x"1A",x"22",x"22",x"13",x"05",x"20",x"F9",x"3E", -- 0x0040 + x"19",x"EA",x"10",x"99",x"21",x"2F",x"99",x"0E", -- 0x0048 + x"0C",x"3D",x"28",x"08",x"32",x"0D",x"20",x"F9", -- 0x0050 + x"2E",x"0F",x"18",x"F3",x"67",x"3E",x"64",x"57", -- 0x0058 + x"E0",x"42",x"3E",x"91",x"E0",x"40",x"04",x"1E", -- 0x0060 + x"02",x"0E",x"0C",x"F0",x"44",x"FE",x"90",x"20", -- 0x0068 + x"FA",x"0D",x"20",x"F7",x"1D",x"20",x"F2",x"0E", -- 0x0070 + x"13",x"24",x"7C",x"1E",x"83",x"FE",x"62",x"28", -- 0x0078 + x"06",x"1E",x"C1",x"FE",x"64",x"20",x"06",x"7B", -- 0x0080 + x"E2",x"0C",x"3E",x"87",x"E2",x"F0",x"42",x"90", -- 0x0088 + x"E0",x"42",x"15",x"20",x"D2",x"05",x"20",x"64", -- 0x0090 + x"16",x"20",x"18",x"CB",x"E0",x"40",x"18",x"5C", -- 0x0098 + x"06",x"04",x"C5",x"CB",x"11",x"17",x"C1",x"CB", -- 0x00A0 + x"11",x"17",x"05",x"20",x"F5",x"22",x"22",x"22", -- 0x00A8 + x"22",x"C9",x"3C",x"42",x"A5",x"81",x"A5",x"99", -- 0x00B0 + x"42",x"3C",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00B8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E0 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E8 + x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00F0 + x"FF",x"FF",x"FF",x"FF",x"3E",x"01",x"E0",x"50" -- 0x00F8 + ); + +begin +process(clk) +begin + if rising_edge(clk) then + data <= ROM (to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Nintendo - Gameboy_Mist/rtl/build_id.sv b/Nintendo - Gameboy_Mist/rtl/build_id.sv new file mode 100644 index 00000000..1d53a3f2 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/build_id.sv @@ -0,0 +1,2 @@ +`define BUILD_DATE "171221" +`define BUILD_TIME "172231" diff --git a/Nintendo - Gameboy_Mist/rtl/build_id.tcl b/Nintendo - Gameboy_Mist/rtl/build_id.tcl new file mode 100644 index 00000000..be673dac --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.sv" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Nintendo - Gameboy_Mist/rtl/dac.sv b/Nintendo - Gameboy_Mist/rtl/dac.sv new file mode 100644 index 00000000..5dea333e --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/dac.sv @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module dac #(parameter MSBI=15, parameter INV=1'b1) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= INV; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= SigmaLatch[MSBI+2] ^ INV; + end +end + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/data_io.sv b/Nintendo - Gameboy_Mist/rtl/data_io.sv new file mode 100644 index 00000000..c1a3ffca --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/data_io.sv @@ -0,0 +1,118 @@ +// +// data_io.v +// +// io controller writable ram for the MiST board +// https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module data_io ( + // io controller spi interface + input sck, + input ss, + input sdi, + + output downloading, // signal indicating an active download + output reg [4:0] index, // menu index used to upload the file + + // external ram interface + input clk, + output reg wr, + output reg [23:0] addr, + output reg [15:0] data +); + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg [14:0] sbuf; +reg [7:0] cmd; +reg [4:0] cnt; +reg rclk; + +reg [23:0] laddr; +reg [15:0] ldata; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +assign downloading = downloading_reg; +reg downloading_reg = 1'b0; + +// data_io has its own SPI interface to the io controller +always@(posedge sck, posedge ss) begin + if(ss == 1'b1) + cnt <= 5'd0; + else begin + rclk <= 1'b0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 23) + sbuf <= { sbuf[13:0], sdi}; + + // count 0-7 8-15 16-23 8-15 16-23 ... + if(cnt < 23) cnt <= cnt + 4'd1; + else cnt <= 4'd8; + + // finished command byte + if(cnt == 7) + cmd <= {sbuf[6:0], sdi}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(sdi) begin + // download rom to address 0 + laddr <= 24'h0 - 24'd1; + downloading_reg <= 1'b1; + end else + downloading_reg <= 1'b0; + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 23)) begin + ldata <= {sbuf, sdi}; + laddr <= laddr + 24'd1; + rclk <= 1'b1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) + index <= {sbuf[3:0], sdi}; + end +end + +reg rclkD, rclkD2; +always@(posedge clk) begin + // bring all signals from spi clock domain into local clock domain + rclkD <= rclk; + rclkD2 <= rclkD; + wr <= 1'b0; + + if(rclkD && !rclkD2) begin + addr <= laddr; + data <= ldata; + wr <= 1'b1; + end +end + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/gb.sv b/Nintendo - Gameboy_Mist/rtl/gb.sv new file mode 100644 index 00000000..e31a9936 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/gb.sv @@ -0,0 +1,359 @@ +// +// gb.v +// +// Gameboy for the MIST board https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module gb ( + input reset, + input clk, + + input fast_boot, + input [7:0] joystick, + + // cartridge interface + // can adress up to 1MB ROM + output [15:0] cart_addr, + output cart_rd, + output cart_wr, + input [7:0] cart_do, + output [7:0] cart_di, + + // audio + output [15:0] audio_l, + output [15:0] audio_r, + + // lcd interface + output lcd_clkena, + output [1:0] lcd_data, + output [1:0] lcd_mode, + output lcd_on +); + +// include cpu +wire [15:0] cpu_addr; +wire [7:0] cpu_do; + +wire sel_timer = (cpu_addr[15:4] == 12'hff0) && (cpu_addr[3:2] == 2'b01); +wire sel_video_reg = cpu_addr[15:4] == 12'hff4; +wire sel_video_oam = cpu_addr[15:8] == 8'hfe; +wire sel_joy = cpu_addr == 16'hff00; // joystick controller +wire sel_rom = !cpu_addr[15]; // lower 32k are rom +wire sel_cram = cpu_addr[15:13] == 3'b101; // 8k cart ram at $a000 +wire sel_vram = cpu_addr[15:13] == 3'b100; // 8k video ram at $8000 +wire sel_ie = cpu_addr == 16'hffff; // interupt enable +wire sel_if = cpu_addr == 16'hff0f; // interupt flag +wire sel_iram = (cpu_addr[15:14] == 2'b11) && (cpu_addr[15:8] != 8'hff); // 8k internal ram at $c000 +wire sel_zpram = (cpu_addr[15:7] == 9'b111111111) && // 127 bytes zero pageram at $ff80 + (cpu_addr != 16'hffff); +wire sel_audio = (cpu_addr[15:8] == 8'hff) && // audio reg ff10 - ff3f + ((cpu_addr[7:5] == 3'b001) || (cpu_addr[7:4] == 4'b0001)); + +// the boot roms sees a special $42 flag in $ff50 if it's supposed to to a fast boot +wire sel_fast = fast_boot && cpu_addr == 16'hff50 && boot_rom_enabled; + +// http://gameboy.mongenel.com/dmg/asmmemmap.html +wire [7:0] cpu_di = + irq_ack?irq_vec: + sel_fast?8'h42: // fast boot flag + sel_joy?joy_do: // joystick register + sel_timer?timer_do: // timer registers + sel_video_reg?video_do: // video registers + sel_video_oam?video_do: // video object attribute memory + sel_audio?audio_do: // audio registers + sel_rom?rom_do: // boot rom + cartridge rom + sel_cram?rom_do: // cartridge ram + sel_vram?vram_do: // vram + sel_zpram?zpram_do: // zero page ram + sel_iram?iram_do: // internal ram + sel_ie?{3'b000, ie_r}: // interrupt enable register + sel_if?{3'b000, if_r}: // interrupt flag register + 8'hff; + +wire cpu_wr_n; +wire cpu_rd_n; +wire cpu_iorq_n; +wire cpu_m1_n; +wire cpu_mreq_n; + +GBse cpu ( + .RESET_n ( !reset ), + .CLK_n ( clk ), + .CLKEN ( 1'b1 ), + .WAIT_n ( 1'b1 ), + .INT_n ( irq_n ), + .NMI_n ( 1'b1 ), + .BUSRQ_n ( 1'b1 ), + .M1_n ( cpu_m1_n ), + .MREQ_n ( cpu_mreq_n ), + .IORQ_n ( cpu_iorq_n ), + .RD_n ( cpu_rd_n ), + .WR_n ( cpu_wr_n ), + .RFSH_n ( ), + .HALT_n ( ), + .BUSAK_n ( ), + .A ( cpu_addr ), + .DI ( cpu_di ), + .DO ( cpu_do ) +); + +// -------------------------------------------------------------------- +// ------------------------------ audio ------------------------------- +// -------------------------------------------------------------------- + +wire audio_rd = !cpu_rd_n && sel_audio; +wire audio_wr = !cpu_wr_n && sel_audio; +wire [7:0] audio_do; + +gbc_snd audio ( + .clk ( clk ), + .reset ( reset ), + + .s1_read ( audio_rd ), + .s1_write ( audio_wr ), + .s1_addr ( cpu_addr[5:0] ), + .s1_readdata ( audio_do ), + .s1_writedata ( cpu_do ), + + .snd_left ( audio_l ), + .snd_right ( audio_r ) +); + +// -------------------------------------------------------------------- +// ------------------------------ inputs ------------------------------ +// -------------------------------------------------------------------- + +wire [3:0] joy_p4 = { !joystick[2], !joystick[3], !joystick[1], !joystick[0] }; +wire [3:0] joy_p5 = { !joystick[7], !joystick[6], !joystick[5], !joystick[4] }; +reg [1:0] p54; + +always @(posedge clk) begin + if(reset) + p54 <= 2'b11; + else if(sel_joy && !cpu_wr_n) + p54 <= cpu_do[5:4]; +end + +wire [7:0] joy_do = { 2'b11, p54, + ((!p54[0])?joy_p4:4'hf) & ((!p54[1])?joy_p5:4'hf) }; + +// -------------------------------------------------------------------- +// ---------------------------- interrupts ---------------------------- +// -------------------------------------------------------------------- + +// interrupt flags are set when the event happens or when the cpu writes +// the register to 1. The "highest" one active is cleared when the cpu +// runs an interrupt ack cycle or when it writes a 0 to the register + +wire irq_ack = !cpu_iorq_n && !cpu_m1_n; + +// latch irq vector at the begin of the irq ack +reg [7:0] irq_vec; +always @(posedge irq_ack) + irq_vec <= + if_r[0]?8'h40: // vsync + if_r[1]?8'h48: // lcdc + if_r[2]?8'h50: // timer + if_r[3]?8'h58: // serial + if_r[4]?8'h60: // input + 8'h55; + +wire vs = (lcd_mode == 2'b01); +reg vsD, vsD2; +reg [3:0] inputD, inputD2; + +// irq is low when an enable irq is active +wire irq_n = !(ie_r & if_r); + +reg [4:0] if_r; +reg [4:0] ie_r; // writing $ffff sets the irq enable mask +always @(posedge clk) begin + if(reset) begin + ie_r <= 5'h00; + if_r <= 5'h00; + end + + // rising edge on vs + vsD <= vs; + vsD2 <= vsD; + if(vsD && !vsD2) if_r[0] <= 1'b1; + + // video irq already is a 1 clock event + if(video_irq) if_r[1] <= 1'b1; + + // timer_irq already is a 1 clock event + if(timer_irq) if_r[2] <= 1'b1; + + // falling edge on any input line P10..P13 + inputD <= joy_p4 | joy_p5; + inputD2 <= inputD; + if(~inputD & inputD2) if_r[4] <= 1'b1; + + // cpu acknowledges irq. this clears the active irq with hte + // highest priority + if(irq_ack) begin + if(if_r[0] && ie_r[0]) if_r[0] <= 1'b0; + else if(if_r[1] && ie_r[1]) if_r[1] <= 1'b0; + else if(if_r[2] && ie_r[2]) if_r[2] <= 1'b0; + else if(if_r[3] && ie_r[3]) if_r[3] <= 1'b0; + else if(if_r[4] && ie_r[4]) if_r[4] <= 1'b0; + end + + // cpu writes interrupt enable register + if(sel_ie && !cpu_wr_n) + ie_r <= cpu_do[4:0]; + + // cpu writes interrupt flag register + if(sel_if && !cpu_wr_n) + if_r <= cpu_do[4:0]; +end + +// -------------------------------------------------------------------- +// ------------------------------ timer ------------------------------- +// -------------------------------------------------------------------- + +wire timer_irq; +wire [7:0] timer_do; +timer timer ( + .reset ( reset ), + .clk ( clk ), + + .irq ( timer_irq ), + + .cpu_sel ( sel_timer ), + .cpu_addr ( cpu_addr[1:0] ), + .cpu_wr ( !cpu_wr_n ), + .cpu_di ( cpu_do ), + .cpu_do ( timer_do ) +); + +// -------------------------------------------------------------------- +// ------------------------------ video ------------------------------- +// -------------------------------------------------------------------- + +// cpu tries to read or write the lcd controller registers +wire video_irq; +wire [7:0] video_do; +wire [12:0] video_addr; +wire [15:0] dma_addr; +wire video_rd, dma_rd; +wire [7:0] dma_data = (dma_addr[15:14]==2'b11)?iram_do:cart_do; + +video video ( + .reset ( reset ), + .clk ( clk ), + + .irq ( video_irq ), + + .cpu_sel_reg ( sel_video_reg ), + .cpu_sel_oam ( sel_video_oam ), + .cpu_addr ( cpu_addr[7:0] ), + .cpu_wr ( !cpu_wr_n ), + .cpu_di ( cpu_do ), + .cpu_do ( video_do ), + + .lcd_on ( lcd_on ), + .lcd_clkena ( lcd_clkena ), + .lcd_data ( lcd_data ), + .mode ( lcd_mode ), + + .vram_rd ( video_rd ), + .vram_addr ( video_addr ), + .vram_data ( vram_do ), + + .dma_rd ( dma_rd ), + .dma_addr ( dma_addr ), + .dma_data ( dma_data ) +); + +// total 8k vram from $8000 to $9fff +wire cpu_wr_vram = sel_vram && !cpu_wr_n; +wire [7:0] vram_do; +wire vram_wren = video_rd?1'b0:cpu_wr_vram; +wire [12:0] vram_addr = video_rd?video_addr:cpu_addr[12:0]; + +vram vram ( + .clock ( clk ), + .address ( vram_addr ), + .wren ( vram_wren ), + .data ( cpu_do ), + .q ( vram_do ) +); + +// -------------------------------------------------------------------- +// -------------------------- zero page ram --------------------------- +// -------------------------------------------------------------------- + +// 127 bytes internal zero page ram from $ff80 to $fffe +wire cpu_wr_zpram = sel_zpram && !cpu_wr_n; +wire [7:0] zpram_do; +zpram zpram ( + .clock ( clk ), + .address ( cpu_addr[6:0] ), + .wren ( cpu_wr_zpram ), + .data ( cpu_do ), + .q ( zpram_do ) +); + +// -------------------------------------------------------------------- +// ------------------------- 8k internal ram -------------------------- +// -------------------------------------------------------------------- + +wire iram_wren = dma_rd?1'b0:cpu_wr_iram; +wire [12:0] iram_addr = dma_rd?dma_addr[12:0]:cpu_addr[12:0]; + +wire cpu_wr_iram = sel_iram && !cpu_wr_n; +wire [7:0] iram_do; +iram iram ( + .clock ( clk ), + .address ( iram_addr[12:0]), + .wren ( iram_wren ), + .data ( cpu_do ), + .q ( iram_do ) +); + +// -------------------------------------------------------------------- +// ------------------------ internal boot rom ------------------------- +// -------------------------------------------------------------------- + +// writing 01 to $ff50 disables the internal rom +reg boot_rom_enabled; +always @(posedge clk) begin + if(reset) + boot_rom_enabled <= 1'b1; + else if((cpu_addr == 16'hff50) && !cpu_wr_n && cpu_do[0]) + boot_rom_enabled <= 1'b0; +end + +// combine boot rom data with cartridge data +wire [7:0] rom_do = ((cpu_addr[14:8] == 7'h00) && boot_rom_enabled)?boot_rom_do:cart_do; + +assign cart_di = cpu_do; +assign cart_addr = dma_rd?dma_addr:cpu_addr; +assign cart_rd = dma_rd || ((sel_rom || sel_cram) && !cpu_rd_n); +assign cart_wr = (sel_rom || sel_cram) && !cpu_wr_n; + +wire [7:0] boot_rom_do; +BROM BROM ( + .addr ( cpu_addr[7:0] ), + .clk ( clk ), + .data ( boot_rom_do ) +); + + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/gb_mist.sv b/Nintendo - Gameboy_Mist/rtl/gb_mist.sv new file mode 100644 index 00000000..b24049f3 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/gb_mist.sv @@ -0,0 +1,439 @@ +// +// gb_mist.v +// +// Gameboy for the MIST board https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module gb_mist ( + input [1:0] CLOCK_27, + + output LED, + + // SPI interface to arm io controller + output SPI_DO, + input SPI_DI, + input SPI_SCK, + input SPI_SS2, + input SPI_SS3, + input SPI_SS4, + input CONF_DATA0, + + // SDRAM interface + inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits + output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits + output SDRAM_DQML, // SDRAM Low-byte Data Mask + output SDRAM_DQMH, // SDRAM High-byte Data Mask + output SDRAM_nWE, // SDRAM Write Enable + output SDRAM_nCAS, // SDRAM Column Address Strobe + output SDRAM_nRAS, // SDRAM Row Address Strobe + output SDRAM_nCS, // SDRAM Chip Select + output [1:0] SDRAM_BA, // SDRAM Bank Address + output SDRAM_CLK, // SDRAM Clock + output SDRAM_CKE, // SDRAM Clock Enable + + // audio + output AUDIO_L, + output AUDIO_R, + + // video + output VGA_HS, + output VGA_VS, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B +); + +assign LED = !dio_download; + +`include "rtl/build_id.sv" +localparam CONF_STR = { + "GAMEBOY;GBCSGB;", + "F,GB;", + "O12,LCD ,white,yellow,invert;", + "O3,Boot,Normal,Fast;", + "O45,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "O6,Mapper,Detect,Force MBC1;", + "T7,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire clk32; +reg clk4; // 4.194304 MHz CPU clock and GB pixel clock +reg clk8; // 8.388608 MHz VGA pixel clock +reg clk16; // 16.777216 MHz +wire pll_locked; +wire reset = (reset_cnt != 0); +reg [9:0] reset_cnt; + +wire [31:0] status; +wire [1:0] buttons, switches; +wire [7:0] kbjoy; +wire [7:0] joy_0, joy_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire hs, vs; +wire [5:0] r,g,b; +wire [15:0] audio_left; +wire [15:0] audio_right; + +wire [7:0] cart_di; // data from cpu to cart +wire [7:0] cart_do = cart_addr[0]?sdram_do[7:0]:sdram_do[15:8]; +wire [15:0] cart_addr; +wire cart_rd; +wire cart_wr; +reg eject = 1'b0; + +wire lcd_clkena; +wire [1:0] lcd_data; +wire [1:0] lcd_mode; +wire lcd_on; +wire invert; +wire color; + +// TODO: ds for cart ram write +wire [1:0] sdram_ds = dio_download?2'b11:{!cart_addr[0], cart_addr[0]}; +wire [15:0] sdram_do; +wire [15:0] sdram_di = dio_download?dio_data:{cart_di, cart_di}; +wire [23:0] sdram_addr = dio_download?dio_addr:{3'b000, mbc_bank, cart_addr[12:1]}; +wire sdram_oe = !dio_download && cart_rd; +wire sdram_we = (dio_download && dio_write) || (!dio_download && cart_ram_wr); +assign SDRAM_CKE = 1'b1; + +wire dio_download; +wire [23:0] dio_addr; +wire [15:0] dio_data; +wire dio_write; + +pll pll ( + .inclk0(CLOCK_27), + .c0(clk32), // 33.557143 MHz + .c1(SDRAM_CLK), // 33.557143 Mhz phase shifted + .locked(pll_locked) + ); + +always @(posedge clk8) + clk4 <= !clk4; + +always @(posedge clk16) + clk8 <= !clk8; + +always @(posedge clk32) + clk16 <= !clk16; + + +always @(posedge clk4) begin + if(status[0] || status[7] || buttons[1] || !pll_locked || dio_download) + reset_cnt <= 10'd1023; + else + if(reset_cnt != 0) + reset_cnt <= reset_cnt - 10'd1; +end + +gb gb ( + .reset ( reset ), + .clk ( clk4 ), + .fast_boot ( status[3] ), + .joystick ( joy0 | joy_1 | kbjoy), + .cart_addr ( cart_addr ), + .cart_rd ( cart_rd ), + .cart_wr ( cart_wr ), + .cart_do ( cart_do ), + .cart_di ( cart_di ), + .audio_l ( audio_left ), + .audio_r ( audio_right ), + .lcd_clkena ( lcd_clkena ), + .lcd_data ( lcd_data ), + .lcd_mode ( lcd_mode ), + .lcd_on ( lcd_on ) +); + +dac dacL( + .CLK ( clk32 ), + .RESET ( reset ), + .DACin ( audio_left[15:1] ), + .DACout ( AUDIO_L ) + ); + +dac dacR( + .CLK ( clk32 ), + .RESET ( reset ), + .DACin ( audio_right[15:1] ), + .DACout ( AUDIO_R ) + ); + +lcd lcd ( + .pclk ( clk8 ), + .clk ( clk4 ), + .tint ( status[2:1] == 1 ? 1 : 0 ), + .inv ( status[2:1] == 2 ? 1 : 0 ), + .clkena ( lcd_clkena), + .data ( lcd_data ), + .mode ( lcd_mode ), // used to detect begin of new lines and frames + .on ( lcd_on ), + .hs ( hs ), + .vs ( vs ), + .r ( r ), + .g ( g ), + .b ( b ) + ); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk32 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joy_0 ), + .joystick_1 (joy_1 ), + .status (status ) + ); + +sdram sdram ( + .sd_data (SDRAM_DQ ), + .sd_addr (SDRAM_A ), + .sd_dqm ({SDRAM_DQMH, SDRAM_DQML} ), + .sd_cs (SDRAM_nCS ), + .sd_ba (SDRAM_BA ), + .sd_we (SDRAM_nWE ), + .sd_ras (SDRAM_nRAS ), + .sd_cas (SDRAM_nCAS ), + .clk (clk32 ), + .clkref (clk4 ), + .init (!pll_locked | eject ), + .din (sdram_di ), + .addr (sdram_addr ), + .ds (sdram_ds ), + .we (sdram_we ), + .oe (sdram_oe ), + .dout (sdram_do ) + ); + +// include ROM download helper +data_io data_io ( + + .sck (SPI_SCK ), + .ss ( SPI_SS2 ), + .sdi ( SPI_DI ), + .downloading ( dio_download ), + .clk ( clk4 ), + .wr ( dio_write ), + .addr ( dio_addr ), + .data ( dio_data ) + ); + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer +( + .clk_sys (clk32 ), + .ce_pix (clk16 ), + .ce_pix_actual (clk16 ), + .SPI_SCK (SPI_SCK ), + .SPI_SS3 (SPI_SS3 ), + .SPI_DI (SPI_DI ), + .R (r ), + .G (g ), + .B (b ), + .HSync (hs ), + .VSync (vs ), + .VGA_R (VGA_R ), + .VGA_G (VGA_G ), + .VGA_B (VGA_B ), + .VGA_VS (VGA_VS ), + .VGA_HS (VGA_HS ), + .scandoubler_disable(1 ),//(scandoubler_disable), //VGA Only + .scanlines(scandoubler_disable ? 2'b00 : {status[5:4] == 3, status[5:4] == 2}), + .hq2x (status[5:4]==1), + .ypbpr_full (1 ), + .line_start (0 ), + .mono (0 ) + ); + +keyboard keyboard( + .clk(clk32), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +// TODO: RAM bank +// http://fms.komkon.org/GameBoy/Tech/Carts.html + +// 32MB SDRAM memory map using word addresses +// 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D +// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S +// ------------------------------------------------- +// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM +// 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as RAM +// 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0) +// 0 0 0 1 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1) + +// --------------------------------------------------------------- +// ----------------------------- MBC1 ---------------------------- +// --------------------------------------------------------------- + +wire [8:0] mbc1_addr = + (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{1'b0, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 + (cart_addr[15:13] == 3'b101)?{7'b1000000, mbc1_ram_bank}: // 8k RAM Bank 0-3 + 9'd0; + +wire [8:0] mbc2_addr = + (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{1'b0, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15 + //todo // 512x4bits RAM, built-in into the MBC2 chip (Read/Write) + 9'd0; + +// -------------------------- RAM banking ------------------------ + +// in mode 0 (16/8 mode) the ram is not banked +// in mode 1 (4/32 mode) four ram banks are used +wire [1:0] mbc1_ram_bank = (mbc1_mode ? mbc1_ram_bank_reg:2'b00) & ram_mask; +wire [1:0] mbc2_ram_bank = (mbc2_mode ? mbc2_ram_bank_reg:2'b00) & ram_mask;//todo +// -------------------------- ROM banking ------------------------ + +// in mode 0 (16/8 mode) the ram bank select signals are the upper rom address lines +// in mode 1 (4/32 mode) the upper two rom address lines are 2'b00 +wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc1_ram_bank_reg, mbc1_rom_bank_reg}; +wire [6:0] mbc2_rom_bank_mode = { mbc2_mode?2'b00:mbc2_ram_bank_reg, mbc2_rom_bank_reg};//todo +// mask address lines to enable proper mirroring +wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask;//128 +wire [6:0] mbc2_rom_bank = mbc2_rom_bank_mode & rom_mask;//16 +// --------------------- CPU register interface ------------------ +reg mbc1_ram_enable; +reg mbc1_mode; +reg [4:0] mbc1_rom_bank_reg; +reg [1:0] mbc1_ram_bank_reg; + +reg mbc2_ram_enable; +reg mbc2_mode; +reg [4:0] mbc2_rom_bank_reg;//todo +reg [1:0] mbc2_ram_bank_reg;//todo + + +// MBC2 todo +always @(posedge clk4) begin + if(reset) begin + mbc1_rom_bank_reg <= 5'd1; + mbc1_ram_bank_reg <= 2'd0; + mbc1_ram_enable <= 1'b0; + mbc1_mode <= 1'b0; + end else begin + if(cart_wr && (cart_addr[15:13] == 3'b000)) + mbc1_ram_enable <= (cart_di[3:0] == 4'ha); + if(cart_wr && (cart_addr[15:13] == 3'b001)) begin + if(cart_di[4:0]==0) mbc1_rom_bank_reg <= 5'd1; + else mbc1_rom_bank_reg <= cart_di[4:0]; + end + if(cart_wr && (cart_addr[15:13] == 3'b010)) + mbc1_ram_bank_reg <= cart_di[1:0]; + if(cart_wr && (cart_addr[15:13] == 3'b011)) + mbc1_mode <= cart_di[0]; + end +// eject <= status[8]; +end + +// extract header fields extracted from cartridge +// during download +reg [7:0] cart_mbc_type; +reg [7:0] cart_rom_size; +reg [7:0] cart_ram_size; +reg [7:0] cgb_flag;//$80 = GBC but GB compatible, $C0 GBC Only, $00 or other = GB +reg [7:0] sgb_flag;//GB/SGB Indicator (00 = GameBoy, 03 = Super GameBoy functions) + //(Super GameBoy functions won't work if <> $03.) + +// only write sdram if the write attept comes from the cart ram area +wire cart_ram_wr = cart_wr && mbc1_ram_enable && (cart_addr[15:13] == 3'b101); + +// RAM size - todo +wire [1:0] ram_mask = // 0 - no ram + (cart_ram_size == 1)?2'b00: // 1 - 2k, 1 bank + (cart_ram_size == 2)?2'b00: // 2 - 8k, 1 bank + 2'b11; // 3 - 32k, 4 banks + // 4 - 128k, ?? banks + // 5 - 64k, ?? banks + +// ROM size +wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped + (cart_rom_size == 1)?7'b0000011: // 1 - 4 banks = 64k + (cart_rom_size == 2)?7'b0000111: // 2 - 8 banks = 128k + (cart_rom_size == 3)?7'b0001111: // 3 - 16 banks = 256k + (cart_rom_size == 4)?7'b0011111: // 4 - 32 banks = 512k + (cart_rom_size == 5)?7'b0111111: // 5 - 64 banks = 1M + (cart_rom_size == 6)?7'b1111111: // 6 - 128 banks = 2M +//? (cart_rom_size == 6)?7'b1111111: // 7 - ??? banks = 4M +//? (cart_rom_size == 6)?7'b1111111: // 8 - ??? banks = 8M + (cart_rom_size == 82)?7'b1000111: //$52 - 72 banks = 1.1M + (cart_rom_size == 83)?7'b1001111: //$53 - 80 banks = 1.2M +// (cart_rom_size == 84)?7'b1011111: + 7'b1011111; //$54 - 96 banks = 1.5M + +wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3) || ~status[6]; +wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6); +wire mmm01 = (cart_mbc_type == 11) || (cart_mbc_type == 12) || (cart_mbc_type == 13) || (cart_mbc_type == 14); +wire mbc3 = (cart_mbc_type == 15) || (cart_mbc_type == 16) || (cart_mbc_type == 17) || (cart_mbc_type == 18) || (cart_mbc_type == 19); +wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23); +wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == 27) || (cart_mbc_type == 28) || (cart_mbc_type == 29) || (cart_mbc_type == 30); +wire tama5 = (cart_mbc_type == 253); +//wire tama6 = (cart_mbc_type == ???); +wire HuC1 = (cart_mbc_type == 254); +wire HuC3 = (cart_mbc_type == 255); + +wire [8:0] mbc_bank = + mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram + mbc2?mbc2_addr: // MBC2, 16k bank 0, 16k bank 1-15 + ram +// mbc3?mbc3_addr: +// mbc4?mbc4_addr: +// mbc5?mbc5_addr: +// tama5?tama5_addr: +// HuC1?HuC1_addr: +// HuC3?HuC3_addr: + {7'b0000000, cart_addr[14:13]}; // no MBC, 32k linear address + + +always @(posedge clk4) begin + if(!pll_locked) begin + cart_mbc_type <= 8'h00; + cart_rom_size <= 8'h00; + cart_ram_size <= 8'h00; + end else begin + if(dio_download && dio_write) begin + // cart is stored in 16 bit wide sdram, so addresses are shifted right + case(dio_addr) + 24'h9f: cgb_flag <= dio_data[7:0]; // $143 + 24'ha2: sgb_flag <= dio_data[7:0]; // $146 + 24'ha3: cart_mbc_type <= dio_data[7:0]; // $147 + 24'ha4: { cart_rom_size, cart_ram_size } <= dio_data; // $148/$149 + endcase + end + end +end + + + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/gbc_snd.vhd b/Nintendo - Gameboy_Mist/rtl/gbc_snd.vhd new file mode 100644 index 00000000..2a9f8cdf --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/gbc_snd.vhd @@ -0,0 +1,935 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; + + +entity gbc_snd is + generic + ( + CLK_FREQ : integer := 100000000 + ); + port + ( + clk : in std_logic; + reset : in std_logic; + + s1_read : in std_logic; + s1_write : in std_logic; + s1_addr : in std_logic_vector(5 downto 0); + s1_readdata : out std_logic_vector(7 downto 0); + s1_writedata : in std_logic_vector(7 downto 0); + + snd_left : out std_logic_vector(15 downto 0); + snd_right : out std_logic_vector(15 downto 0) + ); + +end gbc_snd; + +architecture SYN of gbc_snd is + + subtype wav_t is std_logic_vector(3 downto 0); + type wav_arr_t is array(0 to 31) of wav_t; + + --constant clk_freq : integer := 100000000; + constant snd_freq : integer := 4194304; + + signal en_snd : boolean; -- Enable at base sound frequency (4.19MHz) + signal en_snd2 : boolean; -- Enable at clk/2 + signal en_snd4 : boolean; -- Enable at clk/4 + signal en_512 : boolean; -- 512Hz enable + + signal en_snden2 : boolean; -- Enable at clk/2 + signal en_snden4 : boolean; -- Enable at clk/4 + + signal en_len : boolean; -- Sample length + signal en_env : boolean; -- Envelope + signal en_sweep : boolean; -- Sweep + + signal snd_enable : std_logic; + + signal sq1_swper : std_logic_vector(2 downto 0); -- Sq1 sweep period + signal sq1_swdir : std_logic; -- Sq1 sweep direction + signal sq1_swshift : std_logic_vector(2 downto 0); -- Sq1 sweep frequency shift + signal sq1_duty : std_logic_vector(1 downto 0); -- Sq1 duty cycle + signal sq1_slen : std_logic_vector(5 downto 0); -- Sq1 play length + signal sq1_svol : std_logic_vector(3 downto 0); -- Sq1 initial volume + signal sq1_envsgn : std_logic; -- Sq1 envelope sign + signal sq1_envper : std_logic_vector(2 downto 0); -- Sq1 envelope period + signal sq1_freq : std_logic_vector(10 downto 0); -- Sq1 frequency + signal sq1_trigger : std_logic; -- Sq1 trigger play note + signal sq1_lenchk : std_logic; -- Sq1 length check enable + + signal sq1_fr2 : std_logic_vector(10 downto 0); -- Sq1 frequency (shadow copy) + signal sq1_vol : std_logic_vector(3 downto 0); -- Sq1 initial volume + signal sq1_playing : std_logic; -- Sq1 channel active + signal sq1_wav : std_logic_vector(5 downto 0); -- Sq1 output waveform + + signal sq2_duty : std_logic_vector(1 downto 0); -- Sq2 duty cycle + signal sq2_slen : std_logic_vector(5 downto 0); -- Sq2 play length + signal sq2_svol : std_logic_vector(3 downto 0); -- Sq2 initial volume + signal sq2_envsgn : std_logic; -- Sq2 envelope sign + signal sq2_envper : std_logic_vector(2 downto 0); -- Sq2 envelope period + signal sq2_freq : std_logic_vector(10 downto 0); -- Sq2 frequency + signal sq2_trigger : std_logic; -- Sq2 trigger play note + signal sq2_lenchk : std_logic; -- Sq2 length check enable + + signal sq2_fr2 : std_logic_vector(10 downto 0); -- Sq2 frequency (shadow copy) + signal sq2_vol : std_logic_vector(3 downto 0); -- Sq2 initial volume + signal sq2_playing : std_logic; -- Sq2 channel active + signal sq2_wav : std_logic_vector(5 downto 0); -- Sq2 output waveform + + signal wav_enable : std_logic; -- Wave enable + signal wav_slen : std_logic_vector(7 downto 0); -- Wave play length + signal wav_volsh : std_logic_vector(1 downto 0); -- Wave volume shift + signal wav_freq : std_logic_vector(10 downto 0); -- Wave frequency + signal wav_trigger : std_logic; -- Wave trigger play note + signal wav_lenchk : std_logic; -- Wave length check enable + + signal wav_fr2 : std_logic_vector(10 downto 0); -- Wave frequency (shadow copy) + signal wav_playing : std_logic; + signal wav_wav : std_logic_vector(5 downto 0); -- Wave output waveform + signal wav_ram : wav_arr_t; -- Wave table + signal wav_shift : boolean; + + signal noi_slen : std_logic_vector(5 downto 0); + signal noi_svol : std_logic_vector(3 downto 0); + signal noi_envsgn : std_logic; + signal noi_envper : std_logic_vector(2 downto 0); + signal noi_freqsh : std_logic_vector(3 downto 0); + signal noi_short : std_logic; + signal noi_div : std_logic_vector(2 downto 0); + signal noi_trigger : std_logic; + signal noi_lenchk : std_logic; + + signal noi_fr2 : std_logic_vector(10 downto 0); -- Noise frequency (shadow copy) + signal noi_vol : std_logic_vector(3 downto 0); -- Noise initial volume + signal noi_playing : std_logic; -- Noise channel active + signal noi_wav : std_logic_vector(5 downto 0); -- Noise output waveform + +begin + + en_snd2 <= en_snd and en_snden2; + en_snd4 <= en_snd and en_snden4; + + en_snd <= true; + + -- Calculate base clock enable (4.194304MHz) +-- process(clk, reset) +-- --to_unsigned(snd_freq * 65536 / clk_freq, 16); + --constant clk_frac : unsigned(15 downto 0) := X"0ABD"; -- clk_freq=100MHz +-- constant clk_frac : unsigned(15 downto 0) := X"1991"; -- clk_freq=42MHz +-- variable divacc : unsigned(15 downto 0); +-- variable acc : unsigned(16 downto 0); +-- begin +-- if reset = '1' then +-- divacc := (others => '0'); +-- elsif rising_edge(clk) then + -- Sound base divider clock enable +-- acc := ('0'&divacc) + ('0'&clk_frac); +-- en_snd <= (acc(16) = '1'); +-- divacc := acc(15 downto 0); +-- end if; +-- end process; + + -- Calculate divided and frame sequencer clock enables + process(clk, en_snd, reset) + variable clkcnt : unsigned(1 downto 0); + variable cnt_512 : unsigned(12 downto 0); + variable temp_512 : unsigned(13 downto 0); + variable framecnt : integer range 0 to 7 := 0; + begin + if reset = '1' then + clkcnt := "00"; + cnt_512 := (others => '0'); + framecnt := 0; + + elsif rising_edge(clk) then + -- Base clock divider + if en_snd then + clkcnt := clkcnt + 1; + if clkcnt(0) = '1' then + en_snden2 <= true; + else + en_snden2 <= false; + end if; + if clkcnt = "11" then + en_snden4 <= true; + else + en_snden4 <= false; + end if; + end if; + + -- Frame sequencer (length, envelope, sweep) clock enables + en_len <= false; + en_env <= false; + en_sweep <= false; + if en_512 then + if framecnt = 0 or framecnt = 2 or framecnt = 4 or framecnt = 6 then + en_len <= true; + end if; + if framecnt = 2 or framecnt = 6 then + en_sweep <= true; + end if; + if framecnt = 7 then + en_env <= true; + end if; + + if framecnt < 7 then + framecnt := framecnt + 1; + else + framecnt := 0; + end if; + end if; + + -- + en_512 <= false; + if en_snd then + temp_512 := ('0'&cnt_512) + to_unsigned(1, temp_512'length); + cnt_512 := temp_512(temp_512'high-1 downto temp_512'low); + en_512 <= (temp_512(13) = '1'); + end if; + end if; + end process; + + -- Registers + registers : process(clk, snd_enable, reset) + variable wav_shift_r : boolean; + variable wav_temp : wav_t; + begin + + -- Registers + if snd_enable = '0' then + -- Reset register values + sq1_swper <= (others => '0'); + sq1_swdir <= '0'; + sq1_swshift <= (others => '0'); + sq1_duty <= (others => '0'); + sq1_slen <= (others => '0'); + sq1_svol <= (others => '0'); + sq1_envsgn <= '0'; + sq1_envper <= (others => '0'); + sq1_freq <= (others => '0'); + sq1_lenchk <= '0'; + sq1_trigger <= '0'; + + sq2_duty <= (others => '0'); + sq2_slen <= (others => '0'); + sq2_svol <= (others => '0'); + sq2_envsgn <= '0'; + sq2_envper <= (others => '0'); + sq2_freq <= (others => '0'); + sq2_lenchk <= '0'; + sq2_trigger <= '0'; + + wav_enable <= '0'; + wav_volsh <= (others => '0'); + wav_freq <= (others => '0'); + wav_trigger <= '0'; + wav_lenchk <= '0'; + wav_shift_r := false; + + noi_slen <= (others => '0'); + noi_svol <= (others => '0'); + noi_envsgn <= '0'; + noi_envper <= (others => '0'); + noi_freqsh <= (others => '0'); + noi_short <= '0'; + noi_div <= (others => '0'); + noi_trigger <= '0'; + noi_lenchk <= '0'; + + elsif rising_edge(clk) then + if en_snd then + sq1_trigger <= '0'; + sq2_trigger <= '0'; + wav_trigger <= '0'; + noi_trigger <= '0'; + end if; + + -- Rotate wave table on rising edge of wav_shift + if wav_shift and not wav_shift_r then + wav_temp := wav_ram(0); + for I in 0 to 30 loop + wav_ram(I) <= wav_ram(I+1); + end loop; + wav_ram(31) <= wav_temp; + end if; + + if s1_write = '1' then + case s1_addr is + -- Square 1 + when "010000" => -- NR10 FF10 -PPP NSSS Sweep period, negate, shift + sq1_swper <= s1_writedata(6 downto 4); + sq1_swdir <= s1_writedata(3); + sq1_swshift <= s1_writedata(2 downto 0); + when "010001" => -- NR11 FF11 DDLL LLLL Duty, Length load (64-L) + sq1_duty <= s1_writedata(7 downto 6); + sq1_slen <= s1_writedata(5 downto 0); + when "010010" => -- NR12 FF12 VVVV APPP Starting volume, Envelope add mode, period + sq1_svol <= s1_writedata(7 downto 4); + sq1_envsgn <= s1_writedata(3); + sq1_envper <= s1_writedata(2 downto 0); + when "010011" => -- NR13 FF13 FFFF FFFF Frequency LSB + sq1_freq(7 downto 0) <= s1_writedata; + when "010100" => -- NR14 FF14 TL-- -FFF Trigger, Length enable, Frequency MSB + sq1_trigger <= s1_writedata(7); + sq1_lenchk <= s1_writedata(6); + sq1_freq(10 downto 8) <= s1_writedata(2 downto 0); + + -- Square 2 + when "010110" => -- NR21 FF16 DDLL LLLL Duty, Length load (64-L) + sq2_duty <= s1_writedata(7 downto 6); + sq2_slen <= s1_writedata(5 downto 0); + when "010111" => -- NR22 FF17 VVVV APPP Starting volume, Envelope add mode, period + sq2_svol <= s1_writedata(7 downto 4); + sq2_envsgn <= s1_writedata(3); + sq2_envper <= s1_writedata(2 downto 0); + when "011000" => -- NR23 FF18 FFFF FFFF Frequency LSB + sq2_freq(7 downto 0) <= s1_writedata; + when "011001" => -- NR24 FF19 TL-- -FFF Trigger, Length enable, Frequency MSB + sq2_trigger <= s1_writedata(7); + sq2_lenchk <= s1_writedata(6); + sq2_freq(10 downto 8) <= s1_writedata(2 downto 0); + + -- Wave + when "011010" => -- NR30 FF1A E--- ---- DAC power + wav_enable <= s1_writedata(7); + when "011011" => -- NR31 FF1B LLLL LLLL Length load (256-L) + wav_slen <= s1_writedata; + when "011100" => -- NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%) + wav_volsh <= s1_writedata(6 downto 5); + when "011101" => -- NR33 FF1D FFFF FFFF Frequency LSB + wav_freq(7 downto 0) <= s1_writedata; + when "011110" => -- NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB + wav_trigger <= s1_writedata(7); + wav_lenchk <= s1_writedata(6); + wav_freq(10 downto 8) <= s1_writedata(2 downto 0); + + -- Noise + when "100000" => -- NR41 FF20 --LL LLLL Length load (64-L) + noi_slen <= s1_writedata(5 downto 0); + when "100001" => -- NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period + noi_svol <= s1_writedata(7 downto 4); + noi_envsgn <= s1_writedata(3); + noi_envper <= s1_writedata(2 downto 0); + when "100010" => -- NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code + noi_freqsh <= s1_writedata(7 downto 4); + noi_short <= s1_writedata(3); + noi_div <= s1_writedata(2 downto 0); + when "100011" => -- NR44 FF23 TL-- ---- Trigger, Length enable + noi_trigger <= s1_writedata(7); + noi_lenchk <= s1_writedata(6); + +-- -- Control/Status +-- when "100100" => -- NR50 FF24 ALLL BRRR Vin L enable, Left vol, Vin R enable, Right vol +-- when "100101" => -- NR51 FF25 NW21 NW21 Left enables, Right enables +-- + -- Wave Table + when "110000" => -- FF30 0000 1111 Samples 0 and 1 + wav_ram(0) <= s1_writedata(7 downto 4); + wav_ram(1) <= s1_writedata(3 downto 0); + when "110001" => -- FF31 0000 1111 Samples 2 and 3 + wav_ram(2) <= s1_writedata(7 downto 4); + wav_ram(3) <= s1_writedata(3 downto 0); + when "110010" => -- FF32 0000 1111 Samples 4 and 5 + wav_ram(4) <= s1_writedata(7 downto 4); + wav_ram(5) <= s1_writedata(3 downto 0); + when "110011" => -- FF33 0000 1111 Samples 6 and 31 + wav_ram(6) <= s1_writedata(7 downto 4); + wav_ram(7) <= s1_writedata(3 downto 0); + when "110100" => -- FF34 0000 1111 Samples 8 and 31 + wav_ram(8) <= s1_writedata(7 downto 4); + wav_ram(9) <= s1_writedata(3 downto 0); + when "110101" => -- FF35 0000 1111 Samples 10 and 11 + wav_ram(10) <= s1_writedata(7 downto 4); + wav_ram(11) <= s1_writedata(3 downto 0); + when "110110" => -- FF36 0000 1111 Samples 12 and 13 + wav_ram(12) <= s1_writedata(7 downto 4); + wav_ram(13) <= s1_writedata(3 downto 0); + when "110111" => -- FF37 0000 1111 Samples 14 and 15 + wav_ram(14) <= s1_writedata(7 downto 4); + wav_ram(15) <= s1_writedata(3 downto 0); + when "111000" => -- FF38 0000 1111 Samples 16 and 17 + wav_ram(16) <= s1_writedata(7 downto 4); + wav_ram(17) <= s1_writedata(3 downto 0); + when "111001" => -- FF39 0000 1111 Samples 18 and 19 + wav_ram(18) <= s1_writedata(7 downto 4); + wav_ram(19) <= s1_writedata(3 downto 0); + when "111010" => -- FF3A 0000 1111 Samples 20 and 21 + wav_ram(20) <= s1_writedata(7 downto 4); + wav_ram(21) <= s1_writedata(3 downto 0); + when "111011" => -- FF3B 0000 1111 Samples 22 and 23 + wav_ram(22) <= s1_writedata(7 downto 4); + wav_ram(23) <= s1_writedata(3 downto 0); + when "111100" => -- FF3C 0000 1111 Samples 24 and 25 + wav_ram(24) <= s1_writedata(7 downto 4); + wav_ram(25) <= s1_writedata(3 downto 0); + when "111101" => -- FF3D 0000 1111 Samples 26 and 27 + wav_ram(26) <= s1_writedata(7 downto 4); + wav_ram(27) <= s1_writedata(3 downto 0); + when "111110" => -- FF3E 0000 1111 Samples 28 and 29 + wav_ram(28) <= s1_writedata(7 downto 4); + wav_ram(29) <= s1_writedata(3 downto 0); + when "111111" => -- FF3F 0000 1111 Samples 30 and 31 + wav_ram(30) <= s1_writedata(7 downto 4); + wav_ram(31) <= s1_writedata(3 downto 0); + + when others => + null; + end case; + end if; + + if s1_read = '1' then + case s1_addr is + -- Square 1 + when "010000" => -- NR10 FF10 -PPP NSSS Sweep period, negate, shift + s1_readdata <= '1' & sq1_swper & sq1_swdir & sq1_swshift; + when "010001" => -- NR11 FF11 DDLL LLLL Duty, Length load (64-L) + s1_readdata <= sq1_duty & "111111"; + when "010010" => -- NR12 FF12 VVVV APPP Starting volume, Envelope add mode, period + s1_readdata <= sq1_vol & sq1_envsgn & sq1_envper; + when "010011" => -- NR13 FF13 FFFF FFFF Frequency LSB + s1_readdata <= X"FF"; + when "010100" => -- NR14 FF14 TL-- -FFF Trigger, Length enable, Frequency MSB + s1_readdata <= '0' & sq1_lenchk & "111111"; + + -- Square 2 + when "010110" => -- NR21 FF16 DDLL LLLL Duty, Length load (64-L) + s1_readdata <= sq2_duty & "111111"; + when "010111" => -- NR22 FF17 VVVV APPP Starting volume, Envelope add mode, period + s1_readdata <= sq2_vol & sq2_envsgn & sq2_envper; + when "011000" => -- NR23 FF18 FFFF FFFF Frequency LSB + s1_readdata <= X"FF"; + when "011001" => -- NR24 FF19 TL-- -FFF Trigger, Length enable, Frequency MSB + s1_readdata <= '0' & sq2_lenchk & "111111"; + + when "100110" => -- NR52 FF26 P--- NW21 Power control/status, Channel length statuses + s1_readdata <= snd_enable & "00000" & sq2_playing & sq1_playing; + + -- Wave + when "011010" => -- NR30 FF1A E--- ---- DAC power + s1_readdata <= wav_enable & "1111111"; + when "011011" => -- NR31 FF1B LLLL LLLL Length load (256-L) + s1_readdata <= X"FF"; + when "011100" => -- NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%) + s1_readdata <= '1' & wav_volsh & "11111"; + when "011101" => -- NR33 FF1D FFFF FFFF Frequency LSB + s1_readdata <= X"FF"; + when "011110" => -- NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB + s1_readdata <= wav_trigger & wav_lenchk & "111111"; + + -- Noise + when "100000" => -- NR41 FF20 --LL LLLL Length load (64-L) + s1_readdata <= X"FF"; + when "100001" => -- NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period + s1_readdata <= noi_svol & noi_envsgn & noi_envper; + when "100010" => -- NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code + s1_readdata <= noi_freqsh & noi_short & noi_div; + when "100011" => -- NR44 FF23 TL-- ---- Trigger, Length enable + s1_readdata <= noi_trigger & noi_lenchk & "111111"; + + -- Wave Table + when "110000" => -- FF30 0000 1111 Samples 0 and 1 + s1_readdata <= wav_ram(0) & wav_ram(1); + when "110001" => -- FF31 0000 1111 Samples 2 and 3 + s1_readdata <= wav_ram(2) & wav_ram(3); + when "110010" => -- FF32 0000 1111 Samples 4 and 5 + s1_readdata <= wav_ram(4) & wav_ram(5); + when "110011" => -- FF33 0000 1111 Samples 6 and 31 + s1_readdata <= wav_ram(6) & wav_ram(7); + when "110100" => -- FF34 0000 1111 Samples 8 and 31 + s1_readdata <= wav_ram(8) & wav_ram(9); + when "110101" => -- FF35 0000 1111 Samples 10 and 11 + s1_readdata <= wav_ram(10) & wav_ram(11); + when "110110" => -- FF36 0000 1111 Samples 12 and 13 + s1_readdata <= wav_ram(12) & wav_ram(13); + when "110111" => -- FF37 0000 1111 Samples 14 and 15 + s1_readdata <= wav_ram(14) & wav_ram(15); + when "111000" => -- FF38 0000 1111 Samples 16 and 17 + s1_readdata <= wav_ram(16) & wav_ram(17); + when "111001" => -- FF39 0000 1111 Samples 18 and 19 + s1_readdata <= wav_ram(18) & wav_ram(19); + when "111010" => -- FF3A 0000 1111 Samples 20 and 21 + s1_readdata <= wav_ram(20) & wav_ram(21); + when "111011" => -- FF3B 0000 1111 Samples 22 and 23 + s1_readdata <= wav_ram(22) & wav_ram(23); + when "111100" => -- FF3C 0000 1111 Samples 24 and 25 + s1_readdata <= wav_ram(24) & wav_ram(25); + when "111101" => -- FF3D 0000 1111 Samples 26 and 27 + s1_readdata <= wav_ram(26) & wav_ram(27); + when "111110" => -- FF3E 0000 1111 Samples 28 and 29 + s1_readdata <= wav_ram(28) & wav_ram(29); + when "111111" => -- FF3F 0000 1111 Samples 30 and 31 + s1_readdata <= wav_ram(30) & wav_ram(31); + + when others => + s1_readdata <= X"FF"; + end case; + + end if; + + wav_shift_r := wav_shift; + end if; + + if reset = '1' then + snd_enable <= '0'; + elsif rising_edge(clk) then + if s1_write = '1' and s1_addr = "100110" then + -- NR52 FF26 P--- NW21 Power control/status, Channel length statuses + snd_enable <= s1_writedata(7); + end if; + end if; + end process; + + sound : process(clk, snd_enable, en_snd, en_len, en_env, en_sweep) + constant duty_0 : std_logic_vector(0 to 7) := "00000001"; + constant duty_1 : std_logic_vector(0 to 7) := "10000001"; + constant duty_2 : std_logic_vector(0 to 7) := "10000111"; + constant duty_3 : std_logic_vector(0 to 7) := "01111110"; + variable sq1_fcnt : unsigned(10 downto 0); + variable sq1_phase : integer range 0 to 7; + variable sq1_len : std_logic_vector(6 downto 0); + variable sq1_envcnt : std_logic_vector(2 downto 0); -- Sq1 envelope timer count + variable sq1_swcnt : std_logic_vector(2 downto 0); -- Sq1 sweep timer count + variable sq1_swoffs : unsigned(11 downto 0); + variable sq1_swfr : unsigned(11 downto 0); + variable sq1_out : std_logic; + + variable sq2_fcnt : unsigned(10 downto 0); + variable sq2_phase : integer range 0 to 7; + variable sq2_len : std_logic_vector(6 downto 0); + variable sq2_envcnt : std_logic_vector(2 downto 0); -- Sq2 envelope timer count + variable sq2_out : std_logic; + + variable wav_fcnt : unsigned(10 downto 0); + variable wav_len : std_logic_vector(8 downto 0); + + variable noi_divisor: unsigned(10 downto 0); -- Noise frequency divisor + variable noi_freq : unsigned(10 downto 0); -- Noise frequency (calculated) + variable noi_fcnt : unsigned(10 downto 0); + variable noi_lfsr : unsigned(15 downto 0); + variable noi_len : std_logic_vector(6 downto 0); + variable noi_envcnt : std_logic_vector(2 downto 0); -- Noise envelope timer count + variable noi_out : std_logic; + + variable acc_fcnt : unsigned(11 downto 0); + begin + -- Sound processing + if snd_enable = '0' then + sq1_playing <= '0'; + sq1_fr2 <= (others => '0'); + sq1_fcnt := (others => '0'); + sq1_phase := 0; + sq1_len := (others => '0'); + sq1_vol <= "0000"; + sq1_envcnt := "000"; + sq1_swcnt := "000"; + sq1_swoffs := (others => '0'); + sq1_swfr := (others => '0'); + sq1_out := '0'; + + sq2_playing <= '0'; + sq2_fr2 <= (others => '0'); + sq2_fcnt := (others => '0'); + sq2_phase := 0; + sq2_len := (others => '0'); + sq2_vol <= "0000"; + sq2_envcnt := "000"; + sq2_out := '0'; + + wav_fcnt := (others => '0'); + wav_len := (others => '0'); + + noi_playing <= '0'; + noi_fr2 <= (others => '0'); + noi_fcnt := (others => '0'); + noi_lfsr := (others => '1'); + noi_len := (others => '0'); + noi_vol <= "0000"; + noi_envcnt := "000"; + noi_out := '0'; + + elsif rising_edge(clk) then + if en_snd4 then + -- Sq1 frequency timer + if sq1_playing = '1' then + acc_fcnt := ('0'&sq1_fcnt) + to_unsigned(1, acc_fcnt'length); + if acc_fcnt(acc_fcnt'high) = '1' then + if sq1_phase < 7 then + sq1_phase := sq1_phase + 1; + else + sq1_phase := 0; + end if; + sq1_fcnt := unsigned(sq1_fr2); + else + sq1_fcnt := acc_fcnt(sq1_fcnt'range); + end if; + end if; + + -- Sq2 frequency timer + if sq2_playing = '1' then + acc_fcnt := ('0'&sq2_fcnt) + to_unsigned(1, acc_fcnt'length); + if acc_fcnt(acc_fcnt'high) = '1' then + if sq2_phase < 7 then + sq2_phase := sq2_phase + 1; + else + sq2_phase := 0; + end if; + sq2_fcnt := unsigned(sq2_fr2); + else + sq2_fcnt := acc_fcnt(sq2_fcnt'range); + end if; + end if; + + -- Noi frequency timer + if noi_playing = '1' then + acc_fcnt := ('0'&noi_fcnt) + to_unsigned(1, acc_fcnt'length); + if acc_fcnt(acc_fcnt'high) = '1' then + -- Noise LFSR + if noi_short = '1' then + noi_lfsr := (noi_lfsr(0) xor noi_lfsr(1)) & noi_lfsr(15 downto 8) & (noi_lfsr(0) xor noi_lfsr(1)) & noi_lfsr(6 downto 1); + else + noi_lfsr := (noi_lfsr(0) xor noi_lfsr(1)) & noi_lfsr(15 downto 1); + end if; + + noi_out := not noi_lfsr(0); + noi_fcnt := unsigned(noi_fr2); + else + noi_fcnt := acc_fcnt(noi_fcnt'range); + end if; + end if; + + case sq1_duty is + when "00" => sq1_out := duty_0(sq1_phase); + when "01" => sq1_out := duty_1(sq1_phase); + when "10" => sq1_out := duty_2(sq1_phase); + when "11" => sq1_out := duty_3(sq1_phase); + when others => null; + end case; + + if sq1_out = '1' then + sq1_wav <= sq1_vol & "00"; + else + sq1_wav <= "000000"; + end if; + + case sq2_duty is + when "00" => sq2_out := duty_0(sq2_phase); + when "01" => sq2_out := duty_1(sq2_phase); + when "10" => sq2_out := duty_2(sq2_phase); + when "11" => sq2_out := duty_3(sq2_phase); + when others => null; + end case; + + if sq2_out = '1' then + sq2_wav <= sq2_vol & "00"; + else + sq2_wav <= "000000"; + end if; + + if noi_out = '1' then + noi_wav <= noi_vol & "00"; + else + noi_wav <= "000000"; + end if; + + end if; + + -- Square channel 1 + if sq1_playing = '1' then + -- Length counter + if en_len then + if sq1_len(6) = '0' then + sq1_len := std_logic_vector(unsigned(sq1_len) + to_unsigned(1, sq1_len'length)); + end if; + end if; + + -- Envelope counter + if en_env then + if sq1_envper /= "000" then + sq1_envcnt := std_logic_vector(unsigned(sq1_envcnt) + to_unsigned(1, sq1_envcnt'length)); + if sq1_envcnt = sq1_envper then + if sq1_envsgn = '1' then + if sq1_vol /= "1111" then + sq1_vol <= std_logic_vector(unsigned(sq1_vol) + to_unsigned(1, sq1_vol'length)); + end if; + else + if sq1_vol /= "0000" then + sq1_vol <= std_logic_vector(unsigned(sq1_vol) - to_unsigned(1, sq1_vol'length)); + end if; + end if; + sq1_envcnt := "000"; + end if; + end if; + end if; + + -- Sweep processing + if en_sweep or sq1_trigger = '1' then + case sq1_swshift is + when "000" => sq1_swoffs := unsigned('0' & sq1_fr2); + when "001" => sq1_swoffs := "00" & unsigned(sq1_fr2(10 downto 1)); + when "010" => sq1_swoffs := "000" & unsigned(sq1_fr2(10 downto 2)); + when "011" => sq1_swoffs := "0000" & unsigned(sq1_fr2(10 downto 3)); + when "100" => sq1_swoffs := "00000" & unsigned(sq1_fr2(10 downto 4)); + when "101" => sq1_swoffs := "000000" & unsigned(sq1_fr2(10 downto 5)); + when "110" => sq1_swoffs := "0000000" & unsigned(sq1_fr2(10 downto 6)); + when "111" => sq1_swoffs := "00000000" & unsigned(sq1_fr2(10 downto 7)); + when others => sq1_swoffs := unsigned('0' & sq1_fr2); + end case; + + -- Calculate next sweep frequency + if sq1_swper /= "000" then + if sq1_swdir = '0' then + sq1_swfr := ('0' & unsigned(sq1_fr2)) - sq1_swoffs; + else + sq1_swfr := ('0' & unsigned(sq1_fr2)) + sq1_swoffs; + end if; + else -- Sweep disabled + sq1_swfr := unsigned('0' & sq1_fr2); + end if; + + -- Sweep counter + if sq1_swper /= "000" then + sq1_swcnt := std_logic_vector(unsigned(sq1_swcnt) + to_unsigned(1, sq1_swcnt'length)); + if sq1_swcnt = sq1_swper then + sq1_fr2 <= std_logic_vector(sq1_swfr(10 downto 0)); + sq1_swcnt := "000"; + end if; + end if; + end if; + + -- Check for end of playing conditions + if sq1_vol = X"0" -- Volume == 0 + or (sq1_lenchk = '1' and sq1_len(6) = '1') -- Play length timer overrun + or (sq1_swper /= "000" and sq1_swfr(11) = '1') -- Sweep frequency overrun + then + sq1_playing <= '0'; + sq1_envcnt := "000"; + sq1_swcnt := "000"; + --sq1_wav <= "000000"; + end if; + end if; + + -- Check sample trigger and start playing + if sq1_trigger = '1' then + sq1_fr2 <= sq1_freq; + sq1_fcnt := unsigned(sq1_freq); + noi_lfsr := (others => '1'); + sq1_playing <= '1'; + sq1_vol <= sq1_svol; + sq1_envcnt := "000"; + sq1_swcnt := "000"; + sq1_len := '0' & sq1_slen; + sq1_phase := 0; + end if; + + -- Square channel 2 + if sq2_playing = '1' then + -- Length counter + if en_len then + if sq2_len(6) = '0' then + sq2_len := std_logic_vector(unsigned(sq2_len) + to_unsigned(1, sq2_len'length)); + end if; + end if; + + -- Envelope counter + if en_env then + if sq2_envper /= "000" then + sq2_envcnt := std_logic_vector(unsigned(sq2_envcnt) + to_unsigned(1, sq2_envcnt'length)); + if sq2_envcnt = sq2_envper then + if sq2_envsgn = '1' then + if sq2_vol /= "1111" then + sq2_vol <= std_logic_vector(unsigned(sq2_vol) + to_unsigned(1, sq2_vol'length)); + end if; + else + if sq2_vol /= "0000" then + sq2_vol <= std_logic_vector(unsigned(sq2_vol) - to_unsigned(1, sq2_vol'length)); + end if; + end if; + sq2_envcnt := "000"; + end if; + end if; + end if; + + -- Check for end of playing conditions + if sq2_vol = X"0" -- Volume == 0 + or (sq2_lenchk = '1' and sq2_len(6) = '1') -- Play length timer overrun + then + sq2_playing <= '0'; + sq2_envcnt := "000"; + --sq2_wav <= "000000"; + end if; + end if; + + -- Check sample trigger and start playing + if sq2_trigger = '1' then + sq2_fr2 <= sq2_freq; + sq2_fcnt := unsigned(sq2_freq); + sq2_playing <= '1'; + sq2_vol <= sq2_svol; + sq2_envcnt := "000"; + sq2_len := '0' & sq2_slen; + sq2_phase := 0; + end if; + + -- Noise channel + if noi_playing = '1' then + -- Length counter + if en_len then + if noi_len(6) = '0' then + noi_len := std_logic_vector(unsigned(noi_len) + to_unsigned(1, noi_len'length)); + end if; + end if; + + -- Envelope counter + if en_env then + if noi_envper /= "000" then + noi_envcnt := std_logic_vector(unsigned(noi_envcnt) + to_unsigned(1, noi_envcnt'length)); + if noi_envcnt = noi_envper then + if noi_envsgn = '1' then + if noi_vol /= "1111" then + noi_vol <= std_logic_vector(unsigned(noi_vol) + to_unsigned(1, noi_vol'length)); + end if; + else + if noi_vol /= "0000" then + noi_vol <= std_logic_vector(unsigned(noi_vol) - to_unsigned(1, noi_vol'length)); + end if; + end if; + noi_envcnt := "000"; + end if; + end if; + end if; + + -- Check for end of playing conditions + if noi_vol = X"0" -- Volume == 0 + or (noi_lenchk = '1' and noi_len(6) = '1') -- Play length timer overrun + then + noi_playing <= '0'; + noi_envcnt := "000"; + --sq2_wav <= "000000"; + end if; + end if; + + -- Check sample trigger and start playing + if noi_trigger = '1' then + -- Calculate noise frequency + case noi_div is + when "000" => noi_divisor := to_unsigned(2048 - 8, noi_divisor'length); + when "001" => noi_divisor := to_unsigned(2048 - 16, noi_divisor'length); + when "010" => noi_divisor := to_unsigned(2048 - 32, noi_divisor'length); + when "011" => noi_divisor := to_unsigned(2048 - 48, noi_divisor'length); + when "100" => noi_divisor := to_unsigned(2048 - 64, noi_divisor'length); + when "101" => noi_divisor := to_unsigned(2048 - 80, noi_divisor'length); + when "110" => noi_divisor := to_unsigned(2048 - 96, noi_divisor'length); + when others => noi_divisor := to_unsigned(2048 - 112, noi_divisor'length); + end case; + +-- case noi_freqsh is +-- when "000" => noi_freq := unsigned(noi_divisor); +-- when "001" => noi_freq := '0' & unsigned(noi_divisor(10 downto 1)); +-- when "010" => noi_freq := "00" & unsigned(noi_divisor(10 downto 2)); +-- when "011" => noi_freq := "000" & unsigned(noi_divisor(10 downto 3)); +-- when "100" => noi_freq := "0000" & unsigned(noi_divisor(10 downto 4)); +-- when "101" => noi_freq := "00000" & unsigned(noi_divisor(10 downto 5)); +-- when "110" => noi_freq := "000000" & unsigned(noi_divisor(10 downto 6)); +-- when "111" => noi_freq := "0000000" & unsigned(noi_divisor(10 downto 7)); +-- when others => noi_freq := unsigned(noi_divisor); +-- end case; + noi_freq := noi_divisor sll to_integer(unsigned(noi_freqsh)); + + noi_fr2 <= std_logic_vector(noi_freq); + noi_fcnt := noi_freq; + noi_playing <= '1'; + noi_vol <= noi_svol; + noi_envcnt := "000"; + noi_len := '0' & noi_slen; + end if; + + if en_snd2 then + -- Wave frequency timer + wav_shift <= false; + if wav_playing = '1' then + acc_fcnt := ('0'&wav_fcnt) + to_unsigned(1, acc_fcnt'length); + if acc_fcnt(acc_fcnt'high) = '1' then + wav_shift <= true; + wav_fcnt := unsigned(wav_fr2); + else + wav_fcnt := acc_fcnt(wav_fcnt'range); + end if; + end if; + end if; + + -- Wave channel + if wav_playing = '1' then + -- Length counter + if en_len then + if wav_len(8) = '0' then + wav_len := std_logic_vector(unsigned(wav_len) + to_unsigned(1, wav_len'length)); + end if; + end if; + + -- Check for end of playing conditions + if (wav_lenchk = '1' and wav_len(8) = '1') then + wav_playing <= '0'; + wav_wav <= "000000"; + end if; + end if; + + -- Check sample trigger and start playing + if wav_trigger = '1' then + wav_fr2 <= wav_freq; + wav_fcnt := unsigned(wav_freq); + wav_playing <= '1'; + wav_len := '0' & wav_slen; + end if; + + if wav_enable = '1' and wav_volsh /= "00" then + case wav_volsh is + when "01" => wav_wav <= wav_ram(0) & "00"; + when "10" => wav_wav <= '0' & wav_ram(0) & '0'; + when "11" => wav_wav <= "00" & wav_ram(0); + when others => wav_wav <= (others => 'X'); + end case; + else + wav_wav <= "000000"; + end if; + + end if; -- snd_enable + end process sound; + + -- Test + process(clk, en_512, reset) + variable l : std_logic_vector(15 downto 0); + begin + if reset = '1' then + l := x"4000"; + + elsif rising_edge(clk) then + if en_512 then + l := not l; + end if; +-- snd_left <= l; + end if; + end process; + + -- Mixer + mixer : process(sq1_wav, sq2_wav, noi_wav, wav_wav) + variable snd_left_in : unsigned(7 downto 0); + variable snd_right_in : unsigned(7 downto 0); + begin + snd_left_in := (others => '0'); + snd_right_in := (others => '0'); + + snd_left_in := snd_left_in + ("00"&unsigned(sq1_wav)); + snd_left_in := snd_left_in + ("00"&unsigned(wav_wav)); + snd_right_in := snd_right_in + ("00"&unsigned(sq2_wav)); + snd_right_in := snd_right_in + ("00"&unsigned(noi_wav)); + + snd_left <= std_logic_vector(snd_left_in) & X"00"; + snd_right <= std_logic_vector(snd_right_in) & X"00"; + end process; + +end SYN; diff --git a/Nintendo - Gameboy_Mist/rtl/hq2x.sv b/Nintendo - Gameboy_Mist/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Nintendo - Gameboy_Mist/rtl/iram.sv b/Nintendo - Gameboy_Mist/rtl/iram.sv new file mode 100644 index 00000000..744357db --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/iram.sv @@ -0,0 +1,172 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: iram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module iram ( + address, + clock, + data, + wren, + q); + + input [12:0] address; + input clock; + input [7:0] data; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL iram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL iram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL iram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL iram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL iram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL iram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Nintendo - Gameboy_Mist/rtl/keyboard.sv b/Nintendo - Gameboy_Mist/rtl/keyboard.sv new file mode 100644 index 00000000..a6d2ba94 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/keyboard.sv @@ -0,0 +1,79 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h75: joystick[3] <= ~release_btn; // arrow up + 'h72: joystick[2] <= ~release_btn; // arrow down + 'h6B: joystick[1] <= ~release_btn; // arrow left + 'h74: joystick[0] <= ~release_btn; // arrow right + + 'h29: joystick[4] <= ~release_btn; // Space + 'h11: joystick[5] <= ~release_btn; // Left Alt + 'h0D: joystick[6] <= ~release_btn; // Tab + 'h76: joystick[7] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/lcd.sv b/Nintendo - Gameboy_Mist/rtl/lcd.sv new file mode 100644 index 00000000..df77d663 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/lcd.sv @@ -0,0 +1,147 @@ +// Gameboy for the MiST +// (c) 2015 Till Harbaum + +// The gameboy lcd runs from a shift register which is filled at 4194304 pixels/sec + +module lcd ( + input clk, + input clkena, + input [1:0] data, + input [1:0] mode, + + input tint, + input inv, + // pixel clock + input pclk, + input on, + + // VGA output + output reg hs, + output reg vs, + output [5:0] r, + output [5:0] g, + output [5:0] b +); + +// Mode 00: h-blank +// Mode 01: v-blank +// Mode 10: oam +// Mode 11: oam and vram + +// space for 2*160 pixel +reg [7:0] shift_reg_wptr; +reg p_toggle; +reg [1:0] shift_reg [511:0]; +reg [1:0] last_mode_in; + +// shift register input +always @(posedge clk) begin + last_mode_in <= mode; + + // end of vsync + if(clkena) begin + shift_reg[{p_toggle, shift_reg_wptr}] <= data; + shift_reg_wptr <= shift_reg_wptr + 8'd1; + end + + // reset write pointer at end of hsync phase + if((mode != 2'b00) && (last_mode_in == 2'b00)) begin + shift_reg_wptr <= 8'd0; + p_toggle <= !p_toggle; + end +end + +// +parameter H = 160; // width of visible area +parameter HFP = 24; // unused time before hsync +parameter HS = 20; // width of hsync +parameter HBP = 24; // unused time after hsync +// total = 228 + +parameter V = 576; // height of visible area +parameter VFP = 2; // unused time before vsync +parameter VS = 2; // width of vsync +parameter VBP = 36; // unused time after vsync +// total = 616 + +reg[7:0] h_cnt; // horizontal pixel counter +reg[9:0] v_cnt; // vertical pixel counter + +// horizontal pixel counter +reg [1:0] last_mode_h; +always@(posedge pclk) begin + last_mode_h <= mode; + + if(h_cnt==H+HFP+HS+HBP-1) h_cnt <= 0; + else h_cnt <= h_cnt + 1; + + // generate negative hsync signal + if(h_cnt == H+HFP) hs <= 1'b0; + if(h_cnt == H+HFP+HS) hs <= 1'b1; + + // synchronize to input mode + // end of hblank + if((mode == 2'b10) && (last_mode_h == 2'b00)) + h_cnt <= 0; +end + +// veritical pixel counter +reg [1:0] last_mode_v; +always@(posedge pclk) begin + // the vertical counter is processed at the begin of each hsync + if(h_cnt == H+HFP+HS+HBP-1) begin + if(v_cnt==VS+VFP+V+VBP-1) v_cnt <= 0; + else v_cnt <= v_cnt + 1; + + // generate positive vsync signal + if(v_cnt == V+VFP) vs <= 1'b1; + if(v_cnt == V+VFP+VS) vs <= 1'b0; + + last_mode_v <= mode; + + // synchronize to input mode + // end of mode 01 (vblank) + // make and offset of - 4 for the 4 line delay of the scandoubler + if((mode != 2'b01) && (last_mode_v == 2'b01)) + v_cnt <= 616-4; + end +end + +// ------------------------------------------------------------------------------- +// ------------------------------- pixel generator ------------------------------- +// ------------------------------------------------------------------------------- +reg blank; +reg [1:0] pixel_reg; +reg [7:0] shift_reg_rptr; + +always@(posedge pclk) begin + // visible area? + if((v_cnt < V) && (h_cnt < H)) begin + blank <= 1'b0; + pixel_reg <= shift_reg[{!p_toggle, shift_reg_rptr}]; + shift_reg_rptr <= shift_reg_rptr + 8'd1; + end else begin + blank <= 1'b1; + shift_reg_rptr <= 8'd0; + end +end + +//wire [1:0] pixel = on?pixel_reg:2'b00; +wire [1:0] pixel = on? (pixel_reg ^ {inv,inv}) :2'b00; + +// gameboy "color" palette +wire [5:0] yellow_r = (pixel==0)?6'b100111:(pixel==1)?6'b100000: // 1:100011 + (pixel==2)?6'b001100:6'b000111; +wire [5:0] yellow_g = (pixel==0)?6'b101111:(pixel==1)?6'b101000: // 1:101011 + (pixel==2)?6'b011001:6'b000100; +wire [5:0] yellow_b = (pixel==0)?6'b000100:(pixel==1)?6'b000010: // 1:000100 + (pixel==2)?6'b001100:6'b000100; + +// greyscale +wire [5:0] grey = (pixel==0)?6'd63:(pixel==1)?6'd42:(pixel==2)?6'd24:6'd0; + +assign r = blank?6'b000000:tint?yellow_r:grey; +assign g = blank?6'b000000:tint?yellow_g:grey; +assign b = blank?6'b000000:tint?yellow_b:grey; + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/mist_io.sv b/Nintendo - Gameboy_Mist/rtl/mist_io.sv new file mode 100644 index 00000000..dcc7ecde --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/mist_io.sv @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [23:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [23:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [23:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/osd.sv b/Nintendo - Gameboy_Mist/rtl/osd.sv new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/osd.sv @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/pll.qip b/Nintendo - Gameboy_Mist/rtl/pll.qip new file mode 100644 index 00000000..afd958be --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Nintendo - Gameboy_Mist/rtl/pll.v b/Nintendo - Gameboy_Mist/rtl/pll.v new file mode 100644 index 00000000..47c2b50d --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/pll.v @@ -0,0 +1,421 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + c2, + c3, + c4, + locked); + + input inclk0; + output c0; + output c1; + output c2; + output c3; + output c4; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire3; + wire [0:0] sub_wire9 = 1'h0; + wire [4:4] sub_wire6 = sub_wire0[4:4]; + wire [2:2] sub_wire5 = sub_wire0[2:2]; + wire [0:0] sub_wire4 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire c3 = sub_wire2; + wire locked = sub_wire3; + wire c0 = sub_wire4; + wire c2 = sub_wire5; + wire c4 = sub_wire6; + wire sub_wire7 = inclk0; + wire [1:0] sub_wire8 = {sub_wire9, sub_wire7}; + + altpll altpll_component ( + .inclk (sub_wire8), + .clk (sub_wire0), + .locked (sub_wire3), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 62, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 77, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 62, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 77, + altpll_component.clk1_phase_shift = "-2500", + altpll_component.clk2_divide_by = 130, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 77, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 260, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 77, + altpll_component.clk3_phase_shift = "0", + altpll_component.clk4_divide_by = 520, + altpll_component.clk4_duty_cycle = 50, + altpll_component.clk4_multiply_by = 77, + altpll_component.clk4_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk4 = "PORT_USED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "62" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "62" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "130" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "260" +// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "520" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "33.532257" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "33.532257" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "15.992308" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "7.996154" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "3.998077" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "77" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "77" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "77" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "77" +// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "77" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "33.55714300" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "33.55714300" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "16.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "8.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "4.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2500.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" +// Retrieval info: PRIVATE: USE_CLK4 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "62" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "77" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "62" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "77" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "130" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "77" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "260" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "77" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "520" +// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "77" +// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Nintendo - Gameboy_Mist/rtl/scandoubler.sv b/Nintendo - Gameboy_Mist/rtl/scandoubler.sv new file mode 100644 index 00000000..0213d20c --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/scandoubler.sv @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/sdram.sv b/Nintendo - Gameboy_Mist/rtl/sdram.sv new file mode 100644 index 00000000..5af8c5cd --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/sdram.sv @@ -0,0 +1,150 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout [15:0] sd_data, // 16 bit bidirectional data bus + output reg [12:0] sd_addr, // 13 bit multiplexed address bus + output reg [1:0] sd_dqm, // two byte masks + output reg[1:0] sd_ba, // two banks + output sd_cs, // a single chip select + output sd_we, // write enable + output sd_ras, // row address select + output sd_cas, // columns address select + + // cpu/chipset interface + input init, // init signal after FPGA config to initialize RAM + input clk, // sdram is accessed at up to 128MHz + input clkref, // reference clock to sync to + + input [15:0] din, // data input from chipset/cpu + output [15:0] dout, // data output to chipset/cpu + input [23:0] addr, // 24 bit word address + input [1:0] ds, // data strobe for hi/low byte + input oe, // cpu/chipset requests read + input we // cpu/chipset requests write +); + +// no burst configured +localparam RASCAS_DELAY = 3'd3; // tRCD>=20ns -> 2 cycles@64MHz +localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd3; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +localparam STATE_IDLE = 3'd0; // first state in cycle +localparam STATE_CMD_START = 3'd1; // state in which a new command can be started +localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued +localparam STATE_LAST = 3'd7; // last state in cycle + +reg [2:0] q; +always @(posedge clk) begin + // 32Mhz counter synchronous to 4 Mhz clock + // force counter to pass state 5->6 exactly after the rising edge of clkref + // since clkref is two clocks early + if(((q == 7) && ( clkref == 0)) || + ((q == 0) && ( clkref == 1)) || + ((q != 7) && (q != 0))) + q <= q + 3'd1; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 clkref cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +always @(posedge clk) begin + if(init) reset <= 5'h1f; + else if((q == STATE_LAST) && (reset != 0)) + reset <= reset - 5'd1; +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram + +// drive control signals according to current command +assign sd_cs = sd_cmd[3]; +assign sd_ras = sd_cmd[2]; +assign sd_cas = sd_cmd[1]; +assign sd_we = sd_cmd[0]; + +assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ; + +assign dout = sd_data; + +always @(posedge clk) begin + sd_cmd <= CMD_INHIBIT; + + if(reset != 0) begin + sd_ba <= 2'b00; + sd_dqm <= 2'b00; + + if(reset == 13) sd_addr <= 13'b0010000000000; + else sd_addr <= MODE; + + if(q == STATE_IDLE) begin + if(reset == 13) sd_cmd <= CMD_PRECHARGE; + if(reset == 2) sd_cmd <= CMD_LOAD_MODE; + end + end else begin + if(q <= STATE_CMD_START) begin + sd_addr <= addr[20:8]; + sd_ba <= addr[22:21]; + sd_dqm <= { !ds[1], !ds[0] }; + end else + sd_addr <= { 4'b0010, addr[23], addr[7:0]}; + + if(q == STATE_IDLE) begin + if(we || oe) sd_cmd <= CMD_ACTIVE; + else sd_cmd <= CMD_AUTO_REFRESH; + end else if(q == STATE_CMD_CONT) begin + if(we) sd_cmd <= CMD_WRITE; + else if(oe) sd_cmd <= CMD_READ; + end + end +end + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/sprite.sv b/Nintendo - Gameboy_Mist/rtl/sprite.sv new file mode 100644 index 00000000..81ed82f8 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/sprite.sv @@ -0,0 +1,107 @@ +// +// sprite.v +// +// Gameboy for the MIST board https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sprite ( + input clk, + input size16, + + input [7:0] v_cnt, + input [7:0] h_cnt, + + output [7:0] x, + + // interface to read pixel data from memory + output [10:0] addr, + input [1:0] ds, + input [7:0] data, + + output pixel_active, + output pixel_cmap, + output pixel_prio, + output [1:0] pixel_data, + + input oam_wr, + input [1:0] oam_addr, + input [7:0] oam_di, + output [7:0] oam_do +); + +// x position for priority detection. Invisible sprites are far to the right and +// have minimum priority +assign x = v_visible?x_pos:8'hff; + +// register used to store pixel data for current line +reg [7:0] data0; +reg [7:0] data1; + +always @(posedge clk) begin + if(ds[0]) data0 <= data; + if(ds[1]) data1 <= data; +end + +wire [7:0] height = size16?8'd16:8'd8; + +wire v_visible = (v_cnt + 8'd16 >= y_pos) && (v_cnt + 8'd16 < y_pos + height); +wire visible = v_visible && (h_cnt + 8'd8 >= x_pos) && (h_cnt < x_pos); + +// x position within sprite, mirror horizontally if required +wire [2:0] col_n = h_cnt - x_pos; +wire [2:0] col = flags[1]?col_n:~col_n; + +assign pixel_data = { data1[col], data0[col] }; +assign pixel_active = (pixel_data != 0) && visible; + +// y position within sprite, mirror vertically if required +wire [3:0] row_n = v_cnt - y_pos; +wire [3:0] row = flags[2]?~row_n:row_n; + +// 16 pixel tall sprites use one more rwo counter bit and the lsb +// of the tile index is ignored +wire [10:0] addr8 = { tile , row[2:0]}; +wire [10:0] addr16 = { tile[7:1] , row}; +assign addr = size16?addr16:addr8; + +assign pixel_cmap = flags[0]; +assign pixel_prio = flags[3]; + +reg [7:0] y_pos; +reg [7:0] x_pos; +reg [7:0] tile; +reg [3:0] flags; + +always @(posedge clk) begin + if(oam_wr) begin + case(oam_addr) + 0: y_pos <= oam_di; + 1: x_pos <= oam_di; + 2: tile <= oam_di; + 3: flags <= oam_di[7:4]; + endcase + end +end + +assign oam_do = + (oam_addr == 0)?y_pos: + (oam_addr == 1)?x_pos: + (oam_addr == 2)?tile: + { flags, 4'h0 }; + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/sprite_sort.sv b/Nintendo - Gameboy_Mist/rtl/sprite_sort.sv new file mode 100644 index 00000000..a3626eee --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/sprite_sort.sv @@ -0,0 +1,100 @@ +// +// sprite_sort.v +// +// Gameboy for the MIST board https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sprite_sort #( + parameter WIDTH = 40 +)( + // system signals + input clk, + input load, + + // sort + input [8*WIDTH-1:0] x, + output [6*WIDTH-1:0] idx +); + +wire [7:0] in [WIDTH-1:0]; + +generate +genvar i; + +// map 1d input array onto 2d work array +// and 2d result array into 1d output array +for(i=0;i values[2*i+1]; + assign int_val[2*i+0] = swap0[i]?values[2*i+1]:values[2*i+0]; + assign int_val[2*i+1] = swap0[i]?values[2*i+0]:values[2*i+1]; + assign int_idx[2*i+0] = swap0[i]?index[2*i+1]:index[2*i+0]; + assign int_idx[2*i+1] = swap0[i]?index[2*i+0]:index[2*i+1]; + end + + // 2nd stage + assign sort_val[0] = int_val[0]; + assign sort_idx[0] = int_idx[0]; + assign sort_val[WIDTH-1] = int_val[WIDTH-1]; + assign sort_idx[WIDTH-1] = int_idx[WIDTH-1]; + for(i=0;i int_val[2*i+2]; + assign sort_val[2*i+1] = swap1[i]?int_val[2*i+2]:int_val[2*i+1]; + assign sort_val[2*i+2] = swap1[i]?int_val[2*i+1]:int_val[2*i+2]; + assign sort_idx[2*i+1] = swap1[i]?int_idx[2*i+2]:int_idx[2*i+1]; + assign sort_idx[2*i+2] = swap1[i]?int_idx[2*i+1]:int_idx[2*i+2]; + end + + for(i=0;i +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sprites ( + input clk, + input size16, + + // pixel position input which the current pixel is generated for + input [7:0] v_cnt, + input [7:0] h_cnt, + + // pixel output + output pixel_active, // current pixel + output [1:0] pixel_data, + output pixel_cmap, + output pixel_prio, + + input sort, + input [3:0] index, // index of sprite which video wants to read data for + output [10:0] addr, + input [1:0] dvalid, + input [7:0] data, + + // oam memory interface + input oam_wr, + input [7:0] oam_addr, + input [7:0] oam_di, + output [7:0] oam_do +); + +localparam SPRITES = 40; + +// ------------------------------------------------------------------------ +// ---------------------------- priority sorting -------------------------- +// ------------------------------------------------------------------------ + +// sprites have priority from left to right and the leftmost 10 are +// being displayed. We thus need to sort them +wire [SPRITES*8-1:0] sprite_x; +wire [SPRITES*6-1:0] sprite_idx; + +sprite_sort #(.WIDTH(SPRITES)) sprite_sort ( + .clk ( clk ), + .load ( sort ), // begin of oam phase + .x ( sprite_x ), + .idx ( sprite_idx ) +); + +wire [SPRITES-1:0] sprite_pixel_active; +wire [SPRITES-1:0] sprite_pixel_cmap; +wire [SPRITES-1:0] sprite_pixel_prio; +wire [1:0] sprite_pixel_data [SPRITES-1:0]; + +wire [10:0] sprite_addr [SPRITES-1:0]; +wire [7:0] sprite_oam_do [SPRITES-1:0]; + +assign oam_do = sprite_oam_do[oam_addr[7:2]]; + +// address where the sprite wants to read data from +wire [5:0] sprite_idx_array [SPRITES-1:0]; +wire [5:0] prio_index = sprite_idx_array[index]; +assign addr = sprite_addr[prio_index]; + + +generate +genvar i; +for(i=0;i WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end GBse; + +architecture rtl of GBse is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map + ( + Mode => 3, + IOWait => IOWait, + Flag_S => 0, + Flag_P => 0, + Flag_X => 0, + Flag_Y => 0, + Flag_C => 4, + Flag_H => 5, + Flag_N => 6, + Flag_Z => 7 + ) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/Nintendo - Gameboy_Mist/rtl/t80/T80.vhd b/Nintendo - Gameboy_Mist/rtl/t80/T80.vhd new file mode 100644 index 00000000..1ea66542 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/t80/T80.vhd @@ -0,0 +1,1088 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems +-- +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + signal XYbit_undoc : std_logic; + + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + XY_State => XY_State, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write, + XYbit_undoc => XYbit_undoc); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if Mode = 3 then + IStatus <= "10"; + elsif IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + if XYbit_undoc='1' then + DO <= ALU_Q; + end if; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusA <= "--------"; + end case; + if XYbit_undoc='1' then + BusA <= DI_Reg; + BusB <= DI_Reg; + end if; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + Auto_Wait_t1 <= Auto_Wait; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then + + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Nintendo - Gameboy_Mist/rtl/t80/T80_ALU.vhd b/Nintendo - Gameboy_Mist/rtl/t80/T80_ALU.vhd new file mode 100644 index 00000000..95c98dab --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/t80/T80_ALU.vhd @@ -0,0 +1,371 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + + -- bug fix - parity flag is just parity for 8080, also overflow for Z80 + process (Carry_v, Carry7_v, Q_v) + begin + if(Mode=2) then + OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor + Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else + OverFlow_v <= Carry_v xor Carry7_v; + end if; + end process; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; +end; diff --git a/Nintendo - Gameboy_Mist/rtl/t80/T80_MCode.vhd b/Nintendo - Gameboy_Mist/rtl/t80/T80_MCode.vhd new file mode 100644 index 00000000..22e6ef99 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/t80/T80_MCode.vhd @@ -0,0 +1,2026 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes + +-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + XYbit_undoc <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + --I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + if mode = 3 then + MCycles <= "011"; + else + MCycles <= "101"; + end if; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + IORQ <= '1'; --TH must be earlier to be stable when address is generated + when 2 => + Write <= '1'; +--TH this is too late IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + IORQ <= '1'; --TH must be earlier to be stable when address is generated + when 2 => + Read_To_Acc <= '1'; +--TH this is too late IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- R/S (IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if XY_State="00" then + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + else + -- BIT b,(IX+d), undocumented + MCycles <= "010"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => null; + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- SET b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if XY_State="00" then + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + else + -- RES b,(IX+d),Reg, undocumented + MCycles <= "011"; + XYbit_undoc <= '1'; + case to_integer(unsigned(MCycle)) is + when 1 | 7=> + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end if; + + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => null; + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + -- note B is decremented AFTER being put on the bus + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + --IncDec_16 <= "0010"; + IncDec_16 <= "0110"; + else + --IncDec_16 <= "1010"; + IncDec_16 <= "1110"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + -- note B is decremented BEFORE being put on the bus. + -- mikej fix for hl inc + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0110"; -- mikej + else + IncDec_16 <= "1110"; -- mikej + end if; + TStates <= "100"; -- MIKEJ should be 4 for IO cycle + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Nintendo - Gameboy_Mist/rtl/t80/T80_Pack.vhd b/Nintendo - Gameboy_Mist/rtl/t80/T80_Pack.vhd new file mode 100644 index 00000000..907db408 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/t80/T80_Pack.vhd @@ -0,0 +1,228 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + XY_State : in std_logic_vector(1 downto 0); + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + XYbit_undoc : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Nintendo - Gameboy_Mist/rtl/t80/T80_Reg.vhd b/Nintendo - Gameboy_Mist/rtl/t80/T80_Reg.vhd new file mode 100644 index 00000000..1c0f2638 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/t80/T80_Reg.vhd @@ -0,0 +1,114 @@ +-- **** +-- T80(b) core. In an effort to merge and maintain bug fixes .... +-- +-- +-- Ver 300 started tidyup +-- MikeJ March 2005 +-- Latest version from www.fpgaarcade.com (original www.opencores.org) +-- +-- **** +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Nintendo - Gameboy_Mist/rtl/timer.sv b/Nintendo - Gameboy_Mist/rtl/timer.sv new file mode 100644 index 00000000..23d5999c --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/timer.sv @@ -0,0 +1,103 @@ +// +// timer.v +// +// Gameboy for the MIST board https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module timer ( + input reset, + input clk, // 4 Mhz cpu clock + + output reg irq, + + // cpu register interface + input cpu_sel, + input [1:0] cpu_addr, + input cpu_wr, + input [7:0] cpu_di, + output [7:0] cpu_do +); + +// input: 4Mhz +// clk_div[0] = 2Mhz +// clk_div[1] = 1Mhz +// clk_div[2] = 524khz +// clk_div[3] = 262khz +// clk_div[4] = 131khz +// clk_div[5] = 65khz +// clk_div[6] = 32khz +// clk_div[7] = 16khz +// clk_div[8] = 8khz +// clk_div[9] = 4khz + +reg [9:0] clk_div; +always @(posedge clk) + clk_div <= clk_div + 10'd1; + +reg [7:0] div; +reg [7:0] tma; +reg [7:0] tima; +reg [2:0] tac; + +always @(posedge clk) begin + if(reset) begin + tima <= 8'h00; + tma <= 8'h00; + tac <= 8'h00; + irq <= 1'b0; + end else begin + irq <= 1'b0; + + if(clk_div[7:0] == 0) // 16kHz + div <= div + 8'd1; + + // timer enabled? + if(tac[2]) begin + // timer frequency + if(((tac[1:0] == 2'b00) && (clk_div[9:0] == 0)) || // 4 khz + ((tac[1:0] == 2'b01) && (clk_div[3:0] == 0)) || // 262 khz + ((tac[1:0] == 2'b10) && (clk_div[5:0] == 0)) || // 65 khz + ((tac[1:0] == 2'b11) && (clk_div[7:0] == 0))) begin // 16 khz + + if(tima != 8'hff) + tima <= tima + 8'd1; + else begin + irq <= 1'b1; // irq when timer overflows + tima <= tma; // reload timer + end + end + end + + if(cpu_sel && cpu_wr) begin + case(cpu_addr) + 2'b00: div <= 8'h00; // writing clears counter + 2'b01: tima <= cpu_di; + 2'b10: tma <= cpu_di; + 2'b11: tac <= cpu_di[2:0]; + endcase + end + end +end + +assign cpu_do = + (cpu_addr == 2'b00)?div: + (cpu_addr == 2'b01)?tima: + (cpu_addr == 2'b10)?tma: + {5'b00000, tac}; + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/video.sv b/Nintendo - Gameboy_Mist/rtl/video.sv new file mode 100644 index 00000000..7a84f8b0 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/video.sv @@ -0,0 +1,513 @@ +// +// video.v +// +// Gameboy for the MIST board https://github.com/mist-devel +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module video ( + input reset, + input clk, // 4 Mhz cpu clock + + // cpu register adn oam interface + input cpu_sel_oam, + input cpu_sel_reg, + input [7:0] cpu_addr, + input cpu_wr, + input [7:0] cpu_di, + output [7:0] cpu_do, + + // output to lcd + output lcd_on, + output lcd_clkena, + output [1:0] lcd_data, + output reg irq, + + // vram connection + output [1:0] mode, + output vram_rd, + output [12:0] vram_addr, + input [7:0] vram_data, + + // dma connection + output dma_rd, + output [15:0] dma_addr, + input [7:0] dma_data +); + +localparam STAGE2 = 9'd250; // oam + disp + pause +localparam OAM_LEN = 80; + +wire sprite_pixel_active; +wire [1:0] sprite_pixel_data; +wire sprite_pixel_cmap; +wire sprite_pixel_prio; + +wire [7:0] oam_do; +wire [3:0] sprite_index = h_cnt[7:4]-(OAM_LEN/16); // memory io starts at h_cnt == 16 +wire [10:0] sprite_addr; + +// "data strobe" for the two bytes each sprite line consists of +wire [1:0] sprite_dvalid = { + (h_cnt[3:0] == 4'hf) && !vblank && !hblank, + (h_cnt[3:0] == 4'h7) && !vblank && !hblank }; + +sprites sprites ( + .clk ( clk ), + .size16 ( lcdc_spr_siz ), + + .v_cnt ( v_cnt ), + .h_cnt ( h_cnt-STAGE2 ), // sprites are added in second stage + .sort ( h_cnt == 0 ), // start of oam phase + + .pixel_active ( sprite_pixel_active ), + .pixel_data ( sprite_pixel_data ), + .pixel_cmap ( sprite_pixel_cmap ), + .pixel_prio ( sprite_pixel_prio ), + + .index ( sprite_index ), + .addr ( sprite_addr ), + .dvalid ( sprite_dvalid), + .data ( vram_data ), + + .oam_wr ( oam_wr ), + .oam_addr ( oam_addr ), + .oam_di ( oam_di ), + .oam_do ( oam_do ) +); + +// give dma access to oam +wire [7:0] oam_addr = dma_active?dma_addr[7:0]:cpu_addr; +wire oam_wr = dma_active?(dma_cnt[1:0] == 2):(cpu_wr && cpu_sel_oam); +wire [7:0] oam_di = dma_active?dma_data:cpu_di; + + +assign lcd_on = lcdc_on; + +// $ff40 LCDC +wire lcdc_on = lcdc[7]; +wire lcdc_win_tile_map_sel = lcdc[6]; +wire lcdc_win_ena = lcdc[5]; +wire lcdc_tile_data_sel = lcdc[4]; +wire lcdc_bg_tile_map_sel = lcdc[3]; +wire lcdc_spr_siz = lcdc[2]; +wire lcdc_spr_ena = lcdc[1]; +wire lcdc_bg_ena = lcdc[0]; +reg [7:0] lcdc; + +// ff41 STAT +reg [7:0] stat; + +// ff42, ff43 background scroll registers +reg [7:0] scy; +reg [7:0] scy_r; // stable over entire image +reg [7:0] scx; +reg [7:0] scx_r; // stable over line + +// ff44 line counter +reg [7:0] ly; + +// ff45 line counter compare +wire lyc_match = (ly == lyc); +reg [7:0] lyc; + +reg [7:0] bgp; +reg [7:0] obp0; +reg [7:0] obp1; + +reg [7:0] wy; +reg [7:0] wy_r; // stable over entire image +reg [7:0] wx; +reg [7:0] wx_r; // stable over line + +// -------------------------------------------------------------------- +// ----------------------------- DMA engine --------------------------- +// -------------------------------------------------------------------- + +assign dma_addr = { dma, dma_cnt[9:2] }; +assign dma_rd = dma_active; + +reg dma_active; +reg [7:0] dma; +reg [9:0] dma_cnt; // dma runs 4*160 clock cycles = 160us @ 4MHz +always @(posedge clk) begin + if(reset) + dma_active <= 1'b0; + else begin + // writing the dma register engages the dma engine + if(cpu_sel_reg && cpu_wr && (cpu_addr[3:0] == 4'h6)) begin + dma_active <= 1'b1; + dma_cnt <= 10'd0; + end else if(dma_cnt != 160*4-1) + dma_cnt <= dma_cnt + 10'd1; + else + dma_active <= 1'b0; + end +end + +// -------------------------------------------------------------------- +// ------------------------------- IRQs ------------------------------- +// -------------------------------------------------------------------- + +always @(posedge clk) begin + irq <= 1'b0; + + // lyc=ly coincidence + if(stat[6] && (h_cnt == 0) && lyc_match) + irq <= 1'b1; + + // begin of oam phase + if(stat[5] && (h_cnt == 0)) + irq <= 1'b1; + + // begin of vblank + if(stat[4] && (h_cnt == 455) && (v_cnt == 143)) + irq <= 1'b1; + + // begin of hblank + if(stat[3] && (h_cnt == OAM_LEN + 160 + hextra)) + irq <= 1'b1; +end + +// -------------------------------------------------------------------- +// --------------------- CPU register interface ----------------------- +// -------------------------------------------------------------------- + +always @(posedge clk) begin + if(reset) begin + lcdc <= 8'h00; // screen must be off since dmg rom writes to vram + scy <= 8'h00; + scx <= 8'h00; + wy <= 8'h00; + wx <= 8'h00; + bgp <= 8'hfc; + obp0 <= 8'hff; + obp1 <= 8'hff; + end else begin + if(cpu_sel_reg && cpu_wr) begin + case(cpu_addr[3:0]) + 4'h0: lcdc <= cpu_di; + 4'h1: stat <= cpu_di; + 4'h2: scy <= cpu_di; + 4'h3: scx <= cpu_di; + // a write to 4 is supposed to reset the v_cnt + 4'h5: lyc <= cpu_di; + 4'h6: dma <= cpu_di; + 4'h7: bgp <= cpu_di; + 4'h8: obp0 <= cpu_di; + 4'h9: obp1 <= cpu_di; + 4'ha: wy <= cpu_di; + 4'hb: wx <= cpu_di; + endcase + end + end +end + +assign cpu_do = + cpu_sel_oam?oam_do: + (cpu_addr[3:0] == 4'h0)?lcdc: + (cpu_addr[3:0] == 4'h1)?{stat[7:3], lyc_match, mode}: + (cpu_addr[3:0] == 4'h2)?scy: + (cpu_addr[3:0] == 4'h3)?scx: + (cpu_addr[3:0] == 4'h4)?ly: + (cpu_addr[3:0] == 4'h5)?lyc: + (cpu_addr[3:0] == 4'h6)?dma: + (cpu_addr[3:0] == 4'h7)?bgp: + (cpu_addr[3:0] == 4'h8)?obp0: + (cpu_addr[3:0] == 4'h9)?obp1: + (cpu_addr[3:0] == 4'ha)?wy: + (cpu_addr[3:0] == 4'hb)?wx: + 8'hff; + +// -------------------------------------------------------------------- +// ----------------- second output stage: sprites --------------------- +// -------------------------------------------------------------------- + +assign lcd_data = stage2_data; +assign lcd_clkena = stage2_clkena; + +reg [1:0] stage2_data; +reg stage2_clkena; + +reg [1:0] stage2_buffer [159:0]; +reg [7:0] stage2_wptr; +reg [7:0] stage2_rptr; + +// apply bg palette +wire [1:0] stage2_bg_pix = (!lcdc_bg_ena && !window_ena)?2'b11: // background off? + (stage2_buffer[stage2_rptr] == 2'b00)?bgp[1:0]: + (stage2_buffer[stage2_rptr] == 2'b01)?bgp[3:2]: + (stage2_buffer[stage2_rptr] == 2'b10)?bgp[5:4]: + bgp[7:6]; + +// apply sprite palette +wire [7:0] obp = sprite_pixel_cmap?obp1:obp0; +wire [1:0] sprite_pix = + (sprite_pixel_data == 2'b00)?obp[1:0]: + (sprite_pixel_data == 2'b01)?obp[3:2]: + (sprite_pixel_data == 2'b10)?obp[5:4]: + obp[7:6]; + +// a sprite pixel is visible if +// - sprites are enabled +// - there's a sprite at the current position +// - the sprites prioroty bit is 0, or +// - the prites priority is 1 and the backrgound color is 00 + +wire sprite_pixel_visible = + sprite_pixel_active && lcdc_spr_ena && + ((!sprite_pixel_prio) || (stage2_buffer[stage2_rptr] == 2'b00)); + +always @(posedge clk) begin + if(h_cnt == 455) begin + stage2_wptr <= 8'h00; + stage2_rptr <= 8'h00; + end + + if(stage1_clkena) begin + stage2_buffer[stage2_wptr] <= stage1_data; + stage2_wptr <= stage2_wptr + 8'd1; + end + + stage2_clkena = !vblank && stage2; + if(stage2) begin + // mix sprites and bg + if(sprite_pixel_visible) stage2_data <= sprite_pix; + else stage2_data <= stage2_bg_pix; + + stage2_rptr <= stage2_rptr + 8'd1; + end +end + +// -------------------------------------------------------------------- +// --------------- first output stage: bg and window ------------------ +// -------------------------------------------------------------------- + +reg window_ena; + +// output shift registers for both video data bits +reg [7:0] tile_shift_0; +reg [7:0] tile_shift_1; + +reg [7:0] bg_tile; +reg [7:0] bg_tile_data0; +reg [7:0] bg_tile_data1; + +wire stage1_clkena = !vblank && hdvalid; +wire [1:0] stage1_data = { tile_shift_1[7], tile_shift_0[7] }; + +// read data half a clock cycle after ram has been selected +always @(posedge clk) begin + + // every memory access is two pixel cycles + if(h_cnt[0]) begin + if(bg_tile_map_rd) bg_tile <= vram_data; + if(bg_tile_data0_rd) bg_tile_data0 <= vram_data; + if(bg_tile_data1_rd) bg_tile_data1 <= vram_data; + // sprite data is evaluated inside the sprite engine + end + + // shift bg/window pixels out + if(bg_tile_obj_rd && h_cnt[0]) begin + tile_shift_0 <= bg_tile_data0; + tile_shift_1 <= bg_tile_data1; + end else begin + tile_shift_0 <= { tile_shift_0[6:0], 1'b0 }; + tile_shift_1 <= { tile_shift_1[6:0], 1'b0 }; + end +end + +assign vram_rd = lcdc_on && (bg_tile_map_rd || bg_tile_data0_rd || + bg_tile_data1_rd || bg_tile_obj_rd); + +wire bg_tile_a12 = !lcdc_tile_data_sel?(~bg_tile[7]):1'b0; + +wire tile_map_sel = window_ena?lcdc_win_tile_map_sel:lcdc_bg_tile_map_sel; + +assign vram_addr = + bg_tile_map_rd?{2'b11, tile_map_sel, bg_tile_map_addr}: + bg_tile_data0_rd?{bg_tile_a12, bg_tile, tile_line, 1'b0}: + bg_tile_data1_rd?{bg_tile_a12, bg_tile, tile_line, 1'b1}: + {1'b0, sprite_addr, h_cnt[3]}; + +reg [9:0] bg_tile_map_addr; + +wire vblank = (v_cnt >= 144); + +// x scroll & 7 needs one more memory read per line +reg [1:0] hextra_tiles; +wire [7:0] hextra = { 3'b000, hextra_tiles, 3'b000 }; +wire hblank = ((h_cnt < OAM_LEN) || (h_cnt >= 160+OAM_LEN+hextra)); +wire oam = (h_cnt < OAM_LEN); // 80 clocks oam +wire stage2 = ((h_cnt >= STAGE2) && (h_cnt < STAGE2+160)); // output out of stage2 + +// first valid pixels are delivered 8 clocks after end of hblank +// wire hdvalid = ((h_cnt >= OAM_LEN+8) && (h_cnt < 160+OAM_LEN+8)); +wire hdvalid = de; + +reg de; +reg [7:0] skip; +reg [7:0] pcnt; + +localparam STATE_HBLANK = 0; +localparam STATE_OAM = 1; +localparam STATE_ACTIVE = 2; + +always @(negedge clk) begin + if(h_cnt == 455) begin + // end of line + + de <= 1'b0; + hextra_tiles <= 2'd0; + pcnt <= 8'd0; + skip <= 8'd0; + end else if(h_cnt == OAM_LEN) begin + // start of line + + // skip entire oam time plus time until first data is delivered plus + // time to skip the pixels according to the horizontal scroll position + // (or the window start if line starts with window) + if(lcdc_win_ena && (v_cnt >= wy_r) && (wx_r < 8)) + skip <= 8'd8 + (8'd7 - wx_r) - 8'd1; + else + skip <= 8'd8 + scx_r[2:0] - 8'd1; + + // calculate how many extra tiles will have to be read in this line + if(lcdc_win_ena && (v_cnt >= wy_r) && (wx_r < 168)) begin + // window needs at least one extra cycle, two if bg scroll position or + // window are not 8 pixel aligned + if((wx_r[2:0] != 3'd7) || (scx_r[2:0] != 3'd0)) begin + if(wx_r[2:0] > ~scx_r[2:0]) + hextra_tiles <= 2'd3; + else + hextra_tiles <= 2'd2; + end else + hextra_tiles <= 2'd1; + end else + if(scx_r[2:0] != 3'd0) + hextra_tiles <= 2'd1; + end else begin + if(win_start) begin + // if window starts skip until end of current cycle and skip + // pixels until new window data is ready + skip <= { 5'b00000 ,~h_cnt[2:0] } + 8'd8; + de <= 1'b0; + end + + if(skip) skip <= skip - 8'd1; + + // (re-)enable display at the end of the wait phase + if(skip == 1) + de <= 1'b1; + + if(de) begin + if(pcnt != 160) + pcnt <= pcnt + 8'd1; + else + de <= 1'b0; + end + end +end + +// cycle through the B01s states +wire bg_tile_map_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b00); +wire bg_tile_data0_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b01); +wire bg_tile_data1_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b10); +wire bg_tile_obj_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b11); + +// Mode 00: h-blank +// Mode 01: v-blank +// Mode 10: oam +// Mode 11: oam and vram +assign mode = + vblank?2'b01: + oam?2'b10: + hblank?2'b00: + 2'b11; + +reg [8:0] h_cnt; // max 455 +reg [7:0] v_cnt; // max 153 + +// line inside the background/window currently being drawn +wire [7:0] win_line = v_cnt - wy_r; +wire [7:0] bg_line = v_cnt + scy_r; +wire [2:0] tile_line = window_ena?win_line[2:0]:bg_line[2:0]; + +wire win_start = lcdc_win_ena && (v_cnt >= wy_r) && de && (wx_r >= 7) && (pcnt == wx_r-8); + +// each memory access takes two cycles +always @(negedge clk) begin + // this ly change h_cnt is wrong!!! + if(h_cnt == 0) + ly <= (v_cnt >= 153)?(v_cnt-8'd153):(v_cnt+8'd1); + + if(h_cnt != 455) begin + h_cnt <= h_cnt + 9'd1; + + // make sure sginals don't change during the line + // latch at latest possible moment (one clock before display starts) + if(h_cnt == OAM_LEN-2) begin + scx_r <= scx; + wx_r <= wx; + scy_r <= scy; + end + + // increment address at the end of each 8-pixel-cycle. But don't + // increment while waiting for current cycle to end due to window start + if(!hblank && h_cnt[2:0] == 3'b111 && (skip <= 8)) + bg_tile_map_addr[4:0] <= bg_tile_map_addr[4:0] + 10'd1; + + // begin of line + if(h_cnt == OAM_LEN-1) begin + // set tile map address for this line, assume there is no window + bg_tile_map_addr[9:5] <= bg_line[7:3]; + bg_tile_map_addr[4:0] <= scx_r[7:3]; + + // special case wx < 8: line starts with window, no background + // visible at all + if(lcdc_win_ena && (v_cnt >= wy_r) && (wx_r < 8)) begin + window_ena <= 1'b1; + bg_tile_map_addr[9:5] <= win_line[7:3]; + bg_tile_map_addr[4:0] <= 5'd0; // window always start with its very left + end + end + + // check if the window starts here + if(win_start) begin + window_ena <= 1'b1; + bg_tile_map_addr[9:5] <= win_line[7:3]; + bg_tile_map_addr[4:0] <= 5'd0; // window always start with its very left + end + end else begin + window_ena <= 1'b0; // next line starts with background + + // end of line reached + h_cnt <= 9'd0; + + if(v_cnt != 153) + v_cnt <= v_cnt + 8'd1; + else begin + // start of new image + v_cnt <= 8'd0; + + // make sure sginals don't change during the image + wy_r <= wy; + end + end +end + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/video_mixer.sv b/Nintendo - Gameboy_Mist/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Nintendo - Gameboy_Mist/rtl/vram.sv b/Nintendo - Gameboy_Mist/rtl/vram.sv new file mode 100644 index 00000000..1fe1f976 --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/vram.sv @@ -0,0 +1,172 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: vram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module vram ( + address, + clock, + data, + wren, + q); + + input [12:0] address; + input clock; + input [7:0] data; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8192, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 13, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Nintendo - Gameboy_Mist/rtl/zpram.sv b/Nintendo - Gameboy_Mist/rtl/zpram.sv new file mode 100644 index 00000000..5714f7bf --- /dev/null +++ b/Nintendo - Gameboy_Mist/rtl/zpram.sv @@ -0,0 +1,172 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: zpram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module zpram ( + address, + clock, + data, + wren, + q); + + input [7:0] address; + input clock; + input [7:0] data; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 8, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "8" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zpram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zpram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf